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34 : OutgoingValueHandler(MIRBuilder,
MRI), MIB(MIB),
35 DL(MIRBuilder.getMF().getDataLayout()),
41 Register ExtReg = extendRegister(ValVReg, VA);
42 MIRBuilder.buildCopy(PhysReg, ExtReg);
48 Register ExtReg = extendRegister(ValVReg, VA);
52 MIRBuilder.buildStore(ExtReg,
Addr, *MMO);
60 Register StackReg = STI.getRegisterInfo()->getStackRegister();
61 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0);
62 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
65 return AddrReg.getReg(0);
84 auto &
DL =
F.getParent()->getDataLayout();
93 MIRBuilder,
F.getCallingConv(),
106 const auto &
DL =
F.getParent()->getDataLayout();
107 auto &TLI = *getTLI<M68kTargetLowering>();
111 for (
const auto &
Arg :
F.args()) {
119 TLI.getCCAssignFn(
F.getCallingConv(),
false,
F.isVarArg());
123 MIRBuilder,
F.getCallingConv(),
127 void M68kIncomingValueHandler::assignValueToReg(
Register ValVReg,
132 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
135 void M68kIncomingValueHandler::assignValueToAddress(
Register ValVReg,
151 const bool IsImmutable = !Flags.
isByVal();
152 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
163 void CallReturnHandler::assignValueToReg(
Register ValVReg,
Register PhysReg,
174 auto &
DL =
F.getParent()->getDataLayout();
181 for (
auto &OrigArg :
Info.OrigArgs)
185 if (!
Info.OrigRet.Ty->isVoidTy())
188 unsigned AdjStackDown =
TII.getCallFrameSetupOpcode();
189 auto CallSeqStart = MIRBuilder.
buildInstr(AdjStackDown);
192 :
Info.Callee.isReg() ? M68k::CALLj
206 if (
Info.Callee.isReg())
213 if (!
Info.OrigRet.Ty->isVoidTy()) {
224 CallSeqStart.addImm(Assigner.
StackOffset).addImm(0);
226 unsigned AdjStackUp =
TII.getCallFrameDestroyOpcode();
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
M68kOutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB)
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
const M68kSubtarget & STI
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
A parsed version of the target data layout string in and methods for querying it.
Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags) override
Materialize a VReg containing the address of the specified stack-based object.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const RegisterBankInfo * getRegBankInfo() const override
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
const M68kRegisterInfo * getRegisterInfo() const override
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
unsigned const TargetRegisterInfo * TRI
bool empty() const
empty - Check if the array is empty.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
bool enableBigEndian() const override
For targets which want to use big-endian can enable it with enableBigEndian() hook.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
const M68kInstrInfo * getInstrInfo() const override
const HexagonInstrInfo * TII
MachineFunction & getMF()
Getter for the function we currently build.
Analysis containing CSE Info
Register getReg(unsigned Idx) const
Get the register for the operand index.
bool isPositionIndependent() const
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Helper class to build MachineInstr.
This class contains a discriminated union of information about pointers in memory operands,...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Type * getType() const
All values are typed, get the type of this value.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
const TargetMachine & getTargetMachine() const
Function & getFunction()
Return the LLVM function that this machine code represents.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
uint64_t StackOffset
Stack offset for next argument.
MachineIRBuilder & MIRBuilder
@ MOStore
The memory access writes data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
M68kCallLowering(const M68kTargetLowering &TLI)
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Align max(MaybeAlign Lhs, Align Rhs)
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
LLVM Value Representation.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA) override
The specified value has been assigned to a stack location.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const