LLVM 17.0.0git
M68kCallLowering.cpp
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1//===-- M68kCallLowering.cpp - Call lowering --------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12//
13//===----------------------------------------------------------------------===//
14
15#include "M68kCallLowering.h"
16#include "M68kISelLowering.h"
17#include "M68kInstrInfo.h"
18#include "M68kSubtarget.h"
19#include "M68kTargetMachine.h"
25
26using namespace llvm;
27
29 : CallLowering(&TLI) {}
30
34 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
35 DL(MIRBuilder.getMF().getDataLayout()),
36 STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}
37
38 void assignValueToReg(Register ValVReg, Register PhysReg,
39 CCValAssign VA) override {
40 MIB.addUse(PhysReg, RegState::Implicit);
41 Register ExtReg = extendRegister(ValVReg, VA);
42 MIRBuilder.buildCopy(PhysReg, ExtReg);
43 }
44
46 MachinePointerInfo &MPO, CCValAssign &VA) override {
47 MachineFunction &MF = MIRBuilder.getMF();
48 Register ExtReg = extendRegister(ValVReg, VA);
49
50 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
51 inferAlignFromPtrInfo(MF, MPO));
52 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
53 }
54
57 ISD::ArgFlagsTy Flags) override {
58 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
59 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
60 Register StackReg = STI.getRegisterInfo()->getStackRegister();
61 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0);
62 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
64 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
65 return AddrReg.getReg(0);
66 }
68 const DataLayout &DL;
70};
72 const Value *Val, ArrayRef<Register> VRegs,
74 Register SwiftErrorVReg) const {
75
76 auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS);
77 bool Success = true;
78 MachineFunction &MF = MIRBuilder.getMF();
79 const Function &F = MF.getFunction();
81 const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
82 CCAssignFn *AssignFn =
83 TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
84 auto &DL = F.getParent()->getDataLayout();
85 if (!VRegs.empty()) {
87 ArgInfo OrigArg{VRegs, Val->getType(), 0};
89 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
90 OutgoingValueAssigner ArgAssigner(AssignFn);
91 M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
92 Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
93 MIRBuilder, F.getCallingConv(),
94 F.isVarArg());
95 }
96 MIRBuilder.insertInstr(MIB);
97 return Success;
98}
99
101 const Function &F,
103 FunctionLoweringInfo &FLI) const {
104 MachineFunction &MF = MIRBuilder.getMF();
106 const auto &DL = F.getParent()->getDataLayout();
107 auto &TLI = *getTLI<M68kTargetLowering>();
108
109 SmallVector<ArgInfo, 8> SplitArgs;
110 unsigned I = 0;
111 for (const auto &Arg : F.args()) {
112 ArgInfo OrigArg{VRegs[I], Arg.getType(), I};
114 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
115 ++I;
116 }
117
118 CCAssignFn *AssignFn =
119 TLI.getCCAssignFn(F.getCallingConv(), false, F.isVarArg());
120 IncomingValueAssigner ArgAssigner(AssignFn);
121 FormalArgHandler ArgHandler(MIRBuilder, MRI);
122 return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
123 MIRBuilder, F.getCallingConv(),
124 F.isVarArg());
125}
126
127void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
128 Register PhysReg,
129 CCValAssign VA) {
130 MIRBuilder.getMRI()->addLiveIn(PhysReg);
131 MIRBuilder.getMBB().addLiveIn(PhysReg);
132 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
133}
134
135void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
137 LLT MemTy,
139 CCValAssign &VA) {
141 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
142 inferAlignFromPtrInfo(MF, MPO));
143 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
144}
145
146Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
147 int64_t Offset,
149 ISD::ArgFlagsTy Flags) {
150 auto &MFI = MIRBuilder.getMF().getFrameInfo();
151 const bool IsImmutable = !Flags.isByVal();
152 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
154
155 // Build Frame Index
159 StackUsed = std::max(StackUsed, Size + Offset);
160 return AddrReg.getReg(0);
161}
162
163void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
164 CCValAssign VA) {
165 MIB.addDef(PhysReg, RegState::Implicit);
166 MIRBuilder.buildCopy(ValVReg, PhysReg);
167}
168
170 CallLoweringInfo &Info) const {
171 MachineFunction &MF = MIRBuilder.getMF();
172 Function &F = MF.getFunction();
174 auto &DL = F.getParent()->getDataLayout();
175 const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
176 const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
177 const TargetInstrInfo &TII = *STI.getInstrInfo();
178 const M68kRegisterInfo *TRI = STI.getRegisterInfo();
179
181 for (auto &OrigArg : Info.OrigArgs)
182 splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
183
185 if (!Info.OrigRet.Ty->isVoidTy())
186 splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
187
188 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
189 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
190
191 unsigned Opc = TLI.getTargetMachine().isPositionIndependent() ? M68k::CALLq
192 : Info.Callee.isReg() ? M68k::CALLj
193 : M68k::CALLb;
194
195 auto MIB = MIRBuilder.buildInstrNoInsert(Opc)
196 .add(Info.Callee)
197 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
198
199 CCAssignFn *AssignFn = TLI.getCCAssignFn(Info.CallConv, false, Info.IsVarArg);
200 OutgoingValueAssigner Assigner(AssignFn);
201 M68kOutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
202 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
203 Info.CallConv, Info.IsVarArg))
204 return false;
205
206 if (Info.Callee.isReg())
208 *STI.getRegBankInfo(), *MIB, MIB->getDesc(),
209 Info.Callee, 0);
210
211 MIRBuilder.insertInstr(MIB);
212
213 if (!Info.OrigRet.Ty->isVoidTy()) {
214 CCAssignFn *RetAssignFn =
215 TLI.getCCAssignFn(Info.CallConv, true, Info.IsVarArg);
216
217 OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn);
218 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
219 if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
220 Info.CallConv, Info.IsVarArg))
221 return false;
222 }
223
224 CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
225
226 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
227 MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackOffset).addImm(0);
228
229 return true;
230}
231
232bool M68kCallLowering::enableBigEndian() const { return true; }
unsigned const MachineRegisterInfo * MRI
#define Success
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file describes how to lower LLVM calls to machine code calls.
uint64_t Addr
uint64_t Size
const HexagonInstrInfo * TII
This file implements the lowering of LLVM calls to machine code calls for GlobalISel.
This file defines the interfaces that M68k uses to lower LLVM code into a selection DAG.
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file declares the M68k specific subclass of TargetMachine.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static const unsigned FramePtr
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
CCValAssign - Represent assignment of one arg/retval to a location.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:413
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
M68kCallLowering(const M68kTargetLowering &TLI)
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool enableBigEndian() const override
For targets which want to use big-endian can enable it with enableBigEndian() hook.
const RegisterBankInfo * getRegBankInfo() const override
const M68kInstrInfo * getInstrInfo() const override
const M68kRegisterInfo * getRegisterInfo() const override
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
TargetInstrInfo - Interface to description of machine instruction set.
const TargetMachine & getTargetMachine() const
bool isPositionIndependent() const
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:53
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:712
MachineInstrBuilder MIB
Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags) override
Materialize a VReg containing the address of the specified stack-based object.
M68kOutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB)
const DataLayout & DL
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA) override
The specified value has been assigned to a stack location.
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
const M68kSubtarget & STI
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:333
uint64_t StackOffset
Stack offset for next argument.
Definition: CallLowering.h:204
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.