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M68kISelLowering.h
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1 //===-- M68kISelLowering.h - M68k DAG Lowering Interface ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that M68k uses to lower LLVM code into a
11 /// selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
16 #define LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
17 
18 #include "M68k.h"
19 
23 #include "llvm/IR/Function.h"
24 
25 #include <deque>
26 
27 namespace llvm {
28 namespace M68kISD {
29 
30 /// M68k Specific DAG nodes
31 enum NodeType {
32  /// Start the numbering from where ISD NodeType finishes.
34 
36  RET,
39 
40  /// M68k compare and logical compare instructions. Subtracts the source
41  /// operand from the destination data register and sets the condition
42  /// codes according to the result. Immediate always goes first.
43  CMP,
44 
45  /// M68k bit-test instructions.
46  BT,
47 
48  /// M68k Select
50 
51  /// M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
52  /// operand, usually produced by a CMP instruction.
54 
55  // Same as SETCC except it's materialized with a subx and the value is all
56  // one's or all zero's.
57  SETCC_CARRY, // R = carry_bit ? ~0 : 0
58 
59  /// M68k conditional moves. Operand 0 and operand 1 are the two values
60  /// to select from. Operand 2 is the condition code, and operand 3 is the
61  /// flag operand produced by a CMP or TEST instruction. It also writes a
62  /// flag result.
64 
65  /// M68k conditional branches. Operand 0 is the chain operand, operand 1
66  /// is the block to branch if condition is true, operand 2 is the
67  /// condition code, and operand 3 is the flag operand produced by a CMP
68  /// or TEST instruction.
70 
71  // Arithmetic operations with CCR results.
72  ADD,
73  SUB,
78  OR,
79  XOR,
80  AND,
81 
82  // GlobalBaseReg,
84 
85  /// A wrapper node for TargetConstantPool,
86  /// TargetExternalSymbol, and TargetGlobalAddress.
88 
89  /// Special wrapper used under M68k PIC mode for PC
90  /// relative displacements.
92 
93  // For allocating variable amounts of stack space when using
94  // segmented stacks. Check if the current stacklet has enough space, and
95  // falls back to heap allocation if not.
97 };
98 } // namespace M68kISD
99 
100 /// Define some predicates that are used for node matching.
101 namespace M68k {
102 
103 /// Determines whether the callee is required to pop its
104 /// own arguments. Callee pop is necessary to support tail calls.
105 bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO);
106 
107 } // end namespace M68k
108 
109 //===--------------------------------------------------------------------===//
110 // TargetLowering Implementation
111 //===--------------------------------------------------------------------===//
112 
113 class M68kMachineFunctionInfo;
114 class M68kSubtarget;
115 
117  const M68kSubtarget &Subtarget;
118  const M68kTargetMachine &TM;
119 
120 public:
121  explicit M68kTargetLowering(const M68kTargetMachine &TM,
122  const M68kSubtarget &STI);
123 
124  static const M68kTargetLowering *create(const M68kTargetMachine &TM,
125  const M68kSubtarget &STI);
126 
127  const char *getTargetNodeName(unsigned Opcode) const override;
128 
129  /// Return the value type to use for ISD::SETCC.
131  EVT VT) const override;
132 
133  /// EVT is not used in-tree, but is used by out-of-tree target.
134  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
135 
136  /// Provide custom lowering hooks for some operations.
137  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
138 
139  /// Return the entry encoding for a jump table in the current function.
140  /// The returned value is a member of the MachineJumpTableInfo::JTEntryKind
141  /// enum.
142  unsigned getJumpTableEncoding() const override;
143 
145  const MachineBasicBlock *MBB,
146  unsigned uid,
147  MCContext &Ctx) const override;
148 
149  /// Returns relocation base for the given PIC jumptable.
151  SelectionDAG &DAG) const override;
152 
153  /// This returns the relocation base for the given PIC jumptable,
154  /// the same as getPICJumpTableRelocBase, but as an MCExpr.
156  unsigned JTI,
157  MCContext &Ctx) const override;
158 
159  ConstraintType getConstraintType(StringRef ConstraintStr) const override;
160 
161  std::pair<unsigned, const TargetRegisterClass *>
163  StringRef Constraint, MVT VT) const override;
164 
165  // Lower operand with C_Immediate and C_Other constraint type
166  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
167  std::vector<SDValue> &Ops,
168  SelectionDAG &DAG) const override;
169 
172  MachineBasicBlock *MBB) const override;
173 
174  CCAssignFn *getCCAssignFn(CallingConv::ID CC, bool Return,
175  bool IsVarArg) const;
176 
177 private:
178  unsigned GetAlignedArgumentStackSize(unsigned StackSize,
179  SelectionDAG &DAG) const;
180 
181  SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
182 
183  /// Emit a load of return address if tail call
184  /// optimization is performed and it is required.
185  SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
186  SDValue Chain, bool IsTailCall, int FPDiff,
187  const SDLoc &DL) const;
188 
189  /// Emit a store of the return address if tail call
190  /// optimization is performed and it is required (FPDiff!=0).
191  SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
192  SDValue Chain, SDValue RetAddrFrIdx,
193  EVT PtrVT, unsigned SlotSize, int FPDiff,
194  const SDLoc &DL) const;
195 
196  SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
197  const SmallVectorImpl<ISD::InputArg> &ArgInfo,
198  const SDLoc &DL, SelectionDAG &DAG,
199  const CCValAssign &VA, MachineFrameInfo &MFI,
200  unsigned ArgIdx) const;
201 
202  SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
203  const SDLoc &DL, SelectionDAG &DAG,
204  const CCValAssign &VA, ISD::ArgFlagsTy Flags) const;
205 
206  SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
207  SDValue LowerToBT(SDValue And, ISD::CondCode CC, const SDLoc &DL,
208  SelectionDAG &DAG) const;
209  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
210  SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
211  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
212  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
213  SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) const;
214  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
215  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
216  SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
217  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
218  SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
219  int64_t Offset, SelectionDAG &DAG) const;
220  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
221  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
222  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
223 
224  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
225  CallingConv::ID CallConv, bool IsVarArg,
227  const SDLoc &DL, SelectionDAG &DAG,
228  SmallVectorImpl<SDValue> &InVals) const;
229 
230  /// LowerFormalArguments - transform physical registers into virtual
231  /// registers and generate load operations for arguments places on the stack.
232  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,
233  bool IsVarArg,
235  const SDLoc &DL, SelectionDAG &DAG,
236  SmallVectorImpl<SDValue> &InVals) const override;
237 
238  SDValue LowerCall(CallLoweringInfo &CLI,
239  SmallVectorImpl<SDValue> &InVals) const override;
240 
241  /// Lower the result values of a call into the
242  /// appropriate copies out of appropriate physical registers.
243  SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
245  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
246  SelectionDAG &DAG) const override;
247 
248  bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
249  SDValue C) const override;
250 
251  MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
252  MachineBasicBlock *MBB) const;
253  MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
254  MachineBasicBlock *BB) const;
255 
256  /// Emit nodes that will be selected as "test Op0,Op0", or something
257  /// equivalent, for use with the given M68k condition code.
258  SDValue EmitTest(SDValue Op0, unsigned M68kCC, const SDLoc &dl,
259  SelectionDAG &DAG) const;
260 
261  /// Emit nodes that will be selected as "cmp Op0,Op1", or something
262  /// equivalent, for use with the given M68k condition code.
263  SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC, const SDLoc &dl,
264  SelectionDAG &DAG) const;
265 
266  /// Check whether the call is eligible for tail call optimization. Targets
267  /// that want to do tail call optimization should implement this function.
268  bool IsEligibleForTailCallOptimization(
269  SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
270  bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
272  const SmallVectorImpl<SDValue> &OutVals,
273  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
274 
275  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
276 };
277 } // namespace llvm
278 
279 #endif // M68kISELLOWERING_H
llvm::M68kTargetLowering::getCCAssignFn
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: M68kISelLowering.cpp:3419
llvm::M68kTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: M68kISelLowering.cpp:2846
llvm::M68kISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: M68kISelLowering.h:87
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::M68kTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: M68kISelLowering.cpp:2672
llvm::M68kISD::SUBX
@ SUBX
Definition: M68kISelLowering.h:75
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::M68kISD::BRCOND
@ BRCOND
M68k conditional branches.
Definition: M68kISelLowering.h:69
llvm::M68kTargetMachine
Definition: M68kTargetMachine.h:29
llvm::M68kISD::SETCC
@ SETCC
M68k SetCC.
Definition: M68kISelLowering.h:53
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4163
llvm::M68kTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: M68kISelLowering.cpp:3157
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::M68kISD::SELECT
@ SELECT
M68k Select.
Definition: M68kISelLowering.h:49
llvm::M68kISD::ADD
@ ADD
Definition: M68kISelLowering.h:72
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::M68kISD::CALL
@ CALL
Definition: M68kISelLowering.h:35
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::M68k::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: M68kISelLowering.cpp:2884
llvm::M68kTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: M68kISelLowering.cpp:2668
llvm::M68kTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: M68kISelLowering.cpp:2690
M68k.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
TargetLowering.h
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:59
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::M68kISD::AND
@ AND
Definition: M68kISelLowering.h:80
llvm::M68kTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: M68kISelLowering.cpp:2679
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3195
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3550
llvm::M68kISD::FIRST_NUMBER
@ FIRST_NUMBER
Start the numbering from where ISD NodeType finishes.
Definition: M68kISelLowering.h:33
llvm::M68kTargetLowering::create
static const M68kTargetLowering * create(const M68kTargetMachine &TM, const M68kSubtarget &STI)
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::M68kISD::TC_RETURN
@ TC_RETURN
Definition: M68kISelLowering.h:38
llvm::M68kTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: M68kISelLowering.cpp:2730
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::M68kTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: M68kISelLowering.cpp:1318
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::M68kISD::XOR
@ XOR
Definition: M68kISelLowering.h:79
llvm::M68kISD::CMOV
@ CMOV
M68k conditional moves.
Definition: M68kISelLowering.h:63
llvm::M68kISD::SUB
@ SUB
Definition: M68kISelLowering.h:73
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::M68kISD::SMUL
@ SMUL
Definition: M68kISelLowering.h:76
llvm::M68kISD::TAIL_CALL
@ TAIL_CALL
Definition: M68kISelLowering.h:37
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3753
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::M68kISD::SETCC_CARRY
@ SETCC_CARRY
Definition: M68kISelLowering.h:57
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::M68kISD::ADDX
@ ADDX
Definition: M68kISelLowering.h:74
llvm::M68kISD::RET
@ RET
Definition: M68kISelLowering.h:36
llvm::M68kTargetLowering::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: M68kISelLowering.cpp:168
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1249
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::M68kISD::WrapperPC
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
Definition: M68kISelLowering.h:91
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
CallingConvLower.h
llvm::M68kTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: M68kISelLowering.cpp:3364
llvm::M68kTargetLowering
Definition: M68kISelLowering.h:116
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
Function.h
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::M68kISD::CMP
@ CMP
M68k compare and logical compare instructions.
Definition: M68kISelLowering.h:43
llvm::M68kTargetLowering::M68kTargetLowering
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
Definition: M68kISelLowering.cpp:46
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::M68kISD::OR
@ OR
Definition: M68kISelLowering.h:78
N
#define N
llvm::M68kTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: M68kISelLowering.cpp:162
llvm::M68kTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
Definition: M68kISelLowering.cpp:2696
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::M68kISD::BT
@ BT
M68k bit-test instructions.
Definition: M68kISelLowering.h:46
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::M68kISD::SEG_ALLOCA
@ SEG_ALLOCA
Definition: M68kISelLowering.h:96
llvm::M68kISD::NodeType
NodeType
M68k Specific DAG nodes.
Definition: M68kISelLowering.h:31
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::M68kISD::UMUL
@ UMUL
Definition: M68kISelLowering.h:77