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M68kISelLowering.h
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1//===-- M68kISelLowering.h - M68k DAG Lowering Interface --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the interfaces that M68k uses to lower LLVM code into a
11/// selection DAG.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
16#define LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
17
18#include "M68k.h"
19
23#include "llvm/IR/Function.h"
24
25#include <deque>
26
27namespace llvm {
28namespace M68kISD {
29
30/// M68k Specific DAG nodes
32 /// Start the numbering from where ISD NodeType finishes.
34
39
40 /// M68k compare and logical compare instructions. Subtracts the source
41 /// operand from the destination data register and sets the condition
42 /// codes according to the result. Immediate always goes first.
44
45 /// M68k bit-test instructions.
47
48 /// M68k Select
50
51 /// M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
52 /// operand, usually produced by a CMP instruction.
54
55 // Same as SETCC except it's materialized with a subx and the value is all
56 // one's or all zero's.
57 SETCC_CARRY, // R = carry_bit ? ~0 : 0
58
59 /// M68k conditional moves. Operand 0 and operand 1 are the two values
60 /// to select from. Operand 2 is the condition code, and operand 3 is the
61 /// flag operand produced by a CMP or TEST instruction. It also writes a
62 /// flag result.
64
65 /// M68k conditional branches. Operand 0 is the chain operand, operand 1
66 /// is the block to branch if condition is true, operand 2 is the
67 /// condition code, and operand 3 is the flag operand produced by a CMP
68 /// or TEST instruction.
70
71 // Arithmetic operations with CCR results.
81
82 // GlobalBaseReg,
84
85 /// A wrapper node for TargetConstantPool,
86 /// TargetExternalSymbol, and TargetGlobalAddress.
88
89 /// Special wrapper used under M68k PIC mode for PC
90 /// relative displacements.
92
93 // For allocating variable amounts of stack space when using
94 // segmented stacks. Check if the current stacklet has enough space, and
95 // falls back to heap allocation if not.
97};
98} // namespace M68kISD
99
100/// Define some predicates that are used for node matching.
101namespace M68k {
102
103/// Determines whether the callee is required to pop its
104/// own arguments. Callee pop is necessary to support tail calls.
105bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO);
106
107} // end namespace M68k
108
109//===--------------------------------------------------------------------===//
110// TargetLowering Implementation
111//===--------------------------------------------------------------------===//
112
113class M68kMachineFunctionInfo;
114class M68kSubtarget;
115
117 const M68kSubtarget &Subtarget;
118 const M68kTargetMachine &TM;
119
120public:
122 const M68kSubtarget &STI);
123
125 const M68kSubtarget &STI);
126
127 const char *getTargetNodeName(unsigned Opcode) const override;
128
129 /// Return the value type to use for ISD::SETCC.
131 EVT VT) const override;
132
133 /// EVT is not used in-tree, but is used by out-of-tree target.
134 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
135
136 /// Provide custom lowering hooks for some operations.
137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
138
139 /// Return the entry encoding for a jump table in the current function.
140 /// The returned value is a member of the MachineJumpTableInfo::JTEntryKind
141 /// enum.
142 unsigned getJumpTableEncoding() const override;
143
145 const MachineBasicBlock *MBB,
146 unsigned uid,
147 MCContext &Ctx) const override;
148
149 /// Returns relocation base for the given PIC jumptable.
151 SelectionDAG &DAG) const override;
152
153 /// This returns the relocation base for the given PIC jumptable,
154 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
156 unsigned JTI,
157 MCContext &Ctx) const override;
158
159 ConstraintType getConstraintType(StringRef ConstraintStr) const override;
160
161 std::pair<unsigned, const TargetRegisterClass *>
163 StringRef Constraint, MVT VT) const override;
164
165 // Lower operand with C_Immediate and C_Other constraint type
167 std::vector<SDValue> &Ops,
168 SelectionDAG &DAG) const override;
169
172 MachineBasicBlock *MBB) const override;
173
175 bool IsVarArg) const;
176
178 shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;
179
180 /// If a physical register, this returns the register that receives the
181 /// exception address on entry to an EH pad.
183 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
184
185 /// If a physical register, this returns the register that receives the
186 /// exception typeid on entry to a landing pad.
188 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
189
191 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
192
193private:
194 unsigned GetAlignedArgumentStackSize(unsigned StackSize,
195 SelectionDAG &DAG) const;
196
197 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override {
198 // In many cases, `GA` doesn't give the correct offset to fold. It's
199 // hard to know if the real offset actually fits into the displacement
200 // of the perspective addressing mode.
201 // Thus, we disable offset folding altogether and leave that to ISel
202 // patterns.
203 return false;
204 }
205
206 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
207
208 /// Emit a load of return address if tail call
209 /// optimization is performed and it is required.
210 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
211 SDValue Chain, bool IsTailCall, int FPDiff,
212 const SDLoc &DL) const;
213
214 /// Emit a store of the return address if tail call
215 /// optimization is performed and it is required (FPDiff!=0).
216 SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
217 SDValue Chain, SDValue RetAddrFrIdx,
218 EVT PtrVT, unsigned SlotSize, int FPDiff,
219 const SDLoc &DL) const;
220
221 SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
223 const SDLoc &DL, SelectionDAG &DAG,
224 const CCValAssign &VA, MachineFrameInfo &MFI,
225 unsigned ArgIdx) const;
226
227 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
228 const SDLoc &DL, SelectionDAG &DAG,
229 const CCValAssign &VA, ISD::ArgFlagsTy Flags) const;
230
231 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
232 SDValue LowerToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL,
233 SelectionDAG &DAG) const;
234 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
235 SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
236 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
237 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
238 SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) const;
239 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
240 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
241 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
242 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
243 SDValue LowerGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
244 int64_t Offset, SelectionDAG &DAG) const;
245 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
246 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
247 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
248 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
249 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
250
251 SDValue LowerATOMICFENCE(SDValue Op, SelectionDAG &DAG) const;
252
253 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
254 CallingConv::ID CallConv, bool IsVarArg,
256 const SDLoc &DL, SelectionDAG &DAG,
257 SmallVectorImpl<SDValue> &InVals) const;
258 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
259
260 /// LowerFormalArguments - transform physical registers into virtual
261 /// registers and generate load operations for arguments places on the stack.
262 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CCID,
263 bool IsVarArg,
265 const SDLoc &DL, SelectionDAG &DAG,
266 SmallVectorImpl<SDValue> &InVals) const override;
267
268 SDValue LowerCall(CallLoweringInfo &CLI,
269 SmallVectorImpl<SDValue> &InVals) const override;
270
271 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
272 bool isVarArg,
274 LLVMContext &Context) const override;
275
276 /// Lower the result values of a call into the
277 /// appropriate copies out of appropriate physical registers.
278 SDValue LowerReturn(SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
280 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
281 SelectionDAG &DAG) const override;
282
283 SDValue LowerExternalSymbolCall(SelectionDAG &DAG, SDLoc loc,
284 llvm::StringRef SymbolName,
285 ArgListTy &&ArgList) const;
286 SDValue getTLSGetAddr(GlobalAddressSDNode *GA, SelectionDAG &DAG,
287 unsigned TargetFlags) const;
288 SDValue getM68kReadTp(SDLoc Loc, SelectionDAG &DAG) const;
289
290 SDValue LowerTLSGeneralDynamic(GlobalAddressSDNode *GA,
291 SelectionDAG &DAG) const;
292 SDValue LowerTLSLocalDynamic(GlobalAddressSDNode *GA,
293 SelectionDAG &DAG) const;
294 SDValue LowerTLSInitialExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) const;
295 SDValue LowerTLSLocalExec(GlobalAddressSDNode *GA, SelectionDAG &DAG) const;
296
297 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
298 SDValue C) const override;
299
300 MachineBasicBlock *EmitLoweredSelect(MachineInstr &I,
301 MachineBasicBlock *MBB) const;
302 MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr &MI,
303 MachineBasicBlock *BB) const;
304
305 /// Emit nodes that will be selected as "test Op0,Op0", or something
306 /// equivalent, for use with the given M68k condition code.
307 SDValue EmitTest(SDValue Op0, unsigned M68kCC, const SDLoc &dl,
308 SelectionDAG &DAG) const;
309
310 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
311 /// equivalent, for use with the given M68k condition code.
312 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC, const SDLoc &dl,
313 SelectionDAG &DAG) const;
314
315 /// Check whether the call is eligible for tail call optimization. Targets
316 /// that want to do tail call optimization should implement this function.
317 bool IsEligibleForTailCallOptimization(
318 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
319 bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
321 const SmallVectorImpl<SDValue> &OutVals,
322 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
323
324 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
325};
326} // namespace llvm
327
328#endif // LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
return RetTy
IRTranslator LLVM IR MI
This file contains the entry points for global functions defined in the M68k target library,...
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:748
CCValAssign - Represent assignment of one arg/retval to a location.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
static const M68kTargetLowering * create(const M68kTargetMachine &TM, const M68kSubtarget &STI)
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Context object for machine code objects.
Definition: MCContext.h:81
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
std::vector< ArgListEntry > ArgListTy
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1406
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1529
NodeType
M68k Specific DAG nodes.
@ SETCC
M68k SetCC.
@ BRCOND
M68k conditional branches.
@ FIRST_NUMBER
Start the numbering from where ISD NodeType finishes.
@ CMOV
M68k conditional moves.
@ BTST
M68k bit-test instructions.
@ CMP
M68k compare and logical compare instructions.
@ SELECT
M68k Select.
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ And
Bitwise or logical AND of integers.
#define N
Helper struct shared between Function Specialization and SCCP Solver.
Definition: SCCPSolver.h:41
Extended Value Type.
Definition: ValueTypes.h:34