LLVM 19.0.0git
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MachineScheduler.cpp File Reference
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/PriorityQueue.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <string>
#include <tuple>
#include <utility>
#include <vector>

Go to the source code of this file.

Classes

struct  llvm::GraphTraits< ScheduleDAGMI * >
 
struct  llvm::DOTGraphTraits< ScheduleDAGMI * >
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::MISchedPostRASched
 

Macros

#define DEBUG_TYPE   "machine-scheduler"
 

Typedefs

using MBBRegionsVector = SmallVector< SchedRegion, 16 >
 

Enumerations

enum  llvm::MISchedPostRASched::Direction { llvm::MISchedPostRASched::TopDown , llvm::MISchedPostRASched::BottomUp }
 

Functions

 STATISTIC (NumClustered, "Number of load/store pairs clustered")
 
cl::opt< boolllvm::ForceTopDown ("misched-topdown", cl::Hidden, cl::desc("Force top-down list scheduling"))
 
cl::opt< boolllvm::ForceBottomUp ("misched-bottomup", cl::Hidden, cl::desc("Force bottom-up list scheduling"))
 
cl::opt< boolllvm::VerifyScheduling ("verify-misched", cl::Hidden, cl::desc("Verify machine instrs before and after machine scheduling"))
 
cl::opt< boolllvm::ViewMISchedDAGs ("view-misched-dags", cl::Hidden, cl::desc("Pop up a window to show MISched dags after they are processed"))
 
cl::opt< boolllvm::PrintDAGs ("misched-print-dags", cl::Hidden, cl::desc("Print schedule DAGs"))
 
 INITIALIZE_PASS_BEGIN (MachineScheduler, DEBUG_TYPE, "Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(MachineScheduler
 
 INITIALIZE_PASS_BEGIN (PostMachineScheduler, "postmisched", "PostRA Machine Instruction Scheduler", false, false) INITIALIZE_PASS_END(PostMachineScheduler
 
static ScheduleDAGInstrsuseDefaultMachineSched (MachineSchedContext *C)
 A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.
 
static MachineBasicBlock::const_iterator priorNonDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator Beg)
 Decrement this iterator until reaching the top or a non-debug instr.
 
static MachineBasicBlock::iterator priorNonDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator Beg)
 Non-const version.
 
static MachineBasicBlock::const_iterator nextIfDebug (MachineBasicBlock::const_iterator I, MachineBasicBlock::const_iterator End)
 If this iterator is a debug value, increment until reaching the End or a non-debug instruction.
 
static MachineBasicBlock::iterator nextIfDebug (MachineBasicBlock::iterator I, MachineBasicBlock::const_iterator End)
 Non-const version.
 
static bool isSchedBoundary (MachineBasicBlock::iterator MI, MachineBasicBlock *MBB, MachineFunction *MF, const TargetInstrInfo *TII)
 Return true of the given instruction should not be included in a scheduling region.
 
static void getSchedRegions (MachineBasicBlock *MBB, MBBRegionsVector &Regions, bool RegionsTopDown)
 
std::unique_ptr< ScheduleDAGMutationllvm::createLoadClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
 If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.
 
std::unique_ptr< ScheduleDAGMutationllvm::createStoreClusterDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
 If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store clustering.
 
std::unique_ptr< ScheduleDAGMutationllvm::createCopyConstrainDAGMutation (const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
 
static bool checkResourceLimit (unsigned LFactor, unsigned Count, unsigned Latency, bool AfterSchedNode)
 Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited.
 
static unsigned computeRemLatency (SchedBoundary &CurrZone)
 Compute remaining latency.
 
bool llvm::tryLess (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
 Return true if this heuristic determines order.
 
bool llvm::tryGreater (int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
 
bool llvm::tryLatency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
 
static void tracePick (GenericSchedulerBase::CandReason Reason, bool IsTop)
 
static void tracePick (const GenericSchedulerBase::SchedCandidate &Cand)
 
bool llvm::tryPressure (const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)
 
unsigned llvm::getWeakLeft (const SUnit *SU, bool isTop)
 
int llvm::biasPhysReg (const SUnit *SU, bool isTop)
 Minimize physical register live ranges.
 
static ScheduleDAGInstrscreateConvergingSched (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateILPMaxScheduler (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateILPMinScheduler (MachineSchedContext *C)
 
static ScheduleDAGInstrscreateInstructionShuffler (MachineSchedContext *C)
 
static bool sortIntervals (const ResourceSegments::IntervalTy &A, const ResourceSegments::IntervalTy &B)
 Sort predicate for the intervals stored in an instance of ResourceSegments.
 

Variables

cl::opt< MISchedPostRASched::Directionllvm::PostRADirection ("misched-postra-direction", cl::Hidden, cl::desc("Post reg-alloc list scheduling direction"), cl::init(MISchedPostRASched::TopDown), cl::values(clEnumValN(MISchedPostRASched::TopDown, "topdown", "Force top-down post reg-alloc list scheduling"), clEnumValN(MISchedPostRASched::BottomUp, "bottomup", "Force bottom-up post reg-alloc list scheduling")))
 
cl::opt< boolllvm::DumpCriticalPathLength ("misched-dcpl", cl::Hidden, cl::desc("Print critical path length to stdout"))
 
cl::opt< boolllvm::MISchedDumpReservedCycles ("misched-dump-reserved-cycles", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary."))
 
cl::opt< boolllvm::MischedDetailResourceBooking ("misched-detail-resource-booking", cl::Hidden, cl::init(false), cl::desc("Show details of invoking getNextResoufceCycle."))
 
static cl::opt< unsignedViewMISchedCutoff ("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff"))
 In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them.
 
static cl::opt< unsignedMISchedCutoff ("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U))
 
static cl::opt< std::string > SchedOnlyFunc ("misched-only-func", cl::Hidden, cl::desc("Only schedule this function"))
 
static cl::opt< unsignedSchedOnlyBlock ("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#"))
 
static cl::opt< unsignedReadyListLimit ("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256))
 Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists.
 
static cl::opt< boolEnableRegPressure ("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true))
 
static cl::opt< boolEnableCyclicPath ("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true))
 
static cl::opt< boolEnableMemOpCluster ("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true))
 
static cl::opt< boolForceFastCluster ("force-fast-cluster", cl::Hidden, cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities"), cl::init(false))
 
static cl::opt< unsignedFastClusterThreshold ("fast-cluster-threshold", cl::Hidden, cl::desc("The threshold for fast cluster"), cl::init(1000))
 
static cl::opt< boolMISchedDumpScheduleTrace ("misched-dump-schedule-trace", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary."))
 
static cl::opt< unsignedHeaderColWidth ("misched-dump-schedule-trace-col-header-width", cl::Hidden, cl::desc("Set width of the columns with " "the resources and schedule units"), cl::init(19))
 
static cl::opt< unsignedColWidth ("misched-dump-schedule-trace-col-width", cl::Hidden, cl::desc("Set width of the columns showing resource booking."), cl::init(5))
 
static cl::opt< boolMISchedSortResourcesInTrace ("misched-sort-resources-in-trace", cl::Hidden, cl::init(true), cl::desc("Sort the resources printed in the dump trace"))
 
static cl::opt< unsignedMIResourceCutOff ("misched-resource-cutoff", cl::Hidden, cl::desc("Number of intervals to track"), cl::init(10))
 
static const unsigned MinSubtreeSize = 8
 
 DEBUG_TYPE
 
Machine Instruction Scheduler
 
Machine Instruction false
 
 postmisched
 
static cl::opt< MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser< MachineSchedRegistry > > MachineSchedOpt ("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use"))
 MachineSchedOpt allows command line selection of the scheduler.
 
static MachineSchedRegistry DefaultSchedRegistry ("default", "Use the target's default scheduler choice.", useDefaultMachineSched)
 
static cl::opt< boolEnableMachineSched ("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden)
 
static cl::opt< boolEnablePostRAMachineSched ("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden)
 
static const charscheduleTableLegend = " i: issue\n x: resource booked"
 
static const unsigned InvalidCycle = ~0U
 
static MachineSchedRegistry GenericSchedRegistry ("converge", "Standard converging scheduler.", createConvergingSched)
 
static MachineSchedRegistry ILPMaxRegistry ("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler)
 
static MachineSchedRegistry ILPMinRegistry ("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler)
 
static MachineSchedRegistry ShufflerRegistry ("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler)
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "machine-scheduler"

Definition at line 74 of file MachineScheduler.cpp.

Typedef Documentation

◆ MBBRegionsVector

using MBBRegionsVector = SmallVector<SchedRegion, 16>

Definition at line 548 of file MachineScheduler.cpp.

Function Documentation

◆ checkResourceLimit()

static bool checkResourceLimit ( unsigned  LFactor,
unsigned  Count,
unsigned  Latency,
bool  AfterSchedNode 
)
static

Given a Count of resource usage and a Latency value, return true if a SchedBoundary becomes resource limited.

If we are checking after scheduling a node, we should return true when we just reach the resource limit.

Definition at line 2228 of file MachineScheduler.cpp.

References llvm::Latency.

Referenced by llvm::SchedBoundary::bumpCycle(), llvm::SchedBoundary::bumpNode(), and llvm::GenericSchedulerBase::setPolicy().

◆ computeRemLatency()

static unsigned computeRemLatency ( SchedBoundary CurrZone)
static

Compute remaining latency.

We need this both to determine whether the overall schedule has become latency-limited and whether the instructions outside this zone are resource or latency limited.

The "dependent" latency is updated incrementally during scheduling as the max height/depth of scheduled nodes minus the cycles since it was scheduled: DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone

The "independent" latency is the max ready queue depth: ILat = max N.depth for N in Available|Pending

RemainingLatency is the greater of independent and dependent latency.

These computations are expensive, especially in DAGs with many edges, so only do them if necessary.

Definition at line 2996 of file MachineScheduler.cpp.

References llvm::SchedBoundary::Available, llvm::ReadyQueue::elements(), llvm::SchedBoundary::findMaxLatency(), llvm::SchedBoundary::getDependentLatency(), and llvm::SchedBoundary::Pending.

Referenced by llvm::GenericSchedulerBase::setPolicy().

◆ createConvergingSched()

static ScheduleDAGInstrs * createConvergingSched ( MachineSchedContext C)
static

Definition at line 3848 of file MachineScheduler.cpp.

References llvm::CallingConv::C, and llvm::createGenericSchedLive().

◆ createILPMaxScheduler()

static ScheduleDAGInstrs * createILPMaxScheduler ( MachineSchedContext C)
static

Definition at line 4159 of file MachineScheduler.cpp.

References llvm::CallingConv::C.

◆ createILPMinScheduler()

static ScheduleDAGInstrs * createILPMinScheduler ( MachineSchedContext C)
static

Definition at line 4162 of file MachineScheduler.cpp.

References llvm::CallingConv::C.

◆ createInstructionShuffler()

static ScheduleDAGInstrs * createInstructionShuffler ( MachineSchedContext C)
static

◆ getSchedRegions()

static void getSchedRegions ( MachineBasicBlock MBB,
MBBRegionsVector Regions,
bool  RegionsTopDown 
)
static

◆ INITIALIZE_PASS_BEGIN() [1/2]

INITIALIZE_PASS_BEGIN ( MachineScheduler  ,
DEBUG_TYPE  ,
"Machine Instruction Scheduler"  ,
false  ,
false   
)

◆ INITIALIZE_PASS_BEGIN() [2/2]

INITIALIZE_PASS_BEGIN ( PostMachineScheduler  ,
"postmisched"  ,
"PostRA Machine Instruction Scheduler"  ,
false  ,
false   
)

◆ isSchedBoundary()

static bool isSchedBoundary ( MachineBasicBlock::iterator  MI,
MachineBasicBlock MBB,
MachineFunction MF,
const TargetInstrInfo TII 
)
static

Return true of the given instruction should not be included in a scheduling region.

MachineScheduler does not currently support scheduling across calls. To handle calls, the DAG builder needs to be modified to create register anti/output dependencies on the registers clobbered by the call's regmask operand. In PreRA scheduling, the stack pointer adjustment already prevents scheduling across calls. In PostRA scheduling, we need the isCall to enforce the boundary, but there would be no benefit to postRA scheduling across calls this late anyway.

Definition at line 523 of file MachineScheduler.cpp.

References llvm::HexagonInstrInfo::isSchedulingBoundary(), MBB, MI, and TII.

Referenced by getSchedRegions().

◆ nextIfDebug() [1/2]

If this iterator is a debug value, increment until reaching the End or a non-debug instruction.

Definition at line 367 of file MachineScheduler.cpp.

References End, and I.

Referenced by llvm::ScheduleDAGMI::initQueues(), nextIfDebug(), llvm::ScheduleDAGMI::schedule(), llvm::ScheduleDAGMILive::scheduleMI(), and llvm::ScheduleDAGMILive::updatePressureDiffs().

◆ nextIfDebug() [2/2]

◆ priorNonDebug() [1/2]

Decrement this iterator until reaching the top or a non-debug instr.

Definition at line 346 of file MachineScheduler.cpp.

References assert(), and I.

Referenced by llvm::ScheduleDAGMILive::initRegPressure(), priorNonDebug(), llvm::ScheduleDAGMI::schedule(), and llvm::ScheduleDAGMILive::scheduleMI().

◆ priorNonDebug() [2/2]

◆ sortIntervals()

static bool sortIntervals ( const ResourceSegments::IntervalTy A,
const ResourceSegments::IntervalTy B 
)
static

Sort predicate for the intervals stored in an instance of ResourceSegments.

Intervals are always disjoint (no intersection for any pairs of intervals), therefore we can sort the totality of the intervals by looking only at the left boundary.

Definition at line 4359 of file MachineScheduler.cpp.

References A, and B.

◆ STATISTIC()

STATISTIC ( NumClustered  ,
"Number of load/store pairs clustered"   
)

◆ tracePick() [1/2]

static void tracePick ( const GenericSchedulerBase::SchedCandidate Cand)
static

◆ tracePick() [2/2]

static void tracePick ( GenericSchedulerBase::CandReason  Reason,
bool  IsTop 
)
static

◆ useDefaultMachineSched()

static ScheduleDAGInstrs * useDefaultMachineSched ( MachineSchedContext C)
static

A dummy default scheduler factory indicates whether the scheduler is overridden on the command line.

Definition at line 319 of file MachineScheduler.cpp.

Variable Documentation

◆ ColWidth

cl::opt< unsigned > ColWidth("misched-dump-schedule-trace-col-width", cl::Hidden, cl::desc("Set width of the columns showing resource booking."), cl::init(5)) ( "misched-dump-schedule-trace-col-width"  ,
cl::Hidden  ,
cl::desc("Set width of the columns showing resource booking.")  ,
cl::init(5)   
)
static

◆ DEBUG_TYPE

DEBUG_TYPE

Definition at line 269 of file MachineScheduler.cpp.

◆ DefaultSchedRegistry

MachineSchedRegistry DefaultSchedRegistry("default", "Use the target's default scheduler choice.", useDefaultMachineSched) ( "default"  ,
"Use the target's default scheduler choice."  ,
useDefaultMachineSched   
)
static

◆ EnableCyclicPath

cl::opt< bool > EnableCyclicPath("misched-cyclicpath", cl::Hidden, cl::desc("Enable cyclic critical path analysis."), cl::init(true)) ( "misched-cyclicpath"  ,
cl::Hidden  ,
cl::desc("Enable cyclic critical path analysis.")  ,
cl::init(true  
)
static

◆ EnableMachineSched

cl::opt< bool > EnableMachineSched("enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), cl::Hidden) ( "enable-misched"  ,
cl::desc("Enable the machine instruction scheduling pass.")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableMemOpCluster

cl::opt< bool > EnableMemOpCluster("misched-cluster", cl::Hidden, cl::desc("Enable memop clustering."), cl::init(true)) ( "misched-cluster"  ,
cl::Hidden  ,
cl::desc("Enable memop clustering.")  ,
cl::init(true  
)
static

◆ EnablePostRAMachineSched

cl::opt< bool > EnablePostRAMachineSched("enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden) ( "enable-post-misched"  ,
cl::desc("Enable the post-ra machine instruction scheduling pass.")  ,
cl::init(true ,
cl::Hidden   
)
static

◆ EnableRegPressure

cl::opt< bool > EnableRegPressure("misched-regpressure", cl::Hidden, cl::desc("Enable register pressure scheduling."), cl::init(true)) ( "misched-regpressure"  ,
cl::Hidden  ,
cl::desc("Enable register pressure scheduling.")  ,
cl::init(true  
)
static

◆ false

PostRA Machine Instruction false

Definition at line 270 of file MachineScheduler.cpp.

◆ FastClusterThreshold

cl::opt< unsigned > FastClusterThreshold("fast-cluster-threshold", cl::Hidden, cl::desc("The threshold for fast cluster"), cl::init(1000)) ( "fast-cluster-threshold"  ,
cl::Hidden  ,
cl::desc("The threshold for fast cluster")  ,
cl::init(1000)   
)
static

◆ ForceFastCluster

cl::opt< bool > ForceFastCluster("force-fast-cluster", cl::Hidden, cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities"), cl::init(false)) ( "force-fast-cluster"  ,
cl::Hidden  ,
cl::desc("Switch to fast cluster algorithm with the lost " "of some fusion opportunities")  ,
cl::init(false)   
)
static

◆ GenericSchedRegistry

MachineSchedRegistry GenericSchedRegistry("converge", "Standard converging scheduler.", createConvergingSched) ( "converge"  ,
"Standard converging scheduler."  ,
createConvergingSched   
)
static

◆ HeaderColWidth

cl::opt< unsigned > HeaderColWidth("misched-dump-schedule-trace-col-header-width", cl::Hidden, cl::desc("Set width of the columns with " "the resources and schedule units"), cl::init(19)) ( "misched-dump-schedule-trace-col-header-width"  ,
cl::Hidden  ,
cl::desc("Set width of the columns with " "the resources and schedule units")  ,
cl::init(19)   
)
static

◆ ILPMaxRegistry

MachineSchedRegistry ILPMaxRegistry("ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler) ( "ilpmax"  ,
"Schedule bottom-up for max ILP"  ,
createILPMaxScheduler   
)
static

◆ ILPMinRegistry

MachineSchedRegistry ILPMinRegistry("ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler) ( "ilpmin"  ,
"Schedule bottom-up for min ILP"  ,
createILPMinScheduler   
)
static

◆ InvalidCycle

const unsigned InvalidCycle = ~0U
static

◆ MachineSchedOpt

cl::opt< MachineSchedRegistry::ScheduleDAGCtor, false, RegisterPassParser< MachineSchedRegistry > > MachineSchedOpt("misched", cl::init(&useDefaultMachineSched), cl::Hidden, cl::desc("Machine instruction scheduler to use")) ( "misched"  ,
cl::init &  useDefaultMachineSched,
cl::Hidden  ,
cl::desc("Machine instruction scheduler to use")   
)
static

MachineSchedOpt allows command line selection of the scheduler.

◆ MinSubtreeSize

const unsigned MinSubtreeSize = 8
static

Definition at line 193 of file MachineScheduler.cpp.

Referenced by llvm::ScheduleDAGMILive::computeDFSResult().

◆ MIResourceCutOff

cl::opt< unsigned > MIResourceCutOff("misched-resource-cutoff", cl::Hidden, cl::desc("Number of intervals to track"), cl::init(10)) ( "misched-resource-cutoff"  ,
cl::Hidden  ,
cl::desc("Number of intervals to track")  ,
cl::init(10)   
)
static

◆ MISchedCutoff

cl::opt< unsigned > MISchedCutoff("misched-cutoff", cl::Hidden, cl::desc("Stop scheduling after N instructions"), cl::init(~0U)) ( "misched-cutoff"  ,
cl::Hidden  ,
cl::desc("Stop scheduling after N instructions")  ,
cl::init(~0U)   
)
static

◆ MISchedDumpScheduleTrace

cl::opt< bool > MISchedDumpScheduleTrace("misched-dump-schedule-trace", cl::Hidden, cl::init(false), cl::desc("Dump resource usage at schedule boundary.")) ( "misched-dump-schedule-trace"  ,
cl::Hidden  ,
cl::init(false)  ,
cl::desc("Dump resource usage at schedule boundary.")   
)
static

◆ MISchedSortResourcesInTrace

cl::opt< bool > MISchedSortResourcesInTrace("misched-sort-resources-in-trace", cl::Hidden, cl::init(true), cl::desc("Sort the resources printed in the dump trace")) ( "misched-sort-resources-in-trace"  ,
cl::Hidden  ,
cl::init(true ,
cl::desc("Sort the resources printed in the dump trace")   
)
static

◆ postmisched

postmisched

Definition at line 298 of file MachineScheduler.cpp.

◆ ReadyListLimit

cl::opt< unsigned > ReadyListLimit("misched-limit", cl::Hidden, cl::desc("Limit ready list to N instructions"), cl::init(256)) ( "misched-limit"  ,
cl::Hidden  ,
cl::desc("Limit ready list to N instructions")  ,
cl::init(256)   
)
static

Avoid quadratic complexity in unusually large basic blocks by limiting the size of the ready lists.

Referenced by llvm::SchedBoundary::releaseNode(), and llvm::SchedBoundary::releasePending().

◆ SchedOnlyBlock

cl::opt< unsigned > SchedOnlyBlock("misched-only-block", cl::Hidden, cl::desc("Only schedule this MBB#")) ( "misched-only-block"  ,
cl::Hidden  ,
cl::desc("Only schedule this MBB#")   
)
static

◆ SchedOnlyFunc

cl::opt< std::string > SchedOnlyFunc("misched-only-func", cl::Hidden, cl::desc("Only schedule this function")) ( "misched-only-func"  ,
cl::Hidden  ,
cl::desc("Only schedule this function")   
)
static

◆ Scheduler

PostRA Machine Instruction Scheduler

◆ scheduleTableLegend

const char* scheduleTableLegend = " i: issue\n x: resource booked"
static

◆ ShufflerRegistry

MachineSchedRegistry ShufflerRegistry("shuffle", "Shuffle machine instructions alternating directions", createInstructionShuffler) ( "shuffle"  ,
"Shuffle machine instructions alternating directions"  ,
createInstructionShuffler   
)
static

◆ ViewMISchedCutoff

cl::opt< unsigned > ViewMISchedCutoff("view-misched-cutoff", cl::Hidden, cl::desc("Hide nodes with more predecessor/successor than cutoff")) ( "view-misched-cutoff"  ,
cl::Hidden  ,
cl::desc("Hide nodes with more predecessor/successor than cutoff")   
)
static

In some situations a few uninteresting nodes depend on nearly all other nodes in the graph, provide a cutoff to hide them.

Referenced by llvm::DOTGraphTraits< ScheduleDAGMI * >::isNodeHidden().