LLVM  16.0.0git
Macros | Functions | Variables
RegAllocGreedy.cpp File Reference
#include "RegAllocGreedy.h"
#include "AllocationOrder.h"
#include "InterferenceCache.h"
#include "LiveDebugVariables.h"
#include "RegAllocBase.h"
#include "RegAllocEvictionAdvisor.h"
#include "RegAllocPriorityAdvisor.h"
#include "SpillPlacement.h"
#include "SplitKit.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalUnion.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/Spiller.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/Timer.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <utility>

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "regalloc"
 

Functions

 STATISTIC (NumGlobalSplits, "Number of split global live ranges")
 
 STATISTIC (NumLocalSplits, "Number of split local live ranges")
 
 STATISTIC (NumEvicted, "Number of interferences evicted")
 
 INITIALIZE_PASS_BEGIN (RAGreedy, "greedy", "Greedy Register Allocator", false, false) INITIALIZE_PASS_END(RAGreedy
 
static unsigned getNumAllocatableRegsForConstraints (const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI)
 Get the number of allocatable registers that match the constraints of Reg on MI and that are also in SuperRC. More...
 
static LaneBitmask getInstReadLaneMask (const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const MachineInstr &MI, Register Reg)
 
static bool readsLaneSubset (const MachineRegisterInfo &MRI, const MachineInstr *MI, const LiveInterval &VirtReg, const TargetRegisterInfo *TRI, SlotIndex Use)
 Return true if MI at \P Use reads a subset of the lanes live in VirtReg. More...
 
static bool hasTiedDef (MachineRegisterInfo *MRI, unsigned reg)
 Return true if reg has any tied def operand. More...
 
static bool assignedRegPartiallyOverlaps (const TargetRegisterInfo &TRI, const VirtRegMap &VRM, MCRegister PhysReg, const LiveInterval &Intf)
 Return true if the existing assignment of Intf overlaps, but is not the same, as PhysReg. More...
 

Variables

static cl::opt< SplitEditor::ComplementSpillModeSplitSpillMode ("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")), cl::init(SplitEditor::SM_Speed))
 
static cl::opt< unsigned > LastChanceRecoloringMaxDepth ("lcr-max-depth", cl::Hidden, cl::desc("Last chance recoloring max depth"), cl::init(5))
 
static cl::opt< unsigned > LastChanceRecoloringMaxInterference ("lcr-max-interf", cl::Hidden, cl::desc("Last chance recoloring maximum number of considered" " interference at a time"), cl::init(8))
 
static cl::opt< bool > ExhaustiveSearch ("exhaustive-register-search", cl::NotHidden, cl::desc("Exhaustive Search for registers bypassing the depth " "and interference cutoffs of last chance recoloring"), cl::Hidden)
 
static cl::opt< bool > EnableDeferredSpilling ("enable-deferred-spilling", cl::Hidden, cl::desc("Instead of spilling a variable right away, defer the actual " "code insertion to the end of the allocation. That way the " "allocator might still find a suitable coloring for this " "variable because of other evicted variables."), cl::init(false))
 
static cl::opt< unsigned > CSRFirstTimeCost ("regalloc-csr-first-time-cost", cl::desc("Cost for first time use of callee-saved register."), cl::init(0), cl::Hidden)
 
static cl::opt< unsigned long > GrowRegionComplexityBudget ("grow-region-complexity-budget", cl::desc("growRegion() does not scale with the number of BB edges, so " "limit its budget and bail out once we reach the limit."), cl::init(10000), cl::Hidden)
 
static cl::opt< bool > GreedyRegClassPriorityTrumpsGlobalness ("greedy-regclass-priority-trumps-globalness", cl::desc("Change the greedy register allocator's live range priority " "calculation to make the AllocationPriority of the register class " "more important then whether the range is global"), cl::Hidden)
 
static cl::opt< bool > GreedyReverseLocalAssignment ("greedy-reverse-local-assignment", cl::desc("Reverse allocation order of local live ranges, such that " "shorter local live ranges will tend to be allocated first"), cl::Hidden)
 
static RegisterRegAlloc greedyRegAlloc ("greedy", "greedy register allocator", createGreedyRegisterAllocator)
 
 greedy
 
Greedy Register Allocator
 
Greedy Register false
 
const float Hysteresis = (2007 / 2048.0f)
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "regalloc"

Definition at line 80 of file RegAllocGreedy.cpp.

Function Documentation

◆ assignedRegPartiallyOverlaps()

static bool assignedRegPartiallyOverlaps ( const TargetRegisterInfo TRI,
const VirtRegMap VRM,
MCRegister  PhysReg,
const LiveInterval Intf 
)
static

Return true if the existing assignment of Intf overlaps, but is not the same, as PhysReg.

Definition at line 1751 of file RegAllocGreedy.cpp.

References llvm::VirtRegMap::getPhys(), llvm::LiveInterval::reg(), llvm::TargetRegisterInfo::regsOverlap(), llvm::RegAllocBase::TRI, and llvm::RegAllocBase::VRM.

◆ getInstReadLaneMask()

static LaneBitmask getInstReadLaneMask ( const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const MachineInstr MI,
Register  Reg 
)
static

◆ getNumAllocatableRegsForConstraints()

static unsigned getNumAllocatableRegsForConstraints ( const MachineInstr MI,
Register  Reg,
const TargetRegisterClass SuperRC,
const TargetInstrInfo TII,
const TargetRegisterInfo TRI,
const RegisterClassInfo RCI 
)
static

Get the number of allocatable registers that match the constraints of Reg on MI and that are also in SuperRC.

Definition at line 1246 of file RegAllocGreedy.cpp.

References assert(), llvm::RegisterClassInfo::getNumAllocatableRegs(), MI, TII, and llvm::RegAllocBase::TRI.

◆ hasTiedDef()

static bool hasTiedDef ( MachineRegisterInfo MRI,
unsigned  reg 
)
static

Return true if reg has any tied def operand.

Definition at line 1741 of file RegAllocGreedy.cpp.

References llvm::MachineRegisterInfo::def_operands(), and llvm::RegAllocBase::MRI.

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( RAGreedy  ,
"greedy"  ,
"Greedy Register Allocator ,
false  ,
false   
)

◆ readsLaneSubset()

static bool readsLaneSubset ( const MachineRegisterInfo MRI,
const MachineInstr MI,
const LiveInterval VirtReg,
const TargetRegisterInfo TRI,
SlotIndex  Use 
)
static

Return true if MI at \P Use reads a subset of the lanes live in VirtReg.

Definition at line 1287 of file RegAllocGreedy.cpp.

References llvm::TargetRegisterInfo::getCoveringLanes(), getInstReadLaneMask(), MI, llvm::RegAllocBase::MRI, llvm::LiveInterval::reg(), S, llvm::LiveInterval::subranges(), and llvm::RegAllocBase::TRI.

◆ STATISTIC() [1/3]

STATISTIC ( NumEvicted  ,
"Number of interferences evicted"   
)

◆ STATISTIC() [2/3]

STATISTIC ( NumGlobalSplits  ,
"Number of split global live ranges"   
)

◆ STATISTIC() [3/3]

STATISTIC ( NumLocalSplits  ,
"Number of split local live ranges"   
)

Variable Documentation

◆ Allocator

Greedy Register Allocator

Definition at line 168 of file RegAllocGreedy.cpp.

◆ CSRFirstTimeCost

cl::opt<unsigned> CSRFirstTimeCost("regalloc-csr-first-time-cost", cl::desc("Cost for first time use of callee-saved register."), cl::init(0), cl::Hidden)
static

◆ EnableDeferredSpilling

cl::opt<bool> EnableDeferredSpilling("enable-deferred-spilling", cl::Hidden, cl::desc("Instead of spilling a variable right away, defer the actual " "code insertion to the end of the allocation. That way the " "allocator might still find a suitable coloring for this " "variable because of other evicted variables."), cl::init(false))
static

◆ ExhaustiveSearch

cl::opt<bool> ExhaustiveSearch("exhaustive-register-search", cl::NotHidden, cl::desc("Exhaustive Search for registers bypassing the depth " "and interference cutoffs of last chance recoloring"), cl::Hidden)
static

◆ false

Greedy Register false

Definition at line 168 of file RegAllocGreedy.cpp.

◆ greedy

greedy

Definition at line 167 of file RegAllocGreedy.cpp.

◆ greedyRegAlloc

RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator)
static

◆ GreedyRegClassPriorityTrumpsGlobalness

cl::opt<bool> GreedyRegClassPriorityTrumpsGlobalness("greedy-regclass-priority-trumps-globalness", cl::desc("Change the greedy register allocator's live range priority " "calculation to make the AllocationPriority of the register class " "more important then whether the range is global"), cl::Hidden)
static

◆ GreedyReverseLocalAssignment

cl::opt<bool> GreedyReverseLocalAssignment("greedy-reverse-local-assignment", cl::desc("Reverse allocation order of local live ranges, such that " "shorter local live ranges will tend to be allocated first"), cl::Hidden)
static

◆ GrowRegionComplexityBudget

cl::opt<unsigned long> GrowRegionComplexityBudget("grow-region-complexity-budget", cl::desc("growRegion() does not scale with the number of BB edges, so " "limit its budget and bail out once we reach the limit."), cl::init(10000), cl::Hidden)
static

◆ Hysteresis

const float Hysteresis = (2007 / 2048.0f)

Definition at line 184 of file RegAllocGreedy.cpp.

◆ LastChanceRecoloringMaxDepth

cl::opt<unsigned> LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden, cl::desc("Last chance recoloring max depth"), cl::init(5))
static

◆ LastChanceRecoloringMaxInterference

cl::opt<unsigned> LastChanceRecoloringMaxInterference("lcr-max-interf", cl::Hidden, cl::desc("Last chance recoloring maximum number of considered" " interference at a time"), cl::init(8))
static

◆ SplitSpillMode

cl::opt<SplitEditor::ComplementSpillMode> SplitSpillMode("split-spill-mode", cl::Hidden, cl::desc("Spill mode for splitting live ranges"), cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")), cl::init(SplitEditor::SM_Speed))
static