LLVM 19.0.0git
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SI implementation of the TargetRegisterInfo class. More...
#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "AMDGPUGenRegisterInfo.inc"
Go to the source code of this file.
Classes | |
struct | llvm::SGPRSpillBuilder |
struct | llvm::SGPRSpillBuilder::PerVGPRData |
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namespace | llvm |
This is an optimization pass for GlobalISel generic memory operations. | |
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#define | GET_REGINFO_TARGET_DESC |
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static cl::opt< bool > | EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true)) |
static const std::array< unsigned, 17 > | SubRegFromChannelTableWidthMap |
SI implementation of the TargetRegisterInfo class.
Definition in file SIRegisterInfo.cpp.
#define GET_REGINFO_TARGET_DESC |
Definition at line 29 of file SIRegisterInfo.cpp.
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Definition at line 1255 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), DL, llvm::MachineInstrBuilder::getInstr(), getOffsetMUBUFLoad(), getOffsetMUBUFStore(), MBB, MI, llvm::Offset, spillVGPRtoAGPR(), and TII.
Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
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Definition at line 2717 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth(), and llvm::SIRegisterInfo::getProperlyAlignedRC().
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Definition at line 2791 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().
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Definition at line 2641 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getProperlyAlignedRC(), and llvm::SIRegisterInfo::getVGPRClassForBitWidth().
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Definition at line 2685 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().
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Definition at line 2759 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getVectorSuperClassForBitWidth().
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Definition at line 2609 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().
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Definition at line 1292 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::hasNamedOperand(), llvm_unreachable, and TII.
Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().
Definition at line 959 of file SIRegisterInfo.cpp.
References llvm_unreachable.
Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
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Definition at line 1177 of file SIRegisterInfo.cpp.
Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().
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Definition at line 1154 of file SIRegisterInfo.cpp.
Referenced by llvm::SIRegisterInfo::buildSpillLoadStore().
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Definition at line 1119 of file SIRegisterInfo.cpp.
Referenced by buildMUBUFOffsetLoadStore().
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Definition at line 1096 of file SIRegisterInfo.cpp.
Referenced by buildMUBUFOffsetLoadStore().
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Definition at line 1212 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getVGPRToAGPRSpill(), MBB, MI, MRI, llvm::MachineInstr::ReloadReuse, llvm::MachineInstr::setAsmPrinterFlag(), TII, and TRI.
Referenced by buildMUBUFOffsetLoadStore(), and llvm::SIRegisterInfo::buildSpillLoadStore().
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Definition at line 45 of file SIRegisterInfo.cpp.
Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().