LLVM  13.0.0git
Classes | Namespaces | Macros | Functions | Variables
SIRegisterInfo.cpp File Reference
#include "SIRegisterInfo.h"
#include "AMDGPU.h"
#include "AMDGPURegisterBankInfo.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "AMDGPUGenRegisterInfo.inc"
Include dependency graph for SIRegisterInfo.cpp:

Go to the source code of this file.

Classes

struct  llvm::SGPRSpillBuilder
 
struct  llvm::SGPRSpillBuilder::PerVGPRData
 

Namespaces

 llvm
 

Macros

#define GET_REGINFO_TARGET_DESC
 

Functions

static unsigned getNumSubRegsForSpillOp (unsigned Op)
 
static int getOffsetMUBUFStore (unsigned Opc)
 
static int getOffsetMUBUFLoad (unsigned Opc)
 
static MachineInstrBuilder spillVGPRtoAGPR (const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
 
static bool buildMUBUFOffsetLoadStore (const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
 
static unsigned getFlatScratchSpillOpcode (const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
 
static const TargetRegisterClassgetAnyVGPRClassForBitWidth (unsigned BitWidth)
 
static const TargetRegisterClassgetAlignedVGPRClassForBitWidth (unsigned BitWidth)
 
static const TargetRegisterClassgetAnyAGPRClassForBitWidth (unsigned BitWidth)
 
static const TargetRegisterClassgetAlignedAGPRClassForBitWidth (unsigned BitWidth)
 

Variables

static cl::opt< bool > EnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
 
static const std::array< unsigned, 17 > SubRegFromChannelTableWidthMap
 

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

◆ GET_REGINFO_TARGET_DESC

#define GET_REGINFO_TARGET_DESC

Definition at line 27 of file SIRegisterInfo.cpp.

Function Documentation

◆ buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const GCNSubtarget ST,
MachineFrameInfo MFI,
MachineBasicBlock::iterator  MI,
int  Index,
int64_t  Offset 
)
static

◆ getAlignedAGPRClassForBitWidth()

static const TargetRegisterClass* getAlignedAGPRClassForBitWidth ( unsigned  BitWidth)
static

Definition at line 1944 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

◆ getAlignedVGPRClassForBitWidth()

static const TargetRegisterClass* getAlignedVGPRClassForBitWidth ( unsigned  BitWidth)
static

Definition at line 1888 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

◆ getAnyAGPRClassForBitWidth()

static const TargetRegisterClass* getAnyAGPRClassForBitWidth ( unsigned  BitWidth)
static

Definition at line 1922 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getAGPRClassForBitWidth().

◆ getAnyVGPRClassForBitWidth()

static const TargetRegisterClass* getAnyVGPRClassForBitWidth ( unsigned  BitWidth)
static

Definition at line 1866 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by llvm::SIRegisterInfo::getVGPRClassForBitWidth().

◆ getFlatScratchSpillOpcode()

static unsigned getFlatScratchSpillOpcode ( const SIInstrInfo TII,
unsigned  LoadStoreOp,
unsigned  EltSize 
)
static

◆ getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op)
static

Definition at line 793 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc)
static

Definition at line 884 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc)
static

Definition at line 863 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ spillVGPRtoAGPR()

static MachineInstrBuilder spillVGPRtoAGPR ( const GCNSubtarget ST,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
int  Index,
unsigned  Lane,
unsigned  ValueReg,
bool  IsKill 
)
static

Variable Documentation

◆ EnableSpillSGPRToVGPR

cl::opt<bool> EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
static

◆ SubRegFromChannelTableWidthMap

const std::array<unsigned, 17> SubRegFromChannelTableWidthMap
static
Initial value:
= {
0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9}

Definition at line 43 of file SIRegisterInfo.cpp.

Referenced by llvm::SIRegisterInfo::getSubRegFromChannel(), and llvm::SIRegisterInfo::SIRegisterInfo().