LLVM 20.0.0git
AMDGPURegisterBankInfo.h
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1//===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
15
16#include "llvm/ADT/SmallSet.h"
20
21#define GET_REGBANK_DECLARATIONS
22#include "AMDGPUGenRegisterBank.inc"
23
24namespace llvm {
25
26class LLT;
27class GCNSubtarget;
28class MachineIRBuilder;
29class SIInstrInfo;
30class SIRegisterInfo;
31class TargetRegisterInfo;
32
33/// This class provides the information for the target register banks.
35
36protected:
37
38#define GET_TARGET_REGBANK_CLASS
39#include "AMDGPUGenRegisterBank.inc"
40};
41
43public:
47
48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const;
49
51 SmallSet<Register, 4> &SGPROperandRegs,
54 ArrayRef<unsigned> OpIndices) const;
55
58 SmallSet<Register, 4> &SGPROperandRegs) const;
59
61 Register Src) const;
62
64 ArrayRef<unsigned> OpIndices) const;
65
67 unsigned OpIdx) const;
69 const OperandsMapper &OpdMapper,
70 MachineInstr &MI) const;
71 bool applyMappingLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper,
72 MachineInstr &MI) const;
74 const OperandsMapper &OpdMapper, int RSrcIdx) const;
75 unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset,
76 Register &VOffsetReg, Register &SOffsetReg,
77 int64_t &InstOffsetVal, Align Alignment) const;
79 const OperandsMapper &OpdMapper) const;
80
81 bool applyMappingBFE(MachineIRBuilder &B, const OperandsMapper &OpdMapper,
82 bool Signed) const;
83
85 const OperandsMapper &OpdMapper) const;
86
88 const OperandsMapper &OpdMapper) const;
89
91 Register Reg) const;
92
93 std::pair<Register, unsigned>
95
96 /// See RegisterBankInfo::applyMapping.
98 const OperandsMapper &OpdMapper) const override;
99
101 Register Ptr) const;
102
105
107 unsigned Default = AMDGPU::VGPRRegBankID) const;
108
109 // Return a value mapping for an operand that is required to be an SGPR.
112 const TargetRegisterInfo &TRI) const;
113
114 // Return a value mapping for an operand that is required to be a VGPR.
117 const TargetRegisterInfo &TRI) const;
118
119 // Return a value mapping for an operand that is required to be a AGPR.
122 const TargetRegisterInfo &TRI) const;
123
124 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
125 /// Regs. This appropriately sets the regbank of the new registers.
128 LLT HalfTy,
129 Register Reg) const;
130
131 template <unsigned NumOps>
133 int8_t RegBanks[NumOps];
134 int16_t Cost;
135 };
136
137 template <unsigned NumOps>
140 const std::array<unsigned, NumOps> RegSrcOpIdx,
141 ArrayRef<OpRegBankEntry<NumOps>> Table) const;
142
145 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
146
149 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
150
151 unsigned getMappingType(const MachineRegisterInfo &MRI,
152 const MachineInstr &MI) const;
153
154 bool isSALUMapping(const MachineInstr &MI) const;
155
159 const MachineInstr &MI) const;
160
162 const MachineInstr &MI,
163 int RsrcIdx) const;
164
165public:
167
168 bool isDivergentRegBank(const RegisterBank *RB) const override;
169
170 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
171 TypeSize Size) const override;
172
173 unsigned getBreakDownCost(const ValueMapping &ValMapping,
174 const RegisterBank *CurBank = nullptr) const override;
175
177 LLT) const override;
178
179 bool isScalarLoadLegal(const MachineInstr &MI) const;
180
182 getInstrAlternativeMappings(const MachineInstr &MI) const override;
183
184 const InstructionMapping &
185 getInstrMapping(const MachineInstr &MI) const override;
186
187private:
188 bool foldExtractEltToCmpSelect(MachineIRBuilder &B, MachineInstr &MI,
189 const OperandsMapper &OpdMapper) const;
190 bool foldInsertEltToCmpSelect(MachineIRBuilder &B, MachineInstr &MI,
191 const OperandsMapper &OpdMapper) const;
192};
193} // End llvm namespace.
194#endif
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
uint64_t Size
IRTranslator LLVM IR MI
unsigned Reg
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
This file defines the SmallSet class.
This class provides the information for the target register banks.
bool applyMappingDynStackAlloc(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register Offset) const
bool collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
const InstructionMapping & getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
InstructionMappings addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const
bool executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs) const
Legalize instruction MI where operands in OpIndices must be SGPRs.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
bool applyMappingMAD_64_32(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad(const MachineInstr &MI) const
void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
bool applyMappingBFE(MachineIRBuilder &B, const OperandsMapper &OpdMapper, bool Signed) const
bool applyMappingImage(MachineIRBuilder &B, MachineInstr &MI, const OperandsMapper &OpdMapper, int RSrcIdx) const
const ValueMapping * getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
bool isScalarLoadLegal(const MachineInstr &MI) const
unsigned setBufferOffsets(MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const
const ValueMapping * getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
bool applyMappingLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
void split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
const ValueMapping * getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const
Return the mapping for a pointer argument.
unsigned getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isDivergentRegBank(const RegisterBank *RB) const override
Returns true if the register bank is considered divergent.
void constrainOpWithReadfirstlane(MachineIRBuilder &B, MachineInstr &MI, unsigned OpIdx) const
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getDefaultMappingSOP(const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingAllVGPR(const MachineInstr &MI) const
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMapping...
unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
Get the cost of using ValMapping to decompose a register.
const ValueMapping * getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const InstructionMapping & getDefaultMappingVOP(const MachineInstr &MI) const
bool isSALUMapping(const MachineInstr &MI) const
Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
bool applyMappingSBufferLoad(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
void applyMappingSMULU64(MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A range adaptor for a pair of iterators.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
@ Default
The result values are uniform if and only if all operands are uniform.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Helper struct that represents how a value is mapped through different register banks.