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13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
21 #define GET_REGBANK_DECLARATIONS
22 #include "AMDGPUGenRegisterBank.inc"
28 class MachineIRBuilder;
31 class TargetRegisterInfo;
38 #define GET_TARGET_REGBANK_CLASS
39 #include "AMDGPUGenRegisterBank.inc"
74 unsigned OpIdx)
const;
92 std::pair<Register, unsigned>
105 unsigned Default = AMDGPU::VGPRRegBankID)
const;
129 template <
unsigned NumOps>
135 template <
unsigned NumOps>
138 const std::array<unsigned, NumOps> RegSrcOpIdx,
167 unsigned Size)
const override;
const ValueMapping * getSGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const InstructionMapping & getDefaultMappingAllVGPR(const MachineInstr &MI) const
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
AMDGPURegisterBankInfo(const GCNSubtarget &STI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMapping...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
const ValueMapping * getVGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const
const SIRegisterInfo * TRI
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
Register buildReadFirstLane(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
This class implements the register bank concept.
bool applyMappingLoad(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
const ValueMapping * getAGPROpMapping(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
InstructionMappings addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) const
const ValueMapping * getValueMappingForPtr(const MachineRegisterInfo &MRI, Register Ptr) const
Return the mapping for a pointer argument.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const
bool collectWaterfallOperands(SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register Offset) const
Holds all the information related to register banks.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Helper class to build MachineInstr.
const GCNSubtarget & Subtarget
Representation of each machine instruction.
unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
Get the cost of using ValMapping to decompose a register.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getMappingType(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
void split64BitValueForMapping(MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
const InstructionMapping & getDefaultMappingSOP(const MachineInstr &MI) const
bool applyMappingImage(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RSrcIdx) const
Helper struct that represents how a value is mapped through different register banks.
bool applyMappingDynStackAlloc(MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const
This class provides the information for the target register banks.
unsigned const MachineRegisterInfo * MRI
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
Wrapper class representing virtual and physical registers.
bool executeInWaterfallLoop(MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs, MachineRegisterInfo &MRI) const
Legalize instruction MI where operands in OpIndices must be SGPRs.
bool applyMappingBFE(const OperandsMapper &OpdMapper, bool Signed) const
const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad(const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingVOP(const MachineInstr &MI) const
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
A range adaptor for a pair of iterators.
bool isSALUMapping(const MachineInstr &MI) const
const InstructionMapping & getImageMapping(const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const