LLVM  13.0.0git
WebAssemblyTargetMachine.cpp
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1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific subclass of TargetMachine.
11 ///
12 //===----------------------------------------------------------------------===//
13 
17 #include "WebAssembly.h"
23 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/Function.h"
29 #include "llvm/Transforms/Scalar.h"
31 #include "llvm/Transforms/Utils.h"
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "wasm"
35 
36 // Emscripten's asm.js-style exception handling
38  "enable-emscripten-cxx-exceptions",
39  cl::desc("WebAssembly Emscripten-style exception handling"),
40  cl::init(false));
41 
42 // Emscripten's asm.js-style setjmp/longjmp handling
44  "enable-emscripten-sjlj",
45  cl::desc("WebAssembly Emscripten-style setjmp/longjmp handling"),
46  cl::init(false));
47 
48 // A command-line option to keep implicit locals
49 // for the purpose of testing with lit/llc ONLY.
50 // This produces output which is not valid WebAssembly, and is not supported
51 // by assemblers/disassemblers and other MC based tools.
53  "wasm-disable-explicit-locals", cl::Hidden,
54  cl::desc("WebAssembly: output implicit locals in"
55  " instruction output for test purposes only."),
56  cl::init(false));
57 
59  // Register the target.
64 
65  // Register backend passes
66  auto &PR = *PassRegistry::getPassRegistry();
91 }
92 
93 //===----------------------------------------------------------------------===//
94 // WebAssembly Lowering public interface.
95 //===----------------------------------------------------------------------===//
96 
98  const Triple &TT) {
99  if (!RM.hasValue()) {
100  // Default to static relocation model. This should always be more optimial
101  // than PIC since the static linker can determine all global addresses and
102  // assume direct function calls.
103  return Reloc::Static;
104  }
105 
106  if (!TT.isOSEmscripten()) {
107  // Relocation modes other than static are currently implemented in a way
108  // that only works for Emscripten, so disable them if we aren't targeting
109  // Emscripten.
110  return Reloc::Static;
111  }
112 
113  return *RM;
114 }
115 
116 /// Create an WebAssembly architecture model.
117 ///
119  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
123  TT.isArch64Bit()
124  ? "e-m:e-p:64:64-i64:64-n32:64-S128-ni:1"
125  : "e-m:e-p:32:32-i64:64-n32:64-S128-ni:1",
126  TT, CPU, FS, Options, getEffectiveRelocModel(RM, TT),
127  getEffectiveCodeModel(CM, CodeModel::Large), OL),
129  // WebAssembly type-checks instructions, but a noreturn function with a return
130  // type that doesn't match the context will cause a check failure. So we lower
131  // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
132  // 'unreachable' instructions which is meant for that case.
133  this->Options.TrapUnreachable = true;
134 
135  // WebAssembly treats each function as an independent unit. Force
136  // -ffunction-sections, effectively, so that we can emit them independently.
137  this->Options.FunctionSections = true;
138  this->Options.DataSections = true;
139  this->Options.UniqueSectionNames = true;
140 
141  initAsmInfo();
142 
143  // Note that we don't use setRequiresStructuredCFG(true). It disables
144  // optimizations than we're ok with, and want, such as critical edge
145  // splitting and tail merging.
146 }
147 
149 
151  return getSubtargetImpl(std::string(getTargetCPU()),
152  std::string(getTargetFeatureString()));
153 }
154 
155 const WebAssemblySubtarget *
157  std::string FS) const {
158  auto &I = SubtargetMap[CPU + FS];
159  if (!I) {
160  I = std::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
161  }
162  return I.get();
163 }
164 
165 const WebAssemblySubtarget *
167  Attribute CPUAttr = F.getFnAttribute("target-cpu");
168  Attribute FSAttr = F.getFnAttribute("target-features");
169 
170  std::string CPU =
171  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
172  std::string FS =
173  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
174 
175  // This needs to be done before we create a new subtarget since any
176  // creation will depend on the TM and the code generation flags on the
177  // function that reside in TargetOptions.
179 
180  return getSubtargetImpl(CPU, FS);
181 }
182 
183 namespace {
184 
185 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
186  // Take the union of all features used in the module and use it for each
187  // function individually, since having multiple feature sets in one module
188  // currently does not make sense for WebAssembly. If atomics are not enabled,
189  // also strip atomic operations and thread local storage.
190  static char ID;
191  WebAssemblyTargetMachine *WasmTM;
192 
193 public:
194  CoalesceFeaturesAndStripAtomics(WebAssemblyTargetMachine *WasmTM)
195  : ModulePass(ID), WasmTM(WasmTM) {}
196 
197  bool runOnModule(Module &M) override {
198  FeatureBitset Features = coalesceFeatures(M);
199 
200  std::string FeatureStr = getFeatureString(Features);
201  WasmTM->setTargetFeatureString(FeatureStr);
202  for (auto &F : M)
203  replaceFeatures(F, FeatureStr);
204 
205  bool StrippedAtomics = false;
206  bool StrippedTLS = false;
207 
208  if (!Features[WebAssembly::FeatureAtomics])
209  StrippedAtomics = stripAtomics(M);
210 
211  if (!Features[WebAssembly::FeatureBulkMemory])
212  StrippedTLS = stripThreadLocals(M);
213 
214  if (StrippedAtomics && !StrippedTLS)
215  stripThreadLocals(M);
216  else if (StrippedTLS && !StrippedAtomics)
217  stripAtomics(M);
218 
219  recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
220 
221  // Conservatively assume we have made some change
222  return true;
223  }
224 
225 private:
226  FeatureBitset coalesceFeatures(const Module &M) {
227  FeatureBitset Features =
228  WasmTM
229  ->getSubtargetImpl(std::string(WasmTM->getTargetCPU()),
230  std::string(WasmTM->getTargetFeatureString()))
231  ->getFeatureBits();
232  for (auto &F : M)
233  Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
234  return Features;
235  }
236 
237  std::string getFeatureString(const FeatureBitset &Features) {
238  std::string Ret;
239  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
240  if (Features[KV.Value])
241  Ret += (StringRef("+") + KV.Key + ",").str();
242  }
243  return Ret;
244  }
245 
246  void replaceFeatures(Function &F, const std::string &Features) {
247  F.removeFnAttr("target-features");
248  F.removeFnAttr("target-cpu");
249  F.addFnAttr("target-features", Features);
250  }
251 
252  bool stripAtomics(Module &M) {
253  // Detect whether any atomics will be lowered, since there is no way to tell
254  // whether the LowerAtomic pass lowers e.g. stores.
255  bool Stripped = false;
256  for (auto &F : M) {
257  for (auto &B : F) {
258  for (auto &I : B) {
259  if (I.isAtomic()) {
260  Stripped = true;
261  goto done;
262  }
263  }
264  }
265  }
266 
267  done:
268  if (!Stripped)
269  return false;
270 
271  LowerAtomicPass Lowerer;
273  for (auto &F : M)
274  Lowerer.run(F, FAM);
275 
276  return true;
277  }
278 
279  bool stripThreadLocals(Module &M) {
280  bool Stripped = false;
281  for (auto &GV : M.globals()) {
282  if (GV.isThreadLocal()) {
283  Stripped = true;
284  GV.setThreadLocal(false);
285  }
286  }
287  return Stripped;
288  }
289 
290  void recordFeatures(Module &M, const FeatureBitset &Features, bool Stripped) {
291  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
292  if (Features[KV.Value]) {
293  // Mark features as used
294  std::string MDKey = (StringRef("wasm-feature-") + KV.Key).str();
295  M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
297  }
298  }
299  // Code compiled without atomics or bulk-memory may have had its atomics or
300  // thread-local data lowered to nonatomic operations or non-thread-local
301  // data. In that case, we mark the pseudo-feature "shared-mem" as disallowed
302  // to tell the linker that it would be unsafe to allow this code ot be used
303  // in a module with shared memory.
304  if (Stripped) {
305  M.addModuleFlag(Module::ModFlagBehavior::Error, "wasm-feature-shared-mem",
307  }
308  }
309 };
311 
312 /// WebAssembly Code Generator Pass Configuration Options.
313 class WebAssemblyPassConfig final : public TargetPassConfig {
314 public:
315  WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
316  : TargetPassConfig(TM, PM) {}
317 
318  WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
319  return getTM<WebAssemblyTargetMachine>();
320  }
321 
322  FunctionPass *createTargetRegisterAllocator(bool) override;
323 
324  void addIRPasses() override;
325  bool addInstSelector() override;
326  void addPostRegAlloc() override;
327  bool addGCPasses() override { return false; }
328  void addPreEmitPass() override;
329 
330  // No reg alloc
331  bool addRegAssignAndRewriteFast() override { return false; }
332 
333  // No reg alloc
334  bool addRegAssignAndRewriteOptimized() override { return false; }
335 };
336 } // end anonymous namespace
337 
341 }
342 
345  return new WebAssemblyPassConfig(*this, PM);
346 }
347 
348 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
349  return nullptr; // No reg alloc
350 }
351 
352 //===----------------------------------------------------------------------===//
353 // The following functions are called from lib/CodeGen/Passes.cpp to modify
354 // the CodeGen pass sequence.
355 //===----------------------------------------------------------------------===//
356 
357 void WebAssemblyPassConfig::addIRPasses() {
358  // Lower atomics and TLS if necessary
359  addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
360 
361  // This is a no-op if atomics are not used in the module
362  addPass(createAtomicExpandPass());
363 
364  // Add signatures to prototype-less function declarations
366 
367  // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
369 
370  // Fix function bitcasts, as WebAssembly requires caller and callee signatures
371  // to match.
373 
374  // Optimize "returned" function attributes.
375  if (getOptLevel() != CodeGenOpt::None)
377 
378  // If exception handling is not enabled and setjmp/longjmp handling is
379  // enabled, we lower invokes into calls and delete unreachable landingpad
380  // blocks. Lowering invokes when there is no EH support is done in
381  // TargetPassConfig::addPassesToHandleExceptions, but this runs after this
382  // function and SjLj handling expects all invokes to be lowered before.
383  if (!EnableEmException &&
384  TM->Options.ExceptionModel == ExceptionHandling::None) {
385  addPass(createLowerInvokePass());
386  // The lower invoke pass may create unreachable code. Remove it in order not
387  // to process dead blocks in setjmp/longjmp handling.
389  }
390 
391  // Handle exceptions and setjmp/longjmp if enabled.
394  EnableEmSjLj));
395 
396  // Expand indirectbr instructions to switches.
397  addPass(createIndirectBrExpandPass());
398 
400 }
401 
402 bool WebAssemblyPassConfig::addInstSelector() {
404  addPass(
405  createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
406  // Run the argument-move pass immediately after the ScheduleDAG scheduler
407  // so that we can fix up the ARGUMENT instructions before anything else
408  // sees them in the wrong place.
410  // Set the p2align operands. This information is present during ISel, however
411  // it's inconvenient to collect. Collect it now, and update the immediate
412  // operands.
414 
415  // Eliminate range checks and add default targets to br_table instructions.
417 
418  return false;
419 }
420 
421 void WebAssemblyPassConfig::addPostRegAlloc() {
422  // TODO: The following CodeGen passes don't currently support code containing
423  // virtual registers. Consider removing their restrictions and re-enabling
424  // them.
425 
426  // These functions all require the NoVRegs property.
427  disablePass(&MachineCopyPropagationID);
428  disablePass(&PostRAMachineSinkingID);
429  disablePass(&PostRASchedulerID);
430  disablePass(&FuncletLayoutID);
431  disablePass(&StackMapLivenessID);
432  disablePass(&LiveDebugValuesID);
433  disablePass(&PatchableFunctionID);
434  disablePass(&ShrinkWrapID);
435 
436  // This pass hurts code size for wasm because it can generate irreducible
437  // control flow.
438  disablePass(&MachineBlockPlacementID);
439 
441 }
442 
443 void WebAssemblyPassConfig::addPreEmitPass() {
445 
446  // Nullify DBG_VALUE_LISTs that we cannot handle.
448 
449  // Eliminate multiple-entry loops.
451 
452  // Do various transformations for exception handling.
453  // Every CFG-changing optimizations should come before this.
454  if (TM->Options.ExceptionModel == ExceptionHandling::Wasm)
456 
457  // Now that we have a prologue and epilogue and all frame indices are
458  // rewritten, eliminate SP and FP. This allows them to be stackified,
459  // colored, and numbered with the rest of the registers.
461 
462  // Preparations and optimizations related to register stackification.
463  if (getOptLevel() != CodeGenOpt::None) {
464  // LiveIntervals isn't commonly run this late. Re-establish preconditions.
466 
467  // Depend on LiveIntervals and perform some optimizations on it.
469 
470  // Prepare memory intrinsic calls for register stackifying.
472 
473  // Mark registers as representing wasm's value stack. This is a key
474  // code-compression technique in WebAssembly. We run this pass (and
475  // MemIntrinsicResults above) very late, so that it sees as much code as
476  // possible, including code emitted by PEI and expanded by late tail
477  // duplication.
478  addPass(createWebAssemblyRegStackify());
479 
480  // Run the register coloring pass to reduce the total number of registers.
481  // This runs after stackification so that it doesn't consider registers
482  // that become stackified.
483  addPass(createWebAssemblyRegColoring());
484  }
485 
486  // Sort the blocks of the CFG into topological order, a prerequisite for
487  // BLOCK and LOOP markers.
488  addPass(createWebAssemblyCFGSort());
489 
490  // Insert BLOCK and LOOP markers.
491  addPass(createWebAssemblyCFGStackify());
492 
493  // Insert explicit local.get and local.set operators.
496 
497  // Lower br_unless into br_if.
499 
500  // Perform the very last peephole optimizations on the code.
501  if (getOptLevel() != CodeGenOpt::None)
502  addPass(createWebAssemblyPeephole());
503 
504  // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
506 
507  // Fix debug_values whose defs have been stackified.
509  addPass(createWebAssemblyDebugFixup());
510 }
511 
514  return new yaml::WebAssemblyFunctionInfo();
515 }
516 
518  const MachineFunction &MF) const {
519  const auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
520  return new yaml::WebAssemblyFunctionInfo(*MFI);
521 }
522 
525  SMDiagnostic &Error, SMRange &SourceRange) const {
526  const auto &YamlMFI =
527  reinterpret_cast<const yaml::WebAssemblyFunctionInfo &>(MFI);
528  MachineFunction &MF = PFS.MF;
529  MF.getInfo<WebAssemblyFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
530  return false;
531 }
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virtual void addPostRegAlloc()
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Definition: TargetPassConfig.h:419
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const SubtargetFeatureKV WebAssemblyFeatureKV[WebAssembly::NumSubtargetFeatures]
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Definition: LowerInvoke.cpp:87
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bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:155
WebAssembly.h
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We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
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A pass that lowers atomic intrinsic into non-atomic intrinsics.
Definition: LowerAtomic.h:22
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Definition: WebAssemblyTargetInfo.cpp:20
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Definition: TargetOptions.h:113
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Definition: MIRYamlMapping.h:671
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Definition: TargetRegistry.h:125
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This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::createWebAssemblyISelDag
FunctionPass * createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a WebAssembly-specific DAG, ready for instruction scheduling.
Definition: WebAssemblyISelDAGToDAG.cpp:230
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Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
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Definition: PassBuilderBindings.cpp:59
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Definition: CommandLine.h:143
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Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:255
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void initializeWebAssemblySetP2AlignOperandsPass(PassRegistry &)
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Definition: Mips16ISelLowering.cpp:341
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Container class for subtarget features.
Definition: SubtargetFeature.h:40
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Definition: MipsISelLowering.h:116
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Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: WebAssemblyTargetMachine.cpp:344
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MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:308
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Definition: WebAssemblyTargetObjectFile.h:22
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Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
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Definition: WebAssemblyTargetMachine.cpp:517
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Definition: CodeGen.h:22
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Definition: WebAssemblyTargetMachine.cpp:58
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virtual bool addInstSelector()
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Definition: TargetPassConfig.h:240
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Definition: LiveDebugValues.cpp:69
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Definition: PassRegistry.cpp:31
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Definition: TargetOptions.h:249
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Definition: MachineFunction.h:674
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Definition: WebAssemblyTargetMachine.h:23
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This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
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Definition: SourceMgr.h:251
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Definition: TargetRegistry.h:1199
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Definition: PassBuilderBindings.cpp:48
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Definition: StackMapLivenessAnalysis.cpp:86
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Definition: TargetMachine.h:98
llvm::initializeWebAssemblyExceptionInfoPass
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Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:34
Utils.h
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str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
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Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
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Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
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const WebAssemblySubtarget * getSubtargetImpl() const
Definition: WebAssemblyTargetMachine.cpp:150
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Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::WebAssemblyTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: WebAssemblyTargetMachine.cpp:513
llvm::initializeWebAssemblyFixIrreducibleControlFlowPass
void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &)
llvm::createWebAssemblyDebugFixup
FunctionPass * createWebAssemblyDebugFixup()
llvm::initializeWebAssemblyRegNumberingPass
void initializeWebAssemblyRegNumberingPass(PassRegistry &)
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
WasmDisableExplicitLocals
static cl::opt< bool > WasmDisableExplicitLocals("wasm-disable-explicit-locals", cl::Hidden, cl::desc("WebAssembly: output implicit locals in" " instruction output for test purposes only."), cl::init(false))
I
#define I(x, y, z)
Definition: MD5.cpp:59
WebAssemblyTargetObjectFile.h
EnableEmException
cl::opt< bool > EnableEmException("enable-emscripten-cxx-exceptions", cl::desc("WebAssembly Emscripten-style exception handling"), cl::init(false))
WebAssemblyTargetInfo.h
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:810
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::initializeWebAssemblyLowerBrUnlessPass
void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &)
llvm::createWebAssemblyNullifyDebugValueLists
FunctionPass * createWebAssemblyNullifyDebugValueLists()
llvm::createWebAssemblyMemIntrinsicResults
FunctionPass * createWebAssemblyMemIntrinsicResults()
TargetPassConfig.h
MachineFunctionPass.h
llvm::createWebAssemblyOptimizeReturned
FunctionPass * createWebAssemblyOptimizeReturned()
llvm::wasm::WASM_FEATURE_PREFIX_USED
@ WASM_FEATURE_PREFIX_USED
Definition: Wasm.h:321
llvm::WebAssemblyFunctionInfo
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Definition: WebAssemblyMachineFunctionInfo.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::WebAssemblyTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: WebAssemblyTargetMachine.cpp:523
llvm::initializeWebAssemblyPrepareForLiveIntervalsPass
void initializeWebAssemblyPrepareForLiveIntervalsPass(PassRegistry &)
llvm::TargetMachine::setTargetFeatureString
void setTargetFeatureString(StringRef FS)
Definition: TargetMachine.h:126
llvm::createWebAssemblyAddMissingPrototypes
ModulePass * createWebAssemblyAddMissingPrototypes()
WebAssemblyMachineFunctionInfo.h
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:469
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createWebAssemblyPrepareForLiveIntervals
FunctionPass * createWebAssemblyPrepareForLiveIntervals()
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::initializeWebAssemblyExplicitLocalsPass
void initializeWebAssemblyExplicitLocalsPass(PassRegistry &)
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:125
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:590
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:81
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:39
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:473
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::getTheWebAssemblyTarget64
Target & getTheWebAssemblyTarget64()
Definition: WebAssemblyTargetInfo.cpp:24
llvm::PerFunctionMIParsingState
Definition: MIParser.h:160
llvm::createWebAssemblyCFGSort
FunctionPass * createWebAssemblyCFGSort()
llvm::initializeWebAssemblyRegColoringPass
void initializeWebAssemblyRegColoringPass(PassRegistry &)
llvm::LowerAtomicPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &)
Definition: LowerAtomic.cpp:146
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::initializeWebAssemblyDebugFixupPass
void initializeWebAssemblyDebugFixupPass(PassRegistry &)
Function.h
llvm::initializeWebAssemblyArgumentMovePass
void initializeWebAssemblyArgumentMovePass(PassRegistry &)
llvm::TargetOptions::DataSections
unsigned DataSections
Emit data into separate sections.
Definition: TargetOptions.h:241
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:162
llvm::initializeWebAssemblyLateEHPreparePass
void initializeWebAssemblyLateEHPreparePass(PassRegistry &)
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::createWebAssemblyArgumentMove
FunctionPass * createWebAssemblyArgumentMove()
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:124
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::createWebAssemblyFixFunctionBitcasts
ModulePass * createWebAssemblyFixFunctionBitcasts()
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::initializeWebAssemblyNullifyDebugValueListsPass
void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &)
llvm::createWebAssemblySetP2AlignOperands
FunctionPass * createWebAssemblySetP2AlignOperands()
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::initializeWebAssemblyPeepholePass
void initializeWebAssemblyPeepholePass(PassRegistry &)
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::createWebAssemblyLowerBrUnless
FunctionPass * createWebAssemblyLowerBrUnless()
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::TargetOptions::FunctionSections
unsigned FunctionSections
Emit functions into separate sections.
Definition: TargetOptions.h:238
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1561
llvm::cl::desc
Definition: CommandLine.h:414
llvm::createWebAssemblyRegNumbering
FunctionPass * createWebAssemblyRegNumbering()
llvm::createWebAssemblyLateEHPrepare
FunctionPass * createWebAssemblyLateEHPrepare()
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:438
llvm::WebAssemblyTTIImpl
Definition: WebAssemblyTargetTransformInfo.h:28
TargetRegistry.h
llvm::initializeOptimizeReturnedPass
void initializeOptimizeReturnedPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::WebAssemblyTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: WebAssemblyTargetMachine.cpp:339
llvm::initializeWebAssemblyReplacePhysRegsPass
void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &)
llvm::yaml::WebAssemblyFunctionInfo
Definition: WebAssemblyMachineFunctionInfo.h:190
llvm::initializeWebAssemblyMemIntrinsicResultsPass
void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &)
llvm::createWebAssemblyPeephole
FunctionPass * createWebAssemblyPeephole()
llvm::initializeFixFunctionBitcastsPass
void initializeFixFunctionBitcastsPass(PassRegistry &)
RegAllocRegistry.h
llvm::wasm::WASM_FEATURE_PREFIX_DISALLOWED
@ WASM_FEATURE_PREFIX_DISALLOWED
Definition: Wasm.h:323
MIParser.h
llvm::WebAssemblyTargetMachine::WebAssemblyTargetMachine
WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an WebAssembly architecture model.
Definition: WebAssemblyTargetMachine.cpp:118
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38