LLVM  16.0.0git
WebAssemblyTargetMachine.cpp
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1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific subclass of TargetMachine.
11 ///
12 //===----------------------------------------------------------------------===//
13 
18 #include "WebAssembly.h"
24 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/InitializePasses.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/TargetRegistry.h"
32 #include "llvm/Transforms/Scalar.h"
34 #include "llvm/Transforms/Utils.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "wasm"
38 
39 // A command-line option to keep implicit locals
40 // for the purpose of testing with lit/llc ONLY.
41 // This produces output which is not valid WebAssembly, and is not supported
42 // by assemblers/disassemblers and other MC based tools.
44  "wasm-disable-explicit-locals", cl::Hidden,
45  cl::desc("WebAssembly: output implicit locals in"
46  " instruction output for test purposes only."),
47  cl::init(false));
48 
50  // Register the target.
55 
56  // Register backend passes
57  auto &PR = *PassRegistry::getPassRegistry();
82 }
83 
84 //===----------------------------------------------------------------------===//
85 // WebAssembly Lowering public interface.
86 //===----------------------------------------------------------------------===//
87 
89  const Triple &TT) {
90  if (!RM) {
91  // Default to static relocation model. This should always be more optimial
92  // than PIC since the static linker can determine all global addresses and
93  // assume direct function calls.
94  return Reloc::Static;
95  }
96 
97  if (!TT.isOSEmscripten()) {
98  // Relocation modes other than static are currently implemented in a way
99  // that only works for Emscripten, so disable them if we aren't targeting
100  // Emscripten.
101  return Reloc::Static;
102  }
103 
104  return *RM;
105 }
106 
107 /// Create an WebAssembly architecture model.
108 ///
110  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
114  T,
115  TT.isArch64Bit()
116  ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
117  "f128:64-n32:64-S128-ni:1:10:20"
118  : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
119  "n32:64-S128-ni:1:10:20")
120  : (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
121  "f128:64-n32:64-S128-ni:1:10:20"
122  : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
123  "n32:64-S128-ni:1:10:20"),
124  TT, CPU, FS, Options, getEffectiveRelocModel(RM, TT),
127  // WebAssembly type-checks instructions, but a noreturn function with a return
128  // type that doesn't match the context will cause a check failure. So we lower
129  // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
130  // 'unreachable' instructions which is meant for that case.
131  this->Options.TrapUnreachable = true;
132 
133  // WebAssembly treats each function as an independent unit. Force
134  // -ffunction-sections, effectively, so that we can emit them independently.
135  this->Options.FunctionSections = true;
136  this->Options.DataSections = true;
137  this->Options.UniqueSectionNames = true;
138 
139  initAsmInfo();
140 
141  // Note that we don't use setRequiresStructuredCFG(true). It disables
142  // optimizations than we're ok with, and want, such as critical edge
143  // splitting and tail merging.
144 }
145 
147 
149  return getSubtargetImpl(std::string(getTargetCPU()),
150  std::string(getTargetFeatureString()));
151 }
152 
153 const WebAssemblySubtarget *
155  std::string FS) const {
156  auto &I = SubtargetMap[CPU + FS];
157  if (!I) {
158  I = std::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
159  }
160  return I.get();
161 }
162 
163 const WebAssemblySubtarget *
165  Attribute CPUAttr = F.getFnAttribute("target-cpu");
166  Attribute FSAttr = F.getFnAttribute("target-features");
167 
168  std::string CPU =
169  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
170  std::string FS =
171  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
172 
173  // This needs to be done before we create a new subtarget since any
174  // creation will depend on the TM and the code generation flags on the
175  // function that reside in TargetOptions.
177 
178  return getSubtargetImpl(CPU, FS);
179 }
180 
181 namespace {
182 
183 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
184  // Take the union of all features used in the module and use it for each
185  // function individually, since having multiple feature sets in one module
186  // currently does not make sense for WebAssembly. If atomics are not enabled,
187  // also strip atomic operations and thread local storage.
188  static char ID;
189  WebAssemblyTargetMachine *WasmTM;
190 
191 public:
192  CoalesceFeaturesAndStripAtomics(WebAssemblyTargetMachine *WasmTM)
193  : ModulePass(ID), WasmTM(WasmTM) {}
194 
195  bool runOnModule(Module &M) override {
196  FeatureBitset Features = coalesceFeatures(M);
197 
198  std::string FeatureStr = getFeatureString(Features);
199  WasmTM->setTargetFeatureString(FeatureStr);
200  for (auto &F : M)
201  replaceFeatures(F, FeatureStr);
202 
203  bool StrippedAtomics = false;
204  bool StrippedTLS = false;
205 
206  if (!Features[WebAssembly::FeatureAtomics]) {
207  StrippedAtomics = stripAtomics(M);
208  StrippedTLS = stripThreadLocals(M);
209  } else if (!Features[WebAssembly::FeatureBulkMemory]) {
210  StrippedTLS |= stripThreadLocals(M);
211  }
212 
213  if (StrippedAtomics && !StrippedTLS)
214  stripThreadLocals(M);
215  else if (StrippedTLS && !StrippedAtomics)
216  stripAtomics(M);
217 
218  recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
219 
220  // Conservatively assume we have made some change
221  return true;
222  }
223 
224 private:
225  FeatureBitset coalesceFeatures(const Module &M) {
226  FeatureBitset Features =
227  WasmTM
228  ->getSubtargetImpl(std::string(WasmTM->getTargetCPU()),
229  std::string(WasmTM->getTargetFeatureString()))
230  ->getFeatureBits();
231  for (auto &F : M)
232  Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
233  return Features;
234  }
235 
236  std::string getFeatureString(const FeatureBitset &Features) {
237  std::string Ret;
238  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
239  if (Features[KV.Value])
240  Ret += (StringRef("+") + KV.Key + ",").str();
241  }
242  return Ret;
243  }
244 
245  void replaceFeatures(Function &F, const std::string &Features) {
246  F.removeFnAttr("target-features");
247  F.removeFnAttr("target-cpu");
248  F.addFnAttr("target-features", Features);
249  }
250 
251  bool stripAtomics(Module &M) {
252  // Detect whether any atomics will be lowered, since there is no way to tell
253  // whether the LowerAtomic pass lowers e.g. stores.
254  bool Stripped = false;
255  for (auto &F : M) {
256  for (auto &B : F) {
257  for (auto &I : B) {
258  if (I.isAtomic()) {
259  Stripped = true;
260  goto done;
261  }
262  }
263  }
264  }
265 
266  done:
267  if (!Stripped)
268  return false;
269 
270  LowerAtomicPass Lowerer;
272  for (auto &F : M)
273  Lowerer.run(F, FAM);
274 
275  return true;
276  }
277 
278  bool stripThreadLocals(Module &M) {
279  bool Stripped = false;
280  for (auto &GV : M.globals()) {
281  if (GV.isThreadLocal()) {
282  Stripped = true;
283  GV.setThreadLocal(false);
284  }
285  }
286  return Stripped;
287  }
288 
289  void recordFeatures(Module &M, const FeatureBitset &Features, bool Stripped) {
290  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
291  if (Features[KV.Value]) {
292  // Mark features as used
293  std::string MDKey = (StringRef("wasm-feature-") + KV.Key).str();
294  M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
296  }
297  }
298  // Code compiled without atomics or bulk-memory may have had its atomics or
299  // thread-local data lowered to nonatomic operations or non-thread-local
300  // data. In that case, we mark the pseudo-feature "shared-mem" as disallowed
301  // to tell the linker that it would be unsafe to allow this code ot be used
302  // in a module with shared memory.
303  if (Stripped) {
304  M.addModuleFlag(Module::ModFlagBehavior::Error, "wasm-feature-shared-mem",
306  }
307  }
308 };
310 
311 /// WebAssembly Code Generator Pass Configuration Options.
312 class WebAssemblyPassConfig final : public TargetPassConfig {
313 public:
314  WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
315  : TargetPassConfig(TM, PM) {}
316 
317  WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
318  return getTM<WebAssemblyTargetMachine>();
319  }
320 
321  FunctionPass *createTargetRegisterAllocator(bool) override;
322 
323  void addIRPasses() override;
324  void addISelPrepare() override;
325  bool addInstSelector() override;
326  void addOptimizedRegAlloc() override;
327  void addPostRegAlloc() override;
328  bool addGCPasses() override { return false; }
329  void addPreEmitPass() override;
330  bool addPreISel() override;
331 
332  // No reg alloc
333  bool addRegAssignAndRewriteFast() override { return false; }
334 
335  // No reg alloc
336  bool addRegAssignAndRewriteOptimized() override { return false; }
337 };
338 } // end anonymous namespace
339 
343 }
344 
347  return new WebAssemblyPassConfig(*this, PM);
348 }
349 
350 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
351  return nullptr; // No reg alloc
352 }
353 
358 
360  // Before checking, we make sure TargetOptions.ExceptionModel is the same as
361  // MCAsmInfo.ExceptionsType. Normally these have to be the same, because clang
362  // stores the exception model info in LangOptions, which is later transferred
363  // to TargetOptions and MCAsmInfo. But when clang compiles bitcode directly,
364  // clang's LangOptions is not used and thus the exception model info is not
365  // correctly transferred to TargetOptions and MCAsmInfo, so we make sure we
366  // have the correct exception model in in WebAssemblyMCAsmInfo constructor.
367  // But in this case TargetOptions is still not updated, so we make sure they
368  // are the same.
369  TM->Options.ExceptionModel = TM->getMCAsmInfo()->getExceptionHandlingType();
370 
371  // Basic Correctness checking related to -exception-model
372  if (TM->Options.ExceptionModel != ExceptionHandling::None &&
373  TM->Options.ExceptionModel != ExceptionHandling::Wasm)
374  report_fatal_error("-exception-model should be either 'none' or 'wasm'");
375  if (WasmEnableEmEH && TM->Options.ExceptionModel == ExceptionHandling::Wasm)
376  report_fatal_error("-exception-model=wasm not allowed with "
377  "-enable-emscripten-cxx-exceptions");
378  if (WasmEnableEH && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
380  "-wasm-enable-eh only allowed with -exception-model=wasm");
381  if (WasmEnableSjLj && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
383  "-wasm-enable-sjlj only allowed with -exception-model=wasm");
384  if ((!WasmEnableEH && !WasmEnableSjLj) &&
385  TM->Options.ExceptionModel == ExceptionHandling::Wasm)
387  "-exception-model=wasm only allowed with at least one of "
388  "-wasm-enable-eh or -wasm-enable-sjj");
389 
390  // You can't enable two modes of EH at the same time
393  "-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-eh");
394  // You can't enable two modes of SjLj at the same time
397  "-enable-emscripten-sjlj not allowed with -wasm-enable-sjlj");
398  // You can't mix Emscripten EH with Wasm SjLj.
401  "-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-sjlj");
402  // Currently it is allowed to mix Wasm EH with Emscripten SjLj as an interim
403  // measure, but some code will error out at compile time in this combination.
404  // See WebAssemblyLowerEmscriptenEHSjLj pass for details.
405 }
406 
407 //===----------------------------------------------------------------------===//
408 // The following functions are called from lib/CodeGen/Passes.cpp to modify
409 // the CodeGen pass sequence.
410 //===----------------------------------------------------------------------===//
411 
412 void WebAssemblyPassConfig::addIRPasses() {
413  // Add signatures to prototype-less function declarations
415 
416  // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
418 
419  // Fix function bitcasts, as WebAssembly requires caller and callee signatures
420  // to match.
422 
423  // Optimize "returned" function attributes.
424  if (getOptLevel() != CodeGenOpt::None)
426 
428 
429  // If exception handling is not enabled and setjmp/longjmp handling is
430  // enabled, we lower invokes into calls and delete unreachable landingpad
431  // blocks. Lowering invokes when there is no EH support is done in
432  // TargetPassConfig::addPassesToHandleExceptions, but that runs after these IR
433  // passes and Emscripten SjLj handling expects all invokes to be lowered
434  // before.
435  if (!WasmEnableEmEH && !WasmEnableEH) {
436  addPass(createLowerInvokePass());
437  // The lower invoke pass may create unreachable code. Remove it in order not
438  // to process dead blocks in setjmp/longjmp handling.
440  }
441 
442  // Handle exceptions and setjmp/longjmp if enabled. Unlike Wasm EH preparation
443  // done in WasmEHPrepare pass, Wasm SjLj preparation shares libraries and
444  // transformation algorithms with Emscripten SjLj, so we run
445  // LowerEmscriptenEHSjLj pass also when Wasm SjLj is enabled.
448 
449  // Expand indirectbr instructions to switches.
450  addPass(createIndirectBrExpandPass());
451 
453 }
454 
455 void WebAssemblyPassConfig::addISelPrepare() {
456  // Lower atomics and TLS if necessary
457  addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
458 
459  // This is a no-op if atomics are not used in the module
460  addPass(createAtomicExpandPass());
461 
463 }
464 
465 bool WebAssemblyPassConfig::addInstSelector() {
467  addPass(
468  createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
469  // Run the argument-move pass immediately after the ScheduleDAG scheduler
470  // so that we can fix up the ARGUMENT instructions before anything else
471  // sees them in the wrong place.
473  // Set the p2align operands. This information is present during ISel, however
474  // it's inconvenient to collect. Collect it now, and update the immediate
475  // operands.
477 
478  // Eliminate range checks and add default targets to br_table instructions.
480 
481  return false;
482 }
483 
484 void WebAssemblyPassConfig::addOptimizedRegAlloc() {
485  // Currently RegisterCoalesce degrades wasm debug info quality by a
486  // significant margin. As a quick fix, disable this for -O1, which is often
487  // used for debugging large applications. Disabling this increases code size
488  // of Emscripten core benchmarks by ~5%, which is acceptable for -O1, which is
489  // usually not used for production builds.
490  // TODO Investigate why RegisterCoalesce degrades debug info quality and fix
491  // it properly
492  if (getOptLevel() == CodeGenOpt::Less)
493  disablePass(&RegisterCoalescerID);
495 }
496 
497 void WebAssemblyPassConfig::addPostRegAlloc() {
498  // TODO: The following CodeGen passes don't currently support code containing
499  // virtual registers. Consider removing their restrictions and re-enabling
500  // them.
501 
502  // These functions all require the NoVRegs property.
503  disablePass(&MachineCopyPropagationID);
504  disablePass(&PostRAMachineSinkingID);
505  disablePass(&PostRASchedulerID);
506  disablePass(&FuncletLayoutID);
507  disablePass(&StackMapLivenessID);
508  disablePass(&LiveDebugValuesID);
509  disablePass(&PatchableFunctionID);
510  disablePass(&ShrinkWrapID);
511 
512  // This pass hurts code size for wasm because it can generate irreducible
513  // control flow.
514  disablePass(&MachineBlockPlacementID);
515 
517 }
518 
519 void WebAssemblyPassConfig::addPreEmitPass() {
521 
522  // Nullify DBG_VALUE_LISTs that we cannot handle.
524 
525  // Eliminate multiple-entry loops.
527 
528  // Do various transformations for exception handling.
529  // Every CFG-changing optimizations should come before this.
530  if (TM->Options.ExceptionModel == ExceptionHandling::Wasm)
532 
533  // Now that we have a prologue and epilogue and all frame indices are
534  // rewritten, eliminate SP and FP. This allows them to be stackified,
535  // colored, and numbered with the rest of the registers.
537 
538  // Preparations and optimizations related to register stackification.
539  if (getOptLevel() != CodeGenOpt::None) {
540  // Depend on LiveIntervals and perform some optimizations on it.
542 
543  // Prepare memory intrinsic calls for register stackifying.
545 
546  // Mark registers as representing wasm's value stack. This is a key
547  // code-compression technique in WebAssembly. We run this pass (and
548  // MemIntrinsicResults above) very late, so that it sees as much code as
549  // possible, including code emitted by PEI and expanded by late tail
550  // duplication.
551  addPass(createWebAssemblyRegStackify());
552 
553  // Run the register coloring pass to reduce the total number of registers.
554  // This runs after stackification so that it doesn't consider registers
555  // that become stackified.
556  addPass(createWebAssemblyRegColoring());
557  }
558 
559  // Sort the blocks of the CFG into topological order, a prerequisite for
560  // BLOCK and LOOP markers.
561  addPass(createWebAssemblyCFGSort());
562 
563  // Insert BLOCK and LOOP markers.
564  addPass(createWebAssemblyCFGStackify());
565 
566  // Insert explicit local.get and local.set operators.
569 
570  // Lower br_unless into br_if.
572 
573  // Perform the very last peephole optimizations on the code.
574  if (getOptLevel() != CodeGenOpt::None)
575  addPass(createWebAssemblyPeephole());
576 
577  // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
579 
580  // Fix debug_values whose defs have been stackified.
582  addPass(createWebAssemblyDebugFixup());
583 
584  // Collect information to prepare for MC lowering / asm printing.
586 }
587 
588 bool WebAssemblyPassConfig::addPreISel() {
591  return false;
592 }
593 
596  return new yaml::WebAssemblyFunctionInfo();
597 }
598 
600  const MachineFunction &MF) const {
601  const auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
602  return new yaml::WebAssemblyFunctionInfo(MF, *MFI);
603 }
604 
607  SMDiagnostic &Error, SMRange &SourceRange) const {
608  const auto &YamlMFI = static_cast<const yaml::WebAssemblyFunctionInfo &>(MFI);
609  MachineFunction &MF = PFS.MF;
610  MF.getInfo<WebAssemblyFunctionInfo>()->initializeBaseYamlFields(MF, YamlMFI);
611  return false;
612 }
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Definition: TargetTransformInfo.h:172
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Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
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llvm::initializeWebAssemblyCFGSortPass
void initializeWebAssemblyCFGSortPass(PassRegistry &)
LLVMInitializeWebAssemblyTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeWebAssemblyTarget()
Definition: WebAssemblyTargetMachine.cpp:49
llvm::createWebAssemblyFixIrreducibleControlFlow
FunctionPass * createWebAssemblyFixIrreducibleControlFlow()
llvm::TargetPassConfig::addInstSelector
virtual bool addInstSelector()
addInstSelector - This method should install an instruction selector pass, which converts from LLVM c...
Definition: TargetPassConfig.h:239
llvm::createWebAssemblyFixBrTableDefaults
FunctionPass * createWebAssemblyFixBrTableDefaults()
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:95
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::wasm::WASM_FEATURE_PREFIX_USED
@ WASM_FEATURE_PREFIX_USED
Definition: Wasm.h:344
llvm::TargetOptions::UniqueSectionNames
unsigned UniqueSectionNames
Definition: TargetOptions.h:274
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::WebAssemblyTargetMachine
Definition: WebAssemblyTargetMachine.h:23
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::WebAssembly::WasmEnableEmSjLj
cl::opt< bool > WasmEnableEmSjLj
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:405
llvm::createWebAssemblyRegStackify
FunctionPass * createWebAssemblyRegStackify()
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1356
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::initializeWebAssemblyAddMissingPrototypesPass
void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &)
llvm::initializeWebAssemblyOptimizeLiveIntervalsPass
void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &)
llvm::createWebAssemblyLowerEmscriptenEHSjLj
ModulePass * createWebAssemblyLowerEmscriptenEHSjLj()
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createWebAssemblyOptimizeLiveIntervals
FunctionPass * createWebAssemblyOptimizeLiveIntervals()
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::initializeWebAssemblyExceptionInfoPass
void initializeWebAssemblyExceptionInfoPass(PassRegistry &)
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:35
Utils.h
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
WebAssemblyUtilities.h
WebAssemblyMCTargetDesc.h
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::WebAssemblyTargetMachine::getSubtargetImpl
const WebAssemblySubtarget * getSubtargetImpl() const
Definition: WebAssemblyTargetMachine.cpp:148
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::WebAssemblyTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: WebAssemblyTargetMachine.cpp:595
llvm::createWebAssemblyMCLowerPrePass
ModulePass * createWebAssemblyMCLowerPrePass()
llvm::initializeWebAssemblyFixIrreducibleControlFlowPass
void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &)
llvm::createWebAssemblyDebugFixup
FunctionPass * createWebAssemblyDebugFixup()
llvm::initializeWebAssemblyMCLowerPrePassPass
void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &)
llvm::initializeWebAssemblyRegNumberingPass
void initializeWebAssemblyRegNumberingPass(PassRegistry &)
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
WasmDisableExplicitLocals
static cl::opt< bool > WasmDisableExplicitLocals("wasm-disable-explicit-locals", cl::Hidden, cl::desc("WebAssembly: output implicit locals in" " instruction output for test purposes only."), cl::init(false))
I
#define I(x, y, z)
Definition: MD5.cpp:58
WebAssemblyTargetObjectFile.h
WebAssemblyTargetInfo.h
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::TargetPassConfig::addOptimizedRegAlloc
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
Definition: TargetPassConfig.cpp:1461
llvm::initializeWebAssemblyLowerBrUnlessPass
void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &)
llvm::createWebAssemblyNullifyDebugValueLists
FunctionPass * createWebAssemblyNullifyDebugValueLists()
llvm::createWebAssemblyMemIntrinsicResults
FunctionPass * createWebAssemblyMemIntrinsicResults()
llvm::WebAssembly::WasmEnableSjLj
cl::opt< bool > WasmEnableSjLj
TargetPassConfig.h
MachineFunctionPass.h
llvm::createWebAssemblyOptimizeReturned
FunctionPass * createWebAssemblyOptimizeReturned()
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
LowerAtomicPass.h
llvm::WebAssemblyFunctionInfo
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Definition: WebAssemblyMachineFunctionInfo.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::WebAssemblyTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: WebAssemblyTargetMachine.cpp:605
llvm::TargetMachine::setTargetFeatureString
void setTargetFeatureString(StringRef FS)
Definition: TargetMachine.h:129
llvm::createWebAssemblyAddMissingPrototypes
ModulePass * createWebAssemblyAddMissingPrototypes()
WebAssemblyMachineFunctionInfo.h
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
basicCheckForEHAndSjLj
static void basicCheckForEHAndSjLj(TargetMachine *TM)
Definition: WebAssemblyTargetMachine.cpp:359
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::initializeWebAssemblyExplicitLocalsPass
void initializeWebAssemblyExplicitLocalsPass(PassRegistry &)
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:128
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:622
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:77
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::createWebAssemblyLowerRefTypesIntPtrConv
FunctionPass * createWebAssemblyLowerRefTypesIntPtrConv()
llvm::WebAssemblyTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: WebAssemblyTargetMachine.cpp:341
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::WebAssembly::WasmEnableEH
cl::opt< bool > WasmEnableEH
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:506
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::getTheWebAssemblyTarget64
Target & getTheWebAssemblyTarget64()
Definition: WebAssemblyTargetInfo.cpp:24
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::createWebAssemblyCFGSort
FunctionPass * createWebAssemblyCFGSort()
llvm::initializeWebAssemblyRegColoringPass
void initializeWebAssemblyRegColoringPass(PassRegistry &)
llvm::LowerAtomicPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &)
Definition: LowerAtomicPass.cpp:68
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::initializeWebAssemblyDebugFixupPass
void initializeWebAssemblyDebugFixupPass(PassRegistry &)
Function.h
llvm::initializeWebAssemblyArgumentMovePass
void initializeWebAssemblyArgumentMovePass(PassRegistry &)
llvm::TargetOptions::DataSections
unsigned DataSections
Emit data into separate sections.
Definition: TargetOptions.h:266
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::initializeWebAssemblyLateEHPreparePass
void initializeWebAssemblyLateEHPreparePass(PassRegistry &)
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::createWebAssemblyArgumentMove
FunctionPass * createWebAssemblyArgumentMove()
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:1002
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:127
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::createWebAssemblyFixFunctionBitcasts
ModulePass * createWebAssemblyFixFunctionBitcasts()
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::initializeWebAssemblyNullifyDebugValueListsPass
void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &)
llvm::createWebAssemblySetP2AlignOperands
FunctionPass * createWebAssemblySetP2AlignOperands()
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:360
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::initializeWebAssemblyPeepholePass
void initializeWebAssemblyPeepholePass(PassRegistry &)
llvm::createWebAssemblyLowerBrUnless
FunctionPass * createWebAssemblyLowerBrUnless()
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::TargetOptions::FunctionSections
unsigned FunctionSections
Emit functions into separate sections.
Definition: TargetOptions.h:263
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1622
llvm::cl::desc
Definition: CommandLine.h:413
llvm::createWebAssemblyRegNumbering
FunctionPass * createWebAssemblyRegNumbering()
llvm::createWebAssemblyLateEHPrepare
FunctionPass * createWebAssemblyLateEHPrepare()
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:439
llvm::CodeGenOpt::Less
@ Less
Definition: CodeGen.h:54
llvm::WebAssemblyTTIImpl
Definition: WebAssemblyTargetTransformInfo.h:28
TargetRegistry.h
InitializePasses.h
llvm::initializeOptimizeReturnedPass
void initializeOptimizeReturnedPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::initializeWebAssemblyReplacePhysRegsPass
void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &)
llvm::yaml::WebAssemblyFunctionInfo
Definition: WebAssemblyMachineFunctionInfo.h:189
llvm::initializeWebAssemblyMemIntrinsicResultsPass
void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &)
llvm::createWebAssemblyPeephole
FunctionPass * createWebAssemblyPeephole()
llvm::initializeFixFunctionBitcastsPass
void initializeFixFunctionBitcastsPass(PassRegistry &)
llvm::WebAssembly::WasmEnableEmEH
cl::opt< bool > WasmEnableEmEH
RegAllocRegistry.h
MIParser.h
llvm::WebAssemblyTargetMachine::WebAssemblyTargetMachine
WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an WebAssembly architecture model.
Definition: WebAssemblyTargetMachine.cpp:109