LLVM  15.0.0git
WebAssemblyTargetMachine.cpp
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1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the WebAssembly-specific subclass of TargetMachine.
11 ///
12 //===----------------------------------------------------------------------===//
13 
18 #include "WebAssembly.h"
24 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/InitializePasses.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/TargetRegistry.h"
32 #include "llvm/Transforms/Scalar.h"
34 #include "llvm/Transforms/Utils.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "wasm"
38 
39 // A command-line option to keep implicit locals
40 // for the purpose of testing with lit/llc ONLY.
41 // This produces output which is not valid WebAssembly, and is not supported
42 // by assemblers/disassemblers and other MC based tools.
44  "wasm-disable-explicit-locals", cl::Hidden,
45  cl::desc("WebAssembly: output implicit locals in"
46  " instruction output for test purposes only."),
47  cl::init(false));
48 
50  // Register the target.
55 
56  // Register backend passes
57  auto &PR = *PassRegistry::getPassRegistry();
83 }
84 
85 //===----------------------------------------------------------------------===//
86 // WebAssembly Lowering public interface.
87 //===----------------------------------------------------------------------===//
88 
90  const Triple &TT) {
91  if (!RM.hasValue()) {
92  // Default to static relocation model. This should always be more optimial
93  // than PIC since the static linker can determine all global addresses and
94  // assume direct function calls.
95  return Reloc::Static;
96  }
97 
98  if (!TT.isOSEmscripten()) {
99  // Relocation modes other than static are currently implemented in a way
100  // that only works for Emscripten, so disable them if we aren't targeting
101  // Emscripten.
102  return Reloc::Static;
103  }
104 
105  return *RM;
106 }
107 
108 /// Create an WebAssembly architecture model.
109 ///
111  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
115  T,
116  TT.isArch64Bit()
117  ? (TT.isOSEmscripten() ? "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
118  "f128:64-n32:64-S128-ni:1:10:20"
119  : "e-m:e-p:64:64-p10:8:8-p20:8:8-i64:64-"
120  "n32:64-S128-ni:1:10:20")
121  : (TT.isOSEmscripten() ? "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
122  "f128:64-n32:64-S128-ni:1:10:20"
123  : "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-"
124  "n32:64-S128-ni:1:10:20"),
125  TT, CPU, FS, Options, getEffectiveRelocModel(RM, TT),
128  // WebAssembly type-checks instructions, but a noreturn function with a return
129  // type that doesn't match the context will cause a check failure. So we lower
130  // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's
131  // 'unreachable' instructions which is meant for that case.
132  this->Options.TrapUnreachable = true;
133 
134  // WebAssembly treats each function as an independent unit. Force
135  // -ffunction-sections, effectively, so that we can emit them independently.
136  this->Options.FunctionSections = true;
137  this->Options.DataSections = true;
138  this->Options.UniqueSectionNames = true;
139 
140  initAsmInfo();
141 
142  // Note that we don't use setRequiresStructuredCFG(true). It disables
143  // optimizations than we're ok with, and want, such as critical edge
144  // splitting and tail merging.
145 }
146 
148 
150  return getSubtargetImpl(std::string(getTargetCPU()),
151  std::string(getTargetFeatureString()));
152 }
153 
154 const WebAssemblySubtarget *
156  std::string FS) const {
157  auto &I = SubtargetMap[CPU + FS];
158  if (!I) {
159  I = std::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this);
160  }
161  return I.get();
162 }
163 
164 const WebAssemblySubtarget *
166  Attribute CPUAttr = F.getFnAttribute("target-cpu");
167  Attribute FSAttr = F.getFnAttribute("target-features");
168 
169  std::string CPU =
170  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
171  std::string FS =
172  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
173 
174  // This needs to be done before we create a new subtarget since any
175  // creation will depend on the TM and the code generation flags on the
176  // function that reside in TargetOptions.
178 
179  return getSubtargetImpl(CPU, FS);
180 }
181 
182 namespace {
183 
184 class CoalesceFeaturesAndStripAtomics final : public ModulePass {
185  // Take the union of all features used in the module and use it for each
186  // function individually, since having multiple feature sets in one module
187  // currently does not make sense for WebAssembly. If atomics are not enabled,
188  // also strip atomic operations and thread local storage.
189  static char ID;
190  WebAssemblyTargetMachine *WasmTM;
191 
192 public:
193  CoalesceFeaturesAndStripAtomics(WebAssemblyTargetMachine *WasmTM)
194  : ModulePass(ID), WasmTM(WasmTM) {}
195 
196  bool runOnModule(Module &M) override {
197  FeatureBitset Features = coalesceFeatures(M);
198 
199  std::string FeatureStr = getFeatureString(Features);
200  WasmTM->setTargetFeatureString(FeatureStr);
201  for (auto &F : M)
202  replaceFeatures(F, FeatureStr);
203 
204  bool StrippedAtomics = false;
205  bool StrippedTLS = false;
206 
207  if (!Features[WebAssembly::FeatureAtomics])
208  StrippedAtomics = stripAtomics(M);
209 
210  if (!Features[WebAssembly::FeatureBulkMemory])
211  StrippedTLS = stripThreadLocals(M);
212 
213  if (StrippedAtomics && !StrippedTLS)
214  stripThreadLocals(M);
215  else if (StrippedTLS && !StrippedAtomics)
216  stripAtomics(M);
217 
218  recordFeatures(M, Features, StrippedAtomics || StrippedTLS);
219 
220  // Conservatively assume we have made some change
221  return true;
222  }
223 
224 private:
225  FeatureBitset coalesceFeatures(const Module &M) {
226  FeatureBitset Features =
227  WasmTM
228  ->getSubtargetImpl(std::string(WasmTM->getTargetCPU()),
229  std::string(WasmTM->getTargetFeatureString()))
230  ->getFeatureBits();
231  for (auto &F : M)
232  Features |= WasmTM->getSubtargetImpl(F)->getFeatureBits();
233  return Features;
234  }
235 
236  std::string getFeatureString(const FeatureBitset &Features) {
237  std::string Ret;
238  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
239  if (Features[KV.Value])
240  Ret += (StringRef("+") + KV.Key + ",").str();
241  }
242  return Ret;
243  }
244 
245  void replaceFeatures(Function &F, const std::string &Features) {
246  F.removeFnAttr("target-features");
247  F.removeFnAttr("target-cpu");
248  F.addFnAttr("target-features", Features);
249  }
250 
251  bool stripAtomics(Module &M) {
252  // Detect whether any atomics will be lowered, since there is no way to tell
253  // whether the LowerAtomic pass lowers e.g. stores.
254  bool Stripped = false;
255  for (auto &F : M) {
256  for (auto &B : F) {
257  for (auto &I : B) {
258  if (I.isAtomic()) {
259  Stripped = true;
260  goto done;
261  }
262  }
263  }
264  }
265 
266  done:
267  if (!Stripped)
268  return false;
269 
270  LowerAtomicPass Lowerer;
272  for (auto &F : M)
273  Lowerer.run(F, FAM);
274 
275  return true;
276  }
277 
278  bool stripThreadLocals(Module &M) {
279  bool Stripped = false;
280  for (auto &GV : M.globals()) {
281  if (GV.isThreadLocal()) {
282  Stripped = true;
283  GV.setThreadLocal(false);
284  }
285  }
286  return Stripped;
287  }
288 
289  void recordFeatures(Module &M, const FeatureBitset &Features, bool Stripped) {
290  for (const SubtargetFeatureKV &KV : WebAssemblyFeatureKV) {
291  if (Features[KV.Value]) {
292  // Mark features as used
293  std::string MDKey = (StringRef("wasm-feature-") + KV.Key).str();
294  M.addModuleFlag(Module::ModFlagBehavior::Error, MDKey,
296  }
297  }
298  // Code compiled without atomics or bulk-memory may have had its atomics or
299  // thread-local data lowered to nonatomic operations or non-thread-local
300  // data. In that case, we mark the pseudo-feature "shared-mem" as disallowed
301  // to tell the linker that it would be unsafe to allow this code ot be used
302  // in a module with shared memory.
303  if (Stripped) {
304  M.addModuleFlag(Module::ModFlagBehavior::Error, "wasm-feature-shared-mem",
306  }
307  }
308 };
310 
311 /// WebAssembly Code Generator Pass Configuration Options.
312 class WebAssemblyPassConfig final : public TargetPassConfig {
313 public:
314  WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
315  : TargetPassConfig(TM, PM) {}
316 
317  WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
318  return getTM<WebAssemblyTargetMachine>();
319  }
320 
321  FunctionPass *createTargetRegisterAllocator(bool) override;
322 
323  void addIRPasses() override;
324  void addISelPrepare() override;
325  bool addInstSelector() override;
326  void addPostRegAlloc() override;
327  bool addGCPasses() override { return false; }
328  void addPreEmitPass() override;
329  bool addPreISel() override;
330 
331  // No reg alloc
332  bool addRegAssignAndRewriteFast() override { return false; }
333 
334  // No reg alloc
335  bool addRegAssignAndRewriteOptimized() override { return false; }
336 };
337 } // end anonymous namespace
338 
342 }
343 
346  return new WebAssemblyPassConfig(*this, PM);
347 }
348 
349 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
350  return nullptr; // No reg alloc
351 }
352 
357 
359  // Before checking, we make sure TargetOptions.ExceptionModel is the same as
360  // MCAsmInfo.ExceptionsType. Normally these have to be the same, because clang
361  // stores the exception model info in LangOptions, which is later transferred
362  // to TargetOptions and MCAsmInfo. But when clang compiles bitcode directly,
363  // clang's LangOptions is not used and thus the exception model info is not
364  // correctly transferred to TargetOptions and MCAsmInfo, so we make sure we
365  // have the correct exception model in in WebAssemblyMCAsmInfo constructor.
366  // But in this case TargetOptions is still not updated, so we make sure they
367  // are the same.
368  TM->Options.ExceptionModel = TM->getMCAsmInfo()->getExceptionHandlingType();
369 
370  // Basic Correctness checking related to -exception-model
371  if (TM->Options.ExceptionModel != ExceptionHandling::None &&
372  TM->Options.ExceptionModel != ExceptionHandling::Wasm)
373  report_fatal_error("-exception-model should be either 'none' or 'wasm'");
374  if (WasmEnableEmEH && TM->Options.ExceptionModel == ExceptionHandling::Wasm)
375  report_fatal_error("-exception-model=wasm not allowed with "
376  "-enable-emscripten-cxx-exceptions");
377  if (WasmEnableEH && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
379  "-wasm-enable-eh only allowed with -exception-model=wasm");
380  if (WasmEnableSjLj && TM->Options.ExceptionModel != ExceptionHandling::Wasm)
382  "-wasm-enable-sjlj only allowed with -exception-model=wasm");
383  if ((!WasmEnableEH && !WasmEnableSjLj) &&
384  TM->Options.ExceptionModel == ExceptionHandling::Wasm)
386  "-exception-model=wasm only allowed with at least one of "
387  "-wasm-enable-eh or -wasm-enable-sjj");
388 
389  // You can't enable two modes of EH at the same time
392  "-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-eh");
393  // You can't enable two modes of SjLj at the same time
396  "-enable-emscripten-sjlj not allowed with -wasm-enable-sjlj");
397  // You can't mix Emscripten EH with Wasm SjLj.
400  "-enable-emscripten-cxx-exceptions not allowed with -wasm-enable-sjlj");
401  // Currently it is allowed to mix Wasm EH with Emscripten SjLj as an interim
402  // measure, but some code will error out at compile time in this combination.
403  // See WebAssemblyLowerEmscriptenEHSjLj pass for details.
404 }
405 
406 //===----------------------------------------------------------------------===//
407 // The following functions are called from lib/CodeGen/Passes.cpp to modify
408 // the CodeGen pass sequence.
409 //===----------------------------------------------------------------------===//
410 
411 void WebAssemblyPassConfig::addIRPasses() {
412  // Add signatures to prototype-less function declarations
414 
415  // Lower .llvm.global_dtors into .llvm_global_ctors with __cxa_atexit calls.
417 
418  // Fix function bitcasts, as WebAssembly requires caller and callee signatures
419  // to match.
421 
422  // Optimize "returned" function attributes.
423  if (getOptLevel() != CodeGenOpt::None)
425 
427 
428  // If exception handling is not enabled and setjmp/longjmp handling is
429  // enabled, we lower invokes into calls and delete unreachable landingpad
430  // blocks. Lowering invokes when there is no EH support is done in
431  // TargetPassConfig::addPassesToHandleExceptions, but that runs after these IR
432  // passes and Emscripten SjLj handling expects all invokes to be lowered
433  // before.
434  if (!WasmEnableEmEH && !WasmEnableEH) {
435  addPass(createLowerInvokePass());
436  // The lower invoke pass may create unreachable code. Remove it in order not
437  // to process dead blocks in setjmp/longjmp handling.
439  }
440 
441  // Handle exceptions and setjmp/longjmp if enabled. Unlike Wasm EH preparation
442  // done in WasmEHPrepare pass, Wasm SjLj preparation shares libraries and
443  // transformation algorithms with Emscripten SjLj, so we run
444  // LowerEmscriptenEHSjLj pass also when Wasm SjLj is enabled.
447 
448  // Expand indirectbr instructions to switches.
449  addPass(createIndirectBrExpandPass());
450 
452 }
453 
454 void WebAssemblyPassConfig::addISelPrepare() {
455  // Lower atomics and TLS if necessary
456  addPass(new CoalesceFeaturesAndStripAtomics(&getWebAssemblyTargetMachine()));
457 
458  // This is a no-op if atomics are not used in the module
459  addPass(createAtomicExpandPass());
460 
462 }
463 
464 bool WebAssemblyPassConfig::addInstSelector() {
466  addPass(
467  createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel()));
468  // Run the argument-move pass immediately after the ScheduleDAG scheduler
469  // so that we can fix up the ARGUMENT instructions before anything else
470  // sees them in the wrong place.
472  // Set the p2align operands. This information is present during ISel, however
473  // it's inconvenient to collect. Collect it now, and update the immediate
474  // operands.
476 
477  // Eliminate range checks and add default targets to br_table instructions.
479 
480  return false;
481 }
482 
483 void WebAssemblyPassConfig::addPostRegAlloc() {
484  // TODO: The following CodeGen passes don't currently support code containing
485  // virtual registers. Consider removing their restrictions and re-enabling
486  // them.
487 
488  // These functions all require the NoVRegs property.
489  disablePass(&MachineCopyPropagationID);
490  disablePass(&PostRAMachineSinkingID);
491  disablePass(&PostRASchedulerID);
492  disablePass(&FuncletLayoutID);
493  disablePass(&StackMapLivenessID);
494  disablePass(&LiveDebugValuesID);
495  disablePass(&PatchableFunctionID);
496  disablePass(&ShrinkWrapID);
497 
498  // This pass hurts code size for wasm because it can generate irreducible
499  // control flow.
500  disablePass(&MachineBlockPlacementID);
501 
503 }
504 
505 void WebAssemblyPassConfig::addPreEmitPass() {
507 
508  // Nullify DBG_VALUE_LISTs that we cannot handle.
510 
511  // Eliminate multiple-entry loops.
513 
514  // Do various transformations for exception handling.
515  // Every CFG-changing optimizations should come before this.
516  if (TM->Options.ExceptionModel == ExceptionHandling::Wasm)
518 
519  // Now that we have a prologue and epilogue and all frame indices are
520  // rewritten, eliminate SP and FP. This allows them to be stackified,
521  // colored, and numbered with the rest of the registers.
523 
524  // Preparations and optimizations related to register stackification.
525  if (getOptLevel() != CodeGenOpt::None) {
526  // LiveIntervals isn't commonly run this late. Re-establish preconditions.
528 
529  // Depend on LiveIntervals and perform some optimizations on it.
531 
532  // Prepare memory intrinsic calls for register stackifying.
534 
535  // Mark registers as representing wasm's value stack. This is a key
536  // code-compression technique in WebAssembly. We run this pass (and
537  // MemIntrinsicResults above) very late, so that it sees as much code as
538  // possible, including code emitted by PEI and expanded by late tail
539  // duplication.
540  addPass(createWebAssemblyRegStackify());
541 
542  // Run the register coloring pass to reduce the total number of registers.
543  // This runs after stackification so that it doesn't consider registers
544  // that become stackified.
545  addPass(createWebAssemblyRegColoring());
546  }
547 
548  // Sort the blocks of the CFG into topological order, a prerequisite for
549  // BLOCK and LOOP markers.
550  addPass(createWebAssemblyCFGSort());
551 
552  // Insert BLOCK and LOOP markers.
553  addPass(createWebAssemblyCFGStackify());
554 
555  // Insert explicit local.get and local.set operators.
558 
559  // Lower br_unless into br_if.
561 
562  // Perform the very last peephole optimizations on the code.
563  if (getOptLevel() != CodeGenOpt::None)
564  addPass(createWebAssemblyPeephole());
565 
566  // Create a mapping from LLVM CodeGen virtual registers to wasm registers.
568 
569  // Fix debug_values whose defs have been stackified.
571  addPass(createWebAssemblyDebugFixup());
572 
573  // Collect information to prepare for MC lowering / asm printing.
575 }
576 
577 bool WebAssemblyPassConfig::addPreISel() {
580  return false;
581 }
582 
585  return new yaml::WebAssemblyFunctionInfo();
586 }
587 
589  const MachineFunction &MF) const {
590  const auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
591  return new yaml::WebAssemblyFunctionInfo(*MFI);
592 }
593 
596  SMDiagnostic &Error, SMRange &SourceRange) const {
597  const auto &YamlMFI = static_cast<const yaml::WebAssemblyFunctionInfo &>(MFI);
598  MachineFunction &MF = PFS.MF;
599  MF.getInfo<WebAssemblyFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
600  return false;
601 }
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Definition: Wasm.h:342
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virtual void addPostRegAlloc()
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Definition: TargetPassConfig.h:417
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Definition: Wasm.h:344
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Definition: LowerInvoke.cpp:85
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Definition: AddressRanges.h:17
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Definition: Attributes.h:169
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We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
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Definition: LowerAtomicPass.h:22
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Definition: TargetOptions.h:124
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Definition: TargetRegistry.h:140
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Definition: TargetTransformInfo.h:167
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This pass converts a legalized DAG into a WebAssembly-specific DAG, ready for instruction scheduling.
Definition: WebAssemblyISelDAGToDAG.cpp:286
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Definition: Triple.h:44
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Definition: PassBuilderBindings.cpp:59
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Definition: CommandLine.h:139
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Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
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Definition: SubtargetFeature.h:40
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Definition: MipsISelLowering.h:119
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Definition: WebAssemblyTargetMachine.cpp:345
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Definition: MachineCopyPropagation.cpp:307
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Definition: WebAssemblyTargetObjectFile.h:22
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new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
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Definition: MD5.cpp:55
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Definition: WebAssemblyTargetMachine.cpp:588
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Definition: WebAssemblyTargetMachine.cpp:49
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Definition: TargetPassConfig.h:239
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Definition: LiveDebugValues.cpp:95
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CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::TargetOptions::UniqueSectionNames
unsigned UniqueSectionNames
Definition: TargetOptions.h:274
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::WebAssemblyTargetMachine
Definition: WebAssemblyTargetMachine.h:23
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::WebAssembly::WasmEnableEmSjLj
cl::opt< bool > WasmEnableEmSjLj
llvm::createWebAssemblyRegStackify
FunctionPass * createWebAssemblyRegStackify()
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1296
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::ExceptionHandling::Wasm
@ Wasm
WebAssembly Exception Handling.
llvm::initializeWebAssemblyAddMissingPrototypesPass
void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &)
llvm::initializeWebAssemblyOptimizeLiveIntervalsPass
void initializeWebAssemblyOptimizeLiveIntervalsPass(PassRegistry &)
llvm::createWebAssemblyLowerEmscriptenEHSjLj
ModulePass * createWebAssemblyLowerEmscriptenEHSjLj()
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createWebAssemblyOptimizeLiveIntervals
FunctionPass * createWebAssemblyOptimizeLiveIntervals()
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::initializeWebAssemblyExceptionInfoPass
void initializeWebAssemblyExceptionInfoPass(PassRegistry &)
llvm::SubtargetFeatureKV
Used to provide key value pairs for feature and CPU bit flags.
Definition: MCSubtargetInfo.h:35
Utils.h
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:305
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
WebAssemblyUtilities.h
WebAssemblyMCTargetDesc.h
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::WebAssemblyTargetMachine::getSubtargetImpl
const WebAssemblySubtarget * getSubtargetImpl() const
Definition: WebAssemblyTargetMachine.cpp:149
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::WebAssemblyTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: WebAssemblyTargetMachine.cpp:584
llvm::createWebAssemblyMCLowerPrePass
ModulePass * createWebAssemblyMCLowerPrePass()
llvm::initializeWebAssemblyFixIrreducibleControlFlowPass
void initializeWebAssemblyFixIrreducibleControlFlowPass(PassRegistry &)
llvm::createWebAssemblyDebugFixup
FunctionPass * createWebAssemblyDebugFixup()
llvm::initializeWebAssemblyMCLowerPrePassPass
void initializeWebAssemblyMCLowerPrePassPass(PassRegistry &)
llvm::initializeWebAssemblyRegNumberingPass
void initializeWebAssemblyRegNumberingPass(PassRegistry &)
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
WasmDisableExplicitLocals
static cl::opt< bool > WasmDisableExplicitLocals("wasm-disable-explicit-locals", cl::Hidden, cl::desc("WebAssembly: output implicit locals in" " instruction output for test purposes only."), cl::init(false))
I
#define I(x, y, z)
Definition: MD5.cpp:58
WebAssemblyTargetObjectFile.h
WebAssemblyTargetInfo.h
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:848
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::initializeWebAssemblyLowerBrUnlessPass
void initializeWebAssemblyLowerBrUnlessPass(PassRegistry &)
llvm::createWebAssemblyNullifyDebugValueLists
FunctionPass * createWebAssemblyNullifyDebugValueLists()
llvm::createWebAssemblyMemIntrinsicResults
FunctionPass * createWebAssemblyMemIntrinsicResults()
llvm::WebAssembly::WasmEnableSjLj
cl::opt< bool > WasmEnableSjLj
TargetPassConfig.h
MachineFunctionPass.h
llvm::createWebAssemblyOptimizeReturned
FunctionPass * createWebAssemblyOptimizeReturned()
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
LowerAtomicPass.h
llvm::WebAssemblyFunctionInfo
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
Definition: WebAssemblyMachineFunctionInfo.h:33
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::WebAssemblyTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: WebAssemblyTargetMachine.cpp:594
llvm::initializeWebAssemblyPrepareForLiveIntervalsPass
void initializeWebAssemblyPrepareForLiveIntervalsPass(PassRegistry &)
llvm::TargetMachine::setTargetFeatureString
void setTargetFeatureString(StringRef FS)
Definition: TargetMachine.h:129
llvm::createWebAssemblyAddMissingPrototypes
ModulePass * createWebAssemblyAddMissingPrototypes()
WebAssemblyMachineFunctionInfo.h
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
basicCheckForEHAndSjLj
static void basicCheckForEHAndSjLj(TargetMachine *TM)
Definition: WebAssemblyTargetMachine.cpp:358
llvm::createWebAssemblyPrepareForLiveIntervals
FunctionPass * createWebAssemblyPrepareForLiveIntervals()
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::initializeWebAssemblyExplicitLocalsPass
void initializeWebAssemblyExplicitLocalsPass(PassRegistry &)
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:128
llvm::MachineBlockPlacementID
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
Definition: MachineBlockPlacement.cpp:609
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:77
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::WebAssemblySubtarget
Definition: WebAssemblySubtarget.h:35
llvm::createWebAssemblyLowerRefTypesIntPtrConv
FunctionPass * createWebAssemblyLowerRefTypesIntPtrConv()
llvm::WebAssemblyTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: WebAssemblyTargetMachine.cpp:340
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::WebAssembly::WasmEnableEH
cl::opt< bool > WasmEnableEH
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:497
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::getTheWebAssemblyTarget64
Target & getTheWebAssemblyTarget64()
Definition: WebAssemblyTargetInfo.cpp:24
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::createWebAssemblyCFGSort
FunctionPass * createWebAssemblyCFGSort()
llvm::initializeWebAssemblyRegColoringPass
void initializeWebAssemblyRegColoringPass(PassRegistry &)
llvm::LowerAtomicPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &)
Definition: LowerAtomicPass.cpp:68
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::initializeWebAssemblyDebugFixupPass
void initializeWebAssemblyDebugFixupPass(PassRegistry &)
Function.h
llvm::initializeWebAssemblyArgumentMovePass
void initializeWebAssemblyArgumentMovePass(PassRegistry &)
llvm::TargetOptions::DataSections
unsigned DataSections
Emit data into separate sections.
Definition: TargetOptions.h:266
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:405
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::initializeWebAssemblyLateEHPreparePass
void initializeWebAssemblyLateEHPreparePass(PassRegistry &)
llvm::ExceptionHandling::None
@ None
No exception support.
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::createWebAssemblyArgumentMove
FunctionPass * createWebAssemblyArgumentMove()
llvm::TargetPassConfig::addISelPrepare
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Definition: TargetPassConfig.cpp:993
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:127
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
llvm::createWebAssemblyFixFunctionBitcasts
ModulePass * createWebAssemblyFixFunctionBitcasts()
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::initializeWebAssemblyNullifyDebugValueListsPass
void initializeWebAssemblyNullifyDebugValueListsPass(PassRegistry &)
llvm::createWebAssemblySetP2AlignOperands
FunctionPass * createWebAssemblySetP2AlignOperands()
llvm::TargetPassConfig::addPreISel
virtual bool addPreISel()
Methods with trivial inline returns are convenient points in the common codegen pass pipeline where t...
Definition: TargetPassConfig.h:357
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::initializeWebAssemblyPeepholePass
void initializeWebAssemblyPeepholePass(PassRegistry &)
llvm::createWebAssemblyLowerBrUnless
FunctionPass * createWebAssemblyLowerBrUnless()
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::TargetOptions::FunctionSections
unsigned FunctionSections
Emit functions into separate sections.
Definition: TargetOptions.h:263
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1612
llvm::cl::desc
Definition: CommandLine.h:405
llvm::createWebAssemblyRegNumbering
FunctionPass * createWebAssemblyRegNumbering()
llvm::createWebAssemblyLateEHPrepare
FunctionPass * createWebAssemblyLateEHPrepare()
llvm::TargetPassConfig::addPreEmitPass
virtual void addPreEmitPass()
This pass may be implemented by targets that want to run passes immediately before machine code is em...
Definition: TargetPassConfig.h:436
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::WebAssemblyTTIImpl
Definition: WebAssemblyTargetTransformInfo.h:28
TargetRegistry.h
InitializePasses.h
llvm::initializeOptimizeReturnedPass
void initializeOptimizeReturnedPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::initializeWebAssemblyReplacePhysRegsPass
void initializeWebAssemblyReplacePhysRegsPass(PassRegistry &)
llvm::yaml::WebAssemblyFunctionInfo
Definition: WebAssemblyMachineFunctionInfo.h:194
llvm::initializeWebAssemblyMemIntrinsicResultsPass
void initializeWebAssemblyMemIntrinsicResultsPass(PassRegistry &)
llvm::createWebAssemblyPeephole
FunctionPass * createWebAssemblyPeephole()
llvm::initializeFixFunctionBitcastsPass
void initializeFixFunctionBitcastsPass(PassRegistry &)
llvm::WebAssembly::WasmEnableEmEH
cl::opt< bool > WasmEnableEmEH
RegAllocRegistry.h
MIParser.h
llvm::WebAssemblyTargetMachine::WebAssemblyTargetMachine
WebAssemblyTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an WebAssembly architecture model.
Definition: WebAssemblyTargetMachine.cpp:110
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37