63#define DEBUG_TYPE "regalloc"
65STATISTIC(numJoins ,
"Number of interval joins performed");
66STATISTIC(numCrossRCs ,
"Number of cross class joins performed");
67STATISTIC(numCommutes ,
"Number of instruction commuting performed");
69STATISTIC(NumReMats ,
"Number of instructions re-materialized");
70STATISTIC(NumInflated ,
"Number of register classes inflated");
71STATISTIC(NumLaneConflicts,
"Number of dead lane conflicts tested");
72STATISTIC(NumLaneResolves,
"Number of dead lane conflicts resolved");
73STATISTIC(NumShrinkToUses,
"Number of shrinkToUses called");
76 cl::desc(
"Coalesce copies (default=true)"),
91 cl::desc(
"Coalesce copies that span blocks (default=subtarget)"),
96 cl::desc(
"Verify machine instrs before and after register coalescing"),
101 cl::desc(
"During rematerialization for a copy, if the def instruction has "
102 "many other copy uses to be rematerialized, delay the multiple "
103 "separate live interval update work and do them all at once after "
104 "all those rematerialization are done. It will save a lot of "
110 cl::desc(
"If the valnos size of an interval is larger than the threshold, "
111 "it is regarded as a large interval. "),
116 cl::desc(
"For a large interval, if it is coalesed with other live "
117 "intervals many times more than the threshold, stop its "
118 "coalescing to control the compile time. "),
153 using DbgValueLoc = std::pair<SlotIndex, MachineInstr*>;
162 bool ShrinkMainRange =
false;
166 bool JoinGlobalCopies =
false;
170 bool JoinSplitEdges =
false;
202 void coalesceLocals();
205 void joinAllIntervals();
220 void lateLiveIntervalUpdate();
225 bool copyValueUndefInPredecessors(
LiveRange &S,
291 std::pair<bool,bool> removeCopyByCommutingDef(
const CoalescerPair &CP,
362 MI->eraseFromParent();
389 MachineFunctionProperties::Property::IsSSA);
403char RegisterCoalescer::ID = 0;
408 "Register Coalescer",
false,
false)
421 Dst =
MI->getOperand(0).getReg();
422 DstSub =
MI->getOperand(0).getSubReg();
423 Src =
MI->getOperand(1).getReg();
424 SrcSub =
MI->getOperand(1).getSubReg();
425 }
else if (
MI->isSubregToReg()) {
426 Dst =
MI->getOperand(0).getReg();
427 DstSub = tri.composeSubRegIndices(
MI->getOperand(0).getSubReg(),
428 MI->getOperand(3).getImm());
429 Src =
MI->getOperand(2).getReg();
430 SrcSub =
MI->getOperand(2).getSubReg();
445 for (
const auto &
MI : *
MBB) {
446 if (!
MI.isCopyLike() && !
MI.isUnconditionalBranch())
456 Flipped = CrossClass =
false;
459 unsigned SrcSub = 0, DstSub = 0;
462 Partial = SrcSub || DstSub;
465 if (Src.isPhysical()) {
466 if (Dst.isPhysical())
475 if (Dst.isPhysical()) {
478 Dst =
TRI.getSubReg(Dst, DstSub);
479 if (!Dst)
return false;
485 Dst =
TRI.getMatchingSuperReg(Dst, SrcSub,
MRI.getRegClass(Src));
486 if (!Dst)
return false;
487 }
else if (!
MRI.getRegClass(Src)->contains(Dst)) {
496 if (SrcSub && DstSub) {
498 if (Src == Dst && SrcSub != DstSub)
501 NewRC =
TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
508 NewRC =
TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
512 NewRC =
TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
515 NewRC =
TRI.getCommonSubClass(DstRC, SrcRC);
524 if (DstIdx && !SrcIdx) {
530 CrossClass = NewRC != DstRC || NewRC != SrcRC;
533 assert(Src.isVirtual() &&
"Src must be virtual");
534 assert(!(Dst.isPhysical() && DstSub) &&
"Cannot have a physical SubIdx");
553 unsigned SrcSub = 0, DstSub = 0;
561 }
else if (Src != SrcReg) {
567 if (!Dst.isPhysical())
569 assert(!DstIdx && !SrcIdx &&
"Inconsistent CoalescerPair state.");
572 Dst =
TRI.getSubReg(Dst, DstSub);
575 return DstReg == Dst;
577 return Register(
TRI.getSubReg(DstReg, SrcSub)) == Dst;
583 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
584 TRI.composeSubRegIndices(DstIdx, DstSub);
588void RegisterCoalescer::getAnalysisUsage(
AnalysisUsage &AU)
const {
600void RegisterCoalescer::eliminateDeadDefs(
LiveRangeEdit *Edit) {
610void RegisterCoalescer::LRE_WillEraseInstruction(
MachineInstr *
MI) {
615bool RegisterCoalescer::adjustCopiesBackFrom(
const CoalescerPair &CP,
617 assert(!
CP.isPartial() &&
"This doesn't work for partial copies.");
618 assert(!
CP.isPhys() &&
"This doesn't work for physreg copies.");
643 if (BS == IntB.
end())
return false;
644 VNInfo *BValNo = BS->valno;
649 if (BValNo->
def != CopyIdx)
return false;
655 if (AS == IntA.
end())
return false;
656 VNInfo *AValNo = AS->valno;
662 if (!
CP.isCoalescable(ACopyMI) || !ACopyMI->
isFullCopy())
668 if (ValS == IntB.
end())
681 if (ValS+1 != BS)
return false;
685 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
689 BValNo->
def = FillerStart;
697 if (BValNo != ValS->valno)
706 S.removeSegment(*SS,
true);
710 if (!S.getVNInfoAt(FillerStart)) {
713 S.extendInBlock(BBStart, FillerStart);
715 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
718 if (SubBValNo != SubValSNo)
719 S.MergeValueNumberInto(SubBValNo, SubValSNo);
736 bool RecomputeLiveRange = AS->end == CopyIdx;
737 if (!RecomputeLiveRange) {
740 if (SS != S.end() &&
SS->end == CopyIdx) {
741 RecomputeLiveRange =
true;
746 if (RecomputeLiveRange)
753bool RegisterCoalescer::hasOtherReachingDefs(
LiveInterval &IntA,
763 if (ASeg.
valno != AValNo)
continue;
765 if (BI != IntB.
begin())
767 for (; BI != IntB.
end() && ASeg.
end >= BI->start; ++BI) {
768 if (BI->valno == BValNo)
770 if (BI->start <= ASeg.
start && BI->end > ASeg.
start)
772 if (BI->start > ASeg.
start && BI->start < ASeg.
end)
781static std::pair<bool,bool>
784 bool Changed =
false;
785 bool MergedWithDead =
false;
787 if (S.
valno != SrcValNo)
798 MergedWithDead =
true;
801 return std::make_pair(Changed, MergedWithDead);
805RegisterCoalescer::removeCopyByCommutingDef(
const CoalescerPair &CP,
838 assert(BValNo !=
nullptr && BValNo->
def == CopyIdx);
844 return {
false,
false };
847 return {
false,
false };
849 return {
false,
false };
856 return {
false,
false };
868 if (!
TII->findCommutedOpIndices(*
DefMI, UseOpIdx, NewDstIdx))
869 return {
false,
false };
874 return {
false,
false };
878 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
879 return {
false,
false };
888 if (US == IntA.
end() || US->valno != AValNo)
892 return {
false,
false };
902 TII->commuteInstruction(*
DefMI,
false, UseOpIdx, NewDstIdx);
904 return {
false,
false };
906 !
MRI->constrainRegClass(IntB.
reg(),
MRI->getRegClass(IntA.
reg())))
907 return {
false,
false };
908 if (NewMI !=
DefMI) {
933 UseMO.setReg(NewReg);
938 assert(US != IntA.
end() &&
"Use must be live");
939 if (US->valno != AValNo)
942 UseMO.setIsKill(
false);
944 UseMO.substPhysReg(NewReg, *
TRI);
946 UseMO.setReg(NewReg);
965 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
968 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
970 S.MergeValueNumberInto(SubDVNI, SubBValNo);
978 bool ShrinkB =
false;
992 VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
1001 MaskA |= SA.LaneMask;
1004 Allocator, SA.LaneMask,
1005 [&Allocator, &SA, CopyIdx, ASubValNo,
1007 VNInfo *BSubValNo = SR.empty() ? SR.getNextValue(CopyIdx, Allocator)
1008 : SR.getVNInfoAt(CopyIdx);
1009 assert(BSubValNo != nullptr);
1010 auto P = addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
1011 ShrinkB |= P.second;
1013 BSubValNo->def = ASubValNo->def;
1021 if ((SB.LaneMask & MaskA).any())
1025 SB.removeSegment(*S,
true);
1029 BValNo->
def = AValNo->
def;
1031 ShrinkB |=
P.second;
1038 return {
true, ShrinkB };
1088bool RegisterCoalescer::removePartialRedundancy(
const CoalescerPair &CP,
1121 bool FoundReverseCopy =
false;
1140 bool ValB_Changed =
false;
1141 for (
auto *VNI : IntB.
valnos) {
1142 if (VNI->isUnused())
1145 ValB_Changed =
true;
1153 FoundReverseCopy =
true;
1157 if (!FoundReverseCopy)
1167 if (CopyLeftBB && CopyLeftBB->
succ_size() > 1)
1178 if (InsPos != CopyLeftBB->
end()) {
1184 LLVM_DEBUG(
dbgs() <<
"\tremovePartialRedundancy: Move the copy to "
1189 TII->get(TargetOpcode::COPY), IntB.
reg())
1200 ErasedInstrs.
erase(NewCopyMI);
1202 LLVM_DEBUG(
dbgs() <<
"\tremovePartialRedundancy: Remove the copy from "
1213 deleteInstr(&CopyMI);
1229 if (!IntB.
liveAt(UseIdx))
1230 MO.setIsUndef(
true);
1240 VNInfo *BValNo = SR.Query(CopyIdx).valueOutOrDead();
1241 assert(BValNo &&
"All sublanes should be live");
1250 for (
unsigned I = 0;
I != EndPoints.
size(); ) {
1252 EndPoints[
I] = EndPoints.
back();
1274 assert(!Reg.isPhysical() &&
"This code cannot handle physreg aliasing");
1277 if (
Op.getReg() != Reg)
1281 if (
Op.getSubReg() == 0 ||
Op.isUndef())
1287bool RegisterCoalescer::reMaterializeTrivialDef(
const CoalescerPair &CP,
1291 Register SrcReg =
CP.isFlipped() ?
CP.getDstReg() :
CP.getSrcReg();
1292 unsigned SrcIdx =
CP.isFlipped() ?
CP.getDstIdx() :
CP.getSrcIdx();
1293 Register DstReg =
CP.isFlipped() ?
CP.getSrcReg() :
CP.getDstReg();
1294 unsigned DstIdx =
CP.isFlipped() ?
CP.getSrcIdx() :
CP.getDstIdx();
1316 LiveRangeEdit Edit(&SrcInt, NewRegs, *MF, *LIS,
nullptr,
this);
1322 bool SawStore =
false;
1339 if (SrcIdx && DstIdx)
1348 unsigned NewDstIdx =
TRI->composeSubRegIndices(
CP.getSrcIdx(),
1351 NewDstReg =
TRI->getSubReg(DstReg, NewDstIdx);
1361 "Only expect to deal with virtual or physical registers");
1387 assert(SrcIdx == 0 &&
CP.isFlipped()
1388 &&
"Shouldn't have SrcIdx+DstIdx at this point");
1391 TRI->getCommonSubClass(DefRC, DstRC);
1392 if (CommonRC !=
nullptr) {
1400 if (MO.isReg() && MO.getReg() == DstReg && MO.getSubReg() == DstIdx) {
1421 assert(MO.
isImplicit() &&
"No explicit operands after implicit operands.");
1424 "unexpected implicit virtual register def");
1430 ErasedInstrs.
insert(CopyMI);
1444 bool NewMIDefinesFullReg =
false;
1454 if (MO.
getReg() == DstReg)
1455 NewMIDefinesFullReg =
true;
1460 ((
TRI->getSubReg(MO.
getReg(), DefSubIdx) ==
1473 assert(!
MRI->shouldTrackSubRegLiveness(DstReg) &&
1474 "subrange update for implicit-def of super register may not be "
1475 "properly handled");
1483 if (DefRC !=
nullptr) {
1485 NewRC =
TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
1487 NewRC =
TRI->getCommonSubClass(NewRC, DefRC);
1488 assert(NewRC &&
"subreg chosen for remat incompatible with instruction");
1493 SR.LaneMask =
TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
1495 MRI->setRegClass(DstReg, NewRC);
1498 updateRegDefsUses(DstReg, DstReg, DstIdx);
1526 if (!SR.liveAt(DefIndex))
1527 SR.createDeadDef(DefIndex,
Alloc);
1528 MaxMask &= ~SR.LaneMask;
1530 if (MaxMask.
any()) {
1548 bool UpdatedSubRanges =
false;
1553 if ((SR.
LaneMask & DstMask).none()) {
1555 <<
"Removing undefined SubRange "
1568 UpdatedSubRanges =
true;
1579 if (UpdatedSubRanges)
1586 "Only expect virtual or physical registers in remat");
1589 if (!NewMIDefinesFullReg) {
1591 CopyDstReg,
true ,
true ,
false ));
1634 if (
MRI->use_nodbg_empty(SrcReg)) {
1640 UseMO.substPhysReg(DstReg, *
TRI);
1642 UseMO.setReg(DstReg);
1651 if (ToBeUpdated.
count(SrcReg))
1654 unsigned NumCopyUses = 0;
1656 if (UseMO.getParent()->isCopyLike())
1662 if (!DeadDefs.
empty())
1663 eliminateDeadDefs(&Edit);
1665 ToBeUpdated.
insert(SrcReg);
1683 unsigned SrcSubIdx = 0, DstSubIdx = 0;
1684 if(!
isMoveInstr(*
TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1693 if ((SR.
LaneMask & SrcMask).none())
1706 assert(Seg !=
nullptr &&
"No segment for defining instruction");
1711 if (((V &&
V->isPHIDef()) || (!V && !DstLI.
liveAt(
Idx)))) {
1719 CopyMI->
getOpcode() == TargetOpcode::SUBREG_TO_REG);
1724 CopyMI->
setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1741 if ((SR.
LaneMask & DstMask).none())
1763 if ((SR.
LaneMask & UseMask).none())
1771 isLive = DstLI.
liveAt(UseIdx);
1784 if (MO.
getReg() == DstReg)
1796 bool IsUndef =
true;
1798 if ((S.LaneMask & Mask).none())
1800 if (S.liveAt(UseIdx)) {
1813 ShrinkMainRange =
true;
1822 if (DstInt && DstInt->
hasSubRanges() && DstReg != SrcReg) {
1828 if (
MI.isDebugInstr())
1831 addUndefFlag(*DstInt, UseIdx, MO,
SubReg);
1837 I =
MRI->reg_instr_begin(SrcReg), E =
MRI->reg_instr_end();
1846 if (SrcReg == DstReg && !Visited.
insert(
UseMI).second)
1859 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
1865 if (SubIdx && MO.
isDef())
1870 if (MO.
isUse() && !DstIsPhys) {
1871 unsigned SubUseIdx =
TRI->composeSubRegIndices(SubIdx, MO.
getSubReg());
1872 if (SubUseIdx != 0 &&
MRI->shouldTrackSubRegLiveness(DstReg)) {
1889 addUndefFlag(*DstInt, UseIdx, MO, SubUseIdx);
1900 dbgs() <<
"\t\tupdated: ";
1908bool RegisterCoalescer::canJoinPhys(
const CoalescerPair &CP) {
1912 if (!
MRI->isReserved(
CP.getDstReg())) {
1913 LLVM_DEBUG(
dbgs() <<
"\tCan only merge into reserved registers.\n");
1922 dbgs() <<
"\tCannot join complex intervals into reserved register.\n");
1926bool RegisterCoalescer::copyValueUndefInPredecessors(
1940void RegisterCoalescer::setUndefOnPrunedSubRegUses(
LiveInterval &LI,
1947 if (SubRegIdx == 0 || MO.
isUndef())
1953 if (!S.
liveAt(Pos) && (PrunedLanes & SubRegMask).any()) {
1969bool RegisterCoalescer::joinCopy(
1976 if (!
CP.setRegisters(CopyMI)) {
1981 if (
CP.getNewRC()) {
1982 auto SrcRC =
MRI->getRegClass(
CP.getSrcReg());
1983 auto DstRC =
MRI->getRegClass(
CP.getDstReg());
1984 unsigned SrcIdx =
CP.getSrcIdx();
1985 unsigned DstIdx =
CP.getDstIdx();
1986 if (
CP.isFlipped()) {
1990 if (!
TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
1991 CP.getNewRC(), *LIS)) {
2003 eliminateDeadDefs();
2010 if (
MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
2011 if (UndefMI->isImplicitDef())
2013 deleteInstr(CopyMI);
2021 if (
CP.getSrcReg() ==
CP.getDstReg()) {
2023 LLVM_DEBUG(
dbgs() <<
"\tCopy already coalesced: " << LI <<
'\n');
2028 assert(ReadVNI &&
"No value before copy and no <undef> flag.");
2029 assert(ReadVNI != DefVNI &&
"Cannot read and define the same value.");
2044 if (copyValueUndefInPredecessors(S,
MBB, SLRQ)) {
2045 LLVM_DEBUG(
dbgs() <<
"Incoming sublane value is undef at copy\n");
2046 PrunedLanes |= S.LaneMask;
2053 if (PrunedLanes.
any()) {
2055 << PrunedLanes <<
'\n');
2056 setUndefOnPrunedSubRegUses(LI,
CP.getSrcReg(), PrunedLanes);
2061 deleteInstr(CopyMI);
2070 if (!canJoinPhys(CP)) {
2073 bool IsDefCopy =
false;
2074 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
2087 dbgs() <<
"\tConsidering merging to "
2088 <<
TRI->getRegClassName(
CP.getNewRC()) <<
" with ";
2089 if (
CP.getDstIdx() &&
CP.getSrcIdx())
2091 <<
TRI->getSubRegIndexName(
CP.getDstIdx()) <<
" and "
2093 <<
TRI->getSubRegIndexName(
CP.getSrcIdx()) <<
'\n';
2101 ShrinkMainRange =
false;
2107 if (!joinIntervals(CP)) {
2112 bool IsDefCopy =
false;
2113 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
2118 if (!
CP.isPartial() && !
CP.isPhys()) {
2119 bool Changed = adjustCopiesBackFrom(CP, CopyMI);
2120 bool Shrink =
false;
2122 std::tie(Changed, Shrink) = removeCopyByCommutingDef(CP, CopyMI);
2124 deleteInstr(CopyMI);
2126 Register DstReg =
CP.isFlipped() ?
CP.getSrcReg() :
CP.getDstReg();
2138 if (!
CP.isPartial() && !
CP.isPhys())
2139 if (removePartialRedundancy(CP, *CopyMI))
2150 if (
CP.isCrossClass()) {
2152 MRI->setRegClass(
CP.getDstReg(),
CP.getNewRC());
2163 if (ErasedInstrs.
erase(CopyMI))
2165 CurrentErasedInstrs.
insert(CopyMI);
2170 updateRegDefsUses(
CP.getDstReg(),
CP.getDstReg(),
CP.getDstIdx());
2171 updateRegDefsUses(
CP.getSrcReg(),
CP.getDstReg(),
CP.getSrcIdx());
2174 if (ShrinkMask.
any()) {
2177 if ((S.LaneMask & ShrinkMask).none())
2182 ShrinkMainRange =
true;
2190 if (ToBeUpdated.
count(
CP.getSrcReg()))
2191 ShrinkMainRange =
true;
2193 if (ShrinkMainRange) {
2203 TRI->updateRegAllocHint(
CP.getSrcReg(),
CP.getDstReg(), *MF);
2208 dbgs() <<
"\tResult = ";
2220bool RegisterCoalescer::joinReservedPhysReg(
CoalescerPair &CP) {
2223 assert(
CP.isPhys() &&
"Must be a physreg copy");
2224 assert(
MRI->isReserved(DstReg) &&
"Not a reserved register");
2228 assert(
RHS.containsOneValue() &&
"Invalid join with reserved register");
2237 if (!
MRI->isConstantPhysReg(DstReg)) {
2241 if (!
MRI->isReserved(*RI))
2254 !RegMaskUsable.
test(DstReg)) {
2267 if (
CP.isFlipped()) {
2275 CopyMI =
MRI->getVRegDef(SrcReg);
2276 deleteInstr(CopyMI);
2285 if (!
MRI->hasOneNonDBGUse(SrcReg)) {
2296 CopyMI = &*
MRI->use_instr_nodbg_begin(SrcReg);
2300 if (!
MRI->isConstantPhysReg(DstReg)) {
2308 if (
MI->readsRegister(DstReg,
TRI)) {
2318 <<
printReg(DstReg,
TRI) <<
" at " << CopyRegIdx <<
"\n");
2321 deleteInstr(CopyMI);
2331 MRI->clearKillFlags(
CP.getSrcReg());
2416 const unsigned SubIdx;
2424 const bool SubRangeJoin;
2427 const bool TrackSubRegLiveness;
2443 enum ConflictResolution {
2475 ConflictResolution Resolution = CR_Keep;
2485 VNInfo *RedefVNI =
nullptr;
2488 VNInfo *OtherVNI =
nullptr;
2501 bool ErasableImplicitDef =
false;
2505 bool Pruned =
false;
2508 bool PrunedComputed =
false;
2515 bool Identical =
false;
2519 bool isAnalyzed()
const {
return WriteLanes.
any(); }
2526 ErasableImplicitDef =
false;
2540 std::pair<const VNInfo *, Register> followCopyChain(
const VNInfo *VNI)
const;
2542 bool valuesIdentical(
VNInfo *Value0,
VNInfo *Value1,
const JoinVals &
Other)
const;
2551 ConflictResolution analyzeValue(
unsigned ValNo, JoinVals &
Other);
2556 void computeAssignment(
unsigned ValNo, JoinVals &
Other);
2587 bool isPrunedValue(
unsigned ValNo, JoinVals &
Other);
2593 bool TrackSubRegLiveness)
2594 : LR(LR),
Reg(
Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2595 SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2596 NewVNInfo(newVNInfo),
CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2597 TRI(
TRI), Assignments(LR.getNumValNums(), -1),
2598 Vals(LR.getNumValNums()) {}
2602 bool mapValues(JoinVals &
Other);
2606 bool resolveConflicts(JoinVals &
Other);
2626 void pruneMainSegments(
LiveInterval &LI,
bool &ShrinkMainRange);
2637 void removeImplicitDefs();
2640 const int *getAssignments()
const {
return Assignments.
data(); }
2643 ConflictResolution getResolution(
unsigned Num)
const {
2644 return Vals[Num].Resolution;
2656 L |=
TRI->getSubRegIndexLaneMask(
2664std::pair<const VNInfo *, Register>
2665JoinVals::followCopyChain(
const VNInfo *VNI)
const {
2671 assert(
MI &&
"No defining instruction");
2672 if (!
MI->isFullCopy())
2673 return std::make_pair(VNI, TrackReg);
2674 Register SrcReg =
MI->getOperand(1).getReg();
2676 return std::make_pair(VNI, TrackReg);
2690 LaneBitmask SMask =
TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
2691 if ((SMask & LaneMask).
none())
2699 return std::make_pair(VNI, TrackReg);
2702 if (ValueIn ==
nullptr) {
2709 return std::make_pair(
nullptr, SrcReg);
2714 return std::make_pair(VNI, TrackReg);
2717bool JoinVals::valuesIdentical(
VNInfo *Value0,
VNInfo *Value1,
2718 const JoinVals &
Other)
const {
2721 std::tie(Orig0, Reg0) = followCopyChain(Value0);
2722 if (Orig0 == Value1 && Reg0 ==
Other.Reg)
2727 std::tie(Orig1, Reg1) =
Other.followCopyChain(Value1);
2731 if (Orig0 ==
nullptr || Orig1 ==
nullptr)
2732 return Orig0 == Orig1 && Reg0 == Reg1;
2738 return Orig0->
def == Orig1->
def && Reg0 == Reg1;
2741JoinVals::ConflictResolution
2742JoinVals::analyzeValue(
unsigned ValNo, JoinVals &
Other) {
2743 Val &
V = Vals[ValNo];
2744 assert(!
V.isAnalyzed() &&
"Value has already been analyzed!");
2756 :
TRI->getSubRegIndexLaneMask(SubIdx);
2757 V.ValidLanes =
V.WriteLanes = Lanes;
2766 V.ErasableImplicitDef =
true;
2770 V.ValidLanes =
V.WriteLanes = computeWriteLanes(
DefMI, Redef);
2789 assert((TrackSubRegLiveness ||
V.RedefVNI) &&
2790 "Instruction is reading nonexistent value");
2791 if (
V.RedefVNI !=
nullptr) {
2792 computeAssignment(
V.RedefVNI->id,
Other);
2793 V.ValidLanes |= Vals[
V.RedefVNI->id].ValidLanes;
2805 V.ErasableImplicitDef =
true;
2822 if (OtherVNI->
def < VNI->
def)
2823 Other.computeAssignment(OtherVNI->
id, *
this);
2828 return CR_Impossible;
2830 V.OtherVNI = OtherVNI;
2831 Val &OtherV =
Other.Vals[OtherVNI->
id];
2835 if (!OtherV.isAnalyzed() ||
Other.Assignments[OtherVNI->
id] == -1)
2842 if ((
V.ValidLanes & OtherV.ValidLanes).any())
2844 return CR_Impossible;
2859 Other.computeAssignment(
V.OtherVNI->id, *
this);
2860 Val &OtherV =
Other.Vals[
V.OtherVNI->id];
2862 if (OtherV.ErasableImplicitDef) {
2882 <<
", keeping it.\n");
2883 OtherV.mustKeepImplicitDef(*
TRI, *OtherImpDef);
2890 dbgs() <<
"IMPLICIT_DEF defined at " <<
V.OtherVNI->def
2891 <<
" may be live into EH pad successors, keeping it.\n");
2892 OtherV.mustKeepImplicitDef(*
TRI, *OtherImpDef);
2895 OtherV.ValidLanes &= ~OtherV.WriteLanes;
2910 if (
CP.isCoalescable(
DefMI)) {
2913 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
2928 valuesIdentical(VNI,
V.OtherVNI,
Other)) {
2951 if ((
V.WriteLanes & OtherV.ValidLanes).none())
2964 "Only early clobber defs can overlap a kill");
2965 return CR_Impossible;
2972 if ((
TRI->getSubRegIndexLaneMask(
Other.SubIdx) & ~
V.WriteLanes).none())
2973 return CR_Impossible;
2975 if (TrackSubRegLiveness) {
2980 if (!OtherLI.hasSubRanges()) {
2982 return (OtherMask &
V.WriteLanes).none() ? CR_Replace : CR_Impossible;
2990 TRI->composeSubRegIndexLaneMask(
Other.SubIdx, OtherSR.LaneMask);
2991 if ((OtherMask &
V.WriteLanes).none())
2994 auto OtherSRQ = OtherSR.Query(VNI->
def);
2995 if (OtherSRQ.valueIn() && OtherSRQ.endPoint() > VNI->
def) {
2997 return CR_Impossible;
3010 return CR_Impossible;
3019 return CR_Unresolved;
3022void JoinVals::computeAssignment(
unsigned ValNo, JoinVals &
Other) {
3023 Val &
V = Vals[ValNo];
3024 if (
V.isAnalyzed()) {
3027 assert(Assignments[ValNo] != -1 &&
"Bad recursion?");
3030 switch ((
V.Resolution = analyzeValue(ValNo,
Other))) {
3034 assert(
V.OtherVNI &&
"OtherVNI not assigned, can't merge.");
3035 assert(
Other.Vals[
V.OtherVNI->id].isAnalyzed() &&
"Missing recursion");
3036 Assignments[ValNo] =
Other.Assignments[
V.OtherVNI->id];
3040 <<
V.OtherVNI->def <<
" --> @"
3041 << NewVNInfo[Assignments[ValNo]]->def <<
'\n');
3044 case CR_Unresolved: {
3046 assert(
V.OtherVNI &&
"OtherVNI not assigned, can't prune");
3047 Val &OtherV =
Other.Vals[
V.OtherVNI->id];
3048 OtherV.Pruned =
true;
3053 Assignments[ValNo] = NewVNInfo.
size();
3059bool JoinVals::mapValues(JoinVals &
Other) {
3061 computeAssignment(i,
Other);
3062 if (Vals[i].Resolution == CR_Impossible) {
3080 assert(OtherI !=
Other.LR.end() &&
"No conflict?");
3085 if (
End >= MBBEnd) {
3087 << OtherI->valno->id <<
'@' << OtherI->start <<
'\n');
3091 << OtherI->valno->id <<
'@' << OtherI->start <<
" to "
3096 TaintExtent.push_back(std::make_pair(
End, TaintedLanes));
3099 if (++OtherI ==
Other.LR.end() || OtherI->start >= MBBEnd)
3103 const Val &OV =
Other.Vals[OtherI->valno->id];
3104 TaintedLanes &= ~OV.WriteLanes;
3107 }
while (TaintedLanes.
any());
3113 if (
MI.isDebugOrPseudoInstr())
3120 unsigned S =
TRI->composeSubRegIndices(SubIdx, MO.
getSubReg());
3121 if ((Lanes &
TRI->getSubRegIndexLaneMask(S)).any())
3127bool JoinVals::resolveConflicts(JoinVals &
Other) {
3130 assert(
V.Resolution != CR_Impossible &&
"Unresolvable conflict");
3131 if (
V.Resolution != CR_Unresolved)
3140 assert(
V.OtherVNI &&
"Inconsistent conflict resolution.");
3142 const Val &OtherV =
Other.Vals[
V.OtherVNI->id];
3147 LaneBitmask TaintedLanes =
V.WriteLanes & OtherV.ValidLanes;
3149 if (!taintExtent(i, TaintedLanes,
Other, TaintExtent))
3153 assert(!TaintExtent.
empty() &&
"There should be at least one conflict.");
3166 "Interference ends on VNI->def. Should have been handled earlier");
3169 assert(LastMI &&
"Range must end at a proper instruction");
3170 unsigned TaintNum = 0;
3173 if (usesLanes(*
MI,
Other.Reg,
Other.SubIdx, TaintedLanes)) {
3178 if (&*
MI == LastMI) {
3179 if (++TaintNum == TaintExtent.
size())
3182 assert(LastMI &&
"Range must end at a proper instruction");
3183 TaintedLanes = TaintExtent[TaintNum].second;
3189 V.Resolution = CR_Replace;
3195bool JoinVals::isPrunedValue(
unsigned ValNo, JoinVals &
Other) {
3196 Val &
V = Vals[ValNo];
3197 if (
V.Pruned ||
V.PrunedComputed)
3200 if (
V.Resolution != CR_Erase &&
V.Resolution != CR_Merge)
3205 V.PrunedComputed =
true;
3206 V.Pruned =
Other.isPrunedValue(
V.OtherVNI->id, *
this);
3210void JoinVals::pruneValues(JoinVals &
Other,
3212 bool changeInstrs) {
3215 switch (Vals[i].Resolution) {
3225 Val &OtherV =
Other.Vals[Vals[i].OtherVNI->id];
3226 bool EraseImpDef = OtherV.ErasableImplicitDef &&
3227 OtherV.Resolution == CR_Keep;
3228 if (!
Def.isBlock()) {
3248 <<
": " <<
Other.LR <<
'\n');
3253 if (isPrunedValue(i,
Other)) {
3260 << Def <<
": " << LR <<
'\n');
3318 bool DidPrune =
false;
3323 if (
V.Resolution != CR_Erase &&
3324 (
V.Resolution != CR_Keep || !
V.ErasableImplicitDef || !
V.Pruned))
3331 OtherDef =
V.OtherVNI->def;
3334 LLVM_DEBUG(
dbgs() <<
"\t\tExpecting instruction removal at " << Def
3342 if (ValueOut !=
nullptr && (Q.
valueIn() ==
nullptr ||
3343 (
V.Identical &&
V.Resolution == CR_Erase &&
3344 ValueOut->
def == Def))) {
3346 <<
" at " << Def <<
"\n");
3353 if (
V.Identical && S.Query(OtherDef).valueOutOrDead()) {
3363 ShrinkMask |= S.LaneMask;
3377 ShrinkMask |= S.LaneMask;
3389 if (VNI->
def == Def)
3395void JoinVals::pruneMainSegments(
LiveInterval &LI,
bool &ShrinkMainRange) {
3399 if (Vals[i].Resolution != CR_Keep)
3404 Vals[i].Pruned =
true;
3405 ShrinkMainRange =
true;
3409void JoinVals::removeImplicitDefs() {
3412 if (
V.Resolution != CR_Keep || !
V.ErasableImplicitDef || !
V.Pruned)
3428 switch (Vals[i].Resolution) {
3433 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
3445 if (LI !=
nullptr) {
3470 ED = ED.
isValid() ? std::min(ED,
I->start) :
I->start;
3472 LE =
LE.isValid() ? std::max(LE,
I->end) :
I->
end;
3475 NewEnd = std::min(NewEnd, LE);
3477 NewEnd = std::min(NewEnd, ED);
3483 if (S != LR.
begin())
3484 std::prev(S)->end = NewEnd;
3488 dbgs() <<
"\t\tremoved " << i <<
'@' <<
Def <<
": " << LR <<
'\n';
3490 dbgs() <<
"\t\t LHS = " << *LI <<
'\n';
3497 assert(
MI &&
"No instruction to erase");
3500 if (
Reg.isVirtual() && Reg !=
CP.getSrcReg() && Reg !=
CP.getDstReg())
3506 MI->eraseFromParent();
3519 JoinVals RHSVals(RRange,
CP.getSrcReg(),
CP.getSrcIdx(), LaneMask,
3520 NewVNInfo, CP, LIS,
TRI,
true,
true);
3521 JoinVals LHSVals(LRange,
CP.getDstReg(),
CP.getDstIdx(), LaneMask,
3522 NewVNInfo, CP, LIS,
TRI,
true,
true);
3529 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals)) {
3534 if (!LHSVals.resolveConflicts(RHSVals) ||
3535 !RHSVals.resolveConflicts(LHSVals)) {
3546 LHSVals.pruneValues(RHSVals, EndPoints,
false);
3547 RHSVals.pruneValues(LHSVals, EndPoints,
false);
3549 LHSVals.removeImplicitDefs();
3550 RHSVals.removeImplicitDefs();
3556 LRange.
join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
3560 <<
' ' << LRange <<
"\n");
3561 if (EndPoints.
empty())
3567 dbgs() <<
"\t\trestoring liveness to " << EndPoints.
size() <<
" points: ";
3568 for (
unsigned i = 0, n = EndPoints.
size(); i != n; ++i) {
3569 dbgs() << EndPoints[i];
3573 dbgs() <<
": " << LRange <<
'\n';
3578void RegisterCoalescer::mergeSubRangeInto(
LiveInterval &LI,
3582 unsigned ComposeSubRegIdx) {
3585 Allocator, LaneMask,
3588 SR.assign(ToMerge, Allocator);
3591 LiveRange RangeCopy(ToMerge, Allocator);
3592 joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
3598bool RegisterCoalescer::isHighCostLiveInterval(
LiveInterval &LI) {
3601 auto &Counter = LargeLIVisitCounter[LI.
reg()];
3613 bool TrackSubRegLiveness =
MRI->shouldTrackSubRegLiveness(*
CP.getNewRC());
3615 NewVNInfo, CP, LIS,
TRI,
false, TrackSubRegLiveness);
3617 NewVNInfo, CP, LIS,
TRI,
false, TrackSubRegLiveness);
3619 LLVM_DEBUG(
dbgs() <<
"\t\tRHS = " << RHS <<
"\n\t\tLHS = " << LHS <<
'\n');
3621 if (isHighCostLiveInterval(LHS) || isHighCostLiveInterval(RHS))
3626 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
3630 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
3634 if (
RHS.hasSubRanges() ||
LHS.hasSubRanges()) {
3639 unsigned DstIdx =
CP.getDstIdx();
3640 if (!
LHS.hasSubRanges()) {
3642 :
TRI->getSubRegIndexLaneMask(DstIdx);
3645 LHS.createSubRangeFrom(Allocator, Mask, LHS);
3646 }
else if (DstIdx != 0) {
3657 unsigned SrcIdx =
CP.getSrcIdx();
3658 if (!
RHS.hasSubRanges()) {
3660 :
TRI->getSubRegIndexLaneMask(SrcIdx);
3661 mergeSubRangeInto(LHS, RHS, Mask, CP, DstIdx);
3666 mergeSubRangeInto(LHS, R, Mask, CP, DstIdx);
3673 LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
3675 LHSVals.pruneSubRegValues(LHS, ShrinkMask);
3676 RHSVals.pruneSubRegValues(LHS, ShrinkMask);
3684 LHSVals.pruneValues(RHSVals, EndPoints,
true);
3685 RHSVals.pruneValues(LHSVals, EndPoints,
true);
3690 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs, &LHS);
3691 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
3692 while (!ShrinkRegs.
empty())
3696 checkMergingChangesDbgValues(CP, LHS, LHSVals, RHS, RHSVals);
3700 auto RegIt = RegToPHIIdx.
find(
CP.getSrcReg());
3701 if (RegIt != RegToPHIIdx.
end()) {
3703 for (
unsigned InstID : RegIt->second) {
3704 auto PHIIt = PHIValToPos.
find(InstID);
3709 auto LII =
RHS.find(SI);
3710 if (LII ==
RHS.end() || LII->start > SI)
3725 if (
CP.getSrcIdx() != 0 ||
CP.getDstIdx() != 0)
3728 if (PHIIt->second.SubReg && PHIIt->second.SubReg !=
CP.getSrcIdx())
3732 PHIIt->second.Reg =
CP.getDstReg();
3736 if (
CP.getSrcIdx() != 0)
3737 PHIIt->second.SubReg =
CP.getSrcIdx();
3743 auto InstrNums = RegIt->second;
3744 RegToPHIIdx.
erase(RegIt);
3748 RegIt = RegToPHIIdx.
find(
CP.getDstReg());
3749 if (RegIt != RegToPHIIdx.
end())
3750 RegIt->second.insert(RegIt->second.end(), InstrNums.begin(),
3753 RegToPHIIdx.
insert({
CP.getDstReg(), InstrNums});
3757 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
3762 MRI->clearKillFlags(
LHS.reg());
3763 MRI->clearKillFlags(
RHS.reg());
3765 if (!EndPoints.
empty()) {
3769 dbgs() <<
"\t\trestoring liveness to " << EndPoints.
size() <<
" points: ";
3770 for (
unsigned i = 0, n = EndPoints.
size(); i != n; ++i) {
3771 dbgs() << EndPoints[i];
3775 dbgs() <<
": " <<
LHS <<
'\n';
3784 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(
CP);
3795 for (
auto *
X : ToInsert) {
3796 for (
const auto &
Op :
X->debug_operands()) {
3797 if (
Op.isReg() &&
Op.getReg().isVirtual())
3808 for (
auto &
MBB : MF) {
3811 for (
auto &
MI :
MBB) {
3812 if (
MI.isDebugValue()) {
3814 return MO.isReg() && MO.getReg().isVirtual();
3816 ToInsert.push_back(&
MI);
3817 }
else if (!
MI.isDebugOrPseudoInstr()) {
3819 CloseNewDVRange(CurrentSlot);
3828 for (
auto &Pair : DbgVRegToValues)
3832void RegisterCoalescer::checkMergingChangesDbgValues(
CoalescerPair &CP,
3836 JoinVals &RHSVals) {
3838 checkMergingChangesDbgValuesImpl(Reg, RHS, LHS, LHSVals);
3842 checkMergingChangesDbgValuesImpl(Reg, LHS, RHS, RHSVals);
3846 ScanForSrcReg(
CP.getSrcReg());
3847 ScanForDstReg(
CP.getDstReg());
3850void RegisterCoalescer::checkMergingChangesDbgValuesImpl(
Register Reg,
3853 JoinVals &RegVals) {
3855 auto VRegMapIt = DbgVRegToValues.
find(Reg);
3856 if (VRegMapIt == DbgVRegToValues.
end())
3859 auto &DbgValueSet = VRegMapIt->second;
3860 auto DbgValueSetIt = DbgValueSet.begin();
3861 auto SegmentIt = OtherLR.
begin();
3863 bool LastUndefResult =
false;
3868 auto ShouldUndef = [&RegVals, &
RegLR, &LastUndefResult,
3873 if (LastUndefIdx ==
Idx)
3874 return LastUndefResult;
3881 if (OtherIt ==
RegLR.end())
3890 auto Resolution = RegVals.getResolution(OtherIt->valno->id);
3891 LastUndefResult = Resolution != JoinVals::CR_Keep &&
3892 Resolution != JoinVals::CR_Erase;
3894 return LastUndefResult;
3900 while (DbgValueSetIt != DbgValueSet.end() && SegmentIt != OtherLR.
end()) {
3901 if (DbgValueSetIt->first < SegmentIt->end) {
3904 if (DbgValueSetIt->first >= SegmentIt->start) {
3905 bool HasReg = DbgValueSetIt->second->hasDebugOperandForReg(Reg);
3906 bool ShouldUndefReg = ShouldUndef(DbgValueSetIt->first);
3907 if (HasReg && ShouldUndefReg) {
3909 DbgValueSetIt->second->setDebugValueUndef();
3923struct MBBPriorityInfo {
3929 :
MBB(mbb),
Depth(depth), IsSplit(issplit) {}
3939 const MBBPriorityInfo *RHS) {
3941 if (
LHS->Depth !=
RHS->Depth)
3942 return LHS->Depth >
RHS->Depth ? -1 : 1;
3945 if (
LHS->IsSplit !=
RHS->IsSplit)
3946 return LHS->IsSplit ? -1 : 1;
3950 unsigned cl =
LHS->MBB->pred_size() +
LHS->MBB->succ_size();
3951 unsigned cr =
RHS->MBB->pred_size() +
RHS->MBB->succ_size();
3953 return cl > cr ? -1 : 1;
3956 return LHS->MBB->getNumber() <
RHS->MBB->getNumber() ? -1 : 1;
3961 if (!Copy->isCopy())
3964 if (Copy->getOperand(1).isUndef())
3967 Register SrcReg = Copy->getOperand(1).getReg();
3968 Register DstReg = Copy->getOperand(0).getReg();
3976void RegisterCoalescer::lateLiveIntervalUpdate() {
3982 if (!DeadDefs.
empty())
3983 eliminateDeadDefs();
3985 ToBeUpdated.clear();
3988bool RegisterCoalescer::
3990 bool Progress =
false;
4002 bool Success = joinCopy(
MI, Again, CurrentErasedInstrs);
4008 if (!CurrentErasedInstrs.
empty()) {
4010 if (
MI && CurrentErasedInstrs.
count(
MI))
4014 if (
MI && CurrentErasedInstrs.
count(
MI))
4025 assert(Copy.isCopyLike());
4028 if (&
MI != &Copy &&
MI.isCopyLike())
4033bool RegisterCoalescer::applyTerminalRule(
const MachineInstr &Copy)
const {
4038 unsigned SrcSubReg = 0, DstSubReg = 0;
4039 if (!
isMoveInstr(*
TRI, &Copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
4060 if (&
MI == &Copy || !
MI.isCopyLike() ||
MI.getParent() != OrigBB)
4063 unsigned OtherSrcSubReg = 0, OtherSubReg = 0;
4064 if (!
isMoveInstr(*
TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
4067 if (OtherReg == SrcReg)
4068 OtherReg = OtherSrcReg;
4088 const unsigned PrevSize = WorkList.
size();
4089 if (JoinGlobalCopies) {
4097 if (!
MI.isCopyLike())
4099 bool ApplyTerminalRule = applyTerminalRule(
MI);
4101 if (ApplyTerminalRule)
4106 if (ApplyTerminalRule)
4113 LocalWorkList.
append(LocalTerminals.
begin(), LocalTerminals.
end());
4119 if (MII.isCopyLike()) {
4120 if (applyTerminalRule(MII))
4132 CurrList(WorkList.
begin() + PrevSize, WorkList.
end());
4133 if (copyCoalesceWorkList(CurrList))
4134 WorkList.
erase(std::remove(WorkList.
begin() + PrevSize, WorkList.
end(),
4135 nullptr), WorkList.
end());
4138void RegisterCoalescer::coalesceLocals() {
4139 copyCoalesceWorkList(LocalWorkList);
4140 for (
unsigned j = 0, je = LocalWorkList.
size(); j != je; ++j) {
4141 if (LocalWorkList[j])
4144 LocalWorkList.
clear();
4147void RegisterCoalescer::joinAllIntervals() {
4148 LLVM_DEBUG(
dbgs() <<
"********** JOINING INTERVALS ***********\n");
4149 assert(WorkList.
empty() && LocalWorkList.
empty() &&
"Old data still around.");
4151 std::vector<MBBPriorityInfo> MBBs;
4152 MBBs.reserve(MF->size());
4154 MBBs.push_back(MBBPriorityInfo(&
MBB,
Loops->getLoopDepth(&
MBB),
4160 unsigned CurrDepth = std::numeric_limits<unsigned>::max();
4161 for (MBBPriorityInfo &
MBB : MBBs) {
4163 if (JoinGlobalCopies &&
MBB.Depth < CurrDepth) {
4165 CurrDepth =
MBB.Depth;
4167 copyCoalesceInMBB(
MBB.MBB);
4169 lateLiveIntervalUpdate();
4174 while (copyCoalesceWorkList(WorkList))
4176 lateLiveIntervalUpdate();
4179void RegisterCoalescer::releaseMemory() {
4180 ErasedInstrs.
clear();
4183 InflateRegs.
clear();
4184 LargeLIVisitCounter.
clear();
4188 LLVM_DEBUG(
dbgs() <<
"********** REGISTER COALESCER **********\n"
4189 <<
"********** Function: " << fn.
getName() <<
'\n');
4201 dbgs() <<
"* Skipped as it exposes functions that returns twice.\n");
4210 LIS = &getAnalysis<LiveIntervals>();
4211 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
4212 Loops = &getAnalysis<MachineLoopInfo>();
4221 for (
const auto &DebugPHI : MF->DebugPHIPositions) {
4224 unsigned SubReg = DebugPHI.second.SubReg;
4227 PHIValToPos.
insert(std::make_pair(DebugPHI.first,
P));
4228 RegToPHIIdx[
Reg].push_back(DebugPHI.first);
4237 MF->verify(
this,
"Before register coalescing");
4239 DbgVRegToValues.
clear();
4252 InflateRegs.
erase(std::unique(InflateRegs.
begin(), InflateRegs.
end()),
4257 if (
MRI->reg_nodbg_empty(Reg))
4259 if (
MRI->recomputeRegClass(Reg)) {
4261 <<
TRI->getRegClassName(
MRI->getRegClass(Reg)) <<
'\n');
4268 if (!
MRI->shouldTrackSubRegLiveness(Reg)) {
4276 assert((S.LaneMask & ~MaxMask).none());
4286 for (
auto &p : MF->DebugPHIPositions) {
4287 auto it = PHIValToPos.
find(
p.first);
4289 p.second.Reg = it->second.Reg;
4290 p.second.SubReg = it->second.SubReg;
4293 PHIValToPos.
clear();
4294 RegToPHIIdx.
clear();
4298 MF->verify(
this,
"After register coalescing");
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseSet and SmallDenseSet classes.
std::optional< std::vector< StOtherPiece > > Other
SmallVector< uint32_t, 0 > Writes
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static cl::opt< cl::boolOrDefault > EnableGlobalCopies("join-globalcopies", cl::desc("Coalesce copies that span blocks (default=subtarget)"), cl::init(cl::BOU_UNSET), cl::Hidden)
Temporary flag to test global copy optimization.
static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS)
static bool isSplitEdge(const MachineBasicBlock *MBB)
Return true if this block should be vacated by the coalescer to eliminate branches.
static int compareMBBPriority(const MBBPriorityInfo *LHS, const MBBPriorityInfo *RHS)
C-style comparator that sorts first based on the loop depth of the basic block (the unsigned),...
register Register Coalescer
static cl::opt< unsigned > LargeIntervalSizeThreshold("large-interval-size-threshold", cl::Hidden, cl::desc("If the valnos size of an interval is larger than the threshold, " "it is regarded as a large interval. "), cl::init(100))
static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def)
Check if any of the subranges of LI contain a definition at Def.
static cl::opt< unsigned > LargeIntervalFreqThreshold("large-interval-freq-threshold", cl::Hidden, cl::desc("For a large interval, if it is coalesed with other live " "intervals many times more than the threshold, stop its " "coalescing to control the compile time. "), cl::init(256))
static std::pair< bool, bool > addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo, const LiveRange &Src, const VNInfo *SrcValNo)
Copy segments with value number SrcValNo from liverange Src to live range @Dst and use value number D...
static bool isLiveThrough(const LiveQueryResult Q)
static bool isTerminalReg(Register DstReg, const MachineInstr &Copy, const MachineRegisterInfo *MRI)
Check if DstReg is a terminal node.
static cl::opt< bool > VerifyCoalescing("verify-coalescing", cl::desc("Verify machine instrs before and after register coalescing"), cl::Hidden)
register Register static false bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, Register &Src, Register &Dst, unsigned &SrcSub, unsigned &DstSub)
static cl::opt< bool > EnableJoinSplits("join-splitedges", cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden)
Temporary flag to test critical edge unsplitting.
static cl::opt< bool > EnableJoining("join-liveintervals", cl::desc("Coalesce copies (default=true)"), cl::init(true), cl::Hidden)
static bool definesFullReg(const MachineInstr &MI, Register Reg)
Returns true if MI defines the full vreg Reg, as opposed to just defining a subregister.
static cl::opt< unsigned > LateRematUpdateThreshold("late-remat-update-threshold", cl::Hidden, cl::desc("During rematerialization for a copy, if the def instruction has " "many other copy uses to be rematerialized, delay the multiple " "separate live interval update work and do them all at once after " "all those rematerialization are done. It will save a lot of " "repeated work. "), cl::init(100))
static cl::opt< bool > UseTerminalRule("terminal-rule", cl::desc("Apply the terminal rule"), cl::init(false), cl::Hidden)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static DenseMap< Register, std::vector< std::pair< SlotIndex, MachineInstr * > > > buildVRegToDbgValueMap(MachineFunction &MF, const LiveIntervals *Liveness)
static void shrinkToUses(LiveInterval &LI, LiveIntervals &LIS)
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
bool test(unsigned Idx) const
Allocate memory in an ever growing pool, as if by bump-pointer.
A helper class for register coalescers.
bool flip()
Swap SrcReg and DstReg.
bool isCoalescable(const MachineInstr *) const
Return true if MI is a copy instruction that will become an identity copy after coalescing.
bool setRegisters(const MachineInstr *)
Set registers to match the copy instruction MI.
This class represents an Operation in the Expression.
The location of a single variable, composed of an expression and 0 or more DbgValueLocEntries.
iterator find(const_arg_type_t< KeyT > Val)
bool erase(const KeyT &Val)
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
bool isAsCheapAsAMove(const MachineInstr &MI) const override
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
bool hasSubRanges() const
Returns true if subregister liveness information is available.
SubRange * createSubRangeFrom(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, const LiveRange &CopyFrom)
Like createSubRange() but the new range is filled with a copy of the liveness information in CopyFrom...
iterator_range< subrange_iterator > subranges()
void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, std::function< void(LiveInterval::SubRange &)> Apply, const SlotIndexes &Indexes, const TargetRegisterInfo &TRI, unsigned ComposeSubRegIdx=0)
Refines the subranges to support LaneMask.
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
void clearSubRanges()
Removes all subregister liveness information.
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const
Returns true if VNI is killed by any PHI-def values in LI.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
void pruneValue(LiveRange &LR, SlotIndex Kill, SmallVectorImpl< SlotIndex > *EndPoints)
If LR has a live value at Kill, prune its live range by removing any liveness reachable from Kill.
void removeInterval(Register Reg)
Interval removal.
MachineBasicBlock * intervalIsInOneMBB(const LiveInterval &LI) const
If LI is confined to a single basic block, return a pointer to that block.
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
void extendToIndices(LiveRange &LR, ArrayRef< SlotIndex > Indices, ArrayRef< SlotIndex > Undefs)
Extend the live range LR to reach all points in Indices.
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
VNInfo * valueOutOrDead() const
Returns the value alive at the end of the instruction, if any.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
VNInfo * valueDefined() const
Return the value defined by this instruction, if any.
SlotIndex endPoint() const
Return the end point of the last live range segment to interact with the instruction,...
bool isKill() const
Return true if the live-in value is killed by this instruction.
Callback methods for LiveRangeEdit owners.
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< Register > RegsBeingSpilled=std::nullopt)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false, unsigned SubIdx=0, MachineInstr *ReplaceIndexMI=nullptr)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
void join(LiveRange &Other, const int *ValNoAssignments, const int *RHSValNoAssignments, SmallVectorImpl< VNInfo * > &NewVNInfo)
join - Join two live ranges (this, and other) together.
bool liveAt(SlotIndex index) const
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
void removeValNo(VNInfo *ValNo)
removeValNo - Remove all the segments defined by the specified value#.
void verify() const
Walk the range and assert if any invariants fail to hold.
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
VNInfo * MergeValueNumberInto(VNInfo *V1, VNInfo *V2)
MergeValueNumberInto - This method is called when two value numbers are found to be equivalent.
unsigned getNumValNums() const
bool containsOneValue() const
iterator FindSegmentContaining(SlotIndex Idx)
Return an iterator to the segment that contains the specified index, or end() if there is none.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
Wrapper class representing physical registers. Should be passed by value.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool hasEHPadSuccessor() const
bool isEHPad() const
Returns true if the block is a landing pad.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
iterator_range< pred_iterator > predecessors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual MachineFunctionProperties getClearedProperties() const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool exposesReturnsTwice() const
exposesReturnsTwice - Returns true if the function calls setjmp or any other similar functions with a...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isImplicitDef() const
const MachineBasicBlock * getParent() const
bool isCopyLike() const
Return true if the instruction behaves like a copy.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool isDebugInstr() const
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx=nullptr) const
Given the index of a register def operand, check if the register def is tied to a source operand,...
int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isKill=false) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
bool isCommutable(QueryType Type=IgnoreBundle) const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
iterator_range< mop_iterator > operands()
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
iterator_range< filtered_mop_iterator > all_defs()
Returns an iterator range over all operands that are (explicit or implicit) register defs.
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
void setDebugLoc(DebugLoc DL)
Replace current source information with new such.
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsUndef(bool Val=true)
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
defusechain_iterator - This class provides iterator support for machine operands in the function that...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
virtual void releaseMemory()
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
bool isProperSubClass(const TargetRegisterClass *RC) const
isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isValid() const
Returns true if this is a valid index.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Returns the basic block which the given index falls in.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
SlotIndex getNextNonNullIndex(SlotIndex Index)
Returns the next non-null index, if one exists.
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
SlotIndex getIndexBefore(const MachineInstr &MI) const
getIndexBefore - Returns the index of the last indexed instruction before MI, or the start index of i...
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction for the given index, or null if the given index has no instruction associated...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
pointer data()
Return a pointer to the vector's buffer, even if empty().
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
static const unsigned CommuteAnyOperandIndex
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual bool enableJoinGlobalCopies() const
True if the subtarget should enable joining global copies.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
VNInfo - Value Number Information.
void markUnused()
Mark this value as unused.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
void initializeRegisterCoalescerPass(PassRegistry &)
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static constexpr LaneBitmask getLane(unsigned Lane)
static constexpr LaneBitmask getAll()
constexpr bool any() const
static constexpr LaneBitmask getNone()
Remat - Information needed to rematerialize at a specific location.
This represents a simple continuous liveness interval for a value.