LLVM  15.0.0git
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
15 #include "RISCV.h"
17 #include "RISCVTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/InitializePasses.h"
33 #include "llvm/MC/TargetRegistry.h"
36 #include "llvm/Transforms/IPO.h"
37 using namespace llvm;
38 
40  "riscv-enable-copyelim",
41  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
42  cl::Hidden);
43 
47  auto *PR = PassRegistry::getPassRegistry();
54 }
55 
56 static StringRef computeDataLayout(const Triple &TT) {
57  if (TT.isArch64Bit())
58  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
59  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
60  return "e-m:e-p:32:32-i64:64-n32-S128";
61 }
62 
65  if (!RM.hasValue())
66  return Reloc::Static;
67  return *RM;
68 }
69 
71  StringRef CPU, StringRef FS,
72  const TargetOptions &Options,
75  CodeGenOpt::Level OL, bool JIT)
79  TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
80  initAsmInfo();
81 
82  // RISC-V supports the MachineOutliner.
83  setMachineOutliner(true);
85 }
86 
87 const RISCVSubtarget *
89  Attribute CPUAttr = F.getFnAttribute("target-cpu");
90  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
91  Attribute FSAttr = F.getFnAttribute("target-features");
92 
93  std::string CPU =
94  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
95  std::string TuneCPU =
96  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
97  std::string FS =
98  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
99  std::string Key = CPU + TuneCPU + FS;
100  auto &I = SubtargetMap[Key];
101  if (!I) {
102  // This needs to be done before we create a new subtarget since any
103  // creation will depend on the TM and the code generation flags on the
104  // function that reside in TargetOptions.
106  auto ABIName = Options.MCOptions.getABIName();
107  if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
108  F.getParent()->getModuleFlag("target-abi"))) {
109  auto TargetABI = RISCVABI::getTargetABI(ABIName);
110  if (TargetABI != RISCVABI::ABI_Unknown &&
111  ModuleTargetABI->getString() != ABIName) {
112  report_fatal_error("-target-abi option != target-abi module flag");
113  }
114  ABIName = ModuleTargetABI->getString();
115  }
116  I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
117  }
118  return I.get();
119 }
120 
123  return TargetTransformInfo(RISCVTTIImpl(this, F));
124 }
125 
126 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
127 // for all memory accesses, so it is reasonable to assume that an
128 // implementation has no-op address space casts. If an implementation makes a
129 // change to this, they can override it here.
131  unsigned DstAS) const {
132  return true;
133 }
134 
135 namespace {
136 class RISCVPassConfig : public TargetPassConfig {
137 public:
138  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
139  : TargetPassConfig(TM, PM) {}
140 
141  RISCVTargetMachine &getRISCVTargetMachine() const {
142  return getTM<RISCVTargetMachine>();
143  }
144 
145  void addIRPasses() override;
146  bool addPreISel() override;
147  bool addInstSelector() override;
148  bool addIRTranslator() override;
149  bool addLegalizeMachineIR() override;
150  bool addRegBankSelect() override;
151  bool addGlobalInstructionSelect() override;
152  void addPreEmitPass() override;
153  void addPreEmitPass2() override;
154  void addPreSched2() override;
155  void addMachineSSAOptimization() override;
156  void addPreRegAlloc() override;
157  void addPostRegAlloc() override;
158 };
159 } // namespace
160 
162  return new RISCVPassConfig(*this, PM);
163 }
164 
165 void RISCVPassConfig::addIRPasses() {
166  addPass(createAtomicExpandPass());
167 
169 
171 }
172 
173 bool RISCVPassConfig::addPreISel() {
174  if (TM->getOptLevel() != CodeGenOpt::None) {
175  // Add a barrier before instruction selection so that we will not get
176  // deleted block address after enabling default outlining. See D99707 for
177  // more details.
178  addPass(createBarrierNoopPass());
179  }
180  return false;
181 }
182 
183 bool RISCVPassConfig::addInstSelector() {
184  addPass(createRISCVISelDag(getRISCVTargetMachine()));
185 
186  return false;
187 }
188 
189 bool RISCVPassConfig::addIRTranslator() {
190  addPass(new IRTranslator(getOptLevel()));
191  return false;
192 }
193 
194 bool RISCVPassConfig::addLegalizeMachineIR() {
195  addPass(new Legalizer());
196  return false;
197 }
198 
199 bool RISCVPassConfig::addRegBankSelect() {
200  addPass(new RegBankSelect());
201  return false;
202 }
203 
204 bool RISCVPassConfig::addGlobalInstructionSelect() {
205  addPass(new InstructionSelect(getOptLevel()));
206  return false;
207 }
208 
209 void RISCVPassConfig::addPreSched2() {}
210 
211 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
212 
213 void RISCVPassConfig::addPreEmitPass2() {
214  addPass(createRISCVExpandPseudoPass());
215  // Schedule the expansion of AMOs at the last possible moment, avoiding the
216  // possibility for other passes to break the requirements for forward
217  // progress in the LR/SC block.
219 }
220 
221 void RISCVPassConfig::addMachineSSAOptimization() {
223 
224  if (TM->getTargetTriple().getArch() == Triple::riscv64)
225  addPass(createRISCVSExtWRemovalPass());
226 }
227 
228 void RISCVPassConfig::addPreRegAlloc() {
229  if (TM->getOptLevel() != CodeGenOpt::None)
231  addPass(createRISCVInsertVSETVLIPass());
232 }
233 
234 void RISCVPassConfig::addPostRegAlloc() {
235  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
237 }
238 
241  return new yaml::RISCVMachineFunctionInfo();
242 }
243 
246  const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
247  return new yaml::RISCVMachineFunctionInfo(*MFI);
248 }
249 
252  SMDiagnostic &Error, SMRange &SourceRange) const {
253  const auto &YamlMFI =
254  static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
255  PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
256  return false;
257 }
llvm::Triple::riscv64
@ riscv64
Definition: Triple.h:76
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:169
llvm::RISCVTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: RISCVTargetMachine.cpp:250
llvm::RISCVTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: RISCVTargetMachine.cpp:245
llvm::RISCVTTIImpl
Definition: RISCVTargetTransformInfo.h:28
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:72
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::RISCVTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: RISCVTargetMachine.cpp:161
T
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:52
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:676
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MCTargetOptions::getABIName
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
Definition: MCTargetOptions.cpp:22
llvm::createRISCVInsertVSETVLIPass
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
Definition: RISCVInsertVSETVLI.cpp:1363
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::createRISCVMergeBaseOffsetOptPass
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Definition: RISCVMergeBaseOffset.cpp:291
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::createRISCVExpandAtomicPseudoPass
FunctionPass * createRISCVExpandAtomicPseudoPass()
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:253
InstructionSelect.h
llvm::Optional< Reloc::Model >
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::RISCVTargetMachine::getSubtargetImpl
const RISCVSubtarget * getSubtargetImpl() const =delete
llvm::initializeRISCVMergeBaseOffsetOptPass
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
STLExtras.h
llvm::initializeRISCVExpandPseudoPass
void initializeRISCVExpandPseudoPass(PassRegistry &)
llvm::RISCVTargetMachine::RISCVTargetMachine
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: RISCVTargetMachine.cpp:70
LegacyPassManager.h
llvm::RISCVELFTargetObjectFile
This implementation is used for RISCV ELF targets.
Definition: RISCVTargetObjectFile.h:17
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: RISCVTargetMachine.cpp:56
llvm::RISCVTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: RISCVTargetMachine.cpp:240
FormattedStream.h
MIRYamlMapping.h
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:250
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::Legalizer
Definition: Legalizer.h:36
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
RISCVTargetObjectFile.h
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::TargetOptions::MCOptions
MCTargetOptions MCOptions
Machine level options.
Definition: TargetOptions.h:442
llvm::initializeRISCVSExtWRemovalPass
void initializeRISCVSExtWRemovalPass(PassRegistry &)
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1296
LLVMInitializeRISCVTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
Definition: RISCVTargetMachine.cpp:44
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:305
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::initializeRISCVGatherScatterLoweringPass
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
IPO.h
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
TargetPassConfig.h
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:481
llvm::createRISCVGatherScatterLoweringPass
FunctionPass * createRISCVGatherScatterLoweringPass()
llvm::createRISCVISelDag
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM)
Definition: RISCVISelDAGToDAG.cpp:2434
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
IRTranslator.h
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:497
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::createRISCVSExtWRemovalPass
FunctionPass * createRISCVSExtWRemovalPass()
std
Definition: BitVector.h:851
llvm::createRISCVRedundantCopyEliminationPass
FunctionPass * createRISCVRedundantCopyEliminationPass()
Definition: RISCVRedundantCopyElimination.cpp:177
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1303
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
RegBankSelect.h
llvm::yaml::RISCVMachineFunctionInfo
Definition: RISCVMachineFunctionInfo.h:26
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:405
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
RISCVBaseInfo.h
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:118
Legalizer.h
llvm::initializeRISCVInsertVSETVLIPass
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
llvm::RISCVTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: RISCVTargetMachine.cpp:122
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:355
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
RISCVMachineFunctionInfo.h
TargetTransformInfo.h
llvm::RISCVTargetMachine::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: RISCVTargetMachine.cpp:130
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
RISCVTargetInfo.h
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::cl::desc
Definition: CommandLine.h:405
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::MDString
A single uniqued string.
Definition: Metadata.h:612
RISCVTargetTransformInfo.h
TargetRegistry.h
InitializePasses.h
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
MIParser.h
TargetLoweringObjectFileImpl.h
RISCVTargetMachine.h