LLVM 18.0.0git
RISCVTargetMachine.cpp
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1//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISC-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
15#include "RISCV.h"
17#include "RISCVMacroFusion.h"
21#include "llvm/ADT/STLExtras.h"
29#include "llvm/CodeGen/Passes.h"
36#include "llvm/Transforms/IPO.h"
37#include <optional>
38using namespace llvm;
39
41 "riscv-enable-copyelim",
42 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
44
45// FIXME: Unify control over GlobalMerge.
47 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
48 cl::desc("Enable the global merge pass"));
49
50static cl::opt<bool>
51 EnableMachineCombiner("riscv-enable-machine-combiner",
52 cl::desc("Enable the machine combiner pass"),
53 cl::init(true), cl::Hidden);
54
56 "riscv-v-vector-bits-max",
57 cl::desc("Assume V extension vector registers are at most this big, "
58 "with zero meaning no maximum size is assumed."),
60
62 "riscv-v-vector-bits-min",
63 cl::desc("Assume V extension vector registers are at least this big, "
64 "with zero meaning no minimum size is assumed. A value of -1 "
65 "means use Zvl*b extension. This is primarily used to enable "
66 "autovectorization with fixed width vectors."),
67 cl::init(-1), cl::Hidden);
68
70 "riscv-enable-copy-propagation",
71 cl::desc("Enable the copy propagation with RISC-V copy instr"),
72 cl::init(true), cl::Hidden);
73
75 "riscv-enable-dead-defs", cl::Hidden,
76 cl::desc("Enable the pass that removes dead"
77 " definitons and replaces stores to"
78 " them with stores to x0"),
79 cl::init(true));
80
103}
104
106 if (TT.isArch64Bit())
107 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
108 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
109 return "e-m:e-p:32:32-i64:64-n32-S128";
110}
111
113 std::optional<Reloc::Model> RM) {
114 return RM.value_or(Reloc::Static);
115}
116
118 StringRef CPU, StringRef FS,
119 const TargetOptions &Options,
120 std::optional<Reloc::Model> RM,
121 std::optional<CodeModel::Model> CM,
122 CodeGenOptLevel OL, bool JIT)
123 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
125 getEffectiveCodeModel(CM, CodeModel::Small), OL),
126 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
127 initAsmInfo();
128
129 // RISC-V supports the MachineOutliner.
130 setMachineOutliner(true);
132
133 if (TT.isOSFuchsia() && !TT.isArch64Bit())
134 report_fatal_error("Fuchsia is only supported for 64-bit");
135}
136
137const RISCVSubtarget *
139 Attribute CPUAttr = F.getFnAttribute("target-cpu");
140 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
141 Attribute FSAttr = F.getFnAttribute("target-features");
142
143 std::string CPU =
144 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
145 std::string TuneCPU =
146 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
147 std::string FS =
148 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
149
150 unsigned RVVBitsMin = RVVVectorBitsMinOpt;
151 unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
152
153 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
154 if (VScaleRangeAttr.isValid()) {
155 if (!RVVVectorBitsMinOpt.getNumOccurrences())
156 RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
157 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
158 if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
159 RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
160 }
161
162 if (RVVBitsMin != -1U) {
163 // FIXME: Change to >= 32 when VLEN = 32 is supported.
164 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
165 isPowerOf2_32(RVVBitsMin))) &&
166 "V or Zve* extension requires vector length to be in the range of "
167 "64 to 65536 and a power 2!");
168 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
169 "Minimum V extension vector length should not be larger than its "
170 "maximum!");
171 }
172 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
173 isPowerOf2_32(RVVBitsMax))) &&
174 "V or Zve* extension requires vector length to be in the range of "
175 "64 to 65536 and a power 2!");
176
177 if (RVVBitsMin != -1U) {
178 if (RVVBitsMax != 0) {
179 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
180 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
181 }
182
183 RVVBitsMin = llvm::bit_floor(
184 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
185 }
186 RVVBitsMax =
187 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
188
190 Key += "RVVMin";
191 Key += std::to_string(RVVBitsMin);
192 Key += "RVVMax";
193 Key += std::to_string(RVVBitsMax);
194 Key += CPU;
195 Key += TuneCPU;
196 Key += FS;
197 auto &I = SubtargetMap[Key];
198 if (!I) {
199 // This needs to be done before we create a new subtarget since any
200 // creation will depend on the TM and the code generation flags on the
201 // function that reside in TargetOptions.
203 auto ABIName = Options.MCOptions.getABIName();
204 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
205 F.getParent()->getModuleFlag("target-abi"))) {
206 auto TargetABI = RISCVABI::getTargetABI(ABIName);
207 if (TargetABI != RISCVABI::ABI_Unknown &&
208 ModuleTargetABI->getString() != ABIName) {
209 report_fatal_error("-target-abi option != target-abi module flag");
210 }
211 ABIName = ModuleTargetABI->getString();
212 }
213 I = std::make_unique<RISCVSubtarget>(
214 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
215 }
216 return I.get();
217}
218
220 BumpPtrAllocator &Allocator, const Function &F,
221 const TargetSubtargetInfo *STI) const {
222 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
223 F, STI);
224}
225
228 return TargetTransformInfo(RISCVTTIImpl(this, F));
229}
230
231// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
232// for all memory accesses, so it is reasonable to assume that an
233// implementation has no-op address space casts. If an implementation makes a
234// change to this, they can override it here.
236 unsigned DstAS) const {
237 return true;
238}
239
240namespace {
241class RISCVPassConfig : public TargetPassConfig {
242public:
243 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
244 : TargetPassConfig(TM, PM) {}
245
246 RISCVTargetMachine &getRISCVTargetMachine() const {
247 return getTM<RISCVTargetMachine>();
248 }
249
251 createMachineScheduler(MachineSchedContext *C) const override {
252 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
253 if (ST.hasMacroFusion()) {
256 return DAG;
257 }
258 return nullptr;
259 }
260
262 createPostMachineScheduler(MachineSchedContext *C) const override {
263 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
264 if (ST.hasMacroFusion()) {
267 return DAG;
268 }
269 return nullptr;
270 }
271
272 void addIRPasses() override;
273 bool addPreISel() override;
274 bool addInstSelector() override;
275 bool addIRTranslator() override;
276 void addPreLegalizeMachineIR() override;
277 bool addLegalizeMachineIR() override;
278 bool addRegBankSelect() override;
279 bool addGlobalInstructionSelect() override;
280 void addPreEmitPass() override;
281 void addPreEmitPass2() override;
282 void addPreSched2() override;
283 void addMachineSSAOptimization() override;
284 void addPreRegAlloc() override;
285 void addPostRegAlloc() override;
286 void addOptimizedRegAlloc() override;
287 void addFastRegAlloc() override;
288};
289} // namespace
290
292 return new RISCVPassConfig(*this, PM);
293}
294
295void RISCVPassConfig::addIRPasses() {
296 addPass(createAtomicExpandPass());
297
298 if (getOptLevel() != CodeGenOptLevel::None) {
302 }
303
305}
306
307bool RISCVPassConfig::addPreISel() {
308 if (TM->getOptLevel() != CodeGenOptLevel::None) {
309 // Add a barrier before instruction selection so that we will not get
310 // deleted block address after enabling default outlining. See D99707 for
311 // more details.
312 addPass(createBarrierNoopPass());
313 }
314
316 addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
317 /* OnlyOptimizeForSize */ false,
318 /* MergeExternalByDefault */ true));
319 }
320
321 return false;
322}
323
324bool RISCVPassConfig::addInstSelector() {
325 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
326
327 return false;
328}
329
330bool RISCVPassConfig::addIRTranslator() {
331 addPass(new IRTranslator(getOptLevel()));
332 return false;
333}
334
335void RISCVPassConfig::addPreLegalizeMachineIR() {
336 if (getOptLevel() == CodeGenOptLevel::None) {
338 } else {
340 }
341}
342
343bool RISCVPassConfig::addLegalizeMachineIR() {
344 addPass(new Legalizer());
345 return false;
346}
347
348bool RISCVPassConfig::addRegBankSelect() {
349 addPass(new RegBankSelect());
350 return false;
351}
352
353bool RISCVPassConfig::addGlobalInstructionSelect() {
354 addPass(new InstructionSelect(getOptLevel()));
355 return false;
356}
357
358void RISCVPassConfig::addPreSched2() {
359 // Emit KCFI checks for indirect calls.
360 addPass(createKCFIPass());
361}
362
363void RISCVPassConfig::addPreEmitPass() {
364 addPass(&BranchRelaxationPassID);
366
367 // TODO: It would potentially be better to schedule copy propagation after
368 // expanding pseudos (in addPreEmitPass2). However, performing copy
369 // propagation after the machine outliner (which runs after addPreEmitPass)
370 // currently leads to incorrect code-gen, where copies to registers within
371 // outlined functions are removed erroneously.
372 if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
375}
376
377void RISCVPassConfig::addPreEmitPass2() {
378 if (TM->getOptLevel() != CodeGenOptLevel::None) {
379 addPass(createRISCVMoveMergePass());
380 // Schedule PushPop Optimization before expansion of Pseudo instruction,
381 // ensuring return instruction is detected correctly.
383 }
385
386 // Schedule the expansion of AMOs at the last possible moment, avoiding the
387 // possibility for other passes to break the requirements for forward
388 // progress in the LR/SC block.
390
391 // KCFI indirect call checks are lowered to a bundle.
392 addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
393 return MF.getFunction().getParent()->getModuleFlag("kcfi");
394 }));
395}
396
397void RISCVPassConfig::addMachineSSAOptimization() {
400 addPass(&MachineCombinerID);
401
402 if (TM->getTargetTriple().getArch() == Triple::riscv64) {
403 addPass(createRISCVOptWInstrsPass());
404 }
405}
406
407void RISCVPassConfig::addPreRegAlloc() {
409 if (TM->getOptLevel() != CodeGenOptLevel::None)
412 if (TM->getOptLevel() != CodeGenOptLevel::None &&
416}
417
418void RISCVPassConfig::addOptimizedRegAlloc() {
419 insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
420
422}
423
424void RISCVPassConfig::addFastRegAlloc() {
425 addPass(createRISCVInitUndefPass());
427}
428
429
430void RISCVPassConfig::addPostRegAlloc() {
431 if (TM->getOptLevel() != CodeGenOptLevel::None &&
434}
435
439}
440
443 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
444 return new yaml::RISCVMachineFunctionInfo(*MFI);
445}
446
449 SMDiagnostic &Error, SMRange &SourceRange) const {
450 const auto &YamlMFI =
451 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
452 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
453 return false;
454}
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static const Function * getParent(const Value *V)
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:381
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:375
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
A single uniqued string.
Definition: Metadata.h:611
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
void initializeRISCVInitUndefPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
FunctionPass * createRISCVPreLegalizerCombiner()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVO0PreLegalizerCombiner()
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createRISCVOptWInstrsPass()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeRISCVOptWInstrsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeKCFIPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createRISCVInitUndefPass()
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition: bit.h:291
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
char & RISCVInitUndefID
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.