LLVM 17.0.0git
RISCVTargetMachine.cpp
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1//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISC-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
15#include "RISCV.h"
17#include "RISCVMacroFusion.h"
21#include "llvm/ADT/STLExtras.h"
29#include "llvm/CodeGen/Passes.h"
36#include "llvm/Transforms/IPO.h"
37#include <optional>
38using namespace llvm;
39
41 "riscv-enable-copyelim",
42 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
44
45// FIXME: Unify control over GlobalMerge.
47 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
48 cl::desc("Enable the global merge pass"));
49
50static cl::opt<bool>
51 EnableMachineCombiner("riscv-enable-machine-combiner",
52 cl::desc("Enable the machine combiner pass"),
53 cl::init(true), cl::Hidden);
54
56 "riscv-v-vector-bits-max",
57 cl::desc("Assume V extension vector registers are at most this big, "
58 "with zero meaning no maximum size is assumed."),
60
62 "riscv-v-vector-bits-min",
63 cl::desc("Assume V extension vector registers are at least this big, "
64 "with zero meaning no minimum size is assumed. A value of -1 "
65 "means use Zvl*b extension. This is primarily used to enable "
66 "autovectorization with fixed width vectors."),
67 cl::init(-1), cl::Hidden);
68
70 "riscv-enable-copy-propagation",
71 cl::desc("Enable the copy propagation with RISC-V copy instr"),
72 cl::init(true), cl::Hidden);
73
90}
91
93 if (TT.isArch64Bit())
94 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
95 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
96 return "e-m:e-p:32:32-i64:64-n32-S128";
97}
98
100 std::optional<Reloc::Model> RM) {
101 return RM.value_or(Reloc::Static);
102}
103
105 StringRef CPU, StringRef FS,
106 const TargetOptions &Options,
107 std::optional<Reloc::Model> RM,
108 std::optional<CodeModel::Model> CM,
109 CodeGenOpt::Level OL, bool JIT)
110 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
112 getEffectiveCodeModel(CM, CodeModel::Small), OL),
113 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
114 initAsmInfo();
115
116 // RISC-V supports the MachineOutliner.
117 setMachineOutliner(true);
119
120 if (TT.isOSFuchsia() && !TT.isArch64Bit())
121 report_fatal_error("Fuchsia is only supported for 64-bit");
122}
123
124const RISCVSubtarget *
126 Attribute CPUAttr = F.getFnAttribute("target-cpu");
127 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
128 Attribute FSAttr = F.getFnAttribute("target-features");
129
130 std::string CPU =
131 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
132 std::string TuneCPU =
133 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
134 std::string FS =
135 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
136
137 unsigned RVVBitsMin = RVVVectorBitsMinOpt;
138 unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
139
140 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
141 if (VScaleRangeAttr.isValid()) {
142 if (!RVVVectorBitsMinOpt.getNumOccurrences())
143 RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
144 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
145 if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
146 RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
147 }
148
149 if (RVVBitsMin != -1U) {
150 // FIXME: Change to >= 32 when VLEN = 32 is supported.
151 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
152 isPowerOf2_32(RVVBitsMin))) &&
153 "V or Zve* extension requires vector length to be in the range of "
154 "64 to 65536 and a power 2!");
155 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
156 "Minimum V extension vector length should not be larger than its "
157 "maximum!");
158 }
159 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
160 isPowerOf2_32(RVVBitsMax))) &&
161 "V or Zve* extension requires vector length to be in the range of "
162 "64 to 65536 and a power 2!");
163
164 if (RVVBitsMin != -1U) {
165 if (RVVBitsMax != 0) {
166 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
167 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
168 }
169
170 RVVBitsMin = llvm::bit_floor(
171 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
172 }
173 RVVBitsMax =
174 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
175
177 Key += "RVVMin";
178 Key += std::to_string(RVVBitsMin);
179 Key += "RVVMax";
180 Key += std::to_string(RVVBitsMax);
181 Key += CPU;
182 Key += TuneCPU;
183 Key += FS;
184 auto &I = SubtargetMap[Key];
185 if (!I) {
186 // This needs to be done before we create a new subtarget since any
187 // creation will depend on the TM and the code generation flags on the
188 // function that reside in TargetOptions.
190 auto ABIName = Options.MCOptions.getABIName();
191 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
192 F.getParent()->getModuleFlag("target-abi"))) {
193 auto TargetABI = RISCVABI::getTargetABI(ABIName);
194 if (TargetABI != RISCVABI::ABI_Unknown &&
195 ModuleTargetABI->getString() != ABIName) {
196 report_fatal_error("-target-abi option != target-abi module flag");
197 }
198 ABIName = ModuleTargetABI->getString();
199 }
200 I = std::make_unique<RISCVSubtarget>(
201 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
202 }
203 return I.get();
204}
205
207 BumpPtrAllocator &Allocator, const Function &F,
208 const TargetSubtargetInfo *STI) const {
209 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
210 F, STI);
211}
212
215 return TargetTransformInfo(RISCVTTIImpl(this, F));
216}
217
218// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
219// for all memory accesses, so it is reasonable to assume that an
220// implementation has no-op address space casts. If an implementation makes a
221// change to this, they can override it here.
223 unsigned DstAS) const {
224 return true;
225}
226
227namespace {
228class RISCVPassConfig : public TargetPassConfig {
229public:
230 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
231 : TargetPassConfig(TM, PM) {}
232
233 RISCVTargetMachine &getRISCVTargetMachine() const {
234 return getTM<RISCVTargetMachine>();
235 }
236
238 createMachineScheduler(MachineSchedContext *C) const override {
239 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
240 if (ST.hasMacroFusion()) {
243 return DAG;
244 }
245 return nullptr;
246 }
247
249 createPostMachineScheduler(MachineSchedContext *C) const override {
250 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
251 if (ST.hasMacroFusion()) {
254 return DAG;
255 }
256 return nullptr;
257 }
258
259 void addIRPasses() override;
260 bool addPreISel() override;
261 bool addInstSelector() override;
262 bool addIRTranslator() override;
263 bool addLegalizeMachineIR() override;
264 bool addRegBankSelect() override;
265 bool addGlobalInstructionSelect() override;
266 void addPreEmitPass() override;
267 void addPreEmitPass2() override;
268 void addPreSched2() override;
269 void addMachineSSAOptimization() override;
270 void addPreRegAlloc() override;
271 void addPostRegAlloc() override;
272 void addOptimizedRegAlloc() override;
273};
274} // namespace
275
277 return new RISCVPassConfig(*this, PM);
278}
279
280void RISCVPassConfig::addIRPasses() {
281 addPass(createAtomicExpandPass());
282
283 if (getOptLevel() != CodeGenOpt::None)
285
286 if (getOptLevel() != CodeGenOpt::None)
288
290}
291
292bool RISCVPassConfig::addPreISel() {
293 if (TM->getOptLevel() != CodeGenOpt::None) {
294 // Add a barrier before instruction selection so that we will not get
295 // deleted block address after enabling default outlining. See D99707 for
296 // more details.
297 addPass(createBarrierNoopPass());
298 }
299
301 addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
302 /* OnlyOptimizeForSize */ false,
303 /* MergeExternalByDefault */ true));
304 }
305
306 return false;
307}
308
309bool RISCVPassConfig::addInstSelector() {
310 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
311
312 return false;
313}
314
315bool RISCVPassConfig::addIRTranslator() {
316 addPass(new IRTranslator(getOptLevel()));
317 return false;
318}
319
320bool RISCVPassConfig::addLegalizeMachineIR() {
321 addPass(new Legalizer());
322 return false;
323}
324
325bool RISCVPassConfig::addRegBankSelect() {
326 addPass(new RegBankSelect());
327 return false;
328}
329
330bool RISCVPassConfig::addGlobalInstructionSelect() {
331 addPass(new InstructionSelect(getOptLevel()));
332 return false;
333}
334
335void RISCVPassConfig::addPreSched2() {}
336
337void RISCVPassConfig::addPreEmitPass() {
338 addPass(&BranchRelaxationPassID);
340
341 // TODO: It would potentially be better to schedule copy propagation after
342 // expanding pseudos (in addPreEmitPass2). However, performing copy
343 // propagation after the machine outliner (which runs after addPreEmitPass)
344 // currently leads to incorrect code-gen, where copies to registers within
345 // outlined functions are removed erroneously.
346 if (TM->getOptLevel() >= CodeGenOpt::Default && EnableRISCVCopyPropagation)
348}
349
350void RISCVPassConfig::addPreEmitPass2() {
352
353 // Schedule the expansion of AMOs at the last possible moment, avoiding the
354 // possibility for other passes to break the requirements for forward
355 // progress in the LR/SC block.
357}
358
359void RISCVPassConfig::addMachineSSAOptimization() {
362 addPass(&MachineCombinerID);
363
364 if (TM->getTargetTriple().getArch() == Triple::riscv64) {
367 }
368}
369
370void RISCVPassConfig::addPreRegAlloc() {
372 if (TM->getOptLevel() != CodeGenOpt::None)
375}
376
377void RISCVPassConfig::addOptimizedRegAlloc() {
378 if (getOptimizeRegAlloc())
379 insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
380
382}
383
384void RISCVPassConfig::addPostRegAlloc() {
385 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
387}
388
392}
393
396 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
397 return new yaml::RISCVMachineFunctionInfo(*MFI);
398}
399
402 SMDiagnostic &Error, SMRange &SourceRange) const {
403 const auto &YamlMFI =
404 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
405 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
406 return false;
407}
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:380
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:374
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:317
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:187
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
A single uniqued string.
Definition: Metadata.h:611
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ Default
-O2, -Os
Definition: CodeGen.h:60
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeRISCVExpandPseudoPass(PassRegistry &)
void initializeRISCVSExtWRemovalPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createRISCVStripWSuffixPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
void initializeRISCVInitUndefPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:292
void initializeRISCVStripWSuffixPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVSExtWRemovalPass()
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition: bit.h:291
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
char & RISCVInitUndefID
Definition: BitVector.h:858
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.