LLVM 19.0.0git
RISCVTargetMachine.cpp
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1//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISC-V ----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about RISC-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVTargetMachine.h"
15#include "RISCV.h"
20#include "llvm/ADT/STLExtras.h"
30#include "llvm/CodeGen/Passes.h"
39#include "llvm/Transforms/IPO.h"
42#include <optional>
43using namespace llvm;
44
46 "riscv-enable-copyelim",
47 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
49
50// FIXME: Unify control over GlobalMerge.
52 EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
53 cl::desc("Enable the global merge pass"));
54
55static cl::opt<bool>
56 EnableMachineCombiner("riscv-enable-machine-combiner",
57 cl::desc("Enable the machine combiner pass"),
58 cl::init(true), cl::Hidden);
59
61 "riscv-v-vector-bits-max",
62 cl::desc("Assume V extension vector registers are at most this big, "
63 "with zero meaning no maximum size is assumed."),
65
67 "riscv-v-vector-bits-min",
68 cl::desc("Assume V extension vector registers are at least this big, "
69 "with zero meaning no minimum size is assumed. A value of -1 "
70 "means use Zvl*b extension. This is primarily used to enable "
71 "autovectorization with fixed width vectors."),
72 cl::init(-1), cl::Hidden);
73
75 "riscv-enable-copy-propagation",
76 cl::desc("Enable the copy propagation with RISC-V copy instr"),
77 cl::init(true), cl::Hidden);
78
80 "riscv-enable-dead-defs", cl::Hidden,
81 cl::desc("Enable the pass that removes dead"
82 " definitons and replaces stores to"
83 " them with stores to x0"),
84 cl::init(true));
85
86static cl::opt<bool>
87 EnableSinkFold("riscv-enable-sink-fold",
88 cl::desc("Enable sinking and folding of instruction copies"),
89 cl::init(true), cl::Hidden);
90
91static cl::opt<bool>
92 EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden,
93 cl::desc("Enable the loop data prefetch pass"),
94 cl::init(true));
95
97 "riscv-misched-load-clustering", cl::Hidden,
98 cl::desc("Enable load clustering in the machine scheduler"),
99 cl::init(false));
100
102 "riscv-vsetvl-after-rvv-regalloc", cl::Hidden,
103 cl::desc("Insert vsetvls after vector register allocation"),
104 cl::init(true));
105
131}
132
134 const TargetOptions &Options) {
135 StringRef ABIName = Options.MCOptions.getABIName();
136 if (TT.isArch64Bit()) {
137 if (ABIName == "lp64e")
138 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S64";
139
140 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
141 }
142 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
143
144 if (ABIName == "ilp32e")
145 return "e-m:e-p:32:32-i64:64-n32-S32";
146
147 return "e-m:e-p:32:32-i64:64-n32-S128";
148}
149
151 std::optional<Reloc::Model> RM) {
152 return RM.value_or(Reloc::Static);
153}
154
156 StringRef CPU, StringRef FS,
157 const TargetOptions &Options,
158 std::optional<Reloc::Model> RM,
159 std::optional<CodeModel::Model> CM,
160 CodeGenOptLevel OL, bool JIT)
163 getEffectiveCodeModel(CM, CodeModel::Small), OL),
164 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
165 initAsmInfo();
166
167 // RISC-V supports the MachineOutliner.
168 setMachineOutliner(true);
170
171 if (TT.isOSFuchsia() && !TT.isArch64Bit())
172 report_fatal_error("Fuchsia is only supported for 64-bit");
173}
174
175const RISCVSubtarget *
177 Attribute CPUAttr = F.getFnAttribute("target-cpu");
178 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
179 Attribute FSAttr = F.getFnAttribute("target-features");
180
181 std::string CPU =
182 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
183 std::string TuneCPU =
184 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
185 std::string FS =
186 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
187
188 unsigned RVVBitsMin = RVVVectorBitsMinOpt;
189 unsigned RVVBitsMax = RVVVectorBitsMaxOpt;
190
191 Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
192 if (VScaleRangeAttr.isValid()) {
193 if (!RVVVectorBitsMinOpt.getNumOccurrences())
194 RVVBitsMin = VScaleRangeAttr.getVScaleRangeMin() * RISCV::RVVBitsPerBlock;
195 std::optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
196 if (VScaleMax.has_value() && !RVVVectorBitsMaxOpt.getNumOccurrences())
197 RVVBitsMax = *VScaleMax * RISCV::RVVBitsPerBlock;
198 }
199
200 if (RVVBitsMin != -1U) {
201 // FIXME: Change to >= 32 when VLEN = 32 is supported.
202 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
203 isPowerOf2_32(RVVBitsMin))) &&
204 "V or Zve* extension requires vector length to be in the range of "
205 "64 to 65536 and a power 2!");
206 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
207 "Minimum V extension vector length should not be larger than its "
208 "maximum!");
209 }
210 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
211 isPowerOf2_32(RVVBitsMax))) &&
212 "V or Zve* extension requires vector length to be in the range of "
213 "64 to 65536 and a power 2!");
214
215 if (RVVBitsMin != -1U) {
216 if (RVVBitsMax != 0) {
217 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
218 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
219 }
220
221 RVVBitsMin = llvm::bit_floor(
222 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
223 }
224 RVVBitsMax =
225 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
226
228 raw_svector_ostream(Key) << "RVVMin" << RVVBitsMin << "RVVMax" << RVVBitsMax
229 << CPU << TuneCPU << FS;
230 auto &I = SubtargetMap[Key];
231 if (!I) {
232 // This needs to be done before we create a new subtarget since any
233 // creation will depend on the TM and the code generation flags on the
234 // function that reside in TargetOptions.
236 auto ABIName = Options.MCOptions.getABIName();
237 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
238 F.getParent()->getModuleFlag("target-abi"))) {
239 auto TargetABI = RISCVABI::getTargetABI(ABIName);
240 if (TargetABI != RISCVABI::ABI_Unknown &&
241 ModuleTargetABI->getString() != ABIName) {
242 report_fatal_error("-target-abi option != target-abi module flag");
243 }
244 ABIName = ModuleTargetABI->getString();
245 }
246 I = std::make_unique<RISCVSubtarget>(
247 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
248 }
249 return I.get();
250}
251
253 BumpPtrAllocator &Allocator, const Function &F,
254 const TargetSubtargetInfo *STI) const {
255 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(Allocator,
256 F, STI);
257}
258
261 return TargetTransformInfo(RISCVTTIImpl(this, F));
262}
263
264// A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
265// for all memory accesses, so it is reasonable to assume that an
266// implementation has no-op address space casts. If an implementation makes a
267// change to this, they can override it here.
269 unsigned DstAS) const {
270 return true;
271}
272
273namespace {
274
275class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
276public:
277 RVVRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
278 : RegisterRegAllocBase(N, D, C) {}
279};
280
281static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
282 const TargetRegisterClass &RC) {
284}
285
286static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
287
288static llvm::once_flag InitializeDefaultRVVRegisterAllocatorFlag;
289
290/// -riscv-rvv-regalloc=<fast|basic|greedy> command line option.
291/// This option could designate the rvv register allocator only.
292/// For example: -riscv-rvv-regalloc=basic
293static cl::opt<RVVRegisterRegAlloc::FunctionPassCtor, false,
295 RVVRegAlloc("riscv-rvv-regalloc", cl::Hidden,
297 cl::desc("Register allocator to use for RVV register."));
298
299static void initializeDefaultRVVRegisterAllocatorOnce() {
300 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
301
302 if (!Ctor) {
303 Ctor = RVVRegAlloc;
304 RVVRegisterRegAlloc::setDefault(RVVRegAlloc);
305 }
306}
307
308static FunctionPass *createBasicRVVRegisterAllocator() {
309 return createBasicRegisterAllocator(onlyAllocateRVVReg);
310}
311
312static FunctionPass *createGreedyRVVRegisterAllocator() {
313 return createGreedyRegisterAllocator(onlyAllocateRVVReg);
314}
315
316static FunctionPass *createFastRVVRegisterAllocator() {
317 return createFastRegisterAllocator(onlyAllocateRVVReg, false);
318}
319
320static RVVRegisterRegAlloc basicRegAllocRVVReg("basic",
321 "basic register allocator",
322 createBasicRVVRegisterAllocator);
323static RVVRegisterRegAlloc
324 greedyRegAllocRVVReg("greedy", "greedy register allocator",
325 createGreedyRVVRegisterAllocator);
326
327static RVVRegisterRegAlloc fastRegAllocRVVReg("fast", "fast register allocator",
328 createFastRVVRegisterAllocator);
329
330class RISCVPassConfig : public TargetPassConfig {
331public:
332 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
333 : TargetPassConfig(TM, PM) {
334 if (TM.getOptLevel() != CodeGenOptLevel::None)
335 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
336 setEnableSinkAndFold(EnableSinkFold);
337 }
338
339 RISCVTargetMachine &getRISCVTargetMachine() const {
340 return getTM<RISCVTargetMachine>();
341 }
342
344 createMachineScheduler(MachineSchedContext *C) const override {
345 ScheduleDAGMILive *DAG = nullptr;
349 DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
350 }
351 return DAG;
352 }
353
354 void addIRPasses() override;
355 bool addPreISel() override;
356 void addCodeGenPrepare() override;
357 bool addInstSelector() override;
358 bool addIRTranslator() override;
359 void addPreLegalizeMachineIR() override;
360 bool addLegalizeMachineIR() override;
361 void addPreRegBankSelect() override;
362 bool addRegBankSelect() override;
363 bool addGlobalInstructionSelect() override;
364 void addPreEmitPass() override;
365 void addPreEmitPass2() override;
366 void addPreSched2() override;
367 void addMachineSSAOptimization() override;
368 FunctionPass *createRVVRegAllocPass(bool Optimized);
369 bool addRegAssignAndRewriteFast() override;
370 bool addRegAssignAndRewriteOptimized() override;
371 void addPreRegAlloc() override;
372 void addPostRegAlloc() override;
373 void addFastRegAlloc() override;
374};
375} // namespace
376
378 return new RISCVPassConfig(*this, PM);
379}
380
381FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
382 // Initialize the global default.
383 llvm::call_once(InitializeDefaultRVVRegisterAllocatorFlag,
384 initializeDefaultRVVRegisterAllocatorOnce);
385
386 RegisterRegAlloc::FunctionPassCtor Ctor = RVVRegisterRegAlloc::getDefault();
387 if (Ctor != useDefaultRegisterAllocator)
388 return Ctor();
389
390 if (Optimized)
391 return createGreedyRVVRegisterAllocator();
392
393 return createFastRVVRegisterAllocator();
394}
395
396bool RISCVPassConfig::addRegAssignAndRewriteFast() {
397 addPass(createRVVRegAllocPass(false));
400 if (TM->getOptLevel() != CodeGenOptLevel::None &&
404}
405
406bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
407 addPass(createRVVRegAllocPass(true));
408 addPass(createVirtRegRewriter(false));
411 if (TM->getOptLevel() != CodeGenOptLevel::None &&
415}
416
417void RISCVPassConfig::addIRPasses() {
419
420 if (getOptLevel() != CodeGenOptLevel::None) {
423
427 }
428
430}
431
432bool RISCVPassConfig::addPreISel() {
433 if (TM->getOptLevel() != CodeGenOptLevel::None) {
434 // Add a barrier before instruction selection so that we will not get
435 // deleted block address after enabling default outlining. See D99707 for
436 // more details.
437 addPass(createBarrierNoopPass());
438 }
439
441 addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
442 /* OnlyOptimizeForSize */ false,
443 /* MergeExternalByDefault */ true));
444 }
445
446 return false;
447}
448
449void RISCVPassConfig::addCodeGenPrepare() {
450 if (getOptLevel() != CodeGenOptLevel::None)
453}
454
455bool RISCVPassConfig::addInstSelector() {
456 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
457
458 return false;
459}
460
461bool RISCVPassConfig::addIRTranslator() {
462 addPass(new IRTranslator(getOptLevel()));
463 return false;
464}
465
466void RISCVPassConfig::addPreLegalizeMachineIR() {
467 if (getOptLevel() == CodeGenOptLevel::None) {
469 } else {
471 }
472}
473
474bool RISCVPassConfig::addLegalizeMachineIR() {
475 addPass(new Legalizer());
476 return false;
477}
478
479void RISCVPassConfig::addPreRegBankSelect() {
480 if (getOptLevel() != CodeGenOptLevel::None)
482}
483
484bool RISCVPassConfig::addRegBankSelect() {
485 addPass(new RegBankSelect());
486 return false;
487}
488
489bool RISCVPassConfig::addGlobalInstructionSelect() {
490 addPass(new InstructionSelect(getOptLevel()));
491 return false;
492}
493
494void RISCVPassConfig::addPreSched2() {
496
497 // Emit KCFI checks for indirect calls.
498 addPass(createKCFIPass());
499}
500
501void RISCVPassConfig::addPreEmitPass() {
502 // TODO: It would potentially be better to schedule copy propagation after
503 // expanding pseudos (in addPreEmitPass2). However, performing copy
504 // propagation after the machine outliner (which runs after addPreEmitPass)
505 // currently leads to incorrect code-gen, where copies to registers within
506 // outlined functions are removed erroneously.
507 if (TM->getOptLevel() >= CodeGenOptLevel::Default &&
510 addPass(&BranchRelaxationPassID);
512}
513
514void RISCVPassConfig::addPreEmitPass2() {
515 if (TM->getOptLevel() != CodeGenOptLevel::None) {
516 addPass(createRISCVMoveMergePass());
517 // Schedule PushPop Optimization before expansion of Pseudo instruction,
518 // ensuring return instruction is detected correctly.
520 }
522
523 // Schedule the expansion of AMOs at the last possible moment, avoiding the
524 // possibility for other passes to break the requirements for forward
525 // progress in the LR/SC block.
527
528 // KCFI indirect call checks are lowered to a bundle.
529 addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
530 return MF.getFunction().getParent()->getModuleFlag("kcfi");
531 }));
532}
533
534void RISCVPassConfig::addMachineSSAOptimization() {
536
538
540 addPass(&MachineCombinerID);
541
542 if (TM->getTargetTriple().isRISCV64()) {
543 addPass(createRISCVOptWInstrsPass());
544 }
545}
546
547void RISCVPassConfig::addPreRegAlloc() {
549 if (TM->getOptLevel() != CodeGenOptLevel::None)
551
554
555 // Run RISCVInsertVSETVLI after PHI elimination. On O1 and above do it after
556 // register coalescing so needVSETVLIPHI doesn't need to look through COPYs.
558 if (TM->getOptLevel() == CodeGenOptLevel::None)
560 else
562 }
563}
564
565void RISCVPassConfig::addFastRegAlloc() {
566 addPass(&InitUndefID);
568}
569
570
571void RISCVPassConfig::addPostRegAlloc() {
572 if (TM->getOptLevel() != CodeGenOptLevel::None &&
575}
576
579 OptimizationLevel Level) {
581 });
582}
583
587}
588
591 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
592 return new yaml::RISCVMachineFunctionInfo(*MFI);
593}
594
597 SMDiagnostic &Error, SMRange &SourceRange) const {
598 const auto &YamlMFI =
599 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
600 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
601 return false;
602}
static cl::opt< bool > EnableSinkFold("aarch64-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static const Function * getParent(const Value *V)
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableSinkFold("riscv-enable-sink-fold", cl::desc("Enable sinking and folding of instruction copies"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("riscv-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
static cl::opt< bool > EnableVSETVLIAfterRVVRegAlloc("riscv-vsetvl-after-rvv-regalloc", cl::Hidden, cl::desc("Insert vsetvls after vector register allocation"), cl::init(true))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMISchedLoadClustering("riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), cl::init(false))
This file defines a TargetTransformInfo::Concept conforming object specific to the RISC-V target mach...
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
static FunctionPass * useDefaultRegisterAllocator()
-regalloc=... command line option.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
Definition: Attributes.cpp:465
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:459
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:391
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:203
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
A single uniqued string.
Definition: Metadata.h:720
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:106
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:420
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
RegisterPassParser class - Handle the addition of new machine passes.
RegisterRegAllocBase class - Track the registration of register allocators.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:575
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:576
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:223
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:98
std::string TargetCPU
Definition: TargetMachine.h:97
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
FunctionPass * createRISCVPostLegalizerCombiner()
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
char & InitUndefID
Definition: InitUndef.cpp:98
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createRISCVPostRAExpandPseudoPass()
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeRISCVPostRAExpandPseudoPass(PassRegistry &)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:291
FunctionPass * createRISCVPreLegalizerCombiner()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVO0PreLegalizerCombiner()
void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:62
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
void initializeRISCVInsertWriteVXRMPass(PassRegistry &)
FunctionPass * createLoopDataPrefetchPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createRISCVOptWInstrsPass()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)
If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...
void initializeRISCVOptWInstrsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
char & RISCVInsertVSETVLIID
FunctionPass * createRISCVVectorPeepholePass()
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
Definition: Threading.h:87
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeKCFIPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
FunctionPass * createVirtRegRewriter(bool ClearVirtRegs=true)
Definition: VirtRegMap.cpp:645
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
Definition: bit.h:327
FunctionPass * createRISCVInsertWriteVXRMPass()
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVVectorPeepholePass(PassRegistry &)
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
void initializeRISCVPostLegalizerCombinerPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
#define N
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
static bool isRVVRegClass(const TargetRegisterClass *RC)
RegisterTargetMachine - Helper template for registering a target machine implementation,...
The llvm::once_flag structure.
Definition: Threading.h:68
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.