LLVM  16.0.0git
RISCVTargetMachine.cpp
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1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
15 #include "RISCV.h"
17 #include "RISCVMacroFusion.h"
18 #include "RISCVTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/CodeGen/Passes.h"
33 #include "llvm/InitializePasses.h"
34 #include "llvm/MC/TargetRegistry.h"
37 #include "llvm/Transforms/IPO.h"
38 using namespace llvm;
39 
41  "riscv-enable-copyelim",
42  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
43  cl::Hidden);
44 
45 // FIXME: Unify control over GlobalMerge.
47  EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden,
48  cl::desc("Enable the global merge pass"));
49 
50 static cl::opt<bool>
51  EnableMachineCombiner("riscv-enable-machine-combiner",
52  cl::desc("Enable the machine combiner pass"),
53  cl::init(true), cl::Hidden);
54 
58  auto *PR = PassRegistry::getPassRegistry();
68 }
69 
70 static StringRef computeDataLayout(const Triple &TT) {
71  if (TT.isArch64Bit())
72  return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
73  assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
74  return "e-m:e-p:32:32-i64:64-n32-S128";
75 }
76 
79  return RM.value_or(Reloc::Static);
80 }
81 
83  StringRef CPU, StringRef FS,
84  const TargetOptions &Options,
87  CodeGenOpt::Level OL, bool JIT)
91  TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
92  initAsmInfo();
93 
94  // RISC-V supports the MachineOutliner.
95  setMachineOutliner(true);
97 }
98 
99 const RISCVSubtarget *
101  Attribute CPUAttr = F.getFnAttribute("target-cpu");
102  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
103  Attribute FSAttr = F.getFnAttribute("target-features");
104 
105  std::string CPU =
106  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
107  std::string TuneCPU =
108  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
109  std::string FS =
110  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
111  std::string Key = CPU + TuneCPU + FS;
112  auto &I = SubtargetMap[Key];
113  if (!I) {
114  // This needs to be done before we create a new subtarget since any
115  // creation will depend on the TM and the code generation flags on the
116  // function that reside in TargetOptions.
118  auto ABIName = Options.MCOptions.getABIName();
119  if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
120  F.getParent()->getModuleFlag("target-abi"))) {
121  auto TargetABI = RISCVABI::getTargetABI(ABIName);
122  if (TargetABI != RISCVABI::ABI_Unknown &&
123  ModuleTargetABI->getString() != ABIName) {
124  report_fatal_error("-target-abi option != target-abi module flag");
125  }
126  ABIName = ModuleTargetABI->getString();
127  }
128  I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
129  }
130  return I.get();
131 }
132 
135  return TargetTransformInfo(RISCVTTIImpl(this, F));
136 }
137 
138 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
139 // for all memory accesses, so it is reasonable to assume that an
140 // implementation has no-op address space casts. If an implementation makes a
141 // change to this, they can override it here.
143  unsigned DstAS) const {
144  return true;
145 }
146 
147 namespace {
148 class RISCVPassConfig : public TargetPassConfig {
149 public:
150  RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
151  : TargetPassConfig(TM, PM) {}
152 
153  RISCVTargetMachine &getRISCVTargetMachine() const {
154  return getTM<RISCVTargetMachine>();
155  }
156 
158  createMachineScheduler(MachineSchedContext *C) const override {
159  const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
160  if (ST.hasMacroFusion()) {
163  return DAG;
164  }
165  return nullptr;
166  }
167 
169  createPostMachineScheduler(MachineSchedContext *C) const override {
170  const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
171  if (ST.hasMacroFusion()) {
174  return DAG;
175  }
176  return nullptr;
177  }
178 
179  void addIRPasses() override;
180  bool addPreISel() override;
181  bool addInstSelector() override;
182  bool addIRTranslator() override;
183  bool addLegalizeMachineIR() override;
184  bool addRegBankSelect() override;
185  bool addGlobalInstructionSelect() override;
186  void addPreEmitPass() override;
187  void addPreEmitPass2() override;
188  void addPreSched2() override;
189  void addMachineSSAOptimization() override;
190  void addPreRegAlloc() override;
191  void addPostRegAlloc() override;
192 };
193 } // namespace
194 
196  return new RISCVPassConfig(*this, PM);
197 }
198 
199 void RISCVPassConfig::addIRPasses() {
200  addPass(createAtomicExpandPass());
201 
202  if (getOptLevel() != CodeGenOpt::None)
204 
205  if (getOptLevel() != CodeGenOpt::None)
207 
209 }
210 
211 bool RISCVPassConfig::addPreISel() {
212  if (TM->getOptLevel() != CodeGenOpt::None) {
213  // Add a barrier before instruction selection so that we will not get
214  // deleted block address after enabling default outlining. See D99707 for
215  // more details.
216  addPass(createBarrierNoopPass());
217  }
218 
220  addPass(createGlobalMergePass(TM, /* MaxOffset */ 2047,
221  /* OnlyOptimizeForSize */ false,
222  /* MergeExternalByDefault */ true));
223  }
224 
225  return false;
226 }
227 
228 bool RISCVPassConfig::addInstSelector() {
229  addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel()));
230 
231  return false;
232 }
233 
234 bool RISCVPassConfig::addIRTranslator() {
235  addPass(new IRTranslator(getOptLevel()));
236  return false;
237 }
238 
239 bool RISCVPassConfig::addLegalizeMachineIR() {
240  addPass(new Legalizer());
241  return false;
242 }
243 
244 bool RISCVPassConfig::addRegBankSelect() {
245  addPass(new RegBankSelect());
246  return false;
247 }
248 
249 bool RISCVPassConfig::addGlobalInstructionSelect() {
250  addPass(new InstructionSelect(getOptLevel()));
251  return false;
252 }
253 
254 void RISCVPassConfig::addPreSched2() {}
255 
256 void RISCVPassConfig::addPreEmitPass() {
257  addPass(&BranchRelaxationPassID);
259 }
260 
261 void RISCVPassConfig::addPreEmitPass2() {
262  addPass(createRISCVExpandPseudoPass());
263  // Schedule the expansion of AMOs at the last possible moment, avoiding the
264  // possibility for other passes to break the requirements for forward
265  // progress in the LR/SC block.
267 }
268 
269 void RISCVPassConfig::addMachineSSAOptimization() {
272  addPass(&MachineCombinerID);
273 
274  if (TM->getTargetTriple().getArch() == Triple::riscv64)
275  addPass(createRISCVSExtWRemovalPass());
276 }
277 
278 void RISCVPassConfig::addPreRegAlloc() {
280  if (TM->getOptLevel() != CodeGenOpt::None)
282  addPass(createRISCVInsertVSETVLIPass());
283 }
284 
285 void RISCVPassConfig::addPostRegAlloc() {
286  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
288 }
289 
292  return new yaml::RISCVMachineFunctionInfo();
293 }
294 
297  const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
298  return new yaml::RISCVMachineFunctionInfo(*MFI);
299 }
300 
303  SMDiagnostic &Error, SMRange &SourceRange) const {
304  const auto &YamlMFI =
305  static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
306  PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
307  return false;
308 }
llvm::Triple::riscv64
@ riscv64
Definition: Triple.h:76
llvm::initializeRISCVCodeGenPreparePass
void initializeRISCVCodeGenPreparePass(PassRegistry &)
RISCVMacroFusion.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
llvm::RISCVTargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: RISCVTargetMachine.cpp:301
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:493
llvm::RISCVTargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: RISCVTargetMachine.cpp:296
llvm::RISCVTTIImpl
Definition: RISCVTargetTransformInfo.h:28
llvm::getTheRISCV64Target
Target & getTheRISCV64Target()
Definition: RISCVTargetInfo.cpp:18
llvm::RISCVABI::getTargetABI
ABI getTargetABI(StringRef ABIName)
Definition: RISCVBaseInfo.cpp:72
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::RISCVTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: RISCVTargetMachine.cpp:195
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:66
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:676
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCTargetOptions::getABIName
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
Definition: MCTargetOptions.cpp:23
llvm::createRISCVInsertVSETVLIPass
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
Definition: RISCVInsertVSETVLI.cpp:1358
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::createRISCVMergeBaseOffsetOptPass
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Definition: RISCVMergeBaseOffset.cpp:440
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::createRISCVCodeGenPreparePass
FunctionPass * createRISCVCodeGenPreparePass()
Definition: RISCVCodeGenPrepare.cpp:176
llvm::createRISCVExpandAtomicPseudoPass
FunctionPass * createRISCVExpandAtomicPseudoPass()
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
llvm::X86AS::FS
@ FS
Definition: X86.h:200
InstructionSelect.h
llvm::Optional< Reloc::Model >
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::RISCVTargetMachine::getSubtargetImpl
const RISCVSubtarget * getSubtargetImpl() const =delete
llvm::initializeRISCVMergeBaseOffsetOptPass
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
STLExtras.h
llvm::initializeRISCVExpandPseudoPass
void initializeRISCVExpandPseudoPass(PassRegistry &)
llvm::RISCVTargetMachine::RISCVTargetMachine
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: RISCVTargetMachine.cpp:82
LegacyPassManager.h
llvm::RISCVELFTargetObjectFile
This implementation is used for RISCV ELF targets.
Definition: RISCVTargetObjectFile.h:17
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
computeDataLayout
static StringRef computeDataLayout(const Triple &TT)
Definition: RISCVTargetMachine.cpp:70
llvm::RISCVTargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: RISCVTargetMachine.cpp:291
FormattedStream.h
MIRYamlMapping.h
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
RISCVTargetObjectFile.h
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
llvm::TargetOptions::MCOptions
MCTargetOptions MCOptions
Machine level options.
Definition: TargetOptions.h:442
llvm::initializeRISCVSExtWRemovalPass
void initializeRISCVSExtWRemovalPass(PassRegistry &)
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3645
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1356
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:325
LLVMInitializeRISCVTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
Definition: RISCVTargetMachine.cpp:55
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::createRISCVISelDag
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: RISCVISelDAGToDAG.cpp:2892
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3488
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::initializeRISCVGatherScatterLoweringPass
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
IPO.h
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:492
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:127
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::initializeRISCVMakeCompressibleOptPass
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
TargetPassConfig.h
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::createRISCVMakeCompressibleOptPass
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
Definition: RISCVMakeCompressible.cpp:388
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:273
EnableMachineCombiner
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::createRISCVGatherScatterLoweringPass
FunctionPass * createRISCVGatherScatterLoweringPass()
llvm::createRISCVMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
Definition: RISCVMacroFusion.cpp:71
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
IRTranslator.h
llvm::initializeRISCVPreRAExpandPseudoPass
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:506
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::createRISCVSExtWRemovalPass
FunctionPass * createRISCVSExtWRemovalPass()
std
Definition: BitVector.h:851
llvm::createRISCVRedundantCopyEliminationPass
FunctionPass * createRISCVRedundantCopyEliminationPass()
Definition: RISCVRedundantCopyElimination.cpp:179
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1308
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
RegBankSelect.h
llvm::yaml::RISCVMachineFunctionInfo
Definition: RISCVMachineFunctionInfo.h:26
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
RISCVBaseInfo.h
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:692
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:631
Legalizer.h
llvm::initializeRISCVInsertVSETVLIPass
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
llvm::RISCVTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: RISCVTargetMachine.cpp:134
llvm::RISCVABI::ABI_Unknown
@ ABI_Unknown
Definition: RISCVBaseInfo.h:380
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
RISCVMachineFunctionInfo.h
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:131
TargetTransformInfo.h
llvm::RISCVTargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: RISCVTargetMachine.cpp:142
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
RISCVTargetInfo.h
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::cl::desc
Definition: CommandLine.h:413
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:392
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::MDString
A single uniqued string.
Definition: Metadata.h:612
RISCVTargetTransformInfo.h
TargetRegistry.h
InitializePasses.h
llvm::getTheRISCV32Target
Target & getTheRISCV32Target()
Definition: RISCVTargetInfo.cpp:13
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
MIParser.h
TargetLoweringObjectFileImpl.h
RISCVTargetMachine.h