41 "riscv-enable-copyelim",
48 cl::desc(
"Enable the global merge pass"));
52 cl::desc(
"Enable the machine combiner pass"),
56 "riscv-v-vector-bits-max",
57 cl::desc(
"Assume V extension vector registers are at most this big, "
58 "with zero meaning no maximum size is assumed."),
62 "riscv-v-vector-bits-min",
63 cl::desc(
"Assume V extension vector registers are at least this big, "
64 "with zero meaning no minimum size is assumed. A value of -1 "
65 "means use Zvl*b extension. This is primarily used to enable "
66 "autovectorization with fixed width vectors."),
70 "riscv-enable-copy-propagation",
71 cl::desc(
"Enable the copy propagation with RISC-V copy instr"),
76 cl::desc(
"Enable the pass that removes dead"
77 " definitons and replaces stores to"
78 " them with stores to x0"),
106 if (TT.isArch64Bit())
107 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
108 assert(TT.isArch32Bit() &&
"only RV32 and RV64 are currently supported");
109 return "e-m:e-p:32:32-i64:64-n32-S128";
113 std::optional<Reloc::Model> RM) {
120 std::optional<Reloc::Model> RM,
121 std::optional<CodeModel::Model> CM,
133 if (TT.isOSFuchsia() && !TT.isArch64Bit())
139 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
140 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
141 Attribute FSAttr =
F.getFnAttribute(
"target-features");
145 std::string TuneCPU =
153 Attribute VScaleRangeAttr =
F.getFnAttribute(Attribute::VScaleRange);
154 if (VScaleRangeAttr.
isValid()) {
162 if (RVVBitsMin != -1U) {
164 assert((RVVBitsMin == 0 || (RVVBitsMin >= 64 && RVVBitsMin <= 65536 &&
166 "V or Zve* extension requires vector length to be in the range of "
167 "64 to 65536 and a power 2!");
168 assert((RVVBitsMax >= RVVBitsMin || RVVBitsMax == 0) &&
169 "Minimum V extension vector length should not be larger than its "
172 assert((RVVBitsMax == 0 || (RVVBitsMax >= 64 && RVVBitsMax <= 65536 &&
174 "V or Zve* extension requires vector length to be in the range of "
175 "64 to 65536 and a power 2!");
177 if (RVVBitsMin != -1U) {
178 if (RVVBitsMax != 0) {
179 RVVBitsMin = std::min(RVVBitsMin, RVVBitsMax);
180 RVVBitsMax = std::max(RVVBitsMin, RVVBitsMax);
184 (RVVBitsMin < 64 || RVVBitsMin > 65536) ? 0 : RVVBitsMin);
187 llvm::bit_floor((RVVBitsMax < 64 || RVVBitsMax > 65536) ? 0 : RVVBitsMax);
191 Key += std::to_string(RVVBitsMin);
193 Key += std::to_string(RVVBitsMax);
197 auto &
I = SubtargetMap[Key];
204 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
205 F.getParent()->getModuleFlag(
"target-abi"))) {
208 ModuleTargetABI->getString() != ABIName) {
211 ABIName = ModuleTargetABI->getString();
213 I = std::make_unique<RISCVSubtarget>(
214 TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *
this);
222 return RISCVMachineFunctionInfo::create<RISCVMachineFunctionInfo>(
Allocator,
236 unsigned DstAS)
const {
247 return getTM<RISCVTargetMachine>();
253 if (
ST.hasMacroFusion()) {
264 if (
ST.hasMacroFusion()) {
272 void addIRPasses()
override;
273 bool addPreISel()
override;
274 bool addInstSelector()
override;
275 bool addIRTranslator()
override;
276 void addPreLegalizeMachineIR()
override;
277 bool addLegalizeMachineIR()
override;
278 bool addRegBankSelect()
override;
279 bool addGlobalInstructionSelect()
override;
280 void addPreEmitPass()
override;
281 void addPreEmitPass2()
override;
282 void addPreSched2()
override;
283 void addMachineSSAOptimization()
override;
284 void addPreRegAlloc()
override;
285 void addPostRegAlloc()
override;
286 void addOptimizedRegAlloc()
override;
287 void addFastRegAlloc()
override;
292 return new RISCVPassConfig(*
this, PM);
295void RISCVPassConfig::addIRPasses() {
307bool RISCVPassConfig::addPreISel() {
324bool RISCVPassConfig::addInstSelector() {
330bool RISCVPassConfig::addIRTranslator() {
335void RISCVPassConfig::addPreLegalizeMachineIR() {
343bool RISCVPassConfig::addLegalizeMachineIR() {
348bool RISCVPassConfig::addRegBankSelect() {
353bool RISCVPassConfig::addGlobalInstructionSelect() {
358void RISCVPassConfig::addPreSched2() {
363void RISCVPassConfig::addPreEmitPass() {
377void RISCVPassConfig::addPreEmitPass2() {
397void RISCVPassConfig::addMachineSSAOptimization() {
407void RISCVPassConfig::addPreRegAlloc() {
418void RISCVPassConfig::addOptimizedRegAlloc() {
424void RISCVPassConfig::addFastRegAlloc() {
430void RISCVPassConfig::addPostRegAlloc() {
450 const auto &YamlMFI =
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static const Function * getParent(const Value *V)
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static std::string computeDataLayout()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
static cl::opt< bool > EnableRedundantCopyElimination("riscv-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
static cl::opt< unsigned > RVVVectorBitsMaxOpt("riscv-v-vector-bits-max", cl::desc("Assume V extension vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("riscv-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget()
static cl::opt< bool > EnableRISCVCopyPropagation("riscv-enable-copy-propagation", cl::desc("Enable the copy propagation with RISC-V copy instr"), cl::init(true), cl::Hidden)
static cl::opt< int > RVVVectorBitsMinOpt("riscv-v-vector-bits-min", cl::desc("Assume V extension vector registers are at least this big, " "with zero meaning no minimum size is assumed. A value of -1 " "means use Zvl*b extension. This is primarily used to enable " "autovectorization with fixed width vectors."), cl::init(-1), cl::Hidden)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
static cl::opt< bool > EnableRISCVDeadRegisterElimination("riscv-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to x0"), cl::init(true))
static cl::opt< bool > EnableMachineCombiner("riscv-enable-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
std::optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or std::nullopt when unknown.
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
Lightweight error class with error context and mandatory checking.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This implementation is used for RISC-V ELF targets.
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
const RISCVSubtarget * getSubtargetImpl() const =delete
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addOptimizedRegAlloc()
addOptimizedRegAlloc - Add passes related to register allocation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addFastRegAlloc()
addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast registe...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
ABI getTargetABI(StringRef ABIName)
static constexpr unsigned RVVBitsPerBlock
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
void initializeRISCVPushPopOptPass(PassRegistry &)
void initializeRISCVExpandPseudoPass(PassRegistry &)
FunctionPass * createRISCVMoveMergePass()
createRISCVMoveMergePass - returns an instance of the move merge pass.
void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &)
void initializeRISCVPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createRISCVExpandAtomicPseudoPass()
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createRISCVInsertReadWriteCSRPass()
Target & getTheRISCV32Target()
void initializeRISCVInsertVSETVLIPass(PassRegistry &)
void initializeRISCVInitUndefPass(PassRegistry &)
std::unique_ptr< ScheduleDAGMutation > createRISCVMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createRISCVMacroFusionDAGMutation()); to RISCVPassConfig::...
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createRISCVGatherScatterLoweringPass()
FunctionPass * createRISCVMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
void initializeRISCVDAGToDAGISelPass(PassRegistry &)
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
FunctionPass * createRISCVPreLegalizerCombiner()
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createRISCVO0PreLegalizerCombiner()
FunctionPass * createRISCVPushPopOptimizationPass()
createRISCVPushPopOptimizationPass - returns an instance of the Push/Pop optimization pass.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
FunctionPass * createRISCVRedundantCopyEliminationPass()
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &)
char & DetectDeadLanesID
This pass adds dead/undef flags after analyzing subregister lanes.
FunctionPass * createRISCVInsertVSETVLIPass()
Returns an instance of the Insert VSETVLI pass.
CodeGenOptLevel
Code generation optimization level.
FunctionPass * createRISCVOptWInstrsPass()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVCodeGenPreparePass()
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
void initializeRISCVOptWInstrsPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeRISCVCodeGenPreparePass(PassRegistry &)
Target & getTheRISCV64Target()
void initializeRISCVO0PreLegalizerCombinerPass(PassRegistry &)
void initializeKCFIPass(PassRegistry &)
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &)
FunctionPass * createRISCVISelDag(RISCVTargetMachine &TM, CodeGenOptLevel OptLevel)
void initializeRISCVGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createRISCVExpandPseudoPass()
FunctionPass * createRISCVPreRAExpandPseudoPass()
FunctionPass * createRISCVInitUndefPass()
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
MachineFunctionPass * createMachineCopyPropagationPass(bool UseCopyInstr)
void initializeRISCVPreRAExpandPseudoPass(PassRegistry &)
void initializeRISCVMoveMergePass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.