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A15SDOptimizer.cpp
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1 //=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // The Cortex-A15 processor employs a tracking scheme in its register renaming
10 // in order to process each instruction's micro-ops speculatively and
11 // out-of-order with appropriate forwarding. The ARM architecture allows VFP
12 // instructions to read and write 32-bit S-registers. Each S-register
13 // corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
14 //
15 // There are several instruction patterns which can be used to provide this
16 // capability which can provide higher performance than other, potentially more
17 // direct patterns, specifically around when one micro-op reads a D-register
18 // operand that has recently been written as one or more S-register results.
19 //
20 // This file defines a pre-regalloc pass which looks for SPR producers which
21 // are going to be used by a DPR (or QPR) consumers and creates the more
22 // optimized access pattern.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #include "ARM.h"
27 #include "ARMBaseInstrInfo.h"
28 #include "ARMBaseRegisterInfo.h"
29 #include "ARMSubtarget.h"
30 #include "llvm/ADT/Statistic.h"
38 #include "llvm/Support/Debug.h"
40 #include <map>
41 #include <set>
42 
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "a15-sd-optimizer"
46 
47 namespace {
48  struct A15SDOptimizer : public MachineFunctionPass {
49  static char ID;
50  A15SDOptimizer() : MachineFunctionPass(ID) {}
51 
52  bool runOnMachineFunction(MachineFunction &Fn) override;
53 
54  StringRef getPassName() const override { return "ARM A15 S->D optimizer"; }
55 
56  private:
57  const ARMBaseInstrInfo *TII;
58  const TargetRegisterInfo *TRI;
60 
61  bool runOnInstruction(MachineInstr *MI);
62 
63  //
64  // Instruction builder helpers
65  //
66  unsigned createDupLane(MachineBasicBlock &MBB,
67  MachineBasicBlock::iterator InsertBefore,
68  const DebugLoc &DL, unsigned Reg, unsigned Lane,
69  bool QPR = false);
70 
71  unsigned createExtractSubreg(MachineBasicBlock &MBB,
72  MachineBasicBlock::iterator InsertBefore,
73  const DebugLoc &DL, unsigned DReg,
74  unsigned Lane, const TargetRegisterClass *TRC);
75 
76  unsigned createVExt(MachineBasicBlock &MBB,
77  MachineBasicBlock::iterator InsertBefore,
78  const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
79 
80  unsigned createRegSequence(MachineBasicBlock &MBB,
81  MachineBasicBlock::iterator InsertBefore,
82  const DebugLoc &DL, unsigned Reg1,
83  unsigned Reg2);
84 
85  unsigned createInsertSubreg(MachineBasicBlock &MBB,
86  MachineBasicBlock::iterator InsertBefore,
87  const DebugLoc &DL, unsigned DReg,
88  unsigned Lane, unsigned ToInsert);
89 
90  unsigned createImplicitDef(MachineBasicBlock &MBB,
91  MachineBasicBlock::iterator InsertBefore,
92  const DebugLoc &DL);
93 
94  //
95  // Various property checkers
96  //
97  bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
98  bool hasPartialWrite(MachineInstr *MI);
100  unsigned getDPRLaneFromSPR(unsigned SReg);
101 
102  //
103  // Methods used for getting the definitions of partial registers
104  //
105 
106  MachineInstr *elideCopies(MachineInstr *MI);
107  void elideCopiesAndPHIs(MachineInstr *MI,
109 
110  //
111  // Pattern optimization methods
112  //
113  unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
114  unsigned optimizeSDPattern(MachineInstr *MI);
115  unsigned getPrefSPRLane(unsigned SReg);
116 
117  //
118  // Sanitizing method - used to make sure if don't leave dead code around.
119  //
120  void eraseInstrWithNoUses(MachineInstr *MI);
121 
122  //
123  // A map used to track the changes done by this pass.
124  //
125  std::map<MachineInstr*, unsigned> Replacements;
126  std::set<MachineInstr *> DeadInstr;
127  };
128  char A15SDOptimizer::ID = 0;
129 } // end anonymous namespace
130 
131 // Returns true if this is a use of a SPR register.
132 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
133  const TargetRegisterClass *TRC) {
134  if (!MO.isReg())
135  return false;
136  Register Reg = MO.getReg();
137 
139  return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
140  else
141  return TRC->contains(Reg);
142 }
143 
144 unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145  unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
146  &ARM::DPRRegClass);
147  if (DReg != ARM::NoRegister) return ARM::ssub_1;
148  return ARM::ssub_0;
149 }
150 
151 // Get the subreg type that is most likely to be coalesced
152 // for an SPR register that will be used in VDUP32d pseudo.
153 unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
154  if (!Register::isVirtualRegister(SReg))
155  return getDPRLaneFromSPR(SReg);
156 
157  MachineInstr *MI = MRI->getVRegDef(SReg);
158  if (!MI) return ARM::ssub_0;
159  MachineOperand *MO = MI->findRegisterDefOperand(SReg);
160  if (!MO) return ARM::ssub_0;
161  assert(MO->isReg() && "Non-register operand found!");
162 
163  if (MI->isCopy() && usesRegClass(MI->getOperand(1),
164  &ARM::SPRRegClass)) {
165  SReg = MI->getOperand(1).getReg();
166  }
167 
168  if (Register::isVirtualRegister(SReg)) {
169  if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
170  return ARM::ssub_0;
171  }
172  return getDPRLaneFromSPR(SReg);
173 }
174 
175 // MI is known to be dead. Figure out what instructions
176 // are also made dead by this and mark them for removal.
177 void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
179  DeadInstr.insert(MI);
180 
181  LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
182  Front.push_back(MI);
183 
184  while (Front.size() != 0) {
185  MI = Front.pop_back_val();
186 
187  // MI is already known to be dead. We need to see
188  // if other instructions can also be removed.
189  for (MachineOperand &MO : MI->operands()) {
190  if ((!MO.isReg()) || (!MO.isUse()))
191  continue;
192  Register Reg = MO.getReg();
194  continue;
195  MachineOperand *Op = MI->findRegisterDefOperand(Reg);
196 
197  if (!Op)
198  continue;
199 
200  MachineInstr *Def = Op->getParent();
201 
202  // We don't need to do anything if we have already marked
203  // this instruction as being dead.
204  if (DeadInstr.find(Def) != DeadInstr.end())
205  continue;
206 
207  // Check if all the uses of this instruction are marked as
208  // dead. If so, we can also mark this instruction as being
209  // dead.
210  bool IsDead = true;
211  for (MachineOperand &MODef : Def->operands()) {
212  if ((!MODef.isReg()) || (!MODef.isDef()))
213  continue;
214  Register DefReg = MODef.getReg();
215  if (!Register::isVirtualRegister(DefReg)) {
216  IsDead = false;
217  break;
218  }
220  // We don't care about self references.
221  if (&Use == Def)
222  continue;
223  if (DeadInstr.find(&Use) == DeadInstr.end()) {
224  IsDead = false;
225  break;
226  }
227  }
228  }
229 
230  if (!IsDead) continue;
231 
232  LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
233  DeadInstr.insert(Def);
234  }
235  }
236 }
237 
238 // Creates the more optimized patterns and generally does all the code
239 // transformations in this pass.
240 unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
241  if (MI->isCopy()) {
242  return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
243  }
244 
245  if (MI->isInsertSubreg()) {
246  Register DPRReg = MI->getOperand(1).getReg();
247  Register SPRReg = MI->getOperand(2).getReg();
248 
250  MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
251  MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
252 
253  if (DPRMI && SPRMI) {
254  // See if the first operand of this insert_subreg is IMPLICIT_DEF
255  MachineInstr *ECDef = elideCopies(DPRMI);
256  if (ECDef && ECDef->isImplicitDef()) {
257  // Another corner case - if we're inserting something that is purely
258  // a subreg copy of a DPR, just use that DPR.
259 
260  MachineInstr *EC = elideCopies(SPRMI);
261  // Is it a subreg copy of ssub_0?
262  if (EC && EC->isCopy() &&
263  EC->getOperand(1).getSubReg() == ARM::ssub_0) {
264  LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
265 
266  // Find the thing we're subreg copying out of - is it of the same
267  // regclass as DPRMI? (i.e. a DPR or QPR).
268  Register FullReg = SPRMI->getOperand(1).getReg();
269  const TargetRegisterClass *TRC =
270  MRI->getRegClass(MI->getOperand(1).getReg());
271  if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
272  LLVM_DEBUG(dbgs() << "Subreg copy is compatible - returning ");
273  LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
274  eraseInstrWithNoUses(MI);
275  return FullReg;
276  }
277  }
278 
279  return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
280  }
281  }
282  }
283  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
284  }
285 
286  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
287  &ARM::SPRRegClass)) {
288  // See if all bar one of the operands are IMPLICIT_DEF and insert the
289  // optimizer pattern accordingly.
290  unsigned NumImplicit = 0, NumTotal = 0;
291  unsigned NonImplicitReg = ~0U;
292 
293  for (unsigned I = 1; I < MI->getNumExplicitOperands(); ++I) {
294  if (!MI->getOperand(I).isReg())
295  continue;
296  ++NumTotal;
297  Register OpReg = MI->getOperand(I).getReg();
298 
299  if (!Register::isVirtualRegister(OpReg))
300  break;
301 
302  MachineInstr *Def = MRI->getVRegDef(OpReg);
303  if (!Def)
304  break;
305  if (Def->isImplicitDef())
306  ++NumImplicit;
307  else
308  NonImplicitReg = MI->getOperand(I).getReg();
309  }
310 
311  if (NumImplicit == NumTotal - 1)
312  return optimizeAllLanesPattern(MI, NonImplicitReg);
313  else
314  return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
315  }
316 
317  llvm_unreachable("Unhandled update pattern!");
318 }
319 
320 // Return true if this MachineInstr inserts a scalar (SPR) value into
321 // a D or Q register.
322 bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
323  // The only way we can do a partial register update is through a COPY,
324  // INSERT_SUBREG or REG_SEQUENCE.
325  if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
326  return true;
327 
328  if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
329  &ARM::SPRRegClass))
330  return true;
331 
332  if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
333  return true;
334 
335  return false;
336 }
337 
338 // Looks through full copies to get the instruction that defines the input
339 // operand for MI.
340 MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
341  if (!MI->isFullCopy())
342  return MI;
343  if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
344  return nullptr;
345  MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
346  if (!Def)
347  return nullptr;
348  return elideCopies(Def);
349 }
350 
351 // Look through full copies and PHIs to get the set of non-copy MachineInstrs
352 // that can produce MI.
353 void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
355  // Looking through PHIs may create loops so we need to track what
356  // instructions we have visited before.
357  std::set<MachineInstr *> Reached;
359  Front.push_back(MI);
360  while (Front.size() != 0) {
361  MI = Front.pop_back_val();
362 
363  // If we have already explored this MachineInstr, ignore it.
364  if (Reached.find(MI) != Reached.end())
365  continue;
366  Reached.insert(MI);
367  if (MI->isPHI()) {
368  for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
369  Register Reg = MI->getOperand(I).getReg();
371  continue;
372  }
373  MachineInstr *NewMI = MRI->getVRegDef(Reg);
374  if (!NewMI)
375  continue;
376  Front.push_back(NewMI);
377  }
378  } else if (MI->isFullCopy()) {
379  if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
380  continue;
381  MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
382  if (!NewMI)
383  continue;
384  Front.push_back(NewMI);
385  } else {
386  LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n");
387  Outs.push_back(MI);
388  }
389  }
390 }
391 
392 // Return the DPR virtual registers that are read by this machine instruction
393 // (if any).
394 SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
395  if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
396  MI->isKill())
397  return SmallVector<unsigned, 8>();
398 
400  for (MachineOperand &MO : MI->operands()) {
401  if (!MO.isReg() || !MO.isUse())
402  continue;
403  if (!usesRegClass(MO, &ARM::DPRRegClass) &&
404  !usesRegClass(MO, &ARM::QPRRegClass) &&
405  !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
406  continue;
407 
408  Defs.push_back(MO.getReg());
409  }
410  return Defs;
411 }
412 
413 // Creates a DPR register from an SPR one by using a VDUP.
414 unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
415  MachineBasicBlock::iterator InsertBefore,
416  const DebugLoc &DL, unsigned Reg,
417  unsigned Lane, bool QPR) {
418  Register Out =
419  MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
420  BuildMI(MBB, InsertBefore, DL,
421  TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
422  .addReg(Reg)
423  .addImm(Lane)
424  .add(predOps(ARMCC::AL));
425 
426  return Out;
427 }
428 
429 // Creates a SPR register from a DPR by copying the value in lane 0.
430 unsigned A15SDOptimizer::createExtractSubreg(
432  const DebugLoc &DL, unsigned DReg, unsigned Lane,
433  const TargetRegisterClass *TRC) {
434  Register Out = MRI->createVirtualRegister(TRC);
435  BuildMI(MBB,
436  InsertBefore,
437  DL,
438  TII->get(TargetOpcode::COPY), Out)
439  .addReg(DReg, 0, Lane);
440 
441  return Out;
442 }
443 
444 // Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
445 unsigned A15SDOptimizer::createRegSequence(
447  const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
448  Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
449  BuildMI(MBB,
450  InsertBefore,
451  DL,
452  TII->get(TargetOpcode::REG_SEQUENCE), Out)
453  .addReg(Reg1)
454  .addImm(ARM::dsub_0)
455  .addReg(Reg2)
456  .addImm(ARM::dsub_1);
457  return Out;
458 }
459 
460 // Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
461 // and merges them into one DPR register.
462 unsigned A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
463  MachineBasicBlock::iterator InsertBefore,
464  const DebugLoc &DL, unsigned Ssub0,
465  unsigned Ssub1) {
466  Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
467  BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
468  .addReg(Ssub0)
469  .addReg(Ssub1)
470  .addImm(1)
471  .add(predOps(ARMCC::AL));
472  return Out;
473 }
474 
475 unsigned A15SDOptimizer::createInsertSubreg(
477  const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
478  Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
479  BuildMI(MBB,
480  InsertBefore,
481  DL,
482  TII->get(TargetOpcode::INSERT_SUBREG), Out)
483  .addReg(DReg)
484  .addReg(ToInsert)
485  .addImm(Lane);
486 
487  return Out;
488 }
489 
490 unsigned
491 A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
492  MachineBasicBlock::iterator InsertBefore,
493  const DebugLoc &DL) {
494  Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
495  BuildMI(MBB,
496  InsertBefore,
497  DL,
498  TII->get(TargetOpcode::IMPLICIT_DEF), Out);
499  return Out;
500 }
501 
502 // This function inserts instructions in order to optimize interactions between
503 // SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
504 // lanes, and the using VEXT instructions to recompose the result.
505 unsigned
506 A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
508  DebugLoc DL = MI->getDebugLoc();
509  MachineBasicBlock &MBB = *MI->getParent();
510  InsertPt++;
511  unsigned Out;
512 
513  // DPair has the same length as QPR and also has two DPRs as subreg.
514  // Treat DPair as QPR.
515  if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
516  MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
517  unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
518  ARM::dsub_0, &ARM::DPRRegClass);
519  unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
520  ARM::dsub_1, &ARM::DPRRegClass);
521 
522  unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
523  unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
524  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
525 
526  unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
527  unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
528  Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
529 
530  Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
531 
532  } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
533  unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
534  unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
535  Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
536 
537  } else {
538  assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
539  "Found unexpected regclass!");
540 
541  unsigned PrefLane = getPrefSPRLane(Reg);
542  unsigned Lane;
543  switch (PrefLane) {
544  case ARM::ssub_0: Lane = 0; break;
545  case ARM::ssub_1: Lane = 1; break;
546  default: llvm_unreachable("Unknown preferred lane!");
547  }
548 
549  // Treat DPair as QPR
550  bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
551  usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
552 
553  Out = createImplicitDef(MBB, InsertPt, DL);
554  Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
555  Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
556  eraseInstrWithNoUses(MI);
557  }
558  return Out;
559 }
560 
561 bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
562  // We look for instructions that write S registers that are then read as
563  // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
564  // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
565  // merge two SPR values to form a DPR register. In order avoid false
566  // positives we make sure that there is an SPR producer so we look past
567  // COPY and PHI nodes to find it.
568  //
569  // The best code pattern for when an SPR producer is going to be used by a
570  // DPR or QPR consumer depends on whether the other lanes of the
571  // corresponding DPR/QPR are currently defined.
572  //
573  // We can handle these efficiently, depending on the type of
574  // pseudo-instruction that is producing the pattern
575  //
576  // * COPY: * VDUP all lanes and merge the results together
577  // using VEXTs.
578  //
579  // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
580  // lane, and the other lane(s) of the DPR/QPR register
581  // that we are inserting in are undefined, use the
582  // original DPR/QPR value.
583  // * Otherwise, fall back on the same stategy as COPY.
584  //
585  // * REG_SEQUENCE: * If all except one of the input operands are
586  // IMPLICIT_DEFs, insert the VDUP pattern for just the
587  // defined input operand
588  // * Otherwise, fall back on the same stategy as COPY.
589  //
590 
591  // First, get all the reads of D-registers done by this instruction.
592  SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
593  bool Modified = false;
594 
595  for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end();
596  I != E; ++I) {
597  // Follow the def-use chain for this DPR through COPYs, and also through
598  // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
599  // we can end up with multiple defs of this DPR.
600 
603  continue;
605  if (!Def)
606  continue;
607 
608  elideCopiesAndPHIs(Def, DefSrcs);
609 
610  for (MachineInstr *MI : DefSrcs) {
611  // If we've already analyzed and replaced this operand, don't do
612  // anything.
613  if (Replacements.find(MI) != Replacements.end())
614  continue;
615 
616  // Now, work out if the instruction causes a SPR->DPR dependency.
617  if (!hasPartialWrite(MI))
618  continue;
619 
620  // Collect all the uses of this MI's DPR def for updating later.
622  Register DPRDefReg = MI->getOperand(0).getReg();
624  E = MRI->use_end(); I != E; ++I)
625  Uses.push_back(&*I);
626 
627  // We can optimize this.
628  unsigned NewReg = optimizeSDPattern(MI);
629 
630  if (NewReg != 0) {
631  Modified = true;
633  E = Uses.end(); I != E; ++I) {
634  // Make sure to constrain the register class of the new register to
635  // match what we're replacing. Otherwise we can optimize a DPR_VFP2
636  // reference into a plain DPR, and that will end poorly. NewReg is
637  // always virtual here, so there will always be a matching subclass
638  // to find.
639  MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
640 
641  LLVM_DEBUG(dbgs() << "Replacing operand " << **I << " with "
642  << printReg(NewReg) << "\n");
643  (*I)->substVirtReg(NewReg, 0, *TRI);
644  }
645  }
646  Replacements[MI] = NewReg;
647  }
648  }
649  return Modified;
650 }
651 
652 bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
653  if (skipFunction(Fn.getFunction()))
654  return false;
655 
656  const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
657  // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
658  // enabled when NEON is available.
659  if (!(STI.useSplatVFPToNeon() && STI.hasNEON()))
660  return false;
661 
662  TII = STI.getInstrInfo();
663  TRI = STI.getRegisterInfo();
664  MRI = &Fn.getRegInfo();
665  bool Modified = false;
666 
667  LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n");
668 
669  DeadInstr.clear();
670  Replacements.clear();
671 
672  for (MachineBasicBlock &MBB : Fn) {
673  for (MachineInstr &MI : MBB) {
674  Modified |= runOnInstruction(&MI);
675  }
676  }
677 
678  for (MachineInstr *MI : DeadInstr) {
679  MI->eraseFromParent();
680  }
681 
682  return Modified;
683 }
684 
686  return new A15SDOptimizer();
687 }
ARMSubtarget.h
IsDead
bool IsDead
Definition: SILowerControlFlow.cpp:161
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::MachineInstr::isImplicitDef
bool isImplicitDef() const
Definition: MachineInstr.h:1260
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::SmallVector< unsigned, 8 >
Statistic.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:571
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:589
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:93
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::createA15SDOptimizerPass
FunctionPass * createA15SDOptimizerPass()
Definition: A15SDOptimizer.cpp:685
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:138
LoopDeletionResult::Modified
@ Modified
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
ARMBaseRegisterInfo.h
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:577
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMSubtarget::useSplatVFPToNeon
bool useSplatVFPToNeon() const
Definition: ARMSubtarget.h:717
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
llvm::SmallVectorImpl::const_iterator
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:563
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ARMBaseInstrInfo.h
llvm::codeview::CompileSym2Flags::EC
@ EC
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
ARM.h
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::ARMSubtarget::hasNEON
bool hasNEON() const
Definition: ARMSubtarget.h:665
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:583
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:464
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::MachineRegisterInfo::use_end
static use_iterator use_end()
Definition: MachineRegisterInfo.h:467
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
llvm::SmallVectorImpl< MachineInstr * >
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:540
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
Debug.h
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:773