LLVM 17.0.0git
A15SDOptimizer.cpp
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1//=== A15SDOptimizerPass.cpp - Optimize DPR and SPR register accesses on A15==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The Cortex-A15 processor employs a tracking scheme in its register renaming
10// in order to process each instruction's micro-ops speculatively and
11// out-of-order with appropriate forwarding. The ARM architecture allows VFP
12// instructions to read and write 32-bit S-registers. Each S-register
13// corresponds to one half (upper or lower) of an overlaid 64-bit D-register.
14//
15// There are several instruction patterns which can be used to provide this
16// capability which can provide higher performance than other, potentially more
17// direct patterns, specifically around when one micro-op reads a D-register
18// operand that has recently been written as one or more S-register results.
19//
20// This file defines a pre-regalloc pass which looks for SPR producers which
21// are going to be used by a DPR (or QPR) consumers and creates the more
22// optimized access pattern.
23//
24//===----------------------------------------------------------------------===//
25
26#include "ARM.h"
27#include "ARMBaseInstrInfo.h"
28#include "ARMBaseRegisterInfo.h"
29#include "ARMSubtarget.h"
30#include "llvm/ADT/Statistic.h"
38#include "llvm/Support/Debug.h"
40#include <map>
41#include <set>
42
43using namespace llvm;
44
45#define DEBUG_TYPE "a15-sd-optimizer"
46
47namespace {
48 struct A15SDOptimizer : public MachineFunctionPass {
49 static char ID;
50 A15SDOptimizer() : MachineFunctionPass(ID) {}
51
52 bool runOnMachineFunction(MachineFunction &Fn) override;
53
54 StringRef getPassName() const override { return "ARM A15 S->D optimizer"; }
55
56 private:
57 const ARMBaseInstrInfo *TII;
60
61 bool runOnInstruction(MachineInstr *MI);
62
63 //
64 // Instruction builder helpers
65 //
66 unsigned createDupLane(MachineBasicBlock &MBB,
67 MachineBasicBlock::iterator InsertBefore,
68 const DebugLoc &DL, unsigned Reg, unsigned Lane,
69 bool QPR = false);
70
71 unsigned createExtractSubreg(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator InsertBefore,
73 const DebugLoc &DL, unsigned DReg,
74 unsigned Lane, const TargetRegisterClass *TRC);
75
76 unsigned createVExt(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator InsertBefore,
78 const DebugLoc &DL, unsigned Ssub0, unsigned Ssub1);
79
80 unsigned createRegSequence(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator InsertBefore,
82 const DebugLoc &DL, unsigned Reg1,
83 unsigned Reg2);
84
85 unsigned createInsertSubreg(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator InsertBefore,
87 const DebugLoc &DL, unsigned DReg,
88 unsigned Lane, unsigned ToInsert);
89
90 unsigned createImplicitDef(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator InsertBefore,
92 const DebugLoc &DL);
93
94 //
95 // Various property checkers
96 //
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
98 bool hasPartialWrite(MachineInstr *MI);
100 unsigned getDPRLaneFromSPR(unsigned SReg);
101
102 //
103 // Methods used for getting the definitions of partial registers
104 //
105
106 MachineInstr *elideCopies(MachineInstr *MI);
107 void elideCopiesAndPHIs(MachineInstr *MI,
109
110 //
111 // Pattern optimization methods
112 //
113 unsigned optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg);
114 unsigned optimizeSDPattern(MachineInstr *MI);
115 unsigned getPrefSPRLane(unsigned SReg);
116
117 //
118 // Sanitizing method - used to make sure if don't leave dead code around.
119 //
120 void eraseInstrWithNoUses(MachineInstr *MI);
121
122 //
123 // A map used to track the changes done by this pass.
124 //
125 std::map<MachineInstr*, unsigned> Replacements;
126 std::set<MachineInstr *> DeadInstr;
127 };
128 char A15SDOptimizer::ID = 0;
129} // end anonymous namespace
130
131// Returns true if this is a use of a SPR register.
132bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
133 const TargetRegisterClass *TRC) {
134 if (!MO.isReg())
135 return false;
136 Register Reg = MO.getReg();
137
138 if (Reg.isVirtual())
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
140 else
141 return TRC->contains(Reg);
142}
143
144unsigned A15SDOptimizer::getDPRLaneFromSPR(unsigned SReg) {
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
146 &ARM::DPRRegClass);
147 if (DReg != ARM::NoRegister) return ARM::ssub_1;
148 return ARM::ssub_0;
149}
150
151// Get the subreg type that is most likely to be coalesced
152// for an SPR register that will be used in VDUP32d pseudo.
153unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) {
155 return getDPRLaneFromSPR(SReg);
156
157 MachineInstr *MI = MRI->getVRegDef(SReg);
158 if (!MI) return ARM::ssub_0;
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
160 if (!MO) return ARM::ssub_0;
161 assert(MO->isReg() && "Non-register operand found!");
162
163 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
164 &ARM::SPRRegClass)) {
165 SReg = MI->getOperand(1).getReg();
166 }
167
168 if (Register::isVirtualRegister(SReg)) {
169 if (MO->getSubReg() == ARM::ssub_1) return ARM::ssub_1;
170 return ARM::ssub_0;
171 }
172 return getDPRLaneFromSPR(SReg);
173}
174
175// MI is known to be dead. Figure out what instructions
176// are also made dead by this and mark them for removal.
177void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) {
179 DeadInstr.insert(MI);
180
181 LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
182 Front.push_back(MI);
183
184 while (Front.size() != 0) {
185 MI = Front.pop_back_val();
186
187 // MI is already known to be dead. We need to see
188 // if other instructions can also be removed.
189 for (MachineOperand &MO : MI->operands()) {
190 if ((!MO.isReg()) || (!MO.isUse()))
191 continue;
192 Register Reg = MO.getReg();
193 if (!Reg.isVirtual())
194 continue;
195 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
196
197 if (!Op)
198 continue;
199
200 MachineInstr *Def = Op->getParent();
201
202 // We don't need to do anything if we have already marked
203 // this instruction as being dead.
204 if (DeadInstr.find(Def) != DeadInstr.end())
205 continue;
206
207 // Check if all the uses of this instruction are marked as
208 // dead. If so, we can also mark this instruction as being
209 // dead.
210 bool IsDead = true;
211 for (MachineOperand &MODef : Def->operands()) {
212 if ((!MODef.isReg()) || (!MODef.isDef()))
213 continue;
214 Register DefReg = MODef.getReg();
215 if (!DefReg.isVirtual()) {
216 IsDead = false;
217 break;
218 }
219 for (MachineInstr &Use : MRI->use_instructions(Reg)) {
220 // We don't care about self references.
221 if (&Use == Def)
222 continue;
223 if (DeadInstr.find(&Use) == DeadInstr.end()) {
224 IsDead = false;
225 break;
226 }
227 }
228 }
229
230 if (!IsDead) continue;
231
232 LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
233 DeadInstr.insert(Def);
234 }
235 }
236}
237
238// Creates the more optimized patterns and generally does all the code
239// transformations in this pass.
240unsigned A15SDOptimizer::optimizeSDPattern(MachineInstr *MI) {
241 if (MI->isCopy()) {
242 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
243 }
244
245 if (MI->isInsertSubreg()) {
246 Register DPRReg = MI->getOperand(1).getReg();
247 Register SPRReg = MI->getOperand(2).getReg();
248
249 if (DPRReg.isVirtual() && SPRReg.isVirtual()) {
250 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
251 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
252
253 if (DPRMI && SPRMI) {
254 // See if the first operand of this insert_subreg is IMPLICIT_DEF
255 MachineInstr *ECDef = elideCopies(DPRMI);
256 if (ECDef && ECDef->isImplicitDef()) {
257 // Another corner case - if we're inserting something that is purely
258 // a subreg copy of a DPR, just use that DPR.
259
260 MachineInstr *EC = elideCopies(SPRMI);
261 // Is it a subreg copy of ssub_0?
262 if (EC && EC->isCopy() &&
263 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
264 LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
265
266 // Find the thing we're subreg copying out of - is it of the same
267 // regclass as DPRMI? (i.e. a DPR or QPR).
268 Register FullReg = SPRMI->getOperand(1).getReg();
269 const TargetRegisterClass *TRC =
270 MRI->getRegClass(MI->getOperand(1).getReg());
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
272 LLVM_DEBUG(dbgs() << "Subreg copy is compatible - returning ");
273 LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
274 eraseInstrWithNoUses(MI);
275 return FullReg;
276 }
277 }
278
279 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
280 }
281 }
282 }
283 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
284 }
285
286 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
287 &ARM::SPRRegClass)) {
288 // See if all bar one of the operands are IMPLICIT_DEF and insert the
289 // optimizer pattern accordingly.
290 unsigned NumImplicit = 0, NumTotal = 0;
291 unsigned NonImplicitReg = ~0U;
292
293 for (MachineOperand &MO : llvm::drop_begin(MI->explicit_operands())) {
294 if (!MO.isReg())
295 continue;
296 ++NumTotal;
297 Register OpReg = MO.getReg();
298
299 if (!OpReg.isVirtual())
300 break;
301
302 MachineInstr *Def = MRI->getVRegDef(OpReg);
303 if (!Def)
304 break;
305 if (Def->isImplicitDef())
306 ++NumImplicit;
307 else
308 NonImplicitReg = MO.getReg();
309 }
310
311 if (NumImplicit == NumTotal - 1)
312 return optimizeAllLanesPattern(MI, NonImplicitReg);
313 else
314 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
315 }
316
317 llvm_unreachable("Unhandled update pattern!");
318}
319
320// Return true if this MachineInstr inserts a scalar (SPR) value into
321// a D or Q register.
322bool A15SDOptimizer::hasPartialWrite(MachineInstr *MI) {
323 // The only way we can do a partial register update is through a COPY,
324 // INSERT_SUBREG or REG_SEQUENCE.
325 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
326 return true;
327
328 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
329 &ARM::SPRRegClass))
330 return true;
331
332 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
333 return true;
334
335 return false;
336}
337
338// Looks through full copies to get the instruction that defines the input
339// operand for MI.
340MachineInstr *A15SDOptimizer::elideCopies(MachineInstr *MI) {
341 if (!MI->isFullCopy())
342 return MI;
343 if (!MI->getOperand(1).getReg().isVirtual())
344 return nullptr;
345 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
346 if (!Def)
347 return nullptr;
348 return elideCopies(Def);
349}
350
351// Look through full copies and PHIs to get the set of non-copy MachineInstrs
352// that can produce MI.
353void A15SDOptimizer::elideCopiesAndPHIs(MachineInstr *MI,
355 // Looking through PHIs may create loops so we need to track what
356 // instructions we have visited before.
357 std::set<MachineInstr *> Reached;
359 Front.push_back(MI);
360 while (Front.size() != 0) {
361 MI = Front.pop_back_val();
362
363 // If we have already explored this MachineInstr, ignore it.
364 if (!Reached.insert(MI).second)
365 continue;
366 if (MI->isPHI()) {
367 for (unsigned I = 1, E = MI->getNumOperands(); I != E; I += 2) {
368 Register Reg = MI->getOperand(I).getReg();
369 if (!Reg.isVirtual()) {
370 continue;
371 }
372 MachineInstr *NewMI = MRI->getVRegDef(Reg);
373 if (!NewMI)
374 continue;
375 Front.push_back(NewMI);
376 }
377 } else if (MI->isFullCopy()) {
378 if (!MI->getOperand(1).getReg().isVirtual())
379 continue;
380 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
381 if (!NewMI)
382 continue;
383 Front.push_back(NewMI);
384 } else {
385 LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n");
386 Outs.push_back(MI);
387 }
388 }
389}
390
391// Return the DPR virtual registers that are read by this machine instruction
392// (if any).
393SmallVector<unsigned, 8> A15SDOptimizer::getReadDPRs(MachineInstr *MI) {
394 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() ||
395 MI->isKill())
397
399 for (MachineOperand &MO : MI->operands()) {
400 if (!MO.isReg() || !MO.isUse())
401 continue;
402 if (!usesRegClass(MO, &ARM::DPRRegClass) &&
403 !usesRegClass(MO, &ARM::QPRRegClass) &&
404 !usesRegClass(MO, &ARM::DPairRegClass)) // Treat DPair as QPR
405 continue;
406
407 Defs.push_back(MO.getReg());
408 }
409 return Defs;
410}
411
412// Creates a DPR register from an SPR one by using a VDUP.
413unsigned A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
414 MachineBasicBlock::iterator InsertBefore,
415 const DebugLoc &DL, unsigned Reg,
416 unsigned Lane, bool QPR) {
417 Register Out =
418 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
419 BuildMI(MBB, InsertBefore, DL,
420 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
421 .addReg(Reg)
422 .addImm(Lane)
424
425 return Out;
426}
427
428// Creates a SPR register from a DPR by copying the value in lane 0.
429unsigned A15SDOptimizer::createExtractSubreg(
431 const DebugLoc &DL, unsigned DReg, unsigned Lane,
432 const TargetRegisterClass *TRC) {
433 Register Out = MRI->createVirtualRegister(TRC);
434 BuildMI(MBB,
435 InsertBefore,
436 DL,
437 TII->get(TargetOpcode::COPY), Out)
438 .addReg(DReg, 0, Lane);
439
440 return Out;
441}
442
443// Takes two SPR registers and creates a DPR by using a REG_SEQUENCE.
444unsigned A15SDOptimizer::createRegSequence(
446 const DebugLoc &DL, unsigned Reg1, unsigned Reg2) {
447 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
448 BuildMI(MBB,
449 InsertBefore,
450 DL,
451 TII->get(TargetOpcode::REG_SEQUENCE), Out)
452 .addReg(Reg1)
453 .addImm(ARM::dsub_0)
454 .addReg(Reg2)
455 .addImm(ARM::dsub_1);
456 return Out;
457}
458
459// Takes two DPR registers that have previously been VDUPed (Ssub0 and Ssub1)
460// and merges them into one DPR register.
461unsigned A15SDOptimizer::createVExt(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator InsertBefore,
463 const DebugLoc &DL, unsigned Ssub0,
464 unsigned Ssub1) {
465 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
466 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
467 .addReg(Ssub0)
468 .addReg(Ssub1)
469 .addImm(1)
471 return Out;
472}
473
474unsigned A15SDOptimizer::createInsertSubreg(
476 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) {
477 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
478 BuildMI(MBB,
479 InsertBefore,
480 DL,
481 TII->get(TargetOpcode::INSERT_SUBREG), Out)
482 .addReg(DReg)
483 .addReg(ToInsert)
484 .addImm(Lane);
485
486 return Out;
487}
488
489unsigned
490A15SDOptimizer::createImplicitDef(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator InsertBefore,
492 const DebugLoc &DL) {
493 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
494 BuildMI(MBB,
495 InsertBefore,
496 DL,
497 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
498 return Out;
499}
500
501// This function inserts instructions in order to optimize interactions between
502// SPR registers and DPR/QPR registers. It does so by performing VDUPs on all
503// lanes, and the using VEXT instructions to recompose the result.
504unsigned
505A15SDOptimizer::optimizeAllLanesPattern(MachineInstr *MI, unsigned Reg) {
507 DebugLoc DL = MI->getDebugLoc();
508 MachineBasicBlock &MBB = *MI->getParent();
509 InsertPt++;
510 unsigned Out;
511
512 // DPair has the same length as QPR and also has two DPRs as subreg.
513 // Treat DPair as QPR.
514 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
515 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
516 unsigned DSub0 = createExtractSubreg(MBB, InsertPt, DL, Reg,
517 ARM::dsub_0, &ARM::DPRRegClass);
518 unsigned DSub1 = createExtractSubreg(MBB, InsertPt, DL, Reg,
519 ARM::dsub_1, &ARM::DPRRegClass);
520
521 unsigned Out1 = createDupLane(MBB, InsertPt, DL, DSub0, 0);
522 unsigned Out2 = createDupLane(MBB, InsertPt, DL, DSub0, 1);
523 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
524
525 unsigned Out3 = createDupLane(MBB, InsertPt, DL, DSub1, 0);
526 unsigned Out4 = createDupLane(MBB, InsertPt, DL, DSub1, 1);
527 Out2 = createVExt(MBB, InsertPt, DL, Out3, Out4);
528
529 Out = createRegSequence(MBB, InsertPt, DL, Out, Out2);
530
531 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
532 unsigned Out1 = createDupLane(MBB, InsertPt, DL, Reg, 0);
533 unsigned Out2 = createDupLane(MBB, InsertPt, DL, Reg, 1);
534 Out = createVExt(MBB, InsertPt, DL, Out1, Out2);
535
536 } else {
537 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
538 "Found unexpected regclass!");
539
540 unsigned PrefLane = getPrefSPRLane(Reg);
541 unsigned Lane;
542 switch (PrefLane) {
543 case ARM::ssub_0: Lane = 0; break;
544 case ARM::ssub_1: Lane = 1; break;
545 default: llvm_unreachable("Unknown preferred lane!");
546 }
547
548 // Treat DPair as QPR
549 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
550 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
551
552 Out = createImplicitDef(MBB, InsertPt, DL);
553 Out = createInsertSubreg(MBB, InsertPt, DL, Out, PrefLane, Reg);
554 Out = createDupLane(MBB, InsertPt, DL, Out, Lane, UsesQPR);
555 eraseInstrWithNoUses(MI);
556 }
557 return Out;
558}
559
560bool A15SDOptimizer::runOnInstruction(MachineInstr *MI) {
561 // We look for instructions that write S registers that are then read as
562 // D/Q registers. These can only be caused by COPY, INSERT_SUBREG and
563 // REG_SEQUENCE pseudos that insert an SPR value into a DPR register or
564 // merge two SPR values to form a DPR register. In order avoid false
565 // positives we make sure that there is an SPR producer so we look past
566 // COPY and PHI nodes to find it.
567 //
568 // The best code pattern for when an SPR producer is going to be used by a
569 // DPR or QPR consumer depends on whether the other lanes of the
570 // corresponding DPR/QPR are currently defined.
571 //
572 // We can handle these efficiently, depending on the type of
573 // pseudo-instruction that is producing the pattern
574 //
575 // * COPY: * VDUP all lanes and merge the results together
576 // using VEXTs.
577 //
578 // * INSERT_SUBREG: * If the SPR value was originally in another DPR/QPR
579 // lane, and the other lane(s) of the DPR/QPR register
580 // that we are inserting in are undefined, use the
581 // original DPR/QPR value.
582 // * Otherwise, fall back on the same stategy as COPY.
583 //
584 // * REG_SEQUENCE: * If all except one of the input operands are
585 // IMPLICIT_DEFs, insert the VDUP pattern for just the
586 // defined input operand
587 // * Otherwise, fall back on the same stategy as COPY.
588 //
589
590 // First, get all the reads of D-registers done by this instruction.
591 SmallVector<unsigned, 8> Defs = getReadDPRs(MI);
592 bool Modified = false;
593
594 for (unsigned I : Defs) {
595 // Follow the def-use chain for this DPR through COPYs, and also through
596 // PHIs (which are essentially multi-way COPYs). It is because of PHIs that
597 // we can end up with multiple defs of this DPR.
598
601 continue;
602 MachineInstr *Def = MRI->getVRegDef(I);
603 if (!Def)
604 continue;
605
606 elideCopiesAndPHIs(Def, DefSrcs);
607
608 for (MachineInstr *MI : DefSrcs) {
609 // If we've already analyzed and replaced this operand, don't do
610 // anything.
611 if (Replacements.find(MI) != Replacements.end())
612 continue;
613
614 // Now, work out if the instruction causes a SPR->DPR dependency.
615 if (!hasPartialWrite(MI))
616 continue;
617
618 // Collect all the uses of this MI's DPR def for updating later.
620 Register DPRDefReg = MI->getOperand(0).getReg();
621 for (MachineOperand &MO : MRI->use_operands(DPRDefReg))
622 Uses.push_back(&MO);
623
624 // We can optimize this.
625 unsigned NewReg = optimizeSDPattern(MI);
626
627 if (NewReg != 0) {
628 Modified = true;
629 for (MachineOperand *Use : Uses) {
630 // Make sure to constrain the register class of the new register to
631 // match what we're replacing. Otherwise we can optimize a DPR_VFP2
632 // reference into a plain DPR, and that will end poorly. NewReg is
633 // always virtual here, so there will always be a matching subclass
634 // to find.
635 MRI->constrainRegClass(NewReg, MRI->getRegClass(Use->getReg()));
636
637 LLVM_DEBUG(dbgs() << "Replacing operand " << *Use << " with "
638 << printReg(NewReg) << "\n");
639 Use->substVirtReg(NewReg, 0, *TRI);
640 }
641 }
642 Replacements[MI] = NewReg;
643 }
644 }
645 return Modified;
646}
647
648bool A15SDOptimizer::runOnMachineFunction(MachineFunction &Fn) {
649 if (skipFunction(Fn.getFunction()))
650 return false;
651
652 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
653 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
654 // enabled when NEON is available.
655 if (!(STI.useSplatVFPToNeon() && STI.hasNEON()))
656 return false;
657
658 TII = STI.getInstrInfo();
659 TRI = STI.getRegisterInfo();
660 MRI = &Fn.getRegInfo();
661 bool Modified = false;
662
663 LLVM_DEBUG(dbgs() << "Running on function " << Fn.getName() << "\n");
664
665 DeadInstr.clear();
666 Replacements.clear();
667
668 for (MachineBasicBlock &MBB : Fn) {
669 for (MachineInstr &MI : MBB) {
670 Modified |= runOnInstruction(&MI);
671 }
672 }
673
674 for (MachineInstr *MI : DeadInstr) {
675 MI->eraseFromParent();
676 }
677
678 return Modified;
679}
680
682 return new A15SDOptimizer();
683}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SmallPtrSet< MachineInstr *, 2 > Uses
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool IsDead
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:262
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:274
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool isImplicitDef() const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:809
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:386
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createA15SDOptimizerPass()
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.