LLVM
15.0.0git
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#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "AMDGPUGenGlobalISel.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "amdgpu-isel" |
#define | GET_GLOBALISEL_IMPL |
#define | AMDGPUSubtarget GCNSubtarget |
#define | GET_GLOBALISEL_PREDICATES_INIT |
#define | GET_GLOBALISEL_TEMPORARIES_INIT |
Functions | |
static unsigned | getLogicalBitOpcode (unsigned Opc, bool Is64) |
static int | getV_CMPOpcode (CmpInst::Predicate P, unsigned Size) |
static unsigned | gwsIntrinToOpcode (unsigned IntrID) |
static bool | parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail) |
static int | sizeToSubRegIndex (unsigned Size) |
static bool | shouldUseAndMask (unsigned Size, unsigned &Mask) |
static bool | isConstant (const MachineInstr &MI) |
static bool | isVCmpResult (Register Reg, MachineRegisterInfo &MRI) |
static std::pair< Register, unsigned > | computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize) |
Return the register to use for the index value, and the subregister to use for the indirectly accessed register. More... | |
static bool | isZeroOrUndef (int X) |
static bool | isOneOrUndef (int X) |
static bool | isZeroOrOneOrUndef (int X) |
static Register | normalizeVOP3PMask (int NewMask[2], Register Src0, Register Src1, ArrayRef< int > Mask) |
static Register | matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg) |
Match a zero extend from a 32-bit value to 64-bits. More... | |
static Register | getWaveAddress (const MachineInstr *Def) |
static void | addZeroImm (MachineInstrBuilder &MIB) |
static Register | buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr) |
Return a resource descriptor for use with an arbitrary 64-bit pointer. More... | |
static Register | buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr) |
static Register | buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr) |
static Optional< uint64_t > | getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI) |
Get an immediate that must be 32-bits, and treated as zero extended. More... | |
Variables | |
static cl::opt< bool > | AllowRiskySelect ("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden) |
This file implements the targeting of the InstructionSelector class for AMDGPU.
Definition in file AMDGPUInstructionSelector.cpp.
#define AMDGPUSubtarget GCNSubtarget |
Definition at line 42 of file AMDGPUInstructionSelector.cpp.
#define DEBUG_TYPE "amdgpu-isel" |
Definition at line 30 of file AMDGPUInstructionSelector.cpp.
#define GET_GLOBALISEL_IMPL |
Definition at line 41 of file AMDGPUInstructionSelector.cpp.
#define GET_GLOBALISEL_PREDICATES_INIT |
#define GET_GLOBALISEL_TEMPORARIES_INIT |
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Definition at line 4443 of file AMDGPUInstructionSelector.cpp.
References llvm::MachineInstrBuilder::addImm().
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Definition at line 4492 of file AMDGPUInstructionSelector.cpp.
References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.
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Definition at line 4501 of file AMDGPUInstructionSelector.cpp.
References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.
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Return a resource descriptor for use with an arbitrary 64-bit pointer.
If BasePtr
is not valid, a null base pointer will be used.
Definition at line 4449 of file AMDGPUInstructionSelector.cpp.
References B, llvm::MachineRegisterInfo::createVirtualRegister(), and MRI.
Referenced by buildAddr64RSrc(), and buildOffsetSrc().
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Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
Definition at line 2634 of file AMDGPUInstructionSelector.cpp.
References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::ArrayRef< T >::size(), and TRI.
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Get an immediate that must be 32-bits, and treated as zero extended.
Definition at line 4763 of file AMDGPUInstructionSelector.cpp.
References llvm::getIConstantVRegSExtVal(), llvm::isInt< 32 >(), llvm::Lo_32(), MRI, and llvm::None.
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Definition at line 270 of file AMDGPUInstructionSelector.cpp.
References llvm_unreachable.
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Definition at line 1007 of file AMDGPUInstructionSelector.cpp.
References llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, and P.
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Definition at line 4265 of file AMDGPUInstructionSelector.cpp.
References llvm::tgtok::Def.
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Definition at line 1361 of file AMDGPUInstructionSelector.cpp.
References llvm_unreachable.
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Definition at line 2335 of file AMDGPUInstructionSelector.cpp.
References MI.
Referenced by llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), and llvm::SCCPInstVisitor::isStructLatticeConstant().
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Definition at line 2813 of file AMDGPUInstructionSelector.cpp.
References X.
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Definition at line 2433 of file AMDGPUInstructionSelector.cpp.
References llvm::MachineRegisterInfo::getUniqueVRegDef(), MI, and MRI.
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Definition at line 2817 of file AMDGPUInstructionSelector.cpp.
References X.
Referenced by normalizeVOP3PMask().
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Definition at line 2809 of file AMDGPUInstructionSelector.cpp.
References X.
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Match a zero extend from a 32-bit value to 64-bits.
Definition at line 3215 of file AMDGPUInstructionSelector.cpp.
References llvm::tgtok::Def, llvm::getDefIgnoringCopies(), llvm::MachineRegisterInfo::getType(), llvm::MIPatternMatch::m_GZExt(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_ZeroInt(), llvm::MIPatternMatch::mi_match(), MRI, and llvm::LLT::scalar().
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Definition at line 2823 of file AMDGPUInstructionSelector.cpp.
References assert(), isZeroOrOneOrUndef(), and llvm::BitmaskEnumDetail::Mask().
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Definition at line 1518 of file AMDGPUInstructionSelector.cpp.
References x2().
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Size
bits will be an inline immediate. Definition at line 2018 of file AMDGPUInstructionSelector.cpp.
References llvm::BitmaskEnumDetail::Mask().
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Definition at line 1876 of file AMDGPUInstructionSelector.cpp.
References llvm::PowerOf2Ceil().