LLVM 19.0.0git
Macros | Functions
AMDGPUInstructionSelector.cpp File Reference

This file implements the targeting of the InstructionSelector class for AMDGPU. More...

#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include <optional>
#include "AMDGPUGenGlobalISel.inc"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "amdgpu-isel"
 
#define GET_GLOBALISEL_IMPL
 
#define AMDGPUSubtarget   GCNSubtarget
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static Register getWaveAddress (const MachineInstr *Def)
 
static unsigned getLogicalBitOpcode (unsigned Opc, bool Is64)
 
static int getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
 
static unsigned gwsIntrinToOpcode (unsigned IntrID)
 
static bool parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
 
static int sizeToSubRegIndex (unsigned Size)
 
static bool shouldUseAndMask (unsigned Size, unsigned &Mask)
 
static bool isExtractHiElt (MachineRegisterInfo &MRI, Register In, Register &Out)
 
static bool isConstant (const MachineInstr &MI)
 
static bool isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
 
static std::pair< Register, unsignedcomputeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits)
 Return the register to use for the index value, and the subregister to use for the indirectly accessed register.
 
static Register matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
 Match a zero extend from a 32-bit value to 64-bits.
 
static Register buildRegSequence (SmallVectorImpl< Register > &Elts, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
 
static void selectWMMAModsNegAbs (unsigned ModOpcode, unsigned &Mods, SmallVectorImpl< Register > &Elts, Register &Src, MachineInstr *InsertPt, MachineRegisterInfo &MRI)
 
static bool isNoUnsignedWrap (MachineInstr *Addr)
 
static void addZeroImm (MachineInstrBuilder &MIB)
 
static Register buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
 Return a resource descriptor for use with an arbitrary 64-bit pointer.
 
static Register buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
 
static Register buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
 
static std::optional< uint64_tgetConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
 Get an immediate that must be 32-bits, and treated as zero extended.
 
static MachineInstrstripBitCast (MachineInstr *MI, MachineRegisterInfo &MRI)
 
static MachineInstrisExtractHiElt (MachineInstr *Inst, MachineRegisterInfo &MRI)
 
unsigned getNamedBarrierOp (bool HasInlineConst, Intrinsic::ID IntrID)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:
This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

◆ AMDGPUSubtarget

Definition at line 38 of file AMDGPUInstructionSelector.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-isel"

Definition at line 32 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 37 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ addZeroImm()

static void addZeroImm ( MachineInstrBuilder MIB)
static

◆ buildAddr64RSrc()

static Register buildAddr64RSrc ( MachineIRBuilder B,
MachineRegisterInfo MRI,
const SIInstrInfo TII,
Register  BasePtr 
)
static

Definition at line 5083 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildOffsetSrc()

static Register buildOffsetSrc ( MachineIRBuilder B,
MachineRegisterInfo MRI,
const SIInstrInfo TII,
Register  BasePtr 
)
static

Definition at line 5092 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildRegSequence()

static Register buildRegSequence ( SmallVectorImpl< Register > &  Elts,
MachineInstr InsertPt,
MachineRegisterInfo MRI 
)
static

◆ buildRSRC()

static Register buildRSRC ( MachineIRBuilder B,
MachineRegisterInfo MRI,
uint32_t  FormatLo,
uint32_t  FormatHi,
Register  BasePtr 
)
static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 5040 of file AMDGPUInstructionSelector.cpp.

References B, and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

◆ computeIndirectRegIndex()

static std::pair< Register, unsigned > computeIndirectRegIndex ( MachineRegisterInfo MRI,
const SIRegisterInfo TRI,
const TargetRegisterClass SuperRC,
Register  IdxReg,
unsigned  EltSize,
GISelKnownBits KnownBits 
)
static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 3057 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::Offset, llvm::ArrayRef< T >::size(), and TRI.

◆ getConstantZext32Val()

static std::optional< uint64_t > getConstantZext32Val ( Register  Reg,
const MachineRegisterInfo MRI 
)
static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 5312 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::Lo_32(), and MRI.

◆ getLogicalBitOpcode()

static unsigned getLogicalBitOpcode ( unsigned  Opc,
bool  Is64 
)
static

Definition at line 276 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ getNamedBarrierOp()

unsigned getNamedBarrierOp ( bool  HasInlineConst,
Intrinsic::ID  IntrID 
)

Definition at line 5544 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ getV_CMPOpcode()

static int getV_CMPOpcode ( CmpInst::Predicate  P,
unsigned  Size,
const GCNSubtarget ST 
)
static

◆ getWaveAddress()

static Register getWaveAddress ( const MachineInstr Def)
static

Definition at line 70 of file AMDGPUInstructionSelector.cpp.

◆ gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned  IntrID)
static

Definition at line 1634 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ isConstant()

static bool isConstant ( const MachineInstr MI)
static

◆ isExtractHiElt() [1/2]

static MachineInstr * isExtractHiElt ( MachineInstr Inst,
MachineRegisterInfo MRI 
)
static

◆ isExtractHiElt() [2/2]

static bool isExtractHiElt ( MachineRegisterInfo MRI,
Register  In,
Register Out 
)
static

◆ isNoUnsignedWrap()

static bool isNoUnsignedWrap ( MachineInstr Addr)
static

Definition at line 4752 of file AMDGPUInstructionSelector.cpp.

References Addr, and llvm::MachineInstr::NoUWrap.

◆ isVCmpResult()

static bool isVCmpResult ( Register  Reg,
MachineRegisterInfo MRI 
)
static

Definition at line 2851 of file AMDGPUInstructionSelector.cpp.

References isVCmpResult(), MI, and MRI.

Referenced by isVCmpResult().

◆ matchZeroExtendFromS32()

static Register matchZeroExtendFromS32 ( MachineRegisterInfo MRI,
Register  Reg 
)
static

◆ parseTexFail()

static bool parseTexFail ( uint64_t  TexFailCtrl,
bool TFE,
bool LWE,
bool IsTexFail 
)
static

Definition at line 1803 of file AMDGPUInstructionSelector.cpp.

◆ selectWMMAModsNegAbs()

static void selectWMMAModsNegAbs ( unsigned  ModOpcode,
unsigned Mods,
SmallVectorImpl< Register > &  Elts,
Register Src,
MachineInstr InsertPt,
MachineRegisterInfo MRI 
)
static

◆ shouldUseAndMask()

static bool shouldUseAndMask ( unsigned  Size,
unsigned Mask 
)
static
Returns
true if a bitmask for Size bits will be an inline immediate.

Definition at line 2366 of file AMDGPUInstructionSelector.cpp.

References Size.

◆ sizeToSubRegIndex()

static int sizeToSubRegIndex ( unsigned  Size)
static

Definition at line 2218 of file AMDGPUInstructionSelector.cpp.

References llvm::bit_ceil(), Size, and sizeToSubRegIndex().

Referenced by sizeToSubRegIndex().

◆ stripBitCast()

static MachineInstr * stripBitCast ( MachineInstr MI,
MachineRegisterInfo MRI 
)
static

Definition at line 5373 of file AMDGPUInstructionSelector.cpp.

References llvm::getDefIgnoringCopies(), MI, and MRI.

Referenced by isExtractHiElt().