LLVM  16.0.0git
Macros | Functions | Variables
AMDGPUInstructionSelector.cpp File Reference
#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include <optional>
#include "AMDGPUGenGlobalISel.inc"
Include dependency graph for AMDGPUInstructionSelector.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "amdgpu-isel"
 
#define GET_GLOBALISEL_IMPL
 
#define AMDGPUSubtarget   GCNSubtarget
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static unsigned getLogicalBitOpcode (unsigned Opc, bool Is64)
 
static int getV_CMPOpcode (CmpInst::Predicate P, unsigned Size, const GCNSubtarget &ST)
 
static unsigned gwsIntrinToOpcode (unsigned IntrID)
 
static bool parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)
 
static int sizeToSubRegIndex (unsigned Size)
 
static bool shouldUseAndMask (unsigned Size, unsigned &Mask)
 
static bool isConstant (const MachineInstr &MI)
 
static bool isVCmpResult (Register Reg, MachineRegisterInfo &MRI)
 
static std::pair< Register, unsigned > computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize, GISelKnownBits &KnownBits)
 Return the register to use for the index value, and the subregister to use for the indirectly accessed register. More...
 
static Register matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
 Match a zero extend from a 32-bit value to 64-bits. More...
 
static Register getWaveAddress (const MachineInstr *Def)
 
static void addZeroImm (MachineInstrBuilder &MIB)
 
static Register buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
 Return a resource descriptor for use with an arbitrary 64-bit pointer. More...
 
static Register buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
 
static Register buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)
 
static Optional< uint64_tgetConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
 Get an immediate that must be 32-bits, and treated as zero extended. More...
 
static MachineInstrstripBitCast (MachineInstr *MI, MachineRegisterInfo &MRI)
 
static MachineInstrisExtractHiElt (MachineInstr *Inst, MachineRegisterInfo &MRI)
 

Variables

static cl::opt< bool > AllowRiskySelect ("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:
This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

◆ AMDGPUSubtarget

Definition at line 43 of file AMDGPUInstructionSelector.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-isel"

Definition at line 31 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 42 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ addZeroImm()

static void addZeroImm ( MachineInstrBuilder MIB)
static

◆ buildAddr64RSrc()

static Register buildAddr64RSrc ( MachineIRBuilder B,
MachineRegisterInfo MRI,
const SIInstrInfo TII,
Register  BasePtr 
)
static

Definition at line 4552 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildOffsetSrc()

static Register buildOffsetSrc ( MachineIRBuilder B,
MachineRegisterInfo MRI,
const SIInstrInfo TII,
Register  BasePtr 
)
static

Definition at line 4561 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildRSRC()

static Register buildRSRC ( MachineIRBuilder B,
MachineRegisterInfo MRI,
uint32_t  FormatLo,
uint32_t  FormatHi,
Register  BasePtr 
)
static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 4509 of file AMDGPUInstructionSelector.cpp.

References B, llvm::MachineRegisterInfo::createVirtualRegister(), and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

◆ computeIndirectRegIndex()

static std::pair<Register, unsigned> computeIndirectRegIndex ( MachineRegisterInfo MRI,
const SIRegisterInfo TRI,
const TargetRegisterClass SuperRC,
Register  IdxReg,
unsigned  EltSize,
GISelKnownBits KnownBits 
)
static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 2897 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, llvm::ArrayRef< T >::size(), and TRI.

◆ getConstantZext32Val()

static Optional<uint64_t> getConstantZext32Val ( Register  Reg,
const MachineRegisterInfo MRI 
)
static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 4823 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::Lo_32(), MRI, and llvm::None.

◆ getLogicalBitOpcode()

static unsigned getLogicalBitOpcode ( unsigned  Opc,
bool  Is64 
)
static

Definition at line 271 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ getV_CMPOpcode()

static int getV_CMPOpcode ( CmpInst::Predicate  P,
unsigned  Size,
const GCNSubtarget ST 
)
static

◆ getWaveAddress()

static Register getWaveAddress ( const MachineInstr Def)
static

Definition at line 4325 of file AMDGPUInstructionSelector.cpp.

References llvm::tgtok::Def.

◆ gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned  IntrID)
static

Definition at line 1576 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ isConstant()

static bool isConstant ( const MachineInstr MI)
static

◆ isExtractHiElt()

static MachineInstr* isExtractHiElt ( MachineInstr Inst,
MachineRegisterInfo MRI 
)
static

◆ isVCmpResult()

static bool isVCmpResult ( Register  Reg,
MachineRegisterInfo MRI 
)
static

◆ matchZeroExtendFromS32()

static Register matchZeroExtendFromS32 ( MachineRegisterInfo MRI,
Register  Reg 
)
static

◆ parseTexFail()

static bool parseTexFail ( uint64_t  TexFailCtrl,
bool &  TFE,
bool &  LWE,
bool &  IsTexFail 
)
static

Definition at line 1731 of file AMDGPUInstructionSelector.cpp.

References x2().

◆ shouldUseAndMask()

static bool shouldUseAndMask ( unsigned  Size,
unsigned &  Mask 
)
static
Returns
true if a bitmask for Size bits will be an inline immediate.

Definition at line 2265 of file AMDGPUInstructionSelector.cpp.

References llvm::BitmaskEnumDetail::Mask().

◆ sizeToSubRegIndex()

static int sizeToSubRegIndex ( unsigned  Size)
static

Definition at line 2123 of file AMDGPUInstructionSelector.cpp.

References llvm::PowerOf2Ceil().

◆ stripBitCast()

static MachineInstr* stripBitCast ( MachineInstr MI,
MachineRegisterInfo MRI 
)
static

Definition at line 4885 of file AMDGPUInstructionSelector.cpp.

References llvm::getDefIgnoringCopies(), MI, and MRI.

Referenced by isExtractHiElt().

Variable Documentation

◆ AllowRiskySelect

cl::opt<bool> AllowRiskySelect("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden)
static