#include "AMDGPUInstructionSelector.h"
#include "AMDGPU.h"
#include "AMDGPUGlobalISelUtils.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPURegisterBankInfo.h"
#include "AMDGPUTargetMachine.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "AMDGPUGenGlobalISel.inc"

Include dependency graph for AMDGPUInstructionSelector.cpp:

Macros
#define	DEBUG_TYPE "amdgpu-isel"

#define	GET_GLOBALISEL_IMPL

#define	AMDGPUSubtarget GCNSubtarget

#define	GET_GLOBALISEL_PREDICATES_INIT

#define	GET_GLOBALISEL_TEMPORARIES_INIT

Functions
static unsigned	getLogicalBitOpcode (unsigned Opc, bool Is64)

static int	getV_CMPOpcode (CmpInst::Predicate P, unsigned Size)

static unsigned	gwsIntrinToOpcode (unsigned IntrID)

static bool	parseTexFail (uint64_t TexFailCtrl, bool &TFE, bool &LWE, bool &IsTexFail)

static int	sizeToSubRegIndex (unsigned Size)

static bool	shouldUseAndMask (unsigned Size, unsigned &Mask)

static bool	isConstant (const MachineInstr &MI)

static bool	isVCmpResult (Register Reg, MachineRegisterInfo &MRI)

static std::pair< Register, unsigned >	computeIndirectRegIndex (MachineRegisterInfo &MRI, const SIRegisterInfo &TRI, const TargetRegisterClass *SuperRC, Register IdxReg, unsigned EltSize)
	Return the register to use for the index value, and the subregister to use for the indirectly accessed register. More...

static bool	isZeroOrUndef (int X)

static bool	isOneOrUndef (int X)

static bool	isZeroOrOneOrUndef (int X)

static Register	normalizeVOP3PMask (int NewMask[2], Register Src0, Register Src1, ArrayRef< int > Mask)

static Register	matchZeroExtendFromS32 (MachineRegisterInfo &MRI, Register Reg)
	Match a zero extend from a 32-bit value to 64-bits. More...

static void	addZeroImm (MachineInstrBuilder &MIB)

static Register	buildRSRC (MachineIRBuilder &B, MachineRegisterInfo &MRI, uint32_t FormatLo, uint32_t FormatHi, Register BasePtr)
	Return a resource descriptor for use with an arbitrary 64-bit pointer. More...

static Register	buildAddr64RSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)

static Register	buildOffsetSrc (MachineIRBuilder &B, MachineRegisterInfo &MRI, const SIInstrInfo &TII, Register BasePtr)

static Optional< uint64_t >	getConstantZext32Val (Register Reg, const MachineRegisterInfo &MRI)
	Get an immediate that must be 32-bits, and treated as zero extended. More...

Variables
static cl::opt< bool >	AllowRiskySelect ("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden)

Detailed Description

This file implements the targeting of the InstructionSelector class for AMDGPU.

Todo:: This should be generated by TableGen.

Definition in file AMDGPUInstructionSelector.cpp.

Macro Definition Documentation

◆ AMDGPUSubtarget

#define AMDGPUSubtarget GCNSubtarget

Definition at line 41 of file AMDGPUInstructionSelector.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "amdgpu-isel"

Definition at line 29 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 40 of file AMDGPUInstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ addZeroImm()

static void addZeroImm ( MachineInstrBuilder & MIB )

static

Definition at line 4048 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm().

◆ buildAddr64RSrc()

static Register buildAddr64RSrc	(	MachineIRBuilder &	B,
		MachineRegisterInfo &	MRI,
		const SIInstrInfo &	TII,
		Register	BasePtr
	)

static

Definition at line 4097 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildOffsetSrc()

static Register buildOffsetSrc	(	MachineIRBuilder &	B,
		MachineRegisterInfo &	MRI,
		const SIInstrInfo &	TII,
		Register	BasePtr
	)

static

Definition at line 4106 of file AMDGPUInstructionSelector.cpp.

References B, buildRSRC(), llvm::Hi_32(), MRI, and TII.

◆ buildRSRC()

static Register buildRSRC	(	MachineIRBuilder &	B,
		MachineRegisterInfo &	MRI,
		uint32_t	FormatLo,
		uint32_t	FormatHi,
		Register	BasePtr
	)

static

Return a resource descriptor for use with an arbitrary 64-bit pointer.

If BasePtr is not valid, a null base pointer will be used.

Definition at line 4054 of file AMDGPUInstructionSelector.cpp.

References B, llvm::MachineRegisterInfo::createVirtualRegister(), and MRI.

Referenced by buildAddr64RSrc(), and buildOffsetSrc().

◆ computeIndirectRegIndex()

static std::pair<Register, unsigned> computeIndirectRegIndex	(	MachineRegisterInfo &	MRI,
		const SIRegisterInfo &	TRI,
		const TargetRegisterClass *	SuperRC,
		Register	IdxReg,
		unsigned	EltSize
	)

static

Return the register to use for the index value, and the subregister to use for the indirectly accessed register.

Definition at line 2638 of file AMDGPUInstructionSelector.cpp.

References assert(), llvm::AMDGPU::getBaseWithConstantOffset(), MRI, Offset, llvm::ArrayRef< T >::size(), and TRI.

◆ getConstantZext32Val()

static Optional<uint64_t> getConstantZext32Val	(	Register	Reg,
		const MachineRegisterInfo &	MRI
	)

static

Get an immediate that must be 32-bits, and treated as zero extended.

Definition at line 4368 of file AMDGPUInstructionSelector.cpp.

References llvm::getIConstantVRegSExtVal(), llvm::isInt< 32 >(), llvm::Lo_32(), MRI, llvm::None, and Reg.

◆ getLogicalBitOpcode()

static unsigned getLogicalBitOpcode	(	unsigned	Opc,
		bool	Is64
	)

static

Definition at line 266 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ getV_CMPOpcode()

static int getV_CMPOpcode	(	CmpInst::Predicate	P,
		unsigned	Size
	)

static

Definition at line 978 of file AMDGPUInstructionSelector.cpp.

References llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::CmpInst::ICMP_SGE, llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, llvm::CmpInst::ICMP_SLT, llvm::CmpInst::ICMP_UGE, llvm::CmpInst::ICMP_UGT, llvm::CmpInst::ICMP_ULE, llvm::CmpInst::ICMP_ULT, llvm_unreachable, P, and llvm::Check::Size.

◆ gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned IntrID )

static

Definition at line 1320 of file AMDGPUInstructionSelector.cpp.

References llvm_unreachable.

◆ isConstant()

static bool isConstant ( const MachineInstr & MI )

static

Definition at line 2278 of file AMDGPUInstructionSelector.cpp.

References MI.

Referenced by llvm::buildModuleSummaryIndex(), llvm::MDBuilder::createTBAANode(), llvm::HexagonInstrInfo::expandPostRAPseudo(), and llvm::SCCPInstVisitor::isStructLatticeConstant().

◆ isOneOrUndef()

static bool isOneOrUndef ( int X )

static

Definition at line 2817 of file AMDGPUInstructionSelector.cpp.

References X.

◆ isVCmpResult()

static bool isVCmpResult	(	Register	Reg,
		MachineRegisterInfo &	MRI
	)

static

Definition at line 2435 of file AMDGPUInstructionSelector.cpp.

References llvm::MachineRegisterInfo::getUniqueVRegDef(), MI, MRI, and Reg.

◆ isZeroOrOneOrUndef()

static bool isZeroOrOneOrUndef ( int X )

static

Definition at line 2821 of file AMDGPUInstructionSelector.cpp.

References X.

Referenced by normalizeVOP3PMask().

◆ isZeroOrUndef()

static bool isZeroOrUndef ( int X )

static

Definition at line 2813 of file AMDGPUInstructionSelector.cpp.

References X.

◆ matchZeroExtendFromS32()

static Register matchZeroExtendFromS32	(	MachineRegisterInfo &	MRI,
		Register	Reg
	)

static

Match a zero extend from a 32-bit value to 64-bits.

Definition at line 3587 of file AMDGPUInstructionSelector.cpp.

References llvm::tgtok::Def, llvm::getDefIgnoringCopies(), llvm::MachineRegisterInfo::getType(), llvm::MIPatternMatch::m_GZExt(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::m_ZeroInt(), llvm::MIPatternMatch::mi_match(), MRI, Reg, and llvm::LLT::scalar().

◆ normalizeVOP3PMask()

static Register normalizeVOP3PMask	(	int	NewMask[2],
		Register	Src0,
		Register	Src1,
		ArrayRef< int >	Mask
	)

static

Definition at line 2827 of file AMDGPUInstructionSelector.cpp.

References assert(), isZeroOrOneOrUndef(), and llvm::BitmaskEnumDetail::Mask().

◆ parseTexFail()

static bool parseTexFail	(	uint64_t	TexFailCtrl,
		bool &	TFE,
		bool &	LWE,
		bool &	IsTexFail
	)

static

Definition at line 1491 of file AMDGPUInstructionSelector.cpp.

References x2().

◆ shouldUseAndMask()

static bool shouldUseAndMask	(	unsigned	Size,
		unsigned &	Mask
	)

static

Returns: true if a bitmask for Size bits will be an inline immediate.

Definition at line 1961 of file AMDGPUInstructionSelector.cpp.

References llvm::BitmaskEnumDetail::Mask(), and llvm::Check::Size.

◆ sizeToSubRegIndex()

static int sizeToSubRegIndex ( unsigned Size )

static

Definition at line 1819 of file AMDGPUInstructionSelector.cpp.

References llvm::PowerOf2Ceil(), and llvm::Check::Size.

Variable Documentation

◆ AllowRiskySelect

cl::opt<bool> AllowRiskySelect("amdgpu-global-isel-risky-select", cl::desc("Allow GlobalISel to select cases that are likely to not work yet"), cl::init(false), cl::ReallyHidden)

static

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ AMDGPUSubtarget

◆ DEBUG_TYPE

◆ GET_GLOBALISEL_IMPL

◆ GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ addZeroImm()

◆ buildAddr64RSrc()

◆ buildOffsetSrc()

◆ buildRSRC()

◆ computeIndirectRegIndex()

◆ getConstantZext32Val()

◆ getLogicalBitOpcode()

◆ getV_CMPOpcode()

◆ gwsIntrinToOpcode()

◆ isConstant()

◆ isOneOrUndef()

◆ isVCmpResult()

◆ isZeroOrOneOrUndef()

◆ isZeroOrUndef()

◆ matchZeroExtendFromS32()

◆ normalizeVOP3PMask()

◆ parseTexFail()

◆ shouldUseAndMask()

◆ sizeToSubRegIndex()

Variable Documentation

◆ AllowRiskySelect