LLVM  15.0.0git
AMDGPULegalizerInfo.h
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32  const GCNSubtarget &ST;
33 
34 public:
36  const GCNTargetMachine &TM);
37 
38  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40  Register getSegmentAperture(unsigned AddrSpace,
42  MachineIRBuilder &B) const;
43 
45  MachineIRBuilder &B) const;
47  MachineIRBuilder &B) const;
49  MachineIRBuilder &B) const;
51  MachineIRBuilder &B) const;
53  MachineIRBuilder &B) const;
55  MachineIRBuilder &B, bool Signed) const;
57  MachineIRBuilder &B, bool Signed) const;
60  MachineIRBuilder &B) const;
62  MachineIRBuilder &B) const;
64  MachineIRBuilder &B) const;
65 
67  MachineIRBuilder &B) const;
68 
70  const GlobalValue *GV, int64_t Offset,
71  unsigned GAFlags = SIInstrInfo::MO_NONE) const;
72 
74  MachineIRBuilder &B) const;
75  bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
76 
78  MachineIRBuilder &B) const;
79 
81  MachineIRBuilder &B) const;
83  double Log2BaseInverted) const;
87  MachineIRBuilder &B) const;
88 
90  MachineIRBuilder &B) const;
92  MachineIRBuilder &B) const;
93 
95  const ArgDescriptor *Arg,
96  const TargetRegisterClass *ArgRC, LLT ArgTy) const;
99 
105  unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
106 
107  Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const;
109  uint64_t Offset,
110  Align Alignment = Align(4)) const;
111 
113  MachineIRBuilder &B) const;
114 
116  Register DstRemReg, Register Num,
117  Register Den) const;
118 
120  Register DstRemReg, Register Num,
121  Register Den) const;
122 
124  MachineIRBuilder &B) const;
125 
127  MachineIRBuilder &B) const;
129  MachineIRBuilder &B) const;
131  MachineIRBuilder &B) const;
133  MachineIRBuilder &B) const;
135  MachineIRBuilder &B) const;
137  MachineIRBuilder &B) const;
139  MachineIRBuilder &B) const;
140 
142  MachineIRBuilder &B) const;
143 
145  MachineInstr &MI, Intrinsic::ID IID) const;
146 
148  MachineIRBuilder &B) const;
149 
151  MachineIRBuilder &B) const;
153  MachineIRBuilder &B, unsigned AddrSpace) const;
154 
155  std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
156  Register OrigOffset) const;
157  void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
158  Register SOffset, unsigned ImmOffset, Register VIndex,
159  MachineRegisterInfo &MRI) const;
160 
162  Register Reg, bool ImageStore = false) const;
164  MachineIRBuilder &B, bool IsFormat) const;
166  MachineIRBuilder &B, bool IsFormat) const;
168  bool IsFormat) const;
169 
171  MachineIRBuilder &B, bool IsTyped,
172  bool IsFormat) const;
174  MachineIRBuilder &B, bool IsFormat,
175  bool IsTyped) const;
177  Intrinsic::ID IID) const;
178 
180 
182 
185  GISelChangeObserver &Observer,
186  const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
187 
188  bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
189 
191  bool IsInc) const;
192 
194  MachineIRBuilder &B) const;
196  MachineIRBuilder &B) const;
198  MachineIRBuilder &B) const;
200  MachineIRBuilder &B) const;
202  MachineIRBuilder &B) const;
203 
204  bool legalizeIntrinsic(LegalizerHelper &Helper,
205  MachineInstr &MI) const override;
206 };
207 } // End llvm namespace.
208 #endif
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic
bool legalizeWorkitemIDIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:3014
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4635
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3850
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
Definition: AMDGPULegalizerInfo.cpp:3867
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPULegalizerInfo::loadInputValue
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
Definition: AMDGPULegalizerInfo.cpp:2936
llvm::AMDGPULegalizerInfo::legalizeShuffleVector
bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2367
llvm::AMDGPULegalizerInfo::splitBufferOffsets
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const
Definition: AMDGPULegalizerInfo.cpp:3887
llvm::AMDGPULegalizerInfo::legalizeFrem
bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2063
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2325
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::AMDGPULegalizerInfo::legalizeSBufferLoad
bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:4850
llvm::AMDGPULegalizerInfo::legalizeLoad
bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2584
llvm::SPIRV::Dim
Dim
Definition: SPIRVBaseInfo.h:279
llvm::AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4998
llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2688
llvm::LegalizerHelper
Definition: LegalizerHelper.h:46
LegalizerInfo.h
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:31
llvm::AMDGPULegalizerInfo::legalizeFlog
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
Definition: AMDGPULegalizerInfo.cpp:2713
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl
void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3195
llvm::AMDGPULegalizerInfo::legalizeFPTOI
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2205
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::AMDGPULegalizerInfo::legalizeFDIV
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3090
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:156
llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2097
llvm::AMDGPULegalizerInfo::legalizeFExp
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2728
llvm::AMDGPULegalizerInfo::legalizeFceil
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2034
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AMDGPULegalizerInfo::legalizeFDIV16
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3501
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic
bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5019
llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:2997
llvm::AMDGPULegalizerInfo::fixStoreSourceType
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4020
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4901
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPULegalizerInfo::legalizeGlobalValue
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2475
llvm::AMDGPULegalizerInfo::legalizeFPTruncRound
bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5122
llvm::AMDGPULegalizerInfo::legalizeAtomicIncDec
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
Definition: AMDGPULegalizerInfo.cpp:4248
llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3716
llvm::AMDGPULegalizerInfo::getImplicitArgPtr
bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3831
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AMDGPULegalizerInfo::handleD16VData
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
Handle register layout difference for f16 images for some subtargets.
Definition: AMDGPULegalizerInfo.cpp:3957
llvm::AMDGPULegalizerInfo::legalizeTrapHsa
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4990
llvm::AMDGPULegalizerInfo::legalizeBufferStore
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4043
SIInstrInfo.h
llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic
bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:3813
llvm::AMDGPULegalizerInfo::getKernargParameterPtr
Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const
Definition: AMDGPULegalizerInfo.cpp:3054
llvm::AMDGPULegalizerInfo::legalizeFPow
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2742
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:73
llvm::AMDGPULegalizerInfo::legalizeFrint
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2008
llvm::AMDGPULegalizerInfo::legalizeFDIV64
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3635
llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2291
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::AMDGPULegalizerInfo::legalizeTrapEndpgm
bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4924
llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
Definition: AMDGPULegalizerInfo.cpp:2415
llvm::AMDGPULegalizerInfo::legalizeIntrinsic
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
Definition: AMDGPULegalizerInfo.cpp:5143
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPULegalizerInfo::legalizeITOFP
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2142
llvm::AMDGPULegalizerInfo::legalizeKernargMemParameter
bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, uint64_t Offset, Align Alignment=Align(4)) const
Legalize a value that's loaded from kernel arguments.
Definition: AMDGPULegalizerInfo.cpp:3072
llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM
bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3347
llvm::AMDGPULegalizerInfo::legalizeBufferAtomic
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:4317
llvm::AMDGPULegalizerInfo::getSegmentAperture
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1778
llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr
bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4931
llvm::AMDGPULegalizerInfo::legalizeRawBufferLoad
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic
bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3757
llvm::AMDGPULegalizerInfo::legalizeFFloor
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2789
llvm::AMDGPULegalizerInfo::legalizeCTLZ_CTTZ
bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2867
llvm::AMDGPULegalizerInfo::legalizeFMad
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2666
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3415
llvm::AMDGPULegalizerInfo::legalizeBufferLoad
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat, bool IsTyped) const
Definition: AMDGPULegalizerInfo.cpp:4130
llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1888
llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
Definition: AMDGPULegalizerInfo.cpp:426
llvm::AMDGPULegalizerInfo::legalizeBuildVector
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2847
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM
bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3307
llvm::AMDGPULegalizerInfo::legalizeRawBufferStore
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64
bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3464
llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic
bool legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
Rewrite image intrinsics to use register layouts expected by the subtarget.
Definition: AMDGPULegalizerInfo.cpp:4499
llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2272
llvm::AMDGPULegalizerInfo::legalizeFDIV32
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3566
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl
void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3109
llvm::AMDGPULegalizerInfo::legalizeCustom
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
Definition: AMDGPULegalizerInfo.cpp:1696
AMDGPUArgumentUsageInfo.h
llvm::AMDGPULegalizerInfo::legalizeSinCos
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2387
llvm::AMDGPULegalizerInfo::updateBufferMMO
void updateBufferMMO(MachineMemOperand *MMO, Register VOffset, Register SOffset, unsigned ImmOffset, Register VIndex, MachineRegisterInfo &MRI) const
Update MMO based on the offset inputs to a raw/struct buffer intrinsic.
Definition: AMDGPULegalizerInfo.cpp:3932
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::LLT
Definition: LowLevelTypeImpl.h:39