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AMDGPULegalizerInfo.h
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32  const GCNSubtarget &ST;
33 
34 public:
36  const GCNTargetMachine &TM);
37 
38  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40  Register getSegmentAperture(unsigned AddrSpace,
42  MachineIRBuilder &B) const;
43 
45  MachineIRBuilder &B) const;
47  MachineIRBuilder &B) const;
49  MachineIRBuilder &B) const;
51  MachineIRBuilder &B) const;
53  MachineIRBuilder &B) const;
55  MachineIRBuilder &B, bool Signed) const;
57  MachineIRBuilder &B, bool Signed) const;
60  MachineIRBuilder &B) const;
62  MachineIRBuilder &B) const;
63 
65  MachineIRBuilder &B) const;
66 
68  const GlobalValue *GV, int64_t Offset,
69  unsigned GAFlags = SIInstrInfo::MO_NONE) const;
70 
72  MachineIRBuilder &B) const;
73  bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
74 
76  MachineIRBuilder &B) const;
77 
79  MachineIRBuilder &B) const;
81  double Log2BaseInverted) const;
85  MachineIRBuilder &B) const;
86 
88  MachineIRBuilder &B) const;
89 
92  bool UsePartialMad64_32,
93  bool SeparateOddAlignedProducts) const;
94  bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const;
96  MachineIRBuilder &B) const;
97 
99  const ArgDescriptor *Arg,
100  const TargetRegisterClass *ArgRC, LLT ArgTy) const;
103 
109  unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
110 
111  Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const;
113  uint64_t Offset,
114  Align Alignment = Align(4)) const;
115 
117  MachineIRBuilder &B) const;
118 
120  Register DstRemReg, Register Num,
121  Register Den) const;
122 
124  Register DstRemReg, Register Num,
125  Register Den) const;
126 
128  MachineIRBuilder &B) const;
129 
131  MachineIRBuilder &B) const;
133  MachineIRBuilder &B) const;
135  MachineIRBuilder &B) const;
137  MachineIRBuilder &B) const;
139  MachineIRBuilder &B) const;
141  MachineIRBuilder &B) const;
143  MachineIRBuilder &B) const;
144 
146  MachineIRBuilder &B) const;
147 
149  MachineInstr &MI, Intrinsic::ID IID) const;
150 
152  MachineIRBuilder &B) const;
153 
155  MachineIRBuilder &B) const;
156 
158  MachineIRBuilder &B) const;
159 
161  MachineIRBuilder &B) const;
162 
164  MachineIRBuilder &B, unsigned AddrSpace) const;
165 
166  std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
167  Register OrigOffset) const;
168  void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
169  Register SOffset, unsigned ImmOffset, Register VIndex,
170  MachineRegisterInfo &MRI) const;
171 
173  Register Reg, bool ImageStore = false) const;
175  MachineIRBuilder &B, bool IsFormat) const;
177  MachineIRBuilder &B, bool IsFormat) const;
179  bool IsFormat) const;
180 
182  MachineIRBuilder &B, bool IsTyped,
183  bool IsFormat) const;
185  MachineIRBuilder &B, bool IsFormat,
186  bool IsTyped) const;
188  Intrinsic::ID IID) const;
189 
191 
193 
196  GISelChangeObserver &Observer,
197  const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
198 
199  bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
200 
202  bool IsInc) const;
203 
205  MachineIRBuilder &B) const;
207  MachineIRBuilder &B) const;
209  MachineIRBuilder &B) const;
211  MachineIRBuilder &B) const;
213  MachineIRBuilder &B) const;
214 
215  bool legalizeIntrinsic(LegalizerHelper &Helper,
216  MachineInstr &MI) const override;
217 };
218 } // End llvm namespace.
219 #endif
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic
bool legalizeWorkitemIDIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:3324
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4160
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
Definition: AMDGPULegalizerInfo.cpp:4206
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPULegalizerInfo::loadInputValue
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
Definition: AMDGPULegalizerInfo.cpp:3246
llvm::AMDGPULegalizerInfo::splitBufferOffsets
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const
Definition: AMDGPULegalizerInfo.cpp:4226
llvm::AMDGPULegalizerInfo::legalizeFrem
bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2095
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2357
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::AMDGPULegalizerInfo::legalizeSBufferLoad
bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:5231
llvm::AMDGPULegalizerInfo::legalizeLoad
bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2596
llvm::AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5379
llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2700
llvm::LegalizerHelper
Definition: LegalizerHelper.h:46
LegalizerInfo.h
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:31
llvm::AMDGPULegalizerInfo::legalizeFlog
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
Definition: AMDGPULegalizerInfo.cpp:2725
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl
void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3505
llvm::AMDGPULegalizerInfo::legalizeFPTOI
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2237
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::AMDGPULegalizerInfo::legalizeFDIV
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3400
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:157
llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2129
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
llvm::AMDGPULegalizerInfo::legalizeFExp
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2740
llvm::AMDGPULegalizerInfo::legalizeFceil
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2066
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AMDGPULegalizerInfo::legalizeFDIV16
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3811
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic
bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5400
llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:3307
llvm::AMDGPULegalizerInfo::fixStoreSourceType
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4359
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5282
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPULegalizerInfo::legalizeGlobalValue
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2487
llvm::AMDGPULegalizerInfo::legalizeFPTruncRound
bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5542
llvm::AMDGPULegalizerInfo::legalizeAtomicIncDec
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
Definition: AMDGPULegalizerInfo.cpp:4622
llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4026
llvm::AMDGPULegalizerInfo::getImplicitArgPtr
bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4141
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AMDGPULegalizerInfo::handleD16VData
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
Handle register layout difference for f16 images for some subtargets.
Definition: AMDGPULegalizerInfo.cpp:4296
llvm::AMDGPULegalizerInfo::legalizeTrapHsa
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5371
llvm::AMDGPULegalizerInfo::legalizeBufferStore
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4382
SIInstrInfo.h
llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic
bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:4123
llvm::AMDGPULegalizerInfo::getKernargParameterPtr
Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const
Definition: AMDGPULegalizerInfo.cpp:3364
llvm::AMDGPULegalizerInfo::legalizeFPow
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2754
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:74
llvm::AMDGPULegalizerInfo::legalizeFrint
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2040
llvm::AMDGPULegalizerInfo::legalizeMul
bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:3125
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AMDGPULegalizerInfo::buildMultiply
void buildMultiply(LegalizerHelper &Helper, MutableArrayRef< Register > Accum, ArrayRef< Register > Src0, ArrayRef< Register > Src1, bool UsePartialMad64_32, bool SeparateOddAlignedProducts) const
Definition: AMDGPULegalizerInfo.cpp:2891
llvm::AMDGPULegalizerInfo::legalizeFDIV64
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3945
llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2323
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::AMDGPULegalizerInfo::legalizeTrapEndpgm
bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5305
llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
Definition: AMDGPULegalizerInfo.cpp:2427
llvm::AMDGPULegalizerInfo::legalizeIntrinsic
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
Definition: AMDGPULegalizerInfo.cpp:5563
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPULegalizerInfo::legalizeITOFP
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2174
llvm::AMDGPULegalizerInfo::legalizeKernargMemParameter
bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, uint64_t Offset, Align Alignment=Align(4)) const
Legalize a value that's loaded from kernel arguments.
Definition: AMDGPULegalizerInfo.cpp:3382
llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM
bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3657
llvm::AMDGPULegalizerInfo::legalizeBufferAtomic
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:4691
llvm::AMDGPULegalizerInfo::getSegmentAperture
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1814
llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr
bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5312
llvm::AMDGPULegalizerInfo::legalizeRawBufferLoad
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::getLDSKernelId
bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4177
llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic
bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4067
llvm::AMDGPULegalizerInfo::legalizeFFloor
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2801
llvm::AMDGPULegalizerInfo::legalizeCTLZ_CTTZ
bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3177
llvm::AMDGPULegalizerInfo::legalizeFMad
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2678
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3725
llvm::AMDGPULegalizerInfo::legalizeBufferLoad
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat, bool IsTyped) const
Definition: AMDGPULegalizerInfo.cpp:4490
llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1920
llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
Definition: AMDGPULegalizerInfo.cpp:426
llvm::AMDGPULegalizerInfo::legalizeBuildVector
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2859
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM
bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3617
llvm::AMDGPULegalizerInfo::legalizeRawBufferStore
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64
bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3774
llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic
bool legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
Rewrite image intrinsics to use register layouts expected by the subtarget.
Definition: AMDGPULegalizerInfo.cpp:4873
llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2304
llvm::AMDGPULegalizerInfo::legalizeFDIV32
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3876
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1182
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl
void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3419
llvm::AMDGPULegalizerInfo::legalizeCustom
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
Definition: AMDGPULegalizerInfo.cpp:1731
AMDGPUArgumentUsageInfo.h
llvm::AMDGPULegalizerInfo::legalizeSinCos
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2399
llvm::AMDGPULegalizerInfo::updateBufferMMO
void updateBufferMMO(MachineMemOperand *MMO, Register VOffset, Register SOffset, unsigned ImmOffset, Register VIndex, MachineRegisterInfo &MRI) const
Update MMO based on the offset inputs to a raw/struct buffer intrinsic.
Definition: AMDGPULegalizerInfo.cpp:4271
llvm::AMDGPULegalizerInfo::legalizeLDSKernelId
bool legalizeLDSKernelId(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4188
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
llvm::LLT
Definition: LowLevelTypeImpl.h:39