LLVM  13.0.0git
AMDGPULegalizerInfo.h
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class LLVMContext;
25 class GCNSubtarget;
26 class MachineIRBuilder;
27 
28 namespace AMDGPU {
29 struct ImageDimIntrinsicInfo;
30 }
31 /// This class provides the information for the target register banks.
32 class AMDGPULegalizerInfo final : public LegalizerInfo {
33  const GCNSubtarget &ST;
34 
35 public:
37  const GCNTargetMachine &TM);
38 
39  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
40 
41  Register getSegmentAperture(unsigned AddrSpace,
43  MachineIRBuilder &B) const;
44 
46  MachineIRBuilder &B) const;
48  MachineIRBuilder &B) const;
50  MachineIRBuilder &B) const;
52  MachineIRBuilder &B) const;
54  MachineIRBuilder &B) const;
56  MachineIRBuilder &B, bool Signed) const;
58  MachineIRBuilder &B, bool Signed) const;
61  MachineIRBuilder &B) const;
63  MachineIRBuilder &B) const;
65  MachineIRBuilder &B) const;
66 
68  MachineIRBuilder &B) const;
69 
71  const GlobalValue *GV, int64_t Offset,
72  unsigned GAFlags = SIInstrInfo::MO_NONE) const;
73 
75  MachineIRBuilder &B) const;
76  bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
77 
79  MachineIRBuilder &B) const;
80 
82  MachineIRBuilder &B) const;
84  double Log2BaseInverted) const;
88  MachineIRBuilder &B) const;
89 
91  MachineIRBuilder &B) const;
92 
94  const ArgDescriptor *Arg,
95  const TargetRegisterClass *ArgRC, LLT ArgTy) const;
101 
103  MachineIRBuilder &B) const;
104 
106  Register DstReg, Register Num, Register Den,
107  bool IsRem) const;
108 
110  Register DstReg, Register Numer, Register Denom,
111  bool IsDiv) const;
112 
114  MachineIRBuilder &B) const;
116  MachineIRBuilder &B) const;
117 
119  MachineIRBuilder &B) const;
121  MachineIRBuilder &B) const;
123  MachineIRBuilder &B) const;
125  MachineIRBuilder &B) const;
127  MachineIRBuilder &B) const;
129  MachineIRBuilder &B) const;
131  MachineIRBuilder &B) const;
132 
134  MachineIRBuilder &B) const;
135 
137  MachineInstr &MI, Intrinsic::ID IID) const;
138 
140  MachineIRBuilder &B) const;
141 
143  MachineIRBuilder &B) const;
145  MachineIRBuilder &B, unsigned AddrSpace) const;
146 
147  std::tuple<Register, unsigned, unsigned>
148  splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
149 
151  Register Reg, bool ImageStore = false) const;
153  MachineIRBuilder &B, bool IsFormat) const;
155  MachineIRBuilder &B, bool IsFormat) const;
157  bool IsFormat) const;
158 
160  MachineIRBuilder &B, bool IsTyped,
161  bool IsFormat) const;
163  MachineIRBuilder &B, bool IsFormat,
164  bool IsTyped) const;
166  Intrinsic::ID IID) const;
167 
169 
172  GISelChangeObserver &Observer,
173  const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
174 
175  bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
176 
178  bool IsInc) const;
179 
181  MachineIRBuilder &B) const;
183  MachineIRBuilder &B) const;
185  MachineIRBuilder &B) const;
187  MachineIRBuilder &B) const;
189  MachineIRBuilder &B) const;
190 
191  bool legalizeIntrinsic(LegalizerHelper &Helper,
192  MachineInstr &MI) const override;
193 };
194 } // End llvm namespace.
195 #endif
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4544
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3494
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::AMDGPULegalizerInfo::legalizeUDIV_UREM64
bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
Definition: AMDGPULegalizerInfo.cpp:3511
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:50
llvm::AMDGPULegalizerInfo::loadInputValue
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
Definition: AMDGPULegalizerInfo.cpp:2719
llvm::AMDGPULegalizerInfo::legalizeShuffleVector
bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2169
llvm::AMDGPULegalizerInfo::legalizeSDIV_SREM
bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3014
llvm::AMDGPULegalizerInfo::legalizeFrem
bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1940
llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2136
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl
void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, Register DstReg, Register Num, Register Den, bool IsRem) const
Definition: AMDGPULegalizerInfo.cpp:2793
llvm::AMDGPULegalizerInfo::legalizeSBufferLoad
bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:4479
llvm::AMDGPULegalizerInfo::legalizeLoad
bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2390
llvm::AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4586
llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2492
llvm::LegalizerHelper
Definition: LegalizerHelper.h:37
LegalizerInfo.h
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:32
llvm::AMDGPULegalizerInfo::legalizeFlog
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
Definition: AMDGPULegalizerInfo.cpp:2517
llvm::AMDGPULegalizerInfo::legalizeFPTOI
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2052
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::AMDGPULegalizerInfo::legalizeFDIV
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2774
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:150
llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1974
llvm::AMDGPULegalizerInfo::legalizeFExp
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2532
llvm::AMDGPULegalizerInfo::legalizeFceil
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1912
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AMDGPULegalizerInfo::legalizeFDIV16
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3145
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::AMDGPULegalizerInfo::legalizeUDIV_UREM
bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2991
llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic
bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4607
llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:2764
llvm::AMDGPULegalizerInfo::fixStoreSourceType
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:3634
llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4530
llvm::AMDGPULegalizerInfo::legalizeGlobalValue
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2277
llvm::AMDGPULegalizerInfo::legalizeAtomicIncDec
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
Definition: AMDGPULegalizerInfo.cpp:3867
llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3360
llvm::AMDGPULegalizerInfo::getImplicitArgPtr
bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3475
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::AMDGPULegalizerInfo::splitBufferOffsets
std::tuple< Register, unsigned, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const
Definition: AMDGPULegalizerInfo.cpp:3531
llvm::AMDGPULegalizerInfo::legalizeUDIV_UREM64Impl
void legalizeUDIV_UREM64Impl(MachineIRBuilder &B, Register DstReg, Register Numer, Register Denom, bool IsDiv) const
Definition: AMDGPULegalizerInfo.cpp:2878
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::AMDGPULegalizerInfo::handleD16VData
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
Handle register layout difference for f16 images for some subtargets.
Definition: AMDGPULegalizerInfo.cpp:3578
llvm::AMDGPULegalizerInfo::legalizeTrapHsa
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4578
llvm::AMDGPULegalizerInfo::legalizeBufferStore
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:3657
SIInstrInfo.h
llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic
bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:3457
llvm::AMDGPULegalizerInfo::legalizeFPow
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2546
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:95
llvm::AMDGPULegalizerInfo::legalizeFrint
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1886
llvm::AMDGPULegalizerInfo::legalizeFDIV64
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3279
llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2104
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::AMDGPULegalizerInfo::legalizeTrapEndpgm
bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4552
llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
Definition: AMDGPULegalizerInfo.cpp:2217
llvm::AMDGPULegalizerInfo::legalizeIntrinsic
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
Definition: AMDGPULegalizerInfo.cpp:4679
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPULegalizerInfo::legalizeITOFP
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2019
llvm::AMDGPULegalizerInfo::legalizeBufferAtomic
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:3937
llvm::AMDGPULegalizerInfo::getSegmentAperture
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1731
llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr
bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4559
llvm::AMDGPULegalizerInfo::legalizeRawBufferLoad
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic
bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3401
llvm::AMDGPULegalizerInfo::legalizeFFloor
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2593
llvm::AMDGPULegalizerInfo::legalizeFMad
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2470
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3059
llvm::AMDGPULegalizerInfo::legalizeBufferLoad
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat, bool IsTyped) const
Definition: AMDGPULegalizerInfo.cpp:3747
llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1790
llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
Definition: AMDGPULegalizerInfo.cpp:413
llvm::AMDGPULegalizerInfo::legalizeBuildVector
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2651
llvm::AMDGPULegalizerInfo::legalizeRawBufferStore
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64
bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3108
llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic
bool legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
Rewrite image intrinsics to use register layouts expected by the subtarget.
Definition: AMDGPULegalizerInfo.cpp:4111
llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2085
llvm::AMDGPULegalizerInfo::legalizeFDIV32
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3210
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1058
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPULegalizerInfo::legalizeCustom
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
Definition: AMDGPULegalizerInfo.cpp:1658
AMDGPUArgumentUsageInfo.h
llvm::AMDGPULegalizerInfo::legalizeSinCos
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2189
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40