LLVM  13.0.0git
Public Member Functions | List of all members
llvm::AMDGPULegalizerInfo Class Referencefinal

This class provides the information for the target register banks. More...

#include "Target/AMDGPU/AMDGPULegalizerInfo.h"

Inheritance diagram for llvm::AMDGPULegalizerInfo:
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Collaboration diagram for llvm::AMDGPULegalizerInfo:
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Public Member Functions

 AMDGPULegalizerInfo (const GCNSubtarget &ST, const GCNTargetMachine &TM)
 
bool legalizeCustom (LegalizerHelper &Helper, MachineInstr &MI) const override
 Called for instructions with the Custom LegalizationAction. More...
 
Register getSegmentAperture (unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeAddrSpaceCast (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFrint (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFceil (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFrem (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeIntrinsicTrunc (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeITOFP (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
 
bool legalizeFPTOI (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
 
bool legalizeMinNumMaxNum (LegalizerHelper &Helper, MachineInstr &MI) const
 
bool legalizeExtractVectorElt (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeInsertVectorElt (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeShuffleVector (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeSinCos (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool buildPCRelGlobalAddress (Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
 
bool legalizeGlobalValue (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeLoad (LegalizerHelper &Helper, MachineInstr &MI) const
 
bool legalizeFMad (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeAtomicCmpXChg (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFlog (MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
 
bool legalizeFExp (MachineInstr &MI, MachineIRBuilder &B) const
 
bool legalizeFPow (MachineInstr &MI, MachineIRBuilder &B) const
 
bool legalizeFFloor (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeBuildVector (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool loadInputValue (Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
 
bool loadInputValue (Register DstReg, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
 
bool legalizePreloadedArgIntrin (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
 
bool legalizeUDIV_UREM (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
void legalizeUDIV_UREM32Impl (MachineIRBuilder &B, Register DstReg, Register Num, Register Den, bool IsRem) const
 
void legalizeUDIV_UREM64Impl (MachineIRBuilder &B, Register DstReg, Register Numer, Register Denom, bool IsDiv) const
 
bool legalizeUDIV_UREM64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeSDIV_SREM (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFDIV (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFDIV16 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFDIV32 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFDIV64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFastUnsafeFDIV (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFastUnsafeFDIV64 (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeFDIVFastIntrin (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeRsqClampIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeDSAtomicFPIntrinsic (LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
 
bool getImplicitArgPtr (Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeImplicitArgPtr (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeIsAddrSpace (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
 
std::tuple< Register, unsigned, unsigned > splitBufferOffsets (MachineIRBuilder &B, Register OrigOffset) const
 
Register handleD16VData (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
 Handle register layout difference for f16 images for some subtargets. More...
 
bool legalizeRawBufferStore (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
 
bool legalizeRawBufferLoad (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
 
Register fixStoreSourceType (MachineIRBuilder &B, Register VData, bool IsFormat) const
 
bool legalizeBufferStore (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
 
bool legalizeBufferLoad (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat, bool IsTyped) const
 
bool legalizeBufferAtomic (MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
 
bool legalizeBVHIntrinsic (MachineInstr &MI, MachineIRBuilder &B) const
 
bool legalizeImageIntrinsic (MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
 Rewrite image intrinsics to use register layouts expected by the subtarget. More...
 
bool legalizeSBufferLoad (LegalizerHelper &Helper, MachineInstr &MI) const
 
bool legalizeAtomicIncDec (MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
 
bool legalizeTrapIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeTrapEndpgm (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeTrapHsaQueuePtr (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeTrapHsa (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeDebugTrapIntrinsic (MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
 
bool legalizeIntrinsic (LegalizerHelper &Helper, MachineInstr &MI) const override
 
- Public Member Functions inherited from llvm::LegalizerInfo
 LegalizerInfo ()
 
virtual ~LegalizerInfo ()=default
 
unsigned getOpcodeIdxForOpcode (unsigned Opcode) const
 
unsigned getActionDefinitionsIdx (unsigned Opcode) const
 
void computeTables ()
 Compute any ancillary tables needed to quickly decide how an operation should be handled. More...
 
void verify (const MCInstrInfo &MII) const
 Perform simple self-diagnostic and assert if there is anything obviously wrong with the actions set up. More...
 
void setAction (const InstrAspect &Aspect, LegalizeAction Action)
 More friendly way to set an action for common types that have an LLT representation. More...
 
void setLegalizeScalarToDifferentSizeStrategy (const unsigned Opcode, const unsigned TypeIdx, SizeChangeStrategy S)
 The setAction calls record the non-size-changing legalization actions to take on specificly-sized types. More...
 
void setLegalizeVectorElementToDifferentSizeStrategy (const unsigned Opcode, const unsigned TypeIdx, SizeChangeStrategy S)
 See also setLegalizeScalarToDifferentSizeStrategy. More...
 
const LegalizeRuleSetgetActionDefinitions (unsigned Opcode) const
 Get the action definitions for the given opcode. More...
 
LegalizeRuleSetgetActionDefinitionsBuilder (unsigned Opcode)
 Get the action definition builder for the given opcode. More...
 
LegalizeRuleSetgetActionDefinitionsBuilder (std::initializer_list< unsigned > Opcodes)
 Get the action definition builder for the given set of opcodes. More...
 
void aliasActionDefinitions (unsigned OpcodeTo, unsigned OpcodeFrom)
 
LegalizeActionStep getAction (const LegalityQuery &Query) const
 Determine what action should be taken to legalize the described instruction. More...
 
LegalizeActionStep getAction (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 Determine what action should be taken to legalize the given generic instruction. More...
 
bool isLegal (const LegalityQuery &Query) const
 
bool isLegalOrCustom (const LegalityQuery &Query) const
 
bool isLegal (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
bool isLegalOrCustom (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
virtual unsigned getExtOpcodeForWideningConstant (LLT SmallTy) const
 Return the opcode (SEXT/ZEXT/ANYEXT) that should be performed while widening a constant of type SmallTy which targets can override. More...
 

Additional Inherited Members

- Public Types inherited from llvm::LegalizerInfo
using SizeAndAction = std::pair< uint16_t, LegalizeAction >
 
using SizeAndActionsVec = std::vector< SizeAndAction >
 
using SizeChangeStrategy = std::function< SizeAndActionsVec(const SizeAndActionsVec &v)>
 
- Static Public Member Functions inherited from llvm::LegalizerInfo
static bool needsLegalizingToDifferentSize (const LegalizeAction Action)
 
static SizeAndActionsVec unsupportedForDifferentSizes (const SizeAndActionsVec &v)
 A SizeChangeStrategy for the common case where legalization for a particular operation consists of only supporting a specific set of type sizes. More...
 
static SizeAndActionsVec widenToLargerTypesAndNarrowToLargest (const SizeAndActionsVec &v)
 A SizeChangeStrategy for the common case where legalization for a particular operation consists of widening the type to a large legal type, unless there is no such type and then instead it should be narrowed to the largest legal type. More...
 
static SizeAndActionsVec widenToLargerTypesUnsupportedOtherwise (const SizeAndActionsVec &v)
 
static SizeAndActionsVec narrowToSmallerAndUnsupportedIfTooSmall (const SizeAndActionsVec &v)
 
static SizeAndActionsVec narrowToSmallerAndWidenToSmallest (const SizeAndActionsVec &v)
 
static SizeAndActionsVec moreToWiderTypesAndLessToWidest (const SizeAndActionsVec &v)
 A SizeChangeStrategy for the common case where legalization for a particular vector operation consists of having more elements in the vector, to a type that is legal. More...
 
static SizeAndActionsVec increaseToLargerTypesAndDecreaseToLargest (const SizeAndActionsVec &v, LegalizeAction IncreaseAction, LegalizeAction DecreaseAction)
 Helper function to implement many typical SizeChangeStrategy functions. More...
 
static SizeAndActionsVec decreaseToSmallerTypesAndIncreaseToSmallest (const SizeAndActionsVec &v, LegalizeAction DecreaseAction, LegalizeAction IncreaseAction)
 Helper function to implement many typical SizeChangeStrategy functions. More...
 

Detailed Description

This class provides the information for the target register banks.

Definition at line 32 of file AMDGPULegalizerInfo.h.

Constructor & Destructor Documentation

◆ AMDGPULegalizerInfo()

AMDGPULegalizerInfo::AMDGPULegalizerInfo ( const GCNSubtarget ST,
const GCNTargetMachine TM 
)

Member Function Documentation

◆ buildPCRelGlobalAddress()

bool AMDGPULegalizerInfo::buildPCRelGlobalAddress ( Register  DstReg,
LLT  PtrTy,
MachineIRBuilder B,
const GlobalValue GV,
int64_t  Offset,
unsigned  GAFlags = SIInstrInfo::MO_NONE 
) const

◆ fixStoreSourceType()

Register AMDGPULegalizerInfo::fixStoreSourceType ( MachineIRBuilder B,
Register  VData,
bool  IsFormat 
) const

◆ getImplicitArgPtr()

bool AMDGPULegalizerInfo::getImplicitArgPtr ( Register  DstReg,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ getSegmentAperture()

Register AMDGPULegalizerInfo::getSegmentAperture ( unsigned  AddrSpace,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ handleD16VData()

Register AMDGPULegalizerInfo::handleD16VData ( MachineIRBuilder B,
MachineRegisterInfo MRI,
Register  Reg,
bool  ImageStore = false 
) const

◆ legalizeAddrSpaceCast()

bool AMDGPULegalizerInfo::legalizeAddrSpaceCast ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeAtomicCmpXChg()

bool AMDGPULegalizerInfo::legalizeAtomicCmpXChg ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeAtomicIncDec()

bool AMDGPULegalizerInfo::legalizeAtomicIncDec ( MachineInstr MI,
MachineIRBuilder B,
bool  IsInc 
) const

Definition at line 3867 of file AMDGPULegalizerInfo.cpp.

References B, and MI.

Referenced by legalizeIntrinsic().

◆ legalizeBufferAtomic()

bool AMDGPULegalizerInfo::legalizeBufferAtomic ( MachineInstr MI,
MachineIRBuilder B,
Intrinsic::ID  IID 
) const

◆ legalizeBufferLoad()

bool AMDGPULegalizerInfo::legalizeBufferLoad ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  IsFormat,
bool  IsTyped 
) const

◆ legalizeBufferStore()

bool AMDGPULegalizerInfo::legalizeBufferStore ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  IsTyped,
bool  IsFormat 
) const

◆ legalizeBuildVector()

bool AMDGPULegalizerInfo::legalizeBuildVector ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeBVHIntrinsic()

bool AMDGPULegalizerInfo::legalizeBVHIntrinsic ( MachineInstr MI,
MachineIRBuilder B 
) const

◆ legalizeCustom()

bool AMDGPULegalizerInfo::legalizeCustom ( LegalizerHelper Helper,
MachineInstr MI 
) const
overridevirtual

◆ legalizeDebugTrapIntrinsic()

bool AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeDSAtomicFPIntrinsic()

bool AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic ( LegalizerHelper Helper,
MachineInstr MI,
Intrinsic::ID  IID 
) const

◆ legalizeExtractVectorElt()

bool AMDGPULegalizerInfo::legalizeExtractVectorElt ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFastUnsafeFDIV()

bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFastUnsafeFDIV64()

bool AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64 ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFceil()

bool AMDGPULegalizerInfo::legalizeFceil ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFDIV()

bool AMDGPULegalizerInfo::legalizeFDIV ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFDIV16()

bool AMDGPULegalizerInfo::legalizeFDIV16 ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

Definition at line 3145 of file AMDGPULegalizerInfo.cpp.

References B, legalizeFastUnsafeFDIV(), MI, MRI, llvm::AMDGPUISD::RCP, and llvm::LLT::scalar().

Referenced by legalizeFDIV().

◆ legalizeFDIV32()

bool AMDGPULegalizerInfo::legalizeFDIV32 ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFDIV64()

bool AMDGPULegalizerInfo::legalizeFDIV64 ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFDIVFastIntrin()

bool AMDGPULegalizerInfo::legalizeFDIVFastIntrin ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFExp()

bool AMDGPULegalizerInfo::legalizeFExp ( MachineInstr MI,
MachineIRBuilder B 
) const

Definition at line 2532 of file AMDGPULegalizerInfo.cpp.

References B, llvm::numbers::log2e, MI, and llvm::Mul.

Referenced by legalizeCustom().

◆ legalizeFFloor()

bool AMDGPULegalizerInfo::legalizeFFloor ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFlog()

bool AMDGPULegalizerInfo::legalizeFlog ( MachineInstr MI,
MachineIRBuilder B,
double  Log2BaseInverted 
) const

Definition at line 2517 of file AMDGPULegalizerInfo.cpp.

References B, and MI.

Referenced by legalizeCustom().

◆ legalizeFMad()

bool AMDGPULegalizerInfo::legalizeFMad ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeFPow()

bool AMDGPULegalizerInfo::legalizeFPow ( MachineInstr MI,
MachineIRBuilder B 
) const

Definition at line 2546 of file AMDGPULegalizerInfo.cpp.

References B, MI, llvm::Mul, and llvm::LLT::scalar().

Referenced by legalizeCustom().

◆ legalizeFPTOI()

bool AMDGPULegalizerInfo::legalizeFPTOI ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  Signed 
) const

◆ legalizeFrem()

bool AMDGPULegalizerInfo::legalizeFrem ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

Definition at line 1940 of file AMDGPULegalizerInfo.cpp.

References B, llvm::MachineRegisterInfo::getType(), MI, and MRI.

Referenced by legalizeCustom().

◆ legalizeFrint()

bool AMDGPULegalizerInfo::legalizeFrint ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeGlobalValue()

bool AMDGPULegalizerInfo::legalizeGlobalValue ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeImageIntrinsic()

bool AMDGPULegalizerInfo::legalizeImageIntrinsic ( MachineInstr MI,
MachineIRBuilder B,
GISelChangeObserver Observer,
const AMDGPU::ImageDimIntrinsicInfo Intr 
) const

Rewrite image intrinsics to use register layouts expected by the subtarget.

Depending on the subtarget, load/store with 16-bit element data need to be rewritten to use the low half of 32-bit registers, or directly use a packed layout. 16-bit addresses should also sometimes be packed into 32-bit registers.

We don't want to directly select image instructions just yet, but also want to exposes all register repacking to the legalizer/combiners. We also don't want a selected instrution entering RegBankSelect. In order to avoid defining a multitude of intermediate image instructions, directly hack on the intrinsic's arguments. In cases like a16 addreses, this requires padding now unnecessary arguments with $noreg.

Definition at line 4111 of file AMDGPULegalizerInfo.cpp.

References assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic, llvm::AMDGPU::MIMGBaseOpcodeInfo::AtomicX2, B, llvm::GISelChangeObserver::changedInstr(), llvm::LLT::changeNumElements(), llvm::GISelChangeObserver::changingInstr(), Concat, convertImageAddrToPacked(), llvm::countPopulation(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineOperand::CreateImm(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Gather4, llvm::LLT::getElementType(), llvm::AMDGPU::getImageDimInstrinsicByBaseOpcode(), llvm::SrcOp::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGLZMappingInfo(), llvm::AMDGPU::getMIMGMIPMappingInfo(), llvm::LLT::getNumElements(), llvm::SrcOp::getReg(), llvm::LLT::getScalarType(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, handleD16VData(), llvm::GCNSubtarget::hasA16(), llvm::GCNSubtarget::hasG16(), llvm::GCNSubtarget::hasNSAEncoding(), llvm::GCNSubtarget::hasUnpackedD16VMem(), I, llvm::AMDGPU::ImageDimIntrinsicInfo::Intr, Intr, llvm::ConstantFP::isNegative(), llvm::LLT::isVector(), llvm::ConstantFP::isZero(), llvm::MIPatternMatch::m_GFCst(), llvm::MIPatternMatch::m_ICst(), llvm::make_scope_exit(), MI, llvm::MIPatternMatch::mi_match(), MRI, packImage16bitOpsToDwords(), Reg, llvm::SmallVectorImpl< T >::resize(), llvm::LLT::scalar(), llvm::LLT::scalarOrVector(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Store, llvm::RegState::Undef, and llvm::LLT::vector().

Referenced by legalizeIntrinsic().

◆ legalizeImplicitArgPtr()

bool AMDGPULegalizerInfo::legalizeImplicitArgPtr ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeInsertVectorElt()

bool AMDGPULegalizerInfo::legalizeInsertVectorElt ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeIntrinsic()

bool AMDGPULegalizerInfo::legalizeIntrinsic ( LegalizerHelper Helper,
MachineInstr MI 
) const
overridevirtual
Returns
true if MI is either legal or has been legalized and false if not legal. Return true if MI is either legal or has been legalized and false if not legal.

Reimplemented from llvm::LegalizerInfo.

Definition at line 4679 of file AMDGPULegalizerInfo.cpp.

References B, llvm::tgtok::Def, llvm::AMDGPUFunctionArgInfo::DISPATCH_ID, llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR, llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::MachineInstr::getOperand(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR, llvm::AMDGPU::isKernel(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, legalizeAtomicIncDec(), legalizeBufferAtomic(), legalizeBufferLoad(), legalizeBufferStore(), legalizeBVHIntrinsic(), legalizeDebugTrapIntrinsic(), legalizeDSAtomicFPIntrinsic(), legalizeFDIVFastIntrin(), legalizeImageIntrinsic(), legalizeImplicitArgPtr(), legalizeIsAddrSpace(), legalizePreloadedArgIntrin(), legalizeRsqClampIntrinsic(), legalizeSBufferLoad(), legalizeTrapIntrinsic(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, llvm::LegalizerHelper::MIRBuilder, MRI, llvm::LegalizerHelper::Observer, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::AMDGPUFunctionArgInfo::QUEUE_PTR, Reg, llvm::MachineOperand::setMBB(), llvm::MachineRegisterInfo::setRegClass(), std::swap(), TRI, verifyCFIntrinsic(), llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X, llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y, and llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z.

◆ legalizeIntrinsicTrunc()

bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeIsAddrSpace()

bool AMDGPULegalizerInfo::legalizeIsAddrSpace ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
unsigned  AddrSpace 
) const

◆ legalizeITOFP()

bool AMDGPULegalizerInfo::legalizeITOFP ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  Signed 
) const

◆ legalizeLoad()

bool AMDGPULegalizerInfo::legalizeLoad ( LegalizerHelper Helper,
MachineInstr MI 
) const

◆ legalizeMinNumMaxNum()

bool AMDGPULegalizerInfo::legalizeMinNumMaxNum ( LegalizerHelper Helper,
MachineInstr MI 
) const

◆ legalizePreloadedArgIntrin()

bool AMDGPULegalizerInfo::legalizePreloadedArgIntrin ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
AMDGPUFunctionArgInfo::PreloadedValue  ArgType 
) const

Definition at line 2764 of file AMDGPULegalizerInfo.cpp.

References B, loadInputValue(), and MI.

Referenced by legalizeImplicitArgPtr(), and legalizeIntrinsic().

◆ legalizeRawBufferLoad()

bool llvm::AMDGPULegalizerInfo::legalizeRawBufferLoad ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  IsFormat 
) const

◆ legalizeRawBufferStore()

bool llvm::AMDGPULegalizerInfo::legalizeRawBufferStore ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B,
bool  IsFormat 
) const

◆ legalizeRsqClampIntrinsic()

bool AMDGPULegalizerInfo::legalizeRsqClampIntrinsic ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeSBufferLoad()

bool AMDGPULegalizerInfo::legalizeSBufferLoad ( LegalizerHelper Helper,
MachineInstr MI 
) const

◆ legalizeSDIV_SREM()

bool AMDGPULegalizerInfo::legalizeSDIV_SREM ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeShuffleVector()

bool AMDGPULegalizerInfo::legalizeShuffleVector ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeSinCos()

bool AMDGPULegalizerInfo::legalizeSinCos ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeTrapEndpgm()

bool AMDGPULegalizerInfo::legalizeTrapEndpgm ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

Definition at line 4552 of file AMDGPULegalizerInfo.cpp.

References B, and MI.

Referenced by legalizeTrapIntrinsic().

◆ legalizeTrapHsa()

bool AMDGPULegalizerInfo::legalizeTrapHsa ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

Definition at line 4578 of file AMDGPULegalizerInfo.cpp.

References B, llvm::GCNSubtarget::LLVMAMDHSATrap, and MI.

Referenced by legalizeTrapIntrinsic().

◆ legalizeTrapHsaQueuePtr()

bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeTrapIntrinsic()

bool AMDGPULegalizerInfo::legalizeTrapIntrinsic ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeUDIV_UREM()

bool AMDGPULegalizerInfo::legalizeUDIV_UREM ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeUDIV_UREM32Impl()

void AMDGPULegalizerInfo::legalizeUDIV_UREM32Impl ( MachineIRBuilder B,
Register  DstReg,
Register  Num,
Register  Den,
bool  IsRem 
) const

◆ legalizeUDIV_UREM64()

bool llvm::AMDGPULegalizerInfo::legalizeUDIV_UREM64 ( MachineInstr MI,
MachineRegisterInfo MRI,
MachineIRBuilder B 
) const

◆ legalizeUDIV_UREM64Impl()

void AMDGPULegalizerInfo::legalizeUDIV_UREM64Impl ( MachineIRBuilder B,
Register  DstReg,
Register  Numer,
Register  Denom,
bool  IsDiv 
) const

◆ loadInputValue() [1/2]

bool AMDGPULegalizerInfo::loadInputValue ( Register  DstReg,
MachineIRBuilder B,
AMDGPUFunctionArgInfo::PreloadedValue  ArgType 
) const

◆ loadInputValue() [2/2]

bool AMDGPULegalizerInfo::loadInputValue ( Register  DstReg,
MachineIRBuilder B,
const ArgDescriptor Arg,
const TargetRegisterClass ArgRC,
LLT  ArgTy 
) const

◆ splitBufferOffsets()

std::tuple< Register, unsigned, unsigned > AMDGPULegalizerInfo::splitBufferOffsets ( MachineIRBuilder B,
Register  OrigOffset 
) const

The documentation for this class was generated from the following files: