LLVM 22.0.0git
Classes | Public Member Functions | Public Attributes | List of all members
llvm::AMDGPURegisterBankInfo Class Referencefinal

#include "Target/AMDGPU/AMDGPURegisterBankInfo.h"

Inheritance diagram for llvm::AMDGPURegisterBankInfo:
[legend]

Classes

struct  OpRegBankEntry

Public Member Functions

bool buildVCopy (MachineIRBuilder &B, Register DstReg, Register SrcReg) const
bool collectWaterfallOperands (SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
bool executeInWaterfallLoop (MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs) const
 Legalize instruction MI where operands in OpIndices must be SGPRs.
Register buildReadFirstLane (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Src) const
bool executeInWaterfallLoop (MachineIRBuilder &B, MachineInstr &MI, ArrayRef< unsigned > OpIndices) const
void constrainOpWithReadfirstlane (MachineIRBuilder &B, MachineInstr &MI, unsigned OpIdx) const
bool applyMappingDynStackAlloc (MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
bool applyMappingLoad (MachineIRBuilder &B, const OperandsMapper &OpdMapper, MachineInstr &MI) const
bool applyMappingImage (MachineIRBuilder &B, MachineInstr &MI, const OperandsMapper &OpdMapper, int RSrcIdx) const
unsigned setBufferOffsets (MachineIRBuilder &B, Register CombinedOffset, Register &VOffsetReg, Register &SOffsetReg, int64_t &InstOffsetVal, Align Alignment) const
bool applyMappingSBufferLoad (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
bool applyMappingBFE (MachineIRBuilder &B, const OperandsMapper &OpdMapper, bool Signed) const
bool applyMappingMAD_64_32 (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
void applyMappingSMULU64 (MachineIRBuilder &B, const OperandsMapper &OpdMapper) const
Register handleD16VData (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
 Handle register layout difference for f16 images for some subtargets.
std::pair< Register, unsigned > splitBufferOffsets (MachineIRBuilder &B, Register Offset) const
void applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override
 See RegisterBankInfo::applyMapping.
const ValueMapping * getValueMappingForPtr (const MachineRegisterInfo &MRI, Register Ptr) const
 Return the mapping for a pointer argument.
const RegisterBankInfo::InstructionMapping & getInstrMappingForLoad (const MachineInstr &MI) const
unsigned getRegBankID (Register Reg, const MachineRegisterInfo &MRI, unsigned Default=AMDGPU::VGPRRegBankID) const
const ValueMapping * getSGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const ValueMapping * getVGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
const ValueMapping * getAGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
void split64BitValueForMapping (MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
 Split 64-bit value Reg into two 32-bit halves and populate them into Regs.
template<unsigned NumOps>
InstructionMappings addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
unsigned getMappingType (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
bool isSALUMapping (const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingSOP (const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingVOP (const MachineInstr &MI) const
const InstructionMapping & getDefaultMappingAllVGPR (const MachineInstr &MI) const
const InstructionMapping & getImageMapping (const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
 AMDGPURegisterBankInfo (const GCNSubtarget &STI)
bool isDivergentRegBank (const RegisterBank *RB) const override
 Returns true if the register bank is considered divergent.
unsigned copyCost (const RegisterBank &A, const RegisterBank &B, TypeSize Size) const override
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
unsigned getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
 Get the cost of using ValMapping to decompose a register.
const RegisterBank & getRegBankFromRegClass (const TargetRegisterClass &RC, LLT) const override
 Get a register bank that covers RC.
bool isScalarLoadLegal (const MachineInstr &MI) const
InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const override
 Get the alternative mappings for MI.
const InstructionMapping & getInstrMapping (const MachineInstr &MI) const override
 This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.
template<unsigned NumOps>
RegisterBankInfo::InstructionMappings addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps > > Table) const
Public Member Functions inherited from llvm::RegisterBankInfo
const RegisterBank * getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.
virtual ~RegisterBankInfo ()=default
const RegisterBank & getRegBank (unsigned ID) const
 Get the register bank identified by ID.
unsigned getMaximumSize (unsigned RegBankID) const
 Get the maximum size in bits that fits in the given register bank.
const RegisterBank * getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg.
unsigned getNumRegBanks () const
 Get the total number of register banks.
bool cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const
InstructionMappings getInstrPossibleMappings (const MachineInstr &MI) const
 Get the possible mapping for MI.
void applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
 Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
TypeSize getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the size in bits of Reg.
bool verify (const TargetRegisterInfo &TRI) const
 Check that information hold by this instance make sense for the given TRI.
const InstructionMapping & getInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping.
const InstructionMapping & getInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping.

Public Attributes

const GCNSubtarget & Subtarget
const SIRegisterInfo * TRI
const SIInstrInfo * TII

Additional Inherited Members

Public Types inherited from llvm::RegisterBankInfo
using InstructionMappings = SmallVector<const InstructionMapping *, 4>
 Convenient type to represent the alternatives for mapping an instruction.
Static Public Member Functions inherited from llvm::RegisterBankInfo
static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping.
static const TargetRegisterClass * constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC.
Static Public Attributes inherited from llvm::RegisterBankInfo
static const unsigned DefaultMappingID = UINT_MAX
 Identifier used when the related instruction mapping instance is generated by target independent code.
static const unsigned InvalidMappingID = UINT_MAX - 1
 Identifier used when the related instruction mapping instance is generated by the default constructor.
Protected Member Functions inherited from llvm::RegisterBankInfo
 RegisterBankInfo (const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
 RegisterBankInfo ()
 This constructor is meaningless.
const RegisterBank & getRegBank (unsigned ID)
 Get the register bank identified by ID.
const TargetRegisterClass * getMinimalPhysRegClass (MCRegister Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg.
const InstructionMapping & getInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI.
const PartialMapping & getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments.
const ValueMapping & getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping.
const ValueMapping & getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments.
template<typename Iterator>
const ValueMapping * getOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
const ValueMapping * getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.
const ValueMapping * getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments.
Protected Attributes inherited from llvm::RegisterBankInfo
const RegisterBank ** RegBanks
 Hold the set of supported register banks.
unsigned NumRegBanks
 Total number of register banks.
const unsigned * Sizes
 Hold the sizes of the register banks for all HwModes.
unsigned HwMode
 Current HwMode for the target.
DenseMap< hash_code, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map.
DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map.
DenseMap< MCRegister, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive.

Detailed Description

Definition at line 42 of file AMDGPURegisterBankInfo.h.

Constructor & Destructor Documentation

◆ AMDGPURegisterBankInfo()

AMDGPURegisterBankInfo::AMDGPURegisterBankInfo ( const GCNSubtarget & STI)

Definition at line 204 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::call_once(), llvm::RegisterBankInfo::getRegBank(), Subtarget, TII, and TRI.

Member Function Documentation

◆ addMappingFromTable() [1/2]

template<unsigned NumOps>
RegisterBankInfo::InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable ( const MachineInstr & MI,
const MachineRegisterInfo & MRI,
const std::array< unsigned, NumOps > RegSrcOpIdx,
ArrayRef< OpRegBankEntry< NumOps > > Table ) const

Definition at line 309 of file AMDGPURegisterBankInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Operands, OpIdx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::Sizes, and TRI.

◆ addMappingFromTable() [2/2]

template<unsigned NumOps>
InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable ( const MachineInstr & MI,
const MachineRegisterInfo & MRI,
const std::array< unsigned, NumOps > RegSrcOpIdx,
ArrayRef< OpRegBankEntry< NumOps > > Table ) const

References A(), B(), MI, MRI, and Size.

Referenced by getInstrAlternativeMappings(), getInstrAlternativeMappingsIntrinsic(), and getInstrAlternativeMappingsIntrinsicWSideEffects().

◆ applyMappingBFE()

bool AMDGPURegisterBankInfo::applyMappingBFE ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper,
bool Signed ) const

Definition at line 1475 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), B(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::constrainSelectedInstRegOperands(), llvm::getIConstantVRegValWithLookThrough(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::isa(), llvm_unreachable, llvm::maskTrailingOnes(), MI, MRI, Opc, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, S64, llvm::LLT::scalar(), llvm::Signed, TII, and TRI.

Referenced by applyMappingImpl().

◆ applyMappingDynStackAlloc()

bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper,
MachineInstr & MI ) const

Definition at line 1172 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::assumeAligned(), B(), llvm::MachineFunction::getInfo(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::Log2(), MI, MRI, llvm::LLT::scalar(), SPReg, llvm::TargetFrameLowering::StackGrowsUp, TRI, and llvm::Align::value().

Referenced by applyMappingImpl().

◆ applyMappingImage()

bool AMDGPURegisterBankInfo::applyMappingImage ( MachineIRBuilder & B,
MachineInstr & MI,
const OperandsMapper & OpdMapper,
int RSrcIdx ) const

Definition at line 1226 of file AMDGPURegisterBankInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::RegisterBankInfo::applyDefaultMapping(), B(), executeInWaterfallLoop(), I, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by applyMappingImpl().

◆ applyMappingImpl()

void AMDGPURegisterBankInfo::applyMappingImpl ( MachineIRBuilder & Builder,
const OperandsMapper & OpdMapper ) const
overridevirtual

See RegisterBankInfo::applyMapping.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 2204 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), applyMappingBFE(), applyMappingDynStackAlloc(), applyMappingImage(), applyMappingLoad(), applyMappingMAD_64_32(), applyMappingSBufferLoad(), applyMappingSMULU64(), assert(), B(), llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, buildVCopy(), llvm::cast(), llvm::SmallVectorImpl< T >::clear(), collectWaterfallOperands(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, constrainOpWithReadfirstlane(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MachineInstrSpan::end(), executeInWaterfallLoop(), extendLow32IntoHigh32(), llvm::LLT::fixed_vector(), llvm::AMDGPU::getBaseWithConstantOffset(), getExtendOp(), llvm::MachineBasicBlock::getFirstTerminator(), getHalfSizedType(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::Type::getInt32Ty(), getIntrinsicID(), llvm::AMDGPU::getIntrinsicID(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::LLT::getNumElements(), llvm::MachineBasicBlock::getParent(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::Hi, I, llvm::AMDGPU::isFlatGlobalAddrSpace(), llvm::AMDGPU::RsrcIntrinsic::IsImage, llvm::LLT::isScalar(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, llvm_unreachable, llvm::Lo, llvm::AMDGPU::lookupRsrcIntrinsic(), llvm::LegalizerHelper::lowerAbsToMaxNeg(), llvm::MIPatternMatch::m_SpecificICstOrSplat(), llvm::make_range(), MBB, MI, llvm::MIPatternMatch::mi_match(), MRI, llvm::LegalizerHelper::narrowScalar(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::PartialMapping::RegBank, reinsertVectorIndexAdd(), llvm::SmallVectorImpl< T >::resize(), llvm::reverse(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, S32, S64, llvm::LLT::scalar(), setRegsToType(), llvm::Signed, llvm::SmallVectorTemplateCommon< T, typename >::size(), split64BitValueForMapping(), substituteSimpleCopyRegs(), Subtarget, TII, TRI, unpackV2S16ToS32(), llvm::LegalizerHelper::widenScalar(), llvm::LegalizerHelper::widenScalarDst(), llvm::LegalizerHelper::widenScalarSrc(), X, and Y.

◆ applyMappingLoad()

bool AMDGPURegisterBankInfo::applyMappingLoad ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper,
MachineInstr & MI ) const

Definition at line 1054 of file AMDGPURegisterBankInfo.cpp.

References assert(), B(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::cast(), llvm::LLT::divide(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::LegalizerHelper::fewerElementsVector(), llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineMemOperand::getSize(), llvm::LLT::getSizeInBits(), llvm::LocationSize::getValue(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::AMDGPUSubtarget::GFX12, llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::LLT::isScalar(), isScalarLoadLegal(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, MI, MRI, llvm::LegalizerHelper::narrowScalar(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::LegalizerHelper::reduceLoadStoreWidth(), llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), splitUnequalType(), Subtarget, and widen96To128().

Referenced by applyMappingImpl().

◆ applyMappingMAD_64_32()

bool AMDGPURegisterBankInfo::applyMappingMAD_64_32 ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper ) const

Definition at line 1581 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::applyDefaultMapping(), B(), buildReadFirstLane(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::CmpInst::ICMP_SLT, llvm::MIPatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, S1, S32, llvm::LLT::scalar(), and Subtarget.

Referenced by applyMappingImpl().

◆ applyMappingSBufferLoad()

bool AMDGPURegisterBankInfo::applyMappingSBufferLoad ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper ) const

Definition at line 1357 of file AMDGPURegisterBankInfo.cpp.

References B(), llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::MachineInstrSpan::end(), executeInWaterfallLoop(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineFunction::getMachineMemOperand(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), getSBufferLoadCorrespondingBufferLoadOpcode(), llvm::SmallSet< T, N, C >::insert(), llvm::make_range(), MI, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, MRI, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), and setBufferOffsets().

Referenced by applyMappingImpl().

◆ applyMappingSMULU64()

void AMDGPURegisterBankInfo::applyMappingSMULU64 ( MachineIRBuilder & B,
const OperandsMapper & OpdMapper ) const

Definition at line 2137 of file AMDGPURegisterBankInfo.cpp.

References llvm::Add, llvm::RegisterBankInfo::applyDefaultMapping(), assert(), B(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::Hi, MI, MRI, llvm::LLT::scalar(), setRegsToType(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and split64BitValueForMapping().

Referenced by applyMappingImpl().

◆ buildReadFirstLane()

Register AMDGPURegisterBankInfo::buildReadFirstLane ( MachineIRBuilder & B,
MachineRegisterInfo & MRI,
Register Src ) const

Definition at line 703 of file AMDGPURegisterBankInfo.cpp.

References assert(), B(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::RegisterBankInfo::getRegBank(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S32, llvm::LLT::scalar(), and TRI.

Referenced by applyMappingMAD_64_32(), constrainOpWithReadfirstlane(), and executeInWaterfallLoop().

◆ buildVCopy()

bool AMDGPURegisterBankInfo::buildVCopy ( MachineIRBuilder & B,
Register DstReg,
Register SrcReg ) const

Definition at line 1869 of file AMDGPURegisterBankInfo.cpp.

References B(), llvm::RegisterBankInfo::constrainGenericRegister(), and MRI.

Referenced by applyMappingImpl().

◆ collectWaterfallOperands()

bool AMDGPURegisterBankInfo::collectWaterfallOperands ( SmallSet< Register, 4 > & SGPROperandRegs,
MachineInstr & MI,
MachineRegisterInfo & MRI,
ArrayRef< unsigned > OpIndices ) const

Definition at line 985 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::SmallSet< T, N, C >::empty(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::SmallSet< T, N, C >::insert(), MI, MRI, and TRI.

Referenced by applyMappingImpl(), and executeInWaterfallLoop().

◆ constrainOpWithReadfirstlane()

void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane ( MachineIRBuilder & B,
MachineInstr & MI,
unsigned OpIdx ) const

Definition at line 1015 of file AMDGPURegisterBankInfo.cpp.

References B(), buildReadFirstLane(), llvm::RegisterBankInfo::getRegBank(), MI, MRI, OpIdx, and TRI.

Referenced by applyMappingImpl().

◆ copyCost()

unsigned AMDGPURegisterBankInfo::copyCost ( const RegisterBank & A,
const RegisterBank & B,
TypeSize Size ) const
overridevirtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note
Since this is a copy, both registers have the same size.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 230 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::copyCost(), isVectorRegisterBank(), and Size.

◆ executeInWaterfallLoop() [1/2]

bool AMDGPURegisterBankInfo::executeInWaterfallLoop ( MachineIRBuilder & B,
iterator_range< MachineBasicBlock::iterator > Range,
SmallSet< Register, 4 > & SGPROperandRegs ) const

Legalize instruction MI where operands in OpIndices must be SGPRs.

If any of the required SGPR operands are VGPRs, perform a waterfall loop to execute the instruction for each unique combination of values in all lanes in the wave. The block will be split such that rest of the instructions are moved to a new block.

Essentially performs this loop: Save Execution Mask For (Lane : Wavefront) { Enable Lane, Disable all other lanes SGPR = read SGPR value for current lane from VGPR VGPRResult[Lane] = use_op SGPR } Restore Execution Mask

There is additional complexity to try for compare values to identify the unique values used.

Definition at line 775 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), B(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), buildReadFirstLane(), llvm::SmallSet< T, N, C >::count(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineBasicBlock::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::CmpInst::ICMP_EQ, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineFunction::insert(), llvm::RegState::Kill, llvm::make_range(), MBB, MBBI, MI, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Range, S1, llvm::LLT::scalar(), llvm::MachineBasicBlock::splice(), Subtarget, TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and TRI.

Referenced by applyMappingImage(), applyMappingImpl(), applyMappingSBufferLoad(), and executeInWaterfallLoop().

◆ executeInWaterfallLoop() [2/2]

bool AMDGPURegisterBankInfo::executeInWaterfallLoop ( MachineIRBuilder & B,
MachineInstr & MI,
ArrayRef< unsigned > OpIndices ) const

Definition at line 1000 of file AMDGPURegisterBankInfo.cpp.

References B(), collectWaterfallOperands(), executeInWaterfallLoop(), I, llvm::make_range(), and MI.

◆ getAGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getAGPROpMapping ( Register Reg,
const MachineRegisterInfo & MRI,
const TargetRegisterInfo & TRI ) const

Definition at line 3829 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getBreakDownCost()

unsigned AMDGPURegisterBankInfo::getBreakDownCost ( const ValueMapping & ValMapping,
const RegisterBank * CurBank = nullptr ) const
overridevirtual

Get the cost of using ValMapping to decompose a register.

This is similar to copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank is non-null.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 261 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::RegisterBankInfo::PartialMapping::Length, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, llvm::RegisterBankInfo::PartialMapping::RegBank, and llvm::RegisterBankInfo::PartialMapping::StartIdx.

◆ getDefaultMappingAllVGPR()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingAllVGPR ( const MachineInstr & MI) const

Definition at line 3677 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getDefaultMappingSOP()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingSOP ( const MachineInstr & MI) const

Definition at line 3635 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), MI, MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getDefaultMappingVOP()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingVOP ( const MachineInstr & MI) const

Definition at line 3653 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), MI, MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getImageMapping()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getImageMapping ( const MachineRegisterInfo & MRI,
const MachineInstr & MI,
int RsrcIdx ) const

Definition at line 3696 of file AMDGPURegisterBankInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), getRegBankID(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getInstrAlternativeMappings()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappings ( const MachineInstr & MI) const
overridevirtual

Get the alternative mappings for MI.

Alternative in the sense different from getInstrMapping.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 470 of file AMDGPURegisterBankInfo.cpp.

References addMappingFromTable(), assert(), llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstrAlternativeMappings(), getInstrAlternativeMappingsIntrinsic(), getInstrAlternativeMappingsIntrinsicWSideEffects(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), isScalarLoadLegal(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, MRI, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPUAS::REGION_ADDRESS, Size, and TRI.

◆ getInstrAlternativeMappingsIntrinsic()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic ( const MachineInstr & MI,
const MachineRegisterInfo & MRI ) const

Definition at line 346 of file AMDGPURegisterBankInfo.cpp.

References addMappingFromTable(), llvm::cast(), llvm::RegisterBankInfo::getInstrAlternativeMappings(), getIntrinsicID(), MI, and MRI.

Referenced by getInstrAlternativeMappings().

◆ getInstrAlternativeMappingsIntrinsicWSideEffects()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects ( const MachineInstr & MI,
const MachineRegisterInfo & MRI ) const

Definition at line 386 of file AMDGPURegisterBankInfo.cpp.

References addMappingFromTable(), llvm::cast(), llvm::RegisterBankInfo::getInstrAlternativeMappings(), getIntrinsicID(), MI, and MRI.

Referenced by getInstrAlternativeMappings().

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getInstrMapping ( const MachineInstr & MI) const
overridevirtual

This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.

Any mapping that would cause a VGPR to SGPR generated is illegal.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 3846 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::RegisterBankInfo::cannotCopy(), llvm::cast(), llvm::dyn_cast(), llvm::LLT::fixed_vector(), getAGPROpMapping(), getDefaultMappingAllVGPR(), getDefaultMappingSOP(), getDefaultMappingVOP(), llvm::TypeSize::getFixed(), llvm::RegisterBank::getID(), getImageMapping(), llvm::MachineFunction::getInfo(), getInstrMappingForLoad(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), getIntrinsicID(), llvm::AMDGPU::getIntrinsicID(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), getMappingType(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::MachineFunction::getRegInfo(), getSGPROpMapping(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), llvm::RegisterBankInfo::getValueMapping(), getValueMappingForPtr(), getVGPROpMapping(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::AMDGPU::RsrcIntrinsic::IsImage, isReg(), isSALUMapping(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm::Register::isVirtual(), llvm::AMDGPU::lookupRsrcIntrinsic(), llvm::SIMachineFunctionInfo::mayNeedAGPRs(), MI, MRI, PHI, regBankBoolUnion(), regBankUnion(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, llvm::LLT::scalar(), Size, Subtarget, and TRI.

◆ getInstrMappingForLoad()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getInstrMappingForLoad ( const MachineInstr & MI) const

Definition at line 3755 of file AMDGPURegisterBankInfo.cpp.

References llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), llvm::AMDGPU::isFlatGlobalAddrSpace(), isScalarLoadLegal(), MI, MRI, Size, Subtarget, and TRI.

Referenced by getInstrMapping().

◆ getMappingType()

unsigned AMDGPURegisterBankInfo::getMappingType ( const MachineRegisterInfo & MRI,
const MachineInstr & MI ) const

Definition at line 3601 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getRegBank(), MI, MRI, regBankUnion(), and TRI.

Referenced by getInstrMapping().

◆ getRegBankFromRegClass()

const RegisterBank & AMDGPURegisterBankInfo::getRegBankFromRegClass ( const TargetRegisterClass & RC,
LLT Ty ) const
overridevirtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo
This should be TableGen'ed.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 287 of file AMDGPURegisterBankInfo.cpp.

References llvm::LLT::scalar(), and TRI.

◆ getRegBankID()

unsigned AMDGPURegisterBankInfo::getRegBankID ( Register Reg,
const MachineRegisterInfo & MRI,
unsigned Default = AMDGPU::VGPRRegBankID ) const

Definition at line 3802 of file AMDGPURegisterBankInfo.cpp.

References llvm::Default, llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), MRI, and TRI.

Referenced by applyMappingImpl(), getImageMapping(), getInstrMapping(), and getSGPROpMapping().

◆ getSGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getSGPROpMapping ( Register Reg,
const MachineRegisterInfo & MRI,
const TargetRegisterInfo & TRI ) const

Definition at line 3810 of file AMDGPURegisterBankInfo.cpp.

References getRegBankID(), llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ getValueMappingForPtr()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getValueMappingForPtr ( const MachineRegisterInfo & MRI,
Register Ptr ) const

Return the mapping for a pointer argument.

Definition at line 3740 of file AMDGPURegisterBankInfo.cpp.

References llvm::LLT::getAddressSpace(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::AMDGPU::isFlatGlobalAddrSpace(), MRI, Size, Subtarget, and TRI.

Referenced by getInstrMapping().

◆ getVGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getVGPROpMapping ( Register Reg,
const MachineRegisterInfo & MRI,
const TargetRegisterInfo & TRI ) const

Definition at line 3821 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.

Referenced by getInstrMapping().

◆ handleD16VData()

Register AMDGPURegisterBankInfo::handleD16VData ( MachineIRBuilder & B,
MachineRegisterInfo & MRI,
Register Reg ) const

Handle register layout difference for f16 images for some subtargets.

Definition at line 1784 of file AMDGPURegisterBankInfo.cpp.

References B(), llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), I, llvm::LLT::isVector(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S16, S32, llvm::LLT::scalar(), and Subtarget.

◆ isDivergentRegBank()

bool AMDGPURegisterBankInfo::isDivergentRegBank ( const RegisterBank * RB) const
overridevirtual

Returns true if the register bank is considered divergent.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 226 of file AMDGPURegisterBankInfo.cpp.

◆ isSALUMapping()

bool AMDGPURegisterBankInfo::isSALUMapping ( const MachineInstr & MI) const

Definition at line 3619 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), MI, MRI, and TRI.

Referenced by getInstrMapping().

◆ isScalarLoadLegal()

bool AMDGPURegisterBankInfo::isScalarLoadLegal ( const MachineInstr & MI) const

Definition at line 444 of file AMDGPURegisterBankInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::MachineMemOperand::getFlags(), llvm::MachineMemOperand::getSize(), llvm::LocationSize::getValue(), llvm::MachineMemOperand::isAtomic(), llvm::MachineMemOperand::isInvariant(), llvm::AMDGPU::isUniformMMO(), llvm::MachineMemOperand::isVolatile(), MI, llvm::MONoClobber, and Subtarget.

Referenced by applyMappingLoad(), getInstrAlternativeMappings(), and getInstrMappingForLoad().

◆ setBufferOffsets()

unsigned AMDGPURegisterBankInfo::setBufferOffsets ( MachineIRBuilder & B,
Register CombinedOffset,
Register & VOffsetReg,
Register & SOffsetReg,
int64_t & InstOffsetVal,
Align Alignment ) const

Definition at line 1256 of file AMDGPURegisterBankInfo.cpp.

References llvm::Add, B(), llvm::sampleprof::Base, llvm::AMDGPU::getBaseWithConstantOffset(), llvm::getIConstantVRegSExtVal(), llvm::getOpcodeDef(), llvm::RegisterBankInfo::getRegBank(), llvm::getSrcRegIgnoringCopies(), MRI, llvm::Offset, S32, llvm::LLT::scalar(), TII, and TRI.

Referenced by applyMappingSBufferLoad().

◆ split64BitValueForMapping()

void AMDGPURegisterBankInfo::split64BitValueForMapping ( MachineIRBuilder & B,
SmallVector< Register, 2 > & Regs,
LLT HalfTy,
Register Reg ) const

Split 64-bit value Reg into two 32-bit halves and populate them into Regs.

This appropriately sets the regbank of the new registers.

Definition at line 659 of file AMDGPURegisterBankInfo.cpp.

References assert(), B(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

Referenced by applyMappingImpl(), and applyMappingSMULU64().

◆ splitBufferOffsets()

std::pair< Register, unsigned > AMDGPURegisterBankInfo::splitBufferOffsets ( MachineIRBuilder & B,
Register Offset ) const

Definition at line 1824 of file AMDGPURegisterBankInfo.cpp.

References B(), getBaseWithConstantOffset(), llvm::SIInstrInfo::getMaxMUBUFImmOffset(), S32, llvm::LLT::scalar(), and Subtarget.

Member Data Documentation

◆ Subtarget

const GCNSubtarget& llvm::AMDGPURegisterBankInfo::Subtarget

Definition at line 44 of file AMDGPURegisterBankInfo.h.

Referenced by AMDGPURegisterBankInfo(), applyMappingImpl(), applyMappingLoad(), applyMappingMAD_64_32(), executeInWaterfallLoop(), getInstrMapping(), getInstrMappingForLoad(), getValueMappingForPtr(), handleD16VData(), isScalarLoadLegal(), and splitBufferOffsets().

◆ TII

const SIInstrInfo* llvm::AMDGPURegisterBankInfo::TII

Definition at line 46 of file AMDGPURegisterBankInfo.h.

Referenced by AMDGPURegisterBankInfo(), applyMappingBFE(), applyMappingImpl(), executeInWaterfallLoop(), and setBufferOffsets().

◆ TRI

const SIRegisterInfo* llvm::AMDGPURegisterBankInfo::TRI

Definition at line 45 of file AMDGPURegisterBankInfo.h.

Referenced by addMappingFromTable(), AMDGPURegisterBankInfo(), applyMappingBFE(), applyMappingDynStackAlloc(), applyMappingImpl(), buildReadFirstLane(), collectWaterfallOperands(), constrainOpWithReadfirstlane(), executeInWaterfallLoop(), getAGPROpMapping(), getDefaultMappingAllVGPR(), getDefaultMappingSOP(), getDefaultMappingVOP(), getImageMapping(), getInstrAlternativeMappings(), getInstrMapping(), getInstrMappingForLoad(), getMappingType(), getRegBankFromRegClass(), getRegBankID(), getSGPROpMapping(), getValueMappingForPtr(), getVGPROpMapping(), isSALUMapping(), setBufferOffsets(), and split64BitValueForMapping().

The documentation for this class was generated from the following files:
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