LLVM 17.0.0git
HexagonGenPredicate.cpp
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1//===- HexagonGenPredicate.cpp --------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonInstrInfo.h"
10#include "HexagonSubtarget.h"
11#include "llvm/ADT/SetVector.h"
12#include "llvm/ADT/StringRef.h"
22#include "llvm/IR/DebugLoc.h"
24#include "llvm/Pass.h"
26#include "llvm/Support/Debug.h"
29#include <cassert>
30#include <iterator>
31#include <map>
32#include <queue>
33#include <set>
34#include <utility>
35
36#define DEBUG_TYPE "gen-pred"
37
38using namespace llvm;
39
40namespace llvm {
41
44
45} // end namespace llvm
46
47namespace {
48
49 // FIXME: Use TargetInstrInfo::RegSubRegPair
50 struct RegisterSubReg {
51 Register R;
52 unsigned S;
53
54 RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
55 RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
56 RegisterSubReg(const Register &Reg) : R(Reg), S(0) {}
57
58 bool operator== (const RegisterSubReg &Reg) const {
59 return R == Reg.R && S == Reg.S;
60 }
61
62 bool operator< (const RegisterSubReg &Reg) const {
63 return R < Reg.R || (R == Reg.R && S < Reg.S);
64 }
65 };
66
67 struct PrintRegister {
68 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
69
70 PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
71
72 private:
73 RegisterSubReg Reg;
75 };
76
77 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
79 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
80 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
81 }
82
83 class HexagonGenPredicate : public MachineFunctionPass {
84 public:
85 static char ID;
86
87 HexagonGenPredicate() : MachineFunctionPass(ID) {
89 }
90
91 StringRef getPassName() const override {
92 return "Hexagon generate predicate operations";
93 }
94
95 void getAnalysisUsage(AnalysisUsage &AU) const override {
99 }
100
101 bool runOnMachineFunction(MachineFunction &MF) override;
102
103 private:
104 using VectOfInst = SetVector<MachineInstr *>;
105 using SetOfReg = std::set<RegisterSubReg>;
106 using RegToRegMap = std::map<RegisterSubReg, RegisterSubReg>;
107
108 const HexagonInstrInfo *TII = nullptr;
109 const HexagonRegisterInfo *TRI = nullptr;
110 MachineRegisterInfo *MRI = nullptr;
111 SetOfReg PredGPRs;
112 VectOfInst PUsers;
113 RegToRegMap G2P;
114
115 bool isPredReg(Register R);
116 void collectPredicateGPR(MachineFunction &MF);
117 void processPredicateGPR(const RegisterSubReg &Reg);
118 unsigned getPredForm(unsigned Opc);
119 bool isConvertibleToPredForm(const MachineInstr *MI);
120 bool isScalarCmp(unsigned Opc);
121 bool isScalarPred(RegisterSubReg PredReg);
122 RegisterSubReg getPredRegFor(const RegisterSubReg &Reg);
123 bool convertToPredForm(MachineInstr *MI);
124 bool eliminatePredCopies(MachineFunction &MF);
125 };
126
127} // end anonymous namespace
128
129char HexagonGenPredicate::ID = 0;
130
131INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
132 "Hexagon generate predicate operations", false, false)
134INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred",
135 "Hexagon generate predicate operations", false, false)
136
137bool HexagonGenPredicate::isPredReg(Register R) {
138 if (!R.isVirtual())
139 return false;
140 const TargetRegisterClass *RC = MRI->getRegClass(R);
141 return RC == &Hexagon::PredRegsRegClass;
142}
143
144unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
145 using namespace Hexagon;
146
147 switch (Opc) {
148 case A2_and:
149 case A2_andp:
150 return C2_and;
151 case A4_andn:
152 case A4_andnp:
153 return C2_andn;
154 case M4_and_and:
155 return C4_and_and;
156 case M4_and_andn:
157 return C4_and_andn;
158 case M4_and_or:
159 return C4_and_or;
160
161 case A2_or:
162 case A2_orp:
163 return C2_or;
164 case A4_orn:
165 case A4_ornp:
166 return C2_orn;
167 case M4_or_and:
168 return C4_or_and;
169 case M4_or_andn:
170 return C4_or_andn;
171 case M4_or_or:
172 return C4_or_or;
173
174 case A2_xor:
175 case A2_xorp:
176 return C2_xor;
177
178 case C2_tfrrp:
179 return COPY;
180 }
181 // The opcode corresponding to 0 is TargetOpcode::PHI. We can use 0 here
182 // to denote "none", but we need to make sure that none of the valid opcodes
183 // that we return will ever be 0.
184 static_assert(PHI == 0, "Use different value for <none>");
185 return 0;
186}
187
188bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) {
189 unsigned Opc = MI->getOpcode();
190 if (getPredForm(Opc) != 0)
191 return true;
192
193 // Comparisons against 0 are also convertible. This does not apply to
194 // A4_rcmpeqi or A4_rcmpneqi, since they produce values 0 or 1, which
195 // may not match the value that the predicate register would have if
196 // it was converted to a predicate form.
197 switch (Opc) {
198 case Hexagon::C2_cmpeqi:
199 case Hexagon::C4_cmpneqi:
200 if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
201 return true;
202 break;
203 }
204 return false;
205}
206
207void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
208 for (MachineBasicBlock &B : MF) {
209 for (MachineInstr &MI : B) {
210 unsigned Opc = MI.getOpcode();
211 switch (Opc) {
212 case Hexagon::C2_tfrpr:
213 case TargetOpcode::COPY:
214 if (isPredReg(MI.getOperand(1).getReg())) {
215 RegisterSubReg RD = MI.getOperand(0);
216 if (RD.R.isVirtual())
217 PredGPRs.insert(RD);
218 }
219 break;
220 }
221 }
222 }
223}
224
225void HexagonGenPredicate::processPredicateGPR(const RegisterSubReg &Reg) {
226 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n");
227 using use_iterator = MachineRegisterInfo::use_iterator;
228
229 use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
230 if (I == E) {
231 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
232 MachineInstr *DefI = MRI->getVRegDef(Reg.R);
233 DefI->eraseFromParent();
234 return;
235 }
236
237 for (; I != E; ++I) {
238 MachineInstr *UseI = I->getParent();
239 if (isConvertibleToPredForm(UseI))
240 PUsers.insert(UseI);
241 }
242}
243
244RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
245 // Create a predicate register for a given Reg. The newly created register
246 // will have its value copied from Reg, so that it can be later used as
247 // an operand in other instructions.
248 assert(Reg.R.isVirtual());
249 RegToRegMap::iterator F = G2P.find(Reg);
250 if (F != G2P.end())
251 return F->second;
252
253 LLVM_DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
254 MachineInstr *DefI = MRI->getVRegDef(Reg.R);
255 assert(DefI);
256 unsigned Opc = DefI->getOpcode();
257 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) {
258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
259 RegisterSubReg PR = DefI->getOperand(1);
260 G2P.insert(std::make_pair(Reg, PR));
261 LLVM_DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
262 return PR;
263 }
264
265 MachineBasicBlock &B = *DefI->getParent();
266 DebugLoc DL = DefI->getDebugLoc();
267 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
268 Register NewPR = MRI->createVirtualRegister(PredRC);
269
270 // For convertible instructions, do not modify them, so that they can
271 // be converted later. Generate a copy from Reg to NewPR.
272 if (isConvertibleToPredForm(DefI)) {
273 MachineBasicBlock::iterator DefIt = DefI;
274 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
275 .addReg(Reg.R, 0, Reg.S);
276 G2P.insert(std::make_pair(Reg, RegisterSubReg(NewPR)));
277 LLVM_DEBUG(dbgs() << " -> !" << PrintRegister(RegisterSubReg(NewPR), *TRI)
278 << '\n');
279 return RegisterSubReg(NewPR);
280 }
281
282 llvm_unreachable("Invalid argument");
283}
284
285bool HexagonGenPredicate::isScalarCmp(unsigned Opc) {
286 switch (Opc) {
287 case Hexagon::C2_cmpeq:
288 case Hexagon::C2_cmpgt:
289 case Hexagon::C2_cmpgtu:
290 case Hexagon::C2_cmpeqp:
291 case Hexagon::C2_cmpgtp:
292 case Hexagon::C2_cmpgtup:
293 case Hexagon::C2_cmpeqi:
294 case Hexagon::C2_cmpgti:
295 case Hexagon::C2_cmpgtui:
296 case Hexagon::C2_cmpgei:
297 case Hexagon::C2_cmpgeui:
298 case Hexagon::C4_cmpneqi:
299 case Hexagon::C4_cmpltei:
300 case Hexagon::C4_cmplteui:
301 case Hexagon::C4_cmpneq:
302 case Hexagon::C4_cmplte:
303 case Hexagon::C4_cmplteu:
304 case Hexagon::A4_cmpbeq:
305 case Hexagon::A4_cmpbeqi:
306 case Hexagon::A4_cmpbgtu:
307 case Hexagon::A4_cmpbgtui:
308 case Hexagon::A4_cmpbgt:
309 case Hexagon::A4_cmpbgti:
310 case Hexagon::A4_cmpheq:
311 case Hexagon::A4_cmphgt:
312 case Hexagon::A4_cmphgtu:
313 case Hexagon::A4_cmpheqi:
314 case Hexagon::A4_cmphgti:
315 case Hexagon::A4_cmphgtui:
316 return true;
317 }
318 return false;
319}
320
321bool HexagonGenPredicate::isScalarPred(RegisterSubReg PredReg) {
322 std::queue<RegisterSubReg> WorkQ;
323 WorkQ.push(PredReg);
324
325 while (!WorkQ.empty()) {
326 RegisterSubReg PR = WorkQ.front();
327 WorkQ.pop();
328 const MachineInstr *DefI = MRI->getVRegDef(PR.R);
329 if (!DefI)
330 return false;
331 unsigned DefOpc = DefI->getOpcode();
332 switch (DefOpc) {
333 case TargetOpcode::COPY: {
334 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
335 if (MRI->getRegClass(PR.R) != PredRC)
336 return false;
337 // If it is a copy between two predicate registers, fall through.
338 [[fallthrough]];
339 }
340 case Hexagon::C2_and:
341 case Hexagon::C2_andn:
342 case Hexagon::C4_and_and:
343 case Hexagon::C4_and_andn:
344 case Hexagon::C4_and_or:
345 case Hexagon::C2_or:
346 case Hexagon::C2_orn:
347 case Hexagon::C4_or_and:
348 case Hexagon::C4_or_andn:
349 case Hexagon::C4_or_or:
350 case Hexagon::C4_or_orn:
351 case Hexagon::C2_xor:
352 // Add operands to the queue.
353 for (const MachineOperand &MO : DefI->operands())
354 if (MO.isReg() && MO.isUse())
355 WorkQ.push(RegisterSubReg(MO.getReg()));
356 break;
357
358 // All non-vector compares are ok, everything else is bad.
359 default:
360 return isScalarCmp(DefOpc);
361 }
362 }
363
364 return true;
365}
366
367bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
368 LLVM_DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI);
369
370 unsigned Opc = MI->getOpcode();
371 assert(isConvertibleToPredForm(MI));
372 unsigned NumOps = MI->getNumOperands();
373 for (unsigned i = 0; i < NumOps; ++i) {
374 MachineOperand &MO = MI->getOperand(i);
375 if (!MO.isReg() || !MO.isUse())
376 continue;
377 RegisterSubReg Reg(MO);
378 if (Reg.S && Reg.S != Hexagon::isub_lo)
379 return false;
380 if (!PredGPRs.count(Reg))
381 return false;
382 }
383
384 MachineBasicBlock &B = *MI->getParent();
385 DebugLoc DL = MI->getDebugLoc();
386
387 unsigned NewOpc = getPredForm(Opc);
388 // Special case for comparisons against 0.
389 if (NewOpc == 0) {
390 switch (Opc) {
391 case Hexagon::C2_cmpeqi:
392 NewOpc = Hexagon::C2_not;
393 break;
394 case Hexagon::C4_cmpneqi:
395 NewOpc = TargetOpcode::COPY;
396 break;
397 default:
398 return false;
399 }
400
401 // If it's a scalar predicate register, then all bits in it are
402 // the same. Otherwise, to determine whether all bits are 0 or not
403 // we would need to use any8.
404 RegisterSubReg PR = getPredRegFor(MI->getOperand(1));
405 if (!isScalarPred(PR))
406 return false;
407 // This will skip the immediate argument when creating the predicate
408 // version instruction.
409 NumOps = 2;
410 }
411
412 // Check that def is in operand #0.
413 MachineOperand &Op0 = MI->getOperand(0);
414 assert(Op0.isDef());
415 RegisterSubReg OutR(Op0);
416
417 // Don't use getPredRegFor, since it will create an association between
418 // the argument and a created predicate register (i.e. it will insert a
419 // copy if a new predicate register is created).
420 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
421 RegisterSubReg NewPR = MRI->createVirtualRegister(PredRC);
422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
423
424 // Add predicate counterparts of the GPRs.
425 for (unsigned i = 1; i < NumOps; ++i) {
426 RegisterSubReg GPR = MI->getOperand(i);
427 RegisterSubReg Pred = getPredRegFor(GPR);
428 MIB.addReg(Pred.R, 0, Pred.S);
429 }
430 LLVM_DEBUG(dbgs() << "generated: " << *MIB);
431
432 // Generate a copy-out: NewGPR = NewPR, and replace all uses of OutR
433 // with NewGPR.
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
435 Register NewOutR = MRI->createVirtualRegister(RC);
436 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
437 .addReg(NewPR.R, 0, NewPR.S);
438 MRI->replaceRegWith(OutR.R, NewOutR);
439 MI->eraseFromParent();
440
441 // If the processed instruction was C2_tfrrp (i.e. Rn = Pm; Pk = Rn),
442 // then the output will be a predicate register. Do not visit the
443 // users of it.
444 if (!isPredReg(NewOutR)) {
445 RegisterSubReg R(NewOutR);
446 PredGPRs.insert(R);
447 processPredicateGPR(R);
448 }
449 return true;
450}
451
452bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
453 LLVM_DEBUG(dbgs() << __func__ << "\n");
454 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
455 bool Changed = false;
456 VectOfInst Erase;
457
458 // First, replace copies
459 // IntR = PredR1
460 // PredR2 = IntR
461 // with
462 // PredR2 = PredR1
463 // Such sequences can be generated when a copy-into-pred is generated from
464 // a gpr register holding a result of a convertible instruction. After
465 // the convertible instruction is converted, its predicate result will be
466 // copied back into the original gpr.
467
468 for (MachineBasicBlock &MBB : MF) {
469 for (MachineInstr &MI : MBB) {
470 if (MI.getOpcode() != TargetOpcode::COPY)
471 continue;
472 RegisterSubReg DR = MI.getOperand(0);
473 RegisterSubReg SR = MI.getOperand(1);
474 if (!DR.R.isVirtual())
475 continue;
476 if (!SR.R.isVirtual())
477 continue;
478 if (MRI->getRegClass(DR.R) != PredRC)
479 continue;
480 if (MRI->getRegClass(SR.R) != PredRC)
481 continue;
482 assert(!DR.S && !SR.S && "Unexpected subregister");
483 MRI->replaceRegWith(DR.R, SR.R);
484 Erase.insert(&MI);
485 Changed = true;
486 }
487 }
488
489 for (MachineInstr *MI : Erase)
490 MI->eraseFromParent();
491
492 return Changed;
493}
494
495bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
496 if (skipFunction(MF.getFunction()))
497 return false;
498
499 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
500 TRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
501 MRI = &MF.getRegInfo();
502 PredGPRs.clear();
503 PUsers.clear();
504 G2P.clear();
505
506 bool Changed = false;
507 collectPredicateGPR(MF);
508 for (const RegisterSubReg &R : PredGPRs)
509 processPredicateGPR(R);
510
511 bool Again;
512 do {
513 Again = false;
514 VectOfInst Processed, Copy;
515
516 Copy = PUsers;
517 for (MachineInstr *MI : Copy) {
518 bool Done = convertToPredForm(MI);
519 if (Done) {
520 Processed.insert(MI);
521 Again = true;
522 }
523 }
524 Changed |= Again;
525
526 auto Done = [Processed] (MachineInstr *MI) -> bool {
527 return Processed.count(MI);
528 };
529 PUsers.remove_if(Done);
530 } while (Again);
531
532 Changed |= eliminatePredCopies(MF);
533 return Changed;
534}
535
537 return new HexagonGenPredicate();
538}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Rewrite undef for PHI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:172
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
hexagon gen pred
hexagon gen Hexagon generate predicate operations
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
defusechain_iterator< true, false, false, true, false, false > use_iterator
use_iterator/use_begin/use_end - Walk all uses of the specified register.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
A vector that has set insertion semantics.
Definition: SetVector.h:40
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
-inline-oz-test-model
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
bool isPredReg(MCRegisterInfo const &MRI, unsigned Reg)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:361
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
@ Done
Definition: Threading.h:61
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
void initializeHexagonGenPredicatePass(PassRegistry &Registry)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createHexagonGenPredicate()
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.