Go to the documentation of this file.
43 std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
88 bool shouldBreakDependence(
MachineInstr *,
unsigned OpIdx,
unsigned Pref);
100 #define DEBUG_TYPE "break-false-deps"
109 bool BreakFalseDeps::pickBestRegisterForUndef(
MachineInstr *
MI,
unsigned OpIdx,
113 if (
MI->isRegTiedToDefOperand(OpIdx))
127 unsigned NumRoots = 0;
138 assert(OpRC &&
"Not a valid register class");
143 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
148 MO.
setReg(CurrMO.getReg());
154 unsigned MaxClearance = 0;
155 unsigned MaxClearanceReg = OriginalReg;
159 if (Clearance <= MaxClearance)
161 MaxClearance = Clearance;
162 MaxClearanceReg =
Reg;
164 if (MaxClearance > Pref)
169 if (MaxClearanceReg != OriginalReg)
170 MO.
setReg(MaxClearanceReg);
175 bool BreakFalseDeps::shouldBreakDependence(
MachineInstr *
MI,
unsigned OpIdx,
179 LLVM_DEBUG(
dbgs() <<
"Clearance: " << Clearance <<
", want " << Pref);
181 if (Pref > Clearance) {
190 assert(!
MI->isDebugInstr() &&
"Won't process debug values");
203 bool HadTrueDependency = pickBestRegisterForUndef(
MI,
i, Pref);
207 if (!HadTrueDependency && shouldBreakDependence(
MI,
i, Pref))
208 UndefReads.push_back(std::make_pair(
MI,
i));
227 if (Pref && shouldBreakDependence(
MI,
i, Pref))
233 if (UndefReads.empty())
248 unsigned OpIdx = UndefReads.back().second;
258 UndefReads.pop_back();
259 if (UndefReads.empty())
262 UndefMI = UndefReads.back().first;
263 OpIdx = UndefReads.back().second;
275 if (!
MI.isDebugInstr())
278 processUndefReads(
MBB);
287 RDA = &getAnalysis<ReachingDefAnalysis>();
291 LLVM_DEBUG(
dbgs() <<
"********** BREAK FALSE DEPENDENCIES **********\n");
295 processBasicBlock(&
MBB);
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
This is an optimization pass for GlobalISel generic memory operations.
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
This class provides the reaching def analysis.
virtual const TargetInstrInfo * getInstrInfo() const
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
A set of physical registers with utility functions to track liveness when walking backward/forward th...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
MachineFunctionProperties getRequiredProperties() const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Properties which a MachineFunction may have at a given point in time.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetInstrInfo - Interface to description of machine instruction set.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isValid() const
Check if the iterator is at the end of the list.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void init(const MachineRegisterInfo &MRI)
Register getReg() const
getReg - Returns the register number.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
void initializeBreakFalseDepsPass(PassRegistry &)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
A set of live virtual registers and physical register units.
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Function & getFunction()
Return the LLVM function that this machine code represents.
void setPreservesAll()
Set by analyses that do not transform their input at all.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MCRegUnitRootIterator enumerates the root registers of a register unit.
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
void setReg(Register Reg)
Change the register this operand corresponds to.
auto reverse(ContainerTy &&C)
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
FunctionPass class - This class is used to implement most global optimizations.
int getClearance(MachineInstr *MI, MCRegister PhysReg) const
Provides the clearance - the number of instructions since the closest reaching def instuction of Phys...
AnalysisUsage & addRequired()
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
LaneBitmask contains(Register Reg) const
Wrapper class representing physical registers. Should be passed by value.