LLVM  16.0.0git
CalcSpillWeights.cpp
Go to the documentation of this file.
1 //===- CalcSpillWeights.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/CodeGen/StackMaps.h"
23 #include "llvm/Support/Debug.h"
25 #include <cassert>
26 #include <tuple>
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "calcspillweights"
31 
33  LLVM_DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
34  << "********** Function: " << MF.getName() << '\n');
35 
37  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
39  if (MRI.reg_nodbg_empty(Reg))
40  continue;
42  }
43 }
44 
45 // Return the preferred allocation register for reg, given a COPY instruction.
47  const TargetRegisterInfo &TRI,
48  const MachineRegisterInfo &MRI) {
49  unsigned Sub, HSub;
50  Register HReg;
51  if (MI->getOperand(0).getReg() == Reg) {
52  Sub = MI->getOperand(0).getSubReg();
53  HReg = MI->getOperand(1).getReg();
54  HSub = MI->getOperand(1).getSubReg();
55  } else {
56  Sub = MI->getOperand(1).getSubReg();
57  HReg = MI->getOperand(0).getReg();
58  HSub = MI->getOperand(0).getSubReg();
59  }
60 
61  if (!HReg)
62  return 0;
63 
65  return Sub == HSub ? HReg : Register();
66 
68  MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg();
69  if (RC->contains(CopiedPReg))
70  return CopiedPReg;
71 
72  // Check if reg:sub matches so that a super register could be hinted.
73  if (Sub)
74  return TRI.getMatchingSuperReg(CopiedPReg, Sub, RC);
75 
76  return 0;
77 }
78 
79 // Check if all values in LI are rematerializable
81  const LiveIntervals &LIS,
82  const VirtRegMap &VRM,
83  const TargetInstrInfo &TII) {
84  Register Reg = LI.reg();
85  Register Original = VRM.getOriginal(Reg);
87  I != E; ++I) {
88  const VNInfo *VNI = *I;
89  if (VNI->isUnused())
90  continue;
91  if (VNI->isPHIDef())
92  return false;
93 
95  assert(MI && "Dead valno in interval");
96 
97  // Trace copies introduced by live range splitting. The inline
98  // spiller can rematerialize through these copies, so the spill
99  // weight must reflect this.
100  while (MI->isFullCopy()) {
101  // The copy destination must match the interval register.
102  if (MI->getOperand(0).getReg() != Reg)
103  return false;
104 
105  // Get the source register.
106  Reg = MI->getOperand(1).getReg();
107 
108  // If the original (pre-splitting) registers match this
109  // copy came from a split.
110  if (!Register::isVirtualRegister(Reg) || VRM.getOriginal(Reg) != Original)
111  return false;
112 
113  // Follow the copy live-in value.
114  const LiveInterval &SrcLI = LIS.getInterval(Reg);
115  LiveQueryResult SrcQ = SrcLI.Query(VNI->def);
116  VNI = SrcQ.valueIn();
117  assert(VNI && "Copy from non-existing value");
118  if (VNI->isPHIDef())
119  return false;
120  MI = LIS.getInstructionFromIndex(VNI->def);
121  assert(MI && "Dead valno in interval");
122  }
123 
124  if (!TII.isTriviallyReMaterializable(*MI))
125  return false;
126  }
127  return true;
128 }
129 
130 bool VirtRegAuxInfo::isLiveAtStatepointVarArg(LiveInterval &LI) {
131  return any_of(VRM.getRegInfo().reg_operands(LI.reg()),
132  [](MachineOperand &MO) {
133  MachineInstr *MI = MO.getParent();
134  if (MI->getOpcode() != TargetOpcode::STATEPOINT)
135  return false;
136  return StatepointOpers(MI).getVarIdx() <= MI->getOperandNo(&MO);
137  });
138 }
139 
141  float Weight = weightCalcHelper(LI);
142  // Check if unspillable.
143  if (Weight < 0)
144  return;
145  LI.setWeight(Weight);
146 }
147 
149  SlotIndex *End) {
152  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
153  MachineBasicBlock *MBB = nullptr;
154  MachineLoop *Loop = nullptr;
155  bool IsExiting = false;
156  float TotalWeight = 0;
157  unsigned NumInstr = 0; // Number of instructions using LI
159 
160  std::pair<Register, Register> TargetHint = MRI.getRegAllocationHint(LI.reg());
161 
162  if (LI.isSpillable()) {
163  Register Reg = LI.reg();
164  Register Original = VRM.getOriginal(Reg);
165  const LiveInterval &OrigInt = LIS.getInterval(Original);
166  // li comes from a split of OrigInt. If OrigInt was marked
167  // as not spillable, make sure the new interval is marked
168  // as not spillable as well.
169  if (!OrigInt.isSpillable())
170  LI.markNotSpillable();
171  }
172 
173  // Don't recompute spill weight for an unspillable register.
174  bool IsSpillable = LI.isSpillable();
175 
176  bool IsLocalSplitArtifact = Start && End;
177 
178  // Do not update future local split artifacts.
179  bool ShouldUpdateLI = !IsLocalSplitArtifact;
180 
181  if (IsLocalSplitArtifact) {
182  MachineBasicBlock *LocalMBB = LIS.getMBBFromIndex(*End);
183  assert(LocalMBB == LIS.getMBBFromIndex(*Start) &&
184  "start and end are expected to be in the same basic block");
185 
186  // Local split artifact will have 2 additional copy instructions and they
187  // will be in the same BB.
188  // localLI = COPY other
189  // ...
190  // other = COPY localLI
191  TotalWeight += LiveIntervals::getSpillWeight(true, false, &MBFI, LocalMBB);
192  TotalWeight += LiveIntervals::getSpillWeight(false, true, &MBFI, LocalMBB);
193 
194  NumInstr += 2;
195  }
196 
197  // CopyHint is a sortable hint derived from a COPY instruction.
198  struct CopyHint {
199  const Register Reg;
200  const float Weight;
201  CopyHint(Register R, float W) : Reg(R), Weight(W) {}
202  bool operator<(const CopyHint &Rhs) const {
203  // Always prefer any physreg hint.
204  if (Reg.isPhysical() != Rhs.Reg.isPhysical())
205  return Reg.isPhysical();
206  if (Weight != Rhs.Weight)
207  return (Weight > Rhs.Weight);
208  return Reg.id() < Rhs.Reg.id(); // Tie-breaker.
209  }
210  };
211 
212  std::set<CopyHint> CopyHints;
215  I = MRI.reg_instr_nodbg_begin(LI.reg()),
217  I != E;) {
218  MachineInstr *MI = &*(I++);
219 
220  // For local split artifacts, we are interested only in instructions between
221  // the expected start and end of the range.
223  if (IsLocalSplitArtifact && ((SI < *Start) || (SI > *End)))
224  continue;
225 
226  NumInstr++;
227  if (MI->isIdentityCopy() || MI->isImplicitDef())
228  continue;
229  if (!Visited.insert(MI).second)
230  continue;
231 
232  // For terminators that produce values, ask the backend if the register is
233  // not spillable.
234  if (TII.isUnspillableTerminator(MI) && MI->definesRegister(LI.reg())) {
235  LI.markNotSpillable();
236  return -1.0f;
237  }
238 
239  float Weight = 1.0f;
240  if (IsSpillable) {
241  // Get loop info for mi.
242  if (MI->getParent() != MBB) {
243  MBB = MI->getParent();
244  Loop = Loops.getLoopFor(MBB);
245  IsExiting = Loop ? Loop->isLoopExiting(MBB) : false;
246  }
247 
248  // Calculate instr weight.
249  bool Reads, Writes;
250  std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg());
251  Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI);
252 
253  // Give extra weight to what looks like a loop induction variable update.
254  if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB))
255  Weight *= 3;
256 
257  TotalWeight += Weight;
258  }
259 
260  // Get allocation hints from copies.
261  if (!MI->isCopy())
262  continue;
263  Register HintReg = copyHint(MI, LI.reg(), TRI, MRI);
264  if (!HintReg)
265  continue;
266  // Force hweight onto the stack so that x86 doesn't add hidden precision,
267  // making the comparison incorrectly pass (i.e., 1 > 1 == true??).
268  //
269  // FIXME: we probably shouldn't use floats at all.
270  volatile float HWeight = Hint[HintReg] += Weight;
271  if (HintReg.isVirtual() || MRI.isAllocatable(HintReg))
272  CopyHints.insert(CopyHint(HintReg, HWeight));
273  }
274 
275  // Pass all the sorted copy hints to mri.
276  if (ShouldUpdateLI && CopyHints.size()) {
277  // Remove a generic hint if previously added by target.
278  if (TargetHint.first == 0 && TargetHint.second)
279  MRI.clearSimpleHint(LI.reg());
280 
281  SmallSet<Register, 4> HintedRegs;
282  for (const auto &Hint : CopyHints) {
283  if (!HintedRegs.insert(Hint.Reg).second ||
284  (TargetHint.first != 0 && Hint.Reg == TargetHint.second))
285  // Don't add the same reg twice or the target-type hint again.
286  continue;
287  MRI.addRegAllocationHint(LI.reg(), Hint.Reg);
288  }
289 
290  // Weakly boost the spill weight of hinted registers.
291  TotalWeight *= 1.01F;
292  }
293 
294  // If the live interval was already unspillable, leave it that way.
295  if (!IsSpillable)
296  return -1.0;
297 
298  // Mark li as unspillable if all live ranges are tiny and the interval
299  // is not live at any reg mask. If the interval is live at a reg mask
300  // spilling may be required. If li is live as use in statepoint instruction
301  // spilling may be required due to if we mark interval with use in statepoint
302  // as not spillable we are risky to end up with no register to allocate.
303  // At the same time STATEPOINT instruction is perfectly fine to have this
304  // operand on stack, so spilling such interval and folding its load from stack
305  // into instruction itself makes perfect sense.
306  if (ShouldUpdateLI && LI.isZeroLength(LIS.getSlotIndexes()) &&
307  !LI.isLiveAtIndexes(LIS.getRegMaskSlots()) &&
308  !isLiveAtStatepointVarArg(LI)) {
309  LI.markNotSpillable();
310  return -1.0;
311  }
312 
313  // If all of the definitions of the interval are re-materializable,
314  // it is a preferred candidate for spilling.
315  // FIXME: this gets much more complicated once we support non-trivial
316  // re-materialization.
317  if (isRematerializable(LI, LIS, VRM, *MF.getSubtarget().getInstrInfo()))
318  TotalWeight *= 0.5F;
319 
320  if (IsLocalSplitArtifact)
321  return normalize(TotalWeight, Start->distance(*End), NumInstr);
322  return normalize(TotalWeight, LI.getSize(), NumInstr);
323 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::VirtRegAuxInfo::isRematerializable
static bool isRematerializable(const LiveInterval &LI, const LiveIntervals &LIS, const VirtRegMap &VRM, const TargetInstrInfo &TII)
Determine if all values in LI are rematerializable.
Definition: CalcSpillWeights.cpp:80
llvm::LiveIntervals::getSlotIndexes
SlotIndexes * getSlotIndexes() const
Definition: LiveIntervals.h:209
llvm::MachineLoopInfo::getLoopFor
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
Definition: MachineLoopInfo.h:126
llvm::LiveRange::isZeroLength
bool isZeroLength(SlotIndexes *Indexes) const
Returns true if the live range is zero length, i.e.
Definition: LiveInterval.h:586
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::VirtRegAuxInfo::copyHint
static Register copyHint(const MachineInstr *MI, unsigned Reg, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI)
Return the preferred allocation register for reg, given a COPY instruction.
Definition: CalcSpillWeights.cpp:46
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:546
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::LiveInterval::isSpillable
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:819
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:266
llvm::VirtRegMap::getOriginal
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:169
llvm::LiveIntervals::getInstructionFromIndex
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
Definition: LiveIntervals.h:225
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::defusechain_instr_iterator
defusechain_iterator - This class provides iterator support for machine operands in the function that...
Definition: MachineRegisterInfo.h:277
llvm::VirtRegAuxInfo::normalize
virtual float normalize(float UseDefFreq, unsigned Size, unsigned NumInstr)
Weight normalization function.
Definition: CalcSpillWeights.h:100
llvm::VirtRegAuxInfo::calculateSpillWeightsAndHints
void calculateSpillWeightsAndHints()
Compute spill weights and allocation hints for all virtual register live intervals.
Definition: CalcSpillWeights.cpp:32
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::VNInfo::def
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::LiveIntervals::getRegMaskSlots
ArrayRef< SlotIndex > getRegMaskSlots() const
Returns a sorted array of slot indices of all instructions with register mask operands.
Definition: LiveIntervals.h:345
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:770
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::LiveRange::vni_begin
vni_iterator vni_begin()
Definition: LiveInterval.h:224
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
llvm::VirtRegAuxInfo::calculateSpillWeightAndHint
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
Definition: CalcSpillWeights.cpp:140
llvm::LiveQueryResult
Result of a LiveRange query.
Definition: LiveInterval.h:90
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::LiveIntervals::getMBBFromIndex
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
Definition: LiveIntervals.h:249
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::LiveIntervals::getInstructionIndex
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
Definition: LiveIntervals.h:220
MachineRegisterInfo.h
llvm::LiveRange::isLiveAtIndexes
bool isLiveAtIndexes(ArrayRef< SlotIndex > Slots) const
Definition: LiveInterval.cpp:800
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:97
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
MachineLoopInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LiveInterval::getSize
unsigned getSize() const
getSize - Returns the sum of sizes of all the LiveRange's.
Definition: LiveInterval.cpp:955
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::LiveIntervals::isLiveOutOfMBB
bool isLiveOutOfMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
Definition: LiveIntervals.h:244
llvm::MachineRegisterInfo::reg_instr_nodbg_end
static reg_instr_nodbg_iterator reg_instr_nodbg_end()
Definition: MachineRegisterInfo.h:357
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
SmallPtrSet.h
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::LiveQueryResult::valueIn
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
Definition: LiveInterval.h:105
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::VirtRegMap::getRegInfo
MachineRegisterInfo & getRegInfo() const
Definition: VirtRegMap.h:92
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
LiveIntervals.h
VirtRegMap.h
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:601
llvm::DenseMap
Definition: DenseMap.h:714
llvm::operator<
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:339
llvm::MachineRegisterInfo::reg_instr_nodbg_begin
reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:354
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::LiveRange::Query
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::reg_operands
iterator_range< reg_iterator > reg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:294
llvm::MachineRegisterInfo::isAllocatable
bool isAllocatable(MCRegister PhysReg) const
isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...
Definition: MachineRegisterInfo.h:948
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::Register::asMCReg
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
llvm::LiveIntervals::getInterval
LiveInterval & getInterval(Register Reg)
Definition: LiveIntervals.h:112
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1597
TargetSubtargetInfo.h
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
llvm::LiveInterval::setWeight
void setWeight(float Value)
Definition: LiveInterval.h:720
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::VNInfo::isPHIDef
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::VirtRegAuxInfo::weightCalcHelper
float weightCalcHelper(LiveInterval &LI, SlotIndex *Start=nullptr, SlotIndex *End=nullptr)
Helper function for weight calculations.
Definition: CalcSpillWeights.cpp:148
llvm::LiveIntervals::getSpillWeight
static float getSpillWeight(bool isDef, bool isUse, const MachineBlockFrequencyInfo *MBFI, const MachineInstr &MI)
Calculate the spill weight to assign to a single instruction.
Definition: LiveIntervals.cpp:859
StackMaps.h
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::VNInfo
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
llvm::SmallSet::insert
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:178
LiveInterval.h
llvm::MachineRegisterInfo::addRegAllocationHint
void addRegAllocationHint(Register VReg, Register PrefReg)
addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.
Definition: MachineRegisterInfo.h:787
llvm::LiveInterval::markNotSpillable
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:822
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
MachineOperand.h
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1134
llvm::LoopBase::isLoopExiting
bool isLoopExiting(const BlockT *BB) const
True if terminator in the block can branch to another block that is outside of the current loop.
Definition: LoopInfo.h:241
llvm::VNInfo::isUnused
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
CalcSpillWeights.h
llvm::MachineRegisterInfo::clearSimpleHint
void clearSimpleHint(Register VReg)
Definition: MachineRegisterInfo.h:798
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:385
raw_ostream.h
llvm::LiveRange::vni_end
vni_iterator vni_end()
Definition: LiveInterval.h:225
llvm::LiveRange::const_vni_iterator
VNInfoList::const_iterator const_vni_iterator
Definition: LiveInterval.h:222
MachineFunction.h
TargetRegisterInfo.h
Debug.h
llvm::MachineRegisterInfo::getRegAllocationHint
std::pair< Register, Register > getRegAllocationHint(Register VReg) const
getRegAllocationHint - Return the register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:808
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365