LLVM  13.0.0git
InstructionSelect.cpp
Go to the documentation of this file.
1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/ScopeExit.h"
15 #include "llvm/ADT/Twine.h"
30 #include "llvm/Config/config.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
34 #include "llvm/Support/Debug.h"
37 
38 #define DEBUG_TYPE "instruction-select"
39 
40 using namespace llvm;
41 
42 #ifdef LLVM_GISEL_COV_PREFIX
44  CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
45  cl::desc("Record GlobalISel rule coverage files of this "
46  "prefix if instrumentation was generated"));
47 #else
48 static const std::string CoveragePrefix;
49 #endif
50 
51 char InstructionSelect::ID = 0;
53  "Select target instructions out of generic instructions",
54  false, false)
60  "Select target instructions out of generic instructions",
62 
64  : MachineFunctionPass(ID), OptLevel(OL) {}
65 
66 // In order not to crash when calling getAnalysis during testing with -run-pass
67 // we use the default opt level here instead of None, so that the addRequired()
68 // calls are made in getAnalysisUsage().
70  : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Default) {}
71 
74  if (OptLevel != CodeGenOpt::None) {
79  }
82 }
83 
85  // If the ISel pipeline failed, do not bother running that pass.
86  if (MF.getProperties().hasProperty(
88  return false;
89 
90  LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
91 
92  const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
94 
95  CodeGenOpt::Level OldOptLevel = OptLevel;
96  auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
98  : MF.getTarget().getOptLevel();
99 
100  GISelKnownBits *KB = nullptr;
101  if (OptLevel != CodeGenOpt::None) {
102  KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
103  PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
104  if (PSI && PSI->hasProfileSummary())
105  BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
106  }
107 
108  CodeGenCoverage CoverageInfo;
109  assert(ISel && "Cannot work without InstructionSelector");
110  ISel->setupMF(MF, KB, CoverageInfo, PSI, BFI);
111 
112  // An optimization remark emitter. Used to report failures.
113  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
114 
115  // FIXME: There are many other MF/MFI fields we need to initialize.
116 
118 #ifndef NDEBUG
119  // Check that our input is fully legal: we require the function to have the
120  // Legalized property, so it should be.
121  // FIXME: This should be in the MachineVerifier, as the RegBankSelected
122  // property check already is.
124  if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
125  reportGISelFailure(MF, TPC, MORE, "gisel-select",
126  "instruction is not legal", *MI);
127  return false;
128  }
129  // FIXME: We could introduce new blocks and will need to fix the outer loop.
130  // Until then, keep track of the number of blocks to assert that we don't.
131  const size_t NumBlocks = MF.size();
132 #endif
133 
134  for (MachineBasicBlock *MBB : post_order(&MF)) {
135  ISel->CurMBB = MBB;
136  if (MBB->empty())
137  continue;
138 
139  // Select instructions in reverse block order. We permit erasing so have
140  // to resort to manually iterating and recognizing the begin (rend) case.
141  bool ReachedBegin = false;
142  for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
143  !ReachedBegin;) {
144 #ifndef NDEBUG
145  // Keep track of the insertion range for debug printing.
146  const auto AfterIt = std::next(MII);
147 #endif
148  // Select this instruction.
149  MachineInstr &MI = *MII;
150 
151  // And have our iterator point to the next instruction, if there is one.
152  if (MII == Begin)
153  ReachedBegin = true;
154  else
155  --MII;
156 
157  LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
158 
159  // We could have folded this instruction away already, making it dead.
160  // If so, erase it.
161  if (isTriviallyDead(MI, MRI)) {
162  LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
163  MI.eraseFromParentAndMarkDBGValuesForRemoval();
164  continue;
165  }
166 
167  // Eliminate hints.
168  if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
169  Register DstReg = MI.getOperand(0).getReg();
170  Register SrcReg = MI.getOperand(1).getReg();
171 
172  // At this point, the destination register class of the hint may have
173  // been decided.
174  //
175  // Propagate that through to the source register.
176  const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
177  if (DstRC)
178  MRI.setRegClass(SrcReg, DstRC);
179  assert(canReplaceReg(DstReg, SrcReg, MRI) &&
180  "Must be able to replace dst with src!");
181  MI.eraseFromParent();
182  MRI.replaceRegWith(DstReg, SrcReg);
183  continue;
184  }
185 
186  if (!ISel->select(MI)) {
187  // FIXME: It would be nice to dump all inserted instructions. It's
188  // not obvious how, esp. considering select() can insert after MI.
189  reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
190  return false;
191  }
192 
193  // Dump the range of instructions that MI expanded into.
194  LLVM_DEBUG({
195  auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
196  dbgs() << "Into:\n";
197  for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
198  dbgs() << " " << InsertedMI;
199  dbgs() << '\n';
200  });
201  }
202  }
203 
204  for (MachineBasicBlock &MBB : MF) {
205  if (MBB.empty())
206  continue;
207 
208  // Try to find redundant copies b/w vregs of the same register class.
209  bool ReachedBegin = false;
210  for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
211  // Select this instruction.
212  MachineInstr &MI = *MII;
213 
214  // And have our iterator point to the next instruction, if there is one.
215  if (MII == Begin)
216  ReachedBegin = true;
217  else
218  --MII;
219  if (MI.getOpcode() != TargetOpcode::COPY)
220  continue;
221  Register SrcReg = MI.getOperand(1).getReg();
222  Register DstReg = MI.getOperand(0).getReg();
223  if (Register::isVirtualRegister(SrcReg) &&
224  Register::isVirtualRegister(DstReg)) {
225  auto SrcRC = MRI.getRegClass(SrcReg);
226  auto DstRC = MRI.getRegClass(DstReg);
227  if (SrcRC == DstRC) {
228  MRI.replaceRegWith(DstReg, SrcReg);
229  MI.eraseFromParent();
230  }
231  }
232  }
233  }
234 
235 #ifndef NDEBUG
236  const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
237  // Now that selection is complete, there are no more generic vregs. Verify
238  // that the size of the now-constrained vreg is unchanged and that it has a
239  // register class.
240  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
241  unsigned VReg = Register::index2VirtReg(I);
242 
243  MachineInstr *MI = nullptr;
244  if (!MRI.def_empty(VReg))
245  MI = &*MRI.def_instr_begin(VReg);
246  else if (!MRI.use_empty(VReg))
247  MI = &*MRI.use_instr_begin(VReg);
248  if (!MI)
249  continue;
250 
251  const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
252  if (!RC) {
253  reportGISelFailure(MF, TPC, MORE, "gisel-select",
254  "VReg has no regclass after selection", *MI);
255  return false;
256  }
257 
258  const LLT Ty = MRI.getType(VReg);
259  if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
261  MF, TPC, MORE, "gisel-select",
262  "VReg's low-level type and register class have different sizes", *MI);
263  return false;
264  }
265  }
266 
267  if (MF.size() != NumBlocks) {
268  MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
269  MF.getFunction().getSubprogram(),
270  /*MBB=*/nullptr);
271  R << "inserting blocks is not supported yet";
272  reportGISelFailure(MF, TPC, MORE, R);
273  return false;
274  }
275 #endif
276  // Determine if there are any calls in this machine function. Ported from
277  // SelectionDAG.
278  MachineFrameInfo &MFI = MF.getFrameInfo();
279  for (const auto &MBB : MF) {
280  if (MFI.hasCalls() && MF.hasInlineAsm())
281  break;
282 
283  for (const auto &MI : MBB) {
284  if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
285  MFI.setHasCalls(true);
286  if (MI.isInlineAsm())
287  MF.setHasInlineAsm(true);
288  }
289  }
290 
291  // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
292  auto &TLI = *MF.getSubtarget().getTargetLowering();
293  TLI.finalizeLowering(MF);
294 
295  LLVM_DEBUG({
296  dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
297  for (auto RuleID : CoverageInfo.covered())
298  dbgs() << " id" << RuleID;
299  dbgs() << "\n\n";
300  });
301  CoverageInfo.emit(CoveragePrefix,
302  TLI.getTargetMachine().getTarget().getBackendName());
303 
304  // If we successfully selected the function nothing is going to use the vreg
305  // types after us (otherwise MIRPrinter would need them). Make sure the types
306  // disappear.
308 
309  // FIXME: Should we accurately track changes?
310  return true;
311 }
llvm::InstructionSelect::InstructionSelect
InstructionSelect()
Definition: InstructionSelect.cpp:69
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::MachineFunctionProperties::hasProperty
bool hasProperty(Property P) const
Definition: MachineFunction.h:162
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::InstructionSelect::OptLevel
CodeGenOpt::Level OptLevel
Definition: InstructionSelect.h:59
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:700
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::isPreISelGenericOptimizationHint
bool isPreISelGenericOptimizationHint(unsigned Opcode)
Definition: TargetOpcodes.h:42
llvm::ProfileSummaryInfo::hasProfileSummary
bool hasProfileSummary() const
Returns true if profile summary is available.
Definition: ProfileSummaryInfo.h:71
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:397
llvm::InstructionSelect::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: InstructionSelect.cpp:84
GISelKnownBits.h
LazyBlockFrequencyInfo.h
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:144
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::InstructionSelector::setupMF
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
Definition: InstructionSelector.h:447
llvm::DisableGISelLegalityCheck
cl::opt< bool > DisableGISelLegalityCheck
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
Definition: LazyBlockFrequencyInfo.cpp:62
TargetInstrInfo.h
InstructionSelect.h
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:90
llvm::MachineRegisterInfo::getNumVirtRegs
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Definition: MachineRegisterInfo.h:757
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:741
llvm::Register::index2VirtReg
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
LegalizerInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::CodeGenCoverage::covered
iterator_range< const_covered_iterator > covered() const
Definition: CodeGenCoverage.cpp:41
INITIALIZE_PASS_END
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
Definition: RegBankSelect.cpp:69
llvm::CodeGenCoverage::emit
bool emit(StringRef FilePrefix, StringRef BackendName) const
Definition: CodeGenCoverage.cpp:78
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
MachineRegisterInfo.h
llvm::LazyBlockFrequencyInfoPass
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
Definition: LazyBlockFrequencyInfo.h:100
llvm::TargetSubtargetInfo::getInstructionSelector
virtual InstructionSelector * getInstructionSelector() const
Definition: TargetSubtargetInfo.h:110
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
CommandLine.h
TargetLowering.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::GISelKnownBitsAnalysis
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
Definition: GISelKnownBits.h:113
TargetMachine.h
Constants.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
Twine.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
Utils.h
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:646
false
Definition: StackSlotColoring.cpp:142
llvm::MachineFunction::size
unsigned size() const
Definition: MachineFunction.h:747
llvm::make_scope_exit
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:58
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::machineFunctionIsIllegal
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
Definition: LegalizerInfo.cpp:739
llvm::MachineRegisterInfo::clearVirtRegTypes
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
Definition: MachineRegisterInfo.cpp:199
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::def_empty
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
Definition: MachineRegisterInfo.h:426
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::cl::opt
Definition: CommandLine.h:1419
llvm::instructions
inst_range instructions(Function *F)
Definition: InstIterator.h:133
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:418
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
ProfileSummaryInfo.h
llvm::MachineOptimizationRemarkMissed
Diagnostic information for missed-optimization remarks.
Definition: MachineOptimizationRemarkEmitter.h:82
llvm::MachineRegisterInfo::use_instr_begin
use_instr_iterator use_instr_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:477
CoveragePrefix
static const std::string CoveragePrefix
Definition: InstructionSelect.cpp:48
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::InstructionSelect::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelect.h:56
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::ProfileSummaryInfoWrapperPass
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
Definition: ProfileSummaryInfo.h:188
TargetPassConfig.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:522
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:194
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
DEBUG_TYPE
#define DEBUG_TYPE
Definition: InstructionSelect.cpp:38
llvm::MachineFrameInfo::setHasCalls
void setHasCalls(bool V)
Definition: MachineFrameInfo.h:603
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
TargetSubtargetInfo.h
llvm::InstructionSelect::ID
static char ID
Definition: InstructionSelect.h:33
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
BlockFrequencyInfo.h
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::InstructionSelect::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelect.h:57
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:602
llvm::MachineRegisterInfo::replaceRegWith
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Definition: MachineRegisterInfo.cpp:380
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunctionProperties::Property::FailedISel
@ FailedISel
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
MachineFrameInfo.h
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:180
llvm::post_order
iterator_range< po_iterator< T > > post_order(const T &G)
Definition: PostOrderIterator.h:188
Function.h
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:250
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
PostOrderIterator.h
llvm::InstructionSelect::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: InstructionSelect.cpp:72
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::InstructionSelector::CurMBB
MachineBasicBlock * CurMBB
Definition: InstructionSelector.h:440
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
ScopeExit.h
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::cl::desc
Definition: CommandLine.h:411
TargetRegistry.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
of
Add support for conditional and other related patterns Instead of
Definition: README.txt:134
llvm::InstructionSelector::select
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:40