LLVM 24.0.0git
InstructionSelect.cpp
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1//===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the InstructionSelect class.
10//===----------------------------------------------------------------------===//
11
14#include "llvm/ADT/ScopeExit.h"
15#include "llvm/ADT/SetVector.h"
33#include "llvm/Config/config.h"
34#include "llvm/IR/Analysis.h"
35#include "llvm/IR/Function.h"
39#include "llvm/Support/Debug.h"
43
44#define DEBUG_TYPE "instruction-select"
45
46using namespace llvm;
47
48DEBUG_COUNTER(GlobalISelCounter, "globalisel",
49 "Controls whether to select function with GlobalISel");
50
51#ifdef LLVM_GISEL_COV_PREFIX
53 CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
54 cl::desc("Record GlobalISel rule coverage files of this "
55 "prefix if instrumentation was generated"));
56#else
57static const std::string CoveragePrefix;
58#endif
59
62 "Select target instructions out of generic instructions",
63 false, false)
69 "Select target instructions out of generic instructions",
71
77
79 bool RequireRegBankSelection)
80 : OptLevel(OL), RequireRegBankSelection(RequireRegBankSelection) {}
81
84
85/// This class observes instruction insertions/removals.
86/// InstructionSelect stores an iterator of the instruction prior to the one
87/// that is currently being selected to determine which instruction to select
88/// next. Previously this meant that selecting multiple instructions at once was
89/// illegal behavior due to potential invalidation of this iterator. This is
90/// a non-obvious limitation for selector implementers. Therefore, to allow
91/// deletion of arbitrary instructions, we detect this case and continue
92/// selection with the predecessor of the deleted instruction.
94#ifndef NDEBUG
96#endif
97public:
99
100 void changingInstr(MachineInstr &MI) override {
101 llvm_unreachable("InstructionSelect does not track changed instructions!");
102 }
103 void changedInstr(MachineInstr &MI) override {
104 llvm_unreachable("InstructionSelect does not track changed instructions!");
105 }
106
107 void createdInstr(MachineInstr &MI) override {
108 LLVM_DEBUG(dbgs() << "Creating: " << MI; CreatedInstrs.insert(&MI));
109 }
110
111 void erasingInstr(MachineInstr &MI) override {
112 LLVM_DEBUG(dbgs() << "Erasing: " << MI; CreatedInstrs.remove(&MI));
113 if (MII.getInstrIterator().getNodePtr() == &MI) {
114 // If the iterator points to the MI that will be erased (i.e. the MI prior
115 // to the MI that is currently being selected), the iterator would be
116 // invalidated. Continue selection with its predecessor.
117 ++MII;
118 LLVM_DEBUG(dbgs() << "Instruction removal updated iterator.\n");
119 }
120 }
121
123 LLVM_DEBUG({
124 if (CreatedInstrs.empty()) {
125 dbgs() << "Created no instructions.\n";
126 } else {
127 dbgs() << "Created:\n";
128 for (const auto *MI : CreatedInstrs) {
129 dbgs() << " " << *MI;
130 }
131 CreatedInstrs.clear();
132 }
133 });
134 }
135};
136
149
153 function_ref<BlockFrequencyInfo *()> GetBFI) {
154 // If the ISel pipeline failed, do not bother running that pass.
155 if (MF.getProperties().hasFailedISel())
156 return false;
157
159
160 // FIXME: Properly override OptLevel in TargetMachine. See OptLevelChanger
161 CodeGenOptLevel OldOptLevel = OptLevel;
162 llvm::scope_exit RestoreOptLevel([=]() { OptLevel = OldOptLevel; });
164 : MF.getTarget().getOptLevel();
165
166 VT = GetVT();
168 PSI = GetPSI();
169 if (PSI && PSI->hasProfileSummary())
170 BFI = GetBFI();
171 }
172
173 return selectMachineFunction(MF);
174}
175
177 LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
178 assert(ISel && "Cannot work without InstructionSelector");
179
180 CodeGenCoverage CoverageInfo;
181 ISel->setupMF(MF, VT, &CoverageInfo, PSI, BFI);
182
183 // An optimization remark emitter. Used to report failures.
184 MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
185 ISel->MORE = &MORE;
186
187 // FIXME: There are many other MF/MFI fields we need to initialize.
188
190#ifndef NDEBUG
191 // Check that our input is fully legal: we require the function to have the
192 // Legalized property, so it should be.
193 // FIXME: This should be in the MachineVerifier, as the RegBankSelected
194 // property check already is.
196 if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
197 reportGISelFailure(MF, MORE, "gisel-select", "instruction is not legal",
198 *MI);
199 return false;
200 }
201 // NumBlocks is an invariant to ensure the number of blocks doesn't change.
202 const size_t NumBlocks = MF.size();
203#endif
204 // Keep track of selected blocks, so we can delete unreachable ones later.
205 DenseSet<MachineBasicBlock *> SelectedBlocks;
206
207 {
208 // Observe IR insertions and removals during selection.
209 // We only install a MachineFunction::Delegate instead of a
210 // GISelChangeObserver, because we do not want notifications about changed
211 // instructions. This prevents significant compile-time regressions from
212 // e.g. constrainOperandRegClass().
213 GISelObserverWrapper AllObservers;
214 MIIteratorMaintainer MIIMaintainer;
215 AllObservers.addObserver(&MIIMaintainer);
216 RAIIDelegateInstaller DelInstaller(MF, &AllObservers);
217 ISel->AllObservers = &AllObservers;
218
219 for (MachineBasicBlock *MBB : post_order(&MF)) {
220 ISel->CurMBB = MBB;
221 SelectedBlocks.insert(MBB);
222
223 // Select instructions in reverse block order.
224 MIIMaintainer.MII = MBB->rbegin();
225 for (auto End = MBB->rend(); MIIMaintainer.MII != End;) {
226 MachineInstr &MI = *MIIMaintainer.MII;
227 // Increment early to skip instructions inserted by select().
228 ++MIIMaintainer.MII;
229
230 LLVM_DEBUG(dbgs() << "\nSelect: " << MI);
231 if (!selectInstr(MI)) {
232 LLVM_DEBUG(dbgs() << "Selection failed!\n";
233 MIIMaintainer.reportFullyCreatedInstrs());
234 reportGISelFailure(MF, MORE, "gisel-select", "cannot select", MI);
235 return false;
236 }
237 LLVM_DEBUG(MIIMaintainer.reportFullyCreatedInstrs());
238 }
239 }
240 }
241
242 for (MachineBasicBlock &MBB : MF) {
243 if (MBB.empty())
244 continue;
245
246 if (!SelectedBlocks.contains(&MBB)) {
247 // This is an unreachable block and therefore hasn't been selected, since
248 // the main selection loop above uses a postorder block traversal.
249 // We delete all the instructions in this block since it's unreachable.
250 MBB.clear();
251 // Don't delete the block in case the block has it's address taken or is
252 // still being referenced by a phi somewhere.
253 continue;
254 }
255 // Try to find redundant copies b/w vregs of the same register class.
256 for (auto MII = MBB.rbegin(), End = MBB.rend(); MII != End;) {
257 MachineInstr &MI = *MII;
258 ++MII;
259
260 if (MI.getOpcode() != TargetOpcode::COPY)
261 continue;
262 Register SrcReg = MI.getOperand(1).getReg();
263 Register DstReg = MI.getOperand(0).getReg();
264 unsigned SrcSubIdx = MI.getOperand(1).getSubReg();
265 if (!SrcReg.isVirtual() || !DstReg.isVirtual() || SrcSubIdx)
266 continue;
267
268 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
269 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
270 if (SrcRC == DstRC) {
271 MRI.replaceRegWith(DstReg, SrcReg);
272 MI.eraseFromParent();
273 }
274 }
275 }
276
277#ifndef NDEBUG
279 // Now that selection is complete, there are no more generic vregs. Verify
280 // that the size of the now-constrained vreg is unchanged and that it has a
281 // register class.
282 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
284
285 MachineInstr *MI = nullptr;
286 if (!MRI.def_empty(VReg))
287 MI = &*MRI.def_instr_begin(VReg);
288 else if (!MRI.use_empty(VReg)) {
289 MI = &*MRI.use_instr_begin(VReg);
290 // Debug value instruction is permitted to use undefined vregs.
291 if (MI->isDebugValue())
292 continue;
293 }
294 if (!MI)
295 continue;
296
297 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
298 if (!RC) {
299 reportGISelFailure(MF, MORE, "gisel-select",
300 "VReg has no regclass after selection", *MI);
301 return false;
302 }
303
304 const LLT Ty = MRI.getType(VReg);
305 if (Ty.isValid() &&
306 TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
308 MF, MORE, "gisel-select",
309 "VReg's low-level type and register class have different sizes", *MI);
310 return false;
311 }
312 }
313
314 if (MF.size() != NumBlocks) {
315 MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
317 /*MBB=*/nullptr);
318 R << "inserting blocks is not supported yet";
319 reportGISelFailure(MF, MORE, R);
320 return false;
321 }
322#endif
323
324 if (!DebugCounter::shouldExecute(GlobalISelCounter)) {
325 dbgs() << "Falling back for function " << MF.getName() << "\n";
326 MF.getProperties().setFailedISel();
327 return false;
328 }
329
330 // Determine if there are any calls in this machine function. Ported from
331 // SelectionDAG.
332 MachineFrameInfo &MFI = MF.getFrameInfo();
333 for (const auto &MBB : MF) {
334 if (MFI.hasCalls() && MF.hasInlineAsm())
335 break;
336
337 for (const auto &MI : MBB) {
338 if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
339 MFI.setHasCalls(true);
340 if (MI.isInlineAsm())
341 MF.setHasInlineAsm(true);
342 }
343 }
344
345 // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
346 auto &TLI = *MF.getSubtarget().getTargetLowering();
347 TLI.finalizeLowering(MF);
348
349 LLVM_DEBUG({
350 dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
351 for (auto RuleID : CoverageInfo.covered())
352 dbgs() << " id" << RuleID;
353 dbgs() << "\n\n";
354 });
355 CoverageInfo.emit(CoveragePrefix,
356 TLI.getTargetMachine().getTarget().getBackendName());
357
358 // If we successfully selected the function nothing is going to use the vreg
359 // types after us (otherwise MIRPrinter would need them). Make sure the types
360 // disappear.
361 MRI.clearVirtRegTypes();
362
363 // FIXME: Should we accurately track changes?
364 return true;
365}
366
368 MachineRegisterInfo &MRI = ISel->MF->getRegInfo();
369
370 // We could have folded this instruction away already, making it dead.
371 // If so, erase it.
372 if (isTriviallyDead(MI, MRI)) {
373 LLVM_DEBUG(dbgs() << "Is dead.\n");
374 salvageDebugInfo(MRI, MI);
375 MI.eraseFromParent();
376 return true;
377 }
378
379 // Eliminate hints or G_CONSTANT_FOLD_BARRIER.
380 if (isPreISelGenericOptimizationHint(MI.getOpcode()) ||
381 MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
382 auto [DstReg, SrcReg] = MI.getFirst2Regs();
383
384 // At this point, the destination register class of the op may have
385 // been decided.
386 //
387 // Propagate that through to the source register.
388 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
389 const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
390 if (DstRC && SrcRC)
391 MRI.constrainRegClass(SrcReg, DstRC);
392 else if (DstRC)
393 MRI.setRegClass(SrcReg, DstRC);
394 MI.eraseFromParent();
395 MRI.replaceRegWith(DstReg, SrcReg);
396 return true;
397 }
398
399 if (MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
400 MI.eraseFromParent();
401 return true;
402 }
403
404 return ISel->select(MI);
405}
406
409 return Impl.runOnMachineFunction(
410 MF,
411 [&]() {
413 },
414 [&]() { return &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI(); },
415 [&]() { return &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI(); });
416}
417
421 MFPropsModifier _(*this, MF);
422 InstructionSelectImpl Impl(OptLevel);
423 bool Changed = Impl.runOnMachineFunction(
424 MF, [&]() { return &MFAM.getResult<GISelValueTrackingAnalysis>(MF); },
425 [&]() {
426 ProfileSummaryInfo *PSI =
428 .getCachedResult<ProfileSummaryAnalysis>(
429 *MF.getFunction().getParent());
430 if (!PSI)
431 reportFatalUsageError("instruction-select requires profile-summary");
432 return PSI;
433 },
434 [&]() {
436 .getManager()
437 .getResult<BlockFrequencyAnalysis>(MF.getFunction());
438 });
441}
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock & MBB
This file provides an implementation of debug counters.
#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC)
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
#define DEBUG_TYPE
#define _
IRTranslator LLVM IR MI
static const std::string CoveragePrefix
Interface for Targets to specify which operations they can successfully select and how the others sho...
#define I(x, y, z)
Definition MD5.cpp:57
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
Register const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition PassSupport.h:42
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition PassSupport.h:44
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition PassSupport.h:39
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
This file defines the scope_exit class, which executes user-defined cleanup logic at scope exit.
This file implements a set that has insertion order iteration characteristics.
#define LLVM_DEBUG(...)
Definition Debug.h:119
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
This class observes instruction insertions/removals.
void createdInstr(MachineInstr &MI) override
An instruction has been created and inserted into the function.
void erasingInstr(MachineInstr &MI) override
An instruction is about to be erased.
void changingInstr(MachineInstr &MI) override
This instruction is about to be mutated in some way.
void changedInstr(MachineInstr &MI) override
This instruction was mutated in some way.
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Analysis pass which computes BlockFrequencyInfo.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
LLVM_ABI iterator_range< const_covered_iterator > covered() const
LLVM_ABI bool emit(StringRef FilePrefix, StringRef BackendName) const
static bool shouldExecute(CounterInfo &Counter)
Implements a dense probed hash-table based set.
Definition DenseSet.h:281
DISubprogram * getSubprogram() const
Get the attached subprogram.
bool hasOptNone() const
Do not optimize this function (-O0).
Definition Function.h:685
Abstract class that contains various methods for clients to notify about changes.
Simple wrapper observer that takes several observers, and calls each one for each event.
void addObserver(GISelChangeObserver *O)
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelValueTrackingInfoAnal...
Module * getParent()
Get the module that this global value is contained inside of...
bool selectMachineFunction(MachineFunction &MF)
InstructionSelectImpl(CodeGenOptLevel OL)
InstructionSelector * ISel
bool runOnMachineFunction(MachineFunction &MF, function_ref< GISelValueTracking *()> GetVT, function_ref< ProfileSummaryInfo *()> GetPSI, function_ref< BlockFrequencyInfo *()> GetBFI)
bool selectInstr(MachineInstr &MI)
This pass is responsible for selecting generic machine instructions to target-specific instructions.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
InstructionSelectLegacy(CodeGenOptLevel OL=CodeGenOptLevel::Default, bool RequireRegBankSelection=true, char &PassID=ID)
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
InstructionSelectPass(CodeGenOptLevel OL=CodeGenOptLevel::Default, bool RequireRegBankSelection=true)
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
An RAII based helper class to modify MachineFunctionProperties when running pass.
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Representation of each machine instruction.
Diagnostic information for missed-optimization remarks.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
use_instr_iterator use_instr_begin(Register RegNo) const
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
LLVM_ABI void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A set of analyses that are preserved following a run of a transformation pass.
Definition Analysis.h:112
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
Analysis providing profile information.
A simple RAII based Delegate installer.
Wrapper class representing virtual and physical registers.
Definition Register.h:20
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition Register.h:72
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition Register.h:79
A SetVector that performs no allocations if smaller than a certain size.
Definition SetVector.h:345
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual InstructionSelector * getInstructionSelector() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
virtual const TargetLowering * getTargetLowering() const
std::pair< iterator, bool > insert(const ValueT &V)
Definition DenseSet.h:209
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
Definition DenseSet.h:182
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition TypeSize.h:223
An efficient, type-erasing, non-owning reference to a callable.
Changed
Pass manager infrastructure for declaring and invalidating analyses.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
OuterAnalysisManagerProxy< ModuleAnalysisManager, MachineFunction > ModuleAnalysisManagerMachineFunctionProxy
Provide the ModuleAnalysisManager to Function proxy.
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition Utils.cpp:1675
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
bool isPreISelGenericOptimizationHint(unsigned Opcode)
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI cl::opt< bool > DisableGISelLegalityCheck
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:209
LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition Utils.cpp:261
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
CodeGenOptLevel
Code generation optimization level.
Definition CodeGen.h:149
auto post_order(const T &G)
Post-order traversal of a graph.
LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition Utils.cpp:1137
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition Utils.cpp:224
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
Definition Error.cpp:177
#define MORE()
Definition regcomp.c:246