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27 #include "llvm/Config/config.h"
35 #define DEBUG_TYPE "instruction-select"
39 #ifdef LLVM_GISEL_COV_PREFIX
42 cl::desc(
"Record GlobalISel rule coverage files of this "
43 "prefix if instrumentation was generated"));
50 "Select target instructions out of generic instructions",
98 GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
100 PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
102 BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
106 assert(ISel &&
"Cannot work without InstructionSelector");
123 "instruction is not legal", *
MI);
128 const size_t NumBlocks = MF.
size();
141 bool ReachedBegin =
false;
146 const auto AfterIt = std::next(MII);
163 MI.eraseFromParent();
180 "Must be able to replace dst with src!");
181 MI.eraseFromParent();
195 auto InsertedBegin = ReachedBegin ?
MBB->
begin() : std::next(MII);
197 for (
auto &InsertedMI :
make_range(InsertedBegin, AfterIt))
198 dbgs() <<
" " << InsertedMI;
218 bool ReachedBegin =
false;
219 for (
auto MII = std::prev(
MBB.
end()), Begin =
MBB.
begin(); !ReachedBegin;) {
228 if (
MI.getOpcode() != TargetOpcode::COPY)
236 if (SrcRC == DstRC) {
238 MI.eraseFromParent();
258 if (
MI->isDebugValue())
267 "VReg has no regclass after selection", *
MI);
274 MF, TPC,
MORE,
"gisel-select",
275 "VReg's low-level type and register class have different sizes", *
MI);
280 if (MF.size() != NumBlocks) {
282 MF.getFunction().getSubprogram(),
284 R <<
"inserting blocks is not supported yet";
292 for (
const auto &
MBB : MF) {
293 if (MFI.
hasCalls() && MF.hasInlineAsm())
296 for (
const auto &
MI :
MBB) {
297 if ((
MI.isCall() && !
MI.isReturn()) ||
MI.isStackAligningInlineAsm())
299 if (
MI.isInlineAsm())
300 MF.setHasInlineAsm(
true);
305 auto &TLI = *MF.getSubtarget().getTargetLowering();
306 TLI.finalizeLowering(MF);
309 dbgs() <<
"Rules covered by selecting function: " << MF.getName() <<
":";
310 for (
auto RuleID : CoverageInfo.
covered())
311 dbgs() <<
" id" << RuleID;
315 TLI.getTargetMachine().getTarget().getBackendName());
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
bool hasProperty(Property P) const
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
CodeGenOpt::Level OptLevel
bool hasOptNone() const
Do not optimize this function (-O0).
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool hasProfileSummary() const
Returns true if profile summary is available.
def_instr_iterator def_instr_begin(Register RegNo) const
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB, CodeGenCoverage &covinfo, ProfileSummaryInfo *psi, BlockFrequencyInfo *bfi)
Setup per-MF selector state.
cl::opt< bool > DisableGISelLegalityCheck
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
std::pair< iterator, bool > insert(const ValueT &V)
unsigned const TargetRegisterInfo * TRI
iterator_range< const_covered_iterator > covered() const
bool emit(StringRef FilePrefix, StringRef BackendName) const
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE, "Select target instructions out of generic instructions", false, false) INITIALIZE_PASS_END(InstructionSelect
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
virtual InstructionSelector * getInstructionSelector() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelKnownBitsInfoAnalysis...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Represent the analysis usage information of a pass.
const MachineFunctionProperties & getProperties() const
Get the function properties.
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
This pass is responsible for selecting generic machine instructions to target-specific instructions.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Target-Independent Code Generator Pass Configuration Options.
Implements a dense probed hash-table based set.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
inst_range instructions(Function *F)
Provides the logic to select generic machine instructions.
Representation of each machine instruction.
use_instr_iterator use_instr_begin(Register RegNo) const
static const std::string CoveragePrefix
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
initializer< Ty > init(const Ty &Val)
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool hasCalls() const
Return true if the current function has any function calls.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
Function & getFunction()
Return the LLVM function that this machine code represents.
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
iterator_range< po_iterator< T > > post_order(const T &G)
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
MachineBasicBlock * CurMBB
AnalysisUsage & addRequired()
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Add support for conditional and other related patterns Instead of
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.