33#include "llvm/Config/config.h"
44#define DEBUG_TYPE "instruction-select"
49 "Controls whether to select function with GlobalISel");
51#ifdef LLVM_GISEL_COV_PREFIX
54 cl::desc(
"Record GlobalISel rule coverage files of this "
55 "prefix if instrumentation was generated"));
62 "Select target instructions out of generic instructions",
69 "Select target instructions out of generic instructions",
79 bool RequireRegBankSelection)
80 : OptLevel(OL), RequireRegBankSelection(RequireRegBankSelection) {}
113 if (
MII.getInstrIterator().getNodePtr() == &
MI) {
124 if (CreatedInstrs.empty()) {
125 dbgs() <<
"Created no instructions.\n";
127 dbgs() <<
"Created:\n";
128 for (
const auto *
MI : CreatedInstrs) {
131 CreatedInstrs.clear();
169 if (
PSI &&
PSI->hasProfileSummary())
178 assert(
ISel &&
"Cannot work without InstructionSelector");
202 const size_t NumBlocks = MF.
size();
217 ISel->AllObservers = &AllObservers;
224 MIIMaintainer.
MII =
MBB->rbegin();
225 for (
auto End =
MBB->rend(); MIIMaintainer.
MII != End;) {
256 for (
auto MII =
MBB.rbegin(), End =
MBB.rend(); MII != End;) {
260 if (
MI.getOpcode() != TargetOpcode::COPY)
264 unsigned SrcSubIdx =
MI.getOperand(1).getSubReg();
270 if (SrcRC == DstRC) {
272 MI.eraseFromParent();
291 if (
MI->isDebugValue())
300 "VReg has no regclass after selection", *
MI);
308 MF,
MORE,
"gisel-select",
309 "VReg's low-level type and register class have different sizes", *
MI);
314 if (MF.
size() != NumBlocks) {
318 R <<
"inserting blocks is not supported yet";
325 dbgs() <<
"Falling back for function " << MF.
getName() <<
"\n";
333 for (
const auto &
MBB : MF) {
337 for (
const auto &
MI :
MBB) {
338 if ((
MI.isCall() && !
MI.isReturn()) ||
MI.isStackAligningInlineAsm())
340 if (
MI.isInlineAsm())
350 dbgs() <<
"Rules covered by selecting function: " << MF.
getName() <<
":";
351 for (
auto RuleID : CoverageInfo.
covered())
352 dbgs() <<
" id" << RuleID;
356 TLI.getTargetMachine().getTarget().getBackendName());
375 MI.eraseFromParent();
381 MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
382 auto [DstReg, SrcReg] =
MI.getFirst2Regs();
394 MI.eraseFromParent();
399 if (
MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
400 MI.eraseFromParent();
409 return Impl.runOnMachineFunction(
423 bool Changed = Impl.runOnMachineFunction(
428 .getCachedResult<ProfileSummaryAnalysis>(
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file provides an implementation of debug counters.
#define DEBUG_COUNTER(VARNAME, COUNTERNAME, DESC)
This contains common code to allow clients to notify changes to machine instr.
Provides analysis for querying information about KnownBits during GISel passes.
static const std::string CoveragePrefix
Interface for Targets to specify which operations they can successfully select and how the others sho...
Register const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
This file defines the scope_exit class, which executes user-defined cleanup logic at scope exit.
This file implements a set that has insertion order iteration characteristics.
This file describes how to lower LLVM code to machine code.
Target-Independent Code Generator Pass Configuration Options pass.
This class observes instruction insertions/removals.
MachineBasicBlock::reverse_iterator MII
void createdInstr(MachineInstr &MI) override
An instruction has been created and inserted into the function.
void erasingInstr(MachineInstr &MI) override
An instruction is about to be erased.
void changingInstr(MachineInstr &MI) override
This instruction is about to be mutated in some way.
void changedInstr(MachineInstr &MI) override
This instruction was mutated in some way.
void reportFullyCreatedInstrs()
PassT::Result & getResult(IRUnitT &IR, ExtraArgTs... ExtraArgs)
Get the result of an analysis pass for a given IR unit.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Analysis pass which computes BlockFrequencyInfo.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
LLVM_ABI iterator_range< const_covered_iterator > covered() const
LLVM_ABI bool emit(StringRef FilePrefix, StringRef BackendName) const
static bool shouldExecute(CounterInfo &Counter)
Implements a dense probed hash-table based set.
DISubprogram * getSubprogram() const
Get the attached subprogram.
bool hasOptNone() const
Do not optimize this function (-O0).
Abstract class that contains various methods for clients to notify about changes.
Simple wrapper observer that takes several observers, and calls each one for each event.
void addObserver(GISelChangeObserver *O)
To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelValueTrackingInfoAnal...
Module * getParent()
Get the module that this global value is contained inside of...
bool selectMachineFunction(MachineFunction &MF)
InstructionSelectImpl(CodeGenOptLevel OL)
InstructionSelector * ISel
bool runOnMachineFunction(MachineFunction &MF, function_ref< GISelValueTracking *()> GetVT, function_ref< ProfileSummaryInfo *()> GetPSI, function_ref< BlockFrequencyInfo *()> GetBFI)
bool selectInstr(MachineInstr &MI)
This pass is responsible for selecting generic machine instructions to target-specific instructions.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
InstructionSelectLegacy(CodeGenOptLevel OL=CodeGenOptLevel::Default, bool RequireRegBankSelection=true, char &PassID=ID)
bool RequireRegBankSelection
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
InstructionSelectPass(CodeGenOptLevel OL=CodeGenOptLevel::Default, bool RequireRegBankSelection=true)
This is an alternative analysis pass to BlockFrequencyInfoWrapperPass.
static void getLazyBFIAnalysisUsage(AnalysisUsage &AU)
Helper for client passes to set up the analysis usage on behalf of this pass.
An RAII based helper class to modify MachineFunctionProperties when running pass.
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
MachineFunctionPass(char &ID)
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void setHasInlineAsm(bool B)
Set a flag that indicates that the function contains inline assembly.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool hasInlineAsm() const
Returns true if the function contains any inline assembly.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
use_instr_iterator use_instr_begin(Register RegNo) const
def_instr_iterator def_instr_begin(Register RegNo) const
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
bool def_empty(Register RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
LLVM_ABI void clearVirtRegTypes()
Remove all types associated to virtual registers (after instruction selection and constraining of all...
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A set of analyses that are preserved following a run of a transformation pass.
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
Analysis providing profile information.
A simple RAII based Delegate installer.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A SetVector that performs no allocations if smaller than a certain size.
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Target-Independent Code Generator Pass Configuration Options.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual InstructionSelector * getInstructionSelector() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
virtual const TargetLowering * getTargetLowering() const
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
An efficient, type-erasing, non-owning reference to a callable.
Pass manager infrastructure for declaring and invalidating analyses.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
OuterAnalysisManagerProxy< ModuleAnalysisManager, MachineFunction > ModuleAnalysisManagerMachineFunctionProxy
Provide the ModuleAnalysisManager to Function proxy.
LLVM_ABI void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
bool isPreISelGenericOptimizationHint(unsigned Opcode)
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
LLVM_ABI cl::opt< bool > DisableGISelLegalityCheck
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI void reportGISelFailure(MachineFunction &MF, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
const MachineInstr * machineFunctionIsIllegal(const MachineFunction &MF)
Checks that MIR is fully legal, returns an illegal instruction if it's not, nullptr otherwise.
CodeGenOptLevel
Code generation optimization level.
auto post_order(const T &G)
Post-order traversal of a graph.
LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
LLVM_ABI bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
MCRegisterClass TargetRegisterClass
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.