LLVM  14.0.0git
AArch64StackTaggingPreRA.cpp
Go to the documentation of this file.
1 //===-- AArch64StackTaggingPreRA.cpp --- Stack Tagging for AArch64 -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 
10 #include "AArch64.h"
12 #include "AArch64InstrInfo.h"
14 #include "llvm/ADT/SetVector.h"
15 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Support/Debug.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "aarch64-stack-tagging-pre-ra"
35 
37 
39  "stack-tagging-unchecked-ld-st", cl::Hidden,
41  cl::desc(
42  "Unconditionally apply unchecked-ld-st optimization (even for large "
43  "stack frames, or in the presence of variable sized allocas)."),
44  cl::values(
45  clEnumValN(UncheckedNever, "never", "never apply unchecked-ld-st"),
46  clEnumValN(
47  UncheckedSafe, "safe",
48  "apply unchecked-ld-st when the target is definitely within range"),
49  clEnumValN(UncheckedAlways, "always", "always apply unchecked-ld-st")));
50 
51 static cl::opt<bool>
52  ClFirstSlot("stack-tagging-first-slot-opt", cl::Hidden, cl::init(true),
54  cl::desc("Apply first slot optimization for stack tagging "
55  "(eliminate ADDG Rt, Rn, 0, 0)."));
56 
57 namespace {
58 
59 class AArch64StackTaggingPreRA : public MachineFunctionPass {
60  MachineFunction *MF;
62  MachineFrameInfo *MFI;
64  const AArch64RegisterInfo *TRI;
65  const AArch64InstrInfo *TII;
66 
68 
69 public:
70  static char ID;
71  AArch64StackTaggingPreRA() : MachineFunctionPass(ID) {
73  }
74 
75  bool mayUseUncheckedLoadStore();
76  void uncheckUsesOf(unsigned TaggedReg, int FI);
77  void uncheckLoadsAndStores();
78  Optional<int> findFirstSlotCandidate();
79 
80  bool runOnMachineFunction(MachineFunction &Func) override;
81  StringRef getPassName() const override {
82  return "AArch64 Stack Tagging PreRA";
83  }
84 
85  void getAnalysisUsage(AnalysisUsage &AU) const override {
86  AU.setPreservesCFG();
88  }
89 };
90 } // end anonymous namespace
91 
93 
94 INITIALIZE_PASS_BEGIN(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
95  "AArch64 Stack Tagging PreRA Pass", false, false)
96 INITIALIZE_PASS_END(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra",
97  "AArch64 Stack Tagging PreRA Pass", false, false)
98 
100  return new AArch64StackTaggingPreRA();
101 }
102 
103 static bool isUncheckedLoadOrStoreOpcode(unsigned Opcode) {
104  switch (Opcode) {
105  case AArch64::LDRBBui:
106  case AArch64::LDRHHui:
107  case AArch64::LDRWui:
108  case AArch64::LDRXui:
109 
110  case AArch64::LDRBui:
111  case AArch64::LDRHui:
112  case AArch64::LDRSui:
113  case AArch64::LDRDui:
114  case AArch64::LDRQui:
115 
116  case AArch64::LDRSHWui:
117  case AArch64::LDRSHXui:
118 
119  case AArch64::LDRSBWui:
120  case AArch64::LDRSBXui:
121 
122  case AArch64::LDRSWui:
123 
124  case AArch64::STRBBui:
125  case AArch64::STRHHui:
126  case AArch64::STRWui:
127  case AArch64::STRXui:
128 
129  case AArch64::STRBui:
130  case AArch64::STRHui:
131  case AArch64::STRSui:
132  case AArch64::STRDui:
133  case AArch64::STRQui:
134 
135  case AArch64::LDPWi:
136  case AArch64::LDPXi:
137  case AArch64::LDPSi:
138  case AArch64::LDPDi:
139  case AArch64::LDPQi:
140 
141  case AArch64::LDPSWi:
142 
143  case AArch64::STPWi:
144  case AArch64::STPXi:
145  case AArch64::STPSi:
146  case AArch64::STPDi:
147  case AArch64::STPQi:
148  return true;
149  default:
150  return false;
151  }
152 }
153 
154 bool AArch64StackTaggingPreRA::mayUseUncheckedLoadStore() {
156  return false;
157  else if (ClUncheckedLdSt == UncheckedAlways)
158  return true;
159 
160  // This estimate can be improved if we had harder guarantees about stack frame
161  // layout. With LocalStackAllocation we can estimate SP offset to any
162  // preallocated slot. AArch64FrameLowering::orderFrameObjects could put tagged
163  // objects ahead of non-tagged ones, but that's not always desirable.
164  //
165  // Underestimating SP offset here may require the use of LDG to materialize
166  // the tagged address of the stack slot, along with a scratch register
167  // allocation (post-regalloc!).
168  //
169  // For now we do the safe thing here and require that the entire stack frame
170  // is within range of the shortest of the unchecked instructions.
171  unsigned FrameSize = 0;
172  for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i)
173  FrameSize += MFI->getObjectSize(i);
174  bool EntireFrameReachableFromSP = FrameSize < 0xf00;
175  return !MFI->hasVarSizedObjects() && EntireFrameReachableFromSP;
176 }
177 
178 void AArch64StackTaggingPreRA::uncheckUsesOf(unsigned TaggedReg, int FI) {
179  for (MachineInstr &UseI :
181  if (isUncheckedLoadOrStoreOpcode(UseI.getOpcode())) {
182  // FI operand is always the one before the immediate offset.
183  unsigned OpIdx = TII->getLoadStoreImmIdx(UseI.getOpcode()) - 1;
184  if (UseI.getOperand(OpIdx).isReg() &&
185  UseI.getOperand(OpIdx).getReg() == TaggedReg) {
186  UseI.getOperand(OpIdx).ChangeToFrameIndex(FI);
187  UseI.getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
188  }
189  } else if (UseI.isCopy() &&
190  Register::isVirtualRegister(UseI.getOperand(0).getReg())) {
191  uncheckUsesOf(UseI.getOperand(0).getReg(), FI);
192  }
193  }
194 }
195 
196 void AArch64StackTaggingPreRA::uncheckLoadsAndStores() {
197  for (auto *I : ReTags) {
198  Register TaggedReg = I->getOperand(0).getReg();
199  int FI = I->getOperand(1).getIndex();
200  uncheckUsesOf(TaggedReg, FI);
201  }
202 }
203 
204 namespace {
205 struct SlotWithTag {
206  int FI;
207  int Tag;
208  SlotWithTag(int FI, int Tag) : FI(FI), Tag(Tag) {}
209  explicit SlotWithTag(const MachineInstr &MI)
210  : FI(MI.getOperand(1).getIndex()), Tag(MI.getOperand(4).getImm()) {}
211  bool operator==(const SlotWithTag &Other) const {
212  return FI == Other.FI && Tag == Other.Tag;
213  }
214 };
215 } // namespace
216 
217 namespace llvm {
218 template <> struct DenseMapInfo<SlotWithTag> {
219  static inline SlotWithTag getEmptyKey() { return {-2, -2}; }
220  static inline SlotWithTag getTombstoneKey() { return {-3, -3}; }
221  static unsigned getHashValue(const SlotWithTag &V) {
224  }
225  static bool isEqual(const SlotWithTag &A, const SlotWithTag &B) {
226  return A == B;
227  }
228 };
229 } // namespace llvm
230 
231 static bool isSlotPreAllocated(MachineFrameInfo *MFI, int FI) {
232  return MFI->getUseLocalStackAllocationBlock() &&
233  MFI->isObjectPreAllocated(FI);
234 }
235 
236 // Pin one of the tagged slots to offset 0 from the tagged base pointer.
237 // This would make its address available in a virtual register (IRG's def), as
238 // opposed to requiring an ADDG instruction to materialize. This effectively
239 // eliminates a vreg (by replacing it with direct uses of IRG, which is usually
240 // live almost everywhere anyway), and therefore needs to happen before
241 // regalloc.
242 Optional<int> AArch64StackTaggingPreRA::findFirstSlotCandidate() {
243  // Find the best (FI, Tag) pair to pin to offset 0.
244  // Looking at the possible uses of a tagged address, the advantage of pinning
245  // is:
246  // - COPY to physical register.
247  // Does not matter, this would trade a MOV instruction for an ADDG.
248  // - ST*G matter, but those mostly appear near the function prologue where all
249  // the tagged addresses need to be materialized anyway; also, counting ST*G
250  // uses would overweight large allocas that require more than one ST*G
251  // instruction.
252  // - Load/Store instructions in the address operand do not require a tagged
253  // pointer, so they also do not benefit. These operands have already been
254  // eliminated (see uncheckLoadsAndStores) so all remaining load/store
255  // instructions count.
256  // - Any other instruction may benefit from being pinned to offset 0.
257  LLVM_DEBUG(dbgs() << "AArch64StackTaggingPreRA::findFirstSlotCandidate\n");
258  if (!ClFirstSlot)
259  return None;
260 
261  DenseMap<SlotWithTag, int> RetagScore;
262  SlotWithTag MaxScoreST{-1, -1};
263  int MaxScore = -1;
264  for (auto *I : ReTags) {
265  SlotWithTag ST{*I};
266  if (isSlotPreAllocated(MFI, ST.FI))
267  continue;
268 
269  Register RetagReg = I->getOperand(0).getReg();
270  if (!Register::isVirtualRegister(RetagReg))
271  continue;
272 
273  int Score = 0;
274  SmallVector<Register, 8> WorkList;
275  WorkList.push_back(RetagReg);
276 
277  while (!WorkList.empty()) {
278  Register UseReg = WorkList.pop_back_val();
279  for (auto &UseI : MRI->use_instructions(UseReg)) {
280  unsigned Opcode = UseI.getOpcode();
281  if (Opcode == AArch64::STGOffset || Opcode == AArch64::ST2GOffset ||
282  Opcode == AArch64::STZGOffset || Opcode == AArch64::STZ2GOffset ||
283  Opcode == AArch64::STGPi || Opcode == AArch64::STGloop ||
284  Opcode == AArch64::STZGloop || Opcode == AArch64::STGloop_wback ||
285  Opcode == AArch64::STZGloop_wback)
286  continue;
287  if (UseI.isCopy()) {
288  Register DstReg = UseI.getOperand(0).getReg();
289  if (Register::isVirtualRegister(DstReg))
290  WorkList.push_back(DstReg);
291  continue;
292  }
293  LLVM_DEBUG(dbgs() << "[" << ST.FI << ":" << ST.Tag << "] use of %"
294  << Register::virtReg2Index(UseReg) << " in " << UseI
295  << "\n");
296  Score++;
297  }
298  }
299 
300  int TotalScore = RetagScore[ST] += Score;
301  if (TotalScore > MaxScore ||
302  (TotalScore == MaxScore && ST.FI > MaxScoreST.FI)) {
303  MaxScore = TotalScore;
304  MaxScoreST = ST;
305  }
306  }
307 
308  if (MaxScoreST.FI < 0)
309  return None;
310 
311  // If FI's tag is already 0, we are done.
312  if (MaxScoreST.Tag == 0)
313  return MaxScoreST.FI;
314 
315  // Otherwise, find a random victim pair (FI, Tag) where Tag == 0.
316  SlotWithTag SwapST{-1, -1};
317  for (auto *I : ReTags) {
318  SlotWithTag ST{*I};
319  if (ST.Tag == 0) {
320  SwapST = ST;
321  break;
322  }
323  }
324 
325  // Swap tags between the victim and the highest scoring pair.
326  // If SwapWith is still (-1, -1), that's fine, too - we'll simply take tag for
327  // the highest score slot without changing anything else.
328  for (auto *&I : ReTags) {
329  SlotWithTag ST{*I};
330  MachineOperand &TagOp = I->getOperand(4);
331  if (ST == MaxScoreST) {
332  TagOp.setImm(0);
333  } else if (ST == SwapST) {
334  TagOp.setImm(MaxScoreST.Tag);
335  }
336  }
337  return MaxScoreST.FI;
338 }
339 
340 bool AArch64StackTaggingPreRA::runOnMachineFunction(MachineFunction &Func) {
341  MF = &Func;
342  MRI = &MF->getRegInfo();
343  AFI = MF->getInfo<AArch64FunctionInfo>();
344  TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo());
345  TRI = static_cast<const AArch64RegisterInfo *>(
346  MF->getSubtarget().getRegisterInfo());
347  MFI = &MF->getFrameInfo();
348  ReTags.clear();
349 
350  assert(MRI->isSSA());
351 
352  LLVM_DEBUG(dbgs() << "********** AArch64 Stack Tagging PreRA **********\n"
353  << "********** Function: " << MF->getName() << '\n');
354 
355  SmallSetVector<int, 8> TaggedSlots;
356  for (auto &BB : *MF) {
357  for (auto &I : BB) {
358  if (I.getOpcode() == AArch64::TAGPstack) {
359  ReTags.push_back(&I);
360  int FI = I.getOperand(1).getIndex();
361  TaggedSlots.insert(FI);
362  // There should be no offsets in TAGP yet.
363  assert(I.getOperand(2).getImm() == 0);
364  }
365  }
366  }
367 
368  // Take over from SSP. It does nothing for tagged slots, and should not really
369  // have been enabled in the first place.
370  for (int FI : TaggedSlots)
372 
373  if (ReTags.empty())
374  return false;
375 
376  if (mayUseUncheckedLoadStore())
377  uncheckLoadsAndStores();
378 
379  // Find a slot that is used with zero tag offset, like ADDG #fi, 0.
380  // If the base tagged pointer is set up to the address of this slot,
381  // the ADDG instruction can be eliminated.
382  Optional<int> BaseSlot = findFirstSlotCandidate();
383  if (BaseSlot)
384  AFI->setTaggedBasePointerIndex(*BaseSlot);
385 
386  for (auto *I : ReTags) {
387  int FI = I->getOperand(1).getIndex();
388  int Tag = I->getOperand(4).getImm();
389  Register Base = I->getOperand(3).getReg();
390  if (Tag == 0 && FI == BaseSlot) {
391  BuildMI(*I->getParent(), I, {}, TII->get(AArch64::COPY),
392  I->getOperand(0).getReg())
393  .addReg(Base);
394  I->eraseFromParent();
395  }
396  }
397 
398  return true;
399 }
i
i
Definition: README.txt:29
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
UncheckedNever
@ UncheckedNever
Definition: AArch64StackTaggingPreRA.cpp:36
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
AArch64MachineFunctionInfo.h
AArch64.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
Statistic.h
llvm::MachineFrameInfo::getUseLocalStackAllocationBlock
bool getUseLocalStackAllocationBlock() const
Get whether the local allocation blob should be allocated together or let PEI allocate the locals in ...
Definition: MachineFrameInfo.h:434
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
llvm::MachineFrameInfo::isObjectPreAllocated
bool isObjectPreAllocated(int ObjectIdx) const
Return true if the object was pre-allocated into the local block.
Definition: MachineFrameInfo.h:446
TargetInstrInfo.h
llvm::Optional< int >
llvm::AArch64FunctionInfo::setTaggedBasePointerIndex
void setTaggedBasePointerIndex(int Index)
Definition: AArch64MachineFunctionInfo.h:378
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:644
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:104
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
DepthFirstIterator.h
MachineRegisterInfo.h
MachineTraceMetrics.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
MachineLoopInfo.h
AArch64InstrInfo.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::AArch64InstrInfo
Definition: AArch64InstrInfo.h:37
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::MachineFrameInfo::setObjectSSPLayout
void setObjectSSPLayout(int ObjectIdx, SSPLayoutKind Kind)
Definition: MachineFrameInfo.h:542
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::DenseMapInfo< SlotWithTag >::getHashValue
static unsigned getHashValue(const SlotWithTag &V)
Definition: AArch64StackTaggingPreRA.cpp:221
llvm::MachineFrameInfo::SSPLK_None
@ SSPLK_None
Did not trigger a stack protector.
Definition: MachineFrameInfo.h:112
llvm::None
const NoneType None
Definition: None.h:23
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
isSlotPreAllocated
static bool isSlotPreAllocated(MachineFrameInfo *MFI, int FI)
Definition: AArch64StackTaggingPreRA.cpp:231
llvm::MachineRegisterInfo::isSSA
bool isSSA() const
Definition: MachineRegisterInfo.h:185
llvm::DenseMapInfo< SlotWithTag >::getEmptyKey
static SlotWithTag getEmptyKey()
Definition: AArch64StackTaggingPreRA.cpp:219
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::cl::opt
Definition: CommandLine.h:1432
ra
aarch64 stack tagging pre ra
Definition: AArch64StackTaggingPreRA.cpp:96
llvm::cl::values
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:697
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
UseReg
static Register UseReg(const MachineOperand &MO)
Definition: HexagonCopyToCombine.cpp:254
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:642
MachineFunctionPass.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:546
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineBranchProbabilityInfo.h
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
UncheckedSafe
@ UncheckedSafe
Definition: AArch64StackTaggingPreRA.cpp:36
llvm::operator==
bool operator==(uint64_t V1, const APInt &V2)
Definition: APInt.h:1986
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(AArch64StackTaggingPreRA, "aarch64-stack-tagging-pre-ra", "AArch64 Stack Tagging PreRA Pass", false, false) INITIALIZE_PASS_END(AArch64StackTaggingPreRA
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::initializeAArch64StackTaggingPreRAPass
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
UncheckedAlways
@ UncheckedAlways
Definition: AArch64StackTaggingPreRA.cpp:36
llvm::createAArch64StackTaggingPreRAPass
FunctionPass * createAArch64StackTaggingPreRAPass()
Definition: AArch64StackTaggingPreRA.cpp:99
TargetSubtargetInfo.h
clEnumValN
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:672
ClFirstSlot
static cl::opt< bool > ClFirstSlot("stack-tagging-first-slot-opt", cl::Hidden, cl::init(true), cl::ZeroOrMore, cl::desc("Apply first slot optimization for stack tagging " "(eliminate ADDG Rt, Rn, 0, 0)."))
llvm::AArch64RegisterInfo
Definition: AArch64RegisterInfo.h:26
llvm::DenseMapInfo< SlotWithTag >::getTombstoneKey
static SlotWithTag getTombstoneKey()
Definition: AArch64StackTaggingPreRA.cpp:220
llvm::ifs::IFSSymbolType::Func
@ Func
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MachineFrameInfo.h
isUncheckedLoadOrStoreOpcode
static bool isUncheckedLoadOrStoreOpcode(unsigned Opcode)
Definition: AArch64StackTaggingPreRA.cpp:103
ClUncheckedLdSt
cl::opt< UncheckedLdStMode > ClUncheckedLdSt("stack-tagging-unchecked-ld-st", cl::Hidden, cl::init(UncheckedSafe), cl::desc("Unconditionally apply unchecked-ld-st optimization (even for large " "stack frames, or in the presence of variable sized allocas)."), cl::values(clEnumValN(UncheckedNever, "never", "never apply unchecked-ld-st"), clEnumValN(UncheckedSafe, "safe", "apply unchecked-ld-st when the target is definitely within range"), clEnumValN(UncheckedAlways, "always", "always apply unchecked-ld-st")))
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
UncheckedLdStMode
UncheckedLdStMode
Definition: AArch64StackTaggingPreRA.cpp:36
MachineInstrBuilder.h
llvm::hash_combine
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
Definition: Hashing.h:605
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
stack
S is passed via registers r2 But gcc stores them to the stack
Definition: README.txt:189
Tagging
AArch64 Stack Tagging
Definition: AArch64StackTagging.cpp:350
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::AArch64II::MO_TAGGED
@ MO_TAGGED
MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag in bits 56-63.
Definition: AArch64BaseInfo.h:748
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
MachineFunction.h
llvm::DenseMapInfo< SlotWithTag >::isEqual
static bool isEqual(const SlotWithTag &A, const SlotWithTag &B)
Definition: AArch64StackTaggingPreRA.cpp:225
TargetRegisterInfo.h
Debug.h
SetVector.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1198
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38