LLVM 23.0.0git
Classes | Macros | Typedefs | Functions
AMDGPUDisassembler.cpp File Reference

This file contains definition for AMDGPU ISA disassembler. More...

#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCExpr.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoder.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Compiler.h"
#include "AMDGPUGenDisassemblerTables.inc"

Go to the source code of this file.

Classes

struct  VOPModifiers

Macros

#define DEBUG_TYPE   "amdgpu-disassembler"
#define SGPR_MAX
#define X(NUM, ENUM, NAME)
#define DECODE_OPERAND(StaticDecoderName, DecoderName)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)
#define DECODE_OPERAND_SREG_7(RegClass, OpWidth)
#define DECODE_OPERAND_SREG_8(RegClass, OpWidth)
#define DECODE_SDWA(DecName)
#define GET_FIELD(MASK)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG)
#define CHECK_RESERVED_BITS(MASK)
#define CHECK_RESERVED_BITS_MSG(MASK, MSG)
#define CHECK_RESERVED_BITS_DESC(MASK, DESC)
#define CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)

Typedefs

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Functions

static int64_t getInlineImmValF16 (unsigned Imm)
static int64_t getInlineImmValBF16 (unsigned Imm)
static int64_t getInlineImmVal32 (unsigned Imm)
static int64_t getInlineImmVal64 (unsigned Imm)
static MCDisassembler::DecodeStatus addOperand (MCInst &Inst, const MCOperand &Opnd)
static int insertNamedMCOperand (MCInst &MI, const MCOperand &Op, AMDGPU::OpName Name)
static DecodeStatus decodeSOPPBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSplitBarrier (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeDpp8FI (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSrcOp (MCInst &Inst, unsigned EncSize, unsigned OpWidth, unsigned Imm, unsigned EncImm, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcReg9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImm9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeSrcRegOrImmA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus DecodeVGPR_16RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus DecodeVGPR_16_Lo128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16_Lo128 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus decodeOperand_VSrcT16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VGPR_16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_KImmFP (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_KImmFP64 (MCInst &Inst, uint64_t Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static DecodeStatus decodeAVLdSt (MCInst &Inst, unsigned Imm, unsigned Opw, const MCDisassembler *Decoder)
template<unsigned Opw>
static DecodeStatus decodeAVLdSt (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VSrc_f64 (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeVersionImm (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<typename T>
static T eatBytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 96 > eat12Bytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 128 > eat16Bytes (ArrayRef< uint8_t > &Bytes)
static void adjustMFMA_F8F6F4OpRegClass (const MCRegisterInfo &MRI, MCOperand &MO, uint8_t NumRegs)
 Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister for the used format width.
static VOPModifiers collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
static MCRegister CheckVGPROverflow (MCRegister Reg, const MCRegisterClass &RC, const MCRegisterInfo &MRI)
static SmallString< 32 > getBitRangeFromMask (uint32_t Mask, unsigned BaseBytes)
 Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.
static Error createReservedKDBitsError (uint32_t Mask, unsigned BaseBytes, const char *Msg="")
 Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.
static Error createReservedKDBytesError (unsigned BaseInBytes, unsigned WidthInBytes)
 Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.
static MCSymbolizer * createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static MCDisassembler * createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler ()

Detailed Description

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

Macro Definition Documentation

◆ CHECK_RESERVED_BITS

#define CHECK_RESERVED_BITS ( MASK)
Value:
CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "")
CHECK_RESERVED_BITS_IMPL
#define CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG)
Definition AMDGPUDisassembler.cpp:2408

Definition at line 2418 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2().

◆ CHECK_RESERVED_BITS_DESC

#define CHECK_RESERVED_BITS_DESC ( MASK,
DESC )
Value:
CHECK_RESERVED_BITS_IMPL(MASK, DESC, "")
DESC
#define DESC
Definition MVETailPredication.cpp:56

Definition at line 2421 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2().

◆ CHECK_RESERVED_BITS_DESC_MSG

#define CHECK_RESERVED_BITS_DESC_MSG ( MASK,
DESC,
MSG )
Value:
CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG)

Definition at line 2423 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

◆ CHECK_RESERVED_BITS_IMPL

#define CHECK_RESERVED_BITS_IMPL ( MASK,
DESC,
MSG )
Value:
do { \
if (FourByteBuffer & (MASK)) { \
return createStringError(std::errc::invalid_argument, \
"kernel descriptor " DESC \
" reserved %s set" MSG, \
getBitRangeFromMask((MASK), 0).c_str()); \
} \
} while (0)
getBitRangeFromMask
static SmallString< 32 > getBitRangeFromMask(uint32_t Mask, unsigned BaseBytes)
Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in e...
Definition AMDGPUDisassembler.cpp:2379
llvm::c_str
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
Definition WindowsSupport.h:194
llvm::createStringError
Error createStringError(std::error_code EC, char const *Fmt, const Ts &... Vals)
Create formatted StringError object.
Definition Error.h:1321

Definition at line 2408 of file AMDGPUDisassembler.cpp.

◆ CHECK_RESERVED_BITS_MSG

#define CHECK_RESERVED_BITS_MSG ( MASK,
MSG )
Value:
CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG)

Definition at line 2419 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1().

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-disassembler"

Definition at line 44 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND

#define DECODE_OPERAND ( StaticDecoderName,
DecoderName )
Value:
static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand(Inst, DAsm->DecoderName(Imm)); \
}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition AMDGPUDisassembler.cpp:134
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
uint64_t

Definition at line 198 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8 ( RegClass)
Value:
static DecodeStatus Decode##RegClass##RegisterClass( \
MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
assert(Imm < (1 << 8) && "8-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand( \
Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
}

Definition at line 208 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SREG_7

#define DECODE_OPERAND_SREG_7 ( RegClass,
OpWidth )
Value:
DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm)
DECODE_SrcOp
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)
Definition AMDGPUDisassembler.cpp:218

Definition at line 236 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SREG_8

#define DECODE_OPERAND_SREG_8 ( RegClass,
OpWidth )
Value:
DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm)

Definition at line 239 of file AMDGPUDisassembler.cpp.

◆ DECODE_SDWA

#define DECODE_SDWA ( DecName)
Value:
DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
DECODE_OPERAND
#define DECODE_OPERAND(StaticDecoderName, DecoderName)
Definition AMDGPUDisassembler.cpp:198

Definition at line 448 of file AMDGPUDisassembler.cpp.

◆ DECODE_SrcOp

#define DECODE_SrcOp ( Name,
EncSize,
OpWidth,
EncImm )
Value:
static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm)); \
}

Definition at line 218 of file AMDGPUDisassembler.cpp.

◆ GET_FIELD

#define GET_FIELD ( MASK)
Value:
(AMDHSA_BITS_GET(FourByteBuffer, MASK))
AMDHSA_BITS_GET
#define AMDHSA_BITS_GET(SRC, MSK)
Definition AMDHSAKernelDescriptor.h:39

Definition at line 2397 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

◆ PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE ( DIRECTIVE,
MASK )
Value:
do { \
KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \
} while (0)
GET_FIELD
#define GET_FIELD(MASK)
Definition AMDGPUDisassembler.cpp:2397

Definition at line 2398 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2(), llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(), and llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

◆ PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE ( DIRECTIVE,
MASK )
Value:
do { \
KdStream << Indent << DIRECTIVE " " \
<< ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
} while (0)

Definition at line 2398 of file AMDGPUDisassembler.cpp.

◆ PRINT_PSEUDO_DIRECTIVE_COMMENT

#define PRINT_PSEUDO_DIRECTIVE_COMMENT ( DIRECTIVE,
MASK )
Value:
do { \
KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \
<< GET_FIELD(MASK) << '\n'; \
} while (0)

Definition at line 2402 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

◆ SGPR_MAX

#define SGPR_MAX
Value:
(isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
: AMDGPU::EncValues::SGPR_MAX_SI)

Definition at line 46 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeNonVGPRSrcOp(), and llvm::AMDGPUDisassembler::decodeSDWAVopcDst().

◆ X

#define X ( NUM,
ENUM,
NAME )
Value:
case ELF::ENUM: \
OS << NAME; \
break;

Typedef Documentation

◆ DecodeStatus

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Definition at line 50 of file AMDGPUDisassembler.cpp.

Function Documentation

◆ addOperand()

MCDisassembler::DecodeStatus addOperand ( MCInst & Inst,
const MCOperand & Opnd )
inlinestatic

Definition at line 134 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeAVLdSt(), decodeBoolReg(), decodeDpp8FI(), decodeOperand_KImmFP(), decodeOperand_KImmFP64(), decodeOperand_VGPR_16(), decodeOperand_VSrc_f64(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), decodeSplitBarrier(), decodeSrcOp(), decodeVersionImm(), DecodeVGPR_16_Lo128RegisterClass(), DecodeVGPR_16RegisterClass(), llvm::LoongArchAsmPrinter::LowerSTATEPOINT(), llvm::VPScalarIVStepsRecipe::setStartIndex(), llvm::VPFirstOrderRecurrencePHIRecipe::VPFirstOrderRecurrencePHIRecipe(), llvm::VPInterleaveBase::VPInterleaveBase(), llvm::VPReductionPHIRecipe::VPReductionPHIRecipe(), llvm::VPReductionRecipe::VPReductionRecipe(), llvm::VPUser::VPUser(), llvm::VPWidenInductionRecipe::VPWidenInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), and llvm::VPWidenPointerInductionRecipe::VPWidenPointerInductionRecipe().

◆ adjustMFMA_F8F6F4OpRegClass()

void adjustMFMA_F8F6F4OpRegClass ( const MCRegisterInfo & MRI,
MCOperand & MO,
uint8_t NumRegs )
static

Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister for the used format width.

Definition at line 1069 of file AMDGPUDisassembler.cpp.

References llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::MCOperand::getReg(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm_unreachable, and llvm::MCOperand::setReg().

Referenced by llvm::AMDGPUDisassembler::convertMAIInst(), and llvm::AMDGPUDisassembler::convertWMMAInst().

◆ CheckVGPROverflow()

MCRegister CheckVGPROverflow ( MCRegister Reg,
const MCRegisterClass & RC,
const MCRegisterInfo & MRI )
static

Definition at line 1311 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCRegisterClass::contains(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterClass::getSizeInBits(), llvm::MCRegisterInfo::getSubReg(), and Reg.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ collectVOPModifiers()

VOPModifiers collectVOPModifiers ( const MCInst & MI,
bool IsVOP3P = false )
static

Definition at line 1171 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, OpIdx, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), and llvm::AMDGPUDisassembler::convertVOPC64DPPInst().

◆ createAMDGPUDisassembler()

MCDisassembler * createAMDGPUDisassembler ( const Target & T,
const MCSubtargetInfo & STI,
MCContext & Ctx )
static

Definition at line 3032 of file AMDGPUDisassembler.cpp.

References T.

Referenced by LLVMInitializeAMDGPUDisassembler().

◆ createAMDGPUSymbolizer()

MCSymbolizer * createAMDGPUSymbolizer ( const Triple & ,
LLVMOpInfoCallback ,
LLVMSymbolLookupCallback ,
void * DisInfo,
MCContext * Ctx,
std::unique_ptr< MCRelocationInfo > && RelInfo )
static

Definition at line 3023 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

◆ createReservedKDBitsError()

Error createReservedKDBitsError ( uint32_t Mask,
unsigned BaseBytes,
const char * Msg = "" )
static

Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.

Definition at line 2711 of file AMDGPUDisassembler.cpp.

References llvm::c_str(), llvm::createStringError(), and getBitRangeFromMask().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

◆ createReservedKDBytesError()

Error createReservedKDBytesError ( unsigned BaseInBytes,
unsigned WidthInBytes )
static

Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.

Definition at line 2720 of file AMDGPUDisassembler.cpp.

References llvm::createStringError().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

◆ decodeAV10()

template<unsigned OpWidth>
DecodeStatus decodeAV10 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 247 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::AMDGPU::EncValues::IS_VGPR.

◆ decodeAVLdSt() [1/2]

template<unsigned Opw>
DecodeStatus decodeAVLdSt ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 434 of file AMDGPUDisassembler.cpp.

References decodeAVLdSt().

◆ decodeAVLdSt() [2/2]

DecodeStatus decodeAVLdSt ( MCInst & Inst,
unsigned Imm,
unsigned Opw,
const MCDisassembler * Decoder )
static

Definition at line 427 of file AMDGPUDisassembler.cpp.

References addOperand().

Referenced by decodeAVLdSt().

◆ decodeBoolReg()

DecodeStatus decodeBoolReg ( MCInst & Inst,
unsigned Val,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 179 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeDpp8FI()

DecodeStatus decodeDpp8FI ( MCInst & Inst,
unsigned Val,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 192 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperand_KImmFP()

DecodeStatus decodeOperand_KImmFP ( MCInst & Inst,
unsigned Imm,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 407 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperand_KImmFP64()

DecodeStatus decodeOperand_KImmFP64 ( MCInst & Inst,
uint64_t Imm,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 414 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperand_VGPR_16()

DecodeStatus decodeOperand_VGPR_16 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 394 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

◆ decodeOperand_VSrc_f64()

DecodeStatus decodeOperand_VSrc_f64 ( MCInst & Inst,
unsigned Imm,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 440 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

◆ decodeOperand_VSrcT16()

template<unsigned OpWidth>
DecodeStatus decodeOperand_VSrcT16 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 380 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

◆ decodeOperand_VSrcT16_Lo128()

template<unsigned OpWidth>
DecodeStatus decodeOperand_VSrcT16_Lo128 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 365 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

◆ decodeOperandVOPDDstY()

DecodeStatus decodeOperandVOPDDstY ( MCInst & Inst,
unsigned Val,
uint64_t Addr,
const void * Decoder )
static

Definition at line 421 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeSMEMOffset()

DecodeStatus decodeSMEMOffset ( MCInst & Inst,
unsigned Imm,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 165 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), llvm::Offset, and llvm::SignExtend64().

◆ decodeSOPPBrTarget()

DecodeStatus decodeSOPPBrTarget ( MCInst & Inst,
unsigned Imm,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 152 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), llvm::Offset, llvm::SignExtend64(), and llvm::MCDisassembler::Success.

◆ decodeSplitBarrier()

DecodeStatus decodeSplitBarrier ( MCInst & Inst,
unsigned Val,
uint64_t Addr,
const MCDisassembler * Decoder )
static

Definition at line 185 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeSrcA9()

template<unsigned OpWidth>
DecodeStatus decodeSrcA9 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 265 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeSrcAV10()

template<unsigned OpWidth>
DecodeStatus decodeSrcAV10 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 273 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeSrcOp()

DecodeStatus decodeSrcOp ( MCInst & Inst,
unsigned EncSize,
unsigned OpWidth,
unsigned Imm,
unsigned EncImm,
const MCDisassembler * Decoder )
static

Definition at line 226 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

Referenced by decodeAV10(), decodeSrcA9(), decodeSrcAV10(), decodeSrcReg9(), decodeSrcRegOrImm9(), and decodeSrcRegOrImmA9().

◆ decodeSrcReg9()

template<unsigned OpWidth>
DecodeStatus decodeSrcReg9 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 255 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeSrcRegOrImm9()

template<unsigned OpWidth>
DecodeStatus decodeSrcRegOrImm9 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 285 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeSrcRegOrImmA9()

template<unsigned OpWidth>
DecodeStatus decodeSrcRegOrImmA9 ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 294 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

◆ decodeVersionImm()

DecodeStatus decodeVersionImm ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 455 of file AMDGPUDisassembler.cpp.

References addOperand(), const, and decodeVersionImm().

Referenced by decodeVersionImm().

◆ DecodeVGPR_16_Lo128RegisterClass()

DecodeStatus DecodeVGPR_16_Lo128RegisterClass ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 354 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::isUInt().

◆ DecodeVGPR_16RegisterClass()

DecodeStatus DecodeVGPR_16RegisterClass ( MCInst & Inst,
unsigned Imm,
uint64_t ,
const MCDisassembler * Decoder )
static

Definition at line 341 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), const, DecodeVGPR_16RegisterClass(), and llvm::isUInt().

Referenced by DecodeVGPR_16RegisterClass().

◆ eat12Bytes()

std::bitset< 96 > eat12Bytes ( ArrayRef< uint8_t > & Bytes)
inlinestatic

Definition at line 524 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::support::endian::read(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ eat16Bytes()

std::bitset< 128 > eat16Bytes ( ArrayRef< uint8_t > & Bytes)
inlinestatic

Definition at line 534 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::support::endian::read(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ eatBytes()

template<typename T>
T eatBytes ( ArrayRef< uint8_t > & Bytes)
inlinestatic

Definition at line 516 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::support::endian::read(), llvm::ArrayRef< T >::size(), llvm::ArrayRef< T >::slice(), and T.

Referenced by llvm::AMDGPUDisassembler::decodeLiteral64Constant(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::AMDGPUDisassembler::getInstruction().

◆ getBitRangeFromMask()

SmallString< 32 > getBitRangeFromMask ( uint32_t Mask,
unsigned BaseBytes )
static

Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.

Mask is a single continuous range of 1s surrounded by zeros. The format here is meant to align with the tables that describe these bits in llvm.org/docs/AMDGPUUsage.html.

Definition at line 2379 of file AMDGPUDisassembler.cpp.

References llvm::countr_zero(), and llvm::popcount().

Referenced by createReservedKDBitsError().

◆ getInlineImmVal32()

int64_t getInlineImmVal32 ( unsigned Imm)
static

Definition at line 1792 of file AMDGPUDisassembler.cpp.

References llvm::bit_cast(), and llvm_unreachable.

◆ getInlineImmVal64()

int64_t getInlineImmVal64 ( unsigned Imm)
static

Definition at line 1817 of file AMDGPUDisassembler.cpp.

References llvm::bit_cast(), and llvm_unreachable.

◆ getInlineImmValBF16()

int64_t getInlineImmValBF16 ( unsigned Imm)
static

Definition at line 1867 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

◆ getInlineImmValF16()

int64_t getInlineImmValF16 ( unsigned Imm)
static

Definition at line 1842 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

◆ insertNamedMCOperand()

int insertNamedMCOperand ( MCInst & MI,
const MCOperand & Op,
AMDGPU::OpName Name )
static

Definition at line 141 of file AMDGPUDisassembler.cpp.

References I, MI, and OpIdx.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPC64DPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

◆ LLVMInitializeAMDGPUDisassembler()

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler ( )

Definition at line 3039 of file AMDGPUDisassembler.cpp.

References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().

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