LLVM 17.0.0git
Classes | Macros | Typedefs | Functions
AMDGPUDisassembler.cpp File Reference

This file contains definition for AMDGPU ISA disassembler. More...

#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "AMDGPUGenDisassemblerTables.inc"
Include dependency graph for AMDGPUDisassembler.cpp:

Go to the source code of this file.

Classes

struct  VOPModifiers
 

Macros

#define DEBUG_TYPE   "amdgpu-disassembler"
 
#define SGPR_MAX
 
#define DECODE_OPERAND(StaticDecoderName, DecoderName)
 
#define DECODE_OPERAND_REG_8(RegClass)
 
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, ImmWidth)
 
#define DECODE_OPERAND_REG_7(RegClass, OpWidth)    DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
 
#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
 
#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
 
#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
 
#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
 
#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
 
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
 
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
 
#define DECODE_SDWA(DecName)   DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
 
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
 
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
 

Typedefs

using DecodeStatus = llvm::MCDisassembler::DecodeStatus
 

Functions

static MCDisassembler::DecodeStatus addOperand (MCInst &Inst, const MCOperand &Opnd)
 
static int insertNamedMCOperand (MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
 
static DecodeStatus decodeSoppBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus decodeOperand_f32kimm (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus decodeOperand_f16kimm (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
 
static bool IsAGPROperand (const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
 
static DecodeStatus decodeOperand_AVLdSt_Any (MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
 
static DecodeStatus DecodeAVLdSt_32RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus DecodeAVLdSt_64RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus DecodeAVLdSt_96RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus DecodeAVLdSt_128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
static DecodeStatus DecodeAVLdSt_160RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
 
template<typename T >
static T eatBytes (ArrayRef< uint8_t > &Bytes)
 
static DecoderUInt128 eat12Bytes (ArrayRef< uint8_t > &Bytes)
 
static bool isValidDPP8 (const MCInst &MI)
 
static VOPModifiers collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
 
static int64_t getInlineImmVal32 (unsigned Imm)
 
static int64_t getInlineImmVal64 (unsigned Imm)
 
static int64_t getInlineImmVal16 (unsigned Imm)
 
static MCSymbolizer * createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
 
static MCDisassembler * createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
 
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler ()
 

Detailed Description

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-disassembler"

Definition at line 39 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND

#define DECODE_OPERAND (   StaticDecoderName,
  DecoderName 
)
Value:
static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand(Inst, DAsm->DecoderName(Imm)); \
}
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:59
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:79
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:103
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
uint64_t

Definition at line 110 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_7

#define DECODE_OPERAND_REG_7 (   RegClass,
  OpWidth 
)     DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)

Definition at line 143 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8 (   RegClass)
Value:
static DecodeStatus Decode##RegClass##RegisterClass( \
MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
assert(Imm < (1 << 8) && "8-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand( \
Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
}

Definition at line 120 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_REG_AV10

#define DECODE_OPERAND_REG_AV10 (   RegClass,
  OpWidth 
)
Value:
DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \
Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
DECODE_SrcOp
#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, ImmWidth)
Definition: AMDGPUDisassembler.cpp:130

Definition at line 150 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SRC_REG_9

#define DECODE_OPERAND_SRC_REG_9 (   RegClass,
  OpWidth 
)     DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)

Definition at line 155 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SRC_REG_A9

#define DECODE_OPERAND_SRC_REG_A9 (   RegClass,
  OpWidth 
)     DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)

Definition at line 161 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SRC_REG_OR_IMM_9

#define DECODE_OPERAND_SRC_REG_OR_IMM_9 (   RegClass,
  OpWidth,
  ImmWidth 
)
Value:
DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \
false, ImmWidth)

Definition at line 174 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SRC_REG_OR_IMM_A9

#define DECODE_OPERAND_SRC_REG_OR_IMM_A9 (   RegClass,
  OpWidth,
  ImmWidth 
)
Value:
DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \
Imm | 512, false, ImmWidth)

Definition at line 180 of file AMDGPUDisassembler.cpp.

◆ DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9

#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9 (   RegClass,
  OpWidth,
  ImmWidth 
)
Value:
DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \
OpWidth, Imm, true, ImmWidth)

Definition at line 184 of file AMDGPUDisassembler.cpp.

◆ DECODE_SDWA

#define DECODE_SDWA (   DecName)    DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)

Definition at line 368 of file AMDGPUDisassembler.cpp.

◆ DECODE_SRC_OPERAND_REG_AV10

#define DECODE_SRC_OPERAND_REG_AV10 (   RegClass,
  OpWidth 
)     DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)

Definition at line 166 of file AMDGPUDisassembler.cpp.

◆ DECODE_SrcOp

#define DECODE_SrcOp (   Name,
  EncSize,
  OpWidth,
  EncImm,
  MandatoryLiteral,
  ImmWidth 
)
Value:
static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
const MCDisassembler *Decoder) { \
assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
return addOperand(Inst, \
DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
MandatoryLiteral, ImmWidth)); \
}
Name
std::string Name
Definition: ELFObjHandler.cpp:77

Definition at line 130 of file AMDGPUDisassembler.cpp.

◆ PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE (   DIRECTIVE,
  MASK 
)
Value:
do { \
KdStream << Indent << DIRECTIVE " " \
<< ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
} while (0)

Definition at line 1640 of file AMDGPUDisassembler.cpp.

◆ PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE (   DIRECTIVE,
  MASK 
)
Value:
do { \
KdStream << Indent << DIRECTIVE " " \
<< ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
} while (0)

Definition at line 1640 of file AMDGPUDisassembler.cpp.

◆ SGPR_MAX

#define SGPR_MAX
Value:
(isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
: AMDGPU::EncValues::SGPR_MAX_SI)

Definition at line 41 of file AMDGPUDisassembler.cpp.

Typedef Documentation

◆ DecodeStatus

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Definition at line 45 of file AMDGPUDisassembler.cpp.

Function Documentation

◆ addOperand()

static MCDisassembler::DecodeStatus addOperand ( MCInst &  Inst,
const MCOperand &  Opnd 
)
inlinestatic

Definition at line 59 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeBoolReg(), decodeOperand_AVLdSt_Any(), decodeOperand_f16kimm(), decodeOperand_f32kimm(), decodeOperandVOPDDstY(), decodeSMEMOffset(), and decodeSoppBrTarget().

◆ collectVOPModifiers()

static VOPModifiers collectVOPModifiers ( const MCInst &  MI,
bool  IsVOP3P = false 
)
static

Definition at line 745 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, llvm::AMDGPU::getNamedOperandIdx(), MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), and llvm::AMDGPUDisassembler::convertVOP3PDPPInst().

◆ createAMDGPUDisassembler()

static MCDisassembler * createAMDGPUDisassembler ( const Target &  T,
const MCSubtargetInfo &  STI,
MCContext &  Ctx 
)
static

Definition at line 2050 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

◆ createAMDGPUSymbolizer()

static MCSymbolizer * createAMDGPUSymbolizer ( const Triple &  ,
LLVMOpInfoCallback  ,
LLVMSymbolLookupCallback  ,
void *  DisInfo,
MCContext *  Ctx,
std::unique_ptr< MCRelocationInfo > &&  RelInfo 
)
static

Definition at line 2041 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

◆ DecodeAVLdSt_128RegisterClass()

static DecodeStatus DecodeAVLdSt_128RegisterClass ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 355 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW128.

◆ DecodeAVLdSt_160RegisterClass()

static DecodeStatus DecodeAVLdSt_160RegisterClass ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 362 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW160.

◆ DecodeAVLdSt_32RegisterClass()

static DecodeStatus DecodeAVLdSt_32RegisterClass ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 334 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW32.

◆ DecodeAVLdSt_64RegisterClass()

static DecodeStatus DecodeAVLdSt_64RegisterClass ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 341 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW64.

◆ DecodeAVLdSt_96RegisterClass()

static DecodeStatus DecodeAVLdSt_96RegisterClass ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 348 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW96.

◆ decodeBoolReg()

static DecodeStatus decodeBoolReg ( MCInst &  Inst,
unsigned  Val,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 104 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperand_AVLdSt_Any()

static DecodeStatus decodeOperand_AVLdSt_Any ( MCInst &  Inst,
unsigned  Imm,
AMDGPUDisassembler::OpWidthTy  Opw,
const MCDisassembler *  Decoder 
)
static

Definition at line 299 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::SIInstrFlags::DS, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), IsAGPROperand(), MRI, and TSFlags.

Referenced by DecodeAVLdSt_128RegisterClass(), DecodeAVLdSt_160RegisterClass(), DecodeAVLdSt_32RegisterClass(), DecodeAVLdSt_64RegisterClass(), and DecodeAVLdSt_96RegisterClass().

◆ decodeOperand_f16kimm()

static DecodeStatus decodeOperand_f16kimm ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 272 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperand_f32kimm()

static DecodeStatus decodeOperand_f32kimm ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 265 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeOperandVOPDDstY()

static DecodeStatus decodeOperandVOPDDstY ( MCInst &  Inst,
unsigned  Val,
uint64_t  Addr,
const void *  Decoder 
)
static

Definition at line 279 of file AMDGPUDisassembler.cpp.

References addOperand().

◆ decodeSMEMOffset()

static DecodeStatus decodeSMEMOffset ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 92 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), and llvm::Offset.

◆ decodeSoppBrTarget()

static DecodeStatus decodeSoppBrTarget ( MCInst &  Inst,
unsigned  Imm,
uint64_t  Addr,
const MCDisassembler *  Decoder 
)
static

Definition at line 77 of file AMDGPUDisassembler.cpp.

References addOperand(), Addr, llvm::MCOperand::createImm(), llvm::Offset, llvm::APInt::sext(), and llvm::MCDisassembler::Success.

◆ eat12Bytes()

static DecoderUInt128 eat12Bytes ( ArrayRef< uint8_t > &  Bytes)
inlinestatic

Definition at line 388 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ eatBytes()

template<typename T >
static T eatBytes ( ArrayRef< uint8_t > &  Bytes)
inlinestatic

Definition at line 381 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

◆ getInlineImmVal16()

static int64_t getInlineImmVal16 ( unsigned  Imm)
static

Definition at line 1238 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

◆ getInlineImmVal32()

static int64_t getInlineImmVal32 ( unsigned  Imm)
static

Definition at line 1188 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

◆ getInlineImmVal64()

static int64_t getInlineImmVal64 ( unsigned  Imm)
static

Definition at line 1213 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

◆ insertNamedMCOperand()

static int insertNamedMCOperand ( MCInst &  MI,
const MCOperand &  Op,
uint16_t  NameIdx 
)
static

Definition at line 66 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), I, and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

◆ IsAGPROperand()

static bool IsAGPROperand ( const MCInst &  Inst,
int  OpIdx,
const MCRegisterInfo *  MRI 
)
static

Definition at line 285 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::getOperand(), and MRI.

◆ isValidDPP8()

static bool isValidDPP8 ( const MCInst &  MI)
static

Definition at line 402 of file AMDGPUDisassembler.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst().

◆ LLVMInitializeAMDGPUDisassembler()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler ( )

Definition at line 2056 of file AMDGPUDisassembler.cpp.

References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().

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