AMDGPUDisassembler.cpp File Reference

This file contains definition for AMDGPU ISA disassembler. More...

#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCExpr.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoder.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Compiler.h"
#include "AMDGPUGenDisassemblerTables.inc"

Go to the source code of this file.

Classes
struct	VOPModifiers

Macros
#define	DEBUG_TYPE   "amdgpu-disassembler"
#define	SGPR_MAX
#define	DECODE_OPERAND(StaticDecoderName, DecoderName)
#define	DECODE_OPERAND_REG_8(RegClass)
#define	DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)
#define	DECODE_OPERAND_SREG_7(RegClass, OpWidth)
#define	DECODE_OPERAND_SREG_8(RegClass, OpWidth)
#define	DECODE_SDWA(DecName)
#define	GET_FIELD(MASK)
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)
#define	PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define	CHECK_RESERVED_BITS_IMPL(MASK, DESC, MSG)
#define	CHECK_RESERVED_BITS(MASK)
#define	CHECK_RESERVED_BITS_MSG(MASK, MSG)
#define	CHECK_RESERVED_BITS_DESC(MASK, DESC)
#define	CHECK_RESERVED_BITS_DESC_MSG(MASK, DESC, MSG)
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)

Typedefs
using	DecodeStatus = llvm::MCDisassembler::DecodeStatus

Functions
static int64_t	getInlineImmValF16 (unsigned Imm)
static int64_t	getInlineImmValBF16 (unsigned Imm)
static int64_t	getInlineImmVal32 (unsigned Imm)
static int64_t	getInlineImmVal64 (unsigned Imm)
static MCDisassembler::DecodeStatus	addOperand (MCInst &Inst, const MCOperand &Opnd)
static int	insertNamedMCOperand (MCInst &MI, const MCOperand &Op, AMDGPU::OpName Name)
static DecodeStatus	decodeSOPPBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSplitBarrier (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeDpp8FI (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSrcOp (MCInst &Inst, unsigned EncSize, unsigned OpWidth, unsigned Imm, unsigned EncImm, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeSrcReg9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeSrcA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeSrcAV10 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeSrcRegOrImm9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeSrcRegOrImmA9 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16_Lo128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeOperand_VSrcT16_Lo128 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<unsigned OpWidth>
static DecodeStatus	decodeOperand_VSrcT16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VGPR_16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_KImmFP (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_KImmFP64 (MCInst &Inst, uint64_t Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static DecodeStatus	decodeAVLdSt (MCInst &Inst, unsigned Imm, unsigned Opw, const MCDisassembler *Decoder)
template<unsigned Opw>
static DecodeStatus	decodeAVLdSt (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrc_f64 (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeVersionImm (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
template<typename T>
static T	eatBytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 96 >	eat12Bytes (ArrayRef< uint8_t > &Bytes)
static std::bitset< 128 >	eat16Bytes (ArrayRef< uint8_t > &Bytes)
static void	adjustMFMA_F8F6F4OpRegClass (const MCRegisterInfo &MRI, MCOperand &MO, uint8_t NumRegs)
	Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister for the used format width.
static VOPModifiers	collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
static unsigned	CheckVGPROverflow (unsigned Reg, const MCRegisterClass &RC, const MCRegisterInfo &MRI)
static SmallString< 32 >	getBitRangeFromMask (uint32_t Mask, unsigned BaseBytes)
	Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.
static Error	createReservedKDBitsError (uint32_t Mask, unsigned BaseBytes, const char *Msg="")
	Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.
static Error	createReservedKDBytesError (unsigned BaseInBytes, unsigned WidthInBytes)
	Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.
static MCSymbolizer *	createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static MCDisassembler *	createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeAMDGPUDisassembler ()

Detailed Description

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

Macro Definition Documentation

CHECK_RESERVED_BITS

#define CHECK_RESERVED_BITS

(

MASK

)

Value:

CHECK_RESERVED_BITS_IMPL(MASK, #MASK, "")

Definition at line 2284 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2().

CHECK_RESERVED_BITS_DESC

#define CHECK_RESERVED_BITS_DESC	(		MASK,
			DESC )

Value:

  CHECK_RESERVED_BITS_IMPL(MASK, DESC, "")

Definition at line 2287 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2().

CHECK_RESERVED_BITS_DESC_MSG

#define CHECK_RESERVED_BITS_DESC_MSG	(		MASK,
			DESC,
			MSG )

Value:

  CHECK_RESERVED_BITS_IMPL(MASK, DESC, ", " MSG)

Definition at line 2289 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

CHECK_RESERVED_BITS_IMPL

#define CHECK_RESERVED_BITS_IMPL	(		MASK,
			DESC,
			MSG )

Value:

  do {                                                                         \
    if (FourByteBuffer & (MASK)) {                                             \
      return createStringError(std::errc::invalid_argument,                    \
                               "kernel descriptor " DESC                       \
                               " reserved %s set" MSG,                         \
                               getBitRangeFromMask((MASK), 0).c_str());        \
    }                                                                          \
  } while (0)

Definition at line 2274 of file AMDGPUDisassembler.cpp.

CHECK_RESERVED_BITS_MSG

#define CHECK_RESERVED_BITS_MSG	(		MASK,
			MSG )

Value:

  CHECK_RESERVED_BITS_IMPL(MASK, #MASK, ", " MSG)

Definition at line 2285 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1().

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-disassembler"

Definition at line 44 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND

#define DECODE_OPERAND	(		StaticDecoderName,
			DecoderName )

Value:

  static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
                                        uint64_t /*Addr*/,                     \
                                        const MCDisassembler *Decoder) {       \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst, DAsm->DecoderName(Imm));                           \
  }

Definition at line 145 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8

(

RegClass

)

Value:

  static DecodeStatus Decode##RegClass##RegisterClass(                         \
      MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
      const MCDisassembler *Decoder) {                                         \
    assert(Imm < (1 << 8) && "8-bit encoding");                                \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(                                                         \
        Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
  }

Definition at line 155 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SREG_7

#define DECODE_OPERAND_SREG_7	(		RegClass,
			OpWidth )

Value:

  DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm)

Definition at line 183 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SREG_8

#define DECODE_OPERAND_SREG_8	(		RegClass,
			OpWidth )

Value:

  DECODE_SrcOp(Decode##RegClass##RegisterClass, 8, OpWidth, Imm)

Definition at line 186 of file AMDGPUDisassembler.cpp.

DECODE_SDWA

#define DECODE_SDWA

(

DecName

)

Value:

DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)

Definition at line 395 of file AMDGPUDisassembler.cpp.

DECODE_SrcOp

#define DECODE_SrcOp	(		Name,
			EncSize,
			OpWidth,
			EncImm )

Value:

  static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
                           const MCDisassembler *Decoder) {                    \
    assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst, DAsm->decodeSrcOp(Inst, OpWidth, EncImm));         \
  }

Definition at line 165 of file AMDGPUDisassembler.cpp.

GET_FIELD

#define GET_FIELD

(

MASK

)

Value:

(AMDHSA_BITS_GET(FourByteBuffer, MASK))

Definition at line 2263 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK )

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n';            \
  } while (0)

Definition at line 2264 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2(), llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3(), and llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK )

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " "                                        \
             << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';            \
  } while (0)

Definition at line 2264 of file AMDGPUDisassembler.cpp.

PRINT_PSEUDO_DIRECTIVE_COMMENT

#define PRINT_PSEUDO_DIRECTIVE_COMMENT	(		DIRECTIVE,
			MASK )

Value:

  do {                                                                         \
    KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " "       \
             << GET_FIELD(MASK) << '\n';                                       \
  } while (0)

Definition at line 2268 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), and llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3().

SGPR_MAX

#define SGPR_MAX

Value:

  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10                           \
                 : AMDGPU::EncValues::SGPR_MAX_SI)

Definition at line 46 of file AMDGPUDisassembler.cpp.

Referenced by llvm::AMDGPUDisassembler::decodeNonVGPRSrcOp(), and llvm::AMDGPUDisassembler::decodeSDWAVopcDst().

Typedef Documentation

DecodeStatus

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Definition at line 50 of file AMDGPUDisassembler.cpp.

Function Documentation

addOperand()

MCDisassembler::DecodeStatus addOperand ( MCInst & Inst, const MCOperand & Opnd )

inlinestatic

Definition at line 81 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeAVLdSt(), decodeBoolReg(), decodeDpp8FI(), decodeOperand_KImmFP(), decodeOperand_KImmFP64(), decodeOperand_VGPR_16(), decodeOperand_VSrc_f64(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), decodeSplitBarrier(), decodeSrcOp(), decodeVersionImm(), DecodeVGPR_16_Lo128RegisterClass(), DecodeVGPR_16RegisterClass(), llvm::LoongArchAsmPrinter::LowerSTATEPOINT(), llvm::VPWidenMemoryRecipe::setMask(), llvm::VPInterleaveBase::VPInterleaveBase(), llvm::VPReductionRecipe::VPReductionRecipe(), llvm::VPWidenInductionRecipe::VPWidenInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), llvm::VPWidenIntOrFpInductionRecipe::VPWidenIntOrFpInductionRecipe(), and llvm::VPWidenPointerInductionRecipe::VPWidenPointerInductionRecipe().

adjustMFMA_F8F6F4OpRegClass()

void adjustMFMA_F8F6F4OpRegClass ( const MCRegisterInfo & MRI, MCOperand & MO, uint8_t NumRegs )

static

Adjust the register values used by V_MFMA_F8F6F4_f8_f8 instructions to the appropriate subregister for the used format width.

Definition at line 960 of file AMDGPUDisassembler.cpp.

References llvm::MCOperand::getReg(), llvm_unreachable, MRI, and llvm::MCOperand::setReg().

Referenced by llvm::AMDGPUDisassembler::convertMAIInst(), and llvm::AMDGPUDisassembler::convertWMMAInst().

CheckVGPROverflow()

unsigned CheckVGPROverflow ( unsigned Reg, const MCRegisterClass & RC, const MCRegisterInfo & MRI )

static

Definition at line 1202 of file AMDGPUDisassembler.cpp.

References assert(), llvm::MCRegisterClass::getSizeInBits(), MRI, and Reg.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

collectVOPModifiers()

VOPModifiers collectVOPModifiers ( const MCInst & MI, bool IsVOP3P = false )

static

Definition at line 1062 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, Opc, OpIdx, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), and llvm::AMDGPUDisassembler::convertVOPC64DPPInst().

createAMDGPUDisassembler()

MCDisassembler * createAMDGPUDisassembler ( const Target & T, const MCSubtargetInfo & STI, MCContext & Ctx )

static

Definition at line 2898 of file AMDGPUDisassembler.cpp.

References T.

Referenced by LLVMInitializeAMDGPUDisassembler().

createAMDGPUSymbolizer()

MCSymbolizer * createAMDGPUSymbolizer ( const Triple & , LLVMOpInfoCallback , LLVMSymbolLookupCallback , void * DisInfo, MCContext * Ctx, std::unique_ptr< MCRelocationInfo > && RelInfo )

static

Definition at line 2889 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

createReservedKDBitsError()

Error createReservedKDBitsError ( uint32_t Mask, unsigned BaseBytes, const char * Msg = "" )

static

Create an error object to return from onSymbolStart for reserved kernel descriptor bits being set.

Definition at line 2577 of file AMDGPUDisassembler.cpp.

References llvm::c_str(), llvm::createStringError(), and getBitRangeFromMask().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

createReservedKDBytesError()

Error createReservedKDBytesError ( unsigned BaseInBytes, unsigned WidthInBytes )

static

Create an error object to return from onSymbolStart for reserved kernel descriptor bytes being set.

Definition at line 2586 of file AMDGPUDisassembler.cpp.

References llvm::createStringError().

Referenced by llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective().

decodeAV10()

template<unsigned OpWidth>

DecodeStatus decodeAV10 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 194 of file AMDGPUDisassembler.cpp.

References decodeSrcOp(), and llvm::AMDGPU::EncValues::IS_VGPR.

decodeAVLdSt() [1/2]

template<unsigned Opw>

DecodeStatus decodeAVLdSt ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 381 of file AMDGPUDisassembler.cpp.

References decodeAVLdSt().

decodeAVLdSt() [2/2]

DecodeStatus decodeAVLdSt ( MCInst & Inst, unsigned Imm, unsigned Opw, const MCDisassembler * Decoder )

static

Definition at line 374 of file AMDGPUDisassembler.cpp.

References addOperand().

Referenced by decodeAVLdSt().

decodeBoolReg()

DecodeStatus decodeBoolReg ( MCInst & Inst, unsigned Val, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 126 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeDpp8FI()

DecodeStatus decodeDpp8FI ( MCInst & Inst, unsigned Val, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 139 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_KImmFP()

DecodeStatus decodeOperand_KImmFP ( MCInst & Inst, unsigned Imm, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 354 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_KImmFP64()

DecodeStatus decodeOperand_KImmFP64 ( MCInst & Inst, uint64_t Imm, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 361 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_VGPR_16()

DecodeStatus decodeOperand_VGPR_16 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 341 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

decodeOperand_VSrc_f64()

DecodeStatus decodeOperand_VSrc_f64 ( MCInst & Inst, unsigned Imm, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 387 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

decodeOperand_VSrcT16()

template<unsigned OpWidth>

DecodeStatus decodeOperand_VSrcT16 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 327 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

decodeOperand_VSrcT16_Lo128()

template<unsigned OpWidth>

DecodeStatus decodeOperand_VSrcT16_Lo128 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 312 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), llvm::AMDGPU::EncValues::IS_VGPR, and llvm::isUInt().

decodeOperandVOPDDstY()

DecodeStatus decodeOperandVOPDDstY ( MCInst & Inst, unsigned Val, uint64_t Addr, const void * Decoder )

static

Definition at line 368 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeSMEMOffset()

DecodeStatus decodeSMEMOffset ( MCInst & Inst, unsigned Imm, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 112 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), llvm::Offset, and llvm::SignExtend64().

decodeSOPPBrTarget()

DecodeStatus decodeSOPPBrTarget ( MCInst & Inst, unsigned Imm, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 99 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), llvm::Offset, llvm::SignExtend64(), and llvm::MCDisassembler::Success.

decodeSplitBarrier()

DecodeStatus decodeSplitBarrier ( MCInst & Inst, unsigned Val, uint64_t Addr, const MCDisassembler * Decoder )

static

Definition at line 132 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeSrcA9()

template<unsigned OpWidth>

DecodeStatus decodeSrcA9 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 212 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcAV10()

template<unsigned OpWidth>

DecodeStatus decodeSrcAV10 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 220 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcOp()

DecodeStatus decodeSrcOp ( MCInst & Inst, unsigned EncSize, unsigned OpWidth, unsigned Imm, unsigned EncImm, const MCDisassembler * Decoder )

static

Definition at line 173 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

Referenced by decodeAV10(), decodeSrcA9(), decodeSrcAV10(), decodeSrcReg9(), decodeSrcRegOrImm9(), and decodeSrcRegOrImmA9().

decodeSrcReg9()

template<unsigned OpWidth>

DecodeStatus decodeSrcReg9 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 202 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcRegOrImm9()

template<unsigned OpWidth>

DecodeStatus decodeSrcRegOrImm9 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 232 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeSrcRegOrImmA9()

template<unsigned OpWidth>

DecodeStatus decodeSrcRegOrImmA9 ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 241 of file AMDGPUDisassembler.cpp.

References decodeSrcOp().

decodeVersionImm()

DecodeStatus decodeVersionImm ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 402 of file AMDGPUDisassembler.cpp.

References addOperand(), const, and decodeVersionImm().

Referenced by decodeVersionImm().

DecodeVGPR_16_Lo128RegisterClass()

DecodeStatus DecodeVGPR_16_Lo128RegisterClass ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 301 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::isUInt().

DecodeVGPR_16RegisterClass()

DecodeStatus DecodeVGPR_16RegisterClass ( MCInst & Inst, unsigned Imm, uint64_t , const MCDisassembler * Decoder )

static

Definition at line 288 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), const, DecodeVGPR_16RegisterClass(), and llvm::isUInt().

Referenced by DecodeVGPR_16RegisterClass().

eat12Bytes()

std::bitset< 96 > eat12Bytes ( ArrayRef< uint8_t > & Bytes )

inlinestatic

Definition at line 471 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::support::endian::read(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

eat16Bytes()

std::bitset< 128 > eat16Bytes ( ArrayRef< uint8_t > & Bytes )

inlinestatic

Definition at line 481 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::support::endian::read(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

eatBytes()

template<typename T>

T eatBytes ( ArrayRef< uint8_t > & Bytes )

inlinestatic

Definition at line 463 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::support::endian::read(), llvm::ArrayRef< T >::size(), llvm::ArrayRef< T >::slice(), and T.

Referenced by llvm::AMDGPUDisassembler::decodeLiteral64Constant(), llvm::AMDGPUDisassembler::decodeLiteralConstant(), and llvm::AMDGPUDisassembler::getInstruction().

getBitRangeFromMask()

SmallString< 32 > getBitRangeFromMask ( uint32_t Mask, unsigned BaseBytes )

static

Print a string describing the reserved bit range specified by Mask with offset BaseBytes for use in error comments.

Mask is a single continuous range of 1s surrounded by zeros. The format here is meant to align with the tables that describe these bits in llvm.org/docs/AMDGPUUsage.html.

Definition at line 2245 of file AMDGPUDisassembler.cpp.

References llvm::countr_zero(), and llvm::popcount().

Referenced by createReservedKDBitsError().

getInlineImmVal32()

int64_t getInlineImmVal32 ( unsigned Imm )

static

Definition at line 1672 of file AMDGPUDisassembler.cpp.

References llvm::bit_cast(), and llvm_unreachable.

getInlineImmVal64()

int64_t getInlineImmVal64 ( unsigned Imm )

static

Definition at line 1697 of file AMDGPUDisassembler.cpp.

References llvm::bit_cast(), and llvm_unreachable.

getInlineImmValBF16()

int64_t getInlineImmValBF16 ( unsigned Imm )

static

Definition at line 1747 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

getInlineImmValF16()

int64_t getInlineImmValF16 ( unsigned Imm )

static

Definition at line 1722 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

insertNamedMCOperand()

int insertNamedMCOperand ( MCInst & MI, const MCOperand & Op, AMDGPU::OpName Name )

static

Definition at line 88 of file AMDGPUDisassembler.cpp.

References I, MI, and OpIdx.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPC64DPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

LLVMInitializeAMDGPUDisassembler()

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler

(

)

Definition at line 2905 of file AMDGPUDisassembler.cpp.

References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().