LLVM 18.0.0git
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This file contains definition for AMDGPU ISA disassembler. More...
#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "AMDGPUGenDisassemblerTables.inc"
Go to the source code of this file.
Classes | |
struct | VOPModifiers |
Macros | |
#define | DEBUG_TYPE "amdgpu-disassembler" |
#define | SGPR_MAX |
#define | DECODE_OPERAND(StaticDecoderName, DecoderName) |
#define | DECODE_OPERAND_REG_8(RegClass) |
#define | DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, ImmWidth) |
#define | DECODE_OPERAND_REG_7(RegClass, OpWidth) DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) |
#define | DECODE_OPERAND_REG_AV10(RegClass, OpWidth) |
#define | DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) |
#define | DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) |
#define | DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) |
#define | DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) |
#define | DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) |
#define | DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) |
#define | DECODE_SDWA(DecName) DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) |
#define | GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) |
#define | PRINT_DIRECTIVE(DIRECTIVE, MASK) |
#define | PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) |
#define | PRINT_DIRECTIVE(DIRECTIVE, MASK) |
Typedefs | |
using | DecodeStatus = llvm::MCDisassembler::DecodeStatus |
This file contains definition for AMDGPU ISA disassembler.
Definition in file AMDGPUDisassembler.cpp.
#define DEBUG_TYPE "amdgpu-disassembler" |
Definition at line 39 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND | ( | StaticDecoderName, | |
DecoderName | |||
) |
Definition at line 108 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_REG_7 | ( | RegClass, | |
OpWidth | |||
) | DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) |
Definition at line 141 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_REG_8 | ( | RegClass | ) |
Definition at line 118 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_REG_AV10 | ( | RegClass, | |
OpWidth | |||
) |
Definition at line 148 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_SRC_REG_9 | ( | RegClass, | |
OpWidth | |||
) | DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) |
Definition at line 153 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_SRC_REG_A9 | ( | RegClass, | |
OpWidth | |||
) | DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) |
Definition at line 159 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_SRC_REG_OR_IMM_9 | ( | RegClass, | |
OpWidth, | |||
ImmWidth | |||
) |
Definition at line 172 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9 | ( | RegClass, | |
OpWidth, | |||
ImmWidth | |||
) |
Definition at line 178 of file AMDGPUDisassembler.cpp.
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9 | ( | RegClass, | |
OpWidth, | |||
ImmWidth | |||
) |
Definition at line 182 of file AMDGPUDisassembler.cpp.
#define DECODE_SDWA | ( | DecName | ) | DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) |
Definition at line 416 of file AMDGPUDisassembler.cpp.
#define DECODE_SRC_OPERAND_REG_AV10 | ( | RegClass, | |
OpWidth | |||
) | DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) |
Definition at line 164 of file AMDGPUDisassembler.cpp.
#define DECODE_SrcOp | ( | Name, | |
EncSize, | |||
OpWidth, | |||
EncImm, | |||
MandatoryLiteral, | |||
ImmWidth | |||
) |
Definition at line 128 of file AMDGPUDisassembler.cpp.
#define GET_FIELD | ( | MASK | ) | (AMDHSA_BITS_GET(FourByteBuffer, MASK)) |
Definition at line 1714 of file AMDGPUDisassembler.cpp.
#define PRINT_DIRECTIVE | ( | DIRECTIVE, | |
MASK | |||
) |
Definition at line 1715 of file AMDGPUDisassembler.cpp.
#define PRINT_DIRECTIVE | ( | DIRECTIVE, | |
MASK | |||
) |
Definition at line 1715 of file AMDGPUDisassembler.cpp.
#define PRINT_PSEUDO_DIRECTIVE_COMMENT | ( | DIRECTIVE, | |
MASK | |||
) |
Definition at line 1719 of file AMDGPUDisassembler.cpp.
#define SGPR_MAX |
Definition at line 41 of file AMDGPUDisassembler.cpp.
Definition at line 45 of file AMDGPUDisassembler.cpp.
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inlinestatic |
Definition at line 57 of file AMDGPUDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeBoolReg(), decodeOperand_AVLdSt_Any(), decodeOperand_KImmFP(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), DecodeVGPR_16_Lo128RegisterClass(), and DecodeVGPR_16RegisterClass().
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Definition at line 797 of file AMDGPUDisassembler.cpp.
References llvm::SISrcMods::DST_OP_SEL, llvm::AMDGPU::getNamedOperandIdx(), MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.
Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), and llvm::AMDGPUDisassembler::convertVOP3PDPPInst().
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Definition at line 2181 of file AMDGPUDisassembler.cpp.
Referenced by LLVMInitializeAMDGPUDisassembler().
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Definition at line 2172 of file AMDGPUDisassembler.cpp.
Referenced by LLVMInitializeAMDGPUDisassembler().
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Definition at line 403 of file AMDGPUDisassembler.cpp.
References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW128.
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Definition at line 410 of file AMDGPUDisassembler.cpp.
References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW160.
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Definition at line 382 of file AMDGPUDisassembler.cpp.
References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW32.
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Definition at line 389 of file AMDGPUDisassembler.cpp.
References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW64.
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Definition at line 396 of file AMDGPUDisassembler.cpp.
References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW96.
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Definition at line 102 of file AMDGPUDisassembler.cpp.
References addOperand().
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Definition at line 347 of file AMDGPUDisassembler.cpp.
References addOperand(), llvm::SIInstrFlags::DS, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), IsAGPROperand(), MRI, and TSFlags.
Referenced by DecodeAVLdSt_128RegisterClass(), DecodeAVLdSt_160RegisterClass(), DecodeAVLdSt_32RegisterClass(), DecodeAVLdSt_64RegisterClass(), and DecodeAVLdSt_96RegisterClass().
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Definition at line 320 of file AMDGPUDisassembler.cpp.
References addOperand().
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Definition at line 304 of file AMDGPUDisassembler.cpp.
References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.
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Definition at line 288 of file AMDGPUDisassembler.cpp.
References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.
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Definition at line 327 of file AMDGPUDisassembler.cpp.
References addOperand().
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Definition at line 90 of file AMDGPUDisassembler.cpp.
References addOperand(), llvm::MCOperand::createImm(), and llvm::Offset.
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Definition at line 75 of file AMDGPUDisassembler.cpp.
References addOperand(), Addr, llvm::MCOperand::createImm(), llvm::Offset, llvm::APInt::sext(), and llvm::MCDisassembler::Success.
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Definition at line 278 of file AMDGPUDisassembler.cpp.
References addOperand(), and assert().
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Definition at line 265 of file AMDGPUDisassembler.cpp.
References addOperand(), and assert().
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inlinestatic |
Definition at line 436 of file AMDGPUDisassembler.cpp.
References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().
Referenced by llvm::AMDGPUDisassembler::getInstruction().
Definition at line 429 of file AMDGPUDisassembler.cpp.
References assert(), llvm::ArrayRef< T >::data(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().
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Definition at line 1296 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().
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Definition at line 1246 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().
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Definition at line 1271 of file AMDGPUDisassembler.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().
Definition at line 64 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::getNamedOperandIdx(), I, and MI.
Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().
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Definition at line 333 of file AMDGPUDisassembler.cpp.
References llvm::MCInst::getOperand(), and MRI.
Definition at line 450 of file AMDGPUDisassembler.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), and MI.
Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst().
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler | ( | ) |
Definition at line 2187 of file AMDGPUDisassembler.cpp.
References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().