AMDGPUDisassembler.cpp File Reference

This file contains definition for AMDGPU ISA disassembler. More...

#include "Disassembler/AMDGPUDisassembler.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIDefines.h"
#include "SIRegisterInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm-c/DisassemblerTypes.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "AMDGPUGenDisassemblerTables.inc"

Go to the source code of this file.

Classes
struct	VOPModifiers

Macros
#define	DEBUG_TYPE   "amdgpu-disassembler"
#define	SGPR_MAX
#define	DECODE_OPERAND(StaticDecoderName, DecoderName)
#define	DECODE_OPERAND_REG_8(RegClass)
#define	DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, ImmWidth)
#define	DECODE_OPERAND_REG_7(RegClass, OpWidth)    DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
#define	DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
#define	DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
#define	DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
#define	DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)    DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
#define	DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
#define	DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
#define	DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
#define	DECODE_SDWA(DecName)   DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
#define	GET_FIELD(MASK)   (AMDHSA_BITS_GET(FourByteBuffer, MASK))
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)
#define	PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
#define	PRINT_DIRECTIVE(DIRECTIVE, MASK)

Typedefs
using	DecodeStatus = llvm::MCDisassembler::DecodeStatus

Functions
static MCDisassembler::DecodeStatus	addOperand (MCInst &Inst, const MCOperand &Opnd)
static int	insertNamedMCOperand (MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus	decodeSOPPBrTarget (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeSMEMOffset (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeBoolReg (MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	DecodeVGPR_16_Lo128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrcT16_Lo128 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_VSrcT16 (MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperand_KImmFP (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	decodeOperandVOPDDstY (MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static bool	IsAGPROperand (const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
static DecodeStatus	decodeOperand_AVLdSt_Any (MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus	DecodeAVLdSt_32RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	DecodeAVLdSt_64RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	DecodeAVLdSt_96RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	DecodeAVLdSt_128RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus	DecodeAVLdSt_160RegisterClass (MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
template<typename T >
static T	eatBytes (ArrayRef< uint8_t > &Bytes)
static DecoderUInt128	eat12Bytes (ArrayRef< uint8_t > &Bytes)
static bool	isValidDPP8 (const MCInst &MI)
static VOPModifiers	collectVOPModifiers (const MCInst &MI, bool IsVOP3P=false)
static int64_t	getInlineImmVal32 (unsigned Imm)
static int64_t	getInlineImmVal64 (unsigned Imm)
static int64_t	getInlineImmVal16 (unsigned Imm)
static MCSymbolizer *	createAMDGPUSymbolizer (const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static MCDisassembler *	createAMDGPUDisassembler (const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void	LLVMInitializeAMDGPUDisassembler ()

Detailed Description

This file contains definition for AMDGPU ISA disassembler.

Definition in file AMDGPUDisassembler.cpp.

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "amdgpu-disassembler"

Definition at line 39 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND

#define DECODE_OPERAND	(		StaticDecoderName,
			DecoderName
	)

Value:

  static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm,            \
                                        uint64_t /*Addr*/,                     \
                                        const MCDisassembler *Decoder) {       \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst, DAsm->DecoderName(Imm));                           \
  }

Definition at line 108 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_7

#define DECODE_OPERAND_REG_7	(		RegClass,
			OpWidth
	)		DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)

Definition at line 141 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_8

#define DECODE_OPERAND_REG_8

(

RegClass

)

Value:

  static DecodeStatus Decode##RegClass##RegisterClass(                         \
      MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
      const MCDisassembler *Decoder) {                                         \
    assert(Imm < (1 << 8) && "8-bit encoding");                                \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(                                                         \
        Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
  }

Definition at line 118 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_REG_AV10

#define DECODE_OPERAND_REG_AV10	(		RegClass,
			OpWidth
	)

Value:

  DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth,                   \
               Imm | AMDGPU::EncValues::IS_VGPR, false, 0)

Definition at line 148 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SRC_REG_9

#define DECODE_OPERAND_SRC_REG_9	(		RegClass,
			OpWidth
	)		DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)

Definition at line 153 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SRC_REG_A9

#define DECODE_OPERAND_SRC_REG_A9	(		RegClass,
			OpWidth
	)		DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)

Definition at line 159 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SRC_REG_OR_IMM_9

#define DECODE_OPERAND_SRC_REG_OR_IMM_9	(		RegClass,
			OpWidth,
			ImmWidth
	)

Value:

  DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm,      \
               false, ImmWidth)

Definition at line 172 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SRC_REG_OR_IMM_A9

#define DECODE_OPERAND_SRC_REG_OR_IMM_A9	(		RegClass,
			OpWidth,
			ImmWidth
	)

Value:

  DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth,           \
               Imm | 512, false, ImmWidth)

Definition at line 178 of file AMDGPUDisassembler.cpp.

DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9

#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9	(		RegClass,
			OpWidth,
			ImmWidth
	)

Value:

  DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9,         \
               OpWidth, Imm, true, ImmWidth)

Definition at line 182 of file AMDGPUDisassembler.cpp.

DECODE_SDWA

#define DECODE_SDWA

(

DecName

)

DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)

Definition at line 416 of file AMDGPUDisassembler.cpp.

DECODE_SRC_OPERAND_REG_AV10

#define DECODE_SRC_OPERAND_REG_AV10	(		RegClass,
			OpWidth
	)		DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)

Definition at line 164 of file AMDGPUDisassembler.cpp.

DECODE_SrcOp

#define DECODE_SrcOp	(		Name,
			EncSize,
			OpWidth,
			EncImm,
			MandatoryLiteral,
			ImmWidth
	)

Value:

  static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \
                           const MCDisassembler *Decoder) {                    \
    assert(Imm < (1 << EncSize) && #EncSize "-bit encoding");                  \
    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
    return addOperand(Inst,                                                    \
                      DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm,   \
                                        MandatoryLiteral, ImmWidth));          \
  }

Definition at line 128 of file AMDGPUDisassembler.cpp.

GET_FIELD

#define GET_FIELD

(

MASK

)

(AMDHSA_BITS_GET(FourByteBuffer, MASK))

Definition at line 1714 of file AMDGPUDisassembler.cpp.

PRINT_DIRECTIVE [1/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n';            \
  } while (0)

Definition at line 1715 of file AMDGPUDisassembler.cpp.

PRINT_DIRECTIVE [2/2]

#define PRINT_DIRECTIVE	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << DIRECTIVE " "                                        \
             << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';            \
  } while (0)

Definition at line 1715 of file AMDGPUDisassembler.cpp.

PRINT_PSEUDO_DIRECTIVE_COMMENT

#define PRINT_PSEUDO_DIRECTIVE_COMMENT	(		DIRECTIVE,
			MASK
	)

Value:

  do {                                                                         \
    KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " "       \
             << GET_FIELD(MASK) << '\n';                                       \
  } while (0)

Definition at line 1719 of file AMDGPUDisassembler.cpp.

SGPR_MAX

#define SGPR_MAX

Value:

  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10                           \
                 : AMDGPU::EncValues::SGPR_MAX_SI)

Definition at line 41 of file AMDGPUDisassembler.cpp.

Typedef Documentation

DecodeStatus

using DecodeStatus = llvm::MCDisassembler::DecodeStatus

Definition at line 45 of file AMDGPUDisassembler.cpp.

Function Documentation

addOperand()

static MCDisassembler::DecodeStatus addOperand ( MCInst &  Inst, const MCOperand &  Opnd  )

inlinestatic

Definition at line 57 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::addOperand(), llvm::MCDisassembler::Fail, llvm::MCOperand::isValid(), and llvm::MCDisassembler::Success.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), decodeBoolReg(), decodeOperand_AVLdSt_Any(), decodeOperand_KImmFP(), decodeOperand_VSrcT16(), decodeOperand_VSrcT16_Lo128(), decodeOperandVOPDDstY(), decodeSMEMOffset(), decodeSOPPBrTarget(), DecodeVGPR_16_Lo128RegisterClass(), and DecodeVGPR_16RegisterClass().

collectVOPModifiers()

static VOPModifiers collectVOPModifiers ( const MCInst &  MI, bool  IsVOP3P = false  )

static

Definition at line 797 of file AMDGPUDisassembler.cpp.

References llvm::SISrcMods::DST_OP_SEL, llvm::AMDGPU::getNamedOperandIdx(), MI, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, VOPModifiers::NegHi, VOPModifiers::NegLo, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, VOPModifiers::OpSel, and VOPModifiers::OpSelHi.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), and llvm::AMDGPUDisassembler::convertVOP3PDPPInst().

createAMDGPUDisassembler()

static MCDisassembler * createAMDGPUDisassembler ( const Target &  T, const MCSubtargetInfo &  STI, MCContext &  Ctx  )

static

Definition at line 2181 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

createAMDGPUSymbolizer()

static MCSymbolizer * createAMDGPUSymbolizer ( const Triple &  , LLVMOpInfoCallback  , LLVMSymbolLookupCallback  , void *  DisInfo, MCContext *  Ctx, std::unique_ptr< MCRelocationInfo > &&  RelInfo  )

static

Definition at line 2172 of file AMDGPUDisassembler.cpp.

Referenced by LLVMInitializeAMDGPUDisassembler().

DecodeAVLdSt_128RegisterClass()

static DecodeStatus DecodeAVLdSt_128RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 403 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW128.

DecodeAVLdSt_160RegisterClass()

static DecodeStatus DecodeAVLdSt_160RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 410 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW160.

DecodeAVLdSt_32RegisterClass()

static DecodeStatus DecodeAVLdSt_32RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 382 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW32.

DecodeAVLdSt_64RegisterClass()

static DecodeStatus DecodeAVLdSt_64RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 389 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW64.

DecodeAVLdSt_96RegisterClass()

static DecodeStatus DecodeAVLdSt_96RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 396 of file AMDGPUDisassembler.cpp.

References decodeOperand_AVLdSt_Any(), and llvm::AMDGPUDisassembler::OPW96.

decodeBoolReg()

static DecodeStatus decodeBoolReg ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 102 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_AVLdSt_Any()

static DecodeStatus decodeOperand_AVLdSt_Any ( MCInst &  Inst, unsigned  Imm, AMDGPUDisassembler::OpWidthTy  Opw, const MCDisassembler *  Decoder  )

static

Definition at line 347 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::SIInstrFlags::DS, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), IsAGPROperand(), MRI, and TSFlags.

Referenced by DecodeAVLdSt_128RegisterClass(), DecodeAVLdSt_160RegisterClass(), DecodeAVLdSt_32RegisterClass(), DecodeAVLdSt_64RegisterClass(), and DecodeAVLdSt_96RegisterClass().

decodeOperand_KImmFP()

static DecodeStatus decodeOperand_KImmFP ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 320 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeOperand_VSrcT16()

static DecodeStatus decodeOperand_VSrcT16 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 304 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.

decodeOperand_VSrcT16_Lo128()

static DecodeStatus decodeOperand_VSrcT16_Lo128 ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 288 of file AMDGPUDisassembler.cpp.

References addOperand(), assert(), and llvm::AMDGPUDisassembler::OPW16.

decodeOperandVOPDDstY()

static DecodeStatus decodeOperandVOPDDstY ( MCInst &  Inst, unsigned  Val, uint64_t  Addr, const void *  Decoder  )

static

Definition at line 327 of file AMDGPUDisassembler.cpp.

References addOperand().

decodeSMEMOffset()

static DecodeStatus decodeSMEMOffset ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 90 of file AMDGPUDisassembler.cpp.

References addOperand(), llvm::MCOperand::createImm(), and llvm::Offset.

decodeSOPPBrTarget()

static DecodeStatus decodeSOPPBrTarget ( MCInst &  Inst, unsigned  Imm, uint64_t  Addr, const MCDisassembler *  Decoder  )

static

Definition at line 75 of file AMDGPUDisassembler.cpp.

References addOperand(), Addr, llvm::MCOperand::createImm(), llvm::Offset, llvm::APInt::sext(), and llvm::MCDisassembler::Success.

DecodeVGPR_16_Lo128RegisterClass()

static DecodeStatus DecodeVGPR_16_Lo128RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 278 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

DecodeVGPR_16RegisterClass()

static DecodeStatus DecodeVGPR_16RegisterClass ( MCInst &  Inst, unsigned  Imm, uint64_t  , const MCDisassembler *  Decoder  )

static

Definition at line 265 of file AMDGPUDisassembler.cpp.

References addOperand(), and assert().

eat12Bytes()

static DecoderUInt128 eat12Bytes ( ArrayRef< uint8_t > &  Bytes )

inlinestatic

Definition at line 436 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::Hi, llvm::Lo, llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

eatBytes()

template<typename T >

static T eatBytes ( ArrayRef< uint8_t > &  Bytes )

inlinestatic

Definition at line 429 of file AMDGPUDisassembler.cpp.

References assert(), llvm::ArrayRef< T >::data(), llvm::ArrayRef< T >::size(), and llvm::ArrayRef< T >::slice().

getInlineImmVal16()

static int64_t getInlineImmVal16 ( unsigned  Imm )

static

Definition at line 1296 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

getInlineImmVal32()

static int64_t getInlineImmVal32 ( unsigned  Imm )

static

Definition at line 1246 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

getInlineImmVal64()

static int64_t getInlineImmVal64 ( unsigned  Imm )

static

Definition at line 1271 of file AMDGPUDisassembler.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUDisassembler::decodeFPImmed().

insertNamedMCOperand()

static int insertNamedMCOperand ( MCInst &  MI, const MCOperand &  Op, uint16_t  NameIdx  )

static

Definition at line 64 of file AMDGPUDisassembler.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), I, and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertEXPInst(), llvm::AMDGPUDisassembler::convertFMAanyK(), llvm::AMDGPUDisassembler::convertMacDPPInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::AMDGPUDisassembler::convertVINTERPInst(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), and llvm::AMDGPUDisassembler::getInstruction().

IsAGPROperand()

static bool IsAGPROperand ( const MCInst &  Inst, int  OpIdx, const MCRegisterInfo *  MRI  )

static

Definition at line 333 of file AMDGPUDisassembler.cpp.

References llvm::MCInst::getOperand(), and MRI.

isValidDPP8()

static bool isValidDPP8 ( const MCInst &  MI )

static

Definition at line 450 of file AMDGPUDisassembler.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), and MI.

Referenced by llvm::AMDGPUDisassembler::convertDPP8Inst().

LLVMInitializeAMDGPUDisassembler()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler

(

)

Definition at line 2187 of file AMDGPUDisassembler.cpp.

References createAMDGPUDisassembler(), createAMDGPUSymbolizer(), llvm::getTheGCNTarget(), llvm::TargetRegistry::RegisterMCDisassembler(), and llvm::TargetRegistry::RegisterMCSymbolizer().