LLVM 17.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
48class AMDGPUInstructionSelector final : public InstructionSelector {
49private:
50 MachineRegisterInfo *MRI;
51 const GCNSubtarget *Subtarget;
52
53public:
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelKnownBits *KB,
62 CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_CONSTANT(MachineInstr &I) const;
94 bool selectG_FNEG(MachineInstr &I) const;
95 bool selectG_FABS(MachineInstr &I) const;
96 bool selectG_AND_OR_XOR(MachineInstr &I) const;
97 bool selectG_ADD_SUB(MachineInstr &I) const;
98 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
99 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
100 bool selectG_EXTRACT(MachineInstr &I) const;
101 bool selectG_FMA_FMAD(MachineInstr &I) const;
102 bool selectG_MERGE_VALUES(MachineInstr &I) const;
103 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
104 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
105 bool selectG_PTR_ADD(MachineInstr &I) const;
106 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
107 bool selectG_INSERT(MachineInstr &I) const;
108 bool selectG_SBFX_UBFX(MachineInstr &I) const;
109
110 bool selectInterpP1F16(MachineInstr &MI) const;
111 bool selectWritelane(MachineInstr &MI) const;
112 bool selectDivScale(MachineInstr &MI) const;
113 bool selectIntrinsicCmp(MachineInstr &MI) const;
114 bool selectBallot(MachineInstr &I) const;
115 bool selectInverseBallot(MachineInstr &I) const;
116 bool selectRelocConstant(MachineInstr &I) const;
117 bool selectGroupStaticSize(MachineInstr &I) const;
118 bool selectReturnAddress(MachineInstr &I) const;
119 bool selectG_INTRINSIC(MachineInstr &I) const;
120
121 bool selectEndCfIntrinsic(MachineInstr &MI) const;
122 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
123 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
125 bool selectSBarrier(MachineInstr &MI) const;
126 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
127
128 bool selectImageIntrinsic(MachineInstr &MI,
129 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
130 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
131 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
132 bool selectG_ICMP(MachineInstr &I) const;
133 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
134 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
135 SmallVectorImpl<GEPInfo> &AddrInfo) const;
136
137 void initM0(MachineInstr &I) const;
138 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
139 bool selectG_SELECT(MachineInstr &I) const;
140 bool selectG_BRCOND(MachineInstr &I) const;
141 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
142 bool selectG_PTRMASK(MachineInstr &I) const;
143 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
144 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectBufferLoadLds(MachineInstr &MI) const;
146 bool selectGlobalLoadLds(MachineInstr &MI) const;
147 bool selectBVHIntrinsic(MachineInstr &I) const;
148 bool selectSMFMACIntrin(MachineInstr &I) const;
149 bool selectWaveAddress(MachineInstr &I) const;
150
151 std::pair<Register, unsigned>
152 selectVOP3ModsImpl(MachineOperand &Root, bool AllowAbs = true,
153 bool OpSel = false) const;
154
155 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
156 MachineOperand Root, MachineInstr *InsertPt,
157 bool ForceVGPR = false) const;
158
159 InstructionSelector::ComplexRendererFns
160 selectVCSRC(MachineOperand &Root) const;
161
162 InstructionSelector::ComplexRendererFns
163 selectVSRC0(MachineOperand &Root) const;
164
165 InstructionSelector::ComplexRendererFns
166 selectVOP3Mods0(MachineOperand &Root) const;
167 InstructionSelector::ComplexRendererFns
168 selectVOP3BMods0(MachineOperand &Root) const;
169 InstructionSelector::ComplexRendererFns
170 selectVOP3OMods(MachineOperand &Root) const;
171 InstructionSelector::ComplexRendererFns
172 selectVOP3Mods(MachineOperand &Root) const;
173 InstructionSelector::ComplexRendererFns
174 selectVOP3BMods(MachineOperand &Root) const;
175
176 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
177
178 std::pair<Register, unsigned>
179 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
180 bool IsDOT = false) const;
181
182 InstructionSelector::ComplexRendererFns
183 selectVOP3PMods(MachineOperand &Root) const;
184
185 InstructionSelector::ComplexRendererFns
186 selectVOP3PModsDOT(MachineOperand &Root) const;
187
188 InstructionSelector::ComplexRendererFns
189 selectDotIUVOP3PMods(MachineOperand &Root) const;
190
191 InstructionSelector::ComplexRendererFns
192 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
193
194 InstructionSelector::ComplexRendererFns
195 selectVOP3OpSelMods(MachineOperand &Root) const;
196
197 InstructionSelector::ComplexRendererFns
198 selectVINTERPMods(MachineOperand &Root) const;
199 InstructionSelector::ComplexRendererFns
200 selectVINTERPModsHi(MachineOperand &Root) const;
201
202 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
203 int64_t *Offset) const;
204 InstructionSelector::ComplexRendererFns
205 selectSmrdImm(MachineOperand &Root) const;
206 InstructionSelector::ComplexRendererFns
207 selectSmrdImm32(MachineOperand &Root) const;
208 InstructionSelector::ComplexRendererFns
209 selectSmrdSgpr(MachineOperand &Root) const;
210 InstructionSelector::ComplexRendererFns
211 selectSmrdSgprImm(MachineOperand &Root) const;
212
213 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
214 uint64_t FlatVariant) const;
215
216 InstructionSelector::ComplexRendererFns
217 selectFlatOffset(MachineOperand &Root) const;
218 InstructionSelector::ComplexRendererFns
219 selectGlobalOffset(MachineOperand &Root) const;
220 InstructionSelector::ComplexRendererFns
221 selectScratchOffset(MachineOperand &Root) const;
222
223 InstructionSelector::ComplexRendererFns
224 selectGlobalSAddr(MachineOperand &Root) const;
225
226 InstructionSelector::ComplexRendererFns
227 selectScratchSAddr(MachineOperand &Root) const;
228 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
229 uint64_t ImmOffset) const;
230 InstructionSelector::ComplexRendererFns
231 selectScratchSVAddr(MachineOperand &Root) const;
232
233 InstructionSelector::ComplexRendererFns
234 selectMUBUFScratchOffen(MachineOperand &Root) const;
235 InstructionSelector::ComplexRendererFns
236 selectMUBUFScratchOffset(MachineOperand &Root) const;
237
238 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
239 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
240 unsigned Size) const;
241 bool isFlatScratchBaseLegal(
242 Register Base, uint64_t FlatVariant = SIInstrFlags::FlatScratch) const;
243
244 std::pair<Register, unsigned>
245 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
246 InstructionSelector::ComplexRendererFns
247 selectDS1Addr1Offset(MachineOperand &Root) const;
248
249 InstructionSelector::ComplexRendererFns
250 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
251
252 InstructionSelector::ComplexRendererFns
253 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
254
255 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
256 unsigned size) const;
257 InstructionSelector::ComplexRendererFns
258 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
259
260 std::pair<Register, int64_t>
261 getPtrBaseWithConstantOffset(Register Root,
262 const MachineRegisterInfo &MRI) const;
263
264 // Parse out a chain of up to two g_ptr_add instructions.
265 // g_ptr_add (n0, _)
266 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
267 struct MUBUFAddressData {
268 Register N0, N2, N3;
269 int64_t Offset = 0;
270 };
271
272 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
273
274 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
275 Register &SOffset, int64_t &ImmOffset) const;
276
277 MUBUFAddressData parseMUBUFAddress(Register Src) const;
278
279 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
280 Register &RSrcReg, Register &SOffset,
281 int64_t &Offset) const;
282
283 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
284 Register &SOffset, int64_t &Offset) const;
285
286 InstructionSelector::ComplexRendererFns
287 selectMUBUFAddr64(MachineOperand &Root) const;
288
289 InstructionSelector::ComplexRendererFns
290 selectMUBUFOffset(MachineOperand &Root) const;
291
292 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
293 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
294 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
295
296 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
297 bool &Matched) const;
298 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
299 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
300
301 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
302 int OpIdx = -1) const;
303
304 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
305 int OpIdx) const;
306
307 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
308 int OpIdx) const;
309
310 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
311 int OpIdx) const;
312
313 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
314 int OpIdx) const;
315
316 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
317 int OpIdx) const;
318 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
319 int OpIdx) const;
320 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
321 int OpIdx) const;
322 void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
323 int OpIdx) const;
324
325 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
326 int OpIdx) const;
327
328 bool isInlineImmediate16(int64_t Imm) const;
329 bool isInlineImmediate32(int64_t Imm) const;
330 bool isInlineImmediate64(int64_t Imm) const;
331 bool isInlineImmediate(const APFloat &Imm) const;
332
333 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
334 // shift amount operand's `ShAmtBits` bits is unneeded.
335 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
336
337 const SIInstrInfo &TII;
338 const SIRegisterInfo &TRI;
339 const AMDGPURegisterBankInfo &RBI;
340 const AMDGPUTargetMachine &TM;
341 const GCNSubtarget &STI;
342 bool EnableLateStructurizeCFG;
343#define GET_GLOBALISEL_PREDICATES_DECL
344#define AMDGPUSubtarget GCNSubtarget
345#include "AMDGPUGenGlobalISel.inc"
346#undef GET_GLOBALISEL_PREDICATES_DECL
347#undef AMDGPUSubtarget
348
349#define GET_GLOBALISEL_TEMPORARIES_DECL
350#include "AMDGPUGenGlobalISel.inc"
351#undef GET_GLOBALISEL_TEMPORARIES_DECL
352};
353
354} // End llvm namespace.
355#endif
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2604
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
I
#define I(x, y, z)
Definition: MD5.cpp:58
Reg
unsigned Reg
Definition: MachineSink.cpp:1619
P
#define P(N)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
Definition: AMDGPUInstructionSelector.cpp:65
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3320
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:442
llvm::InstructionSelector::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: InstructionSelector.h:485
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:68
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:440
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