LLVM 24.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class MCRegisterClass;
47using TargetRegisterClass = MCRegisterClass;
48
49class AMDGPUInstructionSelector final : public InstructionSelector {
50private:
51 MachineRegisterInfo *MRI;
52 const GCNSubtarget *Subtarget;
53
54public:
55 AMDGPUInstructionSelector(const GCNSubtarget &STI,
56 const AMDGPURegisterBankInfo &RBI);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectS16MergeToS32(MachineInstr &MI) const;
105 bool selectS16MergeToWide(MachineInstr &MI) const;
106 bool selectG_MERGE_VALUES(MachineInstr &I) const;
107 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
108 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
109 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
110 bool selectG_INSERT(MachineInstr &I) const;
111 bool selectG_SBFX_UBFX(MachineInstr &I) const;
112
113 bool selectInterpP1F16(MachineInstr &MI) const;
114 bool selectWritelane(MachineInstr &MI) const;
115 bool selectDivScale(MachineInstr &MI) const;
116 bool selectBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectInitWholeWave(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
130 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectTensorLoadStore(MachineInstr &MI, Intrinsic::ID IID) const;
149 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;
150 bool selectSMFMACIntrin(MachineInstr &I) const;
151 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
152 bool selectWaveAddress(MachineInstr &I) const;
153 bool selectBITOP3(MachineInstr &I) const;
154 bool selectStackRestore(MachineInstr &MI) const;
155 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
156 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
159 bool selectWaveShuffleIntrin(MachineInstr &I) const;
160
161 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
162 bool IsCanonicalizing = true,
163 bool AllowAbs = true,
164 bool OpSel = false) const;
165 std::pair<Register, unsigned> selectVOP3PModsF32Impl(Register Src) const;
166
167 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
168 MachineOperand Root, MachineInstr *InsertPt,
169 bool ForceVGPR = false) const;
170
171 Register widenSrcIfVGPR16(Register Src, MachineInstr *InsertPt) const;
172
173 InstructionSelector::ComplexRendererFns
174 selectVCSRC(MachineOperand &Root) const;
175
176 InstructionSelector::ComplexRendererFns
177 selectVSRC0(MachineOperand &Root) const;
178
179 InstructionSelector::ComplexRendererFns
180 selectVOP3Mods0(MachineOperand &Root) const;
181 InstructionSelector::ComplexRendererFns
182 selectVOP3BMods0(MachineOperand &Root) const;
183 InstructionSelector::ComplexRendererFns
184 selectVOP3OMods(MachineOperand &Root) const;
185 InstructionSelector::ComplexRendererFns
186 selectVOP3Mods(MachineOperand &Root) const;
187 InstructionSelector::ComplexRendererFns
188 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
189 InstructionSelector::ComplexRendererFns
190 selectVOP3BMods(MachineOperand &Root) const;
191
192 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
193
194 std::pair<Register, unsigned>
195 selectVOP3PModsImpl(Register RootReg, const MachineRegisterInfo &MRI,
196 bool IsDOT = false) const;
197 InstructionSelector::ComplexRendererFns
198 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;
199
200 InstructionSelector::ComplexRendererFns
201 selectVOP3PMods(MachineOperand &Root) const;
202
203 InstructionSelector::ComplexRendererFns
204 selectVOP3PModsDOT(MachineOperand &Root) const;
205 InstructionSelector::ComplexRendererFns
206 selectVOP3PNoModsDOT(MachineOperand &Root) const;
207 InstructionSelector::ComplexRendererFns
208 selectVOP3PModsF32(MachineOperand &Root) const;
209 InstructionSelector::ComplexRendererFns
210 selectVOP3PNoModsF32(MachineOperand &Root) const;
211
212 InstructionSelector::ComplexRendererFns
213 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
214
215 InstructionSelector::ComplexRendererFns
216 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
217 InstructionSelector::ComplexRendererFns
218 selectWMMAModsF16Neg(MachineOperand &Root) const;
219 InstructionSelector::ComplexRendererFns
220 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
221 InstructionSelector::ComplexRendererFns
222 selectWMMAVISrc(MachineOperand &Root) const;
223 InstructionSelector::ComplexRendererFns
224 selectSWMMACIndex8(MachineOperand &Root) const;
225 InstructionSelector::ComplexRendererFns
226 selectSWMMACIndex16(MachineOperand &Root) const;
227 InstructionSelector::ComplexRendererFns
228 selectSWMMACIndex32(MachineOperand &Root) const;
229
230 InstructionSelector::ComplexRendererFns
231 selectVOP3OpSelMods(MachineOperand &Root) const;
232
233 InstructionSelector::ComplexRendererFns
234 selectVINTERPMods(MachineOperand &Root) const;
235 InstructionSelector::ComplexRendererFns
236 selectVINTERPModsHi(MachineOperand &Root) const;
237
238 bool selectScaleOffset(MachineOperand &Root, Register &Offset,
239 bool IsSigned) const;
240 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
241 int64_t *Offset, bool *ScaleOffset) const;
242 InstructionSelector::ComplexRendererFns
243 selectSmrdImm(MachineOperand &Root) const;
244 InstructionSelector::ComplexRendererFns
245 selectSmrdImm32(MachineOperand &Root) const;
246 InstructionSelector::ComplexRendererFns
247 selectSmrdSgpr(MachineOperand &Root) const;
248 InstructionSelector::ComplexRendererFns
249 selectSmrdSgprImm(MachineOperand &Root) const;
250
251 std::pair<Register, int>
252 selectFlatOffsetImpl(MachineOperand &Root,
253 AMDGPU::FlatAddrSpace FlatVariant) const;
254
255 InstructionSelector::ComplexRendererFns
256 selectFlatOffset(MachineOperand &Root) const;
257 InstructionSelector::ComplexRendererFns
258 selectGlobalOffset(MachineOperand &Root) const;
259 InstructionSelector::ComplexRendererFns
260 selectScratchOffset(MachineOperand &Root) const;
261
262 InstructionSelector::ComplexRendererFns
263 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,
264 bool NeedIOffset = true) const;
265 InstructionSelector::ComplexRendererFns
266 selectGlobalSAddr(MachineOperand &Root) const;
267 InstructionSelector::ComplexRendererFns
268 selectGlobalSAddrCPol(MachineOperand &Root) const;
269 InstructionSelector::ComplexRendererFns
270 selectGlobalSAddrCPolM0(MachineOperand &Root) const;
271 InstructionSelector::ComplexRendererFns
272 selectGlobalSAddrGLC(MachineOperand &Root) const;
273 InstructionSelector::ComplexRendererFns
274 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;
275 InstructionSelector::ComplexRendererFns
276 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;
277
278 InstructionSelector::ComplexRendererFns
279 selectScratchSAddr(MachineOperand &Root) const;
280 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
281 uint64_t ImmOffset) const;
282 InstructionSelector::ComplexRendererFns
283 selectScratchSVAddr(MachineOperand &Root) const;
284
285 InstructionSelector::ComplexRendererFns
286 selectMUBUFScratchOffen(MachineOperand &Root) const;
287 InstructionSelector::ComplexRendererFns
288 selectMUBUFScratchOffset(MachineOperand &Root) const;
289
290 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
291 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
292 unsigned Size) const;
293 bool isFlatScratchBaseLegal(Register Addr) const;
294 bool isFlatScratchBaseLegalSV(Register Addr) const;
295 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
296
297 std::pair<Register, unsigned>
298 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
299 InstructionSelector::ComplexRendererFns
300 selectDS1Addr1Offset(MachineOperand &Root) const;
301
302 InstructionSelector::ComplexRendererFns
303 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
304
305 InstructionSelector::ComplexRendererFns
306 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
307
308 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
309 unsigned size) const;
310 InstructionSelector::ComplexRendererFns
311 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
312
313 std::tuple<Register, int64_t, bool>
314 getPtrBaseWithConstantOffset(Register Root,
315 const MachineRegisterInfo &MRI) const;
316
317 // Parse out a chain of up to two g_ptr_add instructions.
318 // g_ptr_add (n0, _)
319 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
320 struct MUBUFAddressData {
321 Register N0, N2, N3;
322 int64_t Offset = 0;
323 };
324
325 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
326
327 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
328 Register &SOffset, int64_t &ImmOffset) const;
329
330 MUBUFAddressData parseMUBUFAddress(Register Src) const;
331
332 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
333 Register &RSrcReg, Register &SOffset,
334 int64_t &Offset) const;
335
336 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
337 Register &SOffset, int64_t &Offset) const;
338
339 InstructionSelector::ComplexRendererFns
340 selectBUFSOffset(MachineOperand &Root) const;
341
342 InstructionSelector::ComplexRendererFns
343 selectMUBUFAddr64(MachineOperand &Root) const;
344
345 InstructionSelector::ComplexRendererFns
346 selectMUBUFOffset(MachineOperand &Root) const;
347
348 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
349 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
350 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
351
352 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
353 bool &Matched) const;
354 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
355 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
356 ComplexRendererFns selectVOP3PMadMixModsExtNeg(MachineOperand &Root) const;
357 ComplexRendererFns selectVOP3PMadMixModsNeg(MachineOperand &Root) const;
358
359 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
360 int OpIdx = -1) const;
361
362 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
363 int OpIdx) const;
364 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
365 int OpIdx) const;
366
367 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
368 int OpIdx) const;
369
370 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
371 const MachineInstr &MI,
372 int OpIdx) const;
373
374 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
375 const MachineInstr &MI,
376 int OpIdx) const;
377
378 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
379 const MachineInstr &MI,
380 int OpIdx) const;
381
382 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
383 const MachineInstr &MI,
384 int OpIdx) const;
385
386 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
387 const MachineInstr &MI, int OpIdx) const;
388
389 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
390 const MachineInstr &MI, int OpIdx) const;
391
392 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,
393 const MachineInstr &MI,
394 int OpIdx) const;
395
396 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,
397 const MachineInstr &MI, int OpIdx) const;
398
399 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
400 int OpIdx) const;
401
402 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
403 int OpIdx) const;
404
405 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
406 int OpIdx) const {
407 renderBitcastFPImm(MIB, MI, OpIdx);
408 }
409 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
410 int OpIdx) const {
411 renderBitcastFPImm(MIB, MI, OpIdx);
412 }
413
414 void renderCountTrailingOnesImm(MachineInstrBuilder &MIB,
415 const MachineInstr &MI, int OpIdx) const;
416 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
417 int OpIdx) const;
418 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
419 int OpIdx) const;
420 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
421 int OpIdx) const;
422
423 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
424 int OpIdx) const;
425
426 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
427 int OpIdx) const;
428
429 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,
430 int OpIdx) const;
431 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,
432 int OpIdx) const;
433 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,
434 int OpIdx) const;
435
436 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,
437 int OpIdx) const;
438
439 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,
440 const MachineInstr &MI, int OpIdx) const;
441
442 bool isInlineImmediate(const APInt &Imm) const;
443 bool isInlineImmediate(const APFloat &Imm) const;
444
445 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
446 // shift amount operand's `ShAmtBits` bits is unneeded.
447 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
448
449 /// Match a zero extend from a 32-bit value to 64-bits.
450 Register matchZeroExtendFromS32(Register Reg) const;
451 /// Match a sign extend from a 32-bit value to 64-bits.
452 Register matchSignExtendFromS32(Register Reg) const;
453 /// Match a zero extend from a 32-bit value to 64-bits, or \p Reg itself if it
454 /// is 32-bit.
455 Register matchZeroExtendFromS32OrS32(Register Reg) const;
456 /// Match a sign extend from a 32-bit value to 64-bits, or \p Reg itself if it
457 /// is 32-bit.
458 Register matchSignExtendFromS32OrS32(Register Reg) const;
459 /// Match either sign or zero extend depending on the \p IsSigned from a
460 /// 32-bit value to 64-bits, or \p Reg itself if it is 32-bit.
461 Register matchExtendFromS32OrS32(Register Reg, bool IsSigned) const;
462 /// Match an any extend from a 32-bit value to 64-bit.
463 Register matchAnyExtendFromS32(Register Reg) const;
464
465 const SIInstrInfo &TII;
466 const SIRegisterInfo &TRI;
467 const AMDGPURegisterBankInfo &RBI;
468 const GCNSubtarget &STI;
469#define GET_GLOBALISEL_PREDICATES_DECL
470#define AMDGPUSubtarget GCNSubtarget
471#include "AMDGPUGenGlobalISel.inc"
472#undef GET_GLOBALISEL_PREDICATES_DECL
473#undef AMDGPUSubtarget
474
475#define GET_GLOBALISEL_TEMPORARIES_DECL
476#include "AMDGPUGenGlobalISel.inc"
477#undef GET_GLOBALISEL_TEMPORARIES_DECL
478};
479
480} // End llvm namespace.
481#endif
Imm
unsigned Imm
Definition AMDGPUDisassembler.cpp:524
uint64_t
unsigned uint64_t
Definition AMDGPUDisassembler.cpp:525
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:854
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2127
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
P
#define P(N)
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI)
Definition AMDGPUInstructionSelector.cpp:42
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition AMDGPUInstructionSelector.cpp:4524
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelValueTracking *VT, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition AMDGPUInstructionSelector.cpp:56
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition GIMatchTableExecutor.h:633
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition MCRegisterInfo.h:37
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:238
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition RegisterBank.h:30
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:592
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1252
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1669
llvm::VectorInstrContext::Load
@ Load
The value being inserted comes from a load (InsertElement only).
Definition TargetTransformInfo.h:191
llvm::TargetRegisterClass
MCRegisterClass TargetRegisterClass
Definition FastISel.h:58
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