LLVM  13.0.0git
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
17 #include "llvm/CodeGen/Register.h"
18 #include "llvm/IR/InstrTypes.h"
19 #include "llvm/IR/Intrinsics.h"
20 #include "llvm/IR/IntrinsicsAMDGPU.h"
21 
22 namespace {
23 #define GET_GLOBALISEL_PREDICATE_BITSET
24 #define AMDGPUSubtarget GCNSubtarget
25 #include "AMDGPUGenGlobalISel.inc"
26 #undef GET_GLOBALISEL_PREDICATE_BITSET
27 #undef AMDGPUSubtarget
28 }
29 
30 namespace llvm {
31 
32 namespace AMDGPU {
33 struct ImageDimIntrinsicInfo;
34 }
35 
36 class AMDGPUInstrInfo;
37 class AMDGPURegisterBankInfo;
38 class AMDGPUTargetMachine;
39 class BlockFrequencyInfo;
40 class ProfileSummaryInfo;
41 class GCNSubtarget;
42 class MachineInstr;
43 class MachineIRBuilder;
44 class MachineOperand;
45 class MachineRegisterInfo;
46 class RegisterBank;
47 class SIInstrInfo;
48 class SIMachineFunctionInfo;
49 class SIRegisterInfo;
50 class TargetRegisterClass;
51 
53 private:
55  const GCNSubtarget *Subtarget;
56 
57 public:
59  const AMDGPURegisterBankInfo &RBI,
60  const AMDGPUTargetMachine &TM);
61 
62  bool select(MachineInstr &I) override;
63  static const char *getName();
64 
67  BlockFrequencyInfo *BFI) override;
68 
69 private:
70  struct GEPInfo {
71  const MachineInstr &GEP;
72  SmallVector<unsigned, 2> SgprParts;
73  SmallVector<unsigned, 2> VgprParts;
74  int64_t Imm;
75  GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
76  };
77 
78  bool isSGPR(Register Reg) const;
79 
80  bool isInstrUniform(const MachineInstr &MI) const;
81  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
82 
83  const RegisterBank *getArtifactRegBank(
85  const TargetRegisterInfo &TRI) const;
86 
87  /// tblgen-erated 'select' implementation.
88  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
89 
90  MachineOperand getSubOperand64(MachineOperand &MO,
91  const TargetRegisterClass &SubRC,
92  unsigned SubIdx) const;
93 
94  bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
95  bool selectCOPY(MachineInstr &I) const;
96  bool selectPHI(MachineInstr &I) const;
97  bool selectG_TRUNC(MachineInstr &I) const;
98  bool selectG_SZA_EXT(MachineInstr &I) const;
99  bool selectG_CONSTANT(MachineInstr &I) const;
100  bool selectG_FNEG(MachineInstr &I) const;
101  bool selectG_FABS(MachineInstr &I) const;
102  bool selectG_AND_OR_XOR(MachineInstr &I) const;
103  bool selectG_ADD_SUB(MachineInstr &I) const;
104  bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
105  bool selectG_EXTRACT(MachineInstr &I) const;
106  bool selectG_MERGE_VALUES(MachineInstr &I) const;
107  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
108  bool selectG_BUILD_VECTOR_TRUNC(MachineInstr &I) const;
109  bool selectG_PTR_ADD(MachineInstr &I) const;
110  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
111  bool selectG_INSERT(MachineInstr &I) const;
112 
113  bool selectInterpP1F16(MachineInstr &MI) const;
114  bool selectWritelane(MachineInstr &MI) const;
115  bool selectDivScale(MachineInstr &MI) const;
116  bool selectIntrinsicIcmp(MachineInstr &MI) const;
117  bool selectBallot(MachineInstr &I) const;
118  bool selectRelocConstant(MachineInstr &I) const;
119  bool selectGroupStaticSize(MachineInstr &I) const;
120  bool selectReturnAddress(MachineInstr &I) const;
121  bool selectG_INTRINSIC(MachineInstr &I) const;
122 
123  bool selectEndCfIntrinsic(MachineInstr &MI) const;
124  bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125  bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
126  bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
127  bool selectSBarrier(MachineInstr &MI) const;
128 
129  bool selectImageIntrinsic(MachineInstr &MI,
130  const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133  bool selectG_ICMP(MachineInstr &I) const;
134  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136  SmallVectorImpl<GEPInfo> &AddrInfo) const;
137  bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
138 
139  void initM0(MachineInstr &I) const;
140  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
141  bool selectG_AMDGPU_ATOMIC_CMPXCHG(MachineInstr &I) const;
142  bool selectG_SELECT(MachineInstr &I) const;
143  bool selectG_BRCOND(MachineInstr &I) const;
144  bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
145  bool selectG_PTRMASK(MachineInstr &I) const;
146  bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
147  bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
148  bool selectG_SHUFFLE_VECTOR(MachineInstr &I) const;
149  bool selectAMDGPU_BUFFER_ATOMIC_FADD(MachineInstr &I) const;
150  bool selectGlobalAtomicFadd(MachineInstr &I, MachineOperand &AddrOp,
151  MachineOperand &DataOp) const;
152  bool selectBVHIntrinsic(MachineInstr &I) const;
153 
154  std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
155  bool AllowAbs = true) const;
156 
158  selectVCSRC(MachineOperand &Root) const;
159 
161  selectVSRC0(MachineOperand &Root) const;
162 
164  selectVOP3Mods0(MachineOperand &Root) const;
166  selectVOP3BMods0(MachineOperand &Root) const;
168  selectVOP3OMods(MachineOperand &Root) const;
170  selectVOP3Mods(MachineOperand &Root) const;
172  selectVOP3BMods(MachineOperand &Root) const;
173 
174  ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
175 
177  selectVOP3Mods_nnan(MachineOperand &Root) const;
178 
179  std::pair<Register, unsigned>
180  selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
181 
183  selectVOP3PMods(MachineOperand &Root) const;
184 
186  selectVOP3OpSelMods(MachineOperand &Root) const;
187 
189  selectSmrdImm(MachineOperand &Root) const;
191  selectSmrdImm32(MachineOperand &Root) const;
193  selectSmrdSgpr(MachineOperand &Root) const;
194 
195  std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
196  uint64_t FlatVariant) const;
197 
199  selectFlatOffset(MachineOperand &Root) const;
201  selectGlobalOffset(MachineOperand &Root) const;
203  selectScratchOffset(MachineOperand &Root) const;
204 
206  selectGlobalSAddr(MachineOperand &Root) const;
207 
209  selectScratchSAddr(MachineOperand &Root) const;
210 
212  selectMUBUFScratchOffen(MachineOperand &Root) const;
214  selectMUBUFScratchOffset(MachineOperand &Root) const;
215 
216  bool isDSOffsetLegal(Register Base, int64_t Offset) const;
217  bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
218  unsigned Size) const;
219 
220  std::pair<Register, unsigned>
221  selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
223  selectDS1Addr1Offset(MachineOperand &Root) const;
224 
226  selectDS64Bit4ByteAligned(MachineOperand &Root) const;
227 
229  selectDS128Bit8ByteAligned(MachineOperand &Root) const;
230 
231  std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
232  unsigned size) const;
234  selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
235 
236  std::pair<Register, int64_t>
237  getPtrBaseWithConstantOffset(Register Root,
238  const MachineRegisterInfo &MRI) const;
239 
240  // Parse out a chain of up to two g_ptr_add instructions.
241  // g_ptr_add (n0, _)
242  // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
243  struct MUBUFAddressData {
244  Register N0, N2, N3;
245  int64_t Offset = 0;
246  };
247 
248  bool shouldUseAddr64(MUBUFAddressData AddrData) const;
249 
250  void splitIllegalMUBUFOffset(MachineIRBuilder &B,
251  Register &SOffset, int64_t &ImmOffset) const;
252 
253  MUBUFAddressData parseMUBUFAddress(Register Src) const;
254 
255  bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
256  Register &RSrcReg, Register &SOffset,
257  int64_t &Offset) const;
258 
259  bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
260  Register &SOffset, int64_t &Offset) const;
261 
263  selectMUBUFAddr64(MachineOperand &Root) const;
264 
266  selectMUBUFOffset(MachineOperand &Root) const;
267 
269  selectMUBUFOffsetAtomic(MachineOperand &Root) const;
270 
272  selectMUBUFAddr64Atomic(MachineOperand &Root) const;
273 
274  ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
275  ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
276 
277  void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
278  int OpIdx = -1) const;
279 
280  void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
281  int OpIdx) const;
282 
283  void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
284  int OpIdx) const;
285 
286  void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
287  int OpIdx) const;
288 
289  void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
290  int OpIdx) const;
291  void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
292  int OpIdx) const;
293  void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
294  int OpIdx) const;
295  void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
296  int OpIdx) const;
297 
298  void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
299  int OpIdx) const;
300 
301  bool isInlineImmediate16(int64_t Imm) const;
302  bool isInlineImmediate32(int64_t Imm) const;
303  bool isInlineImmediate64(int64_t Imm) const;
304  bool isInlineImmediate(const APFloat &Imm) const;
305 
306  const SIInstrInfo &TII;
307  const SIRegisterInfo &TRI;
308  const AMDGPURegisterBankInfo &RBI;
309  const AMDGPUTargetMachine &TM;
310  const GCNSubtarget &STI;
311  bool EnableLateStructurizeCFG;
312 #define GET_GLOBALISEL_PREDICATES_DECL
313 #define AMDGPUSubtarget GCNSubtarget
314 #include "AMDGPUGenGlobalISel.inc"
315 #undef GET_GLOBALISEL_PREDICATES_DECL
316 #undef AMDGPUSubtarget
317 
318 #define GET_GLOBALISEL_TEMPORARIES_DECL
319 #include "AMDGPUGenGlobalISel.inc"
320 #undef GET_GLOBALISEL_TEMPORARIES_DECL
321 };
322 
323 } // End llvm namespace.
324 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AMDGPURegisterBankInfo
Definition: AMDGPURegisterBankInfo.h:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector< unsigned, 2 >
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:50
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Optional
Definition: APInt.h:33
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:27
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3052
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1965
Intrinsics.h
InstrTypes.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:439
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
InstructionSelector.h
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:441
llvm::APFloat
Definition: APFloat.h:701
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:423
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:20
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUInstructionSelector
Definition: AMDGPUInstructionSelector.h:52
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1463
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:443
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:442
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
Definition: AMDGPUInstructionSelector.cpp:63
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition: AMDGPUInstructionSelector.cpp:45
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
Register.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38