LLVM 18.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
48class AMDGPUInstructionSelector final : public InstructionSelector {
49private:
50 MachineRegisterInfo *MRI;
51 const GCNSubtarget *Subtarget;
52
53public:
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelKnownBits *KB,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_FPEXT(MachineInstr &I) const;
94 bool selectG_CONSTANT(MachineInstr &I) const;
95 bool selectG_FNEG(MachineInstr &I) const;
96 bool selectG_FABS(MachineInstr &I) const;
97 bool selectG_AND_OR_XOR(MachineInstr &I) const;
98 bool selectG_ADD_SUB(MachineInstr &I) const;
99 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
100 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
101 bool selectG_EXTRACT(MachineInstr &I) const;
102 bool selectG_FMA_FMAD(MachineInstr &I) const;
103 bool selectG_MERGE_VALUES(MachineInstr &I) const;
104 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
105 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
106 bool selectG_PTR_ADD(MachineInstr &I) const;
107 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
108 bool selectG_INSERT(MachineInstr &I) const;
109 bool selectG_SBFX_UBFX(MachineInstr &I) const;
110
111 bool selectInterpP1F16(MachineInstr &MI) const;
112 bool selectWritelane(MachineInstr &MI) const;
113 bool selectDivScale(MachineInstr &MI) const;
114 bool selectIntrinsicCmp(MachineInstr &MI) const;
115 bool selectBallot(MachineInstr &I) const;
116 bool selectInverseBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectSBarrier(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
130 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectBVHIntrinsic(MachineInstr &I) const;
149 bool selectSMFMACIntrin(MachineInstr &I) const;
150 bool selectWaveAddress(MachineInstr &I) const;
151 bool selectStackRestore(MachineInstr &MI) const;
152
153 std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root,
154 bool IsCanonicalizing = true,
155 bool AllowAbs = true,
156 bool OpSel = false) const;
157
158 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
159 MachineOperand Root, MachineInstr *InsertPt,
160 bool ForceVGPR = false) const;
161
162 InstructionSelector::ComplexRendererFns
163 selectVCSRC(MachineOperand &Root) const;
164
165 InstructionSelector::ComplexRendererFns
166 selectVSRC0(MachineOperand &Root) const;
167
168 InstructionSelector::ComplexRendererFns
169 selectVOP3Mods0(MachineOperand &Root) const;
170 InstructionSelector::ComplexRendererFns
171 selectVOP3BMods0(MachineOperand &Root) const;
172 InstructionSelector::ComplexRendererFns
173 selectVOP3OMods(MachineOperand &Root) const;
174 InstructionSelector::ComplexRendererFns
175 selectVOP3Mods(MachineOperand &Root) const;
176 InstructionSelector::ComplexRendererFns
177 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
178 InstructionSelector::ComplexRendererFns
179 selectVOP3BMods(MachineOperand &Root) const;
180
181 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
182
183 std::pair<Register, unsigned>
184 selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
185 bool IsDOT = false) const;
186
187 InstructionSelector::ComplexRendererFns
188 selectVOP3PMods(MachineOperand &Root) const;
189
190 InstructionSelector::ComplexRendererFns
191 selectVOP3PModsDOT(MachineOperand &Root) const;
192
193 InstructionSelector::ComplexRendererFns
194 selectDotIUVOP3PMods(MachineOperand &Root) const;
195
196 InstructionSelector::ComplexRendererFns
197 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
198
199 InstructionSelector::ComplexRendererFns
200 selectVOP3OpSelMods(MachineOperand &Root) const;
201
202 InstructionSelector::ComplexRendererFns
203 selectVINTERPMods(MachineOperand &Root) const;
204 InstructionSelector::ComplexRendererFns
205 selectVINTERPModsHi(MachineOperand &Root) const;
206
207 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
208 int64_t *Offset) const;
209 InstructionSelector::ComplexRendererFns
210 selectSmrdImm(MachineOperand &Root) const;
211 InstructionSelector::ComplexRendererFns
212 selectSmrdImm32(MachineOperand &Root) const;
213 InstructionSelector::ComplexRendererFns
214 selectSmrdSgpr(MachineOperand &Root) const;
215 InstructionSelector::ComplexRendererFns
216 selectSmrdSgprImm(MachineOperand &Root) const;
217
218 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
219 uint64_t FlatVariant) const;
220
221 InstructionSelector::ComplexRendererFns
222 selectFlatOffset(MachineOperand &Root) const;
223 InstructionSelector::ComplexRendererFns
224 selectGlobalOffset(MachineOperand &Root) const;
225 InstructionSelector::ComplexRendererFns
226 selectScratchOffset(MachineOperand &Root) const;
227
228 InstructionSelector::ComplexRendererFns
229 selectGlobalSAddr(MachineOperand &Root) const;
230
231 InstructionSelector::ComplexRendererFns
232 selectScratchSAddr(MachineOperand &Root) const;
233 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
234 uint64_t ImmOffset) const;
235 InstructionSelector::ComplexRendererFns
236 selectScratchSVAddr(MachineOperand &Root) const;
237
238 InstructionSelector::ComplexRendererFns
239 selectMUBUFScratchOffen(MachineOperand &Root) const;
240 InstructionSelector::ComplexRendererFns
241 selectMUBUFScratchOffset(MachineOperand &Root) const;
242
243 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
244 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
245 unsigned Size) const;
246 bool isFlatScratchBaseLegal(
247 Register Base, uint64_t FlatVariant = SIInstrFlags::FlatScratch) const;
248
249 std::pair<Register, unsigned>
250 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
251 InstructionSelector::ComplexRendererFns
252 selectDS1Addr1Offset(MachineOperand &Root) const;
253
254 InstructionSelector::ComplexRendererFns
255 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
256
257 InstructionSelector::ComplexRendererFns
258 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
259
260 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
261 unsigned size) const;
262 InstructionSelector::ComplexRendererFns
263 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
264
265 std::pair<Register, int64_t>
266 getPtrBaseWithConstantOffset(Register Root,
267 const MachineRegisterInfo &MRI) const;
268
269 // Parse out a chain of up to two g_ptr_add instructions.
270 // g_ptr_add (n0, _)
271 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
272 struct MUBUFAddressData {
273 Register N0, N2, N3;
274 int64_t Offset = 0;
275 };
276
277 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
278
279 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
280 Register &SOffset, int64_t &ImmOffset) const;
281
282 MUBUFAddressData parseMUBUFAddress(Register Src) const;
283
284 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
285 Register &RSrcReg, Register &SOffset,
286 int64_t &Offset) const;
287
288 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
289 Register &SOffset, int64_t &Offset) const;
290
291 InstructionSelector::ComplexRendererFns
292 selectMUBUFAddr64(MachineOperand &Root) const;
293
294 InstructionSelector::ComplexRendererFns
295 selectMUBUFOffset(MachineOperand &Root) const;
296
297 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
298 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
299 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
300
301 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
302 bool &Matched) const;
303 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
304 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
305
306 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
307 int OpIdx = -1) const;
308
309 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
310 int OpIdx) const;
311
312 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
313 int OpIdx) const;
314
315 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
316 int OpIdx) const;
317
318 void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
319 int OpIdx) const;
320
321 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
322 int OpIdx) const;
323 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
324 int OpIdx) const;
325 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
326 int OpIdx) const;
327 void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
328 int OpIdx) const;
329
330 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
331 int OpIdx) const;
332
333 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
334 int OpIdx) const;
335
336 bool isInlineImmediate16(int64_t Imm) const;
337 bool isInlineImmediate32(int64_t Imm) const;
338 bool isInlineImmediate64(int64_t Imm) const;
339 bool isInlineImmediate(const APFloat &Imm) const;
340
341 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
342 // shift amount operand's `ShAmtBits` bits is unneeded.
343 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
344
345 const SIInstrInfo &TII;
346 const SIRegisterInfo &TRI;
347 const AMDGPURegisterBankInfo &RBI;
348 const AMDGPUTargetMachine &TM;
349 const GCNSubtarget &STI;
350 bool EnableLateStructurizeCFG;
351#define GET_GLOBALISEL_PREDICATES_DECL
352#define AMDGPUSubtarget GCNSubtarget
353#include "AMDGPUGenGlobalISel.inc"
354#undef GET_GLOBALISEL_PREDICATES_DECL
355#undef AMDGPUSubtarget
356
357#define GET_GLOBALISEL_TEMPORARIES_DECL
358#include "AMDGPUGenGlobalISel.inc"
359#undef GET_GLOBALISEL_TEMPORARIES_DECL
360};
361
362} // End llvm namespace.
363#endif
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2669
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:111
I
#define I(x, y, z)
Definition: MD5.cpp:58
Reg
unsigned Reg
Definition: MachineSink.cpp:1863
P
#define P(N)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3517
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition: AMDGPUInstructionSelector.cpp:66
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:748
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition: GIMatchTableExecutor.h:538
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:68
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:440
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