LLVM 22.0.0git
AMDGPUInstructionSelector.h
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1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
16#include "SIDefines.h"
17#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
18#include "llvm/IR/InstrTypes.h"
19
20namespace {
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
25#undef AMDGPUSubtarget
26}
27
28namespace llvm {
29
30namespace AMDGPU {
31struct ImageDimIntrinsicInfo;
32}
33
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
38class GCNSubtarget;
39class MachineInstr;
40class MachineIRBuilder;
41class MachineOperand;
42class MachineRegisterInfo;
43class RegisterBank;
44class SIInstrInfo;
45class SIRegisterInfo;
46class TargetRegisterClass;
47
48class AMDGPUInstructionSelector final : public InstructionSelector {
49private:
50 MachineRegisterInfo *MRI;
51 const GCNSubtarget *Subtarget;
52
53public:
54 AMDGPUInstructionSelector(const GCNSubtarget &STI,
55 const AMDGPURegisterBankInfo &RBI,
56 const AMDGPUTargetMachine &TM);
57
58 bool select(MachineInstr &I) override;
59 static const char *getName();
60
61 void setupMF(MachineFunction &MF, GISelValueTracking *VT,
62 CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI,
63 BlockFrequencyInfo *BFI) override;
64
65private:
66 struct GEPInfo {
67 SmallVector<unsigned, 2> SgprParts;
68 SmallVector<unsigned, 2> VgprParts;
69 int64_t Imm = 0;
70 };
71
72 bool isSGPR(Register Reg) const;
73
74 bool isInstrUniform(const MachineInstr &MI) const;
75 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
76
77 const RegisterBank *getArtifactRegBank(
78 Register Reg, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI) const;
80
81 /// tblgen-erated 'select' implementation.
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83
84 MachineOperand getSubOperand64(MachineOperand &MO,
85 const TargetRegisterClass &SubRC,
86 unsigned SubIdx) const;
87
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectCOPY_SCC_VCC(MachineInstr &I) const;
91 bool selectCOPY_VCC_SCC(MachineInstr &I) const;
92 bool selectReadAnyLane(MachineInstr &I) const;
93 bool selectPHI(MachineInstr &I) const;
94 bool selectG_TRUNC(MachineInstr &I) const;
95 bool selectG_SZA_EXT(MachineInstr &I) const;
96 bool selectG_FPEXT(MachineInstr &I) const;
97 bool selectG_FNEG(MachineInstr &I) const;
98 bool selectG_FABS(MachineInstr &I) const;
99 bool selectG_AND_OR_XOR(MachineInstr &I) const;
100 bool selectG_ADD_SUB(MachineInstr &I) const;
101 bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
102 bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
103 bool selectG_EXTRACT(MachineInstr &I) const;
104 bool selectG_FMA_FMAD(MachineInstr &I) const;
105 bool selectG_MERGE_VALUES(MachineInstr &I) const;
106 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
107 bool selectG_BUILD_VECTOR(MachineInstr &I) const;
108 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
109 bool selectG_INSERT(MachineInstr &I) const;
110 bool selectG_SBFX_UBFX(MachineInstr &I) const;
111
112 bool selectInterpP1F16(MachineInstr &MI) const;
113 bool selectWritelane(MachineInstr &MI) const;
114 bool selectDivScale(MachineInstr &MI) const;
115 bool selectIntrinsicCmp(MachineInstr &MI) const;
116 bool selectBallot(MachineInstr &I) const;
117 bool selectRelocConstant(MachineInstr &I) const;
118 bool selectGroupStaticSize(MachineInstr &I) const;
119 bool selectReturnAddress(MachineInstr &I) const;
120 bool selectG_INTRINSIC(MachineInstr &I) const;
121
122 bool selectEndCfIntrinsic(MachineInstr &MI) const;
123 bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
124 bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
125 bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
126 bool selectInitWholeWave(MachineInstr &MI) const;
127 bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
128
129 bool selectImageIntrinsic(MachineInstr &MI,
130 const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
132 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
133 bool selectG_ICMP_or_FCMP(MachineInstr &I) const;
134 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
135 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
136 SmallVectorImpl<GEPInfo> &AddrInfo) const;
137
138 void initM0(MachineInstr &I) const;
139 bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
140 bool selectG_SELECT(MachineInstr &I) const;
141 bool selectG_BRCOND(MachineInstr &I) const;
142 bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
143 bool selectG_PTRMASK(MachineInstr &I) const;
144 bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
145 bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
146 bool selectBufferLoadLds(MachineInstr &MI) const;
147 bool selectGlobalLoadLds(MachineInstr &MI) const;
148 bool selectBVHIntersectRayIntrinsic(MachineInstr &I) const;
149 bool selectSMFMACIntrin(MachineInstr &I) const;
150 bool selectPermlaneSwapIntrin(MachineInstr &I, Intrinsic::ID IntrID) const;
151 bool selectWaveAddress(MachineInstr &I) const;
152 bool selectBITOP3(MachineInstr &I) const;
153 bool selectStackRestore(MachineInstr &MI) const;
154 bool selectNamedBarrierInit(MachineInstr &I, Intrinsic::ID IID) const;
155 bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const;
156 bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const;
157 bool selectSGetBarrierState(MachineInstr &I, Intrinsic::ID IID) const;
158 bool selectSBarrierLeave(MachineInstr &I) const;
159 bool selectWaveShuffleIntrin(MachineInstr &I) const;
160
161 std::pair<Register, unsigned> selectVOP3ModsImpl(Register Src,
162 bool IsCanonicalizing = true,
163 bool AllowAbs = true,
164 bool OpSel = false) const;
165
166 Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
167 MachineOperand Root, MachineInstr *InsertPt,
168 bool ForceVGPR = false) const;
169
170 InstructionSelector::ComplexRendererFns
171 selectVCSRC(MachineOperand &Root) const;
172
173 InstructionSelector::ComplexRendererFns
174 selectVSRC0(MachineOperand &Root) const;
175
176 InstructionSelector::ComplexRendererFns
177 selectVOP3Mods0(MachineOperand &Root) const;
178 InstructionSelector::ComplexRendererFns
179 selectVOP3BMods0(MachineOperand &Root) const;
180 InstructionSelector::ComplexRendererFns
181 selectVOP3OMods(MachineOperand &Root) const;
182 InstructionSelector::ComplexRendererFns
183 selectVOP3Mods(MachineOperand &Root) const;
184 InstructionSelector::ComplexRendererFns
185 selectVOP3ModsNonCanonicalizing(MachineOperand &Root) const;
186 InstructionSelector::ComplexRendererFns
187 selectVOP3BMods(MachineOperand &Root) const;
188
189 ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
190
191 std::pair<Register, unsigned>
192 selectVOP3PModsImpl(Register RootReg, const MachineRegisterInfo &MRI,
193 bool IsDOT = false) const;
194 InstructionSelector::ComplexRendererFns
195 selectVOP3PRetHelper(MachineOperand &Root, bool IsDOT = false) const;
196
197 InstructionSelector::ComplexRendererFns
198 selectVOP3PMods(MachineOperand &Root) const;
199
200 InstructionSelector::ComplexRendererFns
201 selectVOP3PModsDOT(MachineOperand &Root) const;
202
203 InstructionSelector::ComplexRendererFns
204 selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
205
206 InstructionSelector::ComplexRendererFns
207 selectWMMAModsF32NegAbs(MachineOperand &Root) const;
208 InstructionSelector::ComplexRendererFns
209 selectWMMAModsF16Neg(MachineOperand &Root) const;
210 InstructionSelector::ComplexRendererFns
211 selectWMMAModsF16NegAbs(MachineOperand &Root) const;
212 InstructionSelector::ComplexRendererFns
213 selectWMMAVISrc(MachineOperand &Root) const;
214 InstructionSelector::ComplexRendererFns
215 selectSWMMACIndex8(MachineOperand &Root) const;
216 InstructionSelector::ComplexRendererFns
217 selectSWMMACIndex16(MachineOperand &Root) const;
218 InstructionSelector::ComplexRendererFns
219 selectSWMMACIndex32(MachineOperand &Root) const;
220
221 InstructionSelector::ComplexRendererFns
222 selectVOP3OpSelMods(MachineOperand &Root) const;
223
224 InstructionSelector::ComplexRendererFns
225 selectVINTERPMods(MachineOperand &Root) const;
226 InstructionSelector::ComplexRendererFns
227 selectVINTERPModsHi(MachineOperand &Root) const;
228
229 bool selectScaleOffset(MachineOperand &Root, Register &Offset,
230 bool IsSigned) const;
231 bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
232 int64_t *Offset, bool *ScaleOffset) const;
233 InstructionSelector::ComplexRendererFns
234 selectSmrdImm(MachineOperand &Root) const;
235 InstructionSelector::ComplexRendererFns
236 selectSmrdImm32(MachineOperand &Root) const;
237 InstructionSelector::ComplexRendererFns
238 selectSmrdSgpr(MachineOperand &Root) const;
239 InstructionSelector::ComplexRendererFns
240 selectSmrdSgprImm(MachineOperand &Root) const;
241
242 std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
243 uint64_t FlatVariant) const;
244
245 InstructionSelector::ComplexRendererFns
246 selectFlatOffset(MachineOperand &Root) const;
247 InstructionSelector::ComplexRendererFns
248 selectGlobalOffset(MachineOperand &Root) const;
249 InstructionSelector::ComplexRendererFns
250 selectScratchOffset(MachineOperand &Root) const;
251
252 InstructionSelector::ComplexRendererFns
253 selectGlobalSAddr(MachineOperand &Root, unsigned CPolBits,
254 bool NeedIOffset = true) const;
255 InstructionSelector::ComplexRendererFns
256 selectGlobalSAddr(MachineOperand &Root) const;
257 InstructionSelector::ComplexRendererFns
258 selectGlobalSAddrCPol(MachineOperand &Root) const;
259 InstructionSelector::ComplexRendererFns
260 selectGlobalSAddrCPolM0(MachineOperand &Root) const;
261 InstructionSelector::ComplexRendererFns
262 selectGlobalSAddrGLC(MachineOperand &Root) const;
263 InstructionSelector::ComplexRendererFns
264 selectGlobalSAddrNoIOffset(MachineOperand &Root) const;
265 InstructionSelector::ComplexRendererFns
266 selectGlobalSAddrNoIOffsetM0(MachineOperand &Root) const;
267
268 InstructionSelector::ComplexRendererFns
269 selectScratchSAddr(MachineOperand &Root) const;
270 bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
271 uint64_t ImmOffset) const;
272 InstructionSelector::ComplexRendererFns
273 selectScratchSVAddr(MachineOperand &Root) const;
274
275 InstructionSelector::ComplexRendererFns
276 selectMUBUFScratchOffen(MachineOperand &Root) const;
277 InstructionSelector::ComplexRendererFns
278 selectMUBUFScratchOffset(MachineOperand &Root) const;
279
280 bool isDSOffsetLegal(Register Base, int64_t Offset) const;
281 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
282 unsigned Size) const;
283 bool isFlatScratchBaseLegal(Register Addr) const;
284 bool isFlatScratchBaseLegalSV(Register Addr) const;
285 bool isFlatScratchBaseLegalSVImm(Register Addr) const;
286
287 std::pair<Register, unsigned>
288 selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
289 InstructionSelector::ComplexRendererFns
290 selectDS1Addr1Offset(MachineOperand &Root) const;
291
292 InstructionSelector::ComplexRendererFns
293 selectDS64Bit4ByteAligned(MachineOperand &Root) const;
294
295 InstructionSelector::ComplexRendererFns
296 selectDS128Bit8ByteAligned(MachineOperand &Root) const;
297
298 std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
299 unsigned size) const;
300 InstructionSelector::ComplexRendererFns
301 selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
302
303 std::tuple<Register, int64_t, bool>
304 getPtrBaseWithConstantOffset(Register Root,
305 const MachineRegisterInfo &MRI) const;
306
307 // Parse out a chain of up to two g_ptr_add instructions.
308 // g_ptr_add (n0, _)
309 // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
310 struct MUBUFAddressData {
311 Register N0, N2, N3;
312 int64_t Offset = 0;
313 };
314
315 bool shouldUseAddr64(MUBUFAddressData AddrData) const;
316
317 void splitIllegalMUBUFOffset(MachineIRBuilder &B,
318 Register &SOffset, int64_t &ImmOffset) const;
319
320 MUBUFAddressData parseMUBUFAddress(Register Src) const;
321
322 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
323 Register &RSrcReg, Register &SOffset,
324 int64_t &Offset) const;
325
326 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
327 Register &SOffset, int64_t &Offset) const;
328
329 InstructionSelector::ComplexRendererFns
330 selectBUFSOffset(MachineOperand &Root) const;
331
332 InstructionSelector::ComplexRendererFns
333 selectMUBUFAddr64(MachineOperand &Root) const;
334
335 InstructionSelector::ComplexRendererFns
336 selectMUBUFOffset(MachineOperand &Root) const;
337
338 ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
339 ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
340 ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
341
342 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
343 bool &Matched) const;
344 ComplexRendererFns selectVOP3PMadMixModsExt(MachineOperand &Root) const;
345 ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
346
347 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
348 int OpIdx = -1) const;
349
350 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
351 int OpIdx) const;
352 void renderZextBoolTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
353 int OpIdx) const;
354
355 void renderOpSelTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
356 int OpIdx) const;
357
358 void renderSrcAndDstSelToOpSelXForm_0_0(MachineInstrBuilder &MIB,
359 const MachineInstr &MI,
360 int OpIdx) const;
361
362 void renderSrcAndDstSelToOpSelXForm_0_1(MachineInstrBuilder &MIB,
363 const MachineInstr &MI,
364 int OpIdx) const;
365
366 void renderSrcAndDstSelToOpSelXForm_1_0(MachineInstrBuilder &MIB,
367 const MachineInstr &MI,
368 int OpIdx) const;
369
370 void renderSrcAndDstSelToOpSelXForm_1_1(MachineInstrBuilder &MIB,
371 const MachineInstr &MI,
372 int OpIdx) const;
373
374 void renderDstSelToOpSelXForm(MachineInstrBuilder &MIB,
375 const MachineInstr &MI, int OpIdx) const;
376
377 void renderSrcSelToOpSelXForm(MachineInstrBuilder &MIB,
378 const MachineInstr &MI, int OpIdx) const;
379
380 void renderSrcAndDstSelToOpSelXForm_2_0(MachineInstrBuilder &MIB,
381 const MachineInstr &MI,
382 int OpIdx) const;
383
384 void renderDstSelToOpSel3XFormXForm(MachineInstrBuilder &MIB,
385 const MachineInstr &MI, int OpIdx) const;
386
387 void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
388 int OpIdx) const;
389
390 void renderBitcastFPImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
391 int OpIdx) const;
392
393 void renderBitcastFPImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
394 int OpIdx) const {
395 renderBitcastFPImm(MIB, MI, OpIdx);
396 }
397 void renderBitcastFPImm64(MachineInstrBuilder &MIB, const MachineInstr &MI,
398 int OpIdx) const {
399 renderBitcastFPImm(MIB, MI, OpIdx);
400 }
401
402 void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
403 int OpIdx) const;
404 void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
405 int OpIdx) const;
406 void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
407 int OpIdx) const;
408 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
409 int OpIdx) const;
410
411 void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
412 int OpIdx) const;
413
414 void renderFPPow2ToExponent(MachineInstrBuilder &MIB, const MachineInstr &MI,
415 int OpIdx) const;
416
417 void renderRoundMode(MachineInstrBuilder &MIB, const MachineInstr &MI,
418 int OpIdx) const;
419
420 void renderVOP3PModsNeg(MachineInstrBuilder &MIB, const MachineInstr &MI,
421 int OpIdx) const;
422 void renderVOP3PModsNegs(MachineInstrBuilder &MIB, const MachineInstr &MI,
423 int OpIdx) const;
424 void renderVOP3PModsNegAbs(MachineInstrBuilder &MIB, const MachineInstr &MI,
425 int OpIdx) const;
426
427 void renderPrefetchLoc(MachineInstrBuilder &MIB, const MachineInstr &MI,
428 int OpIdx) const;
429
430 void renderScaledMAIIntrinsicOperand(MachineInstrBuilder &MIB,
431 const MachineInstr &MI, int OpIdx) const;
432
433 bool isInlineImmediate(const APInt &Imm) const;
434 bool isInlineImmediate(const APFloat &Imm) const;
435
436 // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
437 // shift amount operand's `ShAmtBits` bits is unneeded.
438 bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
439
440 /// Match a zero extend from a 32-bit value to 64-bits.
441 Register matchZeroExtendFromS32(Register Reg) const;
442 /// Match a sign extend from a 32-bit value to 64-bits.
443 Register matchSignExtendFromS32(Register Reg) const;
444 /// Match a zero extend from a 32-bit value to 64-bits, or \p Reg itself if it
445 /// is 32-bit.
446 Register matchZeroExtendFromS32OrS32(Register Reg) const;
447 /// Match a sign extend from a 32-bit value to 64-bits, or \p Reg itself if it
448 /// is 32-bit.
449 Register matchSignExtendFromS32OrS32(Register Reg) const;
450 /// Match either sign or zero extend depending on the \p IsSigned from a
451 /// 32-bit value to 64-bits, or \p Reg itself if it is 32-bit.
452 Register matchExtendFromS32OrS32(Register Reg, bool IsSigned) const;
453 /// Match an any extend from a 32-bit value to 64-bit.
454 Register matchAnyExtendFromS32(Register Reg) const;
455
456 const SIInstrInfo &TII;
457 const SIRegisterInfo &TRI;
458 const AMDGPURegisterBankInfo &RBI;
459 const AMDGPUTargetMachine &TM;
460 const GCNSubtarget &STI;
461#define GET_GLOBALISEL_PREDICATES_DECL
462#define AMDGPUSubtarget GCNSubtarget
463#include "AMDGPUGenGlobalISel.inc"
464#undef GET_GLOBALISEL_PREDICATES_DECL
465#undef AMDGPUSubtarget
466
467#define GET_GLOBALISEL_TEMPORARIES_DECL
468#include "AMDGPUGenGlobalISel.inc"
469#undef GET_GLOBALISEL_TEMPORARIES_DECL
470};
471
472} // End llvm namespace.
473#endif
MRI
unsigned const MachineRegisterInfo * MRI
Definition AArch64AdvSIMDScalarPass.cpp:103
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
I
#define I(x, y, z)
Definition MD5.cpp:57
Reg
Register Reg
Definition MachineSink.cpp:2117
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2118
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
OpIdx
MachineInstr unsigned OpIdx
Definition NVPTXPrologEpilogPass.cpp:56
P
#define P(N)
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition AMDGPUInstructionSelector.cpp:43
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition AMDGPUInstructionSelector.cpp:4257
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelValueTracking *VT, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
Definition AMDGPUInstructionSelector.cpp:59
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition BlockFrequencyInfo.h:38
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:676
llvm::GIMatchTableExecutor::ComplexRendererFns
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Definition GIMatchTableExecutor.h:622
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition MachineIRBuilder.h:237
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:72
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:53
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition ProfileSummaryInfo.h:42
llvm::RegisterBank
This class implements the register bank concept.
Definition RegisterBank.h:29
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition SmallVector.h:574
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1203
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:242
uint64_t
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
llvm::Offset
@ Offset
Definition DWP.cpp:532
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition STLExtras.h:1667
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