13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
125 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
131 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
153 std::pair<Register, unsigned> selectVOP3ModsImpl(
MachineOperand &Root,
154 bool IsCanonicalizing =
true,
155 bool AllowAbs =
true,
156 bool OpSel =
false)
const;
160 bool ForceVGPR =
false)
const;
183 std::pair<Register, unsigned>
185 bool IsDOT =
false)
const;
218 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
244 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
245 unsigned Size)
const;
246 bool isFlatScratchBaseLegal(
249 std::pair<Register, unsigned>
260 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
261 unsigned size)
const;
265 std::pair<Register, int64_t>
266 getPtrBaseWithConstantOffset(
Register Root,
272 struct MUBUFAddressData {
277 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
279 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
280 Register &SOffset, int64_t &ImmOffset)
const;
282 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
284 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
285 Register &RSrcReg, Register &SOffset,
288 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
289 Register &SOffset, int64_t &
Offset)
const;
292 selectMUBUFAddr64(MachineOperand &Root)
const;
295 selectMUBUFOffset(MachineOperand &Root)
const;
301 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
302 bool &Matched)
const;
306 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
307 int OpIdx = -1)
const;
309 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
312 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
315 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
318 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
321 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
323 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
325 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
327 void renderSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
330 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
333 void renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
336 bool isInlineImmediate16(int64_t Imm)
const;
337 bool isInlineImmediate32(int64_t Imm)
const;
338 bool isInlineImmediate64(int64_t Imm)
const;
339 bool isInlineImmediate(
const APFloat &Imm)
const;
343 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
345 const SIInstrInfo &TII;
346 const SIRegisterInfo &TRI;
347 const AMDGPURegisterBankInfo &RBI;
348 const AMDGPUTargetMachine &
TM;
349 const GCNSubtarget &STI;
350 bool EnableLateStructurizeCFG;
351#define GET_GLOBALISEL_PREDICATES_DECL
352#define AMDGPUSubtarget GCNSubtarget
353#include "AMDGPUGenGlobalISel.inc"
354#undef GET_GLOBALISEL_PREDICATES_DECL
355#undef AMDGPUSubtarget
357#define GET_GLOBALISEL_TEMPORARIES_DECL
358#include "AMDGPUGenGlobalISel.inc"
359#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
CodeGenCoverage * CoverageInfo
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.