LLVM  16.0.0git
AMDGPUInstructionSelector.h
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1 //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the InstructionSelector class for
10 /// AMDGPU.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15 
17 #include "llvm/IR/InstrTypes.h"
18 
19 namespace {
20 #define GET_GLOBALISEL_PREDICATE_BITSET
21 #define AMDGPUSubtarget GCNSubtarget
22 #include "AMDGPUGenGlobalISel.inc"
23 #undef GET_GLOBALISEL_PREDICATE_BITSET
24 #undef AMDGPUSubtarget
25 }
26 
27 namespace llvm {
28 
29 namespace AMDGPU {
30 struct ImageDimIntrinsicInfo;
31 }
32 
33 class AMDGPURegisterBankInfo;
34 class AMDGPUTargetMachine;
35 class BlockFrequencyInfo;
36 class ProfileSummaryInfo;
37 class GCNSubtarget;
38 class MachineInstr;
39 class MachineIRBuilder;
40 class MachineOperand;
41 class MachineRegisterInfo;
42 class RegisterBank;
43 class SIInstrInfo;
44 class SIRegisterInfo;
45 class TargetRegisterClass;
46 
48 private:
50  const GCNSubtarget *Subtarget;
51 
52 public:
54  const AMDGPURegisterBankInfo &RBI,
55  const AMDGPUTargetMachine &TM);
56 
57  bool select(MachineInstr &I) override;
58  static const char *getName();
59 
62  BlockFrequencyInfo *BFI) override;
63 
64 private:
65  struct GEPInfo {
66  SmallVector<unsigned, 2> SgprParts;
67  SmallVector<unsigned, 2> VgprParts;
68  int64_t Imm = 0;
69  };
70 
71  bool isSGPR(Register Reg) const;
72 
73  bool isInstrUniform(const MachineInstr &MI) const;
74  bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
75 
76  const RegisterBank *getArtifactRegBank(
78  const TargetRegisterInfo &TRI) const;
79 
80  /// tblgen-erated 'select' implementation.
81  bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
82 
83  MachineOperand getSubOperand64(MachineOperand &MO,
84  const TargetRegisterClass &SubRC,
85  unsigned SubIdx) const;
86 
87  bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
88  bool selectCOPY(MachineInstr &I) const;
89  bool selectPHI(MachineInstr &I) const;
90  bool selectG_TRUNC(MachineInstr &I) const;
91  bool selectG_SZA_EXT(MachineInstr &I) const;
92  bool selectG_CONSTANT(MachineInstr &I) const;
93  bool selectG_FNEG(MachineInstr &I) const;
94  bool selectG_FABS(MachineInstr &I) const;
95  bool selectG_AND_OR_XOR(MachineInstr &I) const;
96  bool selectG_ADD_SUB(MachineInstr &I) const;
97  bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
98  bool selectG_AMDGPU_MAD_64_32(MachineInstr &I) const;
99  bool selectG_EXTRACT(MachineInstr &I) const;
100  bool selectG_FMA_FMAD(MachineInstr &I) const;
101  bool selectG_MERGE_VALUES(MachineInstr &I) const;
102  bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
103  bool selectG_BUILD_VECTOR(MachineInstr &I) const;
104  bool selectG_PTR_ADD(MachineInstr &I) const;
105  bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
106  bool selectG_INSERT(MachineInstr &I) const;
107  bool selectG_SBFX_UBFX(MachineInstr &I) const;
108 
109  bool selectInterpP1F16(MachineInstr &MI) const;
110  bool selectWritelane(MachineInstr &MI) const;
111  bool selectDivScale(MachineInstr &MI) const;
112  bool selectIntrinsicCmp(MachineInstr &MI) const;
113  bool selectBallot(MachineInstr &I) const;
114  bool selectRelocConstant(MachineInstr &I) const;
115  bool selectGroupStaticSize(MachineInstr &I) const;
116  bool selectReturnAddress(MachineInstr &I) const;
117  bool selectG_INTRINSIC(MachineInstr &I) const;
118 
119  bool selectEndCfIntrinsic(MachineInstr &MI) const;
120  bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
121  bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
122  bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
123  bool selectSBarrier(MachineInstr &MI) const;
124  bool selectDSBvhStackIntrinsic(MachineInstr &MI) const;
125 
126  bool selectImageIntrinsic(MachineInstr &MI,
127  const AMDGPU::ImageDimIntrinsicInfo *Intr) const;
128  bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
129  int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
130  bool selectG_ICMP(MachineInstr &I) const;
131  bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
132  void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
133  SmallVectorImpl<GEPInfo> &AddrInfo) const;
134 
135  void initM0(MachineInstr &I) const;
136  bool selectG_LOAD_STORE_ATOMICRMW(MachineInstr &I) const;
137  bool selectG_SELECT(MachineInstr &I) const;
138  bool selectG_BRCOND(MachineInstr &I) const;
139  bool selectG_GLOBAL_VALUE(MachineInstr &I) const;
140  bool selectG_PTRMASK(MachineInstr &I) const;
141  bool selectG_EXTRACT_VECTOR_ELT(MachineInstr &I) const;
142  bool selectG_INSERT_VECTOR_ELT(MachineInstr &I) const;
143  bool selectBufferLoadLds(MachineInstr &MI) const;
144  bool selectGlobalLoadLds(MachineInstr &MI) const;
145  bool selectBVHIntrinsic(MachineInstr &I) const;
146  bool selectSMFMACIntrin(MachineInstr &I) const;
147  bool selectWaveAddress(MachineInstr &I) const;
148 
149  std::pair<Register, unsigned>
150  selectVOP3ModsImpl(MachineOperand &Root, bool AllowAbs = true,
151  bool OpSel = false) const;
152 
153  Register copyToVGPRIfSrcFolded(Register Src, unsigned Mods,
154  MachineOperand Root, MachineInstr *InsertPt,
155  bool ForceVGPR = false) const;
156 
158  selectVCSRC(MachineOperand &Root) const;
159 
161  selectVSRC0(MachineOperand &Root) const;
162 
164  selectVOP3Mods0(MachineOperand &Root) const;
166  selectVOP3BMods0(MachineOperand &Root) const;
168  selectVOP3OMods(MachineOperand &Root) const;
170  selectVOP3Mods(MachineOperand &Root) const;
172  selectVOP3BMods(MachineOperand &Root) const;
173 
174  ComplexRendererFns selectVOP3NoMods(MachineOperand &Root) const;
175 
177  selectVOP3Mods_nnan(MachineOperand &Root) const;
178 
179  std::pair<Register, unsigned>
180  selectVOP3PModsImpl(Register Src, const MachineRegisterInfo &MRI,
181  bool IsDOT = false) const;
182 
184  selectVOP3PMods(MachineOperand &Root) const;
185 
187  selectVOP3PModsDOT(MachineOperand &Root) const;
188 
190  selectDotIUVOP3PMods(MachineOperand &Root) const;
191 
193  selectWMMAOpSelVOP3PMods(MachineOperand &Root) const;
194 
196  selectVOP3OpSelMods(MachineOperand &Root) const;
197 
199  selectVINTERPMods(MachineOperand &Root) const;
201  selectVINTERPModsHi(MachineOperand &Root) const;
202 
203  bool selectSmrdOffset(MachineOperand &Root, Register &Base, Register *SOffset,
204  int64_t *Offset) const;
206  selectSmrdImm(MachineOperand &Root) const;
208  selectSmrdImm32(MachineOperand &Root) const;
210  selectSmrdSgpr(MachineOperand &Root) const;
212  selectSmrdSgprImm(MachineOperand &Root) const;
213 
214  std::pair<Register, int> selectFlatOffsetImpl(MachineOperand &Root,
215  uint64_t FlatVariant) const;
216 
218  selectFlatOffset(MachineOperand &Root) const;
220  selectGlobalOffset(MachineOperand &Root) const;
222  selectScratchOffset(MachineOperand &Root) const;
223 
225  selectGlobalSAddr(MachineOperand &Root) const;
226 
228  selectScratchSAddr(MachineOperand &Root) const;
229  bool checkFlatScratchSVSSwizzleBug(Register VAddr, Register SAddr,
230  uint64_t ImmOffset) const;
232  selectScratchSVAddr(MachineOperand &Root) const;
233 
235  selectMUBUFScratchOffen(MachineOperand &Root) const;
237  selectMUBUFScratchOffset(MachineOperand &Root) const;
238 
239  bool isDSOffsetLegal(Register Base, int64_t Offset) const;
240  bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
241  unsigned Size) const;
242 
243  std::pair<Register, unsigned>
244  selectDS1Addr1OffsetImpl(MachineOperand &Root) const;
246  selectDS1Addr1Offset(MachineOperand &Root) const;
247 
249  selectDS64Bit4ByteAligned(MachineOperand &Root) const;
250 
252  selectDS128Bit8ByteAligned(MachineOperand &Root) const;
253 
254  std::pair<Register, unsigned> selectDSReadWrite2Impl(MachineOperand &Root,
255  unsigned size) const;
257  selectDSReadWrite2(MachineOperand &Root, unsigned size) const;
258 
259  std::pair<Register, int64_t>
260  getPtrBaseWithConstantOffset(Register Root,
261  const MachineRegisterInfo &MRI) const;
262 
263  // Parse out a chain of up to two g_ptr_add instructions.
264  // g_ptr_add (n0, _)
265  // g_ptr_add (n0, (n1 = g_ptr_add n2, n3))
266  struct MUBUFAddressData {
267  Register N0, N2, N3;
268  int64_t Offset = 0;
269  };
270 
271  bool shouldUseAddr64(MUBUFAddressData AddrData) const;
272 
273  void splitIllegalMUBUFOffset(MachineIRBuilder &B,
274  Register &SOffset, int64_t &ImmOffset) const;
275 
276  MUBUFAddressData parseMUBUFAddress(Register Src) const;
277 
278  bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
279  Register &RSrcReg, Register &SOffset,
280  int64_t &Offset) const;
281 
282  bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
283  Register &SOffset, int64_t &Offset) const;
284 
286  selectMUBUFAddr64(MachineOperand &Root) const;
287 
289  selectMUBUFOffset(MachineOperand &Root) const;
290 
292  selectMUBUFOffsetAtomic(MachineOperand &Root) const;
293 
295  selectMUBUFAddr64Atomic(MachineOperand &Root) const;
296 
297  ComplexRendererFns selectSMRDBufferImm(MachineOperand &Root) const;
298  ComplexRendererFns selectSMRDBufferImm32(MachineOperand &Root) const;
299  ComplexRendererFns selectSMRDBufferSgprImm(MachineOperand &Root) const;
300 
301  std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
302  bool &Matched) const;
303  ComplexRendererFns selectVOP3PMadMixMods(MachineOperand &Root) const;
304 
305  void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
306  int OpIdx = -1) const;
307 
308  void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
309  int OpIdx) const;
310 
311  void renderNegateImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
312  int OpIdx) const;
313 
314  void renderBitcastImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
315  int OpIdx) const;
316 
317  void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
318  int OpIdx) const;
319  void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
320  int OpIdx) const;
321  void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
322  int OpIdx) const;
323  void renderSetGLC(MachineInstrBuilder &MIB, const MachineInstr &MI,
324  int OpIdx) const;
325 
326  void renderFrameIndex(MachineInstrBuilder &MIB, const MachineInstr &MI,
327  int OpIdx) const;
328 
329  bool isInlineImmediate16(int64_t Imm) const;
330  bool isInlineImmediate32(int64_t Imm) const;
331  bool isInlineImmediate64(int64_t Imm) const;
332  bool isInlineImmediate(const APFloat &Imm) const;
333 
334  // Returns true if TargetOpcode::G_AND MachineInstr `MI`'s masking of the
335  // shift amount operand's `ShAmtBits` bits is unneeded.
336  bool isUnneededShiftMask(const MachineInstr &MI, unsigned ShAmtBits) const;
337 
338  const SIInstrInfo &TII;
339  const SIRegisterInfo &TRI;
340  const AMDGPURegisterBankInfo &RBI;
341  const AMDGPUTargetMachine &TM;
342  const GCNSubtarget &STI;
343  bool EnableLateStructurizeCFG;
344 #define GET_GLOBALISEL_PREDICATES_DECL
345 #define AMDGPUSubtarget GCNSubtarget
346 #include "AMDGPUGenGlobalISel.inc"
347 #undef GET_GLOBALISEL_PREDICATES_DECL
348 #undef AMDGPUSubtarget
349 
350 #define GET_GLOBALISEL_TEMPORARIES_DECL
351 #include "AMDGPUGenGlobalISel.inc"
352 #undef GET_GLOBALISEL_TEMPORARIES_DECL
353 };
354 
355 } // End llvm namespace.
356 #endif
llvm::AMDGPURegisterBankInfo
Definition: AMDGPURegisterBankInfo.h:42
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector< unsigned, 2 >
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:882
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Optional
Definition: APInt.h:33
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::AMDGPUTargetMachine
Definition: AMDGPUTargetMachine.h:28
llvm::SIInstrFlags::IsDOT
@ IsDOT
Definition: SIDefines.h:120
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::AMDGPUInstructionSelector::select
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
Definition: AMDGPUInstructionSelector.cpp:3358
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2555
InstrTypes.h
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::InstructionSelector::CoverageInfo
CodeGenCoverage * CoverageInfo
Definition: InstructionSelector.h:444
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:40
InstructionSelector.h
llvm::InstructionSelector::MF
MachineFunction * MF
Definition: InstructionSelector.h:446
llvm::APFloat
Definition: APFloat.h:716
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:428
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:221
llvm::CodeGenCoverage
Definition: CodeGenCoverage.h:19
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::AMDGPUInstructionSelector
Definition: AMDGPUInstructionSelector.h:47
llvm::AMDGPUInstructionSelector::getName
static const char * getName()
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1715
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::InstructionSelector::BFI
BlockFrequencyInfo * BFI
Definition: InstructionSelector.h:448
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::InstructionSelector::PSI
ProfileSummaryInfo * PSI
Definition: InstructionSelector.h:447
llvm::AMDGPUInstructionSelector::setupMF
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
Definition: AMDGPUInstructionSelector.cpp:65
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SIInstrInfo
Definition: SIInstrInfo.h:44
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPUInstructionSelector::AMDGPUInstructionSelector
AMDGPUInstructionSelector(const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, const AMDGPUTargetMachine &TM)
Definition: AMDGPUInstructionSelector.cpp:48
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39