13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
124 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
130 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
151 std::pair<Register, unsigned>
153 bool OpSel =
false)
const;
157 bool ForceVGPR =
false)
const;
178 std::pair<Register, unsigned>
180 bool IsDOT =
false)
const;
213 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
239 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
240 unsigned Size)
const;
241 bool isFlatScratchBaseLegal(
244 std::pair<Register, unsigned>
255 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
256 unsigned size)
const;
260 std::pair<Register, int64_t>
261 getPtrBaseWithConstantOffset(
Register Root,
267 struct MUBUFAddressData {
272 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
274 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
275 Register &SOffset, int64_t &ImmOffset)
const;
277 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
279 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
280 Register &RSrcReg, Register &SOffset,
283 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
284 Register &SOffset, int64_t &
Offset)
const;
287 selectMUBUFAddr64(MachineOperand &Root)
const;
290 selectMUBUFOffset(MachineOperand &Root)
const;
296 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
297 bool &Matched)
const;
301 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
302 int OpIdx = -1)
const;
304 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
307 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
310 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
313 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
316 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
318 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
320 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
322 void renderSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
325 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
328 bool isInlineImmediate16(int64_t Imm)
const;
329 bool isInlineImmediate32(int64_t Imm)
const;
330 bool isInlineImmediate64(int64_t Imm)
const;
331 bool isInlineImmediate(
const APFloat &Imm)
const;
335 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
337 const SIInstrInfo &TII;
338 const SIRegisterInfo &TRI;
339 const AMDGPURegisterBankInfo &RBI;
340 const AMDGPUTargetMachine &
TM;
341 const GCNSubtarget &STI;
342 bool EnableLateStructurizeCFG;
343#define GET_GLOBALISEL_PREDICATES_DECL
344#define AMDGPUSubtarget GCNSubtarget
345#include "AMDGPUGenGlobalISel.inc"
346#undef GET_GLOBALISEL_PREDICATES_DECL
347#undef AMDGPUSubtarget
349#define GET_GLOBALISEL_TEMPORARIES_DECL
350#include "AMDGPUGenGlobalISel.inc"
351#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage &CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF selector state.
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Provides the logic to select generic machine instructions.
CodeGenCoverage * CoverageInfo
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.