LLVM  13.0.0git
Macros | Functions | Variables
PPCISelLowering.cpp File Reference
#include "PPCISelLowering.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCCCState.h"
#include "PPCCallingConv.h"
#include "PPCFrameLowering.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCRegisterInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionXCOFF.h"
#include "llvm/MC/MCSymbolXCOFF.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <list>
#include <utility>
#include <vector>

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "ppc-lowering"
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
 STATISTIC (NumSiblingCalls, "Number of sibling calls")
 
 STATISTIC (ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")
 
 STATISTIC (NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")
 
static bool isNByteElemShuffleMask (ShuffleVectorSDNode *N, unsigned Width, int StepLen)
 Check that the mask is shuffling N byte elements. More...
 
static SDValue widenVec (SelectionDAG &DAG, SDValue Vec, const SDLoc &dl)
 
static void getMaxByValAlign (Type *Ty, Align &MaxAlign, Align MaxMaxAlign)
 getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. More...
 
static bool isFloatingPointZero (SDValue Op)
 isFloatingPointZero - Return true if this is 0.0 or -0.0. More...
 
static bool isConstantOrUndef (int Op, int Val)
 isConstantOrUndef - Op is either an undef node or a ConstantSDNode. More...
 
static bool isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
 isVMerge - Common function, used to match vmrg* shuffles. More...
 
static bool isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue)
 Common function used to match vmrgew and vmrgow shuffles. More...
 
static bool isXXBRShuffleMaskHelper (ShuffleVectorSDNode *N, int Width)
 
static bool provablyDisjointOr (SelectionDAG &DAG, const SDValue &N)
 Used when computing address flags for selecting loads and stores. More...
 
static void fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT)
 
template<typename Ty >
static bool isValidPCRelNode (SDValue N)
 
static bool usePartialVectorLoads (SDNode *N, const PPCSubtarget &ST)
 Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence. More...
 
static void getLabelAccessInfo (bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
 Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. More...
 
static SDValue LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
 
static void setUsesTOCBasePtr (MachineFunction &MF)
 
static void setUsesTOCBasePtr (SelectionDAG &DAG)
 
static unsigned CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
 CalculateStackSlotSize - Calculates the size reserved for this argument on the stack. More...
 
static Align CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
 CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack. More...
 
static bool CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs)
 CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers). More...
 
static unsigned EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes)
 EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target. More...
 
static int CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
 CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall. More...
 
static bool isFunctionGlobalAddress (SDValue Callee)
 
static bool callsShareTOCBase (const Function *Caller, SDValue Callee, const TargetMachine &TM)
 
static bool needStackSlotPassParameters (const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs)
 
static bool hasSameArgumentList (const Function *CallerFn, const CallBase &CB)
 
static bool areCallingConvEligibleForTCO_64SVR4 (CallingConv::ID CallerCC, CallingConv::ID CalleeCC)
 
static SDNodeisBLACompatibleAddress (SDValue Op, SelectionDAG &DAG)
 isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction. More...
 
static void StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl)
 StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. More...
 
static SDValue EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl)
 EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call. More...
 
static void CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
 CalculateTailCallArgDest - Remember Argument for later processing. More...
 
static SDValue CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
 CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size". More...
 
static void LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
 LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls. More...
 
static void PrepareTailCall (SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
 
static bool isIndirectCall (const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint)
 
static bool isTOCSaveRestoreRequired (const PPCSubtarget &Subtarget)
 
static unsigned getCallOpcode (PPCTargetLowering::CallFlags CFlags, const Function &Caller, const SDValue &Callee, const PPCSubtarget &Subtarget, const TargetMachine &TM)
 
static SDValue transformCallee (const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget)
 
static SDValue getOutputChainFromCallSeq (SDValue CallSeqStart)
 
static void prepareIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl)
 
static void prepareDescriptorIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget)
 
static void buildCallOperands (SmallVectorImpl< SDValue > &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget)
 
static bool isGPRShadowAligned (MCPhysReg Reg, Align RequiredAlign)
 
static bool CC_AIX (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &S)
 
static const TargetRegisterClassgetRegClassForSVT (MVT::SimpleValueType SVT, bool IsPPC64)
 
static SDValue truncateScalarIntegerArg (ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl)
 
static unsigned mapArgRegToOffsetAIX (unsigned Reg, const PPCFrameLowering *FL)
 
static unsigned getPPCStrictOpcode (unsigned Opc)
 
static SDValue convertFPToInt (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
 
static SDValue convertIntToFP (SDValue Op, SDValue Src, SelectionDAG &DAG, const PPCSubtarget &Subtarget, SDValue Chain=SDValue())
 
static SDValue getCanonicalConstSplat (uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
 getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
 BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID. More...
 
static SDValue BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
 BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount. More...
 
static bool haveEfficientBuildVectorPattern (BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector)
 Do we have an efficient pattern in a .td file for this node? More...
 
static const SDValuegetNormalLoadInput (const SDValue &Op, bool &IsPermuted)
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
 GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...
 
static bool getVectorCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
 getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison. More...
 
static InstructioncallIntrinsic (IRBuilder<> &Builder, Intrinsic::ID Id)
 
static bool isSignExtended (MachineInstr &MI, const PPCInstrInfo *TII)
 
static int getEstimateRefinementSteps (EVT VT, const PPCSubtarget &Subtarget)
 
static void getBaseWithConstantOffset (SDValue Loc, SDValue &Base, int64_t &Offset, SelectionDAG &DAG)
 
static bool isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
 
static bool isConsecutiveLS (SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
 
static bool findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG)
 
static SDValue generateEquivalentSub (SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG)
 This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR. More...
 
static bool isFPExtLoad (SDValue Op)
 
static SDValue combineBVOfConsecutiveLoads (SDNode *N, SelectionDAG &DAG)
 Reduce the number of loads when building a vector. More...
 
static SDValue addShuffleForVecExtend (SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems)
 
static SDValue combineBVOfVecSExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineBVZEXTLOAD (SDNode *N, SelectionDAG &DAG)
 
static bool isAlternatingShuffMask (const ArrayRef< int > &Mask, int NumElts)
 
static bool isSplatBV (SDValue Op)
 
static SDValue isScalarToVec (SDValue Op)
 
static void fixupShuffleMaskForPermutedSToV (SmallVectorImpl< int > &ShuffV, int LHSMaxIdx, int RHSMinIdx, int RHSMaxIdx, int HalfVec, unsigned ValidLaneWidth, const PPCSubtarget &Subtarget)
 
static SDValue getSToVPermuted (SDValue OrigSToV, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
 
static unsigned invertFMAOpcode (unsigned Opc)
 
static SDValue stripModuloOnShift (const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
 
static SDValue combineADDToADDZE (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
 
static SDValue combineADDToMAT_PCREL_ADDR (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
 
static void setAlignFlagsForFI (SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
 Set alignment flags based on whether or not the Frame Index is aligned. More...
 
static void computeFlagsForAddressComputation (SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
 Given a node, compute flags that are used for address computation when selecting load and store instructions. More...
 

Variables

static cl::opt< bool > DisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
 
static cl::opt< bool > DisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
 
static cl::opt< bool > DisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
 
static cl::opt< bool > DisableSCO ("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)
 
static cl::opt< bool > DisableInnermostLoopAlign32 ("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)
 
static cl::opt< bool > UseAbsoluteJumpTables ("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)
 
cl::opt< bool > ANDIGlueBug
 
static const MCPhysReg FPR []
 FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX. More...
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "ppc-lowering"

Definition at line 104 of file PPCISelLowering.cpp.

Function Documentation

◆ addShuffleForVecExtend()

static SDValue addShuffleForVecExtend ( SDNode N,
SelectionDAG DAG,
SDValue  Input,
uint64_t  Elems,
uint64_t  CorrectElems 
)
static

◆ areCallingConvEligibleForTCO_64SVR4()

static bool areCallingConvEligibleForTCO_64SVR4 ( CallingConv::ID  CallerCC,
CallingConv::ID  CalleeCC 
)
static

Definition at line 4701 of file PPCISelLowering.cpp.

References llvm::CallingConv::C, and llvm::CallingConv::Fast.

◆ buildCallOperands()

static void buildCallOperands ( SmallVectorImpl< SDValue > &  Ops,
PPCTargetLowering::CallFlags  CFlags,
const SDLoc dl,
SelectionDAG DAG,
SmallVector< std::pair< unsigned, SDValue >, 8 > &  RegsToPass,
SDValue  Glue,
SDValue  Chain,
SDValue Callee,
int  SPDiff,
const PPCSubtarget Subtarget 
)
static

◆ BuildIntrinsicOp() [1/3]

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.

Definition at line 8813 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

◆ BuildIntrinsicOp() [2/3]

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  Op,
SelectionDAG DAG,
const SDLoc dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.

Definition at line 8804 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ BuildIntrinsicOp() [3/3]

static SDValue BuildIntrinsicOp ( unsigned  IID,
SDValue  Op0,
SDValue  Op1,
SDValue  Op2,
SelectionDAG DAG,
const SDLoc dl,
EVT  DestVT = MVT::Other 
)
static

BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.

Definition at line 8823 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::MVT::Other.

◆ BuildVSLDOI()

static SDValue BuildVSLDOI ( SDValue  LHS,
SDValue  RHS,
unsigned  Amt,
EVT  VT,
SelectionDAG DAG,
const SDLoc dl 
)
static

BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.

The result has the specified value type.

Definition at line 8833 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), i, T, and llvm::MVT::v16i8.

Referenced by GeneratePerfectShuffle().

◆ CalculateStackSlotAlignment()

static Align CalculateStackSlotAlignment ( EVT  ArgVT,
EVT  OrigVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize 
)
static

◆ CalculateStackSlotSize()

static unsigned CalculateStackSlotSize ( EVT  ArgVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize 
)
static

CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.

Definition at line 3759 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValSize(), llvm::EVT::getStoreSize(), llvm::ISD::ArgFlagsTy::isByVal(), and llvm::ISD::ArgFlagsTy::isInConsecutiveRegs().

Referenced by CalculateStackSlotUsed().

◆ CalculateStackSlotUsed()

static bool CalculateStackSlotUsed ( EVT  ArgVT,
EVT  OrigVT,
ISD::ArgFlagsTy  Flags,
unsigned  PtrByteSize,
unsigned  LinkageSize,
unsigned  ParamAreaSize,
unsigned &  ArgOffset,
unsigned &  AvailableFPRs,
unsigned &  AvailableVRs 
)
static

CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).

ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.

Definition at line 3817 of file PPCISelLowering.cpp.

References llvm::alignTo(), CalculateStackSlotAlignment(), CalculateStackSlotSize(), llvm::MVT::f128, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::ArgFlagsTy::isByVal(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegsLast(), llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.

Referenced by needStackSlotPassParameters().

◆ CalculateTailCallArgDest()

static void CalculateTailCallArgDest ( SelectionDAG DAG,
MachineFunction MF,
bool  isPPC64,
SDValue  Arg,
int  SPDiff,
unsigned  ArgOffset,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments 
)
static

CalculateTailCallArgDest - Remember Argument for later processing.

Calculate the position of the argument.

Definition at line 4912 of file PPCISelLowering.cpp.

References Arg, llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::i32, llvm::MVT::i64, Info, and Offset.

Referenced by LowerMemOpCallTo().

◆ CalculateTailCallSPDiff()

static int CalculateTailCallSPDiff ( SelectionDAG DAG,
bool  isTailCall,
unsigned  ParamSize 
)
static

CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.

Definition at line 4537 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), int, and llvm::PPCFunctionInfo::setTailCallSPDelta().

◆ callIntrinsic()

static Instruction* callIntrinsic ( IRBuilder<> &  Builder,
Intrinsic::ID  Id 
)
static

◆ callsShareTOCBase()

static bool callsShareTOCBase ( const Function Caller,
SDValue  Callee,
const TargetMachine TM 
)
static

◆ CC_AIX()

static bool CC_AIX ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState S 
)
static

◆ combineADDToADDZE()

static SDValue combineADDToADDZE ( SDNode N,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
)
static

◆ combineADDToMAT_PCREL_ADDR()

static SDValue combineADDToMAT_PCREL_ADDR ( SDNode N,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
)
static

◆ combineBVOfConsecutiveLoads()

static SDValue combineBVOfConsecutiveLoads ( SDNode N,
SelectionDAG DAG 
)
static

Reduce the number of loads when building a vector.

Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. If the loads are consecutive but in descending order, a shuffle is added at the end to reorder the vector.

Definition at line 13618 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::numbers::e, llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), i, isConsecutiveLS(), llvm::ARM_MB::LD, llvm::MipsISD::LDL, llvm::SPII::Load, llvm::ISD::LOAD, and N.

◆ combineBVOfVecSExt()

static SDValue combineBVOfVecSExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineBVZEXTLOAD()

static SDValue combineBVZEXTLOAD ( SDNode N,
SelectionDAG DAG 
)
static

◆ computeFlagsForAddressComputation()

static void computeFlagsForAddressComputation ( SDValue  N,
unsigned &  FlagSet,
SelectionDAG DAG 
)
static

Given a node, compute flags that are used for address computation when selecting load and store instructions.

The flags computed are stored in FlagSet. This function takes into account whether the node is a constant, an ADD, OR, or a constant, and computes the address flags accordingly.

Definition at line 16989 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getZExtValue(), llvm::APInt::isSignedIntN(), llvm::PPCISD::Lo, llvm::PPC::MOF_AddrIsSImm32, llvm::PPC::MOF_NotAddNorCst, llvm::PPC::MOF_RPlusLo, llvm::PPC::MOF_RPlusR, llvm::PPC::MOF_RPlusSImm16, llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, llvm::PPC::MOF_RPlusSImm34, N, provablyDisjointOr(), setAlignFlagsForFI(), and x3.

◆ convertFPToInt()

static SDValue convertFPToInt ( SDValue  Op,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
)
static

◆ convertIntToFP()

static SDValue convertIntToFP ( SDValue  Op,
SDValue  Src,
SelectionDAG DAG,
const PPCSubtarget Subtarget,
SDValue  Chain = SDValue() 
)
static

◆ CreateCopyOfByValArgument()

static SDValue CreateCopyOfByValArgument ( SDValue  Src,
SDValue  Dst,
SDValue  Chain,
ISD::ArgFlagsTy  Flags,
SelectionDAG DAG,
const SDLoc dl 
)
static

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".

Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.

Definition at line 4949 of file PPCISelLowering.cpp.

References llvm::ISD::ArgFlagsTy::getByValSize(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemcpy(), llvm::ISD::ArgFlagsTy::getNonZeroByValAlign(), and llvm::MVT::i32.

◆ EmitTailCallStoreFPAndRetAddr()

static SDValue EmitTailCallStoreFPAndRetAddr ( SelectionDAG DAG,
SDValue  Chain,
SDValue  OldRetAddr,
SDValue  OldFP,
int  SPDiff,
const SDLoc dl 
)
static

◆ EnsureStackAlignment()

static unsigned EnsureStackAlignment ( const PPCFrameLowering Lowering,
unsigned  NumBytes 
)
static

EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.

Definition at line 3865 of file PPCISelLowering.cpp.

References llvm::alignTo(), and Lowering.

◆ findConsecutiveLoad()

static bool findConsecutiveLoad ( LoadSDNode LD,
SelectionDAG DAG 
)
static

◆ fixupFuncForFI()

static void fixupFuncForFI ( SelectionDAG DAG,
int  FrameIdx,
EVT  VT 
)
static

◆ fixupShuffleMaskForPermutedSToV()

static void fixupShuffleMaskForPermutedSToV ( SmallVectorImpl< int > &  ShuffV,
int  LHSMaxIdx,
int  RHSMinIdx,
int  RHSMaxIdx,
int  HalfVec,
unsigned  ValidLaneWidth,
const PPCSubtarget Subtarget 
)
static

Definition at line 14324 of file PPCISelLowering.cpp.

References llvm::numbers::e, i, and llvm::PPCSubtarget::isLittleEndian().

◆ generateEquivalentSub()

static SDValue generateEquivalentSub ( SDNode N,
int  Size,
bool  Complement,
bool  Swap,
SDLoc DL,
SelectionDAG DAG 
)
static

This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.

This function is purely for codegen purposes and has some flags to guide the codegen process.

Definition at line 12847 of file PPCISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, N, llvm::ISD::SETCC, llvm::Check::Size, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

◆ GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc dl 
)
static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 9237 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, BuildVSLDOI(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), i, llvm_unreachable, OP_COPY, PerfectShuffleTable, T, and llvm::MVT::v16i8.

◆ getBaseWithConstantOffset()

static void getBaseWithConstantOffset ( SDValue  Loc,
SDValue Base,
int64_t &  Offset,
SelectionDAG DAG 
)
static

◆ getCallOpcode()

static unsigned getCallOpcode ( PPCTargetLowering::CallFlags  CFlags,
const Function Caller,
const SDValue Callee,
const PPCSubtarget Subtarget,
const TargetMachine TM 
)
static

◆ getCanonicalConstSplat()

static SDValue getCanonicalConstSplat ( uint64_t  Val,
unsigned  SplatSize,
EVT  VT,
SelectionDAG DAG,
const SDLoc dl 
)
static

getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.

Cast the result to VT.

Definition at line 8782 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::Other, llvm::MVT::v16i8, llvm::MVT::v4i32, and llvm::MVT::v8i16.

◆ getEstimateRefinementSteps()

static int getEstimateRefinementSteps ( EVT  VT,
const PPCSubtarget Subtarget 
)
static

◆ getLabelAccessInfo()

static void getLabelAccessInfo ( bool  IsPIC,
const PPCSubtarget Subtarget,
unsigned &  HiOpFlags,
unsigned &  LoOpFlags,
const GlobalValue GV = nullptr 
)
static

Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.

Definition at line 3004 of file PPCISelLowering.cpp.

References llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, and llvm::PPCII::MO_PIC_FLAG.

◆ getMaxByValAlign()

static void getMaxByValAlign ( Type Ty,
Align MaxAlign,
Align  MaxMaxAlign 
)
static

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 1511 of file PPCISelLowering.cpp.

References Align.

Referenced by llvm::PPCTargetLowering::getByValTypeAlignment().

◆ getNormalLoadInput()

static const SDValue* getNormalLoadInput ( const SDValue Op,
bool &  IsPermuted 
)
static

◆ getOutputChainFromCallSeq()

static SDValue getOutputChainFromCallSeq ( SDValue  CallSeqStart)
static

◆ getPPCStrictOpcode()

static unsigned getPPCStrictOpcode ( unsigned  Opc)
static

◆ getRegClassForSVT()

static const TargetRegisterClass* getRegClassForSVT ( MVT::SimpleValueType  SVT,
bool  IsPPC64 
)
static

◆ getSToVPermuted()

static SDValue getSToVPermuted ( SDValue  OrigSToV,
SelectionDAG DAG,
const PPCSubtarget Subtarget 
)
static

◆ getVectorCompareInfo()

static bool getVectorCompareInfo ( SDValue  Intrin,
int CompareOpc,
bool &  isDot,
const PPCSubtarget Subtarget 
)
static

getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.

If it is, return true and fill in Opc/isDot with information about the intrinsic.

Definition at line 9953 of file PPCISelLowering.cpp.

References llvm::SDValue::getOperand(), llvm::PPCSubtarget::hasP8Altivec(), llvm::PPCSubtarget::hasP9Altivec(), llvm::PPCSubtarget::hasVSX(), llvm::PPCSubtarget::isISA3_1(), and llvm_unreachable.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ hasSameArgumentList()

static bool hasSameArgumentList ( const Function CallerFn,
const CallBase CB 
)
static

◆ haveEfficientBuildVectorPattern()

static bool haveEfficientBuildVectorPattern ( BuildVectorSDNode V,
bool  HasDirectMove,
bool  HasP8Vector 
)
static

Do we have an efficient pattern in a .td file for this node?

Parameters
V- pointer to the BuildVectorSDNode being matched
HasDirectMove- does this subtarget have VSR <-> GPR direct moves?

There are some patterns where it is beneficial to keep a BUILD_VECTOR node as a BUILD_VECTOR node rather than expanding it. The patterns where the opposite is true (expansion is beneficial) are:

  • The node builds a vector out of integers that are not 32 or 64-bits
  • The node builds a vector out of constants
  • The node is a "load-and-splat" In all other cases, we will choose to keep the BUILD_VECTOR.

Definition at line 8858 of file PPCISelLowering.cpp.

References llvm::numbers::e, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), i, llvm::BuildVectorSDNode::isConstant(), llvm::SDNode::isOnlyUserOf(), llvm::SDValue::isUndef(), llvm::ISD::LOAD, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, and llvm::MVT::v4i32.

◆ invertFMAOpcode()

static unsigned invertFMAOpcode ( unsigned  Opc)
static

Definition at line 16250 of file PPCISelLowering.cpp.

References llvm::ISD::FMA, llvm::PPCISD::FNMSUB, and llvm_unreachable.

◆ isAlternatingShuffMask()

static bool isAlternatingShuffMask ( const ArrayRef< int > &  Mask,
int  NumElts 
)
static

Definition at line 14272 of file PPCISelLowering.cpp.

References llvm::numbers::e, i, and llvm::BitmaskEnumDetail::Mask().

◆ isBLACompatibleAddress()

static SDNode* isBLACompatibleAddress ( SDValue  Op,
SelectionDAG DAG 
)
static

isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.

Definition at line 4842 of file PPCISelLowering.cpp.

References Addr, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), and llvm::SelectionDAG::getTargetLoweringInfo().

Referenced by isIndirectCall(), and transformCallee().

◆ isConsecutiveLS()

static bool isConsecutiveLS ( SDNode N,
LSBaseSDNode Base,
unsigned  Bytes,
int  Dist,
SelectionDAG DAG 
)
static

◆ isConsecutiveLSLoc()

static bool isConsecutiveLSLoc ( SDValue  Loc,
EVT  VT,
LSBaseSDNode Base,
unsigned  Bytes,
int  Dist,
SelectionDAG DAG 
)
static

◆ isConstantOrUndef()

static bool isConstantOrUndef ( int  Op,
int  Val 
)
static

isConstantOrUndef - Op is either an undef node or a ConstantSDNode.

Return true if Op is undef or if it matches the specified value.

Definition at line 1753 of file PPCISelLowering.cpp.

Referenced by isVMerge(), llvm::PPC::isVPKUDUMShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), and llvm::PPC::isVSLDOIShuffleMask().

◆ isFloatingPointZero()

static bool isFloatingPointZero ( SDValue  Op)
static

isFloatingPointZero - Return true if this is 0.0 or -0.0.

Definition at line 1739 of file PPCISelLowering.cpp.

References llvm::HexagonISD::CP, llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().

◆ isFPExtLoad()

static bool isFPExtLoad ( SDValue  Op)
static

Definition at line 13517 of file PPCISelLowering.cpp.

References llvm::ISD::EXTLOAD, llvm::MVT::f64, and llvm::ARM_MB::LD.

◆ isFunctionGlobalAddress()

static bool isFunctionGlobalAddress ( SDValue  Callee)
static

◆ isGPRShadowAligned()

static bool isGPRShadowAligned ( MCPhysReg  Reg,
Align  RequiredAlign 
)
static

Definition at line 6426 of file PPCISelLowering.cpp.

References assert(), R4, R6, Reg, llvm::report_fatal_error(), and llvm::Align::value().

Referenced by CC_AIX().

◆ isIndirectCall()

static bool isIndirectCall ( const SDValue Callee,
SelectionDAG DAG,
const PPCSubtarget Subtarget,
bool  isPatchPoint 
)
static

◆ isNByteElemShuffleMask()

static bool isNByteElemShuffleMask ( ShuffleVectorSDNode N,
unsigned  Width,
int  StepLen 
)
static

Check that the mask is shuffling N byte elements.

Within each N byte element of the mask, the indices could be either in increasing or decreasing order as long as they are consecutive.

Parameters
[in]Nthe shuffle vector SD Node to analyze
[in]Widththe element width in bytes, could be 2/4/8/16 (HalfWord/ Word/DoubleWord/QuadWord).
[in]StepLenthe delta indices number among the N byte element, if the mask is in increasing/decreasing order then it is 1/-1.
Returns
true iff the mask is shuffling N byte elements.

Definition at line 2128 of file PPCISelLowering.cpp.

References assert(), i, j(), and N.

Referenced by isXXBRShuffleMaskHelper(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), and llvm::PPC::isXXSLDWIShuffleMask().

◆ isScalarToVec()

static SDValue isScalarToVec ( SDValue  Op)
static

Definition at line 14305 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, and llvm::ISD::SCALAR_TO_VECTOR.

◆ isSignExtended()

static bool isSignExtended ( MachineInstr MI,
const PPCInstrInfo TII 
)
static

◆ isSplatBV()

static bool isSplatBV ( SDValue  Op)
static

◆ isTOCSaveRestoreRequired()

static bool isTOCSaveRestoreRequired ( const PPCSubtarget Subtarget)
inlinestatic

◆ isValidPCRelNode()

template<typename Ty >
static bool isValidPCRelNode ( SDValue  N)
static

Definition at line 2849 of file PPCISelLowering.cpp.

References llvm::PPCII::MO_PCREL_FLAG, and N.

◆ isVMerge() [1/2]

static bool isVMerge ( ShuffleVectorSDNode N,
unsigned  IndexOffset,
unsigned  RHSStartValue 
)
static

Common function used to match vmrgew and vmrgow shuffles.

The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.

  • Little Endian:
    • Use offset of 0 to check for odd elements
    • Use offset of 4 to check for even elements
  • Big Endian:

The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size

  1. More info on the shuffle vector can be found in the http://llvm.org/docs/LangRef.html#shufflevector-instruction Language Reference.

The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:

  • If the instruction uses the same vector for both inputs, the range of the indices will be 0 to 15. In this case, the RHSStart value passed should be 0.
  • If the instruction has two different vectors then the range of the indices will be 0 to 31. In this case, the RHSStart value passed should be 16 (indices 0-15 specify elements in the first vector while indices 16 to 31 specify elements in the second vector).
Parameters
[in]NThe shuffle vector SD Node to analyze
[in]IndexOffsetSpecifies whether to look for even or odd elements
[in]RHSStartValueSpecifies the starting index for the righthand input vector to the shuffle_vector instruction
Returns
true iff this shuffle vector represents an even or odd word merge

Definition at line 1985 of file PPCISelLowering.cpp.

References i, isConstantOrUndef(), j(), N, and llvm::MVT::v16i8.

◆ isVMerge() [2/2]

static bool isVMerge ( ShuffleVectorSDNode N,
unsigned  UnitSize,
unsigned  LHSStart,
unsigned  RHSStart 
)
static

isVMerge - Common function, used to match vmrg* shuffles.

Definition at line 1875 of file PPCISelLowering.cpp.

References assert(), i, isConstantOrUndef(), j(), N, and llvm::MVT::v16i8.

Referenced by llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), and llvm::PPC::isVMRGLShuffleMask().

◆ isXXBRShuffleMaskHelper()

static bool isXXBRShuffleMaskHelper ( ShuffleVectorSDNode N,
int  Width 
)
static

◆ LowerLabelRef()

static SDValue LowerLabelRef ( SDValue  HiPart,
SDValue  LoPart,
bool  isPIC,
SelectionDAG DAG 
)
static

◆ LowerMemOpCallTo()

static void LowerMemOpCallTo ( SelectionDAG DAG,
MachineFunction MF,
SDValue  Chain,
SDValue  Arg,
SDValue  PtrOff,
int  SPDiff,
unsigned  ArgOffset,
bool  isPPC64,
bool  isTailCall,
bool  isVector,
SmallVectorImpl< SDValue > &  MemOpChains,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments,
const SDLoc dl 
)
static

◆ mapArgRegToOffsetAIX()

static unsigned mapArgRegToOffsetAIX ( unsigned  Reg,
const PPCFrameLowering FL 
)
static

◆ needStackSlotPassParameters()

static bool needStackSlotPassParameters ( const PPCSubtarget Subtarget,
const SmallVectorImpl< ISD::OutputArg > &  Outs 
)
static

◆ prepareDescriptorIndirectCall()

static void prepareDescriptorIndirectCall ( SelectionDAG DAG,
SDValue Callee,
SDValue Glue,
SDValue Chain,
SDValue  CallSeqStart,
const CallBase CB,
const SDLoc dl,
bool  hasNest,
const PPCSubtarget Subtarget 
)
static

◆ prepareIndirectCall()

static void prepareIndirectCall ( SelectionDAG DAG,
SDValue Callee,
SDValue Glue,
SDValue Chain,
const SDLoc dl 
)
static

◆ PrepareTailCall()

static void PrepareTailCall ( SelectionDAG DAG,
SDValue InFlag,
SDValue Chain,
const SDLoc dl,
int  SPDiff,
unsigned  NumBytes,
SDValue  LROp,
SDValue  FPOp,
SmallVectorImpl< TailCallArgumentInfo > &  TailCallArguments 
)
static

◆ provablyDisjointOr()

static bool provablyDisjointOr ( SelectionDAG DAG,
const SDValue N 
)
static

Used when computing address flags for selecting loads and stores.

If we have an OR, check if the LHS and RHS are provably disjoint. An OR of two provably disjoint values is equivalent to an ADD. Most PPC load/store instructions compute the effective address as a sum, so doing this conversion is useful.

Definition at line 2526 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::APInt::getBoolValue(), N, llvm::ISD::OR, and llvm::KnownBits::Zero.

Referenced by computeFlagsForAddressComputation(), and llvm::PPCTargetLowering::SelectForceXFormMode().

◆ setAlignFlagsForFI()

static void setAlignFlagsForFI ( SDValue  N,
unsigned &  FlagSet,
SelectionDAG DAG 
)
static

Set alignment flags based on whether or not the Frame Index is aligned.

Utilized when computing flags for address computation when selecting load and store instructions.

Definition at line 16960 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, N, llvm::ISD::OR, PPC, and llvm::Align::value().

Referenced by computeFlagsForAddressComputation().

◆ setUsesTOCBasePtr() [1/2]

static void setUsesTOCBasePtr ( MachineFunction MF)
static

◆ setUsesTOCBasePtr() [2/2]

static void setUsesTOCBasePtr ( SelectionDAG DAG)
static

◆ STATISTIC() [1/4]

STATISTIC ( NumDynamicAllocaProbed  ,
"Number of dynamic stack allocation probed"   
)

◆ STATISTIC() [2/4]

STATISTIC ( NumSiblingCalls  ,
"Number of sibling calls  
)

◆ STATISTIC() [3/4]

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ STATISTIC() [4/4]

STATISTIC ( ShufflesHandledWithVPERM  ,
"Number of shuffles lowered to a VPERM"   
)

◆ StoreTailCallArgumentsToStackSlot()

static void StoreTailCallArgumentsToStackSlot ( SelectionDAG DAG,
SDValue  Chain,
const SmallVectorImpl< TailCallArgumentInfo > &  TailCallArgs,
SmallVectorImpl< SDValue > &  MemOpChains,
const SDLoc dl 
)
static

StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.

Definition at line 4871 of file PPCISelLowering.cpp.

References Arg, llvm::numbers::e, llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), and i.

Referenced by PrepareTailCall().

◆ stripModuloOnShift()

static SDValue stripModuloOnShift ( const TargetLowering TLI,
SDNode N,
SelectionDAG DAG 
)
static

◆ transformCallee()

static SDValue transformCallee ( const SDValue Callee,
SelectionDAG DAG,
const SDLoc dl,
const PPCSubtarget Subtarget 
)
static

◆ truncateScalarIntegerArg()

static SDValue truncateScalarIntegerArg ( ISD::ArgFlagsTy  Flags,
EVT  ValVT,
SelectionDAG DAG,
SDValue  ArgValue,
MVT  LocVT,
const SDLoc dl 
)
static

◆ usePartialVectorLoads()

static bool usePartialVectorLoads ( SDNode N,
const PPCSubtarget ST 
)
static

Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence.

Definition at line 2872 of file PPCISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::SDValue::hasOneUse(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::isSimple(), llvm::ARM_MB::LD, N, llvm::ISD::SCALAR_TO_VECTOR, llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED, llvm::MVT::SimpleTy, and llvm::ARM_MB::ST.

Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().

◆ widenVec()

static SDValue widenVec ( SelectionDAG DAG,
SDValue  Vec,
const SDLoc dl 
)
static

Variable Documentation

◆ ANDIGlueBug

cl::opt<bool> ANDIGlueBug

◆ DisableILPPref

cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
static

◆ DisableInnermostLoopAlign32

cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)
static

◆ DisablePPCPreinc

cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
static

◆ DisablePPCUnaligned

cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
static

◆ DisableSCO

cl::opt<bool> DisableSCO("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)
static

◆ FPR

const MCPhysReg FPR[]
static
Initial value:
= {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
PPC::F11, PPC::F12, PPC::F13}

FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.

Definition at line 3753 of file PPCISelLowering.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), CC_AIX(), and llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().

◆ UseAbsoluteJumpTables

cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)
static