LLVM 19.0.0git
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#include "PPCISelLowering.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCCCState.h"
#include "PPCCallingConv.h"
#include "PPCFrameLowering.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCRegisterInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionXCOFF.h"
#include "llvm/MC/MCSymbolXCOFF.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <list>
#include <optional>
#include <utility>
#include <vector>
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "ppc-lowering" |
Functions | |
STATISTIC (NumTailCalls, "Number of tail calls") | |
STATISTIC (NumSiblingCalls, "Number of sibling calls") | |
STATISTIC (ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM or XXPERM") | |
STATISTIC (NumDynamicAllocaProbed, "Number of dynamic stack allocation probed") | |
static bool | isNByteElemShuffleMask (ShuffleVectorSDNode *N, unsigned Width, int StepLen) |
Check that the mask is shuffling N byte elements. | |
static SDValue | widenVec (SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) |
static void | getMaxByValAlign (Type *Ty, Align &MaxAlign, Align MaxMaxAlign) |
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment. | |
static bool | isFloatingPointZero (SDValue Op) |
isFloatingPointZero - Return true if this is 0.0 or -0.0. | |
static bool | isConstantOrUndef (int Op, int Val) |
isConstantOrUndef - Op is either an undef node or a ConstantSDNode. | |
static bool | isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart) |
isVMerge - Common function, used to match vmrg* shuffles. | |
static bool | isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue) |
Common function used to match vmrgew and vmrgow shuffles. | |
static bool | isXXBRShuffleMaskHelper (ShuffleVectorSDNode *N, int Width) |
static bool | provablyDisjointOr (SelectionDAG &DAG, const SDValue &N) |
Used when computing address flags for selecting loads and stores. | |
static void | fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT) |
template<typename Ty > | |
static bool | isValidPCRelNode (SDValue N) |
static bool | usePartialVectorLoads (SDNode *N, const PPCSubtarget &ST) |
Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence. | |
static void | getLabelAccessInfo (bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr) |
Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags. | |
static SDValue | LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) |
static void | setUsesTOCBasePtr (MachineFunction &MF) |
static void | setUsesTOCBasePtr (SelectionDAG &DAG) |
static unsigned | CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize) |
CalculateStackSlotSize - Calculates the size reserved for this argument on the stack. | |
static Align | CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize) |
CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack. | |
static bool | CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs) |
CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers). | |
static unsigned | EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes) |
EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target. | |
static int | CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize) |
CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall. | |
static bool | isFunctionGlobalAddress (const GlobalValue *CalleeGV) |
static bool | callsShareTOCBase (const Function *Caller, const GlobalValue *CalleeGV, const TargetMachine &TM) |
static bool | needStackSlotPassParameters (const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs) |
static bool | hasSameArgumentList (const Function *CallerFn, const CallBase &CB) |
static bool | areCallingConvEligibleForTCO_64SVR4 (CallingConv::ID CallerCC, CallingConv::ID CalleeCC) |
static SDNode * | isBLACompatibleAddress (SDValue Op, SelectionDAG &DAG) |
isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction. | |
static void | StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl) |
StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot. | |
static SDValue | EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) |
EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call. | |
static void | CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments) |
CalculateTailCallArgDest - Remember Argument for later processing. | |
static SDValue | CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) |
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size". | |
static void | LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl) |
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls. | |
static void | PrepareTailCall (SelectionDAG &DAG, SDValue &InGlue, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments) |
static bool | isIndirectCall (const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint) |
static bool | isTOCSaveRestoreRequired (const PPCSubtarget &Subtarget) |
static unsigned | getCallOpcode (PPCTargetLowering::CallFlags CFlags, const Function &Caller, const SDValue &Callee, const PPCSubtarget &Subtarget, const TargetMachine &TM, bool IsStrictFPCall=false) |
static SDValue | transformCallee (const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) |
static SDValue | getOutputChainFromCallSeq (SDValue CallSeqStart) |
static void | prepareIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl) |
static void | prepareDescriptorIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) |
static void | buildCallOperands (SmallVectorImpl< SDValue > &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget) |
static bool | isGPRShadowAligned (MCPhysReg Reg, Align RequiredAlign) |
static bool | CC_AIX (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &S) |
static const TargetRegisterClass * | getRegClassForSVT (MVT::SimpleValueType SVT, bool IsPPC64, bool HasP8Vector, bool HasVSX) |
static SDValue | truncateScalarIntegerArg (ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl) |
static unsigned | mapArgRegToOffsetAIX (unsigned Reg, const PPCFrameLowering *FL) |
static unsigned | getPPCStrictOpcode (unsigned Opc) |
static SDValue | convertFPToInt (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) |
static SDValue | convertIntToFP (SDValue Op, SDValue Src, SelectionDAG &DAG, const PPCSubtarget &Subtarget, SDValue Chain=SDValue()) |
static SDValue | getCanonicalConstSplat (uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) |
getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize. | |
static SDValue | BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID. | |
static SDValue | BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID. | |
static SDValue | BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other) |
BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID. | |
static SDValue | BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) |
BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount. | |
static bool | haveEfficientBuildVectorPattern (BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector) |
Do we have an efficient pattern in a .td file for this node? | |
static const SDValue * | getNormalLoadInput (const SDValue &Op, bool &IsPermuted) |
static bool | isValidSplatLoad (const PPCSubtarget &Subtarget, const SDValue &Op, unsigned &Opcode) |
static SDValue | GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) |
GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. | |
static bool | getVectorCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget) |
getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison. | |
static SDValue | getDataClassTest (SDValue Op, FPClassTest Mask, const SDLoc &Dl, SelectionDAG &DAG, const PPCSubtarget &Subtarget) |
static Instruction * | callIntrinsic (IRBuilderBase &Builder, Intrinsic::ID Id) |
static bool | isSignExtended (MachineInstr &MI, const PPCInstrInfo *TII) |
static bool | IsSelectCC (MachineInstr &MI) |
static bool | IsSelect (MachineInstr &MI) |
static int | getEstimateRefinementSteps (EVT VT, const PPCSubtarget &Subtarget) |
static void | getBaseWithConstantOffset (SDValue Loc, SDValue &Base, int64_t &Offset, SelectionDAG &DAG) |
static bool | isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) |
static bool | isConsecutiveLS (SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) |
static bool | findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG) |
static SDValue | generateEquivalentSub (SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG) |
This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR. | |
static bool | isFPExtLoad (SDValue Op) |
static SDValue | combineBVOfConsecutiveLoads (SDNode *N, SelectionDAG &DAG) |
Reduce the number of loads when building a vector. | |
static SDValue | addShuffleForVecExtend (SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems) |
static SDValue | combineBVOfVecSExt (SDNode *N, SelectionDAG &DAG) |
static SDValue | combineBVZEXTLOAD (SDNode *N, SelectionDAG &DAG) |
static bool | isAlternatingShuffMask (const ArrayRef< int > &Mask, int NumElts) |
static bool | isSplatBV (SDValue Op) |
static SDValue | isScalarToVec (SDValue Op) |
static void | fixupShuffleMaskForPermutedSToV (SmallVectorImpl< int > &ShuffV, int LHSMaxIdx, int RHSMinIdx, int RHSMaxIdx, int HalfVec, unsigned ValidLaneWidth, const PPCSubtarget &Subtarget) |
static SDValue | getSToVPermuted (SDValue OrigSToV, SelectionDAG &DAG, const PPCSubtarget &Subtarget) |
static bool | isStoreConditional (SDValue Intrin, unsigned &StoreWidth) |
static unsigned | invertFMAOpcode (unsigned Opc) |
static SDValue | stripModuloOnShift (const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG) |
static SDValue | combineADDToADDZE (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) |
static SDValue | combineADDToMAT_PCREL_ADDR (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) |
static void | setAlignFlagsForFI (SDValue N, unsigned &FlagSet, SelectionDAG &DAG) |
Set alignment flags based on whether or not the Frame Index is aligned. | |
static void | computeFlagsForAddressComputation (SDValue N, unsigned &FlagSet, SelectionDAG &DAG) |
Given a node, compute flags that are used for address computation when selecting load and store instructions. | |
static bool | isPCRelNode (SDValue N) |
static void | setXFormForUnalignedFI (SDValue N, unsigned Flags, PPC::AddrMode &Mode) |
static Intrinsic::ID | getIntrinsicForAtomicRMWBinOp128 (AtomicRMWInst::BinOp BinOp) |
Variables | |
static cl::opt< bool > | DisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden) |
static cl::opt< bool > | DisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden) |
static cl::opt< bool > | DisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden) |
static cl::opt< bool > | DisableSCO ("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden) |
static cl::opt< bool > | DisableInnermostLoopAlign32 ("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden) |
static cl::opt< bool > | UseAbsoluteJumpTables ("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden) |
static cl::opt< bool > | DisablePerfectShuffle ("ppc-disable-perfect-shuffle", cl::desc("disable vector permute decomposition"), cl::init(true), cl::Hidden) |
cl::opt< bool > | DisableAutoPairedVecSt ("disable-auto-paired-vec-st", cl::desc("disable automatically generated 32byte paired vector stores"), cl::init(true), cl::Hidden) |
static cl::opt< unsigned > | PPCMinimumJumpTableEntries ("ppc-min-jump-table-entries", cl::init(64), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on PPC")) |
static const char | AIXSSPCanaryWordName [] = "__ssp_canary_word" |
constexpr uint64_t | AIXSmallTlsPolicySizeLimit = 32751 |
cl::opt< bool > | ANDIGlueBug |
static const MCPhysReg | FPR [] |
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX. | |
#define DEBUG_TYPE "ppc-lowering" |
Definition at line 106 of file PPCISelLowering.cpp.
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Definition at line 14746 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::DataLayout::isLittleEndian(), N, and llvm::ISD::SIGN_EXTEND_INREG.
Referenced by combineBVOfVecSExt().
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Definition at line 4945 of file PPCISelLowering.cpp.
References llvm::CallingConv::C, CC, and llvm::CallingConv::Fast.
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Definition at line 5613 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::PPCTargetLowering::CallFlags::CallConv, llvm::SelectionDAG::getConstant(), llvm::PPCSubtarget::getEnvironmentPointerRegister(), llvm::PPCSubtarget::getFrameLowering(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::PPCSubtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::PPCSubtarget::getStackPointerRegister(), llvm::PPCSubtarget::getTOCPointerRegister(), llvm::PPCFrameLowering::getTOCSaveOffset(), llvm::PPCTargetLowering::CallFlags::HasNest, llvm::PPCSubtarget::is32BitELFABI(), llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), llvm::PPCTargetLowering::CallFlags::IsIndirect, llvm::PPCTargetLowering::CallFlags::IsPatchPoint, llvm::PPCSubtarget::isPPC64(), llvm::PPCTargetLowering::CallFlags::IsTailCall, isTOCSaveRestoreRequired(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), llvm::PPCTargetLowering::CallFlags::IsVarArg, llvm::SmallVectorTemplateBase< T, bool >::push_back(), TRI, and llvm::PPCSubtarget::usesFunctionDescriptors().
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BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.
Definition at line 9149 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, and RHS.
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BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.
Definition at line 9140 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::ISD::INTRINSIC_WO_CHAIN.
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
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BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.
Definition at line 9159 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and llvm::ISD::INTRINSIC_WO_CHAIN.
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BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.
The result has the specified value type.
Definition at line 9169 of file PPCISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), LHS, and RHS.
Referenced by GeneratePerfectShuffle().
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CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.
Definition at line 4030 of file PPCISelLowering.cpp.
References llvm::EVT::getStoreSize(), and llvm_unreachable.
Referenced by CalculateStackSlotUsed().
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CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.
Definition at line 4014 of file PPCISelLowering.cpp.
References llvm::EVT::getStoreSize().
Referenced by CalculateStackSlotUsed().
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CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).
ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.
Definition at line 4072 of file PPCISelLowering.cpp.
References llvm::alignTo(), CalculateStackSlotAlignment(), and CalculateStackSlotSize().
Referenced by needStackSlotPassParameters().
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CalculateTailCallArgDest - Remember Argument for later processing.
Calculate the position of the argument.
Definition at line 5150 of file PPCISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SDValue::getValueSizeInBits(), Info, llvm::Offset, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by LowerMemOpCallTo().
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CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.
Definition at line 4783 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), and llvm::PPCFunctionInfo::setTailCallSPDelta().
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Definition at line 11888 of file PPCISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::Intrinsic::getDeclaration(), llvm::IRBuilderBase::GetInsertBlock(), llvm::GlobalValue::getParent(), and llvm::BasicBlock::getParent().
Referenced by llvm::PPCTargetLowering::emitLeadingFence(), and llvm::PPCTargetLowering::emitTrailingFence().
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Definition at line 4800 of file PPCISelLowering.cpp.
References assert(), F, llvm::GlobalAlias::getAliaseeObject(), llvm::GlobalValue::getSection(), llvm::GlobalValue::hasComdat(), llvm::GlobalValue::isStrongDefinitionForLinker(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), llvm::CodeModel::Large, llvm::CodeModel::Medium, and TM.
Referenced by getCallOpcode().
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Definition at line 6754 of file PPCISelLowering.cpp.
References llvm::CCState::addLoc(), llvm::alignTo(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), assert(), FPR, llvm::ISD::ArgFlagsTy::getByValSize(), llvm::CCValAssign::getCustomMem(), llvm::CCValAssign::getCustomReg(), llvm::CCState::getFirstUnallocated(), llvm::MVT::getFixedSizeInBits(), llvm::CCState::getMachineFunction(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroByValAlign(), llvm::CCValAssign::getReg(), llvm::CCState::getStackSize(), llvm::MVT::getStoreSize(), llvm::MachineFunction::getSubtarget(), I, llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, llvm::ISD::ArgFlagsTy::isByVal(), llvm::AIXCCState::isFixed(), isGPRShadowAligned(), llvm::ISD::ArgFlagsTy::isNest(), llvm::PPCSubtarget::isPPC64(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::CCState::isVarArg(), llvm::Offset, llvm::report_fatal_error(), llvm::CCValAssign::SExt, llvm::MVT::SimpleTy, llvm::ArrayRef< T >::size(), llvm::Align::value(), and llvm::CCValAssign::ZExt.
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Definition at line 17735 of file PPCISelLowering.cpp.
References llvm::Add, llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::PPCSubtarget::isPPC64(), LHS, N, RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SUBC, std::swap(), and llvm::ISD::ZERO_EXTEND.
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Definition at line 17821 of file PPCISelLowering.cpp.
References DL, llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::ConstantSDNode::getSExtValue(), llvm::GlobalAddressSDNode::getTargetFlags(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDNode::getValueType(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), LHS, llvm::PPCISD::MAT_PCREL_ADDR, N, RHS, and std::swap().
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Reduce the number of loads when building a vector.
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. If the loads are consecutive but in descending order, a shuffle is added at the end to reorder the vector.
Definition at line 14648 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAlign(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::ISD::LOAD, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 14785 of file PPCISelLowering.cpp.
References addShuffleForVecExtend(), llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::DataLayout::isLittleEndian(), N, llvm::ISD::SIGN_EXTEND, and llvm::ISD::SIGN_EXTEND_INREG.
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Definition at line 14883 of file PPCISelLowering.cpp.
References DL, llvm::ISD::EXTLOAD, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getVTList(), llvm::ISD::LOAD, llvm::PPCISD::LXVRZX, N, and llvm::ISD::ZEXTLOAD.
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Given a node, compute flags that are used for address computation when selecting load and store instructions.
The flags computed are stored in FlagSet. This function takes into account whether the node is a constant, an ADD, OR, or a constant, and computes the address flags accordingly.
Definition at line 18149 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::APInt::getZExtValue(), llvm::APInt::isSignedIntN(), llvm::PPCISD::Lo, llvm::PPC::MOF_AddrIsSImm32, llvm::PPC::MOF_NotAddNorCst, llvm::PPC::MOF_RPlusLo, llvm::PPC::MOF_RPlusR, llvm::PPC::MOF_RPlusSImm16, llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, llvm::PPC::MOF_RPlusSImm34, N, provablyDisjointOr(), RHS, and setAlignFlagsForFI().
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Definition at line 8216 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::DELETED_NODE, llvm::PPCISD::FCTIDUZ, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWUZ, llvm::PPCISD::FCTIWZ, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), getPPCStrictOpcode(), llvm::SelectionDAG::getVTList(), llvm::PPCSubtarget::isPPC64(), llvm_unreachable, llvm::MVT::SimpleTy, llvm::ISD::STRICT_FP_EXTEND, and llvm::ISD::STRICT_FP_TO_SINT.
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Definition at line 8544 of file PPCISelLowering.cpp.
References llvm::PPCISD::FCFID, llvm::PPCISD::FCFIDS, llvm::PPCISD::FCFIDU, llvm::PPCISD::FCFIDUS, llvm::SelectionDAG::getNode(), getPPCStrictOpcode(), llvm::SelectionDAG::getVTList(), llvm::ISD::SINT_TO_FP, and llvm::ISD::STRICT_SINT_TO_FP.
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CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".
Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.
Definition at line 5187 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getMemcpy().
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EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call.
Definition at line 5126 of file PPCISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::PPCSubtarget::getFrameLowering(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::MachineFunction::getSubtarget(), and llvm::PPCSubtarget::isPPC64().
Referenced by PrepareTailCall().
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EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.
Definition at line 4120 of file PPCISelLowering.cpp.
References llvm::alignTo(), and Lowering.
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Definition at line 13825 of file PPCISelLowering.cpp.
References llvm::SmallSet< T, N, C >::clear(), llvm::SmallSet< T, N, C >::count(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::EVT::getStoreSize(), I, llvm::SmallSet< T, N, C >::insert(), isConsecutiveLS(), llvm::SDNode::ops(), llvm::ISD::TokenFactor, and llvm::SDNode::uses().
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
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Definition at line 2759 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), and llvm::PPCFunctionInfo::setHasNonRISpills().
Referenced by llvm::PPCTargetLowering::SelectAddressRegImm(), and llvm::PPCTargetLowering::SelectOptimalAddrMode().
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Definition at line 15348 of file PPCISelLowering.cpp.
References Idx, llvm::PPCSubtarget::isLittleEndian(), and llvm::SmallVectorBase< Size_T >::size().
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This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.
This function is purely for codegen purposes and has some flags to guide the codegen process.
Definition at line 13891 of file PPCISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, Size, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 9645 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, BuildVSLDOI(), GeneratePerfectShuffle(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), LHS, llvm_unreachable, OP_COPY, PerfectShuffleTable, and RHS.
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Definition at line 13696 of file PPCISelLowering.cpp.
References llvm::sampleprof::Base, getBaseWithConstantOffset(), llvm::SDValue::getOperand(), llvm::SelectionDAG::isBaseWithConstantOffset(), and llvm::Offset.
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Definition at line 5351 of file PPCISelLowering.cpp.
References assert(), llvm::PPCISD::BCTRL, llvm::PPCISD::BCTRL_LOAD_TOC, llvm::PPCISD::BCTRL_LOAD_TOC_RM, llvm::PPCISD::BCTRL_RM, llvm::PPCISD::CALL, llvm::PPCISD::CALL_NOP, llvm::PPCISD::CALL_NOP_RM, llvm::PPCISD::CALL_NOTOC, llvm::PPCISD::CALL_NOTOC_RM, llvm::PPCISD::CALL_RM, callsShareTOCBase(), G, llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), llvm::PPCTargetLowering::CallFlags::IsIndirect, llvm::PPCTargetLowering::CallFlags::IsTailCall, isTOCSaveRestoreRequired(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), llvm_unreachable, llvm::PPCISD::TC_RETURN, and TM.
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getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.
Cast the result to VT.
Definition at line 9118 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getBitcast(), and llvm::SelectionDAG::getConstant().
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Definition at line 11201 of file PPCISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::EXTRACT_ELEMENT, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::fcAllFlags, llvm::fcNan, llvm::fcNegInf, llvm::fcNegNormal, llvm::fcNegSubnormal, llvm::fcNegZero, llvm::fcNormal, llvm::fcPosInf, llvm::fcPosNormal, llvm::fcPosSubnormal, llvm::fcPosZero, llvm::fcQNan, llvm::fcSNan, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), getDataClassTest(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::PPCSubtarget::isLittleEndian(), llvm::PPCSubtarget::isPPC64(), llvm::Normal, llvm::ISD::OR, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SETEQ, and llvm::ISD::SETNE.
Referenced by getDataClassTest().
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Definition at line 13584 of file PPCISelLowering.cpp.
References llvm::EVT::getScalarType().
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Definition at line 18682 of file PPCISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm::AtomicRMWInst::And, llvm_unreachable, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Or, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::Xchg, and llvm::AtomicRMWInst::Xor.
Referenced by llvm::PPCTargetLowering::emitMaskedAtomicRMWIntrinsic().
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Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
Definition at line 3133 of file PPCISelLowering.cpp.
References llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, llvm::PPCII::MO_PIC_HA_FLAG, and llvm::PPCII::MO_PIC_LO_FLAG.
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
Definition at line 1597 of file PPCISelLowering.cpp.
References getMaxByValAlign().
Referenced by llvm::PPCTargetLowering::getByValTypeAlignment(), llvm::X86TargetLowering::getByValTypeAlignment(), and getMaxByValAlign().
Definition at line 9251 of file PPCISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNormalLoad(), llvm::ISD::LOAD, llvm::ISD::SCALAR_TO_VECTOR, and llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED.
Definition at line 5493 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::CALLSEQ_START, llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getValue(), and llvm::SDValue::getValueType().
Referenced by prepareDescriptorIndirectCall().
Definition at line 8193 of file PPCISelLowering.cpp.
References llvm::PPCISD::FCFID, llvm::PPCISD::FCFIDS, llvm::PPCISD::FCFIDU, llvm::PPCISD::FCFIDUS, llvm::PPCISD::FCTIDUZ, llvm::PPCISD::FCTIDZ, llvm::PPCISD::FCTIWUZ, llvm::PPCISD::FCTIWZ, llvm_unreachable, llvm::PPCISD::STRICT_FCFID, llvm::PPCISD::STRICT_FCFIDS, llvm::PPCISD::STRICT_FCFIDU, llvm::PPCISD::STRICT_FCFIDUS, llvm::PPCISD::STRICT_FCTIDUZ, llvm::PPCISD::STRICT_FCTIDZ, llvm::PPCISD::STRICT_FCTIWUZ, and llvm::PPCISD::STRICT_FCTIWZ.
Referenced by convertFPToInt(), and convertIntToFP().
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Definition at line 6981 of file PPCISelLowering.cpp.
References assert(), and llvm::report_fatal_error().
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Definition at line 15366 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), Idx, llvm::PPCSubtarget::isLittleEndian(), llvm::ISD::SCALAR_TO_VECTOR, and llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED.
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getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.
If it is, return true and fill in Opc/isDot with information about the intrinsic.
Definition at line 10468 of file PPCISelLowering.cpp.
References llvm::SDValue::getConstantOperandVal(), and llvm_unreachable.
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
Definition at line 4914 of file PPCISelLowering.cpp.
References llvm::Function::arg_begin(), llvm::CallBase::arg_begin(), llvm::CallBase::arg_end(), llvm::Function::arg_size(), llvm::CallBase::arg_size(), and llvm::Value::getType().
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Do we have an efficient pattern in a .td file for this node?
V | - pointer to the BuildVectorSDNode being matched |
HasDirectMove | - does this subtarget have VSR <-> GPR direct moves? |
There are some patterns where it is beneficial to keep a BUILD_VECTOR node as a BUILD_VECTOR node rather than expanding it. The patterns where the opposite is true (expansion is beneficial) are:
Definition at line 9194 of file PPCISelLowering.cpp.
References llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, and llvm::ISD::LOAD.
Definition at line 17521 of file PPCISelLowering.cpp.
References llvm::ISD::FMA, llvm::PPCISD::FNMSUB, and llvm_unreachable.
Definition at line 15296 of file PPCISelLowering.cpp.
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isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.
Definition at line 5080 of file PPCISelLowering.cpp.
References Addr, llvm::CallingConv::C, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), and llvm::SelectionDAG::getTargetLoweringInfo().
Referenced by isIndirectCall(), and transformCallee().
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Definition at line 13748 of file PPCISelLowering.cpp.
References llvm::sampleprof::Base, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isConsecutiveLSLoc(), and N.
Referenced by findConsecutiveLoad().
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Definition at line 13708 of file PPCISelLowering.cpp.
References llvm::sampleprof::Base, llvm::ISD::FrameIndex, getBaseWithConstantOffset(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::TargetLowering::isGAPlusOffset().
Referenced by isConsecutiveLS().
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isConstantOrUndef - Op is either an undef node or a ConstantSDNode.
Return true if Op is undef or if it matches the specified value.
Definition at line 1874 of file PPCISelLowering.cpp.
isFloatingPointZero - Return true if this is 0.0 or -0.0.
Definition at line 1860 of file PPCISelLowering.cpp.
References llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().
Definition at line 14547 of file PPCISelLowering.cpp.
References llvm::ISD::EXTLOAD.
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Definition at line 5246 of file PPCISelLowering.cpp.
References llvm::GlobalValue::getValueType(), llvm::Type::isFunctionTy(), and llvm::GlobalValue::isThreadLocal().
Referenced by isIndirectCall(), and transformCallee().
Definition at line 6723 of file PPCISelLowering.cpp.
References assert(), llvm::report_fatal_error(), and llvm::Align::value().
Referenced by CC_AIX().
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Definition at line 5321 of file PPCISelLowering.cpp.
References G, isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), and llvm::PPCSubtarget::usesFunctionDescriptors().
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Check that the mask is shuffling N byte elements.
Within each N byte element of the mask, the indices could be either in increasing or decreasing order as long as they are consecutive.
[in] | N | the shuffle vector SD Node to analyze |
[in] | Width | the element width in bytes, could be 2/4/8/16 (HalfWord/ Word/DoubleWord/QuadWord). |
[in] | StepLen | the delta indices number among the N byte element, if the mask is in increasing/decreasing order then it is 1/-1. |
Definition at line 2252 of file PPCISelLowering.cpp.
Referenced by isXXBRShuffleMaskHelper(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), and llvm::PPC::isXXSLDWIShuffleMask().
Definition at line 18201 of file PPCISelLowering.cpp.
References llvm::PPCISD::MAT_PCREL_ADDR, and N.
Referenced by llvm::PPCTargetLowering::SelectOptimalAddrMode().
Definition at line 15329 of file PPCISelLowering.cpp.
References llvm::ISD::BITCAST, and llvm::ISD::SCALAR_TO_VECTOR.
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Definition at line 12769 of file PPCISelLowering.cpp.
References MI.
Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::InstCombiner::getFreelyInvertedImpl(), isReductionCandidate(), and lowerVECTOR_SHUFFLE().
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Definition at line 12750 of file PPCISelLowering.cpp.
References MI.
Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 12045 of file PPCISelLowering.cpp.
Definition at line 15310 of file PPCISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::DWARFExpression::Operation::getNumOperands(), and llvm::SDValue::isUndef().
Definition at line 15655 of file PPCISelLowering.cpp.
References llvm::SDValue::getConstantOperandVal().
Referenced by llvm::PPCTargetLowering::PerformDAGCombine().
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Definition at line 5346 of file PPCISelLowering.cpp.
References llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), and llvm::PPCSubtarget::isUsingPCRelativeCalls().
Referenced by buildCallOperands(), and getCallOpcode().
Definition at line 2978 of file PPCISelLowering.cpp.
References llvm::PPCInstrInfo::hasPCRelFlag(), and N.
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Definition at line 9306 of file PPCISelLowering.cpp.
References llvm::MemSDNode::getMemoryVT(), llvm::EVT::getVectorElementType(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isSEXTLoad(), llvm::ISD::isUNINDEXEDLoad(), llvm::ISD::isZEXTLoad(), llvm::PPCISD::SEXT_LD_SPLAT, and llvm::PPCISD::ZEXT_LD_SPLAT.
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Common function used to match vmrgew and vmrgow shuffles.
The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.
The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size
The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:
[in] | N | The shuffle vector SD Node to analyze |
[in] | IndexOffset | Specifies whether to look for even or odd elements |
[in] | RHSStartValue | Specifies the starting index for the righthand input vector to the shuffle_vector instruction |
Definition at line 2105 of file PPCISelLowering.cpp.
References isConstantOrUndef(), and N.
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isVMerge - Common function, used to match vmrg* shuffles.
Definition at line 1995 of file PPCISelLowering.cpp.
References assert(), isConstantOrUndef(), and N.
Referenced by llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), and llvm::PPC::isVMRGLShuffleMask().
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Definition at line 2416 of file PPCISelLowering.cpp.
References assert(), isNByteElemShuffleMask(), and N.
Referenced by llvm::PPC::isXXBRDShuffleMask(), llvm::PPC::isXXBRHShuffleMask(), llvm::PPC::isXXBRQShuffleMask(), and llvm::PPC::isXXBRWShuffleMask().
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Definition at line 3146 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::PPCISD::GlobalBaseReg, llvm::PPCISD::Hi, llvm::Hi, llvm::PPCISD::Lo, and llvm::Lo.
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LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
Definition at line 5198 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, CalculateTailCallArgDest(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 7026 of file PPCISelLowering.cpp.
References assert(), contains(), llvm::PPCFrameLowering::getLinkageSize(), and llvm_unreachable.
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Definition at line 4878 of file PPCISelLowering.cpp.
References assert(), CalculateStackSlotUsed(), llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getLinkageSize(), and llvm::PPCSubtarget::is64BitELFABI().
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Definition at line 5520 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::PPCSubtarget::descriptorEnvironmentPointerOffset(), llvm::PPCSubtarget::descriptorTOCAnchorOffset(), llvm::CallBase::getCalledOperand(), llvm::SelectionDAG::getCopyToReg(), llvm::PPCSubtarget::getEnvironmentPointerRegister(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), getOutputChainFromCallSeq(), llvm::PPCSubtarget::getTOCPointerRegister(), llvm::SDValue::getValue(), llvm::MachinePointerInfo::getWithOffset(), llvm::PPCSubtarget::isAIXABI(), llvm::PPCSubtarget::isPPC64(), llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MONone, and prepareIndirectCall().
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Definition at line 5509 of file PPCISelLowering.cpp.
References llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), and llvm::PPCISD::MTCTR.
Referenced by prepareDescriptorIndirectCall().
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Used when computing address flags for selecting loads and stores.
If we have an OR, check if the LHS and RHS are provably disjoint. An OR of two provably disjoint values is equivalent to an ADD. Most PPC load/store instructions compute the effective address as a sum, so doing this conversion is useful.
Definition at line 2656 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::computeKnownBits(), llvm::APInt::getBoolValue(), N, llvm::ISD::OR, and llvm::KnownBits::Zero.
Referenced by computeFlagsForAddressComputation(), and llvm::PPCTargetLowering::SelectForceXFormMode().
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Set alignment flags based on whether or not the Frame Index is aligned.
Utilized when computing flags for address computation when selecting load and store instructions.
Definition at line 18120 of file PPCISelLowering.cpp.
References llvm::ISD::ADD, llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, N, llvm::ISD::OR, and llvm::Align::value().
Referenced by computeFlagsForAddressComputation().
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Definition at line 3165 of file PPCISelLowering.cpp.
References llvm::MachineFunction::getInfo(), and llvm::PPCFunctionInfo::setUsesTOCBasePtr().
Referenced by llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), and setUsesTOCBasePtr().
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Definition at line 3170 of file PPCISelLowering.cpp.
References llvm::SelectionDAG::getMachineFunction(), and setUsesTOCBasePtr().
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Definition at line 18494 of file PPCISelLowering.cpp.
References llvm::PPC::AM_DQForm, llvm::PPC::AM_DSForm, llvm::PPC::AM_XForm, llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, and N.
Referenced by llvm::PPCTargetLowering::SelectOptimalAddrMode().
STATISTIC | ( | NumDynamicAllocaProbed | , |
"Number of dynamic stack allocation probed" | |||
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STATISTIC | ( | NumSiblingCalls | , |
"Number of sibling calls" | |||
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STATISTIC | ( | NumTailCalls | , |
"Number of tail calls" | |||
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STATISTIC | ( | ShufflesHandledWithVPERM | , |
"Number of shuffles lowered to a VPERM or XXPERM" | |||
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StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
Definition at line 5109 of file PPCISelLowering.cpp.
References llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorBase< Size_T >::size().
Referenced by PrepareTailCall().
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Definition at line 17655 of file PPCISelLowering.cpp.
References llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::EVT::isVector(), llvm_unreachable, N, llvm::ISD::SHL, llvm::PPCISD::SHL, llvm::ISD::SRA, llvm::PPCISD::SRA, llvm::ISD::SRL, and llvm::PPCISD::SRL.
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Definition at line 5414 of file PPCISelLowering.cpp.
References assert(), Context, F, G, llvm::MachineModuleInfo::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::TargetLoweringObjectFile::getFunctionEntryPointSymbol(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMCSymbol(), llvm::SectionKind::getMetadata(), llvm::MachineFunction::getMMI(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::MCSectionXCOFF::getQualNameSymbol(), llvm::TargetMachine::getRelocationModel(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::PPCSubtarget::getTargetMachine(), llvm::PPCSubtarget::is32BitELFABI(), llvm::PPCSubtarget::isAIXABI(), isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), llvm::PPCII::MO_PLT, llvm::Mod, llvm::Reloc::PIC_, llvm::TargetMachine::shouldAssumeDSOLocal(), TM, llvm::PPCSubtarget::usesFunctionDescriptors(), llvm::XCOFF::XMC_PR, and llvm::XCOFF::XTY_ER.
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Definition at line 7010 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::EVT::getFixedSizeInBits(), llvm::MVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::isScalarInteger(), llvm::MVT::isScalarInteger(), and llvm::ISD::TRUNCATE.
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Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
Definition at line 3001 of file PPCISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isSimple(), N, llvm::ISD::SCALAR_TO_VECTOR, llvm::PPCISD::SCALAR_TO_VECTOR_PERMUTED, and llvm::MVT::SimpleTy.
Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().
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Definition at line 8590 of file PPCISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), and llvm::EVT::isVector().
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Definition at line 156 of file PPCISelLowering.cpp.
Definition at line 150 of file PPCISelLowering.cpp.
Referenced by llvm::PPCTargetLowering::getSDagStackGuard(), and llvm::PPCTargetLowering::insertSSPDeclarations().
cl::opt< bool > DisableAutoPairedVecSt("disable-auto-paired-vec-st", cl::desc("disable automatically generated 32byte paired vector stores"), cl::init(true), cl::Hidden) | ( | "disable-auto-paired-vec-st" | , |
cl::desc("disable automatically generated 32byte paired vector stores") | , | ||
cl::init(true) | , | ||
cl::Hidden | |||
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Referenced by llvm::PPCTargetLowering::getSchedulingPreference().
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Referenced by llvm::PPCTargetLowering::getPrefLoopAlignment().
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Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().
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Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses().
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FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
Definition at line 4008 of file PPCISelLowering.cpp.
Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), CC_AIX(), and llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().
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Referenced by llvm::PPCTargetLowering::PPCTargetLowering().