#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ComplexDeinterleavingPass.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcallUtil.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <optional>
#include <tuple>
#include <utility>
#include <vector>

Classes
struct	BaseUpdateTarget
	Load/store instruction that can be merged with a base address update. More...
struct	BaseUpdateUser

Macros
#define	DEBUG_TYPE "arm-isel"

Typedefs
using	RCPair = std::pair<unsigned, const TargetRegisterClass *>

Enumerations
enum	ShuffleOpCodes { OP_COPY = 0 , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR }
enum	HABaseType { HA_UNKNOWN = 0 , HA_FLOAT , HA_DOUBLE , HA_VECT64 , HA_VECT128 }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
	STATISTIC (NumOptimizedImms, "Number of times immediates were optimized")
	STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt")
	STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments")
	STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools")
static SDValue	handleCMSEValue (const SDValue &Value, const ISD::InputArg &Arg, SelectionDAG &DAG, const SDLoc &DL)
static bool	isSRL16 (const SDValue &Op)
static bool	isSRA16 (const SDValue &Op)
static bool	isSHL16 (const SDValue &Op)
static bool	isS16 (const SDValue &Op, SelectionDAG &DAG)
static ARMCC::CondCodes	IntCCToARMCC (ISD::CondCode CC)
	IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
static void	FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
	FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
static bool	canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls)
static SDValue	LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)
static bool	allUsersAreInFunction (const Value V, const Function F)
	Return true if all users of V are within function F, looking through ConstantExprs.
static SDValue	promoteToConstantPool (const ARMTargetLowering TLI, const GlobalValue GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl)
static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVASTART (SDValue Op, SelectionDAG &DAG)
static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is +0.0.
static bool	isSafeSignedCMN (SDValue Op, SelectionDAG &DAG)
static bool	isCMN (SDValue Op, ISD::CondCode CC, SelectionDAG &DAG)
static unsigned	getCmpOperandFoldingProfit (SDValue Op, const ARMSubtarget &ST)
	Returns how profitable it is to fold a comparison's operand's shift and/or extension operations into the comparison instruction's second operand (so_reg_imm / so_reg_reg for ARM, t2_so_reg for Thumb-2).
static SDValue	valueToCarryFlag (SDValue Value, SelectionDAG &DAG, bool Invert)
static SDValue	carryFlagToValue (SDValue Flags, EVT VT, SelectionDAG &DAG, bool Invert)
static SDValue	overflowFlagToValue (SDValue Flags, EVT VT, SelectionDAG &DAG)
static SDValue	LowerADDSUBSAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static void	checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
static bool	isGTorGE (ISD::CondCode CC)
static bool	isLTorLE (ISD::CondCode CC)
static bool	isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
static SDValue	LowerSaturatingConditional (SDValue Op, SelectionDAG &DAG)
static bool	isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK)
static SDValue	matchCSET (unsigned &Opcode, bool &InvertCond, SDValue TrueVal, SDValue FalseVal, const ARMSubtarget *Subtarget)
static bool	canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
	canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.
static SDValue	bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
static void	expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
static SDValue	getInvertedARMCondCode (SDValue ARMcc, SelectionDAG &DAG)
static SDValue	LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
static void	ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static SDValue	CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
	`BC` is a bitcast that is about to be turned into a VMOVDRR.
static SDValue	getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	getZeroVector - Returns a vector of specified type with all zero elements.
static SDValue	LowerCTTZ (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	LowerCTPOP (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
	Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
	isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
static SDValue	LowerShift (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	Expand64BitShift (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	LowerVSETCC (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG)
static SDValue	isVMOVModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type)
	isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).
static bool	isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
static bool	isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
static bool	isVTBLMask (ArrayRef< int > M, EVT VT)
static unsigned	SelectPairHalf (unsigned Elements, ArrayRef< int > Mask, unsigned Index)
static bool	isVTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isVUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static bool	isVZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
static bool	isVZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
	isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
static unsigned	isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
	Check if `ShuffleMask` is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
static bool	isReverseMask (ArrayRef< int > M, EVT VT)
static bool	isTruncMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNTruncMask (ArrayRef< int > M, EVT ToVT, bool rev)
static SDValue	LowerBuildVectorOfFPTrunc (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBuildVectorOfFPExt (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)
static SDValue	LowerBUILD_VECTOR_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBUILD_VECTORToVIDUP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static bool	IsQRMVEInstruction (const SDNode N, const SDNode Op)
static bool	isLegalMVEShuffleOp (unsigned PFEntry)
static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
static SDValue	LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerReverse_VECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
static EVT	getVectorTyFromPredicateVector (EVT VT)
static SDValue	PromoteMVEPredVector (SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVECTOR_SHUFFLEUsingMovs (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEUsingOneOff (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerINSERT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerTruncatei1 (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	LowerTruncate (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	LowerVectorExtend (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static bool	isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
	isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.
static bool	isSignExtended (SDNode *N, SelectionDAG &DAG)
	isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.
static bool	isZeroExtended (SDNode *N, SelectionDAG &DAG)
	isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.
static EVT	getExtensionTo64Bits (const EVT &OrigVT)
static SDValue	AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
	AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.
static SDValue	SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
	SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.
static SDValue	SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
	SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.
static bool	isAddSubSExt (SDNode *N, SelectionDAG &DAG)
static bool	isAddSubZExt (SDNode *N, SelectionDAG &DAG)
static SDValue	LowerMUL (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerUDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerADDSUBO_CARRY (SDValue Op, SelectionDAG &DAG, unsigned Opcode, bool IsSigned)
static SDValue	WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)
static SDValue	LowerPredicateLoad (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPredicateStore (SDValue Op, SelectionDAG &DAG)
static bool	isZeroVector (SDValue N)
static SDValue	LowerMLOAD (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVecReduce (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceF (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceMinMax (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
static void	ReplaceREADCYCLECOUNTER (SDNode N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	createGPRPairNode2xi32 (SelectionDAG &DAG, SDValue V0, SDValue V1)
static SDValue	createGPRPairNodei64 (SelectionDAG &DAG, SDValue V)
static void	ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static void	ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static MachineBasicBlock *	OtherSucc (MachineBasicBlock MBB, MachineBasicBlock Succ)
static unsigned	getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
	Return the load opcode for a given load size.
static unsigned	getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
	Return the store opcode for a given store size.
static void	emitPostLd (MachineBasicBlock BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment load operation with given size.
static void	emitPostSt (MachineBasicBlock BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment store operation with given size.
static bool	checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock BB, const TargetRegisterInfo TRI)
static Register	genTPEntry (MachineBasicBlock TpEntry, MachineBasicBlock TpLoopBody, MachineBasicBlock TpExit, Register OpSizeReg, const TargetInstrInfo TII, DebugLoc Dl, MachineRegisterInfo &MRI)
	Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.
static void	genTPLoopBody (MachineBasicBlock TpLoopBody, MachineBasicBlock TpEntry, MachineBasicBlock TpExit, const TargetInstrInfo TII, DebugLoc Dl, MachineRegisterInfo &MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy)
	Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.
static void	attachMEMCPYScratchRegs (const ARMSubtarget Subtarget, MachineInstr &MI, const SDNode Node)
	Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.
static bool	isZeroOrAllOnes (SDValue N, bool AllOnes)
static bool	isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
static SDValue	combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
static bool	IsVUZPShuffleNode (SDNode *N)
static SDValue	AddCombineToVPADD (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	AddCombineVUZPToVPADDL (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	AddCombineBUILD_VECTORToVPADDL (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	findMUL_LOHI (SDValue V)
static SDValue	AddCombineTo64BitSMLAL16 (SDNode AddcNode, SDNode AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineTo64bitMLAL (SDNode AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	AddCombineTo64bitUMAAL (SDNode AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformUMLALCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformAddcSubcCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformAddeSubeCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformSELECTCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformVQDMULHCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVSELECTCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformVSetCCToVCTPCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformADDECombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.
static SDValue	PerformADDCombineWithOperands (SDNode N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
static SDValue	TryDistrubutionADDVecReduce (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformADDVecReduce (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformSHLSimplify (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
static SDValue	PerformADDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
static SDValue	PerformSubCSINCCombine (SDNode *N, SelectionDAG &DAG)
static int	getNegationCost (SDValue Op)
static SDValue	performNegCMovCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformSUBCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
static SDValue	PerformVMULCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.
static SDValue	PerformMVEVMULLCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformMULCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	CombineANDShift (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformANDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformORCombineToSMULWBT (SDNode OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformORCombineToBFI (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static bool	isValidMVECond (unsigned CC, bool IsFloat)
static ARMCC::CondCodes	getVCMPCondCode (SDValue N)
static bool	CanInvertMVEVCMP (SDValue N)
static SDValue	PerformORCombine_i1 (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformORCombineToShiftInsert (SelectionDAG &DAG, SDValue AndOp, SDValue ShiftOp, EVT VT, SDLoc dl)
static SDValue	PerformORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformORCombine - Target-specific dag combine xforms for ISD::OR.
static SDValue	PerformXORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)
static bool	BitsProperlyConcatenate (const APInt &A, const APInt &B)
static SDValue	FindBFIToCombineWith (SDNode *N)
static SDValue	PerformBFICombine (SDNode *N, SelectionDAG &DAG)
static SDValue	IsCMPZCSINC (SDNode *Cmp, ARMCC::CondCodes &CC)
static SDValue	PerformCMPZCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformCSETCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVRRDCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
static SDValue	PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
	PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.
static SDValue	PerformVMOVhrCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVMOVrhCombine (SDNode *N, SelectionDAG &DAG)
static bool	hasNormalLoadOperand (SDNode *N)
	hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.
static SDValue	PerformBUILD_VECTORCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.
static SDValue	PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
static SDValue	PerformPREDICATE_CASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVECTOR_REG_CASTCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	PerformVCMPCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.
static SDValue	PerformExtractEltToVMOVRRD (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformExtractEltCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
static SDValue	PerformSignExtendInregCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformShuffleVMOVNCombine (ShuffleVectorSDNode *N, SelectionDAG &DAG)
static SDValue	PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
	PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.
static bool	isValidBaseUpdate (SDNode N, SDNode User)
static bool	TryCombineBaseUpdate (struct BaseUpdateTarget &Target, struct BaseUpdateUser &User, bool SimpleConstIncOnly, TargetLowering::DAGCombinerInfo &DCI)
static unsigned	getPointerConstIncrement (unsigned Opcode, SDValue Ptr, SDValue Inc, const SelectionDAG &DAG)
static bool	findPointerConstIncrement (SDNode N, SDValue Ptr, SDValue *CInc)
static SDValue	CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.
static SDValue	PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformMVEVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
static SDValue	PerformVDUPLANECombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.
static SDValue	PerformVDUPCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
static SDValue	PerformLOADCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
static SDValue	PerformTruncatingStoreCombine (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingMVETruncToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformExtractFpToIntStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSTORECombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget Subtarget)
	PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.
static SDValue	PerformVCVTCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.
static SDValue	PerformFAddVSelectCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformFADDVCMLACombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformFADDCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
static SDValue	PerformVMulVCTPCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget Subtarget)
	PerformVMulVCTPCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VMUL when the VMUL has a constant operand that is a power of 2.
static SDValue	PerformVECREDUCE_ADDCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	PerformReduceShuffleCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQDMULHCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformLongShiftCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformShiftCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
	PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.
static SDValue	PerformSplittingToWideningLoad (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformExtendCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
	PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
static SDValue	PerformFPExtendCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
static SDValue	PerformMinMaxToSatCombine (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformMinMaxCombine (SDNode N, SelectionDAG &DAG, const ARMSubtarget ST)
	PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.
static const APInt *	isPowerOf2Constant (SDValue V)
static SDValue	SearchLoopIntrinsic (SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate)
static SDValue	PerformHWLoopCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
static SDValue	PerformBITCASTCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget ST)
static SDValue	PerformSplittingMVEEXTToWideningLoad (SDNode *N, SelectionDAG &DAG)
static bool	isLegalT1AddressImmediate (int64_t V, EVT VT)
static bool	isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
static bool	isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
	isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.
static bool	getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getMVEIndexedAddressParts (SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	isLegalLogicalImmediate (unsigned Imm, const ARMSubtarget *Subtarget)
static bool	optimizeLogicalImm (SDValue Op, unsigned Imm, const APInt &DemandedBits, const ARMSubtarget *Subtarget, TargetLowering::TargetLoweringOpt &TLO)
	Refine i32 AND/OR/XOR with a constant RHS using demanded bits: replace the immediate with an equivalent constant that ARM/Thumb can encode as a logical immediate (or that selects better lowering), without changing the computed result on those demanded bits.
static bool	isIncompatibleReg (const MCPhysReg &PR, MVT VT)
static RTLIB::Libcall	getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)
static TargetLowering::ArgListTy	getDivRemArgList (const SDNode N, LLVMContext Context, const ARMSubtarget *Subtarget)
static bool	isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)

Variables
static cl::opt< bool >	ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static cl::opt< bool >	EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))
static cl::opt< unsigned >	ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
static cl::opt< unsigned >	ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
cl::opt< unsigned >	MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))
cl::opt< unsigned >	ArmMaxBaseUpdatesToCheck ("arm-max-base-updates-to-check", cl::Hidden, cl::desc("Maximum number of base-updates to check generating postindex."), cl::init(64))
constexpr MVT	FlagsVT = MVT::i32
	Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).
static const MCPhysReg	GPRArgRegs []

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "arm-isel"

Definition at line 118 of file ARMISelLowering.cpp.

Typedef Documentation

◆ RCPair

using RCPair = std::pair<unsigned, const TargetRegisterClass *>

Definition at line 20640 of file ARMISelLowering.cpp.

Enumeration Type Documentation

◆ HABaseType

enum HABaseType

Enumerator
HA_UNKNOWN
HA_FLOAT
HA_DOUBLE
HA_VECT64
HA_VECT128

Definition at line 22206 of file ARMISelLowering.cpp.

◆ ShuffleOpCodes

enum ShuffleOpCodes

Enumerator
OP_COPY
OP_VREV
OP_VDUP0
OP_VDUP1
OP_VDUP2
OP_VDUP3
OP_VEXT1
OP_VEXT2
OP_VEXT3
OP_VUZPL
OP_VUZPR
OP_VZIPL
OP_VZIPR
OP_VTRNL
OP_VTRNR

Definition at line 8223 of file ARMISelLowering.cpp.

Function Documentation

◆ AddCombineBUILD_VECTORToVPADDL()

SDValue AddCombineBUILD_VECTORToVPADDL	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 12724 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, N, SDValue(), llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

Referenced by PerformADDCombineWithOperands().

◆ AddCombineTo64bitMLAL()

SDValue AddCombineTo64bitMLAL	(	SDNode *	AddeSubeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 12905 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddCombineTo64BitSMLAL16(), assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::isPredecessorOf(), Opc, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SMUL_LOHI, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().

Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().

◆ AddCombineTo64BitSMLAL16()

SDValue AddCombineTo64BitSMLAL16	(	SDNode *	AddcNode,
		SDNode *	AddeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 12828 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasBaseDSP(), llvm::Hi, isS16(), isSRA16(), llvm::Lo, llvm::ISD::MUL, Mul, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ISD::SRA.

Referenced by AddCombineTo64bitMLAL().

◆ AddCombineTo64bitUMAAL()

SDValue AddCombineTo64bitUMAAL	(	SDNode *	AddeNode,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 13071 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and SDValue().

Referenced by PerformADDECombine().

◆ AddCombineToVPADD()

SDValue AddCombineToVPADD	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 12643 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, IsVUZPShuffleNode(), N, and SDValue().

Referenced by PerformADDCombineWithOperands().

◆ AddCombineVUZPToVPADDL()

SDValue AddCombineVUZPToVPADDL	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 12671 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), N, SDValue(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by PerformADDCombineWithOperands().

◆ AddRequiredExtensionForVMULL()

SDValue AddRequiredExtensionForVMULL	(	SDValue	N,
		SelectionDAG &	DAG,
		const EVT &	OrigTy,
		const EVT &	ExtTy,
		unsigned	ExtOpcode )

static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 9355 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.

Referenced by SkipExtensionForVMULL().

◆ allUsersAreInFunction()

bool allUsersAreInFunction	(	const Value *	V,
		const Function *	F )

static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 3550 of file ARMISelLowering.cpp.

References llvm::append_range(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, I, llvm::isa(), and llvm::SmallVectorImpl< T >::pop_back_val().

Referenced by promoteToConstantPool().

◆ attachMEMCPYScratchRegs()

void attachMEMCPYScratchRegs	(	const ARMSubtarget *	Subtarget,
		MachineInstr &	MI,
		const SDNode *	Node )

static

Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.

This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.

Definition at line 12376 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Dead, llvm::Define, llvm::getImm(), llvm::MachineFunction::getRegInfo(), I, llvm::ARMSubtarget::isThumb1Only(), and MI.

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection().

◆ bitcastf32Toi32()

SDValue bitcastf32Toi32	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 5469 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), isFloatingPointZero(), and llvm_unreachable.

◆ BitsProperlyConcatenate()

bool BitsProperlyConcatenate	(	const APInt &	A,
		const APInt &	B )

static

Definition at line 15026 of file ARMISelLowering.cpp.

References A(), and B().

Referenced by FindBFIToCombineWith().

◆ canChangeToInt()

bool canChangeToInt	(	SDValue	Op,
		bool &	SeenZero,
		const ARMSubtarget *	Subtarget )

static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 5448 of file ARMISelLowering.cpp.

References isFloatingPointZero(), llvm::ISD::isNormalLoad(), and N.

◆ canGuaranteeTCO()

bool canGuaranteeTCO	(	CallingConv::ID	CC,
		bool	GuaranteeTailCalls )

static

Definition at line 2005 of file ARMISelLowering.cpp.

References llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

◆ CanInvertMVEVCMP()

bool CanInvertMVEVCMP ( SDValue N )

static

Definition at line 14752 of file ARMISelLowering.cpp.

References llvm::ARMCC::getOppositeCondition(), getVCMPCondCode(), isValidMVECond(), and N.

Referenced by PerformORCombine_i1(), and PerformXORCombine().

◆ carryFlagToValue()

SDValue carryFlagToValue	(	SDValue	Flags,
		EVT	VT,
		SelectionDAG &	DAG,
		bool	Invert )

static

Definition at line 4837 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::ISD::SUB.

◆ checkAndUpdateCPSRKill()

bool checkAndUpdateCPSRKill	(	MachineBasicBlock::iterator	SelectItr,
		MachineBasicBlock *	BB,
		const TargetRegisterInfo *	TRI )

static

Definition at line 11830 of file ARMISelLowering.cpp.

References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::successors(), and TRI.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

◆ checkVSELConstraints()

void checkVSELConstraints	(	ISD::CondCode	CC,
		ARMCC::CondCodes &	CondCode,
		bool &	swpCmpOps,
		bool &	swpVselOps )

static

Definition at line 5020 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.

◆ CombineANDShift()

SDValue CombineANDShift	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ CombineBaseUpdate()

SDValue CombineBaseUpdate	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 16344 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, ArmMaxBaseUpdatesToCheck, llvm::sampleprof::Base, llvm::TargetLowering::DAGCombinerInfo::DAG, findPointerConstIncrement(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::User::getNumOperands(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::Use::getOperandNo(), getPointerConstIncrement(), llvm::SDValue::getResNo(), llvm::Use::getUser(), I, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isIntrinsic(), isStore(), LHS, N, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RHS, SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::stable_sort(), llvm::ISD::STORE, TryCombineBaseUpdate(), and llvm::SDNode::uses().

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

◆ combineSelectAndUse()

SDValue combineSelectAndUse	(	SDNode *	N,
		SDValue	Slct,
		SDValue	OtherOp,
		TargetLowering::DAGCombinerInfo &	DCI,
		bool	AllOnes = false )

static

Definition at line 12592 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), isConditionalZeroOrAllOnes(), N, SDValue(), llvm::ISD::SELECT, and std::swap().

Referenced by combineSelectAndUseCommutative(), combineSelectAndUseCommutative(), combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), PerformSUBCombine(), PerformSUBCombine(), and performSUBCombine().

◆ combineSelectAndUseCommutative()

SDValue combineSelectAndUseCommutative	(	SDNode *	N,
		bool	AllOnes,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 12618 of file ARMISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), N, and SDValue().

Referenced by performADDCombine(), PerformANDCombine(), performANDCombine(), llvm::LanaiTargetLowering::PerformDAGCombine(), PerformORCombine(), performORCombine(), PerformXORCombine(), and performXORCombine().

◆ CombineVLDDUP()

bool CombineVLDDUP	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.

If so, combine them to a vldN-dup operation and return true.

Definition at line 16561 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::Use::getUser(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), N, SDValue(), llvm::SDNode::uses(), llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.

Referenced by PerformVDUPLANECombine().

◆ CombineVMOVDRRCandidateWithVecOp()

SDValue CombineVMOVDRRCandidateWithVecOp	(	const SDNode *	BC,
		SelectionDAG &	DAG )

static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 6051 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::EVT::isVector(), and SDValue().

◆ createGPRPairNode2xi32()

SDValue createGPRPairNode2xi32	(	SelectionDAG &	DAG,
		SDValue	V0,
		SDValue	V1 )

static

Definition at line 10309 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getTargetConstant(), SDValue(), and llvm::V1.

Referenced by createGPRPairNodei64(), and ReplaceCMP_SWAP_64Results().

◆ createGPRPairNodei64()

SDValue createGPRPairNodei64	(	SelectionDAG &	DAG,
		SDValue	V )

static

Definition at line 10321 of file ARMISelLowering.cpp.

References createGPRPairNode2xi32(), llvm::SelectionDAG::getDataLayout(), isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::SelectionDAG::SplitScalar(), and std::swap().

Referenced by ReplaceCMP_SWAP_64Results().

◆ emitPostLd()

void emitPostLd	(	MachineBasicBlock *	BB,
		MachineBasicBlock::iterator	Pos,
		const TargetInstrInfo *	TII,
		const DebugLoc &	dl,
		unsigned	LdSize,
		unsigned	Data,
		unsigned	AddrIn,
		unsigned	AddrOut,
		bool	IsThumb1,
		bool	IsThumb2 )

static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11388 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, llvm::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

◆ emitPostSt()

void emitPostSt	(	MachineBasicBlock *	BB,
		MachineBasicBlock::iterator	Pos,
		const TargetInstrInfo *	TII,
		const DebugLoc &	dl,
		unsigned	StSize,
		unsigned	Data,
		unsigned	AddrIn,
		unsigned	AddrOut,
		bool	IsThumb1,
		bool	IsThumb2 )

static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11429 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

◆ Expand64BitShift()

SDValue Expand64BitShift	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

◆ expandf64Toi32()

void expandf64Toi32	(	SDValue	Op,
		SelectionDAG &	DAG,
		SDValue &	RetVal1,
		SDValue &	RetVal2 )

static

Definition at line 5481 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::commonAlignment(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), isFloatingPointZero(), and llvm_unreachable.

◆ ExpandREAD_REGISTER()

void ExpandREAD_REGISTER	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG )

static

Definition at line 6026 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), N, llvm::Read, llvm::ISD::READ_REGISTER, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ FindBFIToCombineWith()

SDValue FindBFIToCombineWith ( SDNode * N )

static

Definition at line 15032 of file ARMISelLowering.cpp.

References BitsProperlyConcatenate(), N, ParseBFI(), and SDValue().

Referenced by PerformBFICombine().

◆ findMUL_LOHI()

SDValue findMUL_LOHI ( SDValue V )

static

Definition at line 12821 of file ARMISelLowering.cpp.

References SDValue(), llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.

Referenced by AddCombineTo64bitMLAL().

◆ findPointerConstIncrement()

bool findPointerConstIncrement	(	SDNode *	N,
		SDValue *	Ptr,
		SDValue *	CInc )

static

Definition at line 16315 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::isa(), N, llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

◆ FPCCToARMCC()

void FPCCToARMCC	(	ISD::CondCode	CC,
		ARMCC::CondCodes &	CondCode,
		ARMCC::CondCodes &	CondCode2 )

static

FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.

Definition at line 1653 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

◆ GeneratePerfectShuffle()

SDValue GeneratePerfectShuffle	(	unsigned	PFEntry,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 8314 of file ARMISelLowering.cpp.

References assert(), GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, llvm::PerfectShuffleTable, and RHS.

◆ genTPEntry()

Register genTPEntry	(	MachineBasicBlock *	TpEntry,
		MachineBasicBlock *	TpLoopBody,
		MachineBasicBlock *	TpExit,
		Register	OpSizeReg,
		const TargetInstrInfo *	TII,
		DebugLoc	Dl,
		MachineRegisterInfo &	MRI )

static

Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.

Definition at line 11859 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::Kill, llvm::predOps(), and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

◆ genTPLoopBody()

void genTPLoopBody	(	MachineBasicBlock *	TpLoopBody,
		MachineBasicBlock *	TpEntry,
		MachineBasicBlock *	TpExit,
		const TargetInstrInfo *	TII,
		DebugLoc	Dl,
		MachineRegisterInfo &	MRI,
		Register	OpSrcReg,
		Register	OpDestReg,
		Register	ElementCountReg,
		Register	TotalIterationsReg,
		bool	IsMemcpy )

static

Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.

These are used by later passes to generate tail predicated loops.

Definition at line 11897 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::ARMVCC::None, llvm::predOps(), llvm::ARMVCC::Then, and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

◆ getARMIndexedAddressParts()

bool getARMIndexedAddressParts	(	SDNode *	Ptr,
		EVT	VT,
		bool	isSEXTLoad,
		SDValue &	Base,
		SDValue &	Offset,
		bool &	isInc,
		SelectionDAG &	DAG )

static

Definition at line 19907 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::ARM_AM::no_shift, llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

◆ getCmpOperandFoldingProfit()

unsigned getCmpOperandFoldingProfit	(	SDValue	Op,
		const ARMSubtarget &	ST )

static

Returns how profitable it is to fold a comparison's operand's shift and/or extension operations into the comparison instruction's second operand (so_reg_imm / so_reg_reg for ARM, t2_so_reg for Thumb-2).

Definition at line 4549 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::isa(), Opc, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

◆ getDivRemArgList()

TargetLowering::ArgListTy getDivRemArgList	(	const SDNode *	N,
		LLVMContext *	Context,
		const ARMSubtarget *	Subtarget )

static

Definition at line 20909 of file ARMISelLowering.cpp.

References assert(), llvm::ARMSubtarget::getTargetTriple(), llvm::EVT::getTypeForEVT(), llvm::Triple::isOSWindows(), isSigned(), N, llvm::ISD::SDIVREM, llvm::ISD::SREM, std::swap(), llvm::ISD::UDIVREM, and llvm::ISD::UREM.

◆ getDivRemLibcall()

RTLIB::Libcall getDivRemLibcall	(	const SDNode *	N,
		MVT::SimpleValueType	SVT )

static

Definition at line 20891 of file ARMISelLowering.cpp.

References assert(), isSigned(), llvm_unreachable, N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

◆ getExtensionTo64Bits()

EVT getExtensionTo64Bits ( const EVT & OrigVT )

static

Definition at line 9335 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().

◆ getInvertedARMCondCode()

SDValue getInvertedARMCondCode	(	SDValue	ARMcc,
		SelectionDAG &	DAG )

static

Definition at line 5574 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getConstant(), and llvm::ARMCC::getOppositeCondition().

◆ getLdOpcode()

unsigned getLdOpcode	(	unsigned	LdSize,
		bool	IsThumb1,
		bool	IsThumb2 )

static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 11350 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

◆ getMVEIndexedAddressParts()

bool getMVEIndexedAddressParts	(	SDNode *	Ptr,
		EVT	VT,
		Align	Alignment,
		bool	isSEXTLoad,
		bool	IsMasked,
		bool	isLE,
		SDValue &	Base,
		SDValue &	Offset,
		bool &	isInc,
		SelectionDAG &	DAG )

static

Definition at line 19991 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::isa(), llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

◆ getNegationCost()

int getNegationCost ( SDValue Op )

static

Definition at line 14086 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), llvm::isa(), llvm::isNullConstant(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by performNegCMovCombine().

◆ getPointerConstIncrement()

unsigned getPointerConstIncrement	(	unsigned	Opcode,
		SDValue	Ptr,
		SDValue	Inc,
		const SelectionDAG &	DAG )

static

Definition at line 16293 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

◆ getStOpcode()

unsigned getStOpcode	(	unsigned	StSize,
		bool	IsThumb1,
		bool	IsThumb2 )

static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 11369 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

◆ getT2IndexedAddressParts()

bool getT2IndexedAddressParts	(	SDNode *	Ptr,
		EVT	VT,
		bool	isSEXTLoad,
		SDValue &	Base,
		SDValue &	Offset,
		bool &	isInc,
		SelectionDAG &	DAG )

static

Definition at line 19966 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

◆ getVCMPCondCode()

ARMCC::CondCodes getVCMPCondCode ( SDValue N )

static

Definition at line 14743 of file ARMISelLowering.cpp.

References llvm_unreachable, and N.

Referenced by CanInvertMVEVCMP(), and PerformXORCombine().

◆ getVectorTyFromPredicateVector()

EVT getVectorTyFromPredicateVector ( EVT VT )

static

Definition at line 8410 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_i1(), LowerINSERT_VECTOR_ELT_i1(), and PromoteMVEPredVector().

◆ getVShiftImm()

bool getVShiftImm	(	SDValue	Op,
		unsigned	ElementBits,
		int64_t &	Cnt )

static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 6460 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

◆ getZeroVector()

SDValue getZeroVector	(	EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 6162 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), and llvm::EVT::isVector().

Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAdd(), combineAnd(), combineAndnp(), combineArithReduction(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMulToPMADD52(), combineTargetShuffle(), combineVTRUNCSAT(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), createVariablePermute(), getAVX2GatherNode(), getGatherNode(), getNullFPConstForNullVal(), getScalarMaskingNode(), getShuffleVectorZeroOrUndef(), getVectorMaskingNode(), LowerAVXCONCAT_VECTORS(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerCTTZ(), LowerMGATHER(), LowerMLOAD(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVALIGN(), lowerShuffleWithEXPAND(), lowerShuffleWithSHUFPD(), lowerV16I8Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), matchBinaryPermuteShuffle(), matchShuffleWithUNPCK(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), and widenSubVector().

◆ handleCMSEValue()

SDValue handleCMSEValue	(	const SDValue &	Value,
		const ISD::InputArg &	Arg,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Definition at line 164 of file ARMISelLowering.cpp.

References llvm::ISD::InputArg::ArgVT, assert(), llvm::EVT::bitsLT(), DL, llvm::ISD::InputArg::Flags, llvm::SelectionDAG::getNode(), llvm::EVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ hasNormalLoadOperand()

bool hasNormalLoadOperand ( SDNode * N )

static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 15411 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::ISD::isNormalLoad(), and N.

Referenced by PerformBUILD_VECTORCombine().

◆ IntCCToARMCC()

ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode CC )

static

IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.

Definition at line 1636 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by LowerSETCCCARRY().

◆ isAddSubSExt()

bool isAddSubSExt	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 9451 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.

◆ isAddSubZExt()

bool isAddSubZExt	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 9462 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.

◆ isCMN()

bool isCMN	(	SDValue	Op,
		ISD::CondCode	CC,
		SelectionDAG &	DAG )

static

Definition at line 4539 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::isKnownNeverZero(), llvm::isNullConstant(), isSafeSignedCMN(), and llvm::ISD::SUB.

◆ IsCMPZCSINC()

SDValue IsCMPZCSINC	(	SDNode *	Cmp,
		ARMCC::CondCodes &	CC )

static

Definition at line 15138 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::isNullConstant(), llvm::isOneConstant(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), PerformCMPZCombine(), and PerformCSETCombine().

◆ isConditionalZeroOrAllOnes()

bool isConditionalZeroOrAllOnes	(	SDNode *	N,
		bool	AllOnes,
		SDValue &	CC,
		bool &	Invert,
		SDValue &	OtherOp,
		SelectionDAG &	DAG )

static

Definition at line 12519 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSelectAndUse(), and combineSelectAndUse().

◆ isExtendedBUILD_VECTOR()

bool isExtendedBUILD_VECTOR	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	isSigned )

static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 9263 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, C(), llvm::dyn_cast(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::DataLayout::isBigEndian(), llvm::isIntN(), isSigned(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), and N.

◆ isFloatingPointZero()

bool isFloatingPointZero ( SDValue Op )

static

isFloatingPointZero - Return true if this is +0.0.

Definition at line 4500 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), and llvm::isNullConstant().

Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().

◆ isGTorGE()

bool isGTorGE ( ISD::CondCode CC )

static

Definition at line 5094 of file ARMISelLowering.cpp.

References llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

◆ isHomogeneousAggregate()

bool isHomogeneousAggregate	(	Type *	Ty,
		HABaseType &	Base,
		uint64_t &	Members )

static

Definition at line 22214 of file ARMISelLowering.cpp.

References llvm::sampleprof::Base, llvm::dyn_cast(), HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, and isHomogeneousAggregate().

Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(), and isHomogeneousAggregate().

◆ isIncompatibleReg()

bool isIncompatibleReg	(	const MCPhysReg &	PR,
		MVT	VT )

static

Definition at line 20630 of file ARMISelLowering.cpp.

References contains(), and llvm::MVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::getRegForInlineAsmConstraint().

◆ isLegalAddressImmediate()

bool isLegalAddressImmediate	(	int64_t	V,
		EVT	VT,
		const ARMSubtarget *	Subtarget )

static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 19700 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::isShiftedUInt(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::isUInt(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

◆ isLegalLogicalImmediate()

bool isLegalLogicalImmediate	(	unsigned	Imm,
		const ARMSubtarget *	Subtarget )

static

Definition at line 20353 of file ARMISelLowering.cpp.

References llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), and llvm::ARMSubtarget::isThumb2().

Referenced by optimizeLogicalImm().

◆ isLegalMVEShuffleOp()

bool isLegalMVEShuffleOp ( unsigned PFEntry )

static

Definition at line 8241 of file ARMISelLowering.cpp.

References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isLegalT1AddressImmediate()

bool isLegalT1AddressImmediate	(	int64_t	V,
		EVT	VT )

static

Definition at line 19620 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::isUInt(), and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

◆ isLegalT2AddressImmediate()

bool isLegalT2AddressImmediate	(	int64_t	V,
		EVT	VT,
		const ARMSubtarget *	Subtarget )

static

Definition at line 19646 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::ARMSubtarget::hasVFP2Base(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::isShiftedUInt(), llvm::isUInt(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

◆ isLowerSaturate()

bool isLowerSaturate	(	const SDValue	LHS,
		const SDValue	RHS,
		const SDValue	TrueVal,
		const SDValue	FalseVal,
		const ISD::CondCode	CC,
		const SDValue	K )

static

Definition at line 5108 of file ARMISelLowering.cpp.

References isGTorGE(), isLTorLE(), LHS, and RHS.

Referenced by isLowerSaturatingConditional().

◆ isLowerSaturatingConditional()

bool isLowerSaturatingConditional	(	const SDValue &	Op,
		SDValue &	V,
		SDValue &	SatK )

static

Definition at line 5200 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::isa(), isLowerSaturate(), LHS, and RHS.

◆ isLTorLE()

bool isLTorLE ( ISD::CondCode CC )

static

Definition at line 5098 of file ARMISelLowering.cpp.

References llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

◆ isNEONTwoResultShuffleMask()

unsigned isNEONTwoResultShuffleMask	(	ArrayRef< int >	ShuffleMask,
		EVT	VT,
		unsigned &	WhichResult,
		bool &	isV_UNDEF )

static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 7388 of file ARMISelLowering.cpp.

References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isPowerOf2Constant()

const APInt * isPowerOf2Constant ( SDValue V )

static

Definition at line 18330 of file ARMISelLowering.cpp.

References C(), llvm::dyn_cast(), and llvm::APInt::isPowerOf2().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().

◆ IsQRMVEInstruction()

bool IsQRMVEInstruction	(	const SDNode *	N,
		const SDNode *	Op )

static

Definition at line 7708 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, N, llvm::ISD::SADDSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.

◆ isReverseMask()

bool isReverseMask	(	ArrayRef< int >	M,
		EVT	VT )

static

Returns: true if this is a reverse operation on an vector.

Definition at line 7411 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), LowerVECTOR_SHUFFLE(), and LowerVECTOR_SHUFFLE_i1().

◆ isS16()

bool isS16	(	const SDValue &	Op,
		SelectionDAG &	DAG )

static

Definition at line 1629 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), isSHL16(), and isSRA16().

Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().

◆ isSafeSignedCMN()

bool isSafeSignedCMN	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 4523 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::getSignedMinValue(), and llvm::APInt::isMinSignedValue().

◆ isSHL16()

bool isSHL16 ( const SDValue & Op )

static

Definition at line 1617 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SHL.

Referenced by isS16(), and PerformORCombineToSMULWBT().

◆ isSignExtended()

bool isSignExtended	(	SDNode *	N,
		SelectionDAG &	DAG )

static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 9316 of file ARMISelLowering.cpp.

References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.

◆ IsSingleInstrConstant()

SDValue IsSingleInstrConstant	(	SDValue	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST,
		const SDLoc &	dl )

static

Definition at line 7594 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), llvm::isa(), N, and SDValue().

◆ isSingletonVEXTMask()

bool isSingletonVEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	Imm )

static

Definition at line 7089 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by LowerVECTOR_SHUFFLE().

◆ isSRA16()

bool isSRA16 ( const SDValue & Op )

static

Definition at line 1609 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SRA.

Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().

◆ isSRL16()

bool isSRL16 ( const SDValue & Op )

static

Definition at line 1601 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SRL.

Referenced by PerformORCombineToSMULWBT().

◆ isTruncMask()

bool isTruncMask	(	ArrayRef< int >	M,
		EVT	VT,
		bool	Top,
		bool	SingleSource )

static

Definition at line 7425 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and llvm::Upper.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isValidBaseUpdate()

bool isValidBaseUpdate	(	SDNode *	N,
		SDNode *	User )

static

Definition at line 15971 of file ARMISelLowering.cpp.

References llvm::SDNode::hasPredecessorHelper(), MaxSteps, N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by TryCombineBaseUpdate().

◆ isValidMVECond()

bool isValidMVECond	(	unsigned	CC,
		bool	IsFloat )

static

Definition at line 14726 of file ARMISelLowering.cpp.

References llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LT, and llvm::ARMCC::NE.

Referenced by CanInvertMVEVCMP(), and PerformVCMPCombine().

◆ isVEXTMask()

bool isVEXTMask	(	ArrayRef< int >	M,
		EVT	VT,
		bool &	ReverseVEXT,
		unsigned &	Imm )

static

Definition at line 7117 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isVMOVModifiedImm()

SDValue isVMOVModifiedImm	(	uint64_t	SplatBits,
		uint64_t	SplatUndef,
		unsigned	SplatBitSize,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT &	VT,
		EVT	VectorVT,
		VMOVModImmType	type )

static

isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).

If so, return the encoded value.

Definition at line 6838 of file ARMISelLowering.cpp.

References assert(), llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), llvm_unreachable, llvm::MVEVMVNModImm, llvm::OtherModImm, SDValue(), and llvm::VMOVModImm.

Referenced by PerformANDCombine(), and PerformORCombine().

◆ isVMOVNMask()

bool isVMOVNMask	(	ArrayRef< int >	M,
		EVT	VT,
		bool	Top,
		bool	SingleSource )

static

Definition at line 7447 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), N, and llvm::Offset.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

◆ isVMOVNTruncMask()

bool isVMOVNTruncMask	(	ArrayRef< int >	M,
		EVT	ToVT,
		bool	rev )

static

Definition at line 7471 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::PerformMVETruncCombine(), and PerformShuffleVMOVNCombine().

◆ isVShiftLImm()

bool isVShiftLImm	(	SDValue	Op,
		EVT	VT,
		bool	isLong,
		int64_t &	Cnt )

static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 6481 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

◆ isVShiftRImm()

bool isVShiftRImm	(	SDValue	Op,
		EVT	VT,
		bool	isNarrow,
		bool	isIntrinsic,
		int64_t &	Cnt )

static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 6495 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), isIntrinsic(), and llvm::EVT::isVector().

◆ isVTBLMask()

bool isVTBLMask	(	ArrayRef< int >	M,
		EVT	VT )

static

Definition at line 7153 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

◆ isVTRN_v_undef_Mask()

bool isVTRN_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 7220 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVTRNMask()

bool isVTRNMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

Definition at line 7188 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVUZP_v_undef_Mask()

bool isVUZP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 7282 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVUZPMask()

bool isVUZPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

Definition at line 7252 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ IsVUZPShuffleNode()

bool IsVUZPShuffleNode ( SDNode * N )

static

Definition at line 12631 of file ARMISelLowering.cpp.

References N.

Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().

◆ isVZIP_v_undef_Mask()

bool isVZIP_v_undef_Mask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 7356 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isVZIPMask()

bool isVZIPMask	(	ArrayRef< int >	M,
		EVT	VT,
		unsigned &	WhichResult )

static

Definition at line 7323 of file ARMISelLowering.cpp.

References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().

Referenced by isNEONTwoResultShuffleMask().

◆ isZeroExtended()

bool isZeroExtended	(	SDNode *	N,
		SelectionDAG &	DAG )

static

isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 9326 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.

◆ isZeroOrAllOnes()

bool isZeroOrAllOnes	(	SDValue	N,
		bool	AllOnes )

inlinestatic

Definition at line 12503 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::isAllOnesConstant(), llvm::isNullConstant(), and N.

Referenced by combineSelectAndUse(), isConditionalZeroOrAllOnes(), and isConditionalZeroOrAllOnes().

◆ isZeroVector()

bool isZeroVector ( SDValue N )

static

Definition at line 10096 of file ARMISelLowering.cpp.

References llvm::ISD::isBuildVectorAllZeros(), llvm::isNullConstant(), and N.

Referenced by findZeroVectorIdx(), LowerMLOAD(), PerformSUBCombine(), and PerformVCMPCombine().

◆ LowerADDSUBO_CARRY()

SDValue LowerADDSUBO_CARRY	(	SDValue	Op,
		SelectionDAG &	DAG,
		unsigned	Opcode,
		bool	IsSigned )

static

Definition at line 9731 of file ARMISelLowering.cpp.

References carryFlagToValue(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), overflowFlagToValue(), and valueToCarryFlag().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ LowerADDSUBSAT()

SDValue LowerADDSUBSAT	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 4909 of file ARMISelLowering.cpp.

References llvm::Add, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ISD::SADDSAT, SDValue(), llvm::MVT::SimpleTy, llvm::ISD::SSUBSAT, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ LowerATOMIC_FENCE()

SDValue LowerATOMIC_FENCE	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 4026 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::Release, llvm::SyncScope::SingleThread, and llvm::ARM_MB::SY.

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ LowerAtomicLoadStore()

SDValue LowerAtomicLoadStore	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 10276 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::isStrongerThanMonotonic(), and SDValue().

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerBUILD_VECTOR_i1()

SDValue LowerBUILD_VECTOR_i1	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 7611 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::sampleprof::Base, llvm::drop_begin(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), SDValue(), and llvm::ISD::SIGN_EXTEND_INREG.

◆ LowerBUILD_VECTORToVIDUP()

SDValue LowerBUILD_VECTORToVIDUP	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 7673 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), I, llvm::isa(), N, and SDValue().

◆ LowerBuildVectorOfFPExt()

SDValue LowerBuildVectorOfFPExt	(	SDValue	BV,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 7552 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::Offset, and SDValue().

◆ LowerBuildVectorOfFPTrunc()

SDValue LowerBuildVectorOfFPTrunc	(	SDValue	BV,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 7499 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), and SDValue().

◆ LowerCONCAT_VECTORS()

SDValue LowerCONCAT_VECTORS	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 9072 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), and LowerCONCAT_VECTORS_i1().

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().

◆ LowerCONCAT_VECTORS_i1()

SDValue LowerCONCAT_VECTORS_i1	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

◆ LowerCTPOP()

SDValue LowerCTPOP	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 6424 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), and N.

◆ LowerCTTZ()

SDValue LowerCTTZ	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 6368 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITREVERSE, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_POISON, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SUB, and X.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ LowerEXTRACT_SUBVECTOR()

SDValue LowerEXTRACT_SUBVECTOR	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

◆ LowerEXTRACT_VECTOR_ELT()

SDValue LowerEXTRACT_VECTOR_ELT	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 8969 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::isa(), LowerEXTRACT_VECTOR_ELT_i1(), and SDValue().

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerEXTRACT_VECTOR_ELT_i1()

SDValue LowerEXTRACT_VECTOR_ELT_i1	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 8951 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getVectorTyFromPredicateVector(), and llvm::ISD::SRL.

Referenced by LowerEXTRACT_VECTOR_ELT().

◆ LowerFP_TO_INT_SAT()

SDValue LowerFP_TO_INT_SAT	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 5786 of file ARMISelLowering.cpp.

References llvm::cast(), DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getValueType(), SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, and llvm::ISD::UMIN.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ LowerINSERT_VECTOR_ELT_i1()

SDValue LowerINSERT_VECTOR_ELT_i1	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 8888 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), and llvm::ISD::SIGN_EXTEND_INREG.

◆ LowerInterruptReturn()

SDValue LowerInterruptReturn	(	SmallVectorImpl< SDValue > &	RetOps,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Definition at line 2913 of file ARMISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), DL, F, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SmallVectorImpl< T >::insert(), and llvm::report_fatal_error().

◆ LowerMLOAD()

SDValue LowerMLOAD	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 10102 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SDValue::isUndef(), isZeroVector(), N, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ LowerMUL()

SDValue LowerMUL	(	SDValue	Op,
		SelectionDAG &	DAG )

static

◆ LowerPredicateLoad()

SDValue LowerPredicateLoad	(	SDValue	Op,
		SelectionDAG &	DAG )

static

◆ LowerPredicateStore()

SDValue LowerPredicateStore	(	SDValue	Op,
		SelectionDAG &	DAG )

static

◆ LowerPREFETCH()

SDValue LowerPREFETCH	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 4062 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMSubtarget::isThumb2().

◆ LowerReverse_VECTOR_SHUFFLE()

SDValue LowerReverse_VECTOR_SHUFFLE	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 8391 of file ARMISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), and llvm::SelectionDAG::getVectorShuffle().

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerSaturatingConditional()

SDValue LowerSaturatingConditional	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 5134 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::countr_one(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), isGTorGE(), isLTorLE(), llvm::isPowerOf2_64(), SDValue(), llvm::ISD::SELECT_CC, and llvm::V1.

◆ LowerSDIV()

SDValue LowerSDIV	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 9618 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerSDIV_v4i16()

SDValue LowerSDIV_v4i16	(	SDValue	N0,
		SDValue	N1,
		const SDLoc &	dl,
		SelectionDAG &	DAG )

static

Definition at line 9579 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, and llvm::ISD::TRUNCATE.

Referenced by LowerSDIV(), and LowerUDIV().

◆ LowerSDIV_v4i8()

SDValue LowerSDIV_v4i8	(	SDValue	X,
		SDValue	Y,
		const SDLoc &	dl,
		SelectionDAG &	DAG )

static

Definition at line 9548 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, X, and Y.

Referenced by LowerSDIV().

◆ LowerSETCCCARRY()

SDValue LowerSETCCCARRY	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 6810 of file ARMISelLowering.cpp.

References assert(), llvm::cast(), Cond, DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), IntCCToARMCC(), LHS, RHS, and valueToCarryFlag().

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerShift()

SDValue LowerShift	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 6510 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by lowerBuildVectorToBitOp(), llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

◆ LowerTruncate()

SDValue LowerTruncate	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 9167 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::Hi, llvm::Lo, LowerTruncatei1(), llvm::ARMISD::MVETRUNC, N, SDValue(), and llvm::SelectionDAG::SplitVectorOperand().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ LowerTruncatei1()

SDValue LowerTruncatei1	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 9151 of file ARMISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, and llvm::ISD::SETNE.

Referenced by LowerTruncate().

◆ LowerUDIV()

SDValue LowerUDIV	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 9654 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVASTART()

SDValue LowerVASTART	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 4089 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ARMFunctionInfo::getVarArgsFrameIndex().

◆ LowerVecReduce()

SDValue LowerVecReduce	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

◆ LowerVecReduceF()

SDValue LowerVecReduceF	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 10195 of file ARMISelLowering.cpp.

References LowerVecReduce(), and SDValue().

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVecReduceMinMax()

SDValue LowerVecReduceMinMax	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

◆ LowerVECTOR_SHUFFLE()

SDValue LowerVECTOR_SHUFFLE	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 8649 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::isa(), isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTruncMask(), llvm::SDNode::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), llvm::Lo, LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), llvm::ARMISD::MVETRUNC, llvm::PerfectShuffleTable, llvm::ISD::SCALAR_TO_VECTOR, SDValue(), llvm::ISD::SRL, std::swap(), and llvm::V1.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ LowerVECTOR_SHUFFLE_i1()

SDValue LowerVECTOR_SHUFFLE_i1	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 8460 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), isReverseMask(), llvm::SDValue::isUndef(), llvm::ARMCC::NE, PromoteMVEPredVector(), llvm::ISD::SRL, and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerVECTOR_SHUFFLEUsingMovs()

SDValue LowerVECTOR_SHUFFLEUsingMovs	(	SDValue	Op,
		ArrayRef< int >	ShuffleMask,
		SelectionDAG &	DAG )

static

Definition at line 8512 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::Length, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerVECTOR_SHUFFLEUsingOneOff()

SDValue LowerVECTOR_SHUFFLEUsingOneOff	(	SDValue	Op,
		ArrayRef< int >	ShuffleMask,
		SelectionDAG &	DAG )

static

Definition at line 8598 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, SDValue(), and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerVECTOR_SHUFFLEv8i8()

SDValue LowerVECTOR_SHUFFLEv8i8	(	SDValue	Op,
		ArrayRef< int >	ShuffleMask,
		SelectionDAG &	DAG )

static

Definition at line 8371 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getBuildVector(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), I, llvm::SDNode::isUndef(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

◆ LowerVectorExtend()

SDValue LowerVectorExtend	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 9227 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, SDValue(), and llvm::ISD::SIGN_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

◆ LowerVectorFP_TO_INT()

SDValue LowerVectorFP_TO_INT	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 5727 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm_unreachable, llvm::ISD::TRUNCATE, and llvm::SelectionDAG::UnrollVectorOp().

◆ LowerVectorINT_TO_FP()

SDValue LowerVectorINT_TO_FP	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 5823 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm_unreachable, Opc, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), and llvm::ISD::ZERO_EXTEND.

◆ LowerVSETCC()

SDValue LowerVSETCC	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 6630 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::cast(), llvm::EVT::changeVectorElementTypeToInteger(), llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LT, llvm::ARMCC::NE, Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and std::swap().

Referenced by combineSetCC(), and llvm::ARMTargetLowering::LowerOperation().

◆ LowerWRITE_REGISTER()

SDValue LowerWRITE_REGISTER	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 3206 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitScalar(), and llvm::ISD::WRITE_REGISTER.

Referenced by llvm::ARMTargetLowering::LowerOperation().

◆ matchCSET()

SDValue matchCSET	(	unsigned &	Opcode,
		bool &	InvertCond,
		SDValue	TrueVal,
		SDValue	FalseVal,
		const ARMSubtarget *	Subtarget )

static

Definition at line 5244 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), llvm::HasLowerConstantMaterializationCost(), SDValue(), and std::swap().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine().

◆ optimizeLogicalImm()

bool optimizeLogicalImm	(	SDValue	Op,
		unsigned	Imm,
		const APInt &	DemandedBits,
		const ARMSubtarget *	Subtarget,
		TargetLowering::TargetLoweringOpt &	TLO )

static

Refine i32 AND/OR/XOR with a constant RHS using demanded bits: replace the immediate with an equivalent constant that ARM/Thumb can encode as a logical immediate (or that selects better lowering), without changing the computed result on those demanded bits.

Definition at line 20367 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), isLegalLogicalImmediate(), and Opc.

◆ OtherSucc()

MachineBasicBlock * OtherSucc	(	MachineBasicBlock *	MBB,
		MachineBasicBlock *	Succ )

static

Definition at line 11341 of file ARMISelLowering.cpp.

References llvm_unreachable, and MBB.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), and simplifySwitchOfCmpIntrinsic().

◆ overflowFlagToValue()

SDValue overflowFlagToValue	(	SDValue	Flags,
		EVT	VT,
		SelectionDAG &	DAG )

static

Definition at line 4857 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::ARMCC::VS.

◆ ParseBFI()

SDValue ParseBFI	(	SDNode *	N,
		APInt &	ToMask,
		APInt &	FromMask )

static

Definition at line 15003 of file ARMISelLowering.cpp.

References assert(), llvm::APInt::getBitWidth(), llvm::SDNode::getConstantOperandAPInt(), llvm::APInt::getLimitedValue(), llvm::APInt::getLowBitsSet(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::isa(), N, llvm::APInt::popcount(), and llvm::ISD::SRL.

Referenced by FindBFIToCombineWith(), and PerformBFICombine().

◆ PerformADDCombine()

SDValue PerformADDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 14045 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDCombineWithOperands()

SDValue PerformADDCombineWithOperands	(	SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 13557 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), N, and SDValue().

Referenced by PerformADDCombine(), and PerformADDCombine().

◆ PerformAddcSubcCombine()

SDValue PerformAddcSubcCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 13148 of file ARMISelLowering.cpp.

References C(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), LHS, N, RHS, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDECombine()

SDValue PerformADDECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 13540 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, PerformAddeSubeCombine(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformAddeSubeCombine()

SDValue PerformAddeSubeCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 13181 of file ARMISelLowering.cpp.

References AddCombineTo64bitMLAL(), C(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), N, RHS, SDValue(), and llvm::ISD::SMUL_LOHI.

Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformADDVecReduce()

SDValue PerformADDVecReduce	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

◆ PerformANDCombine()

SDValue PerformANDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 14490 of file ARMISelLowering.cpp.

References CombineANDShift(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformSHLSimplify(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformARMBUILD_VECTORCombine()

SDValue PerformARMBUILD_VECTORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.

Definition at line 15456 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformBFICombine()

SDValue PerformBFICombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ PerformBITCASTCombine()

SDValue PerformBITCASTCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST )

static

Definition at line 18825 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::DataLayout::isBigEndian(), N, PerformExtractEltToVMOVRRD(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformBUILD_VECTORCombine()

SDValue PerformBUILD_VECTORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.

Definition at line 15423 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), N, PerformVMOVDRRCombine(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformCMPZCombine()

SDValue PerformCMPZCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 15171 of file ARMISelLowering.cpp.

References C(), Cond, llvm::ARMCC::EQ, IsCMPZCSINC(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformCSETCombine()

SDValue PerformCSETCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 15184 of file ARMISelLowering.cpp.

References C(), Cond, llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMCC::getOppositeCondition(), IsCMPZCSINC(), N, llvm::ARMCC::NE, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformExtendCombine()

SDValue PerformExtendCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.

Definition at line 18076 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), I, llvm::isa(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, N, Opc, PerformSplittingToWideningLoad(), SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformExtractEltCombine()

SDValue PerformExtractEltCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST )

static

◆ PerformExtractEltToVMOVRRD()

SDValue PerformExtractEltToVMOVRRD	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 15669 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::iterator_range< IteratorT >::end(), llvm::ISD::EXTRACT_VECTOR_ELT, F64, llvm::find_if(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::TargetLoweringBase::isTypeLegal(), N, SDValue(), llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SDNode::user_begin(), and llvm::SDNode::users().

Referenced by PerformBITCASTCombine(), and PerformExtractEltCombine().

◆ PerformExtractFpToIntStores()

SDValue PerformExtractFpToIntStores	(	StoreSDNode *	St,
		SelectionDAG &	DAG )

static

◆ PerformFADDCombine()

SDValue PerformFADDCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 17198 of file ARMISelLowering.cpp.

References N, PerformFADDVCMLACombine(), PerformFAddVSelectCombine(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformFADDVCMLACombine()

SDValue PerformFADDVCMLACombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 17167 of file ARMISelLowering.cpp.

References A(), B(), DL, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, N, Opc, RHS, SDValue(), and llvm::SDNode::setFlags().

Referenced by PerformFADDCombine().

◆ PerformFAddVSelectCombine()

SDValue PerformFAddVSelectCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 17124 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::ISD::FADD, llvm::FAdd, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNodeFlags::hasNoSignedZeros(), N, SDValue(), std::swap(), and llvm::ISD::VSELECT.

Referenced by PerformFADDCombine().

◆ PerformFPExtendCombine()

SDValue PerformFPExtendCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 18139 of file ARMISelLowering.cpp.

References N, PerformSplittingToWideningLoad(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformHWLoopCombine()

SDValue PerformHWLoopCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST )

static

◆ PerformInsertEltCombine()

SDValue PerformInsertEltCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.

Definition at line 15640 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformInsertSubvectorCombine()

SDValue PerformInsertSubvectorCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

◆ PerformLOADCombine()

SDValue PerformLOADCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 16717 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformLongShiftCombine()

SDValue PerformLongShiftCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 17646 of file ARMISelLowering.cpp.

References C(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), Merge, N, llvm::SelectionDAG::ReplaceAllUsesWith(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformMinMaxCombine()

SDValue PerformMinMaxCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.

Definition at line 18224 of file ARMISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::ISD::isConstantSplatVector(), N, PerformMinMaxToSatCombine(), PerformVQDMULHCombine(), SDValue(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, std::swap(), and llvm::ISD::UMIN.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformMinMaxToSatCombine()

SDValue PerformMinMaxToSatCombine	(	SDValue	Op,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

◆ PerformMULCombine()

SDValue PerformMULCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ PerformMVEVLDCombine()

SDValue PerformMVEVLDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 16439 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ArrayRef(), llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::Use::getUser(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, MaxSteps, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SDNode::uses(), llvm::ARMISD::VLD2_UPD, and llvm::ARMISD::VLD4_UPD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformMVEVMULLCombine()

SDValue PerformMVEVMULLCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 14227 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isAllOnesConstant(), llvm::ARMSubtarget::isLittle(), llvm::isNullConstant(), N, SDValue(), and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by PerformMULCombine().

◆ performNegCMovCombine()

SDValue performNegCMovCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 14113 of file ARMISelLowering.cpp.

References assert(), DL, getNegationCost(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), N, SDValue(), and llvm::ISD::SUB.

Referenced by PerformSUBCombine().

◆ PerformORCombine()

SDValue PerformORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformORCombine - Target-specific dag combine xforms for ISD::OR.

Definition at line 14831 of file ARMISelLowering.cpp.

References llvm::ISD::AND, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::isNullConstant(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVMOVModifiedImm(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::Other, llvm::OtherModImm, PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToShiftInsert(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), SDValue(), and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformORCombine_i1()

SDValue PerformORCombine_i1	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 14757 of file ARMISelLowering.cpp.

References llvm::ISD::AND, CanInvertMVEVCMP(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNode(), N, and SDValue().

Referenced by PerformORCombine().

◆ PerformORCombineToBFI()

SDValue PerformORCombineToBFI	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ PerformORCombineToShiftInsert()

SDValue PerformORCombineToShiftInsert	(	SelectionDAG &	DAG,
		SDValue	AndOp,
		SDValue	ShiftOp,
		EVT	VT,
		SDLoc	dl )

static

Definition at line 14787 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::isConstOrConstSplat(), Opc, SDValue(), llvm::APInt::trunc(), X, and Y.

Referenced by PerformORCombine().

◆ PerformORCombineToSMULWBT()

SDValue PerformORCombineToSMULWBT	(	SDNode *	OR,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 14540 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), isS16(), isSHL16(), isSRA16(), isSRL16(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SHL, llvm::ISD::SMUL_LOHI, and llvm::ISD::SRL.

Referenced by PerformORCombine().

◆ PerformPREDICATE_CASTCombine()

SDValue PerformPREDICATE_CASTCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 15547 of file ARMISelLowering.cpp.

References C(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isBitwiseNot(), N, SDValue(), llvm::TargetLowering::SimplifyDemandedBits(), X, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformReduceShuffleCombine()

SDValue PerformReduceShuffleCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 17536 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::dyn_cast(), E(), llvm::SelectionDAG::getNode(), llvm::APInt::isAllOnes(), N, SDValue(), and llvm::APInt::setBit().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSELECTCombine()

SDValue PerformSELECTCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ PerformShiftCombine()

SDValue PerformShiftCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST )

static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.

As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 17918 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSHLSimplify()

SDValue PerformSHLSimplify	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	ST )

static

◆ PerformShuffleVMOVNCombine()

SDValue PerformShuffleVMOVNCombine	(	ShuffleVectorSDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 15875 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), isVMOVNTruncMask(), llvm::ARMISD::MVETRUNC, N, and SDValue().

Referenced by PerformVECTOR_SHUFFLECombine().

◆ PerformSignExtendInregCombine()

SDValue PerformSignExtendInregCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 15819 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getNode(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSplittingMVEEXTToWideningLoad()

SDValue PerformSplittingMVEEXTToWideningLoad	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 18967 of file ARMISelLowering.cpp.

References assert(), C(), DL, llvm::dyn_cast(), llvm::ISD::EXTLOAD, llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), llvm::ARMISD::MVESEXT, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SEXTLOAD, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::ARMTargetLowering::PerformMVEExtCombine().

◆ PerformSplittingMVETruncToNarrowingStores()

SDValue PerformSplittingMVETruncToNarrowingStores	(	StoreSDNode *	St,
		SelectionDAG &	DAG )

static

Definition at line 16911 of file ARMISelLowering.cpp.

References C(), DL, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getBaseAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), llvm::ARMISD::MVETRUNC, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::Store, and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

◆ PerformSplittingToNarrowingStores()

SDValue PerformSplittingToNarrowingStores	(	StoreSDNode *	St,
		SelectionDAG &	DAG )

static

Definition at line 16818 of file ARMISelLowering.cpp.

References assert(), C(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getBaseAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), I, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::Store, and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

◆ PerformSplittingToWideningLoad()

SDValue PerformSplittingToWideningLoad	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 17995 of file ARMISelLowering.cpp.

References assert(), C(), llvm::cast(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by PerformExtendCombine(), and PerformFPExtendCombine().

◆ PerformSTORECombine()

SDValue PerformSTORECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 16987 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::cast(), CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlign(), llvm::MemSDNode::getBaseAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDNode::hasOneUse(), isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, PerformExtractFpToIntStores(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), SDValue(), and llvm::Store.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformSUBCombine()

SDValue PerformSUBCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 14140 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, combineSelectAndUse(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroVector(), N, performNegCMovCombine(), PerformSubCSINCCombine(), SDValue(), and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), and llvm::LanaiTargetLowering::PerformDAGCombine().

◆ PerformSubCSINCCombine()

SDValue PerformSubCSINCCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 14068 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, SDValue(), llvm::ISD::SUB, and X.

Referenced by PerformSUBCombine().

◆ PerformTruncatingStoreCombine()

SDValue PerformTruncatingStoreCombine	(	StoreSDNode *	St,
		SelectionDAG &	DAG )

static

Definition at line 16733 of file ARMISelLowering.cpp.

Referenced by PerformSTORECombine().

◆ PerformUMLALCombine()

SDValue PerformUMLALCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 13126 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVCMPCombine()

SDValue PerformVCMPCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 15608 of file ARMISelLowering.cpp.

References Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), getSwappedCondition(), llvm::EVT::isFloatingPoint(), isValidMVECond(), isZeroVector(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVCVTCombine()

SDValue PerformVCVTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 17076 of file ARMISelLowering.cpp.

References C(), llvm::cast(), llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), isSigned(), N, SDValue(), and llvm::ISD::TRUNCATE.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDUPCombine()

SDValue PerformVDUPCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.

Definition at line 16679 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and llvm::ARMISD::VLD1DUP.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVDUPLANECombine()

SDValue PerformVDUPLANECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.

Definition at line 16636 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeVMOVModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::isTypeLegal(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVECREDUCE_ADDCombine()

SDValue PerformVECREDUCE_ADDCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 17274 of file ARMISelLowering.cpp.

References A(), AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::any_of(), assert(), B(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::EVT::is128BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::MUL, Mul, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVECTOR_REG_CASTCombine()

SDValue PerformVECTOR_REG_CASTCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	ST )

static

Definition at line 15580 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVECTOR_SHUFFLECombine()

SDValue PerformVECTOR_SHUFFLECombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.

Definition at line 15900 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, PerformShuffleVMOVNCombine(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVLDCombine()

SDValue PerformVLDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 16431 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), N, and SDValue().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVDRRCombine()

SDValue PerformVMOVDRRCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 15298 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), N, and SDValue().

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVhrCombine()

SDValue PerformVMOVhrCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

◆ PerformVMOVNCombine()

SDValue PerformVMOVNCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 17569 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::isUndef(), N, SDValue(), and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMOVrhCombine()

SDValue PerformVMOVrhCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ PerformVMOVRRDCombine()

SDValue PerformVMOVRRDCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.

Definition at line 15206 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::commonAlignment(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FrameIndex, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::DataLayout::isBigEndian(), llvm::ARMSubtarget::isLittle(), llvm::ISD::isNormalLoad(), N, llvm::Offset, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVMULCombine()

SDValue PerformVMULCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 14196 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, SDValue(), llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

◆ PerformVMulVCTPCombine()

SDValue PerformVMulVCTPCombine	(	SDNode *	N,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

PerformVMulVCTPCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VMUL when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 0.125, float 0.125>): vcvt.f32.s32 d16, d16 vmul.f32 d16, d16, d17 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 17216 of file ARMISelLowering.cpp.

References C(), llvm::APFloat::convertToInteger(), DL, llvm::SelectionDAG::getConstant(), llvm::APFloat::getExactInverse(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ConstantFPSDNode::getValueAPF(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::isConstOrConstSplatFP(), isSigned(), N, llvm::APFloatBase::opOK, llvm::APFloatBase::rmTowardZero, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVQDMULHCombine() [1/2]

SDValue PerformVQDMULHCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 13320 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::cast(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::isConstOrConstSplat(), llvm::EVT::isPow2VectorType(), llvm::EVT::isVector(), llvm::ISD::MUL, Mul, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::TRUNCATE, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), PerformMinMaxCombine(), and PerformVSELECTCombine().

◆ PerformVQDMULHCombine() [2/2]

SDValue PerformVQDMULHCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 17625 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), LHS, N, RHS, and SDValue().

◆ PerformVQMOVNCombine()

SDValue PerformVQMOVNCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 17609 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), N, SDValue(), and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVSELECTCombine()

SDValue PerformVSELECTCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

Definition at line 13428 of file ARMISelLowering.cpp.

References C(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::isa(), llvm::isConstOrConstSplat(), LHS, N, PerformVQDMULHCombine(), RHS, SDValue(), llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

◆ PerformVSetCCToVCTPCombine()

SDValue PerformVSetCCToVCTPCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ PerformXORCombine()

SDValue PerformXORCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const ARMSubtarget *	Subtarget )

static

◆ PromoteMVEPredVector()

SDValue PromoteMVEPredVector	(	SDLoc	dl,
		SDValue	Pred,
		EVT	VT,
		SelectionDAG &	DAG )

static

Definition at line 8425 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::ISD::BITCAST, llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), getVectorTyFromPredicateVector(), and llvm::ISD::VSELECT.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), and LowerVECTOR_SHUFFLE_i1().

◆ promoteToConstantPool()

SDValue promoteToConstantPool	(	const ARMTargetLowering *	TLI,
		const GlobalValue *	GV,
		SelectionDAG &	DAG,
		EVT	PtrVT,
		const SDLoc &	dl )

static

Definition at line 3566 of file ARMISelLowering.cpp.

References allUsersAreInFunction(), llvm::StringRef::bytes_begin(), llvm::StringRef::bytes_end(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, llvm::ARMConstantPoolConstant::Create(), llvm::dyn_cast(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F, llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlign(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, SDValue(), llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), Size, and llvm::StringRef::size().

◆ ReplaceCMP_SWAP_64Results()

void ReplaceCMP_SWAP_64Results	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG )

static

◆ ReplaceLongIntrinsic()

void ReplaceLongIntrinsic	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG )

static

Definition at line 10707 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::Lo, N, Opc, Results, and llvm::SelectionDAG::SplitScalar().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ ReplaceREADCYCLECOUNTER()

void ReplaceREADCYCLECOUNTER	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG,
		const ARMSubtarget *	Subtarget )

static

Definition at line 10286 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, N, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

◆ SearchLoopIntrinsic()

SDValue SearchLoopIntrinsic	(	SDValue	N,
		ISD::CondCode &	CC,
		int &	Imm,
		bool &	Negate )

static

Definition at line 18433 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::dyn_cast(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), N, SDValue(), SearchLoopIntrinsic(), llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by PerformHWLoopCombine(), and SearchLoopIntrinsic().

◆ SelectPairHalf()

unsigned SelectPairHalf	(	unsigned	Elements,
		ArrayRef< int >	Mask,
		unsigned	Index )

static

Definition at line 7160 of file ARMISelLowering.cpp.

Referenced by isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().

◆ SkipExtensionForVMULL()

SDValue SkipExtensionForVMULL	(	SDNode *	N,
		SelectionDAG &	DAG )

static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 9401 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by LowerMUL().

◆ SkipLoadExtensionForVMULL()

SDValue SkipLoadExtensionForVMULL	(	LoadSDNode *	LD,
		SelectionDAG &	DAG )

static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 9377 of file ARMISelLowering.cpp.

References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), and llvm::SelectionDAG::getLoad().

Referenced by SkipExtensionForVMULL().

◆ STATISTIC() [1/5]

STATISTIC	(	NumConstpoolPromoted	,
		"Number of constants with their storage promoted into constant pools"	)

◆ STATISTIC() [2/5]

STATISTIC	(	NumLoopByVals	,
		"Number of loops generated for byval arguments"	)

◆ STATISTIC() [3/5]

STATISTIC	(	NumMovwMovt	,
		"Number of GAs materialized with movw + movt"	)

◆ STATISTIC() [4/5]

STATISTIC	(	NumOptimizedImms	,
		"Number of times immediates were optimized"	)

◆ STATISTIC() [5/5]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

◆ TryCombineBaseUpdate()

bool TryCombineBaseUpdate	(	struct BaseUpdateTarget &	Target,
		struct BaseUpdateUser &	User,
		bool	SimpleConstIncOnly,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 15987 of file ARMISelLowering.cpp.

Referenced by CombineBaseUpdate().

◆ TryDistrubutionADDVecReduce()

SDValue TryDistrubutionADDVecReduce	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 13578 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::BaseIndexOffset::match(), llvm::ISD::MUL, N, SDValue(), llvm::ISD::VECREDUCE_ADD, and X.

Referenced by PerformADDVecReduce().

◆ valueToCarryFlag()

SDValue valueToCarryFlag	(	SDValue	Value,
		SelectionDAG &	DAG,
		bool	Invert )

static

Definition at line 4824 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::ISD::SUB.

◆ WinDBZCheckDenominator()

SDValue WinDBZCheckDenominator	(	SelectionDAG &	DAG,
		SDNode *	N,
		SDValue	InChain )

static

Definition at line 9842 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, N, llvm::ISD::OR, and llvm::SelectionDAG::SplitScalar().

Variable Documentation

◆ ARMInterworking

cl::opt< bool > ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))	(	"arm-interworking"	,
		cl::Hidden	,
		cl::desc("Enable / disable ARM interworking (for debugging only)")	,
		cl::init(true)	)

static

◆ ArmMaxBaseUpdatesToCheck

cl::opt< unsigned > ArmMaxBaseUpdatesToCheck("arm-max-base-updates-to-check", cl::Hidden, cl::desc("Maximum number of base-updates to check generating postindex."), cl::init(64))	(	"arm-max-base-updates-to-check"	,
		cl::Hidden	,
		cl::desc("Maximum number of base-updates to check generating postindex.")	,
		cl::init(64)	)

Referenced by CombineBaseUpdate().

◆ ConstpoolPromotionMaxSize

cl::opt< unsigned > ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))	(	"arm-promote-constant-max-size"	,
		cl::Hidden	,
		cl::desc("Maximum size of constant to promote into a constant pool")	,
		cl::init(64)	)

static

Referenced by promoteToConstantPool().

◆ ConstpoolPromotionMaxTotal

cl::opt< unsigned > ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))	(	"arm-promote-constant-max-total"	,
		cl::Hidden	,
		cl::desc("Maximum size of ALL constants to promote into a constant pool")	,
		cl::init(128)	)

static

Referenced by promoteToConstantPool().

◆ EnableConstpoolPromotion

cl::opt< bool > EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))	(	"arm-promote-constant"	,
		cl::Hidden	,
		cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools")	,
		cl::init(false)	)

static

Referenced by promoteToConstantPool().

◆ FlagsVT

MVT FlagsVT = MVT::i32

constexpr

Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).

Definition at line 157 of file ARMISelLowering.cpp.

◆ GPRArgRegs

const MCPhysReg GPRArgRegs[]

static

Initial value:

= {
  ARM::R0, ARM::R1, ARM::R2, ARM::R3
}

Definition at line 160 of file ARMISelLowering.cpp.

◆ MVEMaxSupportedInterleaveFactor

cl::opt< unsigned > MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))	(	"mve-max-interleave-factor"	,
		cl::Hidden	,
		cl::desc("Maximum interleave factor for MVE VLDn to generate.")	,
		cl::init(2)	)

Referenced by canTailPredicateLoop(), and llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().

Classes

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Typedef Documentation

◆ RCPair

Enumeration Type Documentation

◆ HABaseType

◆ ShuffleOpCodes

Function Documentation

◆ AddCombineBUILD_VECTORToVPADDL()

◆ AddCombineTo64bitMLAL()

◆ AddCombineTo64BitSMLAL16()

◆ AddCombineTo64bitUMAAL()

◆ AddCombineToVPADD()

◆ AddCombineVUZPToVPADDL()

◆ AddRequiredExtensionForVMULL()

◆ allUsersAreInFunction()

◆ attachMEMCPYScratchRegs()

◆ bitcastf32Toi32()

◆ BitsProperlyConcatenate()

◆ canChangeToInt()

◆ canGuaranteeTCO()

◆ CanInvertMVEVCMP()

◆ carryFlagToValue()

◆ checkAndUpdateCPSRKill()

◆ checkVSELConstraints()

◆ CombineANDShift()

◆ CombineBaseUpdate()

◆ combineSelectAndUse()

◆ combineSelectAndUseCommutative()

◆ CombineVLDDUP()

◆ CombineVMOVDRRCandidateWithVecOp()

◆ createGPRPairNode2xi32()

◆ createGPRPairNodei64()

◆ emitPostLd()

◆ emitPostSt()

◆ Expand64BitShift()

◆ expandf64Toi32()

◆ ExpandREAD_REGISTER()

◆ FindBFIToCombineWith()

◆ findMUL_LOHI()

◆ findPointerConstIncrement()

◆ FPCCToARMCC()

◆ GeneratePerfectShuffle()

◆ genTPEntry()

◆ genTPLoopBody()

◆ getARMIndexedAddressParts()

◆ getCmpOperandFoldingProfit()

◆ getDivRemArgList()

◆ getDivRemLibcall()

◆ getExtensionTo64Bits()

◆ getInvertedARMCondCode()

◆ getLdOpcode()

◆ getMVEIndexedAddressParts()

◆ getNegationCost()

◆ getPointerConstIncrement()

◆ getStOpcode()

◆ getT2IndexedAddressParts()

◆ getVCMPCondCode()

◆ getVectorTyFromPredicateVector()

◆ getVShiftImm()

◆ getZeroVector()

◆ handleCMSEValue()

◆ hasNormalLoadOperand()

◆ IntCCToARMCC()

◆ isAddSubSExt()

◆ isAddSubZExt()

◆ isCMN()

◆ IsCMPZCSINC()

◆ isConditionalZeroOrAllOnes()

◆ isExtendedBUILD_VECTOR()

◆ isFloatingPointZero()

◆ isGTorGE()

◆ isHomogeneousAggregate()

◆ isIncompatibleReg()