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M68kISelLowering.cpp
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1 //===-- M68kISelLowering.cpp - M68k DAG Lowering Impl ------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that M68k uses to lower LLVM code into a
11 /// selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "M68kISelLowering.h"
16 #include "M68kCallingConv.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kSubtarget.h"
19 #include "M68kTargetMachine.h"
20 #include "M68kTargetObjectFile.h"
21 
22 #include "llvm/ADT/Statistic.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/KnownBits.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "M68k-isel"
43 
44 STATISTIC(NumTailCalls, "Number of tail calls");
45 
47  const M68kSubtarget &STI)
48  : TargetLowering(TM), Subtarget(STI), TM(TM) {
49 
50  MVT PtrVT = MVT::i32;
51 
53 
54  auto *RegInfo = Subtarget.getRegisterInfo();
55  setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
56 
57  // Set up the register classes.
58  addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59  addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60  addRegisterClass(MVT::i32, &M68k::XR32RegClass);
61 
62  for (auto VT : MVT::integer_valuetypes()) {
66  }
67 
68  // We don't accept any truncstore of integer registers.
75 
78  if (Subtarget.atLeastM68020())
80  else
83 
84  for (auto OP :
90  }
91 
92  for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
95  }
96 
97  // FIXME It would be better to use a custom lowering
98  for (auto OP : {ISD::SMULO, ISD::UMULO}) {
102  }
103 
104  // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
105  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
110  }
111 
112  // SADDO and friends are legal with this setup, i hope
113  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
118  }
119 
122 
123  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
129  }
130 
131  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
136  }
137 
144 
149 
152 
154 
156 
157  // 2^2 bytes
158  // FIXME can it be just 2^1?
159  setMinFunctionAlignment(Align::Constant<2>());
160 }
161 
163  LLVMContext &Context, EVT VT) const {
164  // M68k SETcc producess either 0x00 or 0xFF
165  return MVT::i8;
166 }
167 
169  EVT Ty) const {
170  if (Ty.isSimple()) {
171  return Ty.getSimpleVT();
172  }
173  return MVT::getIntegerVT(8 * DL.getPointerSize(0));
174 }
175 
176 #include "M68kGenCallingConv.inc"
177 
179 
180 static StructReturnType
182  if (Outs.empty())
183  return NotStructReturn;
184 
185  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
186  if (!Flags.isSRet())
187  return NotStructReturn;
188  if (Flags.isInReg())
189  return RegStructReturn;
190  return StackStructReturn;
191 }
192 
193 /// Determines whether a function uses struct return semantics.
194 static StructReturnType
196  if (Ins.empty())
197  return NotStructReturn;
198 
199  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
200  if (!Flags.isSRet())
201  return NotStructReturn;
202  if (Flags.isInReg())
203  return RegStructReturn;
204  return StackStructReturn;
205 }
206 
207 /// Make a copy of an aggregate at address specified by "Src" to address
208 /// "Dst" with size and alignment information specified by the specific
209 /// parameter attribute. The copy will be passed as a byval function parameter.
211  SDValue Chain, ISD::ArgFlagsTy Flags,
212  SelectionDAG &DAG, const SDLoc &DL) {
213  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
214 
215  return DAG.getMemcpy(
216  Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
217  /*isVolatile=*/false, /*AlwaysInline=*/true,
218  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
219 }
220 
221 /// Return true if the calling convention is one that we can guarantee TCO for.
222 static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
223 
224 /// Return true if we might ever do TCO for calls with this calling convention.
226  switch (CC) {
227  // C calling conventions:
228  case CallingConv::C:
229  return true;
230  default:
231  return canGuaranteeTCO(CC);
232  }
233 }
234 
235 /// Return true if the function is being made into a tailcall target by
236 /// changing its ABI.
237 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
238  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
239 }
240 
241 /// Return true if the given stack call argument is already available in the
242 /// same position (relatively) of the caller's incoming argument stack.
243 static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
244  ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI,
245  const MachineRegisterInfo *MRI,
246  const M68kInstrInfo *TII,
247  const CCValAssign &VA) {
248  unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
249 
250  for (;;) {
251  // Look through nodes that don't alter the bits of the incoming value.
252  unsigned Op = Arg.getOpcode();
253  if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
254  Arg = Arg.getOperand(0);
255  continue;
256  }
257  if (Op == ISD::TRUNCATE) {
258  const SDValue &TruncInput = Arg.getOperand(0);
259  if (TruncInput.getOpcode() == ISD::AssertZext &&
260  cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
261  Arg.getValueType()) {
262  Arg = TruncInput.getOperand(0);
263  continue;
264  }
265  }
266  break;
267  }
268 
269  int FI = INT_MAX;
270  if (Arg.getOpcode() == ISD::CopyFromReg) {
271  unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
273  return false;
274  MachineInstr *Def = MRI->getVRegDef(VR);
275  if (!Def)
276  return false;
277  if (!Flags.isByVal()) {
278  if (!TII->isLoadFromStackSlot(*Def, FI))
279  return false;
280  } else {
281  unsigned Opcode = Def->getOpcode();
282  if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
283  Def->getOperand(1).isFI()) {
284  FI = Def->getOperand(1).getIndex();
285  Bytes = Flags.getByValSize();
286  } else
287  return false;
288  }
289  } else if (auto *Ld = dyn_cast<LoadSDNode>(Arg)) {
290  if (Flags.isByVal())
291  // ByVal argument is passed in as a pointer but it's now being
292  // dereferenced. e.g.
293  // define @foo(%struct.X* %A) {
294  // tail call @bar(%struct.X* byval %A)
295  // }
296  return false;
297  SDValue Ptr = Ld->getBasePtr();
298  FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
299  if (!FINode)
300  return false;
301  FI = FINode->getIndex();
302  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
303  FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
304  FI = FINode->getIndex();
305  Bytes = Flags.getByValSize();
306  } else
307  return false;
308 
309  assert(FI != INT_MAX);
310  if (!MFI.isFixedObjectIndex(FI))
311  return false;
312 
313  if (Offset != MFI.getObjectOffset(FI))
314  return false;
315 
316  if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
317  // If the argument location is wider than the argument type, check that any
318  // extension flags match.
319  if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
320  Flags.isSExt() != MFI.isObjectSExt(FI)) {
321  return false;
322  }
323  }
324 
325  return Bytes == MFI.getObjectSize(FI);
326 }
327 
328 SDValue
329 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
332  int ReturnAddrIndex = FuncInfo->getRAIndex();
333 
334  if (ReturnAddrIndex == 0) {
335  // Set up a frame object for the return address.
336  unsigned SlotSize = Subtarget.getSlotSize();
337  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(
338  SlotSize, -(int64_t)SlotSize, false);
339  FuncInfo->setRAIndex(ReturnAddrIndex);
340  }
341 
342  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
343 }
344 
345 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
346  SDValue &OutRetAddr,
347  SDValue Chain,
348  bool IsTailCall, int FPDiff,
349  const SDLoc &DL) const {
350  EVT VT = getPointerTy(DAG.getDataLayout());
351  OutRetAddr = getReturnAddressFrameIndex(DAG);
352 
353  // Load the "old" Return address.
354  OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo());
355  return SDValue(OutRetAddr.getNode(), 1);
356 }
357 
358 SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
359  SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI,
360  EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const {
361  if (!FPDiff)
362  return Chain;
363 
364  // Calculate the new stack slot for the return address.
365  int NewFO = MF.getFrameInfo().CreateFixedObject(
366  SlotSize, (int64_t)FPDiff - SlotSize, false);
367 
368  SDValue NewFI = DAG.getFrameIndex(NewFO, PtrVT);
369  // Store the return address to the appropriate stack slot.
370  Chain = DAG.getStore(
371  Chain, DL, RetFI, NewFI,
373  return Chain;
374 }
375 
376 SDValue
377 M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
379  const SDLoc &DL, SelectionDAG &DAG,
380  const CCValAssign &VA,
381  MachineFrameInfo &MFI,
382  unsigned ArgIdx) const {
383  // Create the nodes corresponding to a load from this parameter slot.
384  ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
385  EVT ValVT;
386 
387  // If value is passed by pointer we have address passed instead of the value
388  // itself.
389  if (VA.getLocInfo() == CCValAssign::Indirect)
390  ValVT = VA.getLocVT();
391  else
392  ValVT = VA.getValVT();
393 
394  // Because we are dealing with BE architecture we need to offset loading of
395  // partial types
396  int Offset = VA.getLocMemOffset();
397  if (VA.getValVT() == MVT::i8) {
398  Offset += 3;
399  } else if (VA.getValVT() == MVT::i16) {
400  Offset += 2;
401  }
402 
403  // TODO Interrupt handlers
404  // Calculate SP offset of interrupt parameter, re-arrange the slot normally
405  // taken by a return address.
406 
407  // FIXME For now, all byval parameter objects are marked mutable. This can
408  // be changed with more analysis. In case of tail call optimization mark all
409  // arguments mutable. Since they could be overwritten by lowering of arguments
410  // in case of a tail call.
411  bool AlwaysUseMutable = shouldGuaranteeTCO(
412  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
413  bool IsImmutable = !AlwaysUseMutable && !Flags.isByVal();
414 
415  if (Flags.isByVal()) {
416  unsigned Bytes = Flags.getByValSize();
417  if (Bytes == 0)
418  Bytes = 1; // Don't create zero-sized stack objects.
419  int FI = MFI.CreateFixedObject(Bytes, Offset, IsImmutable);
420  // TODO Interrupt handlers
421  // Adjust SP offset of interrupt parameter.
422  return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
423  } else {
424  int FI =
425  MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, Offset, IsImmutable);
426 
427  // Set SExt or ZExt flag.
428  if (VA.getLocInfo() == CCValAssign::ZExt) {
429  MFI.setObjectZExt(FI, true);
430  } else if (VA.getLocInfo() == CCValAssign::SExt) {
431  MFI.setObjectSExt(FI, true);
432  }
433 
434  // TODO Interrupt handlers
435  // Adjust SP offset of interrupt parameter.
436 
437  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
438  SDValue Val = DAG.getLoad(
439  ValVT, DL, Chain, FIN,
441  return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val)
442  : Val;
443  }
444 }
445 
446 SDValue M68kTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
447  SDValue Arg, const SDLoc &DL,
448  SelectionDAG &DAG,
449  const CCValAssign &VA,
450  ISD::ArgFlagsTy Flags) const {
451  unsigned LocMemOffset = VA.getLocMemOffset();
452  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
453  PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
454  StackPtr, PtrOff);
455  if (Flags.isByVal())
456  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL);
457 
458  return DAG.getStore(
459  Chain, DL, Arg, PtrOff,
460  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
461 }
462 
463 //===----------------------------------------------------------------------===//
464 // Call
465 //===----------------------------------------------------------------------===//
466 
467 SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
468  SmallVectorImpl<SDValue> &InVals) const {
469  SelectionDAG &DAG = CLI.DAG;
470  SDLoc &DL = CLI.DL;
472  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
474  SDValue Chain = CLI.Chain;
475  SDValue Callee = CLI.Callee;
476  CallingConv::ID CallConv = CLI.CallConv;
477  bool &IsTailCall = CLI.IsTailCall;
478  bool IsVarArg = CLI.IsVarArg;
479 
482  bool IsSibcall = false;
484  // const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
485 
486  if (CallConv == CallingConv::M68k_INTR)
487  report_fatal_error("M68k interrupts may not be called directly");
488 
489  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
490  if (Attr.getValueAsBool())
491  IsTailCall = false;
492 
493  // FIXME Add tailcalls support
494 
495  bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
496  if (IsMustTail) {
497  // Force this to be a tail call. The verifier rules are enough to ensure
498  // that we can lower this successfully without moving the return address
499  // around.
500  IsTailCall = true;
501  } else if (IsTailCall) {
502  // Check if it's really possible to do a tail call.
503  IsTailCall = IsEligibleForTailCallOptimization(
504  Callee, CallConv, IsVarArg, SR != NotStructReturn,
505  MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
506  DAG);
507 
508  // Sibcalls are automatically detected tailcalls which do not require
509  // ABI changes.
510  if (!MF.getTarget().Options.GuaranteedTailCallOpt && IsTailCall)
511  IsSibcall = true;
512 
513  if (IsTailCall)
514  ++NumTailCalls;
515  }
516 
517  assert(!(IsVarArg && canGuaranteeTCO(CallConv)) &&
518  "Var args not supported with calling convention fastcc");
519 
520  // Analyze operands of the call, assigning locations to each operand.
522  SmallVector<Type *, 4> ArgTypes;
523  for (const auto &Arg : CLI.getArgs())
524  ArgTypes.emplace_back(Arg.Ty);
525  M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
526  *DAG.getContext());
527  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
528 
529  // Get a count of how many bytes are to be pushed on the stack.
530  unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
531  if (IsSibcall) {
532  // This is a sibcall. The memory operands are available in caller's
533  // own caller's stack.
534  NumBytes = 0;
535  } else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
536  canGuaranteeTCO(CallConv)) {
537  NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
538  }
539 
540  int FPDiff = 0;
541  if (IsTailCall && !IsSibcall && !IsMustTail) {
542  // Lower arguments at fp - stackoffset + fpdiff.
543  unsigned NumBytesCallerPushed = MFI->getBytesToPopOnReturn();
544 
545  FPDiff = NumBytesCallerPushed - NumBytes;
546 
547  // Set the delta of movement of the returnaddr stackslot.
548  // But only set if delta is greater than previous delta.
549  if (FPDiff < MFI->getTCReturnAddrDelta())
550  MFI->setTCReturnAddrDelta(FPDiff);
551  }
552 
553  unsigned NumBytesToPush = NumBytes;
554  unsigned NumBytesToPop = NumBytes;
555 
556  // If we have an inalloca argument, all stack space has already been allocated
557  // for us and be right at the top of the stack. We don't support multiple
558  // arguments passed in memory when using inalloca.
559  if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
560  NumBytesToPush = 0;
561  if (!ArgLocs.back().isMemLoc())
562  report_fatal_error("cannot use inalloca attribute on a register "
563  "parameter");
564  if (ArgLocs.back().getLocMemOffset() != 0)
565  report_fatal_error("any parameter with the inalloca attribute must be "
566  "the only memory argument");
567  }
568 
569  if (!IsSibcall)
570  Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
571  NumBytes - NumBytesToPush, DL);
572 
573  SDValue RetFI;
574  // Load return address for tail calls.
575  if (IsTailCall && FPDiff)
576  Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
577 
579  SmallVector<SDValue, 8> MemOpChains;
581 
582  // Walk the register/memloc assignments, inserting copies/loads. In the case
583  // of tail call optimization arguments are handle later.
584  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
585  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
586  ISD::ArgFlagsTy Flags = Outs[i].Flags;
587 
588  // Skip inalloca arguments, they have already been written.
589  if (Flags.isInAlloca())
590  continue;
591 
592  CCValAssign &VA = ArgLocs[i];
593  EVT RegVT = VA.getLocVT();
594  SDValue Arg = OutVals[i];
595  bool IsByVal = Flags.isByVal();
596 
597  // Promote the value if needed.
598  switch (VA.getLocInfo()) {
599  default:
600  llvm_unreachable("Unknown loc info!");
601  case CCValAssign::Full:
602  break;
603  case CCValAssign::SExt:
604  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
605  break;
606  case CCValAssign::ZExt:
607  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
608  break;
609  case CCValAssign::AExt:
610  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
611  break;
612  case CCValAssign::BCvt:
613  Arg = DAG.getBitcast(RegVT, Arg);
614  break;
615  case CCValAssign::Indirect: {
616  // Store the argument.
617  SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
618  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
619  Chain = DAG.getStore(
620  Chain, DL, Arg, SpillSlot,
622  Arg = SpillSlot;
623  break;
624  }
625  }
626 
627  if (VA.isRegLoc()) {
628  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
629  } else if (!IsSibcall && (!IsTailCall || IsByVal)) {
630  assert(VA.isMemLoc());
631  if (!StackPtr.getNode()) {
632  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
633  getPointerTy(DAG.getDataLayout()));
634  }
635  MemOpChains.push_back(
636  LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
637  }
638  }
639 
640  if (!MemOpChains.empty())
641  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
642 
643  // FIXME Make sure PIC style GOT works as expected
644  // The only time GOT is really needed is for Medium-PIC static data
645  // otherwise we are happy with pc-rel or static references
646 
647  if (IsVarArg && IsMustTail) {
648  const auto &Forwards = MFI->getForwardedMustTailRegParms();
649  for (const auto &F : Forwards) {
650  SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
651  RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
652  }
653  }
654 
655  // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
656  // don't need this because the eligibility check rejects calls that require
657  // shuffling arguments passed in memory.
658  if (!IsSibcall && IsTailCall) {
659  // Force all the incoming stack arguments to be loaded from the stack
660  // before any new outgoing arguments are stored to the stack, because the
661  // outgoing stack slots may alias the incoming argument stack slots, and
662  // the alias isn't otherwise explicit. This is slightly more conservative
663  // than necessary, because it means that each store effectively depends
664  // on every argument instead of just those arguments it would clobber.
665  SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
666 
667  SmallVector<SDValue, 8> MemOpChains2;
668  SDValue FIN;
669  int FI = 0;
670  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
671  CCValAssign &VA = ArgLocs[i];
672  if (VA.isRegLoc())
673  continue;
674  assert(VA.isMemLoc());
675  SDValue Arg = OutVals[i];
676  ISD::ArgFlagsTy Flags = Outs[i].Flags;
677  // Skip inalloca arguments. They don't require any work.
678  if (Flags.isInAlloca())
679  continue;
680  // Create frame index.
681  int32_t Offset = VA.getLocMemOffset() + FPDiff;
682  uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
683  FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
684  FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
685 
686  if (Flags.isByVal()) {
687  // Copy relative to framepointer.
689  if (!StackPtr.getNode()) {
690  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
691  getPointerTy(DAG.getDataLayout()));
692  }
694  StackPtr, Source);
695 
696  MemOpChains2.push_back(
697  CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL));
698  } else {
699  // Store relative to framepointer.
700  MemOpChains2.push_back(DAG.getStore(
701  ArgChain, DL, Arg, FIN,
703  }
704  }
705 
706  if (!MemOpChains2.empty())
707  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2);
708 
709  // Store the return address to the appropriate stack slot.
710  Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
712  Subtarget.getSlotSize(), FPDiff, DL);
713  }
714 
715  // Build a sequence of copy-to-reg nodes chained together with token chain
716  // and flag operands which copy the outgoing args into registers.
717  SDValue InFlag;
718  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
719  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
720  RegsToPass[i].second, InFlag);
721  InFlag = Chain.getValue(1);
722  }
723 
724  if (Callee->getOpcode() == ISD::GlobalAddress) {
725  // If the callee is a GlobalAddress node (quite common, every direct call
726  // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
727  // it.
728  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
729 
730  // We should use extra load for direct calls to dllimported functions in
731  // non-JIT mode.
732  const GlobalValue *GV = G->getGlobal();
733  if (!GV->hasDLLImportStorageClass()) {
734  unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
735 
737  GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
738 
739  if (OpFlags == M68kII::MO_GOTPCREL) {
740 
741  // Add a wrapper.
743  getPointerTy(DAG.getDataLayout()), Callee);
744 
745  // Add extra indirection
746  Callee = DAG.getLoad(
747  getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee,
749  }
750  }
751  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
753  unsigned char OpFlags =
754  Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
755 
757  S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
758  }
759 
760  // Returns a chain & a flag for retval copy to use.
761  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
763 
764  if (!IsSibcall && IsTailCall) {
765  Chain = DAG.getCALLSEQ_END(Chain,
766  DAG.getIntPtrConstant(NumBytesToPop, DL, true),
767  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
768  InFlag = Chain.getValue(1);
769  }
770 
771  Ops.push_back(Chain);
772  Ops.push_back(Callee);
773 
774  if (IsTailCall)
775  Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32));
776 
777  // Add argument registers to the end of the list so that they are known live
778  // into the call.
779  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
780  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
781  RegsToPass[i].second.getValueType()));
782 
783  // Add a register mask operand representing the call-preserved registers.
784  const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
785  assert(Mask && "Missing call preserved mask for calling convention");
786 
787  Ops.push_back(DAG.getRegisterMask(Mask));
788 
789  if (InFlag.getNode())
790  Ops.push_back(InFlag);
791 
792  if (IsTailCall) {
794  return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops);
795  }
796 
797  Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops);
798  InFlag = Chain.getValue(1);
799 
800  // Create the CALLSEQ_END node.
801  unsigned NumBytesForCalleeToPop;
802  if (M68k::isCalleePop(CallConv, IsVarArg,
804  NumBytesForCalleeToPop = NumBytes; // Callee pops everything
805  } else if (!canGuaranteeTCO(CallConv) && SR == StackStructReturn) {
806  // If this is a call to a struct-return function, the callee
807  // pops the hidden struct pointer, so we have to push it back.
808  NumBytesForCalleeToPop = 4;
809  } else {
810  NumBytesForCalleeToPop = 0; // Callee pops nothing.
811  }
812 
813  if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
814  // No need to reset the stack after the call if the call doesn't return. To
815  // make the MI verify, we'll pretend the callee does it for us.
816  NumBytesForCalleeToPop = NumBytes;
817  }
818 
819  // Returns a flag for retval copy to use.
820  if (!IsSibcall) {
821  Chain = DAG.getCALLSEQ_END(
822  Chain, DAG.getIntPtrConstant(NumBytesToPop, DL, true),
823  DAG.getIntPtrConstant(NumBytesForCalleeToPop, DL, true), InFlag, DL);
824  InFlag = Chain.getValue(1);
825  }
826 
827  // Handle result values, copying them out of physregs into vregs that we
828  // return.
829  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
830  InVals);
831 }
832 
833 SDValue M68kTargetLowering::LowerCallResult(
834  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
836  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
837 
838  // Assign locations to each value returned by this call.
840  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
841  *DAG.getContext());
842  CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
843 
844  // Copy all of the result registers out of their specified physreg.
845  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
846  CCValAssign &VA = RVLocs[i];
847  EVT CopyVT = VA.getLocVT();
848 
849  /// ??? is this correct?
850  Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag)
851  .getValue(1);
852  SDValue Val = Chain.getValue(0);
853 
854  if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
855  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
856 
857  InFlag = Chain.getValue(2);
858  InVals.push_back(Val);
859  }
860 
861  return Chain;
862 }
863 
864 //===----------------------------------------------------------------------===//
865 // Formal Arguments Calling Convention Implementation
866 //===----------------------------------------------------------------------===//
867 
868 SDValue M68kTargetLowering::LowerFormalArguments(
869  SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
871  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
874  // const TargetFrameLowering &TFL = *Subtarget.getFrameLowering();
875 
876  MachineFrameInfo &MFI = MF.getFrameInfo();
877 
878  // Assign locations to all of the incoming arguments.
880  SmallVector<Type *, 4> ArgTypes;
881  for (const Argument &Arg : MF.getFunction().args())
882  ArgTypes.emplace_back(Arg.getType());
883  M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext());
884 
885  CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
886 
887  unsigned LastVal = ~0U;
888  SDValue ArgValue;
889  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
890  CCValAssign &VA = ArgLocs[i];
891  assert(VA.getValNo() != LastVal && "Same value in different locations");
892 
893  LastVal = VA.getValNo();
894 
895  if (VA.isRegLoc()) {
896  EVT RegVT = VA.getLocVT();
897  const TargetRegisterClass *RC;
898  if (RegVT == MVT::i32)
899  RC = &M68k::XR32RegClass;
900  else
901  llvm_unreachable("Unknown argument type!");
902 
903  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
904  ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
905 
906  // If this is an 8 or 16-bit value, it is really passed promoted to 32
907  // bits. Insert an assert[sz]ext to capture this, then truncate to the
908  // right size.
909  if (VA.getLocInfo() == CCValAssign::SExt) {
910  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
911  DAG.getValueType(VA.getValVT()));
912  } else if (VA.getLocInfo() == CCValAssign::ZExt) {
913  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
914  DAG.getValueType(VA.getValVT()));
915  } else if (VA.getLocInfo() == CCValAssign::BCvt) {
916  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
917  }
918 
919  if (VA.isExtInLoc()) {
920  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
921  }
922  } else {
923  assert(VA.isMemLoc());
924  ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i);
925  }
926 
927  // If value is passed via pointer - do a load.
928  // TODO Make sure this handling on indirect arguments is correct
929  if (VA.getLocInfo() == CCValAssign::Indirect)
930  ArgValue =
931  DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo());
932 
933  InVals.push_back(ArgValue);
934  }
935 
936  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
937  // Swift calling convention does not require we copy the sret argument
938  // into %D0 for the return. We don't set SRetReturnReg for Swift.
939  if (CCID == CallingConv::Swift)
940  continue;
941 
942  // ABI require that for returning structs by value we copy the sret argument
943  // into %D0 for the return. Save the argument into a virtual register so
944  // that we can access it from the return points.
945  if (Ins[i].Flags.isSRet()) {
946  unsigned Reg = MMFI->getSRetReturnReg();
947  if (!Reg) {
948  MVT PtrTy = getPointerTy(DAG.getDataLayout());
950  MMFI->setSRetReturnReg(Reg);
951  }
952  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
953  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
954  break;
955  }
956  }
957 
958  unsigned StackSize = CCInfo.getNextStackOffset();
959  // Align stack specially for tail calls.
961  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
962 
963  // If the function takes variable number of arguments, make a frame index for
964  // the start of the first vararg value... for expansion of llvm.va_start. We
965  // can skip this if there are no va_start calls.
966  if (MFI.hasVAStart()) {
967  MMFI->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
968  }
969 
970  if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
971  // We forward some GPRs and some vector types.
972  SmallVector<MVT, 2> RegParmTypes;
973  MVT IntVT = MVT::i32;
974  RegParmTypes.push_back(IntVT);
975 
976  // Compute the set of forwarded registers. The rest are scratch.
977  // ??? what is this for?
980  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
981 
982  // Copy all forwards from physical to virtual registers.
983  for (ForwardedRegister &F : Forwards) {
984  // FIXME Can we use a less constrained schedule?
985  SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
987  Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal);
988  }
989  }
990 
991  // Some CCs need callee pop.
992  if (M68k::isCalleePop(CCID, IsVarArg,
994  MMFI->setBytesToPopOnReturn(StackSize); // Callee pops everything.
995  } else {
996  MMFI->setBytesToPopOnReturn(0); // Callee pops nothing.
997  // If this is an sret function, the return should pop the hidden pointer.
999  MMFI->setBytesToPopOnReturn(4);
1000  }
1001 
1002  MMFI->setArgumentStackSize(StackSize);
1003 
1004  return Chain;
1005 }
1006 
1007 //===----------------------------------------------------------------------===//
1008 // Return Value Calling Convention Implementation
1009 //===----------------------------------------------------------------------===//
1010 
1011 SDValue
1012 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
1013  bool IsVarArg,
1014  const SmallVectorImpl<ISD::OutputArg> &Outs,
1015  const SmallVectorImpl<SDValue> &OutVals,
1016  const SDLoc &DL, SelectionDAG &DAG) const {
1017  MachineFunction &MF = DAG.getMachineFunction();
1019 
1021  CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1022  CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1023 
1024  SDValue Flag;
1025  SmallVector<SDValue, 6> RetOps;
1026  // Operand #0 = Chain (updated below)
1027  RetOps.push_back(Chain);
1028  // Operand #1 = Bytes To Pop
1029  RetOps.push_back(
1031 
1032  // Copy the result values into the output registers.
1033  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1034  CCValAssign &VA = RVLocs[i];
1035  assert(VA.isRegLoc() && "Can only return in registers!");
1036  SDValue ValToCopy = OutVals[i];
1037  EVT ValVT = ValToCopy.getValueType();
1038 
1039  // Promote values to the appropriate types.
1040  if (VA.getLocInfo() == CCValAssign::SExt)
1041  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1042  else if (VA.getLocInfo() == CCValAssign::ZExt)
1043  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy);
1044  else if (VA.getLocInfo() == CCValAssign::AExt) {
1045  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
1046  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1047  else
1048  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy);
1049  } else if (VA.getLocInfo() == CCValAssign::BCvt)
1050  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1051 
1052  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Flag);
1053  Flag = Chain.getValue(1);
1054  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1055  }
1056 
1057  // Swift calling convention does not require we copy the sret argument
1058  // into %d0 for the return, and SRetReturnReg is not set for Swift.
1059 
1060  // ABI require that for returning structs by value we copy the sret argument
1061  // into %D0 for the return. Save the argument into a virtual register so that
1062  // we can access it from the return points.
1063  //
1064  // Checking Function.hasStructRetAttr() here is insufficient because the IR
1065  // may not have an explicit sret argument. If MFI.CanLowerReturn is
1066  // false, then an sret argument may be implicitly inserted in the SelDAG. In
1067  // either case MFI->setSRetReturnReg() will have been called.
1068  if (unsigned SRetReg = MFI->getSRetReturnReg()) {
1069  // ??? Can i just move this to the top and escape this explanation?
1070  // When we have both sret and another return value, we should use the
1071  // original Chain stored in RetOps[0], instead of the current Chain updated
1072  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
1073 
1074  // For the case of sret and another return value, we have
1075  // Chain_0 at the function entry
1076  // Chain_1 = getCopyToReg(Chain_0) in the above loop
1077  // If we use Chain_1 in getCopyFromReg, we will have
1078  // Val = getCopyFromReg(Chain_1)
1079  // Chain_2 = getCopyToReg(Chain_1, Val) from below
1080 
1081  // getCopyToReg(Chain_0) will be glued together with
1082  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
1083  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
1084  // Data dependency from Unit B to Unit A due to usage of Val in
1085  // getCopyToReg(Chain_1, Val)
1086  // Chain dependency from Unit A to Unit B
1087 
1088  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
1089  SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
1090  getPointerTy(MF.getDataLayout()));
1091 
1092  // ??? How will this work if CC does not use registers for args passing?
1093  // ??? What if I return multiple structs?
1094  unsigned RetValReg = M68k::D0;
1095  Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Flag);
1096  Flag = Chain.getValue(1);
1097 
1098  RetOps.push_back(
1099  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
1100  }
1101 
1102  RetOps[0] = Chain; // Update chain.
1103 
1104  // Add the flag if we have it.
1105  if (Flag.getNode())
1106  RetOps.push_back(Flag);
1107 
1108  return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps);
1109 }
1110 
1111 //===----------------------------------------------------------------------===//
1112 // Fast Calling Convention (tail call) implementation
1113 //===----------------------------------------------------------------------===//
1114 
1115 // Like std call, callee cleans arguments, convention except that ECX is
1116 // reserved for storing the tail called function address. Only 2 registers are
1117 // free for argument passing (inreg). Tail call optimization is performed
1118 // provided:
1119 // * tailcallopt is enabled
1120 // * caller/callee are fastcc
1121 // On M68k_64 architecture with GOT-style position independent code only
1122 // local (within module) calls are supported at the moment. To keep the stack
1123 // aligned according to platform abi the function GetAlignedArgumentStackSize
1124 // ensures that argument delta is always multiples of stack alignment. (Dynamic
1125 // linkers need this - darwin's dyld for example) If a tail called function
1126 // callee has more arguments than the caller the caller needs to make sure that
1127 // there is room to move the RETADDR to. This is achieved by reserving an area
1128 // the size of the argument delta right after the original RETADDR, but before
1129 // the saved framepointer or the spilled registers e.g. caller(arg1, arg2)
1130 // calls callee(arg1, arg2,arg3,arg4) stack layout:
1131 // arg1
1132 // arg2
1133 // RETADDR
1134 // [ new RETADDR
1135 // move area ]
1136 // (possible EBP)
1137 // ESI
1138 // EDI
1139 // local1 ..
1140 
1141 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
1142 /// requirement.
1143 unsigned
1144 M68kTargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1145  SelectionDAG &DAG) const {
1146  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
1147  unsigned StackAlignment = TFI.getStackAlignment();
1148  uint64_t AlignMask = StackAlignment - 1;
1149  int64_t Offset = StackSize;
1150  unsigned SlotSize = Subtarget.getSlotSize();
1151  if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1152  // Number smaller than 12 so just add the difference.
1153  Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1154  } else {
1155  // Mask out lower bits, add stackalignment once plus the 12 bytes.
1156  Offset =
1157  ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1158  }
1159  return Offset;
1160 }
1161 
1162 /// Check whether the call is eligible for tail call optimization. Targets
1163 /// that want to do tail call optimization should implement this function.
1164 bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1165  SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
1166  bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
1167  const SmallVectorImpl<ISD::OutputArg> &Outs,
1168  const SmallVectorImpl<SDValue> &OutVals,
1169  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1170  if (!mayTailCallThisCC(CalleeCC))
1171  return false;
1172 
1173  // If -tailcallopt is specified, make fastcc functions tail-callable.
1174  MachineFunction &MF = DAG.getMachineFunction();
1175  const auto &CallerF = MF.getFunction();
1176 
1177  CallingConv::ID CallerCC = CallerF.getCallingConv();
1178  bool CCMatch = CallerCC == CalleeCC;
1179 
1181  if (canGuaranteeTCO(CalleeCC) && CCMatch)
1182  return true;
1183  return false;
1184  }
1185 
1186  // Look for obvious safe cases to perform tail call optimization that do not
1187  // require ABI changes. This is what gcc calls sibcall.
1188 
1189  // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1190  // emit a special epilogue.
1191  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1192  if (RegInfo->hasStackRealignment(MF))
1193  return false;
1194 
1195  // Also avoid sibcall optimization if either caller or callee uses struct
1196  // return semantics.
1197  if (IsCalleeStructRet || IsCallerStructRet)
1198  return false;
1199 
1200  // Do not sibcall optimize vararg calls unless all arguments are passed via
1201  // registers.
1202  LLVMContext &C = *DAG.getContext();
1203  if (IsVarArg && !Outs.empty()) {
1204 
1206  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1207 
1208  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1209  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1210  if (!ArgLocs[i].isRegLoc())
1211  return false;
1212  }
1213 
1214  // Check that the call results are passed in the same way.
1215  if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, RetCC_M68k,
1216  RetCC_M68k))
1217  return false;
1218 
1219  // The callee has to preserve all registers the caller needs to preserve.
1220  const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
1221  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1222  if (!CCMatch) {
1223  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1224  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1225  return false;
1226  }
1227 
1228  unsigned StackArgsSize = 0;
1229 
1230  // If the callee takes no arguments then go on to check the results of the
1231  // call.
1232  if (!Outs.empty()) {
1233  // Check if stack adjustment is needed. For now, do not do this if any
1234  // argument is passed on the stack.
1236  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1237 
1238  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1239  StackArgsSize = CCInfo.getNextStackOffset();
1240 
1241  if (CCInfo.getNextStackOffset()) {
1242  // Check if the arguments are already laid out in the right way as
1243  // the caller's fixed stack objects.
1244  MachineFrameInfo &MFI = MF.getFrameInfo();
1245  const MachineRegisterInfo *MRI = &MF.getRegInfo();
1246  const M68kInstrInfo *TII = Subtarget.getInstrInfo();
1247  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1248  CCValAssign &VA = ArgLocs[i];
1249  SDValue Arg = OutVals[i];
1250  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1251  if (VA.getLocInfo() == CCValAssign::Indirect)
1252  return false;
1253  if (!VA.isRegLoc()) {
1254  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI,
1255  TII, VA))
1256  return false;
1257  }
1258  }
1259  }
1260 
1261  bool PositionIndependent = isPositionIndependent();
1262  // If the tailcall address may be in a register, then make sure it's
1263  // possible to register allocate for it. The call address can
1264  // only target %A0 or %A1 since the tail call must be scheduled after
1265  // callee-saved registers are restored. These happen to be the same
1266  // registers used to pass 'inreg' arguments so watch out for those.
1267  if ((!isa<GlobalAddressSDNode>(Callee) &&
1268  !isa<ExternalSymbolSDNode>(Callee)) ||
1269  PositionIndependent) {
1270  unsigned NumInRegs = 0;
1271  // In PIC we need an extra register to formulate the address computation
1272  // for the callee.
1273  unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1274 
1275  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1276  CCValAssign &VA = ArgLocs[i];
1277  if (!VA.isRegLoc())
1278  continue;
1279  unsigned Reg = VA.getLocReg();
1280  switch (Reg) {
1281  default:
1282  break;
1283  case M68k::A0:
1284  case M68k::A1:
1285  if (++NumInRegs == MaxInRegs)
1286  return false;
1287  break;
1288  }
1289  }
1290  }
1291 
1292  const MachineRegisterInfo &MRI = MF.getRegInfo();
1293  if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
1294  return false;
1295  }
1296 
1297  bool CalleeWillPop = M68k::isCalleePop(
1298  CalleeCC, IsVarArg, MF.getTarget().Options.GuaranteedTailCallOpt);
1299 
1300  if (unsigned BytesToPop =
1302  // If we have bytes to pop, the callee must pop them.
1303  bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1304  if (!CalleePopMatches)
1305  return false;
1306  } else if (CalleeWillPop && StackArgsSize > 0) {
1307  // If we don't have bytes to pop, make sure the callee doesn't pop any.
1308  return false;
1309  }
1310 
1311  return true;
1312 }
1313 
1314 //===----------------------------------------------------------------------===//
1315 // Custom Lower
1316 //===----------------------------------------------------------------------===//
1317 
1319  SelectionDAG &DAG) const {
1320  switch (Op.getOpcode()) {
1321  default:
1322  llvm_unreachable("Should not custom lower this!");
1323  case ISD::SADDO:
1324  case ISD::UADDO:
1325  case ISD::SSUBO:
1326  case ISD::USUBO:
1327  case ISD::SMULO:
1328  case ISD::UMULO:
1329  return LowerXALUO(Op, DAG);
1330  case ISD::SETCC:
1331  return LowerSETCC(Op, DAG);
1332  case ISD::SETCCCARRY:
1333  return LowerSETCCCARRY(Op, DAG);
1334  case ISD::SELECT:
1335  return LowerSELECT(Op, DAG);
1336  case ISD::BRCOND:
1337  return LowerBRCOND(Op, DAG);
1338  case ISD::ADDC:
1339  case ISD::ADDE:
1340  case ISD::SUBC:
1341  case ISD::SUBE:
1342  return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1343  case ISD::ConstantPool:
1344  return LowerConstantPool(Op, DAG);
1345  case ISD::GlobalAddress:
1346  return LowerGlobalAddress(Op, DAG);
1347  case ISD::ExternalSymbol:
1348  return LowerExternalSymbol(Op, DAG);
1349  case ISD::BlockAddress:
1350  return LowerBlockAddress(Op, DAG);
1351  case ISD::JumpTable:
1352  return LowerJumpTable(Op, DAG);
1353  case ISD::VASTART:
1354  return LowerVASTART(Op, DAG);
1356  return LowerDYNAMIC_STACKALLOC(Op, DAG);
1357  }
1358 }
1359 
1360 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1361  SDValue C) const {
1362  // Shifts and add instructions in M68000 and M68010 support
1363  // up to 32 bits, but mul only has 16-bit variant. So it's almost
1364  // certainly beneficial to lower 8/16/32-bit mul to their
1365  // add / shifts counterparts. But for 64-bits mul, it might be
1366  // safer to just leave it to compiler runtime implementations.
1367  return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
1368 }
1369 
1370 SDValue M68kTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
1371  // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
1372  // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1373  // looks for this combo and may remove the "setcc" instruction if the "setcc"
1374  // has only one use.
1375  SDNode *N = Op.getNode();
1376  SDValue LHS = N->getOperand(0);
1377  SDValue RHS = N->getOperand(1);
1378  unsigned BaseOp = 0;
1379  unsigned Cond = 0;
1380  SDLoc DL(Op);
1381  switch (Op.getOpcode()) {
1382  default:
1383  llvm_unreachable("Unknown ovf instruction!");
1384  case ISD::SADDO:
1385  BaseOp = M68kISD::ADD;
1386  Cond = M68k::COND_VS;
1387  break;
1388  case ISD::UADDO:
1389  BaseOp = M68kISD::ADD;
1390  Cond = M68k::COND_CS;
1391  break;
1392  case ISD::SSUBO:
1393  BaseOp = M68kISD::SUB;
1394  Cond = M68k::COND_VS;
1395  break;
1396  case ISD::USUBO:
1397  BaseOp = M68kISD::SUB;
1398  Cond = M68k::COND_CS;
1399  break;
1400  }
1401 
1402  // Also sets CCR.
1403  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i8);
1404  SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
1405  SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1406  DAG.getConstant(Cond, DL, MVT::i8),
1407  SDValue(Arith.getNode(), 1));
1408 
1409  return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1410 }
1411 
1412 /// Create a BT (Bit Test) node - Test bit \p BitNo in \p Src and set condition
1413 /// according to equal/not-equal condition code \p CC.
1415  const SDLoc &DL, SelectionDAG &DAG) {
1416  // If Src is i8, promote it to i32 with any_extend. There is no i8 BT
1417  // instruction. Since the shift amount is in-range-or-undefined, we know
1418  // that doing a bittest on the i32 value is ok.
1419  if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1420  Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
1421 
1422  // If the operand types disagree, extend the shift amount to match. Since
1423  // BT ignores high bits (like shifts) we can use anyextend.
1424  if (Src.getValueType() != BitNo.getValueType())
1425  BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo);
1426 
1427  SDValue BT = DAG.getNode(M68kISD::BT, DL, MVT::i32, Src, BitNo);
1428 
1429  // NOTE BTST sets CCR.Z flag
1431  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1432  DAG.getConstant(Cond, DL, MVT::i8), BT);
1433 }
1434 
1435 /// Result of 'and' is compared against zero. Change to a BT node if possible.
1437  SelectionDAG &DAG) {
1438  SDValue Op0 = And.getOperand(0);
1439  SDValue Op1 = And.getOperand(1);
1440  if (Op0.getOpcode() == ISD::TRUNCATE)
1441  Op0 = Op0.getOperand(0);
1442  if (Op1.getOpcode() == ISD::TRUNCATE)
1443  Op1 = Op1.getOperand(0);
1444 
1445  SDValue LHS, RHS;
1446  if (Op1.getOpcode() == ISD::SHL)
1447  std::swap(Op0, Op1);
1448  if (Op0.getOpcode() == ISD::SHL) {
1449  if (isOneConstant(Op0.getOperand(0))) {
1450  // If we looked past a truncate, check that it's only truncating away
1451  // known zeros.
1452  unsigned BitWidth = Op0.getValueSizeInBits();
1453  unsigned AndBitWidth = And.getValueSizeInBits();
1454  if (BitWidth > AndBitWidth) {
1455  auto Known = DAG.computeKnownBits(Op0);
1456  if (Known.countMinLeadingZeros() < BitWidth - AndBitWidth)
1457  return SDValue();
1458  }
1459  LHS = Op1;
1460  RHS = Op0.getOperand(1);
1461  }
1462  } else if (auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1463  uint64_t AndRHSVal = AndRHS->getZExtValue();
1464  SDValue AndLHS = Op0;
1465 
1466  if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
1467  LHS = AndLHS.getOperand(0);
1468  RHS = AndLHS.getOperand(1);
1469  }
1470 
1471  // Use BT if the immediate can't be encoded in a TEST instruction.
1472  if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
1473  LHS = AndLHS;
1474  RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType());
1475  }
1476  }
1477 
1478  if (LHS.getNode())
1479  return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1480 
1481  return SDValue();
1482 }
1483 
1485  switch (SetCCOpcode) {
1486  default:
1487  llvm_unreachable("Invalid integer condition!");
1488  case ISD::SETEQ:
1489  return M68k::COND_EQ;
1490  case ISD::SETGT:
1491  return M68k::COND_GT;
1492  case ISD::SETGE:
1493  return M68k::COND_GE;
1494  case ISD::SETLT:
1495  return M68k::COND_LT;
1496  case ISD::SETLE:
1497  return M68k::COND_LE;
1498  case ISD::SETNE:
1499  return M68k::COND_NE;
1500  case ISD::SETULT:
1501  return M68k::COND_CS;
1502  case ISD::SETUGE:
1503  return M68k::COND_CC;
1504  case ISD::SETUGT:
1505  return M68k::COND_HI;
1506  case ISD::SETULE:
1507  return M68k::COND_LS;
1508  }
1509 }
1510 
1511 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1512 /// condition code, returning the condition code and the LHS/RHS of the
1513 /// comparison to make.
1514 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1515  bool IsFP, SDValue &LHS, SDValue &RHS,
1516  SelectionDAG &DAG) {
1517  if (!IsFP) {
1518  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1519  if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1520  // X > -1 -> X == 0, jump !sign.
1521  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1522  return M68k::COND_PL;
1523  }
1524  if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1525  // X < 0 -> X == 0, jump on sign.
1526  return M68k::COND_MI;
1527  }
1528  if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1529  // X < 1 -> X <= 0
1530  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1531  return M68k::COND_LE;
1532  }
1533  }
1534 
1535  return TranslateIntegerM68kCC(SetCCOpcode);
1536  }
1537 
1538  // First determine if it is required or is profitable to flip the operands.
1539 
1540  // If LHS is a foldable load, but RHS is not, flip the condition.
1541  if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) {
1542  SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1543  std::swap(LHS, RHS);
1544  }
1545 
1546  switch (SetCCOpcode) {
1547  default:
1548  break;
1549  case ISD::SETOLT:
1550  case ISD::SETOLE:
1551  case ISD::SETUGT:
1552  case ISD::SETUGE:
1553  std::swap(LHS, RHS);
1554  break;
1555  }
1556 
1557  // On a floating point condition, the flags are set as follows:
1558  // ZF PF CF op
1559  // 0 | 0 | 0 | X > Y
1560  // 0 | 0 | 1 | X < Y
1561  // 1 | 0 | 0 | X == Y
1562  // 1 | 1 | 1 | unordered
1563  switch (SetCCOpcode) {
1564  default:
1565  llvm_unreachable("Condcode should be pre-legalized away");
1566  case ISD::SETUEQ:
1567  case ISD::SETEQ:
1568  return M68k::COND_EQ;
1569  case ISD::SETOLT: // flipped
1570  case ISD::SETOGT:
1571  case ISD::SETGT:
1572  return M68k::COND_HI;
1573  case ISD::SETOLE: // flipped
1574  case ISD::SETOGE:
1575  case ISD::SETGE:
1576  return M68k::COND_CC;
1577  case ISD::SETUGT: // flipped
1578  case ISD::SETULT:
1579  case ISD::SETLT:
1580  return M68k::COND_CS;
1581  case ISD::SETUGE: // flipped
1582  case ISD::SETULE:
1583  case ISD::SETLE:
1584  return M68k::COND_LS;
1585  case ISD::SETONE:
1586  case ISD::SETNE:
1587  return M68k::COND_NE;
1588  case ISD::SETOEQ:
1589  case ISD::SETUNE:
1590  return M68k::COND_INVALID;
1591  }
1592 }
1593 
1594 // Convert (truncate (srl X, N) to i1) to (bt X, N)
1596  SelectionDAG &DAG) {
1597 
1598  assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
1599  "Expected TRUNCATE to i1 node");
1600 
1601  if (Op.getOperand(0).getOpcode() != ISD::SRL)
1602  return SDValue();
1603 
1604  SDValue ShiftRight = Op.getOperand(0);
1605  return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
1606  CC, DL, DAG);
1607 }
1608 
1609 /// \brief return true if \c Op has a use that doesn't just read flags.
1610 static bool hasNonFlagsUse(SDValue Op) {
1611  for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
1612  ++UI) {
1613  SDNode *User = *UI;
1614  unsigned UOpNo = UI.getOperandNo();
1615  if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1616  // Look pass truncate.
1617  UOpNo = User->use_begin().getOperandNo();
1618  User = *User->use_begin();
1619  }
1620 
1621  if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
1622  !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
1623  return true;
1624  }
1625  return false;
1626 }
1627 
1628 SDValue M68kTargetLowering::EmitTest(SDValue Op, unsigned M68kCC,
1629  const SDLoc &DL, SelectionDAG &DAG) const {
1630 
1631  // CF and OF aren't always set the way we want. Determine which
1632  // of these we need.
1633  bool NeedCF = false;
1634  bool NeedOF = false;
1635  switch (M68kCC) {
1636  default:
1637  break;
1638  case M68k::COND_HI:
1639  case M68k::COND_CC:
1640  case M68k::COND_CS:
1641  case M68k::COND_LS:
1642  NeedCF = true;
1643  break;
1644  case M68k::COND_GT:
1645  case M68k::COND_GE:
1646  case M68k::COND_LT:
1647  case M68k::COND_LE:
1648  case M68k::COND_VS:
1649  case M68k::COND_VC: {
1650  // Check if we really need to set the
1651  // Overflow flag. If NoSignedWrap is present
1652  // that is not actually needed.
1653  switch (Op->getOpcode()) {
1654  case ISD::ADD:
1655  case ISD::SUB:
1656  case ISD::MUL:
1657  case ISD::SHL: {
1658  if (Op.getNode()->getFlags().hasNoSignedWrap())
1659  break;
1661  }
1662  default:
1663  NeedOF = true;
1664  break;
1665  }
1666  break;
1667  }
1668  }
1669  // See if we can use the CCR value from the operand instead of
1670  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
1671  // we prove that the arithmetic won't overflow, we can't use OF or CF.
1672  if (Op.getResNo() != 0 || NeedOF || NeedCF) {
1673  // Emit a CMP with 0, which is the TEST pattern.
1674  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1675  DAG.getConstant(0, DL, Op.getValueType()), Op);
1676  }
1677  unsigned Opcode = 0;
1678  unsigned NumOperands = 0;
1679 
1680  // Truncate operations may prevent the merge of the SETCC instruction
1681  // and the arithmetic instruction before it. Attempt to truncate the operands
1682  // of the arithmetic instruction and use a reduced bit-width instruction.
1683  bool NeedTruncation = false;
1684  SDValue ArithOp = Op;
1685  if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
1686  SDValue Arith = Op->getOperand(0);
1687  // Both the trunc and the arithmetic op need to have one user each.
1688  if (Arith->hasOneUse())
1689  switch (Arith.getOpcode()) {
1690  default:
1691  break;
1692  case ISD::ADD:
1693  case ISD::SUB:
1694  case ISD::AND:
1695  case ISD::OR:
1696  case ISD::XOR: {
1697  NeedTruncation = true;
1698  ArithOp = Arith;
1699  }
1700  }
1701  }
1702 
1703  // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
1704  // which may be the result of a CAST. We use the variable 'Op', which is the
1705  // non-casted variable when we check for possible users.
1706  switch (ArithOp.getOpcode()) {
1707  case ISD::ADD:
1708  Opcode = M68kISD::ADD;
1709  NumOperands = 2;
1710  break;
1711  case ISD::SHL:
1712  case ISD::SRL:
1713  // If we have a constant logical shift that's only used in a comparison
1714  // against zero turn it into an equivalent AND. This allows turning it into
1715  // a TEST instruction later.
1716  if ((M68kCC == M68k::COND_EQ || M68kCC == M68k::COND_NE) &&
1717  Op->hasOneUse() && isa<ConstantSDNode>(Op->getOperand(1)) &&
1718  !hasNonFlagsUse(Op)) {
1719  EVT VT = Op.getValueType();
1720  unsigned BitWidth = VT.getSizeInBits();
1721  unsigned ShAmt = Op->getConstantOperandVal(1);
1722  if (ShAmt >= BitWidth) // Avoid undefined shifts.
1723  break;
1724  APInt Mask = ArithOp.getOpcode() == ISD::SRL
1726  : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
1727  if (!Mask.isSignedIntN(32)) // Avoid large immediates.
1728  break;
1729  Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0),
1730  DAG.getConstant(Mask, DL, VT));
1731  }
1732  break;
1733 
1734  case ISD::AND:
1735  // If the primary 'and' result isn't used, don't bother using
1736  // M68kISD::AND, because a TEST instruction will be better.
1737  if (!hasNonFlagsUse(Op)) {
1738  SDValue Op0 = ArithOp->getOperand(0);
1739  SDValue Op1 = ArithOp->getOperand(1);
1740  EVT VT = ArithOp.getValueType();
1741  bool IsAndn = isBitwiseNot(Op0) || isBitwiseNot(Op1);
1742  bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1743 
1744  // But if we can combine this into an ANDN operation, then create an AND
1745  // now and allow it to be pattern matched into an ANDN.
1746  if (/*!Subtarget.hasBMI() ||*/ !IsAndn || !IsLegalAndnType)
1747  break;
1748  }
1750  case ISD::SUB:
1751  case ISD::OR:
1752  case ISD::XOR:
1753  // Due to the ISEL shortcoming noted above, be conservative if this op is
1754  // likely to be selected as part of a load-modify-store instruction.
1755  for (const auto *U : Op.getNode()->uses())
1756  if (U->getOpcode() == ISD::STORE)
1757  goto default_case;
1758 
1759  // Otherwise use a regular CCR-setting instruction.
1760  switch (ArithOp.getOpcode()) {
1761  default:
1762  llvm_unreachable("unexpected operator!");
1763  case ISD::SUB:
1764  Opcode = M68kISD::SUB;
1765  break;
1766  case ISD::XOR:
1767  Opcode = M68kISD::XOR;
1768  break;
1769  case ISD::AND:
1770  Opcode = M68kISD::AND;
1771  break;
1772  case ISD::OR:
1773  Opcode = M68kISD::OR;
1774  break;
1775  }
1776 
1777  NumOperands = 2;
1778  break;
1779  case M68kISD::ADD:
1780  case M68kISD::SUB:
1781  case M68kISD::OR:
1782  case M68kISD::XOR:
1783  case M68kISD::AND:
1784  return SDValue(Op.getNode(), 1);
1785  default:
1786  default_case:
1787  break;
1788  }
1789 
1790  // If we found that truncation is beneficial, perform the truncation and
1791  // update 'Op'.
1792  if (NeedTruncation) {
1793  EVT VT = Op.getValueType();
1794  SDValue WideVal = Op->getOperand(0);
1795  EVT WideVT = WideVal.getValueType();
1796  unsigned ConvertedOp = 0;
1797  // Use a target machine opcode to prevent further DAGCombine
1798  // optimizations that may separate the arithmetic operations
1799  // from the setcc node.
1800  switch (WideVal.getOpcode()) {
1801  default:
1802  break;
1803  case ISD::ADD:
1804  ConvertedOp = M68kISD::ADD;
1805  break;
1806  case ISD::SUB:
1807  ConvertedOp = M68kISD::SUB;
1808  break;
1809  case ISD::AND:
1810  ConvertedOp = M68kISD::AND;
1811  break;
1812  case ISD::OR:
1813  ConvertedOp = M68kISD::OR;
1814  break;
1815  case ISD::XOR:
1816  ConvertedOp = M68kISD::XOR;
1817  break;
1818  }
1819 
1820  if (ConvertedOp) {
1821  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1822  if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
1823  SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
1824  SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1));
1825  Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
1826  }
1827  }
1828  }
1829 
1830  if (Opcode == 0) {
1831  // Emit a CMP with 0, which is the TEST pattern.
1832  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1833  DAG.getConstant(0, DL, Op.getValueType()), Op);
1834  }
1835  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8);
1836  SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
1837 
1838  SDValue New = DAG.getNode(Opcode, DL, VTs, Ops);
1839  DAG.ReplaceAllUsesWith(Op, New);
1840  return SDValue(New.getNode(), 1);
1841 }
1842 
1843 /// \brief Return true if the condition is an unsigned comparison operation.
1844 static bool isM68kCCUnsigned(unsigned M68kCC) {
1845  switch (M68kCC) {
1846  default:
1847  llvm_unreachable("Invalid integer condition!");
1848  case M68k::COND_EQ:
1849  case M68k::COND_NE:
1850  case M68k::COND_CS:
1851  case M68k::COND_HI:
1852  case M68k::COND_LS:
1853  case M68k::COND_CC:
1854  return true;
1855  case M68k::COND_GT:
1856  case M68k::COND_GE:
1857  case M68k::COND_LT:
1858  case M68k::COND_LE:
1859  return false;
1860  }
1861 }
1862 
1863 SDValue M68kTargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC,
1864  const SDLoc &DL, SelectionDAG &DAG) const {
1865  if (isNullConstant(Op1))
1866  return EmitTest(Op0, M68kCC, DL, DAG);
1867 
1868  assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
1869  "Unexpected comparison operation for MVT::i1 operands");
1870 
1871  if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
1872  Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
1873  // Only promote the compare up to I32 if it is a 16 bit operation
1874  // with an immediate. 16 bit immediates are to be avoided.
1875  if ((Op0.getValueType() == MVT::i16 &&
1876  (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
1878  unsigned ExtendOp =
1880  Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0);
1881  Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1);
1882  }
1883  // Use SUB instead of CMP to enable CSE between SUB and CMP.
1884  SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8);
1885  SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1);
1886  return SDValue(Sub.getNode(), 1);
1887  }
1888  return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1);
1889 }
1890 
1891 /// Result of 'and' or 'trunc to i1' is compared against zero.
1892 /// Change to a BT node if possible.
1893 SDValue M68kTargetLowering::LowerToBT(SDValue Op, ISD::CondCode CC,
1894  const SDLoc &DL,
1895  SelectionDAG &DAG) const {
1896  if (Op.getOpcode() == ISD::AND)
1897  return LowerAndToBT(Op, CC, DL, DAG);
1898  if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
1899  return LowerTruncateToBT(Op, CC, DL, DAG);
1900  return SDValue();
1901 }
1902 
1903 SDValue M68kTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1904  MVT VT = Op.getSimpleValueType();
1905  assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
1906 
1907  SDValue Op0 = Op.getOperand(0);
1908  SDValue Op1 = Op.getOperand(1);
1909  SDLoc DL(Op);
1910  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1911 
1912  // Optimize to BT if possible.
1913  // Lower (X & (1 << N)) == 0 to BT(X, N).
1914  // Lower ((X >>u N) & 1) != 0 to BT(X, N).
1915  // Lower ((X >>s N) & 1) != 0 to BT(X, N).
1916  // Lower (trunc (X >> N) to i1) to BT(X, N).
1917  if (Op0.hasOneUse() && isNullConstant(Op1) &&
1918  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1919  if (SDValue NewSetCC = LowerToBT(Op0, CC, DL, DAG)) {
1920  if (VT == MVT::i1)
1921  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC);
1922  return NewSetCC;
1923  }
1924  }
1925 
1926  // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
1927  // these.
1928  if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
1929  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1930 
1931  // If the input is a setcc, then reuse the input setcc or use a new one with
1932  // the inverted condition.
1933  if (Op0.getOpcode() == M68kISD::SETCC) {
1935  bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
1936  if (!Invert)
1937  return Op0;
1938 
1939  CCode = M68k::GetOppositeBranchCondition(CCode);
1940  SDValue SetCC =
1942  DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1));
1943  if (VT == MVT::i1)
1944  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
1945  return SetCC;
1946  }
1947  }
1948  if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1949  if (isOneConstant(Op1)) {
1951  return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC);
1952  }
1953  if (!isNullConstant(Op1)) {
1954  SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
1955  return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
1956  }
1957  }
1958 
1959  bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
1960  unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
1961  if (M68kCC == M68k::COND_INVALID)
1962  return SDValue();
1963 
1964  SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG);
1965  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1966  DAG.getConstant(M68kCC, DL, MVT::i8), CCR);
1967 }
1968 
1969 SDValue M68kTargetLowering::LowerSETCCCARRY(SDValue Op,
1970  SelectionDAG &DAG) const {
1971  SDValue LHS = Op.getOperand(0);
1972  SDValue RHS = Op.getOperand(1);
1973  SDValue Carry = Op.getOperand(2);
1974  SDValue Cond = Op.getOperand(3);
1975  SDLoc DL(Op);
1976 
1977  assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
1978  M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
1979 
1980  EVT CarryVT = Carry.getValueType();
1981  APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits());
1982  Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry,
1983  DAG.getConstant(NegOne, DL, CarryVT));
1984 
1985  SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
1986  SDValue Cmp =
1987  DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1));
1988 
1989  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1990  DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
1991 }
1992 
1993 /// Return true if opcode is a M68k logical comparison.
1995  unsigned Opc = Op.getNode()->getOpcode();
1996  if (Opc == M68kISD::CMP)
1997  return true;
1998  if (Op.getResNo() == 1 &&
1999  (Opc == M68kISD::ADD || Opc == M68kISD::SUB || Opc == M68kISD::ADDX ||
2000  Opc == M68kISD::SUBX || Opc == M68kISD::SMUL || Opc == M68kISD::UMUL ||
2001  Opc == M68kISD::OR || Opc == M68kISD::XOR || Opc == M68kISD::AND))
2002  return true;
2003 
2004  if (Op.getResNo() == 2 && Opc == M68kISD::UMUL)
2005  return true;
2006 
2007  return false;
2008 }
2009 
2011  if (V.getOpcode() != ISD::TRUNCATE)
2012  return false;
2013 
2014  SDValue VOp0 = V.getOperand(0);
2015  unsigned InBits = VOp0.getValueSizeInBits();
2016  unsigned Bits = V.getValueSizeInBits();
2017  return DAG.MaskedValueIsZero(VOp0,
2018  APInt::getHighBitsSet(InBits, InBits - Bits));
2019 }
2020 
2021 SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2022  bool addTest = true;
2023  SDValue Cond = Op.getOperand(0);
2024  SDValue Op1 = Op.getOperand(1);
2025  SDValue Op2 = Op.getOperand(2);
2026  SDLoc DL(Op);
2027  SDValue CC;
2028 
2029  if (Cond.getOpcode() == ISD::SETCC) {
2030  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2031  Cond = NewCond;
2032  }
2033 
2034  // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2035  // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
2036  // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
2037  // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
2038  if (Cond.getOpcode() == M68kISD::SETCC &&
2039  Cond.getOperand(1).getOpcode() == M68kISD::CMP &&
2040  isNullConstant(Cond.getOperand(1).getOperand(0))) {
2041  SDValue Cmp = Cond.getOperand(1);
2042 
2043  unsigned CondCode =
2044  cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
2045 
2046  if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2048  SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
2049 
2050  SDValue CmpOp0 = Cmp.getOperand(1);
2051  // Apply further optimizations for special cases
2052  // (select (x != 0), -1, 0) -> neg & sbb
2053  // (select (x == 0), 0, -1) -> neg & sbb
2054  if (isNullConstant(Y) &&
2055  (isAllOnesConstant(Op1) == (CondCode == M68k::COND_NE))) {
2056 
2057  SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
2058 
2059  SDValue Neg =
2060  DAG.getNode(M68kISD::SUB, DL, VTs,
2061  DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0);
2062 
2063  SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2065  SDValue(Neg.getNode(), 1));
2066  return Res;
2067  }
2068 
2069  Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2070  DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0);
2071 
2072  SDValue Res = // Res = 0 or -1.
2073  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2074  DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp);
2075 
2076  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_EQ))
2077  Res = DAG.getNOT(DL, Res, Res.getValueType());
2078 
2079  if (!isNullConstant(Op2))
2080  Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
2081  return Res;
2082  }
2083  }
2084 
2085  // Look past (and (setcc_carry (cmp ...)), 1).
2086  if (Cond.getOpcode() == ISD::AND &&
2087  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2088  isOneConstant(Cond.getOperand(1)))
2089  Cond = Cond.getOperand(0);
2090 
2091  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2092  // setting operand in place of the M68kISD::SETCC.
2093  unsigned CondOpcode = Cond.getOpcode();
2094  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2095  CC = Cond.getOperand(0);
2096 
2097  SDValue Cmp = Cond.getOperand(1);
2098  unsigned Opc = Cmp.getOpcode();
2099 
2100  bool IllegalFPCMov = false;
2101 
2102  if ((isM68kLogicalCmp(Cmp) && !IllegalFPCMov) || Opc == M68kISD::BT) {
2103  Cond = Cmp;
2104  addTest = false;
2105  }
2106  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
2107  CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2108  CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2109  SDValue LHS = Cond.getOperand(0);
2110  SDValue RHS = Cond.getOperand(1);
2111  unsigned MxOpcode;
2112  unsigned MxCond;
2113  SDVTList VTs;
2114  switch (CondOpcode) {
2115  case ISD::UADDO:
2116  MxOpcode = M68kISD::ADD;
2117  MxCond = M68k::COND_CS;
2118  break;
2119  case ISD::SADDO:
2120  MxOpcode = M68kISD::ADD;
2121  MxCond = M68k::COND_VS;
2122  break;
2123  case ISD::USUBO:
2124  MxOpcode = M68kISD::SUB;
2125  MxCond = M68k::COND_CS;
2126  break;
2127  case ISD::SSUBO:
2128  MxOpcode = M68kISD::SUB;
2129  MxCond = M68k::COND_VS;
2130  break;
2131  case ISD::UMULO:
2132  MxOpcode = M68kISD::UMUL;
2133  MxCond = M68k::COND_VS;
2134  break;
2135  case ISD::SMULO:
2136  MxOpcode = M68kISD::SMUL;
2137  MxCond = M68k::COND_VS;
2138  break;
2139  default:
2140  llvm_unreachable("unexpected overflowing operator");
2141  }
2142  if (CondOpcode == ISD::UMULO)
2143  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i32);
2144  else
2145  VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2146 
2147  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2148 
2149  if (CondOpcode == ISD::UMULO)
2150  Cond = MxOp.getValue(2);
2151  else
2152  Cond = MxOp.getValue(1);
2153 
2154  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2155  addTest = false;
2156  }
2157 
2158  if (addTest) {
2159  // Look past the truncate if the high bits are known zero.
2161  Cond = Cond.getOperand(0);
2162 
2163  // We know the result of AND is compared against zero. Try to match
2164  // it to BT.
2165  if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
2166  if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
2167  CC = NewSetCC.getOperand(0);
2168  Cond = NewSetCC.getOperand(1);
2169  addTest = false;
2170  }
2171  }
2172  }
2173 
2174  if (addTest) {
2175  CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8);
2176  Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG);
2177  }
2178 
2179  // a < b ? -1 : 0 -> RES = ~setcc_carry
2180  // a < b ? 0 : -1 -> RES = setcc_carry
2181  // a >= b ? -1 : 0 -> RES = setcc_carry
2182  // a >= b ? 0 : -1 -> RES = ~setcc_carry
2183  if (Cond.getOpcode() == M68kISD::SUB) {
2184  unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
2185 
2186  if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) &&
2187  (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2188  (isNullConstant(Op1) || isNullConstant(Op2))) {
2189  SDValue Res =
2190  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2192  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_CS))
2193  return DAG.getNOT(DL, Res, Res.getValueType());
2194  return Res;
2195  }
2196  }
2197 
2198  // M68k doesn't have an i8 cmov. If both operands are the result of a
2199  // truncate widen the cmov and push the truncate through. This avoids
2200  // introducing a new branch during isel and doesn't add any extensions.
2201  if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE &&
2202  Op2.getOpcode() == ISD::TRUNCATE) {
2203  SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
2204  if (T1.getValueType() == T2.getValueType() &&
2205  // Blacklist CopyFromReg to avoid partial register stalls.
2206  T1.getOpcode() != ISD::CopyFromReg &&
2207  T2.getOpcode() != ISD::CopyFromReg) {
2208  SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2209  SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2210  return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2211  }
2212  }
2213 
2214  // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2215  // condition is true.
2216  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2217  SDValue Ops[] = {Op2, Op1, CC, Cond};
2218  return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2219 }
2220 
2221 /// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
2222 /// each of which has no other use apart from the AND / OR.
2223 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
2224  Opc = Op.getOpcode();
2225  if (Opc != ISD::OR && Opc != ISD::AND)
2226  return false;
2227  return (M68k::IsSETCC(Op.getOperand(0).getOpcode()) &&
2228  Op.getOperand(0).hasOneUse() &&
2229  M68k::IsSETCC(Op.getOperand(1).getOpcode()) &&
2230  Op.getOperand(1).hasOneUse());
2231 }
2232 
2233 /// Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the
2234 /// SETCC node has a single use.
2235 static bool isXor1OfSetCC(SDValue Op) {
2236  if (Op.getOpcode() != ISD::XOR)
2237  return false;
2238  if (isOneConstant(Op.getOperand(1)))
2239  return Op.getOperand(0).getOpcode() == M68kISD::SETCC &&
2240  Op.getOperand(0).hasOneUse();
2241  return false;
2242 }
2243 
2244 SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2245  bool AddTest = true;
2246  SDValue Chain = Op.getOperand(0);
2247  SDValue Cond = Op.getOperand(1);
2248  SDValue Dest = Op.getOperand(2);
2249  SDLoc DL(Op);
2250  SDValue CC;
2251  bool Inverted = false;
2252 
2253  if (Cond.getOpcode() == ISD::SETCC) {
2254  // Check for setcc([su]{add,sub}o == 0).
2255  if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
2256  isNullConstant(Cond.getOperand(1)) &&
2257  Cond.getOperand(0).getResNo() == 1 &&
2258  (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
2259  Cond.getOperand(0).getOpcode() == ISD::UADDO ||
2260  Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
2261  Cond.getOperand(0).getOpcode() == ISD::USUBO)) {
2262  Inverted = true;
2263  Cond = Cond.getOperand(0);
2264  } else {
2265  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2266  Cond = NewCond;
2267  }
2268  }
2269 
2270  // Look pass (and (setcc_carry (cmp ...)), 1).
2271  if (Cond.getOpcode() == ISD::AND &&
2272  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2273  isOneConstant(Cond.getOperand(1)))
2274  Cond = Cond.getOperand(0);
2275 
2276  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2277  // setting operand in place of the M68kISD::SETCC.
2278  unsigned CondOpcode = Cond.getOpcode();
2279  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2280  CC = Cond.getOperand(0);
2281 
2282  SDValue Cmp = Cond.getOperand(1);
2283  unsigned Opc = Cmp.getOpcode();
2284 
2285  if (isM68kLogicalCmp(Cmp) || Opc == M68kISD::BT) {
2286  Cond = Cmp;
2287  AddTest = false;
2288  } else {
2289  switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
2290  default:
2291  break;
2292  case M68k::COND_VS:
2293  case M68k::COND_CS:
2294  // These can only come from an arithmetic instruction with overflow,
2295  // e.g. SADDO, UADDO.
2296  Cond = Cond.getNode()->getOperand(1);
2297  AddTest = false;
2298  break;
2299  }
2300  }
2301  }
2302  CondOpcode = Cond.getOpcode();
2303  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2304  CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) {
2305  SDValue LHS = Cond.getOperand(0);
2306  SDValue RHS = Cond.getOperand(1);
2307  unsigned MxOpcode;
2308  unsigned MxCond;
2309  SDVTList VTs;
2310  // Keep this in sync with LowerXALUO, otherwise we might create redundant
2311  // instructions that can't be removed afterwards (i.e. M68kISD::ADD and
2312  // M68kISD::INC).
2313  switch (CondOpcode) {
2314  case ISD::UADDO:
2315  MxOpcode = M68kISD::ADD;
2316  MxCond = M68k::COND_CS;
2317  break;
2318  case ISD::SADDO:
2319  MxOpcode = M68kISD::ADD;
2320  MxCond = M68k::COND_VS;
2321  break;
2322  case ISD::USUBO:
2323  MxOpcode = M68kISD::SUB;
2324  MxCond = M68k::COND_CS;
2325  break;
2326  case ISD::SSUBO:
2327  MxOpcode = M68kISD::SUB;
2328  MxCond = M68k::COND_VS;
2329  break;
2330  case ISD::UMULO:
2331  MxOpcode = M68kISD::UMUL;
2332  MxCond = M68k::COND_VS;
2333  break;
2334  case ISD::SMULO:
2335  MxOpcode = M68kISD::SMUL;
2336  MxCond = M68k::COND_VS;
2337  break;
2338  default:
2339  llvm_unreachable("unexpected overflowing operator");
2340  }
2341 
2342  if (Inverted)
2344 
2345  if (CondOpcode == ISD::UMULO)
2346  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i8);
2347  else
2348  VTs = DAG.getVTList(LHS.getValueType(), MVT::i8);
2349 
2350  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2351 
2352  if (CondOpcode == ISD::UMULO)
2353  Cond = MxOp.getValue(2);
2354  else
2355  Cond = MxOp.getValue(1);
2356 
2357  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2358  AddTest = false;
2359  } else {
2360  unsigned CondOpc;
2361  if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
2362  SDValue Cmp = Cond.getOperand(0).getOperand(1);
2363  if (CondOpc == ISD::OR) {
2364  // Also, recognize the pattern generated by an FCMP_UNE. We can emit
2365  // two branches instead of an explicit OR instruction with a
2366  // separate test.
2367  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp)) {
2368  CC = Cond.getOperand(0).getOperand(0);
2369  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2370  Dest, CC, Cmp);
2371  CC = Cond.getOperand(1).getOperand(0);
2372  Cond = Cmp;
2373  AddTest = false;
2374  }
2375  } else { // ISD::AND
2376  // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
2377  // two branches instead of an explicit AND instruction with a
2378  // separate test. However, we only do this if this block doesn't
2379  // have a fall-through edge, because this requires an explicit
2380  // jmp when the condition is false.
2381  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp) &&
2382  Op.getNode()->hasOneUse()) {
2383  M68k::CondCode CCode =
2384  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2385  CCode = M68k::GetOppositeBranchCondition(CCode);
2386  CC = DAG.getConstant(CCode, DL, MVT::i8);
2387  SDNode *User = *Op.getNode()->use_begin();
2388  // Look for an unconditional branch following this conditional branch.
2389  // We need this because we need to reverse the successors in order
2390  // to implement FCMP_OEQ.
2391  if (User->getOpcode() == ISD::BR) {
2392  SDValue FalseBB = User->getOperand(1);
2393  SDNode *NewBR =
2394  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
2395  assert(NewBR == User);
2396  (void)NewBR;
2397  Dest = FalseBB;
2398 
2399  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2400  Dest, CC, Cmp);
2401  M68k::CondCode CCode =
2402  (M68k::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
2403  CCode = M68k::GetOppositeBranchCondition(CCode);
2404  CC = DAG.getConstant(CCode, DL, MVT::i8);
2405  Cond = Cmp;
2406  AddTest = false;
2407  }
2408  }
2409  }
2410  } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
2411  // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
2412  // It should be transformed during dag combiner except when the condition
2413  // is set by a arithmetics with overflow node.
2414  M68k::CondCode CCode =
2415  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2416  CCode = M68k::GetOppositeBranchCondition(CCode);
2417  CC = DAG.getConstant(CCode, DL, MVT::i8);
2418  Cond = Cond.getOperand(0).getOperand(1);
2419  AddTest = false;
2420  }
2421  }
2422 
2423  if (AddTest) {
2424  // Look pass the truncate if the high bits are known zero.
2426  Cond = Cond.getOperand(0);
2427 
2428  // We know the result is compared against zero. Try to match it to BT.
2429  if (Cond.hasOneUse()) {
2430  if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
2431  CC = NewSetCC.getOperand(0);
2432  Cond = NewSetCC.getOperand(1);
2433  AddTest = false;
2434  }
2435  }
2436  }
2437 
2438  if (AddTest) {
2439  M68k::CondCode MxCond = Inverted ? M68k::COND_EQ : M68k::COND_NE;
2440  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2441  Cond = EmitTest(Cond, MxCond, DL, DAG);
2442  }
2443  return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
2444  Cond);
2445 }
2446 
2447 SDValue M68kTargetLowering::LowerADDC_ADDE_SUBC_SUBE(SDValue Op,
2448  SelectionDAG &DAG) const {
2449  MVT VT = Op.getNode()->getSimpleValueType(0);
2450 
2451  // Let legalize expand this if it isn't a legal type yet.
2452  if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2453  return SDValue();
2454 
2455  SDVTList VTs = DAG.getVTList(VT, MVT::i8);
2456 
2457  unsigned Opc;
2458  bool ExtraOp = false;
2459  switch (Op.getOpcode()) {
2460  default:
2461  llvm_unreachable("Invalid code");
2462  case ISD::ADDC:
2463  Opc = M68kISD::ADD;
2464  break;
2465  case ISD::ADDE:
2466  Opc = M68kISD::ADDX;
2467  ExtraOp = true;
2468  break;
2469  case ISD::SUBC:
2470  Opc = M68kISD::SUB;
2471  break;
2472  case ISD::SUBE:
2473  Opc = M68kISD::SUBX;
2474  ExtraOp = true;
2475  break;
2476  }
2477 
2478  if (!ExtraOp)
2479  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2480  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2481  Op.getOperand(2));
2482 }
2483 
2484 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2485 // their target countpart wrapped in the M68kISD::Wrapper node. Suppose N is
2486 // one of the above mentioned nodes. It has to be wrapped because otherwise
2487 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2488 // be used to form addressing mode. These wrapped nodes will be selected
2489 // into MOV32ri.
2490 SDValue M68kTargetLowering::LowerConstantPool(SDValue Op,
2491  SelectionDAG &DAG) const {
2492  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2493 
2494  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2495  // global base reg.
2496  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2497 
2498  unsigned WrapperKind = M68kISD::Wrapper;
2499  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2500  WrapperKind = M68kISD::WrapperPC;
2501  }
2502 
2503  MVT PtrVT = getPointerTy(DAG.getDataLayout());
2505  CP->getConstVal(), PtrVT, CP->getAlign(), CP->getOffset(), OpFlag);
2506 
2507  SDLoc DL(CP);
2508  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2509 
2510  // With PIC, the address is actually $g + Offset.
2511  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2512  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2513  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2514  Result);
2515  }
2516 
2517  return Result;
2518 }
2519 
2520 SDValue M68kTargetLowering::LowerExternalSymbol(SDValue Op,
2521  SelectionDAG &DAG) const {
2522  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2523 
2524  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2525  // global base reg.
2526  const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
2527  unsigned char OpFlag = Subtarget.classifyExternalReference(*Mod);
2528 
2529  unsigned WrapperKind = M68kISD::Wrapper;
2530  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2531  WrapperKind = M68kISD::WrapperPC;
2532  }
2533 
2534  auto PtrVT = getPointerTy(DAG.getDataLayout());
2535  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
2536 
2537  SDLoc DL(Op);
2538  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2539 
2540  // With PIC, the address is actually $g + Offset.
2541  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2542  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2543  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2544  Result);
2545  }
2546 
2547  // For symbols that require a load from a stub to get the address, emit the
2548  // load.
2549  if (M68kII::isGlobalStubReference(OpFlag)) {
2550  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2552  }
2553 
2554  return Result;
2555 }
2556 
2557 SDValue M68kTargetLowering::LowerBlockAddress(SDValue Op,
2558  SelectionDAG &DAG) const {
2559  unsigned char OpFlags = Subtarget.classifyBlockAddressReference();
2560  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2561  int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2562  SDLoc DL(Op);
2563  auto PtrVT = getPointerTy(DAG.getDataLayout());
2564 
2565  // Create the TargetBlockAddressAddress node.
2566  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
2567 
2568  if (M68kII::isPCRelBlockReference(OpFlags)) {
2569  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2570  } else {
2571  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2572  }
2573 
2574  // With PIC, the address is actually $g + Offset.
2575  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2576  Result =
2577  DAG.getNode(ISD::ADD, DL, PtrVT,
2578  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2579  }
2580 
2581  return Result;
2582 }
2583 
2584 SDValue M68kTargetLowering::LowerGlobalAddress(const GlobalValue *GV,
2585  const SDLoc &DL, int64_t Offset,
2586  SelectionDAG &DAG) const {
2587  unsigned char OpFlags = Subtarget.classifyGlobalReference(GV);
2588  auto PtrVT = getPointerTy(DAG.getDataLayout());
2589 
2590  // Create the TargetGlobalAddress node, folding in the constant
2591  // offset if it is legal.
2592  SDValue Result;
2593  if (M68kII::isDirectGlobalReference(OpFlags)) {
2594  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
2595  Offset = 0;
2596  } else {
2597  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2598  }
2599 
2600  if (M68kII::isPCRelGlobalReference(OpFlags))
2601  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2602  else
2603  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2604 
2605  // With PIC, the address is actually $g + Offset.
2606  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2607  Result =
2608  DAG.getNode(ISD::ADD, DL, PtrVT,
2609  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2610  }
2611 
2612  // For globals that require a load from a stub to get the address, emit the
2613  // load.
2614  if (M68kII::isGlobalStubReference(OpFlags)) {
2615  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2617  }
2618 
2619  // If there was a non-zero offset that we didn't fold, create an explicit
2620  // addition for it.
2621  if (Offset != 0) {
2622  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2623  DAG.getConstant(Offset, DL, PtrVT));
2624  }
2625 
2626  return Result;
2627 }
2628 
2629 SDValue M68kTargetLowering::LowerGlobalAddress(SDValue Op,
2630  SelectionDAG &DAG) const {
2631  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2632  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2633  return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
2634 }
2635 
2636 //===----------------------------------------------------------------------===//
2637 // Custom Lower Jump Table
2638 //===----------------------------------------------------------------------===//
2639 
2640 SDValue M68kTargetLowering::LowerJumpTable(SDValue Op,
2641  SelectionDAG &DAG) const {
2642  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2643 
2644  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2645  // global base reg.
2646  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2647 
2648  unsigned WrapperKind = M68kISD::Wrapper;
2649  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2650  WrapperKind = M68kISD::WrapperPC;
2651  }
2652 
2653  auto PtrVT = getPointerTy(DAG.getDataLayout());
2654  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
2655  SDLoc DL(JT);
2656  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2657 
2658  // With PIC, the address is actually $g + Offset.
2659  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2660  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2661  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2662  Result);
2663  }
2664 
2665  return Result;
2666 }
2667 
2669  return Subtarget.getJumpTableEncoding();
2670 }
2671 
2673  const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
2674  unsigned uid, MCContext &Ctx) const {
2676  Ctx);
2677 }
2678 
2680  SelectionDAG &DAG) const {
2682  return DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(),
2683  getPointerTy(DAG.getDataLayout()));
2684 
2685  // MachineJumpTableInfo::EK_LabelDifference32 entry
2686  return Table;
2687 }
2688 
2689 // NOTE This only used for MachineJumpTableInfo::EK_LabelDifference32 entries
2691  const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const {
2692  return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
2693 }
2694 
2697  if (Constraint.size() > 0) {
2698  switch (Constraint[0]) {
2699  case 'a':
2700  case 'd':
2701  return C_RegisterClass;
2702  case 'I':
2703  case 'J':
2704  case 'K':
2705  case 'L':
2706  case 'M':
2707  case 'N':
2708  case 'O':
2709  case 'P':
2710  return C_Immediate;
2711  case 'C':
2712  if (Constraint.size() == 2)
2713  switch (Constraint[1]) {
2714  case '0':
2715  case 'i':
2716  case 'j':
2717  return C_Immediate;
2718  default:
2719  break;
2720  }
2721  break;
2722  default:
2723  break;
2724  }
2725  }
2726 
2727  return TargetLowering::getConstraintType(Constraint);
2728 }
2729 
2731  std::string &Constraint,
2732  std::vector<SDValue> &Ops,
2733  SelectionDAG &DAG) const {
2734  SDValue Result;
2735 
2736  if (Constraint.size() == 1) {
2737  // Constant constraints
2738  switch (Constraint[0]) {
2739  case 'I':
2740  case 'J':
2741  case 'K':
2742  case 'L':
2743  case 'M':
2744  case 'N':
2745  case 'O':
2746  case 'P': {
2747  auto *C = dyn_cast<ConstantSDNode>(Op);
2748  if (!C)
2749  return;
2750 
2751  int64_t Val = C->getSExtValue();
2752  switch (Constraint[0]) {
2753  case 'I': // constant integer in the range [1,8]
2754  if (Val > 0 && Val <= 8)
2755  break;
2756  return;
2757  case 'J': // constant signed 16-bit integer
2758  if (isInt<16>(Val))
2759  break;
2760  return;
2761  case 'K': // constant that is NOT in the range of [-0x80, 0x80)
2762  if (Val < -0x80 || Val >= 0x80)
2763  break;
2764  return;
2765  case 'L': // constant integer in the range [-8,-1]
2766  if (Val < 0 && Val >= -8)
2767  break;
2768  return;
2769  case 'M': // constant that is NOT in the range of [-0x100, 0x100]
2770  if (Val < -0x100 || Val >= 0x100)
2771  break;
2772  return;
2773  case 'N': // constant integer in the range [24,31]
2774  if (Val >= 24 && Val <= 31)
2775  break;
2776  return;
2777  case 'O': // constant integer 16
2778  if (Val == 16)
2779  break;
2780  return;
2781  case 'P': // constant integer in the range [8,15]
2782  if (Val >= 8 && Val <= 15)
2783  break;
2784  return;
2785  default:
2786  llvm_unreachable("Unhandled constant constraint");
2787  }
2788 
2789  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2790  break;
2791  }
2792  default:
2793  break;
2794  }
2795  }
2796 
2797  if (Constraint.size() == 2) {
2798  switch (Constraint[0]) {
2799  case 'C':
2800  // Constant constraints start with 'C'
2801  switch (Constraint[1]) {
2802  case '0':
2803  case 'i':
2804  case 'j': {
2805  auto *C = dyn_cast<ConstantSDNode>(Op);
2806  if (!C)
2807  break;
2808 
2809  int64_t Val = C->getSExtValue();
2810  switch (Constraint[1]) {
2811  case '0': // constant integer 0
2812  if (!Val)
2813  break;
2814  return;
2815  case 'i': // constant integer
2816  break;
2817  case 'j': // integer constant that doesn't fit in 16 bits
2818  if (!isInt<16>(C->getSExtValue()))
2819  break;
2820  return;
2821  default:
2822  llvm_unreachable("Unhandled constant constraint");
2823  }
2824 
2825  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2826  break;
2827  }
2828  default:
2829  break;
2830  }
2831  break;
2832  default:
2833  break;
2834  }
2835  }
2836 
2837  if (Result.getNode()) {
2838  Ops.push_back(Result);
2839  return;
2840  }
2841 
2842  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2843 }
2844 
2845 std::pair<unsigned, const TargetRegisterClass *>
2847  StringRef Constraint,
2848  MVT VT) const {
2849  if (Constraint.size() == 1) {
2850  switch (Constraint[0]) {
2851  case 'r':
2852  case 'd':
2853  switch (VT.SimpleTy) {
2854  case MVT::i8:
2855  return std::make_pair(0U, &M68k::DR8RegClass);
2856  case MVT::i16:
2857  return std::make_pair(0U, &M68k::DR16RegClass);
2858  case MVT::i32:
2859  return std::make_pair(0U, &M68k::DR32RegClass);
2860  default:
2861  break;
2862  }
2863  break;
2864  case 'a':
2865  switch (VT.SimpleTy) {
2866  case MVT::i16:
2867  return std::make_pair(0U, &M68k::AR16RegClass);
2868  case MVT::i32:
2869  return std::make_pair(0U, &M68k::AR32RegClass);
2870  default:
2871  break;
2872  }
2873  break;
2874  default:
2875  break;
2876  }
2877  }
2878 
2879  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2880 }
2881 
2882 /// Determines whether the callee is required to pop its own arguments.
2883 /// Callee pop is necessary to support tail calls.
2885  bool GuaranteeTCO) {
2886  return false;
2887 }
2888 
2889 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
2890 // together with other CMOV pseudo-opcodes into a single basic-block with
2891 // conditional jump around it.
2893  switch (MI.getOpcode()) {
2894  case M68k::CMOV8d:
2895  case M68k::CMOV16d:
2896  case M68k::CMOV32r:
2897  return true;
2898 
2899  default:
2900  return false;
2901  }
2902 }
2903 
2904 // The CCR operand of SelectItr might be missing a kill marker
2905 // because there were multiple uses of CCR, and ISel didn't know
2906 // which to mark. Figure out whether SelectItr should have had a
2907 // kill marker, and set it if it should. Returns the correct kill
2908 // marker value.
2911  const TargetRegisterInfo *TRI) {
2912  // Scan forward through BB for a use/def of CCR.
2913  MachineBasicBlock::iterator miI(std::next(SelectItr));
2914  for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
2915  const MachineInstr &mi = *miI;
2916  if (mi.readsRegister(M68k::CCR))
2917  return false;
2918  if (mi.definesRegister(M68k::CCR))
2919  break; // Should have kill-flag - update below.
2920  }
2921 
2922  // If we hit the end of the block, check whether CCR is live into a
2923  // successor.
2924  if (miI == BB->end())
2925  for (const auto *SBB : BB->successors())
2926  if (SBB->isLiveIn(M68k::CCR))
2927  return false;
2928 
2929  // We found a def, or hit the end of the basic block and CCR wasn't live
2930  // out. SelectMI should have a kill flag on CCR.
2931  SelectItr->addRegisterKilled(M68k::CCR, TRI);
2932  return true;
2933 }
2934 
2936 M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
2937  MachineBasicBlock *MBB) const {
2938  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2939  DebugLoc DL = MI.getDebugLoc();
2940 
2941  // To "insert" a SELECT_CC instruction, we actually have to insert the
2942  // diamond control-flow pattern. The incoming instruction knows the
2943  // destination vreg to set, the condition code register to branch on, the
2944  // true/false values to select between, and a branch opcode to use.
2945  const BasicBlock *BB = MBB->getBasicBlock();
2947 
2948  // ThisMBB:
2949  // ...
2950  // TrueVal = ...
2951  // cmp ccX, r1, r2
2952  // bcc Copy1MBB
2953  // fallthrough --> Copy0MBB
2954  MachineBasicBlock *ThisMBB = MBB;
2956 
2957  // This code lowers all pseudo-CMOV instructions. Generally it lowers these
2958  // as described above, by inserting a MBB, and then making a PHI at the join
2959  // point to select the true and false operands of the CMOV in the PHI.
2960  //
2961  // The code also handles two different cases of multiple CMOV opcodes
2962  // in a row.
2963  //
2964  // Case 1:
2965  // In this case, there are multiple CMOVs in a row, all which are based on
2966  // the same condition setting (or the exact opposite condition setting).
2967  // In this case we can lower all the CMOVs using a single inserted MBB, and
2968  // then make a number of PHIs at the join point to model the CMOVs. The only
2969  // trickiness here, is that in a case like:
2970  //
2971  // t2 = CMOV cond1 t1, f1
2972  // t3 = CMOV cond1 t2, f2
2973  //
2974  // when rewriting this into PHIs, we have to perform some renaming on the
2975  // temps since you cannot have a PHI operand refer to a PHI result earlier
2976  // in the same block. The "simple" but wrong lowering would be:
2977  //
2978  // t2 = PHI t1(BB1), f1(BB2)
2979  // t3 = PHI t2(BB1), f2(BB2)
2980  //
2981  // but clearly t2 is not defined in BB1, so that is incorrect. The proper
2982  // renaming is to note that on the path through BB1, t2 is really just a
2983  // copy of t1, and do that renaming, properly generating:
2984  //
2985  // t2 = PHI t1(BB1), f1(BB2)
2986  // t3 = PHI t1(BB1), f2(BB2)
2987  //
2988  // Case 2, we lower cascaded CMOVs such as
2989  //
2990  // (CMOV (CMOV F, T, cc1), T, cc2)
2991  //
2992  // to two successives branches.
2993  MachineInstr *CascadedCMOV = nullptr;
2994  MachineInstr *LastCMOV = &MI;
2995  M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
2997  MachineBasicBlock::iterator NextMIIt =
2998  std::next(MachineBasicBlock::iterator(MI));
2999 
3000  // Check for case 1, where there are multiple CMOVs with the same condition
3001  // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
3002  // number of jumps the most.
3003 
3004  if (isCMOVPseudo(MI)) {
3005  // See if we have a string of CMOVS with the same condition.
3006  while (NextMIIt != MBB->end() && isCMOVPseudo(*NextMIIt) &&
3007  (NextMIIt->getOperand(3).getImm() == CC ||
3008  NextMIIt->getOperand(3).getImm() == OppCC)) {
3009  LastCMOV = &*NextMIIt;
3010  ++NextMIIt;
3011  }
3012  }
3013 
3014  // This checks for case 2, but only do this if we didn't already find
3015  // case 1, as indicated by LastCMOV == MI.
3016  if (LastCMOV == &MI && NextMIIt != MBB->end() &&
3017  NextMIIt->getOpcode() == MI.getOpcode() &&
3018  NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
3019  NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
3020  NextMIIt->getOperand(1).isKill()) {
3021  CascadedCMOV = &*NextMIIt;
3022  }
3023 
3024  MachineBasicBlock *Jcc1MBB = nullptr;
3025 
3026  // If we have a cascaded CMOV, we lower it to two successive branches to
3027  // the same block. CCR is used by both, so mark it as live in the second.
3028  if (CascadedCMOV) {
3029  Jcc1MBB = F->CreateMachineBasicBlock(BB);
3030  F->insert(It, Jcc1MBB);
3031  Jcc1MBB->addLiveIn(M68k::CCR);
3032  }
3033 
3034  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(BB);
3035  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
3036  F->insert(It, Copy0MBB);
3037  F->insert(It, SinkMBB);
3038 
3039  // If the CCR register isn't dead in the terminator, then claim that it's
3040  // live into the sink and copy blocks.
3041  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3042 
3043  MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3044  if (!LastCCRSUser->killsRegister(M68k::CCR) &&
3045  !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) {
3046  Copy0MBB->addLiveIn(M68k::CCR);
3047  SinkMBB->addLiveIn(M68k::CCR);
3048  }
3049 
3050  // Transfer the remainder of MBB and its successor edges to SinkMBB.
3051  SinkMBB->splice(SinkMBB->begin(), MBB,
3052  std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
3054 
3055  // Add the true and fallthrough blocks as its successors.
3056  if (CascadedCMOV) {
3057  // The fallthrough block may be Jcc1MBB, if we have a cascaded CMOV.
3058  MBB->addSuccessor(Jcc1MBB);
3059 
3060  // In that case, Jcc1MBB will itself fallthrough the Copy0MBB, and
3061  // jump to the SinkMBB.
3062  Jcc1MBB->addSuccessor(Copy0MBB);
3063  Jcc1MBB->addSuccessor(SinkMBB);
3064  } else {
3065  MBB->addSuccessor(Copy0MBB);
3066  }
3067 
3068  // The true block target of the first (or only) branch is always SinkMBB.
3069  MBB->addSuccessor(SinkMBB);
3070 
3071  // Create the conditional branch instruction.
3072  unsigned Opc = M68k::GetCondBranchFromCond(CC);
3073  BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB);
3074 
3075  if (CascadedCMOV) {
3076  unsigned Opc2 = M68k::GetCondBranchFromCond(
3077  (M68k::CondCode)CascadedCMOV->getOperand(3).getImm());
3078  BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
3079  }
3080 
3081  // Copy0MBB:
3082  // %FalseValue = ...
3083  // # fallthrough to SinkMBB
3084  Copy0MBB->addSuccessor(SinkMBB);
3085 
3086  // SinkMBB:
3087  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
3088  // ...
3090  MachineBasicBlock::iterator MIItEnd =
3091  std::next(MachineBasicBlock::iterator(LastCMOV));
3092  MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
3094  MachineInstrBuilder MIB;
3095 
3096  // As we are creating the PHIs, we have to be careful if there is more than
3097  // one. Later CMOVs may reference the results of earlier CMOVs, but later
3098  // PHIs have to reference the individual true/false inputs from earlier PHIs.
3099  // That also means that PHI construction must work forward from earlier to
3100  // later, and that the code must maintain a mapping from earlier PHI's
3101  // destination registers, and the registers that went into the PHI.
3102 
3103  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
3104  unsigned DestReg = MIIt->getOperand(0).getReg();
3105  unsigned Op1Reg = MIIt->getOperand(1).getReg();
3106  unsigned Op2Reg = MIIt->getOperand(2).getReg();
3107 
3108  // If this CMOV we are generating is the opposite condition from
3109  // the jump we generated, then we have to swap the operands for the
3110  // PHI that is going to be generated.
3111  if (MIIt->getOperand(3).getImm() == OppCC)
3112  std::swap(Op1Reg, Op2Reg);
3113 
3114  if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
3115  Op1Reg = RegRewriteTable[Op1Reg].first;
3116 
3117  if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
3118  Op2Reg = RegRewriteTable[Op2Reg].second;
3119 
3120  MIB =
3121  BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg)
3122  .addReg(Op1Reg)
3123  .addMBB(Copy0MBB)
3124  .addReg(Op2Reg)
3125  .addMBB(ThisMBB);
3126 
3127  // Add this PHI to the rewrite table.
3128  RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3129  }
3130 
3131  // If we have a cascaded CMOV, the second Jcc provides the same incoming
3132  // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
3133  if (CascadedCMOV) {
3134  MIB.addReg(MI.getOperand(2).getReg()).addMBB(Jcc1MBB);
3135  // Copy the PHI result to the register defined by the second CMOV.
3136  BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
3137  DL, TII->get(TargetOpcode::COPY),
3138  CascadedCMOV->getOperand(0).getReg())
3139  .addReg(MI.getOperand(0).getReg());
3140  CascadedCMOV->eraseFromParent();
3141  }
3142 
3143  // Now remove the CMOV(s).
3144  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;)
3145  (MIIt++)->eraseFromParent();
3146 
3147  return SinkMBB;
3148 }
3149 
3151 M68kTargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
3152  MachineBasicBlock *BB) const {
3153  llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on");
3154 }
3155 
3158  MachineBasicBlock *BB) const {
3159  switch (MI.getOpcode()) {
3160  default:
3161  llvm_unreachable("Unexpected instr type to insert");
3162  case M68k::CMOV8d:
3163  case M68k::CMOV16d:
3164  case M68k::CMOV32r:
3165  return EmitLoweredSelect(MI, BB);
3166  case M68k::SALLOCA:
3167  return EmitLoweredSegAlloca(MI, BB);
3168  }
3169 }
3170 
3171 SDValue M68kTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3172  MachineFunction &MF = DAG.getMachineFunction();
3173  auto PtrVT = getPointerTy(MF.getDataLayout());
3175 
3176  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3177  SDLoc DL(Op);
3178 
3179  // vastart just stores the address of the VarArgsFrameIndex slot into the
3180  // memory location argument.
3181  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3182  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3183  MachinePointerInfo(SV));
3184 }
3185 
3186 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3187 // Calls to _alloca are needed to probe the stack when allocating more than 4k
3188 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3189 // that the guard pages used by the OS virtual memory manager are allocated in
3190 // correct sequence.
3191 SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3192  SelectionDAG &DAG) const {
3193  MachineFunction &MF = DAG.getMachineFunction();
3194  bool SplitStack = MF.shouldSplitStack();
3195 
3196  SDLoc DL(Op);
3197 
3198  // Get the inputs.
3199  SDNode *Node = Op.getNode();
3200  SDValue Chain = Op.getOperand(0);
3201  SDValue Size = Op.getOperand(1);
3202  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3203  EVT VT = Node->getValueType(0);
3204 
3205  // Chain the dynamic stack allocation so that it doesn't modify the stack
3206  // pointer when other instructions are using the stack.
3207  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3208 
3209  SDValue Result;
3210  if (SplitStack) {
3211  auto &MRI = MF.getRegInfo();
3212  auto SPTy = getPointerTy(DAG.getDataLayout());
3213  auto *ARClass = getRegClassFor(SPTy);
3214  unsigned Vreg = MRI.createVirtualRegister(ARClass);
3215  Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
3216  Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
3217  DAG.getRegister(Vreg, SPTy));
3218  } else {
3219  auto &TLI = DAG.getTargetLoweringInfo();
3220  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
3221  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3222  " not tell us which reg is the stack pointer!");
3223 
3224  SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3225  Chain = SP.getValue(1);
3226  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3227  unsigned StackAlign = TFI.getStackAlignment();
3228  Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value
3229  if (Align > StackAlign)
3230  Result = DAG.getNode(ISD::AND, DL, VT, Result,
3231  DAG.getConstant(-(uint64_t)Align, DL, VT));
3232  Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
3233  }
3234 
3235  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
3236  DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
3237 
3238  SDValue Ops[2] = {Result, Chain};
3239  return DAG.getMergeValues(Ops, DL);
3240 }
3241 
3242 //===----------------------------------------------------------------------===//
3243 // DAG Combine
3244 //===----------------------------------------------------------------------===//
3245 
3247  SelectionDAG &DAG) {
3248  return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
3249  DAG.getConstant(Cond, dl, MVT::i8), CCR);
3250 }
3251 // When legalizing carry, we create carries via add X, -1
3252 // If that comes from an actual carry, via setcc, we use the
3253 // carry directly.
3255  if (CCR.getOpcode() == M68kISD::ADD) {
3256  if (isAllOnesConstant(CCR.getOperand(1))) {
3257  SDValue Carry = CCR.getOperand(0);
3258  while (Carry.getOpcode() == ISD::TRUNCATE ||
3259  Carry.getOpcode() == ISD::ZERO_EXTEND ||
3260  Carry.getOpcode() == ISD::SIGN_EXTEND ||
3261  Carry.getOpcode() == ISD::ANY_EXTEND ||
3262  (Carry.getOpcode() == ISD::AND &&
3263  isOneConstant(Carry.getOperand(1))))
3264  Carry = Carry.getOperand(0);
3265  if (Carry.getOpcode() == M68kISD::SETCC ||
3266  Carry.getOpcode() == M68kISD::SETCC_CARRY) {
3267  if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
3268  return Carry.getOperand(1);
3269  }
3270  }
3271  }
3272 
3273  return SDValue();
3274 }
3275 
3276 /// Optimize a CCR definition used according to the condition code \p CC into
3277 /// a simpler CCR value, potentially returning a new \p CC and replacing uses
3278 /// of chain values.
3280  SelectionDAG &DAG,
3281  const M68kSubtarget &Subtarget) {
3282  if (CC == M68k::COND_CS)
3283  if (SDValue Flags = combineCarryThroughADD(CCR))
3284  return Flags;
3285 
3286  return SDValue();
3287 }
3288 
3289 // Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
3291  const M68kSubtarget &Subtarget) {
3292  SDLoc DL(N);
3293  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3294  SDValue CCR = N->getOperand(1);
3295 
3296  // Try to simplify the CCR and condition code operands.
3297  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3298  return getSETCC(CC, Flags, DL, DAG);
3299 
3300  return SDValue();
3301 }
3303  const M68kSubtarget &Subtarget) {
3304  SDLoc DL(N);
3305  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3306  SDValue CCR = N->getOperand(3);
3307 
3308  // Try to simplify the CCR and condition code operands.
3309  // Make sure to not keep references to operands, as combineSetCCCCR can
3310  // RAUW them under us.
3311  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3312  SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3313  return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
3314  N->getOperand(1), Cond, Flags);
3315  }
3316 
3317  return SDValue();
3318 }
3319 
3321  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3322  MVT VT = N->getSimpleValueType(0);
3323  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3324  return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
3325  N->getOperand(1), Flags);
3326  }
3327 
3328  return SDValue();
3329 }
3330 
3331 // Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
3334  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3335  MVT VT = N->getSimpleValueType(0);
3336  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3337  return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
3338  N->getOperand(1), Flags);
3339  }
3340 
3341  return SDValue();
3342 }
3343 
3344 SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
3345  DAGCombinerInfo &DCI) const {
3346  SelectionDAG &DAG = DCI.DAG;
3347  switch (N->getOpcode()) {
3348  case M68kISD::SUBX:
3349  return combineSUBX(N, DAG);
3350  case M68kISD::ADDX:
3351  return combineADDX(N, DAG, DCI);
3352  case M68kISD::SETCC:
3353  return combineM68kSetCC(N, DAG, Subtarget);
3354  case M68kISD::BRCOND:
3355  return combineM68kBrCond(N, DAG, Subtarget);
3356  }
3357 
3358  return SDValue();
3359 }
3360 
3361 //===----------------------------------------------------------------------===//
3362 // M68kISD Node Names
3363 //===----------------------------------------------------------------------===//
3364 const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
3365  switch (Opcode) {
3366  case M68kISD::CALL:
3367  return "M68kISD::CALL";
3368  case M68kISD::TAIL_CALL:
3369  return "M68kISD::TAIL_CALL";
3370  case M68kISD::RET:
3371  return "M68kISD::RET";
3372  case M68kISD::TC_RETURN:
3373  return "M68kISD::TC_RETURN";
3374  case M68kISD::ADD:
3375  return "M68kISD::ADD";
3376  case M68kISD::SUB:
3377  return "M68kISD::SUB";
3378  case M68kISD::ADDX:
3379  return "M68kISD::ADDX";
3380  case M68kISD::SUBX:
3381  return "M68kISD::SUBX";
3382  case M68kISD::SMUL:
3383  return "M68kISD::SMUL";
3384  case M68kISD::UMUL:
3385  return "M68kISD::UMUL";
3386  case M68kISD::OR:
3387  return "M68kISD::OR";
3388  case M68kISD::XOR:
3389  return "M68kISD::XOR";
3390  case M68kISD::AND:
3391  return "M68kISD::AND";
3392  case M68kISD::CMP:
3393  return "M68kISD::CMP";
3394  case M68kISD::BT:
3395  return "M68kISD::BT";
3396  case M68kISD::SELECT:
3397  return "M68kISD::SELECT";
3398  case M68kISD::CMOV:
3399  return "M68kISD::CMOV";
3400  case M68kISD::BRCOND:
3401  return "M68kISD::BRCOND";
3402  case M68kISD::SETCC:
3403  return "M68kISD::SETCC";
3404  case M68kISD::SETCC_CARRY:
3405  return "M68kISD::SETCC_CARRY";
3407  return "M68kISD::GLOBAL_BASE_REG";
3408  case M68kISD::Wrapper:
3409  return "M68kISD::Wrapper";
3410  case M68kISD::WrapperPC:
3411  return "M68kISD::WrapperPC";
3412  case M68kISD::SEG_ALLOCA:
3413  return "M68kISD::SEG_ALLOCA";
3414  default:
3415  return NULL;
3416  }
3417 }
3418 
3420  bool IsVarArg) const {
3421  if (Return)
3422  return RetCC_M68k_C;
3423  else
3424  return CC_M68k_C;
3425 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::ArgFlagsTy::isInAlloca
bool isInAlloca() const
Definition: TargetCallingConv.h:91
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1368
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
llvm::MachineFrameInfo::isObjectZExt
bool isObjectZExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:502
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1556
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:710
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
llvm::M68kTargetLowering::getCCAssignFn
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: M68kISelLowering.cpp:3419
llvm::M68kTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: M68kISelLowering.cpp:2846
llvm::M68kISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: M68kISelLowering.h:87
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1738
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:923
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1379
TranslateIntegerM68kCC
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
Definition: M68kISelLowering.cpp:1484
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::M68kTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: M68kISelLowering.cpp:2672
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:319
llvm::M68kISD::SUBX
@ SUBX
Definition: M68kISelLowering.h:75
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::M68kISD::BRCOND
@ BRCOND
M68k conditional branches.
Definition: M68kISelLowering.h:69
llvm::M68kTargetMachine
Definition: M68kTargetMachine.h:29
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::M68kMachineFunctionInfo::setArgumentStackSize
void setArgumentStackSize(unsigned size)
Definition: M68kMachineFunction.h:102
llvm::ISD::ArgFlagsTy::isSRet
bool isSRet() const
Definition: TargetCallingConv.h:82
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:213
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::TargetLowering::CallLoweringInfo::RetTy
Type * RetTy
Definition: TargetLowering.h:3749
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:772
M68kTargetMachine.h
llvm::M68kISD::SETCC
@ SETCC
M68k SetCC.
Definition: M68kISelLowering.h:53
llvm::M68k::CondCode
CondCode
Definition: M68kInstrInfo.h:34
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:197
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::MVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: MachineValueType.h:350
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:435
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1376
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:848
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1380
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4157
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:946
llvm::M68kTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: M68kISelLowering.cpp:3157
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:735
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::isOneConstant
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Definition: SelectionDAG.cpp:9946
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::M68kISD::SELECT
@ SELECT
M68k Select.
Definition: M68kISelLowering.h:49
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:666
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:311
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:931
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1722
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::M68k::COND_PL
@ COND_PL
Definition: M68kInstrInfo.h:45
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1603
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1375
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1012
llvm::M68kISD::ADD
@ ADD
Definition: M68kISelLowering.h:72
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:8551
TranslateM68kCC
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
Definition: M68kISelLowering.cpp:1514
llvm::M68k::COND_GT
@ COND_GT
Definition: M68kInstrInfo.h:49
llvm::ISD::GlobalISel::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:481
ErrorHandling.h
llvm::M68kCCState
Custom state to propagate llvm type info to register CC assigner.
Definition: M68kCallingConv.h:27
llvm::isBitwiseNot
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
Definition: SelectionDAG.cpp:9969
llvm::M68k::COND_NE
@ COND_NE
Definition: M68kInstrInfo.h:41
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SelectionDAG::ReplaceAllUsesWith
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
Definition: SelectionDAG.cpp:9423
llvm::M68kII::isPCRelBlockReference
static bool isPCRelBlockReference(unsigned char Flag)
Return True if the Block is referenced using PC.
Definition: M68kBaseInfo.h:167
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::CCValAssign::Indirect
@ Indirect
Definition: CallingConvLower.h:52
LowerAndToBT
static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BT node if possible.
Definition: M68kISelLowering.cpp:1436
llvm::M68kRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: M68kRegisterInfo.h:100
llvm::SDNode::use_iterator
This class provides iterator support for SDUse operands that use a specific SDNode.
Definition: SelectionDAGNodes.h:727
llvm::M68kRegisterInfo
Definition: M68kRegisterInfo.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1370
MachineJumpTableInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7512
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:702
isXor1OfSetCC
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
Definition: M68kISelLowering.cpp:2235
llvm::CallBase::isMustTailCall
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: Instructions.cpp:298
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:3774
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2301
llvm::M68kII::isDirectGlobalReference
static bool isDirectGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue is a direct reference for a symbol.
Definition: M68kBaseInfo.h:131
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
hasNonFlagsUse
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
Definition: M68kISelLowering.cpp:1610
llvm::M68k::COND_VS
@ COND_VS
Definition: M68kInstrInfo.h:44
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1041
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1335
llvm::MachineFunction::getJTISymbol
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
Definition: MachineFunction.cpp:678
llvm::M68kSubtarget::getRegisterInfo
const M68kRegisterInfo * getRegisterInfo() const override
Definition: M68kSubtarget.h:155
llvm::MCSymbolRefExpr::VK_GOTOFF
@ VK_GOTOFF
Definition: MCExpr.h:199
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1358
llvm::EVT::bitsLE
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:281
llvm::M68kMachineFunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: M68kMachineFunction.h:104
llvm::M68kISD::CALL
@ CALL
Definition: M68kISelLowering.h:35
SelectionDAG.h
llvm::MachineJumpTableInfo::EK_Custom32
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Definition: MachineJumpTableInfo.h:76
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1366
combineCarryThroughADD
static SDValue combineCarryThroughADD(SDValue CCR)
Definition: M68kISelLowering.cpp:3254
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
llvm::M68k::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: M68kISelLowering.cpp:2884
llvm::M68kTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: M68kISelLowering.cpp:2668
F
#define F(x, y, z)
Definition: MD5.cpp:56
M68kTargetObjectFile.h
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:956
MachineRegisterInfo.h
KnownBits.h
llvm::M68kTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: M68kISelLowering.cpp:2690
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1985
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:130
llvm::M68kII::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Return true if the specified TargetFlag operand is a reference to a stub for a global,...
Definition: M68kBaseInfo.h:119
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1411
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:746
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:60
shouldGuaranteeTCO
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
Definition: M68kISelLowering.cpp:237
CommandLine.h
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:963
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7462
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:95
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3752
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::M68kSubtarget::classifyBlockAddressReference
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
Definition: M68kSubtarget.cpp:147
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:694
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2174
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:156
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1121
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:59
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition: M68kSubtarget.h:149
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:679
llvm::SelectionDAG::UpdateNodeOperands
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
Definition: SelectionDAG.cpp:8641
llvm::SDNode::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: SelectionDAGNodes.h:700
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:730
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1377
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::User
Definition: User.h:44
llvm::M68kISD::AND
@ AND
Definition: M68kISelLowering.h:80
llvm::M68kTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: M68kISelLowering.cpp:2679
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:443
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
NotStructReturn
@ NotStructReturn
Definition: M68kISelLowering.cpp:178
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1373
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1821
llvm::M68k::COND_GE
@ COND_GE
Definition: M68kInstrInfo.h:47
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
isAndOrOfSetCCs
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
Definition: M68kISelLowering.cpp:2223
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
Definition: SelectionDAG.cpp:2463
StackStructReturn
@ StackStructReturn
Definition: M68kISelLowering.cpp:178
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3544
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:216
llvm::M68kMachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(unsigned Reg)
Definition: M68kMachineFunction.h:99
llvm::BitTracker
Definition: BitTracker.h:35
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1012
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2181
argsAreStructReturn
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
Definition: M68kISelLowering.cpp:195
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:652
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::TargetLowering::CallLoweringInfo::DoesNotReturn
bool DoesNotReturn
Definition: TargetLowering.h:3754
combineM68kSetCC
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3290
llvm::M68kMachineFunctionInfo::setTCReturnAddrDelta
void setTCReturnAddrDelta(int delta)
Definition: M68kMachineFunction.h:87
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:281
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:280
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1744
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4161
M68kISelLowering.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:318
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1361
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:656
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:1218
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1398
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:1133
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::SDValue::getValueSizeInBits
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
Definition: SelectionDAGNodes.h:192
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1389
RegStructReturn
@ RegStructReturn
Definition: M68kISelLowering.cpp:178
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:315
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1362
llvm::M68kMachineFunctionInfo::getSRetReturnReg
unsigned getSRetReturnReg() const
Definition: M68kMachineFunction.h:98
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1367
llvm::MVT::getScalarType
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
Definition: MachineValueType.h:515
llvm::M68kISD::TC_RETURN
@ TC_RETURN
Definition: M68kISelLowering.h:38
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:683
llvm::M68kTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: M68kISelLowering.cpp:2730
checkAndUpdateCCRKill
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
Definition: M68kISelLowering.cpp:2909
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: MachineValueType.h:340
llvm::M68kTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: M68kISelLowering.cpp:1318
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::M68kISD::XOR
@ XOR
Definition: M68kISelLowering.h:79
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::M68kISD::CMOV
@ CMOV
M68k conditional moves.
Definition: M68kISelLowering.h:63
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:3775
llvm::M68kISD::SUB
@ SUB
Definition: M68kISelLowering.h:73
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1371
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2198
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:310
llvm::TargetLowering::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: TargetLowering.h:3901
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::M68k::COND_HI
@ COND_HI
Definition: M68kInstrInfo.h:37
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::M68kISD::SMUL
@ SMUL
Definition: M68kISelLowering.h:76
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:895
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:572
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:3748
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1496
llvm::M68kMachineFunctionInfo::getRAIndex
int getRAIndex() const
Definition: M68kMachineFunction.h:83
llvm::M68kISD::TAIL_CALL
@ TAIL_CALL
Definition: M68kISelLowering.h:37
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:198
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:167
getBitTestCondition
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BT (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal co...
Definition: M68kISelLowering.cpp:1414
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::M68kII::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Return true if the specified global value reference is relative to a 32-bit PIC base (M68kISD::GLOBAL...
Definition: M68kBaseInfo.h:145
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:761
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:3769
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2147
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:904
llvm::M68k::GetCondBranchFromCond
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
Definition: M68kInstrInfo.h:97
llvm::FrameIndexSDNode::getIndex
int getIndex() const
Definition: SelectionDAGNodes.h:1755
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8316
combineM68kBrCond
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3302
MatchingStackOffset
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const M68kInstrInfo *TII, const CCValAssign &VA)
Return true if the given stack call argument is already available in the same position (relatively) o...
Definition: M68kISelLowering.cpp:243
llvm::SelectionDAG::getNOT
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
Definition: SelectionDAG.cpp:1349
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:3773
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: M68kISelLowering.cpp:225
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:652
llvm::Log2_64_Ceil
unsigned Log2_64_Ceil(uint64_t Value)
Return the ceil log base 2 of the specified value, 64 if the value is zero.
Definition: MathExtras.h:615
llvm::M68k::COND_INVALID
@ COND_INVALID
Definition: M68kInstrInfo.h:52
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::M68kII::isPCRelGlobalReference
static bool isPCRelGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue requires PC addressing mode.
Definition: M68kBaseInfo.h:156
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:607
llvm::M68kSubtarget::getFrameLowering
const M68kFrameLowering * getFrameLowering() const override
Definition: M68kSubtarget.h:151
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1335
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1359
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3747
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:615
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
llvm::M68k::COND_LT
@ COND_LT
Definition: M68kInstrInfo.h:48
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1369
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
M68kCallingConv.h
llvm::M68k::COND_CC
@ COND_CC
Definition: M68kInstrInfo.h:39
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1355
llvm::Value::use_begin
use_iterator use_begin()
Definition: Value.h:361
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2088
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::isNON_EXTLoad
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
Definition: SelectionDAGNodes.h:2901
llvm::M68kISD::SETCC_CARRY
@ SETCC_CARRY
Definition: M68kISelLowering.h:57
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::M68k::COND_VC
@ COND_VC
Definition: M68kInstrInfo.h:43
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
OP
#define OP(n)
Definition: regex2.h:73
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
Definition: SelectionDAG.cpp:2206
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1042
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1368
combineSUBX
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:3320
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: M68kISelLowering.cpp:222
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:935
llvm::CCState::resultsCompatible
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
Definition: CallingConvLower.cpp:266
isM68kLogicalCmp
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
Definition: M68kISelLowering.cpp:1994
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:653
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:3777
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:142
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3772
llvm::M68kMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: M68kMachineFunction.h:93
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:699
callIsStructReturn
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
Definition: M68kISelLowering.cpp:181
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:100
llvm::M68kISD::ADDX
@ ADDX
Definition: M68kISelLowering.h:74
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::M68kISD::RET
@ RET
Definition: M68kISelLowering.h:36
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:155
llvm::CallingConv::M68k_INTR
@ M68k_INTR
M68k_INTR - Calling convention used for M68k interrupt routines.
Definition: CallingConv.h:253
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1842
llvm::M68kTargetLowering::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: M68kISelLowering.cpp:168
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4518
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:353
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
LowerTruncateToBT
static SDValue LowerTruncateToBT(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:1595
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::M68kMachineFunctionInfo
Definition: M68kMachineFunction.h:23
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1129
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SDValue::hasOneUse
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Definition: SelectionDAGNodes.h:1165
llvm::M68kSubtarget::getSlotSize
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
Definition: M68kSubtarget.h:139
llvm::HexagonInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Definition: HexagonInstrInfo.cpp:245
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:4597
llvm::M68kSubtarget::classifyGlobalFunctionReference
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
Definition: M68kSubtarget.cpp:243
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2218
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:183
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::MachineFrameInfo::isObjectSExt
bool isObjectSExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:514
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1335
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::M68kISD::WrapperPC
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
Definition: M68kISelLowering.h:91
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4159
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:634
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:693
llvm::M68kInstrInfo
Definition: M68kInstrInfo.h:237
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:339
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:3763
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1378
llvm::M68k::COND_LS
@ COND_LS
Definition: M68kInstrInfo.h:38
llvm::isAllOnesConstant
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
Definition: SelectionDAG.cpp:9941
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:146
llvm::M68kSubtarget::classifyLocalReference
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
Definition: M68kSubtarget.cpp:153
llvm::M68kMachineFunctionInfo::setBytesToPopOnReturn
void setBytesToPopOnReturn(unsigned bytes)
Definition: M68kMachineFunction.h:81
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2757
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2206
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1718
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::M68kTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: M68kISelLowering.cpp:3364
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:9931
llvm::M68k::IsSETCC
static bool IsSETCC(unsigned SETCC)
Definition: M68kInstrInfo.h:185
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:83
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:937
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::M68kMachineFunctionInfo::setRAIndex
void setRAIndex(int Index)
Definition: M68kMachineFunction.h:84
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:516
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
Definition: SelectionDAG.cpp:454
GlobalVariable.h
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::MachineFrameInfo::setObjectSExt
void setObjectSExt(int ObjectIdx, bool IsSExt)
Definition: MachineFrameInfo.h:520
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
M68kMachineFunction.h
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:201
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1753
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:385
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:233
llvm::M68k::COND_MI
@ COND_MI
Definition: M68kInstrInfo.h:46
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:922
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1037
llvm::M68kISD::CMP
@ CMP
M68k compare and logical compare instructions.
Definition: M68kISelLowering.h:43
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
combineADDX
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: M68kISelLowering.cpp:3332
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:314
llvm::M68kTargetLowering::M68kTargetLowering
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
Definition: M68kISelLowering.cpp:46
llvm::M68kMachineFunctionInfo::getBytesToPopOnReturn
unsigned getBytesToPopOnReturn() const
Definition: M68kMachineFunction.h:80
llvm::M68kRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: M68kRegisterInfo.cpp:64
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:301
isCMOVPseudo
static bool isCMOVPseudo(MachineInstr &MI)
Definition: M68kISelLowering.cpp:2892
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2115
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1360
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
isM68kCCUnsigned
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
Definition: M68kISelLowering.cpp:1844
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::TargetLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: TargetLowering.cpp:80
MachineInstrBuilder.h
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:199
llvm::M68kISD::OR
@ OR
Definition: M68kISelLowering.h:78
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::M68kSubtarget::getJumpTableEncoding
unsigned getJumpTableEncoding() const
Definition: M68kSubtarget.cpp:221
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1285
combineSetCCCCR
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Optimize a CCR definition used according to the condition code CC into a simpler CCR value,...
Definition: M68kISelLowering.cpp:3279
llvm::M68k::COND_EQ
@ COND_EQ
Definition: M68kInstrInfo.h:42
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::M68kTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: M68kISelLowering.cpp:162
M68kSubtarget.h
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2000
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:667
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:852
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:259
llvm::M68kTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
Definition: M68kISelLowering.cpp:2696
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
CreateCopyOfByValArgument
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &DL)
Make a copy of an aggregate at address specified by "Src" to address "Dst" with size and alignment in...
Definition: M68kISelLowering.cpp:210
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:614
llvm::CallingConv::Swift
@ Swift
Definition: CallingConv.h:73
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:3776
llvm::M68kII::MO_GOTPCREL
@ MO_GOTPCREL
On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...
Definition: M68kBaseInfo.h:108
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:885
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:668
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:1117
llvm::ISD::ArgFlagsTy::isInReg
bool isInReg() const
Definition: TargetCallingConv.h:79
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:637
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1363
llvm::TargetLowering::CallLoweringInfo::Callee
SDValue Callee
Definition: TargetLowering.h:3770
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::M68kMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex() const
Definition: M68kMachineFunction.h:92
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1032
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::M68kISD::BT
@ BT
M68k bit-test instructions.
Definition: M68kISelLowering.h:46
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
StructReturnType
StructReturnType
Definition: M68kISelLowering.cpp:178
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
Mod
Module * Mod
Definition: PassBuilderBindings.cpp:54
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::M68kISD::SEG_ALLOCA
@ SEG_ALLOCA
Definition: M68kISelLowering.h:96
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
raw_ostream.h
isTruncWithZeroHighBitsInput
static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:2010
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:6837
llvm::M68kSubtarget::atLeastM68020
bool atLeastM68020() const
Definition: M68kSubtarget.h:87
llvm::StringRef::size
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
MachineFunction.h
llvm::MachineFrameInfo::setObjectZExt
void setObjectZExt(int ObjectIdx, bool IsZExt)
Definition: MachineFrameInfo.h:508
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
llvm::SelectionDAG::getStackArgumentTokenFactor
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
Definition: SelectionDAG.cpp:6244
llvm::M68kSubtarget::classifyExternalReference
unsigned char classifyExternalReference(const Module &M) const
Classify a external variable reference for the current subtarget according to how we should reference...
Definition: M68kSubtarget.cpp:180
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1008
llvm::ISD::ADDE
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:441
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::M68k::COND_CS
@ COND_CS
Definition: M68kInstrInfo.h:40
llvm::M68k::COND_LE
@ COND_LE
Definition: M68kInstrInfo.h:50
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
getSETCC
static SDValue getSETCC(M68k::CondCode Cond, SDValue CCR, const SDLoc &dl, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:3246
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4457
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:669
llvm::M68kISD::UMUL
@ UMUL
Definition: M68kISelLowering.h:77
llvm::SelectionDAG::getSetCC
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
Definition: SelectionDAG.h:1058
llvm::TargetLoweringBase::LibCall
@ LibCall
Definition: TargetLowering.h:200
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:7228
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1158
llvm::M68kSubtarget::classifyGlobalReference
unsigned char classifyGlobalReference(const GlobalValue *GV, const Module &M) const
Classify a global variable reference for the current subtarget according to how we should reference i...
Definition: M68kSubtarget.cpp:195
llvm::M68k::GetOppositeBranchCondition
static M68k::CondCode GetOppositeBranchCondition(M68k::CondCode CC)
Definition: M68kInstrInfo.h:58