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M68kISelLowering.cpp
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1 //===-- M68kISelLowering.cpp - M68k DAG Lowering Impl -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that M68k uses to lower LLVM code into a
11 /// selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "M68kISelLowering.h"
16 #include "M68kCallingConv.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kSubtarget.h"
19 #include "M68kTargetMachine.h"
20 #include "M68kTargetObjectFile.h"
21 
22 #include "llvm/ADT/Statistic.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/KnownBits.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "M68k-isel"
43 
44 STATISTIC(NumTailCalls, "Number of tail calls");
45 
47  const M68kSubtarget &STI)
48  : TargetLowering(TM), Subtarget(STI), TM(TM) {
49 
50  MVT PtrVT = MVT::i32;
51 
53 
54  auto *RegInfo = Subtarget.getRegisterInfo();
55  setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
56 
57  // Set up the register classes.
58  addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59  addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60  addRegisterClass(MVT::i32, &M68k::XR32RegClass);
61 
62  for (auto VT : MVT::integer_valuetypes()) {
66  }
67 
68  // We don't accept any truncstore of integer registers.
75 
78  if (Subtarget.atLeastM68020())
80  else
83 
84  for (auto OP :
90  }
91 
92  for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
95  }
96 
97  // FIXME It would be better to use a custom lowering
98  for (auto OP : {ISD::SMULO, ISD::UMULO}) {
102  }
103 
106 
107  // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
108  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
113  }
114 
115  // SADDO and friends are legal with this setup, i hope
116  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
121  }
122 
125 
126  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
132  }
133 
134  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
139  }
140 
147 
152 
155 
157 
159 
160  // 2^2 bytes
161  // FIXME can it be just 2^1?
162  setMinFunctionAlignment(Align::Constant<2>());
163 }
164 
166  LLVMContext &Context, EVT VT) const {
167  // M68k SETcc producess either 0x00 or 0xFF
168  return MVT::i8;
169 }
170 
172  EVT Ty) const {
173  if (Ty.isSimple()) {
174  return Ty.getSimpleVT();
175  }
176  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
177 }
178 
179 #include "M68kGenCallingConv.inc"
180 
182 
183 static StructReturnType
185  if (Outs.empty())
186  return NotStructReturn;
187 
188  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
189  if (!Flags.isSRet())
190  return NotStructReturn;
191  if (Flags.isInReg())
192  return RegStructReturn;
193  return StackStructReturn;
194 }
195 
196 /// Determines whether a function uses struct return semantics.
197 static StructReturnType
199  if (Ins.empty())
200  return NotStructReturn;
201 
202  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
203  if (!Flags.isSRet())
204  return NotStructReturn;
205  if (Flags.isInReg())
206  return RegStructReturn;
207  return StackStructReturn;
208 }
209 
210 /// Make a copy of an aggregate at address specified by "Src" to address
211 /// "Dst" with size and alignment information specified by the specific
212 /// parameter attribute. The copy will be passed as a byval function parameter.
214  SDValue Chain, ISD::ArgFlagsTy Flags,
215  SelectionDAG &DAG, const SDLoc &DL) {
216  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
217 
218  return DAG.getMemcpy(
219  Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
220  /*isVolatile=*/false, /*AlwaysInline=*/true,
221  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
222 }
223 
224 /// Return true if the calling convention is one that we can guarantee TCO for.
225 static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
226 
227 /// Return true if we might ever do TCO for calls with this calling convention.
229  switch (CC) {
230  // C calling conventions:
231  case CallingConv::C:
232  return true;
233  default:
234  return canGuaranteeTCO(CC);
235  }
236 }
237 
238 /// Return true if the function is being made into a tailcall target by
239 /// changing its ABI.
240 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
241  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
242 }
243 
244 /// Return true if the given stack call argument is already available in the
245 /// same position (relatively) of the caller's incoming argument stack.
246 static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
247  ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI,
248  const MachineRegisterInfo *MRI,
249  const M68kInstrInfo *TII,
250  const CCValAssign &VA) {
251  unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
252 
253  for (;;) {
254  // Look through nodes that don't alter the bits of the incoming value.
255  unsigned Op = Arg.getOpcode();
256  if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
257  Arg = Arg.getOperand(0);
258  continue;
259  }
260  if (Op == ISD::TRUNCATE) {
261  const SDValue &TruncInput = Arg.getOperand(0);
262  if (TruncInput.getOpcode() == ISD::AssertZext &&
263  cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
264  Arg.getValueType()) {
265  Arg = TruncInput.getOperand(0);
266  continue;
267  }
268  }
269  break;
270  }
271 
272  int FI = INT_MAX;
273  if (Arg.getOpcode() == ISD::CopyFromReg) {
274  Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
276  return false;
277  MachineInstr *Def = MRI->getVRegDef(VR);
278  if (!Def)
279  return false;
280  if (!Flags.isByVal()) {
281  if (!TII->isLoadFromStackSlot(*Def, FI))
282  return false;
283  } else {
284  unsigned Opcode = Def->getOpcode();
285  if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
286  Def->getOperand(1).isFI()) {
287  FI = Def->getOperand(1).getIndex();
288  Bytes = Flags.getByValSize();
289  } else
290  return false;
291  }
292  } else if (auto *Ld = dyn_cast<LoadSDNode>(Arg)) {
293  if (Flags.isByVal())
294  // ByVal argument is passed in as a pointer but it's now being
295  // dereferenced. e.g.
296  // define @foo(%struct.X* %A) {
297  // tail call @bar(%struct.X* byval %A)
298  // }
299  return false;
300  SDValue Ptr = Ld->getBasePtr();
301  FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
302  if (!FINode)
303  return false;
304  FI = FINode->getIndex();
305  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
306  FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
307  FI = FINode->getIndex();
308  Bytes = Flags.getByValSize();
309  } else
310  return false;
311 
312  assert(FI != INT_MAX);
313  if (!MFI.isFixedObjectIndex(FI))
314  return false;
315 
316  if (Offset != MFI.getObjectOffset(FI))
317  return false;
318 
319  if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
320  // If the argument location is wider than the argument type, check that any
321  // extension flags match.
322  if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
323  Flags.isSExt() != MFI.isObjectSExt(FI)) {
324  return false;
325  }
326  }
327 
328  return Bytes == MFI.getObjectSize(FI);
329 }
330 
331 SDValue
332 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
335  int ReturnAddrIndex = FuncInfo->getRAIndex();
336 
337  if (ReturnAddrIndex == 0) {
338  // Set up a frame object for the return address.
339  unsigned SlotSize = Subtarget.getSlotSize();
340  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(
341  SlotSize, -(int64_t)SlotSize, false);
342  FuncInfo->setRAIndex(ReturnAddrIndex);
343  }
344 
345  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
346 }
347 
348 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
349  SDValue &OutRetAddr,
350  SDValue Chain,
351  bool IsTailCall, int FPDiff,
352  const SDLoc &DL) const {
353  EVT VT = getPointerTy(DAG.getDataLayout());
354  OutRetAddr = getReturnAddressFrameIndex(DAG);
355 
356  // Load the "old" Return address.
357  OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo());
358  return SDValue(OutRetAddr.getNode(), 1);
359 }
360 
361 SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
362  SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI,
363  EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const {
364  if (!FPDiff)
365  return Chain;
366 
367  // Calculate the new stack slot for the return address.
368  int NewFO = MF.getFrameInfo().CreateFixedObject(
369  SlotSize, (int64_t)FPDiff - SlotSize, false);
370 
371  SDValue NewFI = DAG.getFrameIndex(NewFO, PtrVT);
372  // Store the return address to the appropriate stack slot.
373  Chain = DAG.getStore(
374  Chain, DL, RetFI, NewFI,
376  return Chain;
377 }
378 
379 SDValue
380 M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
382  const SDLoc &DL, SelectionDAG &DAG,
383  const CCValAssign &VA,
384  MachineFrameInfo &MFI,
385  unsigned ArgIdx) const {
386  // Create the nodes corresponding to a load from this parameter slot.
387  ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
388  EVT ValVT;
389 
390  // If value is passed by pointer we have address passed instead of the value
391  // itself.
392  if (VA.getLocInfo() == CCValAssign::Indirect)
393  ValVT = VA.getLocVT();
394  else
395  ValVT = VA.getValVT();
396 
397  // Because we are dealing with BE architecture we need to offset loading of
398  // partial types
399  int Offset = VA.getLocMemOffset();
400  if (VA.getValVT() == MVT::i8) {
401  Offset += 3;
402  } else if (VA.getValVT() == MVT::i16) {
403  Offset += 2;
404  }
405 
406  // TODO Interrupt handlers
407  // Calculate SP offset of interrupt parameter, re-arrange the slot normally
408  // taken by a return address.
409 
410  // FIXME For now, all byval parameter objects are marked mutable. This can
411  // be changed with more analysis. In case of tail call optimization mark all
412  // arguments mutable. Since they could be overwritten by lowering of arguments
413  // in case of a tail call.
414  bool AlwaysUseMutable = shouldGuaranteeTCO(
415  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
416  bool IsImmutable = !AlwaysUseMutable && !Flags.isByVal();
417 
418  if (Flags.isByVal()) {
419  unsigned Bytes = Flags.getByValSize();
420  if (Bytes == 0)
421  Bytes = 1; // Don't create zero-sized stack objects.
422  int FI = MFI.CreateFixedObject(Bytes, Offset, IsImmutable);
423  // TODO Interrupt handlers
424  // Adjust SP offset of interrupt parameter.
425  return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
426  } else {
427  int FI =
428  MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, Offset, IsImmutable);
429 
430  // Set SExt or ZExt flag.
431  if (VA.getLocInfo() == CCValAssign::ZExt) {
432  MFI.setObjectZExt(FI, true);
433  } else if (VA.getLocInfo() == CCValAssign::SExt) {
434  MFI.setObjectSExt(FI, true);
435  }
436 
437  // TODO Interrupt handlers
438  // Adjust SP offset of interrupt parameter.
439 
440  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
441  SDValue Val = DAG.getLoad(
442  ValVT, DL, Chain, FIN,
444  return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val)
445  : Val;
446  }
447 }
448 
449 SDValue M68kTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
450  SDValue Arg, const SDLoc &DL,
451  SelectionDAG &DAG,
452  const CCValAssign &VA,
453  ISD::ArgFlagsTy Flags) const {
454  unsigned LocMemOffset = VA.getLocMemOffset();
455  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
456  PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
457  StackPtr, PtrOff);
458  if (Flags.isByVal())
459  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL);
460 
461  return DAG.getStore(
462  Chain, DL, Arg, PtrOff,
463  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
464 }
465 
466 //===----------------------------------------------------------------------===//
467 // Call
468 //===----------------------------------------------------------------------===//
469 
470 SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
471  SmallVectorImpl<SDValue> &InVals) const {
472  SelectionDAG &DAG = CLI.DAG;
473  SDLoc &DL = CLI.DL;
475  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
477  SDValue Chain = CLI.Chain;
478  SDValue Callee = CLI.Callee;
479  CallingConv::ID CallConv = CLI.CallConv;
480  bool &IsTailCall = CLI.IsTailCall;
481  bool IsVarArg = CLI.IsVarArg;
482 
485  bool IsSibcall = false;
487  // const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
488 
489  if (CallConv == CallingConv::M68k_INTR)
490  report_fatal_error("M68k interrupts may not be called directly");
491 
492  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
493  if (Attr.getValueAsBool())
494  IsTailCall = false;
495 
496  // FIXME Add tailcalls support
497 
498  bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
499  if (IsMustTail) {
500  // Force this to be a tail call. The verifier rules are enough to ensure
501  // that we can lower this successfully without moving the return address
502  // around.
503  IsTailCall = true;
504  } else if (IsTailCall) {
505  // Check if it's really possible to do a tail call.
506  IsTailCall = IsEligibleForTailCallOptimization(
507  Callee, CallConv, IsVarArg, SR != NotStructReturn,
508  MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
509  DAG);
510 
511  // Sibcalls are automatically detected tailcalls which do not require
512  // ABI changes.
513  if (!MF.getTarget().Options.GuaranteedTailCallOpt && IsTailCall)
514  IsSibcall = true;
515 
516  if (IsTailCall)
517  ++NumTailCalls;
518  }
519 
520  assert(!(IsVarArg && canGuaranteeTCO(CallConv)) &&
521  "Var args not supported with calling convention fastcc");
522 
523  // Analyze operands of the call, assigning locations to each operand.
525  SmallVector<Type *, 4> ArgTypes;
526  for (const auto &Arg : CLI.getArgs())
527  ArgTypes.emplace_back(Arg.Ty);
528  M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
529  *DAG.getContext());
530  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
531 
532  // Get a count of how many bytes are to be pushed on the stack.
533  unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
534  if (IsSibcall) {
535  // This is a sibcall. The memory operands are available in caller's
536  // own caller's stack.
537  NumBytes = 0;
538  } else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
539  canGuaranteeTCO(CallConv)) {
540  NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
541  }
542 
543  int FPDiff = 0;
544  if (IsTailCall && !IsSibcall && !IsMustTail) {
545  // Lower arguments at fp - stackoffset + fpdiff.
546  unsigned NumBytesCallerPushed = MFI->getBytesToPopOnReturn();
547 
548  FPDiff = NumBytesCallerPushed - NumBytes;
549 
550  // Set the delta of movement of the returnaddr stackslot.
551  // But only set if delta is greater than previous delta.
552  if (FPDiff < MFI->getTCReturnAddrDelta())
553  MFI->setTCReturnAddrDelta(FPDiff);
554  }
555 
556  unsigned NumBytesToPush = NumBytes;
557  unsigned NumBytesToPop = NumBytes;
558 
559  // If we have an inalloca argument, all stack space has already been allocated
560  // for us and be right at the top of the stack. We don't support multiple
561  // arguments passed in memory when using inalloca.
562  if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
563  NumBytesToPush = 0;
564  if (!ArgLocs.back().isMemLoc())
565  report_fatal_error("cannot use inalloca attribute on a register "
566  "parameter");
567  if (ArgLocs.back().getLocMemOffset() != 0)
568  report_fatal_error("any parameter with the inalloca attribute must be "
569  "the only memory argument");
570  }
571 
572  if (!IsSibcall)
573  Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
574  NumBytes - NumBytesToPush, DL);
575 
576  SDValue RetFI;
577  // Load return address for tail calls.
578  if (IsTailCall && FPDiff)
579  Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
580 
582  SmallVector<SDValue, 8> MemOpChains;
584 
585  // Walk the register/memloc assignments, inserting copies/loads. In the case
586  // of tail call optimization arguments are handle later.
587  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
588  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
589  ISD::ArgFlagsTy Flags = Outs[i].Flags;
590 
591  // Skip inalloca arguments, they have already been written.
592  if (Flags.isInAlloca())
593  continue;
594 
595  CCValAssign &VA = ArgLocs[i];
596  EVT RegVT = VA.getLocVT();
597  SDValue Arg = OutVals[i];
598  bool IsByVal = Flags.isByVal();
599 
600  // Promote the value if needed.
601  switch (VA.getLocInfo()) {
602  default:
603  llvm_unreachable("Unknown loc info!");
604  case CCValAssign::Full:
605  break;
606  case CCValAssign::SExt:
607  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
608  break;
609  case CCValAssign::ZExt:
610  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
611  break;
612  case CCValAssign::AExt:
613  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
614  break;
615  case CCValAssign::BCvt:
616  Arg = DAG.getBitcast(RegVT, Arg);
617  break;
618  case CCValAssign::Indirect: {
619  // Store the argument.
620  SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
621  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
622  Chain = DAG.getStore(
623  Chain, DL, Arg, SpillSlot,
625  Arg = SpillSlot;
626  break;
627  }
628  }
629 
630  if (VA.isRegLoc()) {
631  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
632  } else if (!IsSibcall && (!IsTailCall || IsByVal)) {
633  assert(VA.isMemLoc());
634  if (!StackPtr.getNode()) {
635  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
636  getPointerTy(DAG.getDataLayout()));
637  }
638  MemOpChains.push_back(
639  LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
640  }
641  }
642 
643  if (!MemOpChains.empty())
644  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
645 
646  // FIXME Make sure PIC style GOT works as expected
647  // The only time GOT is really needed is for Medium-PIC static data
648  // otherwise we are happy with pc-rel or static references
649 
650  if (IsVarArg && IsMustTail) {
651  const auto &Forwards = MFI->getForwardedMustTailRegParms();
652  for (const auto &F : Forwards) {
653  SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
654  RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
655  }
656  }
657 
658  // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
659  // don't need this because the eligibility check rejects calls that require
660  // shuffling arguments passed in memory.
661  if (!IsSibcall && IsTailCall) {
662  // Force all the incoming stack arguments to be loaded from the stack
663  // before any new outgoing arguments are stored to the stack, because the
664  // outgoing stack slots may alias the incoming argument stack slots, and
665  // the alias isn't otherwise explicit. This is slightly more conservative
666  // than necessary, because it means that each store effectively depends
667  // on every argument instead of just those arguments it would clobber.
668  SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
669 
670  SmallVector<SDValue, 8> MemOpChains2;
671  SDValue FIN;
672  int FI = 0;
673  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
674  CCValAssign &VA = ArgLocs[i];
675  if (VA.isRegLoc())
676  continue;
677  assert(VA.isMemLoc());
678  SDValue Arg = OutVals[i];
679  ISD::ArgFlagsTy Flags = Outs[i].Flags;
680  // Skip inalloca arguments. They don't require any work.
681  if (Flags.isInAlloca())
682  continue;
683  // Create frame index.
684  int32_t Offset = VA.getLocMemOffset() + FPDiff;
685  uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
686  FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
687  FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
688 
689  if (Flags.isByVal()) {
690  // Copy relative to framepointer.
692  if (!StackPtr.getNode()) {
693  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
694  getPointerTy(DAG.getDataLayout()));
695  }
697  StackPtr, Source);
698 
699  MemOpChains2.push_back(
700  CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL));
701  } else {
702  // Store relative to framepointer.
703  MemOpChains2.push_back(DAG.getStore(
704  ArgChain, DL, Arg, FIN,
706  }
707  }
708 
709  if (!MemOpChains2.empty())
710  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2);
711 
712  // Store the return address to the appropriate stack slot.
713  Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
715  Subtarget.getSlotSize(), FPDiff, DL);
716  }
717 
718  // Build a sequence of copy-to-reg nodes chained together with token chain
719  // and flag operands which copy the outgoing args into registers.
720  SDValue InFlag;
721  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
722  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
723  RegsToPass[i].second, InFlag);
724  InFlag = Chain.getValue(1);
725  }
726 
727  if (Callee->getOpcode() == ISD::GlobalAddress) {
728  // If the callee is a GlobalAddress node (quite common, every direct call
729  // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
730  // it.
731  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
732 
733  // We should use extra load for direct calls to dllimported functions in
734  // non-JIT mode.
735  const GlobalValue *GV = G->getGlobal();
736  if (!GV->hasDLLImportStorageClass()) {
737  unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
738 
740  GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
741 
742  if (OpFlags == M68kII::MO_GOTPCREL) {
743 
744  // Add a wrapper.
746  getPointerTy(DAG.getDataLayout()), Callee);
747 
748  // Add extra indirection
749  Callee = DAG.getLoad(
750  getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee,
752  }
753  }
754  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
756  unsigned char OpFlags =
757  Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
758 
760  S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
761  }
762 
763  // Returns a chain & a flag for retval copy to use.
764  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
766 
767  if (!IsSibcall && IsTailCall) {
768  Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InFlag, DL);
769  InFlag = Chain.getValue(1);
770  }
771 
772  Ops.push_back(Chain);
773  Ops.push_back(Callee);
774 
775  if (IsTailCall)
776  Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32));
777 
778  // Add argument registers to the end of the list so that they are known live
779  // into the call.
780  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
781  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
782  RegsToPass[i].second.getValueType()));
783 
784  // Add a register mask operand representing the call-preserved registers.
785  const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
786  assert(Mask && "Missing call preserved mask for calling convention");
787 
788  Ops.push_back(DAG.getRegisterMask(Mask));
789 
790  if (InFlag.getNode())
791  Ops.push_back(InFlag);
792 
793  if (IsTailCall) {
795  return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops);
796  }
797 
798  Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops);
799  InFlag = Chain.getValue(1);
800 
801  // Create the CALLSEQ_END node.
802  unsigned NumBytesForCalleeToPop;
803  if (M68k::isCalleePop(CallConv, IsVarArg,
805  NumBytesForCalleeToPop = NumBytes; // Callee pops everything
806  } else if (!canGuaranteeTCO(CallConv) && SR == StackStructReturn) {
807  // If this is a call to a struct-return function, the callee
808  // pops the hidden struct pointer, so we have to push it back.
809  NumBytesForCalleeToPop = 4;
810  } else {
811  NumBytesForCalleeToPop = 0; // Callee pops nothing.
812  }
813 
814  if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
815  // No need to reset the stack after the call if the call doesn't return. To
816  // make the MI verify, we'll pretend the callee does it for us.
817  NumBytesForCalleeToPop = NumBytes;
818  }
819 
820  // Returns a flag for retval copy to use.
821  if (!IsSibcall) {
822  Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, NumBytesForCalleeToPop,
823  InFlag, DL);
824  InFlag = Chain.getValue(1);
825  }
826 
827  // Handle result values, copying them out of physregs into vregs that we
828  // return.
829  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
830  InVals);
831 }
832 
833 SDValue M68kTargetLowering::LowerCallResult(
834  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
836  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
837 
838  // Assign locations to each value returned by this call.
840  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
841  *DAG.getContext());
842  CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
843 
844  // Copy all of the result registers out of their specified physreg.
845  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
846  CCValAssign &VA = RVLocs[i];
847  EVT CopyVT = VA.getLocVT();
848 
849  /// ??? is this correct?
850  Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag)
851  .getValue(1);
852  SDValue Val = Chain.getValue(0);
853 
854  if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
855  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
856 
857  InFlag = Chain.getValue(2);
858  InVals.push_back(Val);
859  }
860 
861  return Chain;
862 }
863 
864 //===----------------------------------------------------------------------===//
865 // Formal Arguments Calling Convention Implementation
866 //===----------------------------------------------------------------------===//
867 
868 SDValue M68kTargetLowering::LowerFormalArguments(
869  SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
871  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
874  // const TargetFrameLowering &TFL = *Subtarget.getFrameLowering();
875 
876  MachineFrameInfo &MFI = MF.getFrameInfo();
877 
878  // Assign locations to all of the incoming arguments.
880  SmallVector<Type *, 4> ArgTypes;
881  for (const Argument &Arg : MF.getFunction().args())
882  ArgTypes.emplace_back(Arg.getType());
883  M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext());
884 
885  CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
886 
887  unsigned LastVal = ~0U;
888  SDValue ArgValue;
889  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
890  CCValAssign &VA = ArgLocs[i];
891  assert(VA.getValNo() != LastVal && "Same value in different locations");
892 
893  LastVal = VA.getValNo();
894 
895  if (VA.isRegLoc()) {
896  EVT RegVT = VA.getLocVT();
897  const TargetRegisterClass *RC;
898  if (RegVT == MVT::i32)
899  RC = &M68k::XR32RegClass;
900  else
901  llvm_unreachable("Unknown argument type!");
902 
903  Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
904  ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
905 
906  // If this is an 8 or 16-bit value, it is really passed promoted to 32
907  // bits. Insert an assert[sz]ext to capture this, then truncate to the
908  // right size.
909  if (VA.getLocInfo() == CCValAssign::SExt) {
910  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
911  DAG.getValueType(VA.getValVT()));
912  } else if (VA.getLocInfo() == CCValAssign::ZExt) {
913  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
914  DAG.getValueType(VA.getValVT()));
915  } else if (VA.getLocInfo() == CCValAssign::BCvt) {
916  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
917  }
918 
919  if (VA.isExtInLoc()) {
920  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
921  }
922  } else {
923  assert(VA.isMemLoc());
924  ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i);
925  }
926 
927  // If value is passed via pointer - do a load.
928  // TODO Make sure this handling on indirect arguments is correct
929  if (VA.getLocInfo() == CCValAssign::Indirect)
930  ArgValue =
931  DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo());
932 
933  InVals.push_back(ArgValue);
934  }
935 
936  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
937  // Swift calling convention does not require we copy the sret argument
938  // into %D0 for the return. We don't set SRetReturnReg for Swift.
939  if (CCID == CallingConv::Swift)
940  continue;
941 
942  // ABI require that for returning structs by value we copy the sret argument
943  // into %D0 for the return. Save the argument into a virtual register so
944  // that we can access it from the return points.
945  if (Ins[i].Flags.isSRet()) {
946  unsigned Reg = MMFI->getSRetReturnReg();
947  if (!Reg) {
948  MVT PtrTy = getPointerTy(DAG.getDataLayout());
950  MMFI->setSRetReturnReg(Reg);
951  }
952  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
953  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
954  break;
955  }
956  }
957 
958  unsigned StackSize = CCInfo.getNextStackOffset();
959  // Align stack specially for tail calls.
961  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
962 
963  // If the function takes variable number of arguments, make a frame index for
964  // the start of the first vararg value... for expansion of llvm.va_start. We
965  // can skip this if there are no va_start calls.
966  if (MFI.hasVAStart()) {
967  MMFI->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
968  }
969 
970  if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
971  // We forward some GPRs and some vector types.
972  SmallVector<MVT, 2> RegParmTypes;
973  MVT IntVT = MVT::i32;
974  RegParmTypes.push_back(IntVT);
975 
976  // Compute the set of forwarded registers. The rest are scratch.
977  // ??? what is this for?
980  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
981 
982  // Copy all forwards from physical to virtual registers.
983  for (ForwardedRegister &F : Forwards) {
984  // FIXME Can we use a less constrained schedule?
985  SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
987  Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal);
988  }
989  }
990 
991  // Some CCs need callee pop.
992  if (M68k::isCalleePop(CCID, IsVarArg,
994  MMFI->setBytesToPopOnReturn(StackSize); // Callee pops everything.
995  } else {
996  MMFI->setBytesToPopOnReturn(0); // Callee pops nothing.
997  // If this is an sret function, the return should pop the hidden pointer.
999  MMFI->setBytesToPopOnReturn(4);
1000  }
1001 
1002  MMFI->setArgumentStackSize(StackSize);
1003 
1004  return Chain;
1005 }
1006 
1007 //===----------------------------------------------------------------------===//
1008 // Return Value Calling Convention Implementation
1009 //===----------------------------------------------------------------------===//
1010 
1011 SDValue
1012 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
1013  bool IsVarArg,
1014  const SmallVectorImpl<ISD::OutputArg> &Outs,
1015  const SmallVectorImpl<SDValue> &OutVals,
1016  const SDLoc &DL, SelectionDAG &DAG) const {
1017  MachineFunction &MF = DAG.getMachineFunction();
1019 
1021  CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1022  CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1023 
1024  SDValue Flag;
1025  SmallVector<SDValue, 6> RetOps;
1026  // Operand #0 = Chain (updated below)
1027  RetOps.push_back(Chain);
1028  // Operand #1 = Bytes To Pop
1029  RetOps.push_back(
1031 
1032  // Copy the result values into the output registers.
1033  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1034  CCValAssign &VA = RVLocs[i];
1035  assert(VA.isRegLoc() && "Can only return in registers!");
1036  SDValue ValToCopy = OutVals[i];
1037  EVT ValVT = ValToCopy.getValueType();
1038 
1039  // Promote values to the appropriate types.
1040  if (VA.getLocInfo() == CCValAssign::SExt)
1041  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1042  else if (VA.getLocInfo() == CCValAssign::ZExt)
1043  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy);
1044  else if (VA.getLocInfo() == CCValAssign::AExt) {
1045  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
1046  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1047  else
1048  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy);
1049  } else if (VA.getLocInfo() == CCValAssign::BCvt)
1050  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1051 
1052  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Flag);
1053  Flag = Chain.getValue(1);
1054  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1055  }
1056 
1057  // Swift calling convention does not require we copy the sret argument
1058  // into %d0 for the return, and SRetReturnReg is not set for Swift.
1059 
1060  // ABI require that for returning structs by value we copy the sret argument
1061  // into %D0 for the return. Save the argument into a virtual register so that
1062  // we can access it from the return points.
1063  //
1064  // Checking Function.hasStructRetAttr() here is insufficient because the IR
1065  // may not have an explicit sret argument. If MFI.CanLowerReturn is
1066  // false, then an sret argument may be implicitly inserted in the SelDAG. In
1067  // either case MFI->setSRetReturnReg() will have been called.
1068  if (unsigned SRetReg = MFI->getSRetReturnReg()) {
1069  // ??? Can i just move this to the top and escape this explanation?
1070  // When we have both sret and another return value, we should use the
1071  // original Chain stored in RetOps[0], instead of the current Chain updated
1072  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
1073 
1074  // For the case of sret and another return value, we have
1075  // Chain_0 at the function entry
1076  // Chain_1 = getCopyToReg(Chain_0) in the above loop
1077  // If we use Chain_1 in getCopyFromReg, we will have
1078  // Val = getCopyFromReg(Chain_1)
1079  // Chain_2 = getCopyToReg(Chain_1, Val) from below
1080 
1081  // getCopyToReg(Chain_0) will be glued together with
1082  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
1083  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
1084  // Data dependency from Unit B to Unit A due to usage of Val in
1085  // getCopyToReg(Chain_1, Val)
1086  // Chain dependency from Unit A to Unit B
1087 
1088  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
1089  SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
1090  getPointerTy(MF.getDataLayout()));
1091 
1092  // ??? How will this work if CC does not use registers for args passing?
1093  // ??? What if I return multiple structs?
1094  unsigned RetValReg = M68k::D0;
1095  Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Flag);
1096  Flag = Chain.getValue(1);
1097 
1098  RetOps.push_back(
1099  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
1100  }
1101 
1102  RetOps[0] = Chain; // Update chain.
1103 
1104  // Add the flag if we have it.
1105  if (Flag.getNode())
1106  RetOps.push_back(Flag);
1107 
1108  return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps);
1109 }
1110 
1111 //===----------------------------------------------------------------------===//
1112 // Fast Calling Convention (tail call) implementation
1113 //===----------------------------------------------------------------------===//
1114 
1115 // Like std call, callee cleans arguments, convention except that ECX is
1116 // reserved for storing the tail called function address. Only 2 registers are
1117 // free for argument passing (inreg). Tail call optimization is performed
1118 // provided:
1119 // * tailcallopt is enabled
1120 // * caller/callee are fastcc
1121 // On M68k_64 architecture with GOT-style position independent code only
1122 // local (within module) calls are supported at the moment. To keep the stack
1123 // aligned according to platform abi the function GetAlignedArgumentStackSize
1124 // ensures that argument delta is always multiples of stack alignment. (Dynamic
1125 // linkers need this - darwin's dyld for example) If a tail called function
1126 // callee has more arguments than the caller the caller needs to make sure that
1127 // there is room to move the RETADDR to. This is achieved by reserving an area
1128 // the size of the argument delta right after the original RETADDR, but before
1129 // the saved framepointer or the spilled registers e.g. caller(arg1, arg2)
1130 // calls callee(arg1, arg2,arg3,arg4) stack layout:
1131 // arg1
1132 // arg2
1133 // RETADDR
1134 // [ new RETADDR
1135 // move area ]
1136 // (possible EBP)
1137 // ESI
1138 // EDI
1139 // local1 ..
1140 
1141 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
1142 /// requirement.
1143 unsigned
1144 M68kTargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1145  SelectionDAG &DAG) const {
1146  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
1147  unsigned StackAlignment = TFI.getStackAlignment();
1148  uint64_t AlignMask = StackAlignment - 1;
1149  int64_t Offset = StackSize;
1150  unsigned SlotSize = Subtarget.getSlotSize();
1151  if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1152  // Number smaller than 12 so just add the difference.
1153  Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1154  } else {
1155  // Mask out lower bits, add stackalignment once plus the 12 bytes.
1156  Offset =
1157  ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1158  }
1159  return Offset;
1160 }
1161 
1162 /// Check whether the call is eligible for tail call optimization. Targets
1163 /// that want to do tail call optimization should implement this function.
1164 bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1165  SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
1166  bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
1167  const SmallVectorImpl<ISD::OutputArg> &Outs,
1168  const SmallVectorImpl<SDValue> &OutVals,
1169  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1170  if (!mayTailCallThisCC(CalleeCC))
1171  return false;
1172 
1173  // If -tailcallopt is specified, make fastcc functions tail-callable.
1174  MachineFunction &MF = DAG.getMachineFunction();
1175  const auto &CallerF = MF.getFunction();
1176 
1177  CallingConv::ID CallerCC = CallerF.getCallingConv();
1178  bool CCMatch = CallerCC == CalleeCC;
1179 
1181  if (canGuaranteeTCO(CalleeCC) && CCMatch)
1182  return true;
1183  return false;
1184  }
1185 
1186  // Look for obvious safe cases to perform tail call optimization that do not
1187  // require ABI changes. This is what gcc calls sibcall.
1188 
1189  // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1190  // emit a special epilogue.
1191  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1192  if (RegInfo->hasStackRealignment(MF))
1193  return false;
1194 
1195  // Also avoid sibcall optimization if either caller or callee uses struct
1196  // return semantics.
1197  if (IsCalleeStructRet || IsCallerStructRet)
1198  return false;
1199 
1200  // Do not sibcall optimize vararg calls unless all arguments are passed via
1201  // registers.
1202  LLVMContext &C = *DAG.getContext();
1203  if (IsVarArg && !Outs.empty()) {
1204 
1206  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1207 
1208  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1209  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1210  if (!ArgLocs[i].isRegLoc())
1211  return false;
1212  }
1213 
1214  // Check that the call results are passed in the same way.
1215  if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, RetCC_M68k,
1216  RetCC_M68k))
1217  return false;
1218 
1219  // The callee has to preserve all registers the caller needs to preserve.
1220  const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
1221  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1222  if (!CCMatch) {
1223  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1224  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1225  return false;
1226  }
1227 
1228  unsigned StackArgsSize = 0;
1229 
1230  // If the callee takes no arguments then go on to check the results of the
1231  // call.
1232  if (!Outs.empty()) {
1233  // Check if stack adjustment is needed. For now, do not do this if any
1234  // argument is passed on the stack.
1236  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1237 
1238  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1239  StackArgsSize = CCInfo.getNextStackOffset();
1240 
1241  if (CCInfo.getNextStackOffset()) {
1242  // Check if the arguments are already laid out in the right way as
1243  // the caller's fixed stack objects.
1244  MachineFrameInfo &MFI = MF.getFrameInfo();
1245  const MachineRegisterInfo *MRI = &MF.getRegInfo();
1246  const M68kInstrInfo *TII = Subtarget.getInstrInfo();
1247  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1248  CCValAssign &VA = ArgLocs[i];
1249  SDValue Arg = OutVals[i];
1250  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1251  if (VA.getLocInfo() == CCValAssign::Indirect)
1252  return false;
1253  if (!VA.isRegLoc()) {
1254  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI,
1255  TII, VA))
1256  return false;
1257  }
1258  }
1259  }
1260 
1261  bool PositionIndependent = isPositionIndependent();
1262  // If the tailcall address may be in a register, then make sure it's
1263  // possible to register allocate for it. The call address can
1264  // only target %A0 or %A1 since the tail call must be scheduled after
1265  // callee-saved registers are restored. These happen to be the same
1266  // registers used to pass 'inreg' arguments so watch out for those.
1267  if ((!isa<GlobalAddressSDNode>(Callee) &&
1268  !isa<ExternalSymbolSDNode>(Callee)) ||
1269  PositionIndependent) {
1270  unsigned NumInRegs = 0;
1271  // In PIC we need an extra register to formulate the address computation
1272  // for the callee.
1273  unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1274 
1275  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1276  CCValAssign &VA = ArgLocs[i];
1277  if (!VA.isRegLoc())
1278  continue;
1279  Register Reg = VA.getLocReg();
1280  switch (Reg) {
1281  default:
1282  break;
1283  case M68k::A0:
1284  case M68k::A1:
1285  if (++NumInRegs == MaxInRegs)
1286  return false;
1287  break;
1288  }
1289  }
1290  }
1291 
1292  const MachineRegisterInfo &MRI = MF.getRegInfo();
1293  if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
1294  return false;
1295  }
1296 
1297  bool CalleeWillPop = M68k::isCalleePop(
1298  CalleeCC, IsVarArg, MF.getTarget().Options.GuaranteedTailCallOpt);
1299 
1300  if (unsigned BytesToPop =
1302  // If we have bytes to pop, the callee must pop them.
1303  bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1304  if (!CalleePopMatches)
1305  return false;
1306  } else if (CalleeWillPop && StackArgsSize > 0) {
1307  // If we don't have bytes to pop, make sure the callee doesn't pop any.
1308  return false;
1309  }
1310 
1311  return true;
1312 }
1313 
1314 //===----------------------------------------------------------------------===//
1315 // Custom Lower
1316 //===----------------------------------------------------------------------===//
1317 
1319  SelectionDAG &DAG) const {
1320  switch (Op.getOpcode()) {
1321  default:
1322  llvm_unreachable("Should not custom lower this!");
1323  case ISD::SADDO:
1324  case ISD::UADDO:
1325  case ISD::SSUBO:
1326  case ISD::USUBO:
1327  case ISD::SMULO:
1328  case ISD::UMULO:
1329  return LowerXALUO(Op, DAG);
1330  case ISD::SETCC:
1331  return LowerSETCC(Op, DAG);
1332  case ISD::SETCCCARRY:
1333  return LowerSETCCCARRY(Op, DAG);
1334  case ISD::SELECT:
1335  return LowerSELECT(Op, DAG);
1336  case ISD::BRCOND:
1337  return LowerBRCOND(Op, DAG);
1338  case ISD::ADDC:
1339  case ISD::ADDE:
1340  case ISD::SUBC:
1341  case ISD::SUBE:
1342  return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1343  case ISD::ConstantPool:
1344  return LowerConstantPool(Op, DAG);
1345  case ISD::GlobalAddress:
1346  return LowerGlobalAddress(Op, DAG);
1347  case ISD::ExternalSymbol:
1348  return LowerExternalSymbol(Op, DAG);
1349  case ISD::BlockAddress:
1350  return LowerBlockAddress(Op, DAG);
1351  case ISD::JumpTable:
1352  return LowerJumpTable(Op, DAG);
1353  case ISD::VASTART:
1354  return LowerVASTART(Op, DAG);
1356  return LowerDYNAMIC_STACKALLOC(Op, DAG);
1357  case ISD::SHL_PARTS:
1358  return LowerShiftLeftParts(Op, DAG);
1359  case ISD::SRA_PARTS:
1360  return LowerShiftRightParts(Op, DAG, true);
1361  case ISD::SRL_PARTS:
1362  return LowerShiftRightParts(Op, DAG, false);
1363  }
1364 }
1365 
1366 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1367  SDValue C) const {
1368  // Shifts and add instructions in M68000 and M68010 support
1369  // up to 32 bits, but mul only has 16-bit variant. So it's almost
1370  // certainly beneficial to lower 8/16/32-bit mul to their
1371  // add / shifts counterparts. But for 64-bits mul, it might be
1372  // safer to just leave it to compiler runtime implementations.
1373  return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
1374 }
1375 
1376 SDValue M68kTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
1377  // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
1378  // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1379  // looks for this combo and may remove the "setcc" instruction if the "setcc"
1380  // has only one use.
1381  SDNode *N = Op.getNode();
1382  SDValue LHS = N->getOperand(0);
1383  SDValue RHS = N->getOperand(1);
1384  unsigned BaseOp = 0;
1385  unsigned Cond = 0;
1386  SDLoc DL(Op);
1387  switch (Op.getOpcode()) {
1388  default:
1389  llvm_unreachable("Unknown ovf instruction!");
1390  case ISD::SADDO:
1391  BaseOp = M68kISD::ADD;
1392  Cond = M68k::COND_VS;
1393  break;
1394  case ISD::UADDO:
1395  BaseOp = M68kISD::ADD;
1396  Cond = M68k::COND_CS;
1397  break;
1398  case ISD::SSUBO:
1399  BaseOp = M68kISD::SUB;
1400  Cond = M68k::COND_VS;
1401  break;
1402  case ISD::USUBO:
1403  BaseOp = M68kISD::SUB;
1404  Cond = M68k::COND_CS;
1405  break;
1406  }
1407 
1408  // Also sets CCR.
1409  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i8);
1410  SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
1411  SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1412  DAG.getConstant(Cond, DL, MVT::i8),
1413  SDValue(Arith.getNode(), 1));
1414 
1415  return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1416 }
1417 
1418 /// Create a BTST (Bit Test) node - Test bit \p BitNo in \p Src and set
1419 /// condition according to equal/not-equal condition code \p CC.
1421  const SDLoc &DL, SelectionDAG &DAG) {
1422  // If Src is i8, promote it to i32 with any_extend. There is no i8 BTST
1423  // instruction. Since the shift amount is in-range-or-undefined, we know
1424  // that doing a bittest on the i32 value is ok.
1425  if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1426  Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
1427 
1428  // If the operand types disagree, extend the shift amount to match. Since
1429  // BTST ignores high bits (like shifts) we can use anyextend.
1430  if (Src.getValueType() != BitNo.getValueType())
1431  BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo);
1432 
1433  SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
1434 
1435  // NOTE BTST sets CCR.Z flag
1437  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1438  DAG.getConstant(Cond, DL, MVT::i8), BTST);
1439 }
1440 
1441 /// Result of 'and' is compared against zero. Change to a BTST node if possible.
1443  SelectionDAG &DAG) {
1444  SDValue Op0 = And.getOperand(0);
1445  SDValue Op1 = And.getOperand(1);
1446  if (Op0.getOpcode() == ISD::TRUNCATE)
1447  Op0 = Op0.getOperand(0);
1448  if (Op1.getOpcode() == ISD::TRUNCATE)
1449  Op1 = Op1.getOperand(0);
1450 
1451  SDValue LHS, RHS;
1452  if (Op1.getOpcode() == ISD::SHL)
1453  std::swap(Op0, Op1);
1454  if (Op0.getOpcode() == ISD::SHL) {
1455  if (isOneConstant(Op0.getOperand(0))) {
1456  // If we looked past a truncate, check that it's only truncating away
1457  // known zeros.
1458  unsigned BitWidth = Op0.getValueSizeInBits();
1459  unsigned AndBitWidth = And.getValueSizeInBits();
1460  if (BitWidth > AndBitWidth) {
1461  auto Known = DAG.computeKnownBits(Op0);
1462  if (Known.countMinLeadingZeros() < BitWidth - AndBitWidth)
1463  return SDValue();
1464  }
1465  LHS = Op1;
1466  RHS = Op0.getOperand(1);
1467  }
1468  } else if (auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1469  uint64_t AndRHSVal = AndRHS->getZExtValue();
1470  SDValue AndLHS = Op0;
1471 
1472  if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
1473  LHS = AndLHS.getOperand(0);
1474  RHS = AndLHS.getOperand(1);
1475  }
1476 
1477  // Use BTST if the immediate can't be encoded in a TEST instruction.
1478  if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
1479  LHS = AndLHS;
1480  RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType());
1481  }
1482  }
1483 
1484  if (LHS.getNode())
1485  return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1486 
1487  return SDValue();
1488 }
1489 
1491  switch (SetCCOpcode) {
1492  default:
1493  llvm_unreachable("Invalid integer condition!");
1494  case ISD::SETEQ:
1495  return M68k::COND_EQ;
1496  case ISD::SETGT:
1497  return M68k::COND_GT;
1498  case ISD::SETGE:
1499  return M68k::COND_GE;
1500  case ISD::SETLT:
1501  return M68k::COND_LT;
1502  case ISD::SETLE:
1503  return M68k::COND_LE;
1504  case ISD::SETNE:
1505  return M68k::COND_NE;
1506  case ISD::SETULT:
1507  return M68k::COND_CS;
1508  case ISD::SETUGE:
1509  return M68k::COND_CC;
1510  case ISD::SETUGT:
1511  return M68k::COND_HI;
1512  case ISD::SETULE:
1513  return M68k::COND_LS;
1514  }
1515 }
1516 
1517 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1518 /// condition code, returning the condition code and the LHS/RHS of the
1519 /// comparison to make.
1520 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1521  bool IsFP, SDValue &LHS, SDValue &RHS,
1522  SelectionDAG &DAG) {
1523  if (!IsFP) {
1524  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1525  if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1526  // X > -1 -> X == 0, jump !sign.
1527  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1528  return M68k::COND_PL;
1529  }
1530  if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1531  // X < 0 -> X == 0, jump on sign.
1532  return M68k::COND_MI;
1533  }
1534  if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1535  // X < 1 -> X <= 0
1536  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1537  return M68k::COND_LE;
1538  }
1539  }
1540 
1541  return TranslateIntegerM68kCC(SetCCOpcode);
1542  }
1543 
1544  // First determine if it is required or is profitable to flip the operands.
1545 
1546  // If LHS is a foldable load, but RHS is not, flip the condition.
1547  if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) {
1548  SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1549  std::swap(LHS, RHS);
1550  }
1551 
1552  switch (SetCCOpcode) {
1553  default:
1554  break;
1555  case ISD::SETOLT:
1556  case ISD::SETOLE:
1557  case ISD::SETUGT:
1558  case ISD::SETUGE:
1559  std::swap(LHS, RHS);
1560  break;
1561  }
1562 
1563  // On a floating point condition, the flags are set as follows:
1564  // ZF PF CF op
1565  // 0 | 0 | 0 | X > Y
1566  // 0 | 0 | 1 | X < Y
1567  // 1 | 0 | 0 | X == Y
1568  // 1 | 1 | 1 | unordered
1569  switch (SetCCOpcode) {
1570  default:
1571  llvm_unreachable("Condcode should be pre-legalized away");
1572  case ISD::SETUEQ:
1573  case ISD::SETEQ:
1574  return M68k::COND_EQ;
1575  case ISD::SETOLT: // flipped
1576  case ISD::SETOGT:
1577  case ISD::SETGT:
1578  return M68k::COND_HI;
1579  case ISD::SETOLE: // flipped
1580  case ISD::SETOGE:
1581  case ISD::SETGE:
1582  return M68k::COND_CC;
1583  case ISD::SETUGT: // flipped
1584  case ISD::SETULT:
1585  case ISD::SETLT:
1586  return M68k::COND_CS;
1587  case ISD::SETUGE: // flipped
1588  case ISD::SETULE:
1589  case ISD::SETLE:
1590  return M68k::COND_LS;
1591  case ISD::SETONE:
1592  case ISD::SETNE:
1593  return M68k::COND_NE;
1594  case ISD::SETOEQ:
1595  case ISD::SETUNE:
1596  return M68k::COND_INVALID;
1597  }
1598 }
1599 
1600 // Convert (truncate (srl X, N) to i1) to (bt X, N)
1602  const SDLoc &DL, SelectionDAG &DAG) {
1603 
1604  assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
1605  "Expected TRUNCATE to i1 node");
1606 
1607  if (Op.getOperand(0).getOpcode() != ISD::SRL)
1608  return SDValue();
1609 
1610  SDValue ShiftRight = Op.getOperand(0);
1611  return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
1612  CC, DL, DAG);
1613 }
1614 
1615 /// \brief return true if \c Op has a use that doesn't just read flags.
1616 static bool hasNonFlagsUse(SDValue Op) {
1617  for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
1618  ++UI) {
1619  SDNode *User = *UI;
1620  unsigned UOpNo = UI.getOperandNo();
1621  if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1622  // Look pass truncate.
1623  UOpNo = User->use_begin().getOperandNo();
1624  User = *User->use_begin();
1625  }
1626 
1627  if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
1628  !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
1629  return true;
1630  }
1631  return false;
1632 }
1633 
1634 SDValue M68kTargetLowering::EmitTest(SDValue Op, unsigned M68kCC,
1635  const SDLoc &DL, SelectionDAG &DAG) const {
1636 
1637  // CF and OF aren't always set the way we want. Determine which
1638  // of these we need.
1639  bool NeedCF = false;
1640  bool NeedOF = false;
1641  switch (M68kCC) {
1642  default:
1643  break;
1644  case M68k::COND_HI:
1645  case M68k::COND_CC:
1646  case M68k::COND_CS:
1647  case M68k::COND_LS:
1648  NeedCF = true;
1649  break;
1650  case M68k::COND_GT:
1651  case M68k::COND_GE:
1652  case M68k::COND_LT:
1653  case M68k::COND_LE:
1654  case M68k::COND_VS:
1655  case M68k::COND_VC: {
1656  // Check if we really need to set the
1657  // Overflow flag. If NoSignedWrap is present
1658  // that is not actually needed.
1659  switch (Op->getOpcode()) {
1660  case ISD::ADD:
1661  case ISD::SUB:
1662  case ISD::MUL:
1663  case ISD::SHL: {
1664  if (Op.getNode()->getFlags().hasNoSignedWrap())
1665  break;
1666  [[fallthrough]];
1667  }
1668  default:
1669  NeedOF = true;
1670  break;
1671  }
1672  break;
1673  }
1674  }
1675  // See if we can use the CCR value from the operand instead of
1676  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
1677  // we prove that the arithmetic won't overflow, we can't use OF or CF.
1678  if (Op.getResNo() != 0 || NeedOF || NeedCF) {
1679  // Emit a CMP with 0, which is the TEST pattern.
1680  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1681  DAG.getConstant(0, DL, Op.getValueType()), Op);
1682  }
1683  unsigned Opcode = 0;
1684  unsigned NumOperands = 0;
1685 
1686  // Truncate operations may prevent the merge of the SETCC instruction
1687  // and the arithmetic instruction before it. Attempt to truncate the operands
1688  // of the arithmetic instruction and use a reduced bit-width instruction.
1689  bool NeedTruncation = false;
1690  SDValue ArithOp = Op;
1691  if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
1692  SDValue Arith = Op->getOperand(0);
1693  // Both the trunc and the arithmetic op need to have one user each.
1694  if (Arith->hasOneUse())
1695  switch (Arith.getOpcode()) {
1696  default:
1697  break;
1698  case ISD::ADD:
1699  case ISD::SUB:
1700  case ISD::AND:
1701  case ISD::OR:
1702  case ISD::XOR: {
1703  NeedTruncation = true;
1704  ArithOp = Arith;
1705  }
1706  }
1707  }
1708 
1709  // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
1710  // which may be the result of a CAST. We use the variable 'Op', which is the
1711  // non-casted variable when we check for possible users.
1712  switch (ArithOp.getOpcode()) {
1713  case ISD::ADD:
1714  Opcode = M68kISD::ADD;
1715  NumOperands = 2;
1716  break;
1717  case ISD::SHL:
1718  case ISD::SRL:
1719  // If we have a constant logical shift that's only used in a comparison
1720  // against zero turn it into an equivalent AND. This allows turning it into
1721  // a TEST instruction later.
1722  if ((M68kCC == M68k::COND_EQ || M68kCC == M68k::COND_NE) &&
1723  Op->hasOneUse() && isa<ConstantSDNode>(Op->getOperand(1)) &&
1724  !hasNonFlagsUse(Op)) {
1725  EVT VT = Op.getValueType();
1726  unsigned BitWidth = VT.getSizeInBits();
1727  unsigned ShAmt = Op->getConstantOperandVal(1);
1728  if (ShAmt >= BitWidth) // Avoid undefined shifts.
1729  break;
1730  APInt Mask = ArithOp.getOpcode() == ISD::SRL
1732  : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
1733  if (!Mask.isSignedIntN(32)) // Avoid large immediates.
1734  break;
1735  Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0),
1736  DAG.getConstant(Mask, DL, VT));
1737  }
1738  break;
1739 
1740  case ISD::AND:
1741  // If the primary 'and' result isn't used, don't bother using
1742  // M68kISD::AND, because a TEST instruction will be better.
1743  if (!hasNonFlagsUse(Op)) {
1744  SDValue Op0 = ArithOp->getOperand(0);
1745  SDValue Op1 = ArithOp->getOperand(1);
1746  EVT VT = ArithOp.getValueType();
1747  bool IsAndn = isBitwiseNot(Op0) || isBitwiseNot(Op1);
1748  bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1749 
1750  // But if we can combine this into an ANDN operation, then create an AND
1751  // now and allow it to be pattern matched into an ANDN.
1752  if (/*!Subtarget.hasBMI() ||*/ !IsAndn || !IsLegalAndnType)
1753  break;
1754  }
1755  [[fallthrough]];
1756  case ISD::SUB:
1757  case ISD::OR:
1758  case ISD::XOR:
1759  // Due to the ISEL shortcoming noted above, be conservative if this op is
1760  // likely to be selected as part of a load-modify-store instruction.
1761  for (const auto *U : Op.getNode()->uses())
1762  if (U->getOpcode() == ISD::STORE)
1763  goto default_case;
1764 
1765  // Otherwise use a regular CCR-setting instruction.
1766  switch (ArithOp.getOpcode()) {
1767  default:
1768  llvm_unreachable("unexpected operator!");
1769  case ISD::SUB:
1770  Opcode = M68kISD::SUB;
1771  break;
1772  case ISD::XOR:
1773  Opcode = M68kISD::XOR;
1774  break;
1775  case ISD::AND:
1776  Opcode = M68kISD::AND;
1777  break;
1778  case ISD::OR:
1779  Opcode = M68kISD::OR;
1780  break;
1781  }
1782 
1783  NumOperands = 2;
1784  break;
1785  case M68kISD::ADD:
1786  case M68kISD::SUB:
1787  case M68kISD::OR:
1788  case M68kISD::XOR:
1789  case M68kISD::AND:
1790  return SDValue(Op.getNode(), 1);
1791  default:
1792  default_case:
1793  break;
1794  }
1795 
1796  // If we found that truncation is beneficial, perform the truncation and
1797  // update 'Op'.
1798  if (NeedTruncation) {
1799  EVT VT = Op.getValueType();
1800  SDValue WideVal = Op->getOperand(0);
1801  EVT WideVT = WideVal.getValueType();
1802  unsigned ConvertedOp = 0;
1803  // Use a target machine opcode to prevent further DAGCombine
1804  // optimizations that may separate the arithmetic operations
1805  // from the setcc node.
1806  switch (WideVal.getOpcode()) {
1807  default:
1808  break;
1809  case ISD::ADD:
1810  ConvertedOp = M68kISD::ADD;
1811  break;
1812  case ISD::SUB:
1813  ConvertedOp = M68kISD::SUB;
1814  break;
1815  case ISD::AND:
1816  ConvertedOp = M68kISD::AND;
1817  break;
1818  case ISD::OR:
1819  ConvertedOp = M68kISD::OR;
1820  break;
1821  case ISD::XOR:
1822  ConvertedOp = M68kISD::XOR;
1823  break;
1824  }
1825 
1826  if (ConvertedOp) {
1827  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1828  if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
1829  SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
1830  SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1));
1831  Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
1832  }
1833  }
1834  }
1835 
1836  if (Opcode == 0) {
1837  // Emit a CMP with 0, which is the TEST pattern.
1838  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1839  DAG.getConstant(0, DL, Op.getValueType()), Op);
1840  }
1841  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8);
1842  SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
1843 
1844  SDValue New = DAG.getNode(Opcode, DL, VTs, Ops);
1845  DAG.ReplaceAllUsesWith(Op, New);
1846  return SDValue(New.getNode(), 1);
1847 }
1848 
1849 /// \brief Return true if the condition is an unsigned comparison operation.
1850 static bool isM68kCCUnsigned(unsigned M68kCC) {
1851  switch (M68kCC) {
1852  default:
1853  llvm_unreachable("Invalid integer condition!");
1854  case M68k::COND_EQ:
1855  case M68k::COND_NE:
1856  case M68k::COND_CS:
1857  case M68k::COND_HI:
1858  case M68k::COND_LS:
1859  case M68k::COND_CC:
1860  return true;
1861  case M68k::COND_GT:
1862  case M68k::COND_GE:
1863  case M68k::COND_LT:
1864  case M68k::COND_LE:
1865  return false;
1866  }
1867 }
1868 
1869 SDValue M68kTargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC,
1870  const SDLoc &DL, SelectionDAG &DAG) const {
1871  if (isNullConstant(Op1))
1872  return EmitTest(Op0, M68kCC, DL, DAG);
1873 
1874  assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
1875  "Unexpected comparison operation for MVT::i1 operands");
1876 
1877  if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
1878  Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
1879  // Only promote the compare up to I32 if it is a 16 bit operation
1880  // with an immediate. 16 bit immediates are to be avoided.
1881  if ((Op0.getValueType() == MVT::i16 &&
1882  (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
1884  unsigned ExtendOp =
1886  Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0);
1887  Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1);
1888  }
1889  // Use SUB instead of CMP to enable CSE between SUB and CMP.
1890  SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8);
1891  SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1);
1892  return SDValue(Sub.getNode(), 1);
1893  }
1894  return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1);
1895 }
1896 
1897 /// Result of 'and' or 'trunc to i1' is compared against zero.
1898 /// Change to a BTST node if possible.
1899 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC,
1900  const SDLoc &DL,
1901  SelectionDAG &DAG) const {
1902  if (Op.getOpcode() == ISD::AND)
1903  return LowerAndToBTST(Op, CC, DL, DAG);
1904  if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
1905  return LowerTruncateToBTST(Op, CC, DL, DAG);
1906  return SDValue();
1907 }
1908 
1909 SDValue M68kTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1910  MVT VT = Op.getSimpleValueType();
1911  assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
1912 
1913  SDValue Op0 = Op.getOperand(0);
1914  SDValue Op1 = Op.getOperand(1);
1915  SDLoc DL(Op);
1916  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1917 
1918  // Optimize to BTST if possible.
1919  // Lower (X & (1 << N)) == 0 to BTST(X, N).
1920  // Lower ((X >>u N) & 1) != 0 to BTST(X, N).
1921  // Lower ((X >>s N) & 1) != 0 to BTST(X, N).
1922  // Lower (trunc (X >> N) to i1) to BTST(X, N).
1923  if (Op0.hasOneUse() && isNullConstant(Op1) &&
1924  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1925  if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) {
1926  if (VT == MVT::i1)
1927  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC);
1928  return NewSetCC;
1929  }
1930  }
1931 
1932  // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
1933  // these.
1934  if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
1935  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1936 
1937  // If the input is a setcc, then reuse the input setcc or use a new one with
1938  // the inverted condition.
1939  if (Op0.getOpcode() == M68kISD::SETCC) {
1941  bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
1942  if (!Invert)
1943  return Op0;
1944 
1945  CCode = M68k::GetOppositeBranchCondition(CCode);
1946  SDValue SetCC =
1948  DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1));
1949  if (VT == MVT::i1)
1950  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
1951  return SetCC;
1952  }
1953  }
1954  if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1955  if (isOneConstant(Op1)) {
1957  return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC);
1958  }
1959  if (!isNullConstant(Op1)) {
1960  SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
1961  return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
1962  }
1963  }
1964 
1965  bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
1966  unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
1967  if (M68kCC == M68k::COND_INVALID)
1968  return SDValue();
1969 
1970  SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG);
1971  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1972  DAG.getConstant(M68kCC, DL, MVT::i8), CCR);
1973 }
1974 
1975 SDValue M68kTargetLowering::LowerSETCCCARRY(SDValue Op,
1976  SelectionDAG &DAG) const {
1977  SDValue LHS = Op.getOperand(0);
1978  SDValue RHS = Op.getOperand(1);
1979  SDValue Carry = Op.getOperand(2);
1980  SDValue Cond = Op.getOperand(3);
1981  SDLoc DL(Op);
1982 
1983  assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
1984  M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
1985 
1986  EVT CarryVT = Carry.getValueType();
1987  APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits());
1988  Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry,
1989  DAG.getConstant(NegOne, DL, CarryVT));
1990 
1991  SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
1992  SDValue Cmp =
1993  DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1));
1994 
1995  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1996  DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
1997 }
1998 
1999 /// Return true if opcode is a M68k logical comparison.
2001  unsigned Opc = Op.getNode()->getOpcode();
2002  if (Opc == M68kISD::CMP)
2003  return true;
2004  if (Op.getResNo() == 1 &&
2005  (Opc == M68kISD::ADD || Opc == M68kISD::SUB || Opc == M68kISD::ADDX ||
2006  Opc == M68kISD::SUBX || Opc == M68kISD::SMUL || Opc == M68kISD::UMUL ||
2007  Opc == M68kISD::OR || Opc == M68kISD::XOR || Opc == M68kISD::AND))
2008  return true;
2009 
2010  if (Op.getResNo() == 2 && Opc == M68kISD::UMUL)
2011  return true;
2012 
2013  return false;
2014 }
2015 
2017  if (V.getOpcode() != ISD::TRUNCATE)
2018  return false;
2019 
2020  SDValue VOp0 = V.getOperand(0);
2021  unsigned InBits = VOp0.getValueSizeInBits();
2022  unsigned Bits = V.getValueSizeInBits();
2023  return DAG.MaskedValueIsZero(VOp0,
2024  APInt::getHighBitsSet(InBits, InBits - Bits));
2025 }
2026 
2027 SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2028  bool addTest = true;
2029  SDValue Cond = Op.getOperand(0);
2030  SDValue Op1 = Op.getOperand(1);
2031  SDValue Op2 = Op.getOperand(2);
2032  SDLoc DL(Op);
2033  SDValue CC;
2034 
2035  if (Cond.getOpcode() == ISD::SETCC) {
2036  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2037  Cond = NewCond;
2038  }
2039 
2040  // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2041  // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
2042  // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
2043  // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
2044  if (Cond.getOpcode() == M68kISD::SETCC &&
2045  Cond.getOperand(1).getOpcode() == M68kISD::CMP &&
2046  isNullConstant(Cond.getOperand(1).getOperand(0))) {
2047  SDValue Cmp = Cond.getOperand(1);
2048 
2049  unsigned CondCode =
2050  cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
2051 
2052  if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2054  SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
2055 
2056  SDValue CmpOp0 = Cmp.getOperand(1);
2057  // Apply further optimizations for special cases
2058  // (select (x != 0), -1, 0) -> neg & sbb
2059  // (select (x == 0), 0, -1) -> neg & sbb
2060  if (isNullConstant(Y) &&
2061  (isAllOnesConstant(Op1) == (CondCode == M68k::COND_NE))) {
2062 
2063  SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
2064 
2065  SDValue Neg =
2066  DAG.getNode(M68kISD::SUB, DL, VTs,
2067  DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0);
2068 
2069  SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2071  SDValue(Neg.getNode(), 1));
2072  return Res;
2073  }
2074 
2075  Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2076  DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0);
2077 
2078  SDValue Res = // Res = 0 or -1.
2079  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2080  DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp);
2081 
2082  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_EQ))
2083  Res = DAG.getNOT(DL, Res, Res.getValueType());
2084 
2085  if (!isNullConstant(Op2))
2086  Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
2087  return Res;
2088  }
2089  }
2090 
2091  // Look past (and (setcc_carry (cmp ...)), 1).
2092  if (Cond.getOpcode() == ISD::AND &&
2093  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2094  isOneConstant(Cond.getOperand(1)))
2095  Cond = Cond.getOperand(0);
2096 
2097  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2098  // setting operand in place of the M68kISD::SETCC.
2099  unsigned CondOpcode = Cond.getOpcode();
2100  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2101  CC = Cond.getOperand(0);
2102 
2103  SDValue Cmp = Cond.getOperand(1);
2104  unsigned Opc = Cmp.getOpcode();
2105 
2106  bool IllegalFPCMov = false;
2107 
2108  if ((isM68kLogicalCmp(Cmp) && !IllegalFPCMov) || Opc == M68kISD::BTST) {
2109  Cond = Cmp;
2110  addTest = false;
2111  }
2112  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
2113  CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2114  CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2115  SDValue LHS = Cond.getOperand(0);
2116  SDValue RHS = Cond.getOperand(1);
2117  unsigned MxOpcode;
2118  unsigned MxCond;
2119  SDVTList VTs;
2120  switch (CondOpcode) {
2121  case ISD::UADDO:
2122  MxOpcode = M68kISD::ADD;
2123  MxCond = M68k::COND_CS;
2124  break;
2125  case ISD::SADDO:
2126  MxOpcode = M68kISD::ADD;
2127  MxCond = M68k::COND_VS;
2128  break;
2129  case ISD::USUBO:
2130  MxOpcode = M68kISD::SUB;
2131  MxCond = M68k::COND_CS;
2132  break;
2133  case ISD::SSUBO:
2134  MxOpcode = M68kISD::SUB;
2135  MxCond = M68k::COND_VS;
2136  break;
2137  case ISD::UMULO:
2138  MxOpcode = M68kISD::UMUL;
2139  MxCond = M68k::COND_VS;
2140  break;
2141  case ISD::SMULO:
2142  MxOpcode = M68kISD::SMUL;
2143  MxCond = M68k::COND_VS;
2144  break;
2145  default:
2146  llvm_unreachable("unexpected overflowing operator");
2147  }
2148  if (CondOpcode == ISD::UMULO)
2149  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i32);
2150  else
2151  VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2152 
2153  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2154 
2155  if (CondOpcode == ISD::UMULO)
2156  Cond = MxOp.getValue(2);
2157  else
2158  Cond = MxOp.getValue(1);
2159 
2160  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2161  addTest = false;
2162  }
2163 
2164  if (addTest) {
2165  // Look past the truncate if the high bits are known zero.
2167  Cond = Cond.getOperand(0);
2168 
2169  // We know the result of AND is compared against zero. Try to match
2170  // it to BT.
2171  if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
2172  if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2173  CC = NewSetCC.getOperand(0);
2174  Cond = NewSetCC.getOperand(1);
2175  addTest = false;
2176  }
2177  }
2178  }
2179 
2180  if (addTest) {
2182  Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG);
2183  }
2184 
2185  // a < b ? -1 : 0 -> RES = ~setcc_carry
2186  // a < b ? 0 : -1 -> RES = setcc_carry
2187  // a >= b ? -1 : 0 -> RES = setcc_carry
2188  // a >= b ? 0 : -1 -> RES = ~setcc_carry
2189  if (Cond.getOpcode() == M68kISD::SUB) {
2190  unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
2191 
2192  if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) &&
2193  (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2194  (isNullConstant(Op1) || isNullConstant(Op2))) {
2195  SDValue Res =
2196  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2198  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_CS))
2199  return DAG.getNOT(DL, Res, Res.getValueType());
2200  return Res;
2201  }
2202  }
2203 
2204  // M68k doesn't have an i8 cmov. If both operands are the result of a
2205  // truncate widen the cmov and push the truncate through. This avoids
2206  // introducing a new branch during isel and doesn't add any extensions.
2207  if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE &&
2208  Op2.getOpcode() == ISD::TRUNCATE) {
2209  SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
2210  if (T1.getValueType() == T2.getValueType() &&
2211  // Block CopyFromReg so partial register stalls are avoided.
2212  T1.getOpcode() != ISD::CopyFromReg &&
2213  T2.getOpcode() != ISD::CopyFromReg) {
2214  SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2215  SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2216  return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2217  }
2218  }
2219 
2220  // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2221  // condition is true.
2222  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2223  SDValue Ops[] = {Op2, Op1, CC, Cond};
2224  return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2225 }
2226 
2227 /// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
2228 /// each of which has no other use apart from the AND / OR.
2229 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
2230  Opc = Op.getOpcode();
2231  if (Opc != ISD::OR && Opc != ISD::AND)
2232  return false;
2233  return (M68k::IsSETCC(Op.getOperand(0).getOpcode()) &&
2234  Op.getOperand(0).hasOneUse() &&
2235  M68k::IsSETCC(Op.getOperand(1).getOpcode()) &&
2236  Op.getOperand(1).hasOneUse());
2237 }
2238 
2239 /// Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the
2240 /// SETCC node has a single use.
2241 static bool isXor1OfSetCC(SDValue Op) {
2242  if (Op.getOpcode() != ISD::XOR)
2243  return false;
2244  if (isOneConstant(Op.getOperand(1)))
2245  return Op.getOperand(0).getOpcode() == M68kISD::SETCC &&
2246  Op.getOperand(0).hasOneUse();
2247  return false;
2248 }
2249 
2250 SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2251  bool AddTest = true;
2252  SDValue Chain = Op.getOperand(0);
2253  SDValue Cond = Op.getOperand(1);
2254  SDValue Dest = Op.getOperand(2);
2255  SDLoc DL(Op);
2256  SDValue CC;
2257  bool Inverted = false;
2258 
2259  if (Cond.getOpcode() == ISD::SETCC) {
2260  // Check for setcc([su]{add,sub}o == 0).
2261  if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
2262  isNullConstant(Cond.getOperand(1)) &&
2263  Cond.getOperand(0).getResNo() == 1 &&
2264  (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
2265  Cond.getOperand(0).getOpcode() == ISD::UADDO ||
2266  Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
2267  Cond.getOperand(0).getOpcode() == ISD::USUBO)) {
2268  Inverted = true;
2269  Cond = Cond.getOperand(0);
2270  } else {
2271  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2272  Cond = NewCond;
2273  }
2274  }
2275 
2276  // Look pass (and (setcc_carry (cmp ...)), 1).
2277  if (Cond.getOpcode() == ISD::AND &&
2278  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2279  isOneConstant(Cond.getOperand(1)))
2280  Cond = Cond.getOperand(0);
2281 
2282  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2283  // setting operand in place of the M68kISD::SETCC.
2284  unsigned CondOpcode = Cond.getOpcode();
2285  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2286  CC = Cond.getOperand(0);
2287 
2288  SDValue Cmp = Cond.getOperand(1);
2289  unsigned Opc = Cmp.getOpcode();
2290 
2291  if (isM68kLogicalCmp(Cmp) || Opc == M68kISD::BTST) {
2292  Cond = Cmp;
2293  AddTest = false;
2294  } else {
2295  switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
2296  default:
2297  break;
2298  case M68k::COND_VS:
2299  case M68k::COND_CS:
2300  // These can only come from an arithmetic instruction with overflow,
2301  // e.g. SADDO, UADDO.
2302  Cond = Cond.getNode()->getOperand(1);
2303  AddTest = false;
2304  break;
2305  }
2306  }
2307  }
2308  CondOpcode = Cond.getOpcode();
2309  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2310  CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) {
2311  SDValue LHS = Cond.getOperand(0);
2312  SDValue RHS = Cond.getOperand(1);
2313  unsigned MxOpcode;
2314  unsigned MxCond;
2315  SDVTList VTs;
2316  // Keep this in sync with LowerXALUO, otherwise we might create redundant
2317  // instructions that can't be removed afterwards (i.e. M68kISD::ADD and
2318  // M68kISD::INC).
2319  switch (CondOpcode) {
2320  case ISD::UADDO:
2321  MxOpcode = M68kISD::ADD;
2322  MxCond = M68k::COND_CS;
2323  break;
2324  case ISD::SADDO:
2325  MxOpcode = M68kISD::ADD;
2326  MxCond = M68k::COND_VS;
2327  break;
2328  case ISD::USUBO:
2329  MxOpcode = M68kISD::SUB;
2330  MxCond = M68k::COND_CS;
2331  break;
2332  case ISD::SSUBO:
2333  MxOpcode = M68kISD::SUB;
2334  MxCond = M68k::COND_VS;
2335  break;
2336  case ISD::UMULO:
2337  MxOpcode = M68kISD::UMUL;
2338  MxCond = M68k::COND_VS;
2339  break;
2340  case ISD::SMULO:
2341  MxOpcode = M68kISD::SMUL;
2342  MxCond = M68k::COND_VS;
2343  break;
2344  default:
2345  llvm_unreachable("unexpected overflowing operator");
2346  }
2347 
2348  if (Inverted)
2350 
2351  if (CondOpcode == ISD::UMULO)
2352  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i8);
2353  else
2354  VTs = DAG.getVTList(LHS.getValueType(), MVT::i8);
2355 
2356  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2357 
2358  if (CondOpcode == ISD::UMULO)
2359  Cond = MxOp.getValue(2);
2360  else
2361  Cond = MxOp.getValue(1);
2362 
2363  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2364  AddTest = false;
2365  } else {
2366  unsigned CondOpc;
2367  if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
2368  SDValue Cmp = Cond.getOperand(0).getOperand(1);
2369  if (CondOpc == ISD::OR) {
2370  // Also, recognize the pattern generated by an FCMP_UNE. We can emit
2371  // two branches instead of an explicit OR instruction with a
2372  // separate test.
2373  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp)) {
2374  CC = Cond.getOperand(0).getOperand(0);
2375  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2376  Dest, CC, Cmp);
2377  CC = Cond.getOperand(1).getOperand(0);
2378  Cond = Cmp;
2379  AddTest = false;
2380  }
2381  } else { // ISD::AND
2382  // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
2383  // two branches instead of an explicit AND instruction with a
2384  // separate test. However, we only do this if this block doesn't
2385  // have a fall-through edge, because this requires an explicit
2386  // jmp when the condition is false.
2387  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp) &&
2388  Op.getNode()->hasOneUse()) {
2389  M68k::CondCode CCode =
2390  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2391  CCode = M68k::GetOppositeBranchCondition(CCode);
2392  CC = DAG.getConstant(CCode, DL, MVT::i8);
2393  SDNode *User = *Op.getNode()->use_begin();
2394  // Look for an unconditional branch following this conditional branch.
2395  // We need this because we need to reverse the successors in order
2396  // to implement FCMP_OEQ.
2397  if (User->getOpcode() == ISD::BR) {
2398  SDValue FalseBB = User->getOperand(1);
2399  SDNode *NewBR =
2400  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
2401  assert(NewBR == User);
2402  (void)NewBR;
2403  Dest = FalseBB;
2404 
2405  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2406  Dest, CC, Cmp);
2407  M68k::CondCode CCode =
2408  (M68k::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
2409  CCode = M68k::GetOppositeBranchCondition(CCode);
2410  CC = DAG.getConstant(CCode, DL, MVT::i8);
2411  Cond = Cmp;
2412  AddTest = false;
2413  }
2414  }
2415  }
2416  } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
2417  // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
2418  // It should be transformed during dag combiner except when the condition
2419  // is set by a arithmetics with overflow node.
2420  M68k::CondCode CCode =
2421  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2422  CCode = M68k::GetOppositeBranchCondition(CCode);
2423  CC = DAG.getConstant(CCode, DL, MVT::i8);
2424  Cond = Cond.getOperand(0).getOperand(1);
2425  AddTest = false;
2426  }
2427  }
2428 
2429  if (AddTest) {
2430  // Look pass the truncate if the high bits are known zero.
2432  Cond = Cond.getOperand(0);
2433 
2434  // We know the result is compared against zero. Try to match it to BT.
2435  if (Cond.hasOneUse()) {
2436  if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2437  CC = NewSetCC.getOperand(0);
2438  Cond = NewSetCC.getOperand(1);
2439  AddTest = false;
2440  }
2441  }
2442  }
2443 
2444  if (AddTest) {
2445  M68k::CondCode MxCond = Inverted ? M68k::COND_EQ : M68k::COND_NE;
2446  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2447  Cond = EmitTest(Cond, MxCond, DL, DAG);
2448  }
2449  return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
2450  Cond);
2451 }
2452 
2453 SDValue M68kTargetLowering::LowerADDC_ADDE_SUBC_SUBE(SDValue Op,
2454  SelectionDAG &DAG) const {
2455  MVT VT = Op.getNode()->getSimpleValueType(0);
2456 
2457  // Let legalize expand this if it isn't a legal type yet.
2458  if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2459  return SDValue();
2460 
2461  SDVTList VTs = DAG.getVTList(VT, MVT::i8);
2462 
2463  unsigned Opc;
2464  bool ExtraOp = false;
2465  switch (Op.getOpcode()) {
2466  default:
2467  llvm_unreachable("Invalid code");
2468  case ISD::ADDC:
2469  Opc = M68kISD::ADD;
2470  break;
2471  case ISD::ADDE:
2472  Opc = M68kISD::ADDX;
2473  ExtraOp = true;
2474  break;
2475  case ISD::SUBC:
2476  Opc = M68kISD::SUB;
2477  break;
2478  case ISD::SUBE:
2479  Opc = M68kISD::SUBX;
2480  ExtraOp = true;
2481  break;
2482  }
2483 
2484  if (!ExtraOp)
2485  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2486  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2487  Op.getOperand(2));
2488 }
2489 
2490 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2491 // their target countpart wrapped in the M68kISD::Wrapper node. Suppose N is
2492 // one of the above mentioned nodes. It has to be wrapped because otherwise
2493 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2494 // be used to form addressing mode. These wrapped nodes will be selected
2495 // into MOV32ri.
2496 SDValue M68kTargetLowering::LowerConstantPool(SDValue Op,
2497  SelectionDAG &DAG) const {
2498  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2499 
2500  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2501  // global base reg.
2502  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2503 
2504  unsigned WrapperKind = M68kISD::Wrapper;
2505  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2506  WrapperKind = M68kISD::WrapperPC;
2507  }
2508 
2509  MVT PtrVT = getPointerTy(DAG.getDataLayout());
2511  CP->getConstVal(), PtrVT, CP->getAlign(), CP->getOffset(), OpFlag);
2512 
2513  SDLoc DL(CP);
2514  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2515 
2516  // With PIC, the address is actually $g + Offset.
2517  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2518  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2519  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2520  Result);
2521  }
2522 
2523  return Result;
2524 }
2525 
2526 SDValue M68kTargetLowering::LowerExternalSymbol(SDValue Op,
2527  SelectionDAG &DAG) const {
2528  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2529 
2530  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2531  // global base reg.
2532  const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
2533  unsigned char OpFlag = Subtarget.classifyExternalReference(*Mod);
2534 
2535  unsigned WrapperKind = M68kISD::Wrapper;
2536  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2537  WrapperKind = M68kISD::WrapperPC;
2538  }
2539 
2540  auto PtrVT = getPointerTy(DAG.getDataLayout());
2541  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
2542 
2543  SDLoc DL(Op);
2544  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2545 
2546  // With PIC, the address is actually $g + Offset.
2547  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2548  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2549  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2550  Result);
2551  }
2552 
2553  // For symbols that require a load from a stub to get the address, emit the
2554  // load.
2555  if (M68kII::isGlobalStubReference(OpFlag)) {
2556  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2558  }
2559 
2560  return Result;
2561 }
2562 
2563 SDValue M68kTargetLowering::LowerBlockAddress(SDValue Op,
2564  SelectionDAG &DAG) const {
2565  unsigned char OpFlags = Subtarget.classifyBlockAddressReference();
2566  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2567  int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2568  SDLoc DL(Op);
2569  auto PtrVT = getPointerTy(DAG.getDataLayout());
2570 
2571  // Create the TargetBlockAddressAddress node.
2572  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
2573 
2574  if (M68kII::isPCRelBlockReference(OpFlags)) {
2575  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2576  } else {
2577  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2578  }
2579 
2580  // With PIC, the address is actually $g + Offset.
2581  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2582  Result =
2583  DAG.getNode(ISD::ADD, DL, PtrVT,
2584  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2585  }
2586 
2587  return Result;
2588 }
2589 
2590 SDValue M68kTargetLowering::LowerGlobalAddress(const GlobalValue *GV,
2591  const SDLoc &DL, int64_t Offset,
2592  SelectionDAG &DAG) const {
2593  unsigned char OpFlags = Subtarget.classifyGlobalReference(GV);
2594  auto PtrVT = getPointerTy(DAG.getDataLayout());
2595 
2596  // Create the TargetGlobalAddress node, folding in the constant
2597  // offset if it is legal.
2598  SDValue Result;
2599  if (M68kII::isDirectGlobalReference(OpFlags)) {
2600  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
2601  Offset = 0;
2602  } else {
2603  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2604  }
2605 
2606  if (M68kII::isPCRelGlobalReference(OpFlags))
2607  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2608  else
2609  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2610 
2611  // With PIC, the address is actually $g + Offset.
2612  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2613  Result =
2614  DAG.getNode(ISD::ADD, DL, PtrVT,
2615  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2616  }
2617 
2618  // For globals that require a load from a stub to get the address, emit the
2619  // load.
2620  if (M68kII::isGlobalStubReference(OpFlags)) {
2621  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2623  }
2624 
2625  // If there was a non-zero offset that we didn't fold, create an explicit
2626  // addition for it.
2627  if (Offset != 0) {
2628  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2629  DAG.getConstant(Offset, DL, PtrVT));
2630  }
2631 
2632  return Result;
2633 }
2634 
2635 SDValue M68kTargetLowering::LowerGlobalAddress(SDValue Op,
2636  SelectionDAG &DAG) const {
2637  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2638  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2639  return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
2640 }
2641 
2642 //===----------------------------------------------------------------------===//
2643 // Custom Lower Jump Table
2644 //===----------------------------------------------------------------------===//
2645 
2646 SDValue M68kTargetLowering::LowerJumpTable(SDValue Op,
2647  SelectionDAG &DAG) const {
2648  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2649 
2650  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2651  // global base reg.
2652  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2653 
2654  unsigned WrapperKind = M68kISD::Wrapper;
2655  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2656  WrapperKind = M68kISD::WrapperPC;
2657  }
2658 
2659  auto PtrVT = getPointerTy(DAG.getDataLayout());
2660  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
2661  SDLoc DL(JT);
2662  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2663 
2664  // With PIC, the address is actually $g + Offset.
2665  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2666  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2667  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2668  Result);
2669  }
2670 
2671  return Result;
2672 }
2673 
2675  return Subtarget.getJumpTableEncoding();
2676 }
2677 
2679  const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
2680  unsigned uid, MCContext &Ctx) const {
2682  Ctx);
2683 }
2684 
2686  SelectionDAG &DAG) const {
2688  return DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(),
2689  getPointerTy(DAG.getDataLayout()));
2690 
2691  // MachineJumpTableInfo::EK_LabelDifference32 entry
2692  return Table;
2693 }
2694 
2695 // NOTE This only used for MachineJumpTableInfo::EK_LabelDifference32 entries
2697  const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const {
2698  return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
2699 }
2700 
2703  if (Constraint.size() > 0) {
2704  switch (Constraint[0]) {
2705  case 'a':
2706  case 'd':
2707  return C_RegisterClass;
2708  case 'I':
2709  case 'J':
2710  case 'K':
2711  case 'L':
2712  case 'M':
2713  case 'N':
2714  case 'O':
2715  case 'P':
2716  return C_Immediate;
2717  case 'C':
2718  if (Constraint.size() == 2)
2719  switch (Constraint[1]) {
2720  case '0':
2721  case 'i':
2722  case 'j':
2723  return C_Immediate;
2724  default:
2725  break;
2726  }
2727  break;
2728  default:
2729  break;
2730  }
2731  }
2732 
2733  return TargetLowering::getConstraintType(Constraint);
2734 }
2735 
2737  std::string &Constraint,
2738  std::vector<SDValue> &Ops,
2739  SelectionDAG &DAG) const {
2740  SDValue Result;
2741 
2742  if (Constraint.size() == 1) {
2743  // Constant constraints
2744  switch (Constraint[0]) {
2745  case 'I':
2746  case 'J':
2747  case 'K':
2748  case 'L':
2749  case 'M':
2750  case 'N':
2751  case 'O':
2752  case 'P': {
2753  auto *C = dyn_cast<ConstantSDNode>(Op);
2754  if (!C)
2755  return;
2756 
2757  int64_t Val = C->getSExtValue();
2758  switch (Constraint[0]) {
2759  case 'I': // constant integer in the range [1,8]
2760  if (Val > 0 && Val <= 8)
2761  break;
2762  return;
2763  case 'J': // constant signed 16-bit integer
2764  if (isInt<16>(Val))
2765  break;
2766  return;
2767  case 'K': // constant that is NOT in the range of [-0x80, 0x80)
2768  if (Val < -0x80 || Val >= 0x80)
2769  break;
2770  return;
2771  case 'L': // constant integer in the range [-8,-1]
2772  if (Val < 0 && Val >= -8)
2773  break;
2774  return;
2775  case 'M': // constant that is NOT in the range of [-0x100, 0x100]
2776  if (Val < -0x100 || Val >= 0x100)
2777  break;
2778  return;
2779  case 'N': // constant integer in the range [24,31]
2780  if (Val >= 24 && Val <= 31)
2781  break;
2782  return;
2783  case 'O': // constant integer 16
2784  if (Val == 16)
2785  break;
2786  return;
2787  case 'P': // constant integer in the range [8,15]
2788  if (Val >= 8 && Val <= 15)
2789  break;
2790  return;
2791  default:
2792  llvm_unreachable("Unhandled constant constraint");
2793  }
2794 
2795  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2796  break;
2797  }
2798  default:
2799  break;
2800  }
2801  }
2802 
2803  if (Constraint.size() == 2) {
2804  switch (Constraint[0]) {
2805  case 'C':
2806  // Constant constraints start with 'C'
2807  switch (Constraint[1]) {
2808  case '0':
2809  case 'i':
2810  case 'j': {
2811  auto *C = dyn_cast<ConstantSDNode>(Op);
2812  if (!C)
2813  break;
2814 
2815  int64_t Val = C->getSExtValue();
2816  switch (Constraint[1]) {
2817  case '0': // constant integer 0
2818  if (!Val)
2819  break;
2820  return;
2821  case 'i': // constant integer
2822  break;
2823  case 'j': // integer constant that doesn't fit in 16 bits
2824  if (!isInt<16>(C->getSExtValue()))
2825  break;
2826  return;
2827  default:
2828  llvm_unreachable("Unhandled constant constraint");
2829  }
2830 
2831  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2832  break;
2833  }
2834  default:
2835  break;
2836  }
2837  break;
2838  default:
2839  break;
2840  }
2841  }
2842 
2843  if (Result.getNode()) {
2844  Ops.push_back(Result);
2845  return;
2846  }
2847 
2848  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2849 }
2850 
2851 std::pair<unsigned, const TargetRegisterClass *>
2853  StringRef Constraint,
2854  MVT VT) const {
2855  if (Constraint.size() == 1) {
2856  switch (Constraint[0]) {
2857  case 'r':
2858  case 'd':
2859  switch (VT.SimpleTy) {
2860  case MVT::i8:
2861  return std::make_pair(0U, &M68k::DR8RegClass);
2862  case MVT::i16:
2863  return std::make_pair(0U, &M68k::DR16RegClass);
2864  case MVT::i32:
2865  return std::make_pair(0U, &M68k::DR32RegClass);
2866  default:
2867  break;
2868  }
2869  break;
2870  case 'a':
2871  switch (VT.SimpleTy) {
2872  case MVT::i16:
2873  return std::make_pair(0U, &M68k::AR16RegClass);
2874  case MVT::i32:
2875  return std::make_pair(0U, &M68k::AR32RegClass);
2876  default:
2877  break;
2878  }
2879  break;
2880  default:
2881  break;
2882  }
2883  }
2884 
2885  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2886 }
2887 
2888 /// Determines whether the callee is required to pop its own arguments.
2889 /// Callee pop is necessary to support tail calls.
2891  bool GuaranteeTCO) {
2892  return false;
2893 }
2894 
2895 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
2896 // together with other CMOV pseudo-opcodes into a single basic-block with
2897 // conditional jump around it.
2899  switch (MI.getOpcode()) {
2900  case M68k::CMOV8d:
2901  case M68k::CMOV16d:
2902  case M68k::CMOV32r:
2903  return true;
2904 
2905  default:
2906  return false;
2907  }
2908 }
2909 
2910 // The CCR operand of SelectItr might be missing a kill marker
2911 // because there were multiple uses of CCR, and ISel didn't know
2912 // which to mark. Figure out whether SelectItr should have had a
2913 // kill marker, and set it if it should. Returns the correct kill
2914 // marker value.
2917  const TargetRegisterInfo *TRI) {
2918  // Scan forward through BB for a use/def of CCR.
2919  MachineBasicBlock::iterator miI(std::next(SelectItr));
2920  for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
2921  const MachineInstr &mi = *miI;
2922  if (mi.readsRegister(M68k::CCR))
2923  return false;
2924  if (mi.definesRegister(M68k::CCR))
2925  break; // Should have kill-flag - update below.
2926  }
2927 
2928  // If we hit the end of the block, check whether CCR is live into a
2929  // successor.
2930  if (miI == BB->end())
2931  for (const auto *SBB : BB->successors())
2932  if (SBB->isLiveIn(M68k::CCR))
2933  return false;
2934 
2935  // We found a def, or hit the end of the basic block and CCR wasn't live
2936  // out. SelectMI should have a kill flag on CCR.
2937  SelectItr->addRegisterKilled(M68k::CCR, TRI);
2938  return true;
2939 }
2940 
2942 M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
2943  MachineBasicBlock *MBB) const {
2944  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2945  DebugLoc DL = MI.getDebugLoc();
2946 
2947  // To "insert" a SELECT_CC instruction, we actually have to insert the
2948  // diamond control-flow pattern. The incoming instruction knows the
2949  // destination vreg to set, the condition code register to branch on, the
2950  // true/false values to select between, and a branch opcode to use.
2951  const BasicBlock *BB = MBB->getBasicBlock();
2953 
2954  // ThisMBB:
2955  // ...
2956  // TrueVal = ...
2957  // cmp ccX, r1, r2
2958  // bcc Copy1MBB
2959  // fallthrough --> Copy0MBB
2960  MachineBasicBlock *ThisMBB = MBB;
2962 
2963  // This code lowers all pseudo-CMOV instructions. Generally it lowers these
2964  // as described above, by inserting a MBB, and then making a PHI at the join
2965  // point to select the true and false operands of the CMOV in the PHI.
2966  //
2967  // The code also handles two different cases of multiple CMOV opcodes
2968  // in a row.
2969  //
2970  // Case 1:
2971  // In this case, there are multiple CMOVs in a row, all which are based on
2972  // the same condition setting (or the exact opposite condition setting).
2973  // In this case we can lower all the CMOVs using a single inserted MBB, and
2974  // then make a number of PHIs at the join point to model the CMOVs. The only
2975  // trickiness here, is that in a case like:
2976  //
2977  // t2 = CMOV cond1 t1, f1
2978  // t3 = CMOV cond1 t2, f2
2979  //
2980  // when rewriting this into PHIs, we have to perform some renaming on the
2981  // temps since you cannot have a PHI operand refer to a PHI result earlier
2982  // in the same block. The "simple" but wrong lowering would be:
2983  //
2984  // t2 = PHI t1(BB1), f1(BB2)
2985  // t3 = PHI t2(BB1), f2(BB2)
2986  //
2987  // but clearly t2 is not defined in BB1, so that is incorrect. The proper
2988  // renaming is to note that on the path through BB1, t2 is really just a
2989  // copy of t1, and do that renaming, properly generating:
2990  //
2991  // t2 = PHI t1(BB1), f1(BB2)
2992  // t3 = PHI t1(BB1), f2(BB2)
2993  //
2994  // Case 2, we lower cascaded CMOVs such as
2995  //
2996  // (CMOV (CMOV F, T, cc1), T, cc2)
2997  //
2998  // to two successives branches.
2999  MachineInstr *CascadedCMOV = nullptr;
3000  MachineInstr *LastCMOV = &MI;
3001  M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
3003  MachineBasicBlock::iterator NextMIIt =
3004  std::next(MachineBasicBlock::iterator(MI));
3005 
3006  // Check for case 1, where there are multiple CMOVs with the same condition
3007  // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
3008  // number of jumps the most.
3009 
3010  if (isCMOVPseudo(MI)) {
3011  // See if we have a string of CMOVS with the same condition.
3012  while (NextMIIt != MBB->end() && isCMOVPseudo(*NextMIIt) &&
3013  (NextMIIt->getOperand(3).getImm() == CC ||
3014  NextMIIt->getOperand(3).getImm() == OppCC)) {
3015  LastCMOV = &*NextMIIt;
3016  ++NextMIIt;
3017  }
3018  }
3019 
3020  // This checks for case 2, but only do this if we didn't already find
3021  // case 1, as indicated by LastCMOV == MI.
3022  if (LastCMOV == &MI && NextMIIt != MBB->end() &&
3023  NextMIIt->getOpcode() == MI.getOpcode() &&
3024  NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
3025  NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
3026  NextMIIt->getOperand(1).isKill()) {
3027  CascadedCMOV = &*NextMIIt;
3028  }
3029 
3030  MachineBasicBlock *Jcc1MBB = nullptr;
3031 
3032  // If we have a cascaded CMOV, we lower it to two successive branches to
3033  // the same block. CCR is used by both, so mark it as live in the second.
3034  if (CascadedCMOV) {
3035  Jcc1MBB = F->CreateMachineBasicBlock(BB);
3036  F->insert(It, Jcc1MBB);
3037  Jcc1MBB->addLiveIn(M68k::CCR);
3038  }
3039 
3040  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(BB);
3041  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
3042  F->insert(It, Copy0MBB);
3043  F->insert(It, SinkMBB);
3044 
3045  // If the CCR register isn't dead in the terminator, then claim that it's
3046  // live into the sink and copy blocks.
3047  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3048 
3049  MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3050  if (!LastCCRSUser->killsRegister(M68k::CCR) &&
3051  !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) {
3052  Copy0MBB->addLiveIn(M68k::CCR);
3053  SinkMBB->addLiveIn(M68k::CCR);
3054  }
3055 
3056  // Transfer the remainder of MBB and its successor edges to SinkMBB.
3057  SinkMBB->splice(SinkMBB->begin(), MBB,
3058  std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
3060 
3061  // Add the true and fallthrough blocks as its successors.
3062  if (CascadedCMOV) {
3063  // The fallthrough block may be Jcc1MBB, if we have a cascaded CMOV.
3064  MBB->addSuccessor(Jcc1MBB);
3065 
3066  // In that case, Jcc1MBB will itself fallthrough the Copy0MBB, and
3067  // jump to the SinkMBB.
3068  Jcc1MBB->addSuccessor(Copy0MBB);
3069  Jcc1MBB->addSuccessor(SinkMBB);
3070  } else {
3071  MBB->addSuccessor(Copy0MBB);
3072  }
3073 
3074  // The true block target of the first (or only) branch is always SinkMBB.
3075  MBB->addSuccessor(SinkMBB);
3076 
3077  // Create the conditional branch instruction.
3078  unsigned Opc = M68k::GetCondBranchFromCond(CC);
3079  BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB);
3080 
3081  if (CascadedCMOV) {
3082  unsigned Opc2 = M68k::GetCondBranchFromCond(
3083  (M68k::CondCode)CascadedCMOV->getOperand(3).getImm());
3084  BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
3085  }
3086 
3087  // Copy0MBB:
3088  // %FalseValue = ...
3089  // # fallthrough to SinkMBB
3090  Copy0MBB->addSuccessor(SinkMBB);
3091 
3092  // SinkMBB:
3093  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
3094  // ...
3096  MachineBasicBlock::iterator MIItEnd =
3097  std::next(MachineBasicBlock::iterator(LastCMOV));
3098  MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
3100  MachineInstrBuilder MIB;
3101 
3102  // As we are creating the PHIs, we have to be careful if there is more than
3103  // one. Later CMOVs may reference the results of earlier CMOVs, but later
3104  // PHIs have to reference the individual true/false inputs from earlier PHIs.
3105  // That also means that PHI construction must work forward from earlier to
3106  // later, and that the code must maintain a mapping from earlier PHI's
3107  // destination registers, and the registers that went into the PHI.
3108 
3109  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
3110  Register DestReg = MIIt->getOperand(0).getReg();
3111  Register Op1Reg = MIIt->getOperand(1).getReg();
3112  Register Op2Reg = MIIt->getOperand(2).getReg();
3113 
3114  // If this CMOV we are generating is the opposite condition from
3115  // the jump we generated, then we have to swap the operands for the
3116  // PHI that is going to be generated.
3117  if (MIIt->getOperand(3).getImm() == OppCC)
3118  std::swap(Op1Reg, Op2Reg);
3119 
3120  if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
3121  Op1Reg = RegRewriteTable[Op1Reg].first;
3122 
3123  if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
3124  Op2Reg = RegRewriteTable[Op2Reg].second;
3125 
3126  MIB =
3127  BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg)
3128  .addReg(Op1Reg)
3129  .addMBB(Copy0MBB)
3130  .addReg(Op2Reg)
3131  .addMBB(ThisMBB);
3132 
3133  // Add this PHI to the rewrite table.
3134  RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3135  }
3136 
3137  // If we have a cascaded CMOV, the second Jcc provides the same incoming
3138  // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
3139  if (CascadedCMOV) {
3140  MIB.addReg(MI.getOperand(2).getReg()).addMBB(Jcc1MBB);
3141  // Copy the PHI result to the register defined by the second CMOV.
3142  BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
3143  DL, TII->get(TargetOpcode::COPY),
3144  CascadedCMOV->getOperand(0).getReg())
3145  .addReg(MI.getOperand(0).getReg());
3146  CascadedCMOV->eraseFromParent();
3147  }
3148 
3149  // Now remove the CMOV(s).
3150  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;)
3151  (MIIt++)->eraseFromParent();
3152 
3153  return SinkMBB;
3154 }
3155 
3157 M68kTargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
3158  MachineBasicBlock *BB) const {
3159  llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on");
3160 }
3161 
3164  MachineBasicBlock *BB) const {
3165  switch (MI.getOpcode()) {
3166  default:
3167  llvm_unreachable("Unexpected instr type to insert");
3168  case M68k::CMOV8d:
3169  case M68k::CMOV16d:
3170  case M68k::CMOV32r:
3171  return EmitLoweredSelect(MI, BB);
3172  case M68k::SALLOCA:
3173  return EmitLoweredSegAlloca(MI, BB);
3174  }
3175 }
3176 
3177 SDValue M68kTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3178  MachineFunction &MF = DAG.getMachineFunction();
3179  auto PtrVT = getPointerTy(MF.getDataLayout());
3181 
3182  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3183  SDLoc DL(Op);
3184 
3185  // vastart just stores the address of the VarArgsFrameIndex slot into the
3186  // memory location argument.
3187  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3188  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3189  MachinePointerInfo(SV));
3190 }
3191 
3192 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3193 // Calls to _alloca are needed to probe the stack when allocating more than 4k
3194 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3195 // that the guard pages used by the OS virtual memory manager are allocated in
3196 // correct sequence.
3197 SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3198  SelectionDAG &DAG) const {
3199  MachineFunction &MF = DAG.getMachineFunction();
3200  bool SplitStack = MF.shouldSplitStack();
3201 
3202  SDLoc DL(Op);
3203 
3204  // Get the inputs.
3205  SDNode *Node = Op.getNode();
3206  SDValue Chain = Op.getOperand(0);
3207  SDValue Size = Op.getOperand(1);
3208  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3209  EVT VT = Node->getValueType(0);
3210 
3211  // Chain the dynamic stack allocation so that it doesn't modify the stack
3212  // pointer when other instructions are using the stack.
3213  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3214 
3215  SDValue Result;
3216  if (SplitStack) {
3217  auto &MRI = MF.getRegInfo();
3218  auto SPTy = getPointerTy(DAG.getDataLayout());
3219  auto *ARClass = getRegClassFor(SPTy);
3220  Register Vreg = MRI.createVirtualRegister(ARClass);
3221  Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
3222  Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
3223  DAG.getRegister(Vreg, SPTy));
3224  } else {
3225  auto &TLI = DAG.getTargetLoweringInfo();
3227  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3228  " not tell us which reg is the stack pointer!");
3229 
3230  SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3231  Chain = SP.getValue(1);
3232  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3233  unsigned StackAlign = TFI.getStackAlignment();
3234  Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value
3235  if (Align > StackAlign)
3236  Result = DAG.getNode(ISD::AND, DL, VT, Result,
3237  DAG.getConstant(-(uint64_t)Align, DL, VT));
3238  Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
3239  }
3240 
3241  Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), DL);
3242 
3243  SDValue Ops[2] = {Result, Chain};
3244  return DAG.getMergeValues(Ops, DL);
3245 }
3246 
3247 SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
3248  SelectionDAG &DAG) const {
3249  SDLoc DL(Op);
3250  SDValue Lo = Op.getOperand(0);
3251  SDValue Hi = Op.getOperand(1);
3252  SDValue Shamt = Op.getOperand(2);
3253  EVT VT = Lo.getValueType();
3254 
3255  // if Shamt - register size < 0: // Shamt < register size
3256  // Lo = Lo << Shamt
3257  // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
3258  // else:
3259  // Lo = 0
3260  // Hi = Lo << (Shamt - register size)
3261 
3262  SDValue Zero = DAG.getConstant(0, DL, VT);
3263  SDValue One = DAG.getConstant(1, DL, VT);
3264  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3265  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3266  SDValue ShamtMinusRegisterSize =
3267  DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3268  SDValue RegisterSizeMinus1Shamt =
3269  DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3270 
3271  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
3272  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
3273  SDValue ShiftRightLo =
3274  DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
3275  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
3276  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
3277  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
3278 
3279  SDValue CC =
3280  DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3281 
3282  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
3283  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3284 
3285  return DAG.getMergeValues({Lo, Hi}, DL);
3286 }
3287 
3288 SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
3289  bool IsSRA) const {
3290  SDLoc DL(Op);
3291  SDValue Lo = Op.getOperand(0);
3292  SDValue Hi = Op.getOperand(1);
3293  SDValue Shamt = Op.getOperand(2);
3294  EVT VT = Lo.getValueType();
3295 
3296  // SRA expansion:
3297  // if Shamt - register size < 0: // Shamt < register size
3298  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3299  // Hi = Hi >>s Shamt
3300  // else:
3301  // Lo = Hi >>s (Shamt - register size);
3302  // Hi = Hi >>s (register size - 1)
3303  //
3304  // SRL expansion:
3305  // if Shamt - register size < 0: // Shamt < register size
3306  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3307  // Hi = Hi >>u Shamt
3308  // else:
3309  // Lo = Hi >>u (Shamt - register size);
3310  // Hi = 0;
3311 
3312  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
3313 
3314  SDValue Zero = DAG.getConstant(0, DL, VT);
3315  SDValue One = DAG.getConstant(1, DL, VT);
3316  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3317  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3318  SDValue ShamtMinusRegisterSize =
3319  DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3320  SDValue RegisterSizeMinus1Shamt =
3321  DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3322 
3323  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
3324  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
3325  SDValue ShiftLeftHi =
3326  DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
3327  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
3328  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
3329  SDValue LoFalse =
3330  DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
3331  SDValue HiFalse =
3332  IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
3333 
3334  SDValue CC =
3335  DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3336 
3337  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
3338  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3339 
3340  return DAG.getMergeValues({Lo, Hi}, DL);
3341 }
3342 
3343 //===----------------------------------------------------------------------===//
3344 // DAG Combine
3345 //===----------------------------------------------------------------------===//
3346 
3348  SelectionDAG &DAG) {
3349  return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
3350  DAG.getConstant(Cond, dl, MVT::i8), CCR);
3351 }
3352 // When legalizing carry, we create carries via add X, -1
3353 // If that comes from an actual carry, via setcc, we use the
3354 // carry directly.
3356  if (CCR.getOpcode() == M68kISD::ADD) {
3357  if (isAllOnesConstant(CCR.getOperand(1))) {
3358  SDValue Carry = CCR.getOperand(0);
3359  while (Carry.getOpcode() == ISD::TRUNCATE ||
3360  Carry.getOpcode() == ISD::ZERO_EXTEND ||
3361  Carry.getOpcode() == ISD::SIGN_EXTEND ||
3362  Carry.getOpcode() == ISD::ANY_EXTEND ||
3363  (Carry.getOpcode() == ISD::AND &&
3364  isOneConstant(Carry.getOperand(1))))
3365  Carry = Carry.getOperand(0);
3366  if (Carry.getOpcode() == M68kISD::SETCC ||
3367  Carry.getOpcode() == M68kISD::SETCC_CARRY) {
3368  if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
3369  return Carry.getOperand(1);
3370  }
3371  }
3372  }
3373 
3374  return SDValue();
3375 }
3376 
3377 /// Optimize a CCR definition used according to the condition code \p CC into
3378 /// a simpler CCR value, potentially returning a new \p CC and replacing uses
3379 /// of chain values.
3381  SelectionDAG &DAG,
3382  const M68kSubtarget &Subtarget) {
3383  if (CC == M68k::COND_CS)
3384  if (SDValue Flags = combineCarryThroughADD(CCR))
3385  return Flags;
3386 
3387  return SDValue();
3388 }
3389 
3390 // Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
3392  const M68kSubtarget &Subtarget) {
3393  SDLoc DL(N);
3394  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3395  SDValue CCR = N->getOperand(1);
3396 
3397  // Try to simplify the CCR and condition code operands.
3398  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3399  return getSETCC(CC, Flags, DL, DAG);
3400 
3401  return SDValue();
3402 }
3404  const M68kSubtarget &Subtarget) {
3405  SDLoc DL(N);
3406  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3407  SDValue CCR = N->getOperand(3);
3408 
3409  // Try to simplify the CCR and condition code operands.
3410  // Make sure to not keep references to operands, as combineSetCCCCR can
3411  // RAUW them under us.
3412  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3413  SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3414  return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
3415  N->getOperand(1), Cond, Flags);
3416  }
3417 
3418  return SDValue();
3419 }
3420 
3422  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3423  MVT VT = N->getSimpleValueType(0);
3424  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3425  return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
3426  N->getOperand(1), Flags);
3427  }
3428 
3429  return SDValue();
3430 }
3431 
3432 // Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
3435  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3436  MVT VT = N->getSimpleValueType(0);
3437  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3438  return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
3439  N->getOperand(1), Flags);
3440  }
3441 
3442  return SDValue();
3443 }
3444 
3445 SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
3446  DAGCombinerInfo &DCI) const {
3447  SelectionDAG &DAG = DCI.DAG;
3448  switch (N->getOpcode()) {
3449  case M68kISD::SUBX:
3450  return combineSUBX(N, DAG);
3451  case M68kISD::ADDX:
3452  return combineADDX(N, DAG, DCI);
3453  case M68kISD::SETCC:
3454  return combineM68kSetCC(N, DAG, Subtarget);
3455  case M68kISD::BRCOND:
3456  return combineM68kBrCond(N, DAG, Subtarget);
3457  }
3458 
3459  return SDValue();
3460 }
3461 
3462 //===----------------------------------------------------------------------===//
3463 // M68kISD Node Names
3464 //===----------------------------------------------------------------------===//
3465 const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
3466  switch (Opcode) {
3467  case M68kISD::CALL:
3468  return "M68kISD::CALL";
3469  case M68kISD::TAIL_CALL:
3470  return "M68kISD::TAIL_CALL";
3471  case M68kISD::RET:
3472  return "M68kISD::RET";
3473  case M68kISD::TC_RETURN:
3474  return "M68kISD::TC_RETURN";
3475  case M68kISD::ADD:
3476  return "M68kISD::ADD";
3477  case M68kISD::SUB:
3478  return "M68kISD::SUB";
3479  case M68kISD::ADDX:
3480  return "M68kISD::ADDX";
3481  case M68kISD::SUBX:
3482  return "M68kISD::SUBX";
3483  case M68kISD::SMUL:
3484  return "M68kISD::SMUL";
3485  case M68kISD::UMUL:
3486  return "M68kISD::UMUL";
3487  case M68kISD::OR:
3488  return "M68kISD::OR";
3489  case M68kISD::XOR:
3490  return "M68kISD::XOR";
3491  case M68kISD::AND:
3492  return "M68kISD::AND";
3493  case M68kISD::CMP:
3494  return "M68kISD::CMP";
3495  case M68kISD::BTST:
3496  return "M68kISD::BTST";
3497  case M68kISD::SELECT:
3498  return "M68kISD::SELECT";
3499  case M68kISD::CMOV:
3500  return "M68kISD::CMOV";
3501  case M68kISD::BRCOND:
3502  return "M68kISD::BRCOND";
3503  case M68kISD::SETCC:
3504  return "M68kISD::SETCC";
3505  case M68kISD::SETCC_CARRY:
3506  return "M68kISD::SETCC_CARRY";
3508  return "M68kISD::GLOBAL_BASE_REG";
3509  case M68kISD::Wrapper:
3510  return "M68kISD::Wrapper";
3511  case M68kISD::WrapperPC:
3512  return "M68kISD::WrapperPC";
3513  case M68kISD::SEG_ALLOCA:
3514  return "M68kISD::SEG_ALLOCA";
3515  default:
3516  return NULL;
3517  }
3518 }
3519 
3521  bool IsVarArg) const {
3522  if (Return)
3523  return RetCC_M68k_C;
3524  else
3525  return CC_M68k_C;
3526 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
Definition: SelectionDAG.cpp:7268
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::ArgFlagsTy::isInAlloca
bool isInAlloca() const
Definition: TargetCallingConv.h:91
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1437
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
llvm::MachineFrameInfo::isObjectZExt
bool isObjectZExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:526
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1581
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
llvm::M68kTargetLowering::getCCAssignFn
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: M68kISelLowering.cpp:3520
llvm::M68kTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: M68kISelLowering.cpp:2852
llvm::M68kISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: M68kISelLowering.h:87
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1819
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:967
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1448
TranslateIntegerM68kCC
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
Definition: M68kISelLowering.cpp:1490
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::M68kTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: M68kISelLowering.cpp:2678
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
llvm::M68kISD::SUBX
@ SUBX
Definition: M68kISelLowering.h:75
LowerAndToBTST
static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BTST node if possible.
Definition: M68kISelLowering.cpp:1442
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::M68kISD::BRCOND
@ BRCOND
M68k conditional branches.
Definition: M68kISelLowering.h:69
llvm::M68kTargetMachine
Definition: M68kTargetMachine.h:29
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::M68kMachineFunctionInfo::setArgumentStackSize
void setArgumentStackSize(unsigned size)
Definition: M68kMachineFunction.h:105
llvm::ISD::ArgFlagsTy::isSRet
bool isSRet() const
Definition: TargetCallingConv.h:82
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:221
llvm::TargetLowering::CallLoweringInfo::RetTy
Type * RetTy
Definition: TargetLowering.h:4081
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:765
M68kTargetMachine.h
llvm::M68kISD::SETCC
@ SETCC
M68k SetCC.
Definition: M68kISelLowering.h:53
llvm::M68k::CondCode
CondCode
Definition: M68kInstrInfo.h:34
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1103
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:195
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1445
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1449
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4495
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:991
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
llvm::M68kTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: M68kISelLowering.cpp:3163
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:764
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:159
llvm::isOneConstant
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Definition: SelectionDAG.cpp:10740
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::M68kISD::SELECT
@ SELECT
M68k Select.
Definition: M68kISelLowering.h:49
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:976
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1839
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::M68k::COND_PL
@ COND_PL
Definition: M68kInstrInfo.h:45
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1720
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
Statistic.h
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1444
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1057
llvm::M68kISD::ADD
@ ADD
Definition: M68kISelLowering.h:72
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9316
TranslateM68kCC
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
Definition: M68kISelLowering.cpp:1520
llvm::M68k::COND_GT
@ COND_GT
Definition: M68kInstrInfo.h:49
llvm::ISD::GlobalISel::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:560
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
ErrorHandling.h
llvm::M68kCCState
Custom state to propagate llvm type info to register CC assigner.
Definition: M68kCallingConv.h:27
llvm::isBitwiseNot
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
Definition: SelectionDAG.cpp:10829
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::M68k::COND_NE
@ COND_NE
Definition: M68kInstrInfo.h:41
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::CallingConv::M68k_INTR
@ M68k_INTR
Used for M68k interrupt routines.
Definition: CallingConv.h:236
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::SelectionDAG::ReplaceAllUsesWith
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
Definition: SelectionDAG.cpp:10188
llvm::M68kII::isPCRelBlockReference
static bool isPCRelBlockReference(unsigned char Flag)
Return True if the Block is referenced using PC.
Definition: M68kBaseInfo.h:167
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:272
llvm::CCValAssign::Indirect
@ Indirect
Definition: CallingConvLower.h:50
llvm::M68kRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: M68kRegisterInfo.h:108
llvm::SDNode::use_iterator
This class provides iterator support for SDUse operands that use a specific SDNode.
Definition: SelectionDAGNodes.h:743
llvm::M68kRegisterInfo
Definition: M68kRegisterInfo.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
LowerTruncateToBTST
static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:1601
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1439
MachineJumpTableInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7976
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
isXor1OfSetCC
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
Definition: M68kISelLowering.cpp:2241
llvm::CallBase::isMustTailCall
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: Instructions.cpp:299
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:4106
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2482
llvm::M68kII::isDirectGlobalReference
static bool isDirectGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue is a direct reference for a symbol.
Definition: M68kBaseInfo.h:131
hasNonFlagsUse
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
Definition: M68kISelLowering.cpp:1616
llvm::M68k::COND_VS
@ COND_VS
Definition: M68kInstrInfo.h:44
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1086
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1404
llvm::MachineFunction::getJTISymbol
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
Definition: MachineFunction.cpp:704
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::M68kSubtarget::getRegisterInfo
const M68kRegisterInfo * getRegisterInfo() const override
Definition: M68kSubtarget.h:154
llvm::MCSymbolRefExpr::VK_GOTOFF
@ VK_GOTOFF
Definition: MCExpr.h:199
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1427
llvm::EVT::bitsLE
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:280
llvm::M68kMachineFunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: M68kMachineFunction.h:107
llvm::M68kISD::CALL
@ CALL
Definition: M68kISelLowering.h:35
SelectionDAG.h
llvm::MachineJumpTableInfo::EK_Custom32
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Definition: MachineJumpTableInfo.h:76
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1435
combineCarryThroughADD
static SDValue combineCarryThroughADD(SDValue CCR)
Definition: M68kISelLowering.cpp:3355
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:476
llvm::M68k::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: M68kISelLowering.cpp:2890
llvm::M68kTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: M68kISelLowering.cpp:2674
F
#define F(x, y, z)
Definition: MD5.cpp:55
M68kTargetObjectFile.h
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:1001
MachineRegisterInfo.h
KnownBits.h
llvm::M68kTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: M68kISelLowering.cpp:2696
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2102
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::M68kII::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Return true if the specified TargetFlag operand is a reference to a stub for a global,...
Definition: M68kBaseInfo.h:119
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1472
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:58
shouldGuaranteeTCO
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
Definition: M68kISelLowering.cpp:240
CommandLine.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1008
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7926
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:95
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:4084
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::M68kSubtarget::classifyBlockAddressReference
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
Definition: M68kSubtarget.cpp:146
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2235
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:154
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1138
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:58
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition: M68kSubtarget.h:148
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::SelectionDAG::UpdateNodeOperands
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
Definition: SelectionDAG.cpp:9406
llvm::SDNode::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: SelectionDAGNodes.h:716
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:759
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1446
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::User
Definition: User.h:44
llvm::M68kISD::AND
@ AND
Definition: M68kISelLowering.h:80
llvm::M68kTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: M68kISelLowering.cpp:2685
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:472
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
NotStructReturn
@ NotStructReturn
Definition: M68kISelLowering.cpp:181
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1495
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1860
llvm::M68k::COND_GE
@ COND_GE
Definition: M68kInstrInfo.h:47
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
isAndOrOfSetCCs
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
Definition: M68kISelLowering.cpp:2229
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
Definition: SelectionDAG.cpp:2513
StackStructReturn
@ StackStructReturn
Definition: M68kISelLowering.cpp:181
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3848
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:331
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:214
llvm::M68kMachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(unsigned Reg)
Definition: M68kMachineFunction.h:102
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1027
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2319
argsAreStructReturn
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
Definition: M68kISelLowering.cpp:198
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:654
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::TargetLowering::CallLoweringInfo::DoesNotReturn
bool DoesNotReturn
Definition: TargetLowering.h:4086
combineM68kSetCC
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3391
llvm::M68kMachineFunctionInfo::setTCReturnAddrDelta
void setTCReturnAddrDelta(int delta)
Definition: M68kMachineFunction.h:90
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:279
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:305
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1783
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4500
M68kISelLowering.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1430
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:1285
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1420
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:1150
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::SDValue::getValueSizeInBits
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
Definition: SelectionDAGNodes.h:199
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1411
RegStructReturn
@ RegStructReturn
Definition: M68kISelLowering.cpp:181
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1431
llvm::M68kMachineFunctionInfo::getSRetReturnReg
unsigned getSRetReturnReg() const
Definition: M68kMachineFunction.h:101
llvm::CallingConv::Swift
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1436
llvm::MVT::getScalarType
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
Definition: MachineValueType.h:527
llvm::M68kISD::TC_RETURN
@ TC_RETURN
Definition: M68kISelLowering.h:38
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:712
llvm::M68kTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: M68kISelLowering.cpp:2736
checkAndUpdateCCRKill
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
Definition: M68kISelLowering.cpp:2915
llvm::M68kSubtarget
Definition: M68kSubtarget.h:44
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: MachineValueType.h:350
llvm::M68kTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: M68kISelLowering.cpp:1318
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::M68kISD::XOR
@ XOR
Definition: M68kISelLowering.h:79
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:492
llvm::M68kISD::CMOV
@ CMOV
M68k conditional moves.
Definition: M68kISelLowering.h:63
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:4107
llvm::M68kISD::SUB
@ SUB
Definition: M68kISelLowering.h:73
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1440
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2336
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::TargetLowering::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: TargetLowering.h:4239
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::M68k::COND_HI
@ COND_HI
Definition: M68kInstrInfo.h:37
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::M68kISD::SMUL
@ SMUL
Definition: M68kISelLowering.h:76
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:936
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:650
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:4080
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1615
llvm::M68kMachineFunctionInfo::getRAIndex
int getRAIndex() const
Definition: M68kMachineFunction.h:86
llvm::M68kISD::TAIL_CALL
@ TAIL_CALL
Definition: M68kISelLowering.h:37
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:196
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:165
getBitTestCondition
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BTST (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal ...
Definition: M68kISelLowering.cpp:1420
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::M68kII::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Return true if the specified global value reference is relative to a 32-bit PIC base (M68kISD::GLOBAL...
Definition: M68kBaseInfo.h:145
llvm::DenseMap
Definition: DenseMap.h:714
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:790
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:4101
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2285
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:918
llvm::M68k::GetCondBranchFromCond
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
Definition: M68kInstrInfo.h:97
llvm::FrameIndexSDNode::getIndex
int getIndex() const
Definition: SelectionDAGNodes.h:1794
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:9010
combineM68kBrCond
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3403
MatchingStackOffset
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const M68kInstrInfo *TII, const CCValAssign &VA)
Return true if the given stack call argument is already available in the same position (relatively) o...
Definition: M68kISelLowering.cpp:246
llvm::SelectionDAG::getNOT
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
Definition: SelectionDAG.cpp:1465
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:4105
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: M68kISelLowering.cpp:228
llvm::M68kISD::BTST
@ BTST
M68k bit-test instructions.
Definition: M68kISelLowering.h:46
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:645
llvm::Log2_64_Ceil
unsigned Log2_64_Ceil(uint64_t Value)
Return the ceil log base 2 of the specified value, 64 if the value is zero.
Definition: MathExtras.h:566
llvm::M68k::COND_INVALID
@ COND_INVALID
Definition: M68kInstrInfo.h:52
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::M68kII::isPCRelGlobalReference
static bool isPCRelGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue requires PC addressing mode.
Definition: M68kBaseInfo.h:156
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:631
llvm::M68kSubtarget::getFrameLowering
const M68kFrameLowering * getFrameLowering() const override
Definition: M68kSubtarget.h:150
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:179
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1428
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4079
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:890
llvm::M68k::COND_LT
@ COND_LT
Definition: M68kInstrInfo.h:48
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1438
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
M68kCallingConv.h
llvm::M68k::COND_CC
@ COND_CC
Definition: M68kInstrInfo.h:39
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::Value::use_begin
use_iterator use_begin()
Definition: Value.h:360
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2205
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::isNON_EXTLoad
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
Definition: SelectionDAGNodes.h:3050
llvm::M68kISD::SETCC_CARRY
@ SETCC_CARRY
Definition: M68kISelLowering.h:57
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::M68k::COND_VC
@ COND_VC
Definition: M68kInstrInfo.h:43
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
OP
#define OP(n)
Definition: regex2.h:73
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
Definition: SelectionDAG.cpp:2323
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1087
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1390
combineSUBX
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:3421
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: M68kISelLowering.cpp:225
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:979
llvm::CCState::resultsCompatible
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
Definition: CallingConvLower.cpp:258
llvm::CallingConv::C
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
isM68kLogicalCmp
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
Definition: M68kISelLowering.cpp:2000
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:4109
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:140
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:4104
llvm::M68kMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: M68kMachineFunction.h:96
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:728
callIsStructReturn
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
Definition: M68kISelLowering.cpp:184
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:98
llvm::M68kISD::ADDX
@ ADDX
Definition: M68kISelLowering.h:74
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
llvm::M68kISD::RET
@ RET
Definition: M68kISelLowering.h:36
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1881
llvm::M68kTargetLowering::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: M68kISelLowering.cpp:171
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:5183
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:352
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::M68kMachineFunctionInfo
Definition: M68kMachineFunction.h:23
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1146
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SDValue::hasOneUse
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Definition: SelectionDAGNodes.h:1182
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::M68kSubtarget::getSlotSize
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
Definition: M68kSubtarget.h:138
llvm::HexagonInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Definition: HexagonInstrInfo.cpp:287
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5266
llvm::M68kSubtarget::classifyGlobalFunctionReference
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
Definition: M68kSubtarget.cpp:242
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2375
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:190
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::MachineFrameInfo::isObjectSExt
bool isObjectSExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:538
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1404
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::M68kISD::WrapperPC
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
Definition: M68kISelLowering.h:91
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4497
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:722
llvm::M68kInstrInfo
Definition: M68kInstrInfo.h:237
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:346
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:4095
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1447
llvm::M68k::COND_LS
@ COND_LS
Definition: M68kInstrInfo.h:38
llvm::isAllOnesConstant
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
Definition: SelectionDAG.cpp:10735
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::M68kSubtarget::classifyLocalReference
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
Definition: M68kSubtarget.cpp:152
llvm::M68kMachineFunctionInfo::setBytesToPopOnReturn
void setBytesToPopOnReturn(unsigned bytes)
Definition: M68kMachineFunction.h:84
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2889
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2353
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1757
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::M68kTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: M68kISelLowering.cpp:3465
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10725
llvm::M68k::IsSETCC
static bool IsSETCC(unsigned SETCC)
Definition: M68kInstrInfo.h:185
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:982
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::M68kMachineFunctionInfo::setRAIndex
void setRAIndex(int Index)
Definition: M68kMachineFunction.h:87
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:545
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
Definition: SelectionDAG.cpp:533
GlobalVariable.h
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:466
llvm::MachineFrameInfo::setObjectSExt
void setObjectSExt(int ObjectIdx, bool IsSExt)
Definition: MachineFrameInfo.h:544
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
M68kMachineFunction.h
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:199
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1870
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:48
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:231
llvm::M68k::COND_MI
@ COND_MI
Definition: M68kInstrInfo.h:46
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:967
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1082
llvm::M68kISD::CMP
@ CMP
M68k compare and logical compare instructions.
Definition: M68kISelLowering.h:43
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
combineADDX
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: M68kISelLowering.cpp:3433
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::M68kTargetLowering::M68kTargetLowering
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
Definition: M68kISelLowering.cpp:46
llvm::M68kMachineFunctionInfo::getBytesToPopOnReturn
unsigned getBytesToPopOnReturn() const
Definition: M68kMachineFunction.h:83
llvm::M68kRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: M68kRegisterInfo.cpp:65
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
isCMOVPseudo
static bool isCMOVPseudo(MachineInstr &MI)
Definition: M68kISelLowering.cpp:2898
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2253
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1429
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
isM68kCCUnsigned
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
Definition: M68kISelLowering.cpp:1850
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::TargetLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: TargetLowering.cpp:80
MachineInstrBuilder.h
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:197
llvm::M68kISD::OR
@ OR
Definition: M68kISelLowering.h:78
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141