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M68kISelLowering.cpp
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1 //===-- M68kISelLowering.cpp - M68k DAG Lowering Impl -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file defines the interfaces that M68k uses to lower LLVM code into a
11 /// selection DAG.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "M68kISelLowering.h"
16 #include "M68kCallingConv.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kSubtarget.h"
19 #include "M68kTargetMachine.h"
20 #include "M68kTargetObjectFile.h"
21 
22 #include "llvm/ADT/Statistic.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/KnownBits.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "M68k-isel"
43 
44 STATISTIC(NumTailCalls, "Number of tail calls");
45 
47  const M68kSubtarget &STI)
48  : TargetLowering(TM), Subtarget(STI), TM(TM) {
49 
50  MVT PtrVT = MVT::i32;
51 
53 
54  auto *RegInfo = Subtarget.getRegisterInfo();
55  setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
56 
57  // Set up the register classes.
58  addRegisterClass(MVT::i8, &M68k::DR8RegClass);
59  addRegisterClass(MVT::i16, &M68k::XR16RegClass);
60  addRegisterClass(MVT::i32, &M68k::XR32RegClass);
61 
62  for (auto VT : MVT::integer_valuetypes()) {
66  }
67 
68  // We don't accept any truncstore of integer registers.
75 
78  if (Subtarget.atLeastM68020())
80  else
83 
84  for (auto OP :
90  }
91 
92  for (auto OP : {ISD::UMUL_LOHI, ISD::SMUL_LOHI}) {
95  }
96 
97  // FIXME It would be better to use a custom lowering
98  for (auto OP : {ISD::SMULO, ISD::UMULO}) {
102  }
103 
106 
107  // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
108  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
113  }
114 
115  // SADDO and friends are legal with this setup, i hope
116  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
121  }
122 
125 
126  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
132  }
133 
134  for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
139  }
140 
147 
152 
155 
157 
159 
160  // 2^2 bytes
161  // FIXME can it be just 2^1?
162  setMinFunctionAlignment(Align::Constant<2>());
163 }
164 
166  LLVMContext &Context, EVT VT) const {
167  // M68k SETcc producess either 0x00 or 0xFF
168  return MVT::i8;
169 }
170 
172  EVT Ty) const {
173  if (Ty.isSimple()) {
174  return Ty.getSimpleVT();
175  }
176  return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
177 }
178 
179 #include "M68kGenCallingConv.inc"
180 
182 
183 static StructReturnType
185  if (Outs.empty())
186  return NotStructReturn;
187 
188  const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
189  if (!Flags.isSRet())
190  return NotStructReturn;
191  if (Flags.isInReg())
192  return RegStructReturn;
193  return StackStructReturn;
194 }
195 
196 /// Determines whether a function uses struct return semantics.
197 static StructReturnType
199  if (Ins.empty())
200  return NotStructReturn;
201 
202  const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
203  if (!Flags.isSRet())
204  return NotStructReturn;
205  if (Flags.isInReg())
206  return RegStructReturn;
207  return StackStructReturn;
208 }
209 
210 /// Make a copy of an aggregate at address specified by "Src" to address
211 /// "Dst" with size and alignment information specified by the specific
212 /// parameter attribute. The copy will be passed as a byval function parameter.
214  SDValue Chain, ISD::ArgFlagsTy Flags,
215  SelectionDAG &DAG, const SDLoc &DL) {
216  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32);
217 
218  return DAG.getMemcpy(
219  Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
220  /*isVolatile=*/false, /*AlwaysInline=*/true,
221  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
222 }
223 
224 /// Return true if the calling convention is one that we can guarantee TCO for.
225 static bool canGuaranteeTCO(CallingConv::ID CC) { return false; }
226 
227 /// Return true if we might ever do TCO for calls with this calling convention.
229  switch (CC) {
230  // C calling conventions:
231  case CallingConv::C:
232  return true;
233  default:
234  return canGuaranteeTCO(CC);
235  }
236 }
237 
238 /// Return true if the function is being made into a tailcall target by
239 /// changing its ABI.
240 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
241  return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
242 }
243 
244 /// Return true if the given stack call argument is already available in the
245 /// same position (relatively) of the caller's incoming argument stack.
246 static bool MatchingStackOffset(SDValue Arg, unsigned Offset,
247  ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI,
248  const MachineRegisterInfo *MRI,
249  const M68kInstrInfo *TII,
250  const CCValAssign &VA) {
251  unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
252 
253  for (;;) {
254  // Look through nodes that don't alter the bits of the incoming value.
255  unsigned Op = Arg.getOpcode();
256  if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
257  Arg = Arg.getOperand(0);
258  continue;
259  }
260  if (Op == ISD::TRUNCATE) {
261  const SDValue &TruncInput = Arg.getOperand(0);
262  if (TruncInput.getOpcode() == ISD::AssertZext &&
263  cast<VTSDNode>(TruncInput.getOperand(1))->getVT() ==
264  Arg.getValueType()) {
265  Arg = TruncInput.getOperand(0);
266  continue;
267  }
268  }
269  break;
270  }
271 
272  int FI = INT_MAX;
273  if (Arg.getOpcode() == ISD::CopyFromReg) {
274  Register VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
276  return false;
277  MachineInstr *Def = MRI->getVRegDef(VR);
278  if (!Def)
279  return false;
280  if (!Flags.isByVal()) {
281  if (!TII->isLoadFromStackSlot(*Def, FI))
282  return false;
283  } else {
284  unsigned Opcode = Def->getOpcode();
285  if ((Opcode == M68k::LEA32p || Opcode == M68k::LEA32f) &&
286  Def->getOperand(1).isFI()) {
287  FI = Def->getOperand(1).getIndex();
288  Bytes = Flags.getByValSize();
289  } else
290  return false;
291  }
292  } else if (auto *Ld = dyn_cast<LoadSDNode>(Arg)) {
293  if (Flags.isByVal())
294  // ByVal argument is passed in as a pointer but it's now being
295  // dereferenced. e.g.
296  // define @foo(%struct.X* %A) {
297  // tail call @bar(%struct.X* byval %A)
298  // }
299  return false;
300  SDValue Ptr = Ld->getBasePtr();
301  FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
302  if (!FINode)
303  return false;
304  FI = FINode->getIndex();
305  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
306  FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
307  FI = FINode->getIndex();
308  Bytes = Flags.getByValSize();
309  } else
310  return false;
311 
312  assert(FI != INT_MAX);
313  if (!MFI.isFixedObjectIndex(FI))
314  return false;
315 
316  if (Offset != MFI.getObjectOffset(FI))
317  return false;
318 
319  if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) {
320  // If the argument location is wider than the argument type, check that any
321  // extension flags match.
322  if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
323  Flags.isSExt() != MFI.isObjectSExt(FI)) {
324  return false;
325  }
326  }
327 
328  return Bytes == MFI.getObjectSize(FI);
329 }
330 
331 SDValue
332 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
335  int ReturnAddrIndex = FuncInfo->getRAIndex();
336 
337  if (ReturnAddrIndex == 0) {
338  // Set up a frame object for the return address.
339  unsigned SlotSize = Subtarget.getSlotSize();
340  ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(
341  SlotSize, -(int64_t)SlotSize, false);
342  FuncInfo->setRAIndex(ReturnAddrIndex);
343  }
344 
345  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
346 }
347 
348 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
349  SDValue &OutRetAddr,
350  SDValue Chain,
351  bool IsTailCall, int FPDiff,
352  const SDLoc &DL) const {
353  EVT VT = getPointerTy(DAG.getDataLayout());
354  OutRetAddr = getReturnAddressFrameIndex(DAG);
355 
356  // Load the "old" Return address.
357  OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo());
358  return SDValue(OutRetAddr.getNode(), 1);
359 }
360 
361 SDValue M68kTargetLowering::EmitTailCallStoreRetAddr(
362  SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetFI,
363  EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const {
364  if (!FPDiff)
365  return Chain;
366 
367  // Calculate the new stack slot for the return address.
368  int NewFO = MF.getFrameInfo().CreateFixedObject(
369  SlotSize, (int64_t)FPDiff - SlotSize, false);
370 
371  SDValue NewFI = DAG.getFrameIndex(NewFO, PtrVT);
372  // Store the return address to the appropriate stack slot.
373  Chain = DAG.getStore(
374  Chain, DL, RetFI, NewFI,
376  return Chain;
377 }
378 
379 SDValue
380 M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
382  const SDLoc &DL, SelectionDAG &DAG,
383  const CCValAssign &VA,
384  MachineFrameInfo &MFI,
385  unsigned ArgIdx) const {
386  // Create the nodes corresponding to a load from this parameter slot.
387  ISD::ArgFlagsTy Flags = Ins[ArgIdx].Flags;
388  EVT ValVT;
389 
390  // If value is passed by pointer we have address passed instead of the value
391  // itself.
392  if (VA.getLocInfo() == CCValAssign::Indirect)
393  ValVT = VA.getLocVT();
394  else
395  ValVT = VA.getValVT();
396 
397  // Because we are dealing with BE architecture we need to offset loading of
398  // partial types
399  int Offset = VA.getLocMemOffset();
400  if (VA.getValVT() == MVT::i8) {
401  Offset += 3;
402  } else if (VA.getValVT() == MVT::i16) {
403  Offset += 2;
404  }
405 
406  // TODO Interrupt handlers
407  // Calculate SP offset of interrupt parameter, re-arrange the slot normally
408  // taken by a return address.
409 
410  // FIXME For now, all byval parameter objects are marked mutable. This can
411  // be changed with more analysis. In case of tail call optimization mark all
412  // arguments mutable. Since they could be overwritten by lowering of arguments
413  // in case of a tail call.
414  bool AlwaysUseMutable = shouldGuaranteeTCO(
415  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
416  bool IsImmutable = !AlwaysUseMutable && !Flags.isByVal();
417 
418  if (Flags.isByVal()) {
419  unsigned Bytes = Flags.getByValSize();
420  if (Bytes == 0)
421  Bytes = 1; // Don't create zero-sized stack objects.
422  int FI = MFI.CreateFixedObject(Bytes, Offset, IsImmutable);
423  // TODO Interrupt handlers
424  // Adjust SP offset of interrupt parameter.
425  return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
426  } else {
427  int FI =
428  MFI.CreateFixedObject(ValVT.getSizeInBits() / 8, Offset, IsImmutable);
429 
430  // Set SExt or ZExt flag.
431  if (VA.getLocInfo() == CCValAssign::ZExt) {
432  MFI.setObjectZExt(FI, true);
433  } else if (VA.getLocInfo() == CCValAssign::SExt) {
434  MFI.setObjectSExt(FI, true);
435  }
436 
437  // TODO Interrupt handlers
438  // Adjust SP offset of interrupt parameter.
439 
440  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
441  SDValue Val = DAG.getLoad(
442  ValVT, DL, Chain, FIN,
444  return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val)
445  : Val;
446  }
447 }
448 
449 SDValue M68kTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
450  SDValue Arg, const SDLoc &DL,
451  SelectionDAG &DAG,
452  const CCValAssign &VA,
453  ISD::ArgFlagsTy Flags) const {
454  unsigned LocMemOffset = VA.getLocMemOffset();
455  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL);
456  PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()),
457  StackPtr, PtrOff);
458  if (Flags.isByVal())
459  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL);
460 
461  return DAG.getStore(
462  Chain, DL, Arg, PtrOff,
463  MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
464 }
465 
466 //===----------------------------------------------------------------------===//
467 // Call
468 //===----------------------------------------------------------------------===//
469 
470 SDValue M68kTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
471  SmallVectorImpl<SDValue> &InVals) const {
472  SelectionDAG &DAG = CLI.DAG;
473  SDLoc &DL = CLI.DL;
475  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
477  SDValue Chain = CLI.Chain;
478  SDValue Callee = CLI.Callee;
479  CallingConv::ID CallConv = CLI.CallConv;
480  bool &IsTailCall = CLI.IsTailCall;
481  bool IsVarArg = CLI.IsVarArg;
482 
485  bool IsSibcall = false;
487  // const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
488 
489  if (CallConv == CallingConv::M68k_INTR)
490  report_fatal_error("M68k interrupts may not be called directly");
491 
492  auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
493  if (Attr.getValueAsBool())
494  IsTailCall = false;
495 
496  // FIXME Add tailcalls support
497 
498  bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
499  if (IsMustTail) {
500  // Force this to be a tail call. The verifier rules are enough to ensure
501  // that we can lower this successfully without moving the return address
502  // around.
503  IsTailCall = true;
504  } else if (IsTailCall) {
505  // Check if it's really possible to do a tail call.
506  IsTailCall = IsEligibleForTailCallOptimization(
507  Callee, CallConv, IsVarArg, SR != NotStructReturn,
508  MF.getFunction().hasStructRetAttr(), CLI.RetTy, Outs, OutVals, Ins,
509  DAG);
510 
511  // Sibcalls are automatically detected tailcalls which do not require
512  // ABI changes.
513  if (!MF.getTarget().Options.GuaranteedTailCallOpt && IsTailCall)
514  IsSibcall = true;
515 
516  if (IsTailCall)
517  ++NumTailCalls;
518  }
519 
520  assert(!(IsVarArg && canGuaranteeTCO(CallConv)) &&
521  "Var args not supported with calling convention fastcc");
522 
523  // Analyze operands of the call, assigning locations to each operand.
525  SmallVector<Type *, 4> ArgTypes;
526  for (const auto &Arg : CLI.getArgs())
527  ArgTypes.emplace_back(Arg.Ty);
528  M68kCCState CCInfo(ArgTypes, CallConv, IsVarArg, MF, ArgLocs,
529  *DAG.getContext());
530  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
531 
532  // Get a count of how many bytes are to be pushed on the stack.
533  unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
534  if (IsSibcall) {
535  // This is a sibcall. The memory operands are available in caller's
536  // own caller's stack.
537  NumBytes = 0;
538  } else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
539  canGuaranteeTCO(CallConv)) {
540  NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
541  }
542 
543  int FPDiff = 0;
544  if (IsTailCall && !IsSibcall && !IsMustTail) {
545  // Lower arguments at fp - stackoffset + fpdiff.
546  unsigned NumBytesCallerPushed = MFI->getBytesToPopOnReturn();
547 
548  FPDiff = NumBytesCallerPushed - NumBytes;
549 
550  // Set the delta of movement of the returnaddr stackslot.
551  // But only set if delta is greater than previous delta.
552  if (FPDiff < MFI->getTCReturnAddrDelta())
553  MFI->setTCReturnAddrDelta(FPDiff);
554  }
555 
556  unsigned NumBytesToPush = NumBytes;
557  unsigned NumBytesToPop = NumBytes;
558 
559  // If we have an inalloca argument, all stack space has already been allocated
560  // for us and be right at the top of the stack. We don't support multiple
561  // arguments passed in memory when using inalloca.
562  if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
563  NumBytesToPush = 0;
564  if (!ArgLocs.back().isMemLoc())
565  report_fatal_error("cannot use inalloca attribute on a register "
566  "parameter");
567  if (ArgLocs.back().getLocMemOffset() != 0)
568  report_fatal_error("any parameter with the inalloca attribute must be "
569  "the only memory argument");
570  }
571 
572  if (!IsSibcall)
573  Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
574  NumBytes - NumBytesToPush, DL);
575 
576  SDValue RetFI;
577  // Load return address for tail calls.
578  if (IsTailCall && FPDiff)
579  Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL);
580 
582  SmallVector<SDValue, 8> MemOpChains;
584 
585  // Walk the register/memloc assignments, inserting copies/loads. In the case
586  // of tail call optimization arguments are handle later.
587  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
588  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
589  ISD::ArgFlagsTy Flags = Outs[i].Flags;
590 
591  // Skip inalloca arguments, they have already been written.
592  if (Flags.isInAlloca())
593  continue;
594 
595  CCValAssign &VA = ArgLocs[i];
596  EVT RegVT = VA.getLocVT();
597  SDValue Arg = OutVals[i];
598  bool IsByVal = Flags.isByVal();
599 
600  // Promote the value if needed.
601  switch (VA.getLocInfo()) {
602  default:
603  llvm_unreachable("Unknown loc info!");
604  case CCValAssign::Full:
605  break;
606  case CCValAssign::SExt:
607  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg);
608  break;
609  case CCValAssign::ZExt:
610  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
611  break;
612  case CCValAssign::AExt:
613  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg);
614  break;
615  case CCValAssign::BCvt:
616  Arg = DAG.getBitcast(RegVT, Arg);
617  break;
618  case CCValAssign::Indirect: {
619  // Store the argument.
620  SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
621  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
622  Chain = DAG.getStore(
623  Chain, DL, Arg, SpillSlot,
625  Arg = SpillSlot;
626  break;
627  }
628  }
629 
630  if (VA.isRegLoc()) {
631  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
632  } else if (!IsSibcall && (!IsTailCall || IsByVal)) {
633  assert(VA.isMemLoc());
634  if (!StackPtr.getNode()) {
635  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
636  getPointerTy(DAG.getDataLayout()));
637  }
638  MemOpChains.push_back(
639  LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags));
640  }
641  }
642 
643  if (!MemOpChains.empty())
644  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
645 
646  // FIXME Make sure PIC style GOT works as expected
647  // The only time GOT is really needed is for Medium-PIC static data
648  // otherwise we are happy with pc-rel or static references
649 
650  if (IsVarArg && IsMustTail) {
651  const auto &Forwards = MFI->getForwardedMustTailRegParms();
652  for (const auto &F : Forwards) {
653  SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
654  RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
655  }
656  }
657 
658  // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
659  // don't need this because the eligibility check rejects calls that require
660  // shuffling arguments passed in memory.
661  if (!IsSibcall && IsTailCall) {
662  // Force all the incoming stack arguments to be loaded from the stack
663  // before any new outgoing arguments are stored to the stack, because the
664  // outgoing stack slots may alias the incoming argument stack slots, and
665  // the alias isn't otherwise explicit. This is slightly more conservative
666  // than necessary, because it means that each store effectively depends
667  // on every argument instead of just those arguments it would clobber.
668  SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
669 
670  SmallVector<SDValue, 8> MemOpChains2;
671  SDValue FIN;
672  int FI = 0;
673  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
674  CCValAssign &VA = ArgLocs[i];
675  if (VA.isRegLoc())
676  continue;
677  assert(VA.isMemLoc());
678  SDValue Arg = OutVals[i];
679  ISD::ArgFlagsTy Flags = Outs[i].Flags;
680  // Skip inalloca arguments. They don't require any work.
681  if (Flags.isInAlloca())
682  continue;
683  // Create frame index.
684  int32_t Offset = VA.getLocMemOffset() + FPDiff;
685  uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8;
686  FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
687  FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
688 
689  if (Flags.isByVal()) {
690  // Copy relative to framepointer.
692  if (!StackPtr.getNode()) {
693  StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(),
694  getPointerTy(DAG.getDataLayout()));
695  }
697  StackPtr, Source);
698 
699  MemOpChains2.push_back(
700  CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL));
701  } else {
702  // Store relative to framepointer.
703  MemOpChains2.push_back(DAG.getStore(
704  ArgChain, DL, Arg, FIN,
706  }
707  }
708 
709  if (!MemOpChains2.empty())
710  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2);
711 
712  // Store the return address to the appropriate stack slot.
713  Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetFI,
715  Subtarget.getSlotSize(), FPDiff, DL);
716  }
717 
718  // Build a sequence of copy-to-reg nodes chained together with token chain
719  // and flag operands which copy the outgoing args into registers.
720  SDValue InFlag;
721  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
722  Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
723  RegsToPass[i].second, InFlag);
724  InFlag = Chain.getValue(1);
725  }
726 
727  if (Callee->getOpcode() == ISD::GlobalAddress) {
728  // If the callee is a GlobalAddress node (quite common, every direct call
729  // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
730  // it.
731  GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
732 
733  // We should use extra load for direct calls to dllimported functions in
734  // non-JIT mode.
735  const GlobalValue *GV = G->getGlobal();
736  if (!GV->hasDLLImportStorageClass()) {
737  unsigned char OpFlags = Subtarget.classifyGlobalFunctionReference(GV);
738 
740  GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
741 
742  if (OpFlags == M68kII::MO_GOTPCREL) {
743 
744  // Add a wrapper.
746  getPointerTy(DAG.getDataLayout()), Callee);
747 
748  // Add extra indirection
749  Callee = DAG.getLoad(
750  getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee,
752  }
753  }
754  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
756  unsigned char OpFlags =
757  Subtarget.classifyGlobalFunctionReference(nullptr, *Mod);
758 
760  S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
761  }
762 
763  // Returns a chain & a flag for retval copy to use.
764  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
766 
767  if (!IsSibcall && IsTailCall) {
768  Chain = DAG.getCALLSEQ_END(Chain,
769  DAG.getIntPtrConstant(NumBytesToPop, DL, true),
770  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
771  InFlag = Chain.getValue(1);
772  }
773 
774  Ops.push_back(Chain);
775  Ops.push_back(Callee);
776 
777  if (IsTailCall)
778  Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32));
779 
780  // Add argument registers to the end of the list so that they are known live
781  // into the call.
782  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
783  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
784  RegsToPass[i].second.getValueType()));
785 
786  // Add a register mask operand representing the call-preserved registers.
787  const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
788  assert(Mask && "Missing call preserved mask for calling convention");
789 
790  Ops.push_back(DAG.getRegisterMask(Mask));
791 
792  if (InFlag.getNode())
793  Ops.push_back(InFlag);
794 
795  if (IsTailCall) {
797  return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops);
798  }
799 
800  Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops);
801  InFlag = Chain.getValue(1);
802 
803  // Create the CALLSEQ_END node.
804  unsigned NumBytesForCalleeToPop;
805  if (M68k::isCalleePop(CallConv, IsVarArg,
807  NumBytesForCalleeToPop = NumBytes; // Callee pops everything
808  } else if (!canGuaranteeTCO(CallConv) && SR == StackStructReturn) {
809  // If this is a call to a struct-return function, the callee
810  // pops the hidden struct pointer, so we have to push it back.
811  NumBytesForCalleeToPop = 4;
812  } else {
813  NumBytesForCalleeToPop = 0; // Callee pops nothing.
814  }
815 
816  if (CLI.DoesNotReturn && !getTargetMachine().Options.TrapUnreachable) {
817  // No need to reset the stack after the call if the call doesn't return. To
818  // make the MI verify, we'll pretend the callee does it for us.
819  NumBytesForCalleeToPop = NumBytes;
820  }
821 
822  // Returns a flag for retval copy to use.
823  if (!IsSibcall) {
824  Chain = DAG.getCALLSEQ_END(
825  Chain, DAG.getIntPtrConstant(NumBytesToPop, DL, true),
826  DAG.getIntPtrConstant(NumBytesForCalleeToPop, DL, true), InFlag, DL);
827  InFlag = Chain.getValue(1);
828  }
829 
830  // Handle result values, copying them out of physregs into vregs that we
831  // return.
832  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
833  InVals);
834 }
835 
836 SDValue M68kTargetLowering::LowerCallResult(
837  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
839  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
840 
841  // Assign locations to each value returned by this call.
843  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
844  *DAG.getContext());
845  CCInfo.AnalyzeCallResult(Ins, RetCC_M68k);
846 
847  // Copy all of the result registers out of their specified physreg.
848  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
849  CCValAssign &VA = RVLocs[i];
850  EVT CopyVT = VA.getLocVT();
851 
852  /// ??? is this correct?
853  Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InFlag)
854  .getValue(1);
855  SDValue Val = Chain.getValue(0);
856 
857  if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
858  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
859 
860  InFlag = Chain.getValue(2);
861  InVals.push_back(Val);
862  }
863 
864  return Chain;
865 }
866 
867 //===----------------------------------------------------------------------===//
868 // Formal Arguments Calling Convention Implementation
869 //===----------------------------------------------------------------------===//
870 
871 SDValue M68kTargetLowering::LowerFormalArguments(
872  SDValue Chain, CallingConv::ID CCID, bool IsVarArg,
874  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
877  // const TargetFrameLowering &TFL = *Subtarget.getFrameLowering();
878 
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880 
881  // Assign locations to all of the incoming arguments.
883  SmallVector<Type *, 4> ArgTypes;
884  for (const Argument &Arg : MF.getFunction().args())
885  ArgTypes.emplace_back(Arg.getType());
886  M68kCCState CCInfo(ArgTypes, CCID, IsVarArg, MF, ArgLocs, *DAG.getContext());
887 
888  CCInfo.AnalyzeFormalArguments(Ins, CC_M68k);
889 
890  unsigned LastVal = ~0U;
891  SDValue ArgValue;
892  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
893  CCValAssign &VA = ArgLocs[i];
894  assert(VA.getValNo() != LastVal && "Same value in different locations");
895 
896  LastVal = VA.getValNo();
897 
898  if (VA.isRegLoc()) {
899  EVT RegVT = VA.getLocVT();
900  const TargetRegisterClass *RC;
901  if (RegVT == MVT::i32)
902  RC = &M68k::XR32RegClass;
903  else
904  llvm_unreachable("Unknown argument type!");
905 
906  Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
907  ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
908 
909  // If this is an 8 or 16-bit value, it is really passed promoted to 32
910  // bits. Insert an assert[sz]ext to capture this, then truncate to the
911  // right size.
912  if (VA.getLocInfo() == CCValAssign::SExt) {
913  ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
914  DAG.getValueType(VA.getValVT()));
915  } else if (VA.getLocInfo() == CCValAssign::ZExt) {
916  ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
917  DAG.getValueType(VA.getValVT()));
918  } else if (VA.getLocInfo() == CCValAssign::BCvt) {
919  ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
920  }
921 
922  if (VA.isExtInLoc()) {
923  ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
924  }
925  } else {
926  assert(VA.isMemLoc());
927  ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i);
928  }
929 
930  // If value is passed via pointer - do a load.
931  // TODO Make sure this handling on indirect arguments is correct
932  if (VA.getLocInfo() == CCValAssign::Indirect)
933  ArgValue =
934  DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo());
935 
936  InVals.push_back(ArgValue);
937  }
938 
939  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
940  // Swift calling convention does not require we copy the sret argument
941  // into %D0 for the return. We don't set SRetReturnReg for Swift.
942  if (CCID == CallingConv::Swift)
943  continue;
944 
945  // ABI require that for returning structs by value we copy the sret argument
946  // into %D0 for the return. Save the argument into a virtual register so
947  // that we can access it from the return points.
948  if (Ins[i].Flags.isSRet()) {
949  unsigned Reg = MMFI->getSRetReturnReg();
950  if (!Reg) {
951  MVT PtrTy = getPointerTy(DAG.getDataLayout());
953  MMFI->setSRetReturnReg(Reg);
954  }
955  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
956  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
957  break;
958  }
959  }
960 
961  unsigned StackSize = CCInfo.getNextStackOffset();
962  // Align stack specially for tail calls.
964  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
965 
966  // If the function takes variable number of arguments, make a frame index for
967  // the start of the first vararg value... for expansion of llvm.va_start. We
968  // can skip this if there are no va_start calls.
969  if (MFI.hasVAStart()) {
970  MMFI->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
971  }
972 
973  if (IsVarArg && MFI.hasMustTailInVarArgFunc()) {
974  // We forward some GPRs and some vector types.
975  SmallVector<MVT, 2> RegParmTypes;
976  MVT IntVT = MVT::i32;
977  RegParmTypes.push_back(IntVT);
978 
979  // Compute the set of forwarded registers. The rest are scratch.
980  // ??? what is this for?
983  CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_M68k);
984 
985  // Copy all forwards from physical to virtual registers.
986  for (ForwardedRegister &F : Forwards) {
987  // FIXME Can we use a less constrained schedule?
988  SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT);
990  Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal);
991  }
992  }
993 
994  // Some CCs need callee pop.
995  if (M68k::isCalleePop(CCID, IsVarArg,
997  MMFI->setBytesToPopOnReturn(StackSize); // Callee pops everything.
998  } else {
999  MMFI->setBytesToPopOnReturn(0); // Callee pops nothing.
1000  // If this is an sret function, the return should pop the hidden pointer.
1002  MMFI->setBytesToPopOnReturn(4);
1003  }
1004 
1005  MMFI->setArgumentStackSize(StackSize);
1006 
1007  return Chain;
1008 }
1009 
1010 //===----------------------------------------------------------------------===//
1011 // Return Value Calling Convention Implementation
1012 //===----------------------------------------------------------------------===//
1013 
1014 SDValue
1015 M68kTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CCID,
1016  bool IsVarArg,
1017  const SmallVectorImpl<ISD::OutputArg> &Outs,
1018  const SmallVectorImpl<SDValue> &OutVals,
1019  const SDLoc &DL, SelectionDAG &DAG) const {
1020  MachineFunction &MF = DAG.getMachineFunction();
1022 
1024  CCState CCInfo(CCID, IsVarArg, MF, RVLocs, *DAG.getContext());
1025  CCInfo.AnalyzeReturn(Outs, RetCC_M68k);
1026 
1027  SDValue Flag;
1028  SmallVector<SDValue, 6> RetOps;
1029  // Operand #0 = Chain (updated below)
1030  RetOps.push_back(Chain);
1031  // Operand #1 = Bytes To Pop
1032  RetOps.push_back(
1034 
1035  // Copy the result values into the output registers.
1036  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1037  CCValAssign &VA = RVLocs[i];
1038  assert(VA.isRegLoc() && "Can only return in registers!");
1039  SDValue ValToCopy = OutVals[i];
1040  EVT ValVT = ValToCopy.getValueType();
1041 
1042  // Promote values to the appropriate types.
1043  if (VA.getLocInfo() == CCValAssign::SExt)
1044  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1045  else if (VA.getLocInfo() == CCValAssign::ZExt)
1046  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy);
1047  else if (VA.getLocInfo() == CCValAssign::AExt) {
1048  if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
1049  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy);
1050  else
1051  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy);
1052  } else if (VA.getLocInfo() == CCValAssign::BCvt)
1053  ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1054 
1055  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Flag);
1056  Flag = Chain.getValue(1);
1057  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1058  }
1059 
1060  // Swift calling convention does not require we copy the sret argument
1061  // into %d0 for the return, and SRetReturnReg is not set for Swift.
1062 
1063  // ABI require that for returning structs by value we copy the sret argument
1064  // into %D0 for the return. Save the argument into a virtual register so that
1065  // we can access it from the return points.
1066  //
1067  // Checking Function.hasStructRetAttr() here is insufficient because the IR
1068  // may not have an explicit sret argument. If MFI.CanLowerReturn is
1069  // false, then an sret argument may be implicitly inserted in the SelDAG. In
1070  // either case MFI->setSRetReturnReg() will have been called.
1071  if (unsigned SRetReg = MFI->getSRetReturnReg()) {
1072  // ??? Can i just move this to the top and escape this explanation?
1073  // When we have both sret and another return value, we should use the
1074  // original Chain stored in RetOps[0], instead of the current Chain updated
1075  // in the above loop. If we only have sret, RetOps[0] equals to Chain.
1076 
1077  // For the case of sret and another return value, we have
1078  // Chain_0 at the function entry
1079  // Chain_1 = getCopyToReg(Chain_0) in the above loop
1080  // If we use Chain_1 in getCopyFromReg, we will have
1081  // Val = getCopyFromReg(Chain_1)
1082  // Chain_2 = getCopyToReg(Chain_1, Val) from below
1083 
1084  // getCopyToReg(Chain_0) will be glued together with
1085  // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
1086  // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
1087  // Data dependency from Unit B to Unit A due to usage of Val in
1088  // getCopyToReg(Chain_1, Val)
1089  // Chain dependency from Unit A to Unit B
1090 
1091  // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
1092  SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg,
1093  getPointerTy(MF.getDataLayout()));
1094 
1095  // ??? How will this work if CC does not use registers for args passing?
1096  // ??? What if I return multiple structs?
1097  unsigned RetValReg = M68k::D0;
1098  Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Flag);
1099  Flag = Chain.getValue(1);
1100 
1101  RetOps.push_back(
1102  DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
1103  }
1104 
1105  RetOps[0] = Chain; // Update chain.
1106 
1107  // Add the flag if we have it.
1108  if (Flag.getNode())
1109  RetOps.push_back(Flag);
1110 
1111  return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps);
1112 }
1113 
1114 //===----------------------------------------------------------------------===//
1115 // Fast Calling Convention (tail call) implementation
1116 //===----------------------------------------------------------------------===//
1117 
1118 // Like std call, callee cleans arguments, convention except that ECX is
1119 // reserved for storing the tail called function address. Only 2 registers are
1120 // free for argument passing (inreg). Tail call optimization is performed
1121 // provided:
1122 // * tailcallopt is enabled
1123 // * caller/callee are fastcc
1124 // On M68k_64 architecture with GOT-style position independent code only
1125 // local (within module) calls are supported at the moment. To keep the stack
1126 // aligned according to platform abi the function GetAlignedArgumentStackSize
1127 // ensures that argument delta is always multiples of stack alignment. (Dynamic
1128 // linkers need this - darwin's dyld for example) If a tail called function
1129 // callee has more arguments than the caller the caller needs to make sure that
1130 // there is room to move the RETADDR to. This is achieved by reserving an area
1131 // the size of the argument delta right after the original RETADDR, but before
1132 // the saved framepointer or the spilled registers e.g. caller(arg1, arg2)
1133 // calls callee(arg1, arg2,arg3,arg4) stack layout:
1134 // arg1
1135 // arg2
1136 // RETADDR
1137 // [ new RETADDR
1138 // move area ]
1139 // (possible EBP)
1140 // ESI
1141 // EDI
1142 // local1 ..
1143 
1144 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
1145 /// requirement.
1146 unsigned
1147 M68kTargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1148  SelectionDAG &DAG) const {
1149  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
1150  unsigned StackAlignment = TFI.getStackAlignment();
1151  uint64_t AlignMask = StackAlignment - 1;
1152  int64_t Offset = StackSize;
1153  unsigned SlotSize = Subtarget.getSlotSize();
1154  if ((Offset & AlignMask) <= (StackAlignment - SlotSize)) {
1155  // Number smaller than 12 so just add the difference.
1156  Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1157  } else {
1158  // Mask out lower bits, add stackalignment once plus the 12 bytes.
1159  Offset =
1160  ((~AlignMask) & Offset) + StackAlignment + (StackAlignment - SlotSize);
1161  }
1162  return Offset;
1163 }
1164 
1165 /// Check whether the call is eligible for tail call optimization. Targets
1166 /// that want to do tail call optimization should implement this function.
1167 bool M68kTargetLowering::IsEligibleForTailCallOptimization(
1168  SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
1169  bool IsCalleeStructRet, bool IsCallerStructRet, Type *RetTy,
1170  const SmallVectorImpl<ISD::OutputArg> &Outs,
1171  const SmallVectorImpl<SDValue> &OutVals,
1172  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1173  if (!mayTailCallThisCC(CalleeCC))
1174  return false;
1175 
1176  // If -tailcallopt is specified, make fastcc functions tail-callable.
1177  MachineFunction &MF = DAG.getMachineFunction();
1178  const auto &CallerF = MF.getFunction();
1179 
1180  CallingConv::ID CallerCC = CallerF.getCallingConv();
1181  bool CCMatch = CallerCC == CalleeCC;
1182 
1184  if (canGuaranteeTCO(CalleeCC) && CCMatch)
1185  return true;
1186  return false;
1187  }
1188 
1189  // Look for obvious safe cases to perform tail call optimization that do not
1190  // require ABI changes. This is what gcc calls sibcall.
1191 
1192  // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
1193  // emit a special epilogue.
1194  const M68kRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1195  if (RegInfo->hasStackRealignment(MF))
1196  return false;
1197 
1198  // Also avoid sibcall optimization if either caller or callee uses struct
1199  // return semantics.
1200  if (IsCalleeStructRet || IsCallerStructRet)
1201  return false;
1202 
1203  // Do not sibcall optimize vararg calls unless all arguments are passed via
1204  // registers.
1205  LLVMContext &C = *DAG.getContext();
1206  if (IsVarArg && !Outs.empty()) {
1207 
1209  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1210 
1211  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1212  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1213  if (!ArgLocs[i].isRegLoc())
1214  return false;
1215  }
1216 
1217  // Check that the call results are passed in the same way.
1218  if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins, RetCC_M68k,
1219  RetCC_M68k))
1220  return false;
1221 
1222  // The callee has to preserve all registers the caller needs to preserve.
1223  const M68kRegisterInfo *TRI = Subtarget.getRegisterInfo();
1224  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1225  if (!CCMatch) {
1226  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
1227  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
1228  return false;
1229  }
1230 
1231  unsigned StackArgsSize = 0;
1232 
1233  // If the callee takes no arguments then go on to check the results of the
1234  // call.
1235  if (!Outs.empty()) {
1236  // Check if stack adjustment is needed. For now, do not do this if any
1237  // argument is passed on the stack.
1239  CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, C);
1240 
1241  CCInfo.AnalyzeCallOperands(Outs, CC_M68k);
1242  StackArgsSize = CCInfo.getNextStackOffset();
1243 
1244  if (CCInfo.getNextStackOffset()) {
1245  // Check if the arguments are already laid out in the right way as
1246  // the caller's fixed stack objects.
1247  MachineFrameInfo &MFI = MF.getFrameInfo();
1248  const MachineRegisterInfo *MRI = &MF.getRegInfo();
1249  const M68kInstrInfo *TII = Subtarget.getInstrInfo();
1250  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1251  CCValAssign &VA = ArgLocs[i];
1252  SDValue Arg = OutVals[i];
1253  ISD::ArgFlagsTy Flags = Outs[i].Flags;
1254  if (VA.getLocInfo() == CCValAssign::Indirect)
1255  return false;
1256  if (!VA.isRegLoc()) {
1257  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI,
1258  TII, VA))
1259  return false;
1260  }
1261  }
1262  }
1263 
1264  bool PositionIndependent = isPositionIndependent();
1265  // If the tailcall address may be in a register, then make sure it's
1266  // possible to register allocate for it. The call address can
1267  // only target %A0 or %A1 since the tail call must be scheduled after
1268  // callee-saved registers are restored. These happen to be the same
1269  // registers used to pass 'inreg' arguments so watch out for those.
1270  if ((!isa<GlobalAddressSDNode>(Callee) &&
1271  !isa<ExternalSymbolSDNode>(Callee)) ||
1272  PositionIndependent) {
1273  unsigned NumInRegs = 0;
1274  // In PIC we need an extra register to formulate the address computation
1275  // for the callee.
1276  unsigned MaxInRegs = PositionIndependent ? 1 : 2;
1277 
1278  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1279  CCValAssign &VA = ArgLocs[i];
1280  if (!VA.isRegLoc())
1281  continue;
1282  Register Reg = VA.getLocReg();
1283  switch (Reg) {
1284  default:
1285  break;
1286  case M68k::A0:
1287  case M68k::A1:
1288  if (++NumInRegs == MaxInRegs)
1289  return false;
1290  break;
1291  }
1292  }
1293  }
1294 
1295  const MachineRegisterInfo &MRI = MF.getRegInfo();
1296  if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
1297  return false;
1298  }
1299 
1300  bool CalleeWillPop = M68k::isCalleePop(
1301  CalleeCC, IsVarArg, MF.getTarget().Options.GuaranteedTailCallOpt);
1302 
1303  if (unsigned BytesToPop =
1305  // If we have bytes to pop, the callee must pop them.
1306  bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
1307  if (!CalleePopMatches)
1308  return false;
1309  } else if (CalleeWillPop && StackArgsSize > 0) {
1310  // If we don't have bytes to pop, make sure the callee doesn't pop any.
1311  return false;
1312  }
1313 
1314  return true;
1315 }
1316 
1317 //===----------------------------------------------------------------------===//
1318 // Custom Lower
1319 //===----------------------------------------------------------------------===//
1320 
1322  SelectionDAG &DAG) const {
1323  switch (Op.getOpcode()) {
1324  default:
1325  llvm_unreachable("Should not custom lower this!");
1326  case ISD::SADDO:
1327  case ISD::UADDO:
1328  case ISD::SSUBO:
1329  case ISD::USUBO:
1330  case ISD::SMULO:
1331  case ISD::UMULO:
1332  return LowerXALUO(Op, DAG);
1333  case ISD::SETCC:
1334  return LowerSETCC(Op, DAG);
1335  case ISD::SETCCCARRY:
1336  return LowerSETCCCARRY(Op, DAG);
1337  case ISD::SELECT:
1338  return LowerSELECT(Op, DAG);
1339  case ISD::BRCOND:
1340  return LowerBRCOND(Op, DAG);
1341  case ISD::ADDC:
1342  case ISD::ADDE:
1343  case ISD::SUBC:
1344  case ISD::SUBE:
1345  return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1346  case ISD::ConstantPool:
1347  return LowerConstantPool(Op, DAG);
1348  case ISD::GlobalAddress:
1349  return LowerGlobalAddress(Op, DAG);
1350  case ISD::ExternalSymbol:
1351  return LowerExternalSymbol(Op, DAG);
1352  case ISD::BlockAddress:
1353  return LowerBlockAddress(Op, DAG);
1354  case ISD::JumpTable:
1355  return LowerJumpTable(Op, DAG);
1356  case ISD::VASTART:
1357  return LowerVASTART(Op, DAG);
1359  return LowerDYNAMIC_STACKALLOC(Op, DAG);
1360  case ISD::SHL_PARTS:
1361  return LowerShiftLeftParts(Op, DAG);
1362  case ISD::SRA_PARTS:
1363  return LowerShiftRightParts(Op, DAG, true);
1364  case ISD::SRL_PARTS:
1365  return LowerShiftRightParts(Op, DAG, false);
1366  }
1367 }
1368 
1369 bool M68kTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
1370  SDValue C) const {
1371  // Shifts and add instructions in M68000 and M68010 support
1372  // up to 32 bits, but mul only has 16-bit variant. So it's almost
1373  // certainly beneficial to lower 8/16/32-bit mul to their
1374  // add / shifts counterparts. But for 64-bits mul, it might be
1375  // safer to just leave it to compiler runtime implementations.
1376  return VT.bitsLE(MVT::i32) || Subtarget.atLeastM68020();
1377 }
1378 
1379 SDValue M68kTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
1380  // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
1381  // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
1382  // looks for this combo and may remove the "setcc" instruction if the "setcc"
1383  // has only one use.
1384  SDNode *N = Op.getNode();
1385  SDValue LHS = N->getOperand(0);
1386  SDValue RHS = N->getOperand(1);
1387  unsigned BaseOp = 0;
1388  unsigned Cond = 0;
1389  SDLoc DL(Op);
1390  switch (Op.getOpcode()) {
1391  default:
1392  llvm_unreachable("Unknown ovf instruction!");
1393  case ISD::SADDO:
1394  BaseOp = M68kISD::ADD;
1395  Cond = M68k::COND_VS;
1396  break;
1397  case ISD::UADDO:
1398  BaseOp = M68kISD::ADD;
1399  Cond = M68k::COND_CS;
1400  break;
1401  case ISD::SSUBO:
1402  BaseOp = M68kISD::SUB;
1403  Cond = M68k::COND_VS;
1404  break;
1405  case ISD::USUBO:
1406  BaseOp = M68kISD::SUB;
1407  Cond = M68k::COND_CS;
1408  break;
1409  }
1410 
1411  // Also sets CCR.
1412  SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i8);
1413  SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
1414  SDValue SetCC = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1),
1415  DAG.getConstant(Cond, DL, MVT::i8),
1416  SDValue(Arith.getNode(), 1));
1417 
1418  return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Arith, SetCC);
1419 }
1420 
1421 /// Create a BTST (Bit Test) node - Test bit \p BitNo in \p Src and set
1422 /// condition according to equal/not-equal condition code \p CC.
1424  const SDLoc &DL, SelectionDAG &DAG) {
1425  // If Src is i8, promote it to i32 with any_extend. There is no i8 BTST
1426  // instruction. Since the shift amount is in-range-or-undefined, we know
1427  // that doing a bittest on the i32 value is ok.
1428  if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
1429  Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
1430 
1431  // If the operand types disagree, extend the shift amount to match. Since
1432  // BTST ignores high bits (like shifts) we can use anyextend.
1433  if (Src.getValueType() != BitNo.getValueType())
1434  BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo);
1435 
1436  SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
1437 
1438  // NOTE BTST sets CCR.Z flag
1440  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1441  DAG.getConstant(Cond, DL, MVT::i8), BTST);
1442 }
1443 
1444 /// Result of 'and' is compared against zero. Change to a BTST node if possible.
1446  SelectionDAG &DAG) {
1447  SDValue Op0 = And.getOperand(0);
1448  SDValue Op1 = And.getOperand(1);
1449  if (Op0.getOpcode() == ISD::TRUNCATE)
1450  Op0 = Op0.getOperand(0);
1451  if (Op1.getOpcode() == ISD::TRUNCATE)
1452  Op1 = Op1.getOperand(0);
1453 
1454  SDValue LHS, RHS;
1455  if (Op1.getOpcode() == ISD::SHL)
1456  std::swap(Op0, Op1);
1457  if (Op0.getOpcode() == ISD::SHL) {
1458  if (isOneConstant(Op0.getOperand(0))) {
1459  // If we looked past a truncate, check that it's only truncating away
1460  // known zeros.
1461  unsigned BitWidth = Op0.getValueSizeInBits();
1462  unsigned AndBitWidth = And.getValueSizeInBits();
1463  if (BitWidth > AndBitWidth) {
1464  auto Known = DAG.computeKnownBits(Op0);
1465  if (Known.countMinLeadingZeros() < BitWidth - AndBitWidth)
1466  return SDValue();
1467  }
1468  LHS = Op1;
1469  RHS = Op0.getOperand(1);
1470  }
1471  } else if (auto *AndRHS = dyn_cast<ConstantSDNode>(Op1)) {
1472  uint64_t AndRHSVal = AndRHS->getZExtValue();
1473  SDValue AndLHS = Op0;
1474 
1475  if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
1476  LHS = AndLHS.getOperand(0);
1477  RHS = AndLHS.getOperand(1);
1478  }
1479 
1480  // Use BTST if the immediate can't be encoded in a TEST instruction.
1481  if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
1482  LHS = AndLHS;
1483  RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType());
1484  }
1485  }
1486 
1487  if (LHS.getNode())
1488  return getBitTestCondition(LHS, RHS, CC, DL, DAG);
1489 
1490  return SDValue();
1491 }
1492 
1494  switch (SetCCOpcode) {
1495  default:
1496  llvm_unreachable("Invalid integer condition!");
1497  case ISD::SETEQ:
1498  return M68k::COND_EQ;
1499  case ISD::SETGT:
1500  return M68k::COND_GT;
1501  case ISD::SETGE:
1502  return M68k::COND_GE;
1503  case ISD::SETLT:
1504  return M68k::COND_LT;
1505  case ISD::SETLE:
1506  return M68k::COND_LE;
1507  case ISD::SETNE:
1508  return M68k::COND_NE;
1509  case ISD::SETULT:
1510  return M68k::COND_CS;
1511  case ISD::SETUGE:
1512  return M68k::COND_CC;
1513  case ISD::SETUGT:
1514  return M68k::COND_HI;
1515  case ISD::SETULE:
1516  return M68k::COND_LS;
1517  }
1518 }
1519 
1520 /// Do a one-to-one translation of a ISD::CondCode to the M68k-specific
1521 /// condition code, returning the condition code and the LHS/RHS of the
1522 /// comparison to make.
1523 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL,
1524  bool IsFP, SDValue &LHS, SDValue &RHS,
1525  SelectionDAG &DAG) {
1526  if (!IsFP) {
1527  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1528  if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1529  // X > -1 -> X == 0, jump !sign.
1530  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1531  return M68k::COND_PL;
1532  }
1533  if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1534  // X < 0 -> X == 0, jump on sign.
1535  return M68k::COND_MI;
1536  }
1537  if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1538  // X < 1 -> X <= 0
1539  RHS = DAG.getConstant(0, DL, RHS.getValueType());
1540  return M68k::COND_LE;
1541  }
1542  }
1543 
1544  return TranslateIntegerM68kCC(SetCCOpcode);
1545  }
1546 
1547  // First determine if it is required or is profitable to flip the operands.
1548 
1549  // If LHS is a foldable load, but RHS is not, flip the condition.
1550  if (ISD::isNON_EXTLoad(LHS.getNode()) && !ISD::isNON_EXTLoad(RHS.getNode())) {
1551  SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1552  std::swap(LHS, RHS);
1553  }
1554 
1555  switch (SetCCOpcode) {
1556  default:
1557  break;
1558  case ISD::SETOLT:
1559  case ISD::SETOLE:
1560  case ISD::SETUGT:
1561  case ISD::SETUGE:
1562  std::swap(LHS, RHS);
1563  break;
1564  }
1565 
1566  // On a floating point condition, the flags are set as follows:
1567  // ZF PF CF op
1568  // 0 | 0 | 0 | X > Y
1569  // 0 | 0 | 1 | X < Y
1570  // 1 | 0 | 0 | X == Y
1571  // 1 | 1 | 1 | unordered
1572  switch (SetCCOpcode) {
1573  default:
1574  llvm_unreachable("Condcode should be pre-legalized away");
1575  case ISD::SETUEQ:
1576  case ISD::SETEQ:
1577  return M68k::COND_EQ;
1578  case ISD::SETOLT: // flipped
1579  case ISD::SETOGT:
1580  case ISD::SETGT:
1581  return M68k::COND_HI;
1582  case ISD::SETOLE: // flipped
1583  case ISD::SETOGE:
1584  case ISD::SETGE:
1585  return M68k::COND_CC;
1586  case ISD::SETUGT: // flipped
1587  case ISD::SETULT:
1588  case ISD::SETLT:
1589  return M68k::COND_CS;
1590  case ISD::SETUGE: // flipped
1591  case ISD::SETULE:
1592  case ISD::SETLE:
1593  return M68k::COND_LS;
1594  case ISD::SETONE:
1595  case ISD::SETNE:
1596  return M68k::COND_NE;
1597  case ISD::SETOEQ:
1598  case ISD::SETUNE:
1599  return M68k::COND_INVALID;
1600  }
1601 }
1602 
1603 // Convert (truncate (srl X, N) to i1) to (bt X, N)
1605  const SDLoc &DL, SelectionDAG &DAG) {
1606 
1607  assert(Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1 &&
1608  "Expected TRUNCATE to i1 node");
1609 
1610  if (Op.getOperand(0).getOpcode() != ISD::SRL)
1611  return SDValue();
1612 
1613  SDValue ShiftRight = Op.getOperand(0);
1614  return getBitTestCondition(ShiftRight.getOperand(0), ShiftRight.getOperand(1),
1615  CC, DL, DAG);
1616 }
1617 
1618 /// \brief return true if \c Op has a use that doesn't just read flags.
1619 static bool hasNonFlagsUse(SDValue Op) {
1620  for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
1621  ++UI) {
1622  SDNode *User = *UI;
1623  unsigned UOpNo = UI.getOperandNo();
1624  if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
1625  // Look pass truncate.
1626  UOpNo = User->use_begin().getOperandNo();
1627  User = *User->use_begin();
1628  }
1629 
1630  if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
1631  !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
1632  return true;
1633  }
1634  return false;
1635 }
1636 
1637 SDValue M68kTargetLowering::EmitTest(SDValue Op, unsigned M68kCC,
1638  const SDLoc &DL, SelectionDAG &DAG) const {
1639 
1640  // CF and OF aren't always set the way we want. Determine which
1641  // of these we need.
1642  bool NeedCF = false;
1643  bool NeedOF = false;
1644  switch (M68kCC) {
1645  default:
1646  break;
1647  case M68k::COND_HI:
1648  case M68k::COND_CC:
1649  case M68k::COND_CS:
1650  case M68k::COND_LS:
1651  NeedCF = true;
1652  break;
1653  case M68k::COND_GT:
1654  case M68k::COND_GE:
1655  case M68k::COND_LT:
1656  case M68k::COND_LE:
1657  case M68k::COND_VS:
1658  case M68k::COND_VC: {
1659  // Check if we really need to set the
1660  // Overflow flag. If NoSignedWrap is present
1661  // that is not actually needed.
1662  switch (Op->getOpcode()) {
1663  case ISD::ADD:
1664  case ISD::SUB:
1665  case ISD::MUL:
1666  case ISD::SHL: {
1667  if (Op.getNode()->getFlags().hasNoSignedWrap())
1668  break;
1670  }
1671  default:
1672  NeedOF = true;
1673  break;
1674  }
1675  break;
1676  }
1677  }
1678  // See if we can use the CCR value from the operand instead of
1679  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
1680  // we prove that the arithmetic won't overflow, we can't use OF or CF.
1681  if (Op.getResNo() != 0 || NeedOF || NeedCF) {
1682  // Emit a CMP with 0, which is the TEST pattern.
1683  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1684  DAG.getConstant(0, DL, Op.getValueType()), Op);
1685  }
1686  unsigned Opcode = 0;
1687  unsigned NumOperands = 0;
1688 
1689  // Truncate operations may prevent the merge of the SETCC instruction
1690  // and the arithmetic instruction before it. Attempt to truncate the operands
1691  // of the arithmetic instruction and use a reduced bit-width instruction.
1692  bool NeedTruncation = false;
1693  SDValue ArithOp = Op;
1694  if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
1695  SDValue Arith = Op->getOperand(0);
1696  // Both the trunc and the arithmetic op need to have one user each.
1697  if (Arith->hasOneUse())
1698  switch (Arith.getOpcode()) {
1699  default:
1700  break;
1701  case ISD::ADD:
1702  case ISD::SUB:
1703  case ISD::AND:
1704  case ISD::OR:
1705  case ISD::XOR: {
1706  NeedTruncation = true;
1707  ArithOp = Arith;
1708  }
1709  }
1710  }
1711 
1712  // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
1713  // which may be the result of a CAST. We use the variable 'Op', which is the
1714  // non-casted variable when we check for possible users.
1715  switch (ArithOp.getOpcode()) {
1716  case ISD::ADD:
1717  Opcode = M68kISD::ADD;
1718  NumOperands = 2;
1719  break;
1720  case ISD::SHL:
1721  case ISD::SRL:
1722  // If we have a constant logical shift that's only used in a comparison
1723  // against zero turn it into an equivalent AND. This allows turning it into
1724  // a TEST instruction later.
1725  if ((M68kCC == M68k::COND_EQ || M68kCC == M68k::COND_NE) &&
1726  Op->hasOneUse() && isa<ConstantSDNode>(Op->getOperand(1)) &&
1727  !hasNonFlagsUse(Op)) {
1728  EVT VT = Op.getValueType();
1729  unsigned BitWidth = VT.getSizeInBits();
1730  unsigned ShAmt = Op->getConstantOperandVal(1);
1731  if (ShAmt >= BitWidth) // Avoid undefined shifts.
1732  break;
1733  APInt Mask = ArithOp.getOpcode() == ISD::SRL
1735  : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
1736  if (!Mask.isSignedIntN(32)) // Avoid large immediates.
1737  break;
1738  Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0),
1739  DAG.getConstant(Mask, DL, VT));
1740  }
1741  break;
1742 
1743  case ISD::AND:
1744  // If the primary 'and' result isn't used, don't bother using
1745  // M68kISD::AND, because a TEST instruction will be better.
1746  if (!hasNonFlagsUse(Op)) {
1747  SDValue Op0 = ArithOp->getOperand(0);
1748  SDValue Op1 = ArithOp->getOperand(1);
1749  EVT VT = ArithOp.getValueType();
1750  bool IsAndn = isBitwiseNot(Op0) || isBitwiseNot(Op1);
1751  bool IsLegalAndnType = VT == MVT::i32 || VT == MVT::i64;
1752 
1753  // But if we can combine this into an ANDN operation, then create an AND
1754  // now and allow it to be pattern matched into an ANDN.
1755  if (/*!Subtarget.hasBMI() ||*/ !IsAndn || !IsLegalAndnType)
1756  break;
1757  }
1759  case ISD::SUB:
1760  case ISD::OR:
1761  case ISD::XOR:
1762  // Due to the ISEL shortcoming noted above, be conservative if this op is
1763  // likely to be selected as part of a load-modify-store instruction.
1764  for (const auto *U : Op.getNode()->uses())
1765  if (U->getOpcode() == ISD::STORE)
1766  goto default_case;
1767 
1768  // Otherwise use a regular CCR-setting instruction.
1769  switch (ArithOp.getOpcode()) {
1770  default:
1771  llvm_unreachable("unexpected operator!");
1772  case ISD::SUB:
1773  Opcode = M68kISD::SUB;
1774  break;
1775  case ISD::XOR:
1776  Opcode = M68kISD::XOR;
1777  break;
1778  case ISD::AND:
1779  Opcode = M68kISD::AND;
1780  break;
1781  case ISD::OR:
1782  Opcode = M68kISD::OR;
1783  break;
1784  }
1785 
1786  NumOperands = 2;
1787  break;
1788  case M68kISD::ADD:
1789  case M68kISD::SUB:
1790  case M68kISD::OR:
1791  case M68kISD::XOR:
1792  case M68kISD::AND:
1793  return SDValue(Op.getNode(), 1);
1794  default:
1795  default_case:
1796  break;
1797  }
1798 
1799  // If we found that truncation is beneficial, perform the truncation and
1800  // update 'Op'.
1801  if (NeedTruncation) {
1802  EVT VT = Op.getValueType();
1803  SDValue WideVal = Op->getOperand(0);
1804  EVT WideVT = WideVal.getValueType();
1805  unsigned ConvertedOp = 0;
1806  // Use a target machine opcode to prevent further DAGCombine
1807  // optimizations that may separate the arithmetic operations
1808  // from the setcc node.
1809  switch (WideVal.getOpcode()) {
1810  default:
1811  break;
1812  case ISD::ADD:
1813  ConvertedOp = M68kISD::ADD;
1814  break;
1815  case ISD::SUB:
1816  ConvertedOp = M68kISD::SUB;
1817  break;
1818  case ISD::AND:
1819  ConvertedOp = M68kISD::AND;
1820  break;
1821  case ISD::OR:
1822  ConvertedOp = M68kISD::OR;
1823  break;
1824  case ISD::XOR:
1825  ConvertedOp = M68kISD::XOR;
1826  break;
1827  }
1828 
1829  if (ConvertedOp) {
1830  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1831  if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
1832  SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0));
1833  SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1));
1834  Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1);
1835  }
1836  }
1837  }
1838 
1839  if (Opcode == 0) {
1840  // Emit a CMP with 0, which is the TEST pattern.
1841  return DAG.getNode(M68kISD::CMP, DL, MVT::i8,
1842  DAG.getConstant(0, DL, Op.getValueType()), Op);
1843  }
1844  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i8);
1845  SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
1846 
1847  SDValue New = DAG.getNode(Opcode, DL, VTs, Ops);
1848  DAG.ReplaceAllUsesWith(Op, New);
1849  return SDValue(New.getNode(), 1);
1850 }
1851 
1852 /// \brief Return true if the condition is an unsigned comparison operation.
1853 static bool isM68kCCUnsigned(unsigned M68kCC) {
1854  switch (M68kCC) {
1855  default:
1856  llvm_unreachable("Invalid integer condition!");
1857  case M68k::COND_EQ:
1858  case M68k::COND_NE:
1859  case M68k::COND_CS:
1860  case M68k::COND_HI:
1861  case M68k::COND_LS:
1862  case M68k::COND_CC:
1863  return true;
1864  case M68k::COND_GT:
1865  case M68k::COND_GE:
1866  case M68k::COND_LT:
1867  case M68k::COND_LE:
1868  return false;
1869  }
1870 }
1871 
1872 SDValue M68kTargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned M68kCC,
1873  const SDLoc &DL, SelectionDAG &DAG) const {
1874  if (isNullConstant(Op1))
1875  return EmitTest(Op0, M68kCC, DL, DAG);
1876 
1877  assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
1878  "Unexpected comparison operation for MVT::i1 operands");
1879 
1880  if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
1881  Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
1882  // Only promote the compare up to I32 if it is a 16 bit operation
1883  // with an immediate. 16 bit immediates are to be avoided.
1884  if ((Op0.getValueType() == MVT::i16 &&
1885  (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
1887  unsigned ExtendOp =
1889  Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0);
1890  Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1);
1891  }
1892  // Use SUB instead of CMP to enable CSE between SUB and CMP.
1893  SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i8);
1894  SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1);
1895  return SDValue(Sub.getNode(), 1);
1896  }
1897  return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1);
1898 }
1899 
1900 /// Result of 'and' or 'trunc to i1' is compared against zero.
1901 /// Change to a BTST node if possible.
1902 SDValue M68kTargetLowering::LowerToBTST(SDValue Op, ISD::CondCode CC,
1903  const SDLoc &DL,
1904  SelectionDAG &DAG) const {
1905  if (Op.getOpcode() == ISD::AND)
1906  return LowerAndToBTST(Op, CC, DL, DAG);
1907  if (Op.getOpcode() == ISD::TRUNCATE && Op.getValueType() == MVT::i1)
1908  return LowerTruncateToBTST(Op, CC, DL, DAG);
1909  return SDValue();
1910 }
1911 
1912 SDValue M68kTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1913  MVT VT = Op.getSimpleValueType();
1914  assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
1915 
1916  SDValue Op0 = Op.getOperand(0);
1917  SDValue Op1 = Op.getOperand(1);
1918  SDLoc DL(Op);
1919  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1920 
1921  // Optimize to BTST if possible.
1922  // Lower (X & (1 << N)) == 0 to BTST(X, N).
1923  // Lower ((X >>u N) & 1) != 0 to BTST(X, N).
1924  // Lower ((X >>s N) & 1) != 0 to BTST(X, N).
1925  // Lower (trunc (X >> N) to i1) to BTST(X, N).
1926  if (Op0.hasOneUse() && isNullConstant(Op1) &&
1927  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1928  if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) {
1929  if (VT == MVT::i1)
1930  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC);
1931  return NewSetCC;
1932  }
1933  }
1934 
1935  // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
1936  // these.
1937  if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
1938  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1939 
1940  // If the input is a setcc, then reuse the input setcc or use a new one with
1941  // the inverted condition.
1942  if (Op0.getOpcode() == M68kISD::SETCC) {
1944  bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
1945  if (!Invert)
1946  return Op0;
1947 
1948  CCode = M68k::GetOppositeBranchCondition(CCode);
1949  SDValue SetCC =
1951  DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1));
1952  if (VT == MVT::i1)
1953  return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC);
1954  return SetCC;
1955  }
1956  }
1957  if (Op0.getValueType() == MVT::i1 && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1958  if (isOneConstant(Op1)) {
1960  return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC);
1961  }
1962  if (!isNullConstant(Op1)) {
1963  SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1);
1964  return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC);
1965  }
1966  }
1967 
1968  bool IsFP = Op1.getSimpleValueType().isFloatingPoint();
1969  unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG);
1970  if (M68kCC == M68k::COND_INVALID)
1971  return SDValue();
1972 
1973  SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG);
1974  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1975  DAG.getConstant(M68kCC, DL, MVT::i8), CCR);
1976 }
1977 
1978 SDValue M68kTargetLowering::LowerSETCCCARRY(SDValue Op,
1979  SelectionDAG &DAG) const {
1980  SDValue LHS = Op.getOperand(0);
1981  SDValue RHS = Op.getOperand(1);
1982  SDValue Carry = Op.getOperand(2);
1983  SDValue Cond = Op.getOperand(3);
1984  SDLoc DL(Op);
1985 
1986  assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.");
1987  M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get());
1988 
1989  EVT CarryVT = Carry.getValueType();
1990  APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits());
1991  Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry,
1992  DAG.getConstant(NegOne, DL, CarryVT));
1993 
1994  SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
1995  SDValue Cmp =
1996  DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1));
1997 
1998  return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
1999  DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
2000 }
2001 
2002 /// Return true if opcode is a M68k logical comparison.
2004  unsigned Opc = Op.getNode()->getOpcode();
2005  if (Opc == M68kISD::CMP)
2006  return true;
2007  if (Op.getResNo() == 1 &&
2008  (Opc == M68kISD::ADD || Opc == M68kISD::SUB || Opc == M68kISD::ADDX ||
2009  Opc == M68kISD::SUBX || Opc == M68kISD::SMUL || Opc == M68kISD::UMUL ||
2010  Opc == M68kISD::OR || Opc == M68kISD::XOR || Opc == M68kISD::AND))
2011  return true;
2012 
2013  if (Op.getResNo() == 2 && Opc == M68kISD::UMUL)
2014  return true;
2015 
2016  return false;
2017 }
2018 
2020  if (V.getOpcode() != ISD::TRUNCATE)
2021  return false;
2022 
2023  SDValue VOp0 = V.getOperand(0);
2024  unsigned InBits = VOp0.getValueSizeInBits();
2025  unsigned Bits = V.getValueSizeInBits();
2026  return DAG.MaskedValueIsZero(VOp0,
2027  APInt::getHighBitsSet(InBits, InBits - Bits));
2028 }
2029 
2030 SDValue M68kTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2031  bool addTest = true;
2032  SDValue Cond = Op.getOperand(0);
2033  SDValue Op1 = Op.getOperand(1);
2034  SDValue Op2 = Op.getOperand(2);
2035  SDLoc DL(Op);
2036  SDValue CC;
2037 
2038  if (Cond.getOpcode() == ISD::SETCC) {
2039  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2040  Cond = NewCond;
2041  }
2042 
2043  // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
2044  // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
2045  // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
2046  // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
2047  if (Cond.getOpcode() == M68kISD::SETCC &&
2048  Cond.getOperand(1).getOpcode() == M68kISD::CMP &&
2049  isNullConstant(Cond.getOperand(1).getOperand(0))) {
2050  SDValue Cmp = Cond.getOperand(1);
2051 
2052  unsigned CondCode =
2053  cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
2054 
2055  if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2057  SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
2058 
2059  SDValue CmpOp0 = Cmp.getOperand(1);
2060  // Apply further optimizations for special cases
2061  // (select (x != 0), -1, 0) -> neg & sbb
2062  // (select (x == 0), 0, -1) -> neg & sbb
2063  if (isNullConstant(Y) &&
2064  (isAllOnesConstant(Op1) == (CondCode == M68k::COND_NE))) {
2065 
2066  SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
2067 
2068  SDValue Neg =
2069  DAG.getNode(M68kISD::SUB, DL, VTs,
2070  DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0);
2071 
2072  SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2074  SDValue(Neg.getNode(), 1));
2075  return Res;
2076  }
2077 
2078  Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8,
2079  DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0);
2080 
2081  SDValue Res = // Res = 0 or -1.
2082  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2083  DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp);
2084 
2085  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_EQ))
2086  Res = DAG.getNOT(DL, Res, Res.getValueType());
2087 
2088  if (!isNullConstant(Op2))
2089  Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
2090  return Res;
2091  }
2092  }
2093 
2094  // Look past (and (setcc_carry (cmp ...)), 1).
2095  if (Cond.getOpcode() == ISD::AND &&
2096  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2097  isOneConstant(Cond.getOperand(1)))
2098  Cond = Cond.getOperand(0);
2099 
2100  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2101  // setting operand in place of the M68kISD::SETCC.
2102  unsigned CondOpcode = Cond.getOpcode();
2103  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2104  CC = Cond.getOperand(0);
2105 
2106  SDValue Cmp = Cond.getOperand(1);
2107  unsigned Opc = Cmp.getOpcode();
2108 
2109  bool IllegalFPCMov = false;
2110 
2111  if ((isM68kLogicalCmp(Cmp) && !IllegalFPCMov) || Opc == M68kISD::BTST) {
2112  Cond = Cmp;
2113  addTest = false;
2114  }
2115  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
2116  CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2117  CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) {
2118  SDValue LHS = Cond.getOperand(0);
2119  SDValue RHS = Cond.getOperand(1);
2120  unsigned MxOpcode;
2121  unsigned MxCond;
2122  SDVTList VTs;
2123  switch (CondOpcode) {
2124  case ISD::UADDO:
2125  MxOpcode = M68kISD::ADD;
2126  MxCond = M68k::COND_CS;
2127  break;
2128  case ISD::SADDO:
2129  MxOpcode = M68kISD::ADD;
2130  MxCond = M68k::COND_VS;
2131  break;
2132  case ISD::USUBO:
2133  MxOpcode = M68kISD::SUB;
2134  MxCond = M68k::COND_CS;
2135  break;
2136  case ISD::SSUBO:
2137  MxOpcode = M68kISD::SUB;
2138  MxCond = M68k::COND_VS;
2139  break;
2140  case ISD::UMULO:
2141  MxOpcode = M68kISD::UMUL;
2142  MxCond = M68k::COND_VS;
2143  break;
2144  case ISD::SMULO:
2145  MxOpcode = M68kISD::SMUL;
2146  MxCond = M68k::COND_VS;
2147  break;
2148  default:
2149  llvm_unreachable("unexpected overflowing operator");
2150  }
2151  if (CondOpcode == ISD::UMULO)
2152  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i32);
2153  else
2154  VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
2155 
2156  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2157 
2158  if (CondOpcode == ISD::UMULO)
2159  Cond = MxOp.getValue(2);
2160  else
2161  Cond = MxOp.getValue(1);
2162 
2163  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2164  addTest = false;
2165  }
2166 
2167  if (addTest) {
2168  // Look past the truncate if the high bits are known zero.
2170  Cond = Cond.getOperand(0);
2171 
2172  // We know the result of AND is compared against zero. Try to match
2173  // it to BT.
2174  if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
2175  if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2176  CC = NewSetCC.getOperand(0);
2177  Cond = NewSetCC.getOperand(1);
2178  addTest = false;
2179  }
2180  }
2181  }
2182 
2183  if (addTest) {
2184  CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8);
2185  Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG);
2186  }
2187 
2188  // a < b ? -1 : 0 -> RES = ~setcc_carry
2189  // a < b ? 0 : -1 -> RES = setcc_carry
2190  // a >= b ? -1 : 0 -> RES = setcc_carry
2191  // a >= b ? 0 : -1 -> RES = ~setcc_carry
2192  if (Cond.getOpcode() == M68kISD::SUB) {
2193  unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
2194 
2195  if ((CondCode == M68k::COND_CC || CondCode == M68k::COND_CS) &&
2196  (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
2197  (isNullConstant(Op1) || isNullConstant(Op2))) {
2198  SDValue Res =
2199  DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(),
2201  if (isAllOnesConstant(Op1) != (CondCode == M68k::COND_CS))
2202  return DAG.getNOT(DL, Res, Res.getValueType());
2203  return Res;
2204  }
2205  }
2206 
2207  // M68k doesn't have an i8 cmov. If both operands are the result of a
2208  // truncate widen the cmov and push the truncate through. This avoids
2209  // introducing a new branch during isel and doesn't add any extensions.
2210  if (Op.getValueType() == MVT::i8 && Op1.getOpcode() == ISD::TRUNCATE &&
2211  Op2.getOpcode() == ISD::TRUNCATE) {
2212  SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
2213  if (T1.getValueType() == T2.getValueType() &&
2214  // Block CopyFromReg so partial register stalls are avoided.
2215  T1.getOpcode() != ISD::CopyFromReg &&
2216  T2.getOpcode() != ISD::CopyFromReg) {
2217  SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
2218  SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond);
2219  return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
2220  }
2221  }
2222 
2223  // M68kISD::CMOV means set the result (which is operand 1) to the RHS if
2224  // condition is true.
2225  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2226  SDValue Ops[] = {Op2, Op1, CC, Cond};
2227  return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops);
2228 }
2229 
2230 /// Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes
2231 /// each of which has no other use apart from the AND / OR.
2232 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
2233  Opc = Op.getOpcode();
2234  if (Opc != ISD::OR && Opc != ISD::AND)
2235  return false;
2236  return (M68k::IsSETCC(Op.getOperand(0).getOpcode()) &&
2237  Op.getOperand(0).hasOneUse() &&
2238  M68k::IsSETCC(Op.getOperand(1).getOpcode()) &&
2239  Op.getOperand(1).hasOneUse());
2240 }
2241 
2242 /// Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the
2243 /// SETCC node has a single use.
2244 static bool isXor1OfSetCC(SDValue Op) {
2245  if (Op.getOpcode() != ISD::XOR)
2246  return false;
2247  if (isOneConstant(Op.getOperand(1)))
2248  return Op.getOperand(0).getOpcode() == M68kISD::SETCC &&
2249  Op.getOperand(0).hasOneUse();
2250  return false;
2251 }
2252 
2253 SDValue M68kTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2254  bool AddTest = true;
2255  SDValue Chain = Op.getOperand(0);
2256  SDValue Cond = Op.getOperand(1);
2257  SDValue Dest = Op.getOperand(2);
2258  SDLoc DL(Op);
2259  SDValue CC;
2260  bool Inverted = false;
2261 
2262  if (Cond.getOpcode() == ISD::SETCC) {
2263  // Check for setcc([su]{add,sub}o == 0).
2264  if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
2265  isNullConstant(Cond.getOperand(1)) &&
2266  Cond.getOperand(0).getResNo() == 1 &&
2267  (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
2268  Cond.getOperand(0).getOpcode() == ISD::UADDO ||
2269  Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
2270  Cond.getOperand(0).getOpcode() == ISD::USUBO)) {
2271  Inverted = true;
2272  Cond = Cond.getOperand(0);
2273  } else {
2274  if (SDValue NewCond = LowerSETCC(Cond, DAG))
2275  Cond = NewCond;
2276  }
2277  }
2278 
2279  // Look pass (and (setcc_carry (cmp ...)), 1).
2280  if (Cond.getOpcode() == ISD::AND &&
2281  Cond.getOperand(0).getOpcode() == M68kISD::SETCC_CARRY &&
2282  isOneConstant(Cond.getOperand(1)))
2283  Cond = Cond.getOperand(0);
2284 
2285  // If condition flag is set by a M68kISD::CMP, then use it as the condition
2286  // setting operand in place of the M68kISD::SETCC.
2287  unsigned CondOpcode = Cond.getOpcode();
2288  if (CondOpcode == M68kISD::SETCC || CondOpcode == M68kISD::SETCC_CARRY) {
2289  CC = Cond.getOperand(0);
2290 
2291  SDValue Cmp = Cond.getOperand(1);
2292  unsigned Opc = Cmp.getOpcode();
2293 
2294  if (isM68kLogicalCmp(Cmp) || Opc == M68kISD::BTST) {
2295  Cond = Cmp;
2296  AddTest = false;
2297  } else {
2298  switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
2299  default:
2300  break;
2301  case M68k::COND_VS:
2302  case M68k::COND_CS:
2303  // These can only come from an arithmetic instruction with overflow,
2304  // e.g. SADDO, UADDO.
2305  Cond = Cond.getNode()->getOperand(1);
2306  AddTest = false;
2307  break;
2308  }
2309  }
2310  }
2311  CondOpcode = Cond.getOpcode();
2312  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
2313  CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO) {
2314  SDValue LHS = Cond.getOperand(0);
2315  SDValue RHS = Cond.getOperand(1);
2316  unsigned MxOpcode;
2317  unsigned MxCond;
2318  SDVTList VTs;
2319  // Keep this in sync with LowerXALUO, otherwise we might create redundant
2320  // instructions that can't be removed afterwards (i.e. M68kISD::ADD and
2321  // M68kISD::INC).
2322  switch (CondOpcode) {
2323  case ISD::UADDO:
2324  MxOpcode = M68kISD::ADD;
2325  MxCond = M68k::COND_CS;
2326  break;
2327  case ISD::SADDO:
2328  MxOpcode = M68kISD::ADD;
2329  MxCond = M68k::COND_VS;
2330  break;
2331  case ISD::USUBO:
2332  MxOpcode = M68kISD::SUB;
2333  MxCond = M68k::COND_CS;
2334  break;
2335  case ISD::SSUBO:
2336  MxOpcode = M68kISD::SUB;
2337  MxCond = M68k::COND_VS;
2338  break;
2339  case ISD::UMULO:
2340  MxOpcode = M68kISD::UMUL;
2341  MxCond = M68k::COND_VS;
2342  break;
2343  case ISD::SMULO:
2344  MxOpcode = M68kISD::SMUL;
2345  MxCond = M68k::COND_VS;
2346  break;
2347  default:
2348  llvm_unreachable("unexpected overflowing operator");
2349  }
2350 
2351  if (Inverted)
2353 
2354  if (CondOpcode == ISD::UMULO)
2355  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(), MVT::i8);
2356  else
2357  VTs = DAG.getVTList(LHS.getValueType(), MVT::i8);
2358 
2359  SDValue MxOp = DAG.getNode(MxOpcode, DL, VTs, LHS, RHS);
2360 
2361  if (CondOpcode == ISD::UMULO)
2362  Cond = MxOp.getValue(2);
2363  else
2364  Cond = MxOp.getValue(1);
2365 
2366  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2367  AddTest = false;
2368  } else {
2369  unsigned CondOpc;
2370  if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
2371  SDValue Cmp = Cond.getOperand(0).getOperand(1);
2372  if (CondOpc == ISD::OR) {
2373  // Also, recognize the pattern generated by an FCMP_UNE. We can emit
2374  // two branches instead of an explicit OR instruction with a
2375  // separate test.
2376  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp)) {
2377  CC = Cond.getOperand(0).getOperand(0);
2378  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2379  Dest, CC, Cmp);
2380  CC = Cond.getOperand(1).getOperand(0);
2381  Cond = Cmp;
2382  AddTest = false;
2383  }
2384  } else { // ISD::AND
2385  // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
2386  // two branches instead of an explicit AND instruction with a
2387  // separate test. However, we only do this if this block doesn't
2388  // have a fall-through edge, because this requires an explicit
2389  // jmp when the condition is false.
2390  if (Cmp == Cond.getOperand(1).getOperand(1) && isM68kLogicalCmp(Cmp) &&
2391  Op.getNode()->hasOneUse()) {
2392  M68k::CondCode CCode =
2393  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2394  CCode = M68k::GetOppositeBranchCondition(CCode);
2395  CC = DAG.getConstant(CCode, DL, MVT::i8);
2396  SDNode *User = *Op.getNode()->use_begin();
2397  // Look for an unconditional branch following this conditional branch.
2398  // We need this because we need to reverse the successors in order
2399  // to implement FCMP_OEQ.
2400  if (User->getOpcode() == ISD::BR) {
2401  SDValue FalseBB = User->getOperand(1);
2402  SDNode *NewBR =
2403  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
2404  assert(NewBR == User);
2405  (void)NewBR;
2406  Dest = FalseBB;
2407 
2408  Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain,
2409  Dest, CC, Cmp);
2410  M68k::CondCode CCode =
2411  (M68k::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
2412  CCode = M68k::GetOppositeBranchCondition(CCode);
2413  CC = DAG.getConstant(CCode, DL, MVT::i8);
2414  Cond = Cmp;
2415  AddTest = false;
2416  }
2417  }
2418  }
2419  } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
2420  // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
2421  // It should be transformed during dag combiner except when the condition
2422  // is set by a arithmetics with overflow node.
2423  M68k::CondCode CCode =
2424  (M68k::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
2425  CCode = M68k::GetOppositeBranchCondition(CCode);
2426  CC = DAG.getConstant(CCode, DL, MVT::i8);
2427  Cond = Cond.getOperand(0).getOperand(1);
2428  AddTest = false;
2429  }
2430  }
2431 
2432  if (AddTest) {
2433  // Look pass the truncate if the high bits are known zero.
2435  Cond = Cond.getOperand(0);
2436 
2437  // We know the result is compared against zero. Try to match it to BT.
2438  if (Cond.hasOneUse()) {
2439  if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) {
2440  CC = NewSetCC.getOperand(0);
2441  Cond = NewSetCC.getOperand(1);
2442  AddTest = false;
2443  }
2444  }
2445  }
2446 
2447  if (AddTest) {
2448  M68k::CondCode MxCond = Inverted ? M68k::COND_EQ : M68k::COND_NE;
2449  CC = DAG.getConstant(MxCond, DL, MVT::i8);
2450  Cond = EmitTest(Cond, MxCond, DL, DAG);
2451  }
2452  return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC,
2453  Cond);
2454 }
2455 
2456 SDValue M68kTargetLowering::LowerADDC_ADDE_SUBC_SUBE(SDValue Op,
2457  SelectionDAG &DAG) const {
2458  MVT VT = Op.getNode()->getSimpleValueType(0);
2459 
2460  // Let legalize expand this if it isn't a legal type yet.
2461  if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2462  return SDValue();
2463 
2464  SDVTList VTs = DAG.getVTList(VT, MVT::i8);
2465 
2466  unsigned Opc;
2467  bool ExtraOp = false;
2468  switch (Op.getOpcode()) {
2469  default:
2470  llvm_unreachable("Invalid code");
2471  case ISD::ADDC:
2472  Opc = M68kISD::ADD;
2473  break;
2474  case ISD::ADDE:
2475  Opc = M68kISD::ADDX;
2476  ExtraOp = true;
2477  break;
2478  case ISD::SUBC:
2479  Opc = M68kISD::SUB;
2480  break;
2481  case ISD::SUBE:
2482  Opc = M68kISD::SUBX;
2483  ExtraOp = true;
2484  break;
2485  }
2486 
2487  if (!ExtraOp)
2488  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2489  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2490  Op.getOperand(2));
2491 }
2492 
2493 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2494 // their target countpart wrapped in the M68kISD::Wrapper node. Suppose N is
2495 // one of the above mentioned nodes. It has to be wrapped because otherwise
2496 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2497 // be used to form addressing mode. These wrapped nodes will be selected
2498 // into MOV32ri.
2499 SDValue M68kTargetLowering::LowerConstantPool(SDValue Op,
2500  SelectionDAG &DAG) const {
2501  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2502 
2503  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2504  // global base reg.
2505  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2506 
2507  unsigned WrapperKind = M68kISD::Wrapper;
2508  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2509  WrapperKind = M68kISD::WrapperPC;
2510  }
2511 
2512  MVT PtrVT = getPointerTy(DAG.getDataLayout());
2514  CP->getConstVal(), PtrVT, CP->getAlign(), CP->getOffset(), OpFlag);
2515 
2516  SDLoc DL(CP);
2517  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2518 
2519  // With PIC, the address is actually $g + Offset.
2520  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2521  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2522  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2523  Result);
2524  }
2525 
2526  return Result;
2527 }
2528 
2529 SDValue M68kTargetLowering::LowerExternalSymbol(SDValue Op,
2530  SelectionDAG &DAG) const {
2531  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
2532 
2533  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2534  // global base reg.
2535  const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
2536  unsigned char OpFlag = Subtarget.classifyExternalReference(*Mod);
2537 
2538  unsigned WrapperKind = M68kISD::Wrapper;
2539  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2540  WrapperKind = M68kISD::WrapperPC;
2541  }
2542 
2543  auto PtrVT = getPointerTy(DAG.getDataLayout());
2544  SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
2545 
2546  SDLoc DL(Op);
2547  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2548 
2549  // With PIC, the address is actually $g + Offset.
2550  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2551  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2552  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2553  Result);
2554  }
2555 
2556  // For symbols that require a load from a stub to get the address, emit the
2557  // load.
2558  if (M68kII::isGlobalStubReference(OpFlag)) {
2559  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2561  }
2562 
2563  return Result;
2564 }
2565 
2566 SDValue M68kTargetLowering::LowerBlockAddress(SDValue Op,
2567  SelectionDAG &DAG) const {
2568  unsigned char OpFlags = Subtarget.classifyBlockAddressReference();
2569  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2570  int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
2571  SDLoc DL(Op);
2572  auto PtrVT = getPointerTy(DAG.getDataLayout());
2573 
2574  // Create the TargetBlockAddressAddress node.
2575  SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
2576 
2577  if (M68kII::isPCRelBlockReference(OpFlags)) {
2578  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2579  } else {
2580  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2581  }
2582 
2583  // With PIC, the address is actually $g + Offset.
2584  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2585  Result =
2586  DAG.getNode(ISD::ADD, DL, PtrVT,
2587  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2588  }
2589 
2590  return Result;
2591 }
2592 
2593 SDValue M68kTargetLowering::LowerGlobalAddress(const GlobalValue *GV,
2594  const SDLoc &DL, int64_t Offset,
2595  SelectionDAG &DAG) const {
2596  unsigned char OpFlags = Subtarget.classifyGlobalReference(GV);
2597  auto PtrVT = getPointerTy(DAG.getDataLayout());
2598 
2599  // Create the TargetGlobalAddress node, folding in the constant
2600  // offset if it is legal.
2601  SDValue Result;
2602  if (M68kII::isDirectGlobalReference(OpFlags)) {
2603  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
2604  Offset = 0;
2605  } else {
2606  Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2607  }
2608 
2609  if (M68kII::isPCRelGlobalReference(OpFlags))
2610  Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result);
2611  else
2612  Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result);
2613 
2614  // With PIC, the address is actually $g + Offset.
2615  if (M68kII::isGlobalRelativeToPICBase(OpFlags)) {
2616  Result =
2617  DAG.getNode(ISD::ADD, DL, PtrVT,
2618  DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result);
2619  }
2620 
2621  // For globals that require a load from a stub to get the address, emit the
2622  // load.
2623  if (M68kII::isGlobalStubReference(OpFlags)) {
2624  Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2626  }
2627 
2628  // If there was a non-zero offset that we didn't fold, create an explicit
2629  // addition for it.
2630  if (Offset != 0) {
2631  Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2632  DAG.getConstant(Offset, DL, PtrVT));
2633  }
2634 
2635  return Result;
2636 }
2637 
2638 SDValue M68kTargetLowering::LowerGlobalAddress(SDValue Op,
2639  SelectionDAG &DAG) const {
2640  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2641  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
2642  return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
2643 }
2644 
2645 //===----------------------------------------------------------------------===//
2646 // Custom Lower Jump Table
2647 //===----------------------------------------------------------------------===//
2648 
2649 SDValue M68kTargetLowering::LowerJumpTable(SDValue Op,
2650  SelectionDAG &DAG) const {
2651  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2652 
2653  // In PIC mode (unless we're in PCRel PIC mode) we add an offset to the
2654  // global base reg.
2655  unsigned char OpFlag = Subtarget.classifyLocalReference(nullptr);
2656 
2657  unsigned WrapperKind = M68kISD::Wrapper;
2658  if (M68kII::isPCRelGlobalReference(OpFlag)) {
2659  WrapperKind = M68kISD::WrapperPC;
2660  }
2661 
2662  auto PtrVT = getPointerTy(DAG.getDataLayout());
2663  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
2664  SDLoc DL(JT);
2665  Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
2666 
2667  // With PIC, the address is actually $g + Offset.
2668  if (M68kII::isGlobalRelativeToPICBase(OpFlag)) {
2669  Result = DAG.getNode(ISD::ADD, DL, PtrVT,
2670  DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(), PtrVT),
2671  Result);
2672  }
2673 
2674  return Result;
2675 }
2676 
2678  return Subtarget.getJumpTableEncoding();
2679 }
2680 
2682  const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB,
2683  unsigned uid, MCContext &Ctx) const {
2685  Ctx);
2686 }
2687 
2689  SelectionDAG &DAG) const {
2691  return DAG.getNode(M68kISD::GLOBAL_BASE_REG, SDLoc(),
2692  getPointerTy(DAG.getDataLayout()));
2693 
2694  // MachineJumpTableInfo::EK_LabelDifference32 entry
2695  return Table;
2696 }
2697 
2698 // NOTE This only used for MachineJumpTableInfo::EK_LabelDifference32 entries
2700  const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const {
2701  return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
2702 }
2703 
2706  if (Constraint.size() > 0) {
2707  switch (Constraint[0]) {
2708  case 'a':
2709  case 'd':
2710  return C_RegisterClass;
2711  case 'I':
2712  case 'J':
2713  case 'K':
2714  case 'L':
2715  case 'M':
2716  case 'N':
2717  case 'O':
2718  case 'P':
2719  return C_Immediate;
2720  case 'C':
2721  if (Constraint.size() == 2)
2722  switch (Constraint[1]) {
2723  case '0':
2724  case 'i':
2725  case 'j':
2726  return C_Immediate;
2727  default:
2728  break;
2729  }
2730  break;
2731  default:
2732  break;
2733  }
2734  }
2735 
2736  return TargetLowering::getConstraintType(Constraint);
2737 }
2738 
2740  std::string &Constraint,
2741  std::vector<SDValue> &Ops,
2742  SelectionDAG &DAG) const {
2743  SDValue Result;
2744 
2745  if (Constraint.size() == 1) {
2746  // Constant constraints
2747  switch (Constraint[0]) {
2748  case 'I':
2749  case 'J':
2750  case 'K':
2751  case 'L':
2752  case 'M':
2753  case 'N':
2754  case 'O':
2755  case 'P': {
2756  auto *C = dyn_cast<ConstantSDNode>(Op);
2757  if (!C)
2758  return;
2759 
2760  int64_t Val = C->getSExtValue();
2761  switch (Constraint[0]) {
2762  case 'I': // constant integer in the range [1,8]
2763  if (Val > 0 && Val <= 8)
2764  break;
2765  return;
2766  case 'J': // constant signed 16-bit integer
2767  if (isInt<16>(Val))
2768  break;
2769  return;
2770  case 'K': // constant that is NOT in the range of [-0x80, 0x80)
2771  if (Val < -0x80 || Val >= 0x80)
2772  break;
2773  return;
2774  case 'L': // constant integer in the range [-8,-1]
2775  if (Val < 0 && Val >= -8)
2776  break;
2777  return;
2778  case 'M': // constant that is NOT in the range of [-0x100, 0x100]
2779  if (Val < -0x100 || Val >= 0x100)
2780  break;
2781  return;
2782  case 'N': // constant integer in the range [24,31]
2783  if (Val >= 24 && Val <= 31)
2784  break;
2785  return;
2786  case 'O': // constant integer 16
2787  if (Val == 16)
2788  break;
2789  return;
2790  case 'P': // constant integer in the range [8,15]
2791  if (Val >= 8 && Val <= 15)
2792  break;
2793  return;
2794  default:
2795  llvm_unreachable("Unhandled constant constraint");
2796  }
2797 
2798  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2799  break;
2800  }
2801  default:
2802  break;
2803  }
2804  }
2805 
2806  if (Constraint.size() == 2) {
2807  switch (Constraint[0]) {
2808  case 'C':
2809  // Constant constraints start with 'C'
2810  switch (Constraint[1]) {
2811  case '0':
2812  case 'i':
2813  case 'j': {
2814  auto *C = dyn_cast<ConstantSDNode>(Op);
2815  if (!C)
2816  break;
2817 
2818  int64_t Val = C->getSExtValue();
2819  switch (Constraint[1]) {
2820  case '0': // constant integer 0
2821  if (!Val)
2822  break;
2823  return;
2824  case 'i': // constant integer
2825  break;
2826  case 'j': // integer constant that doesn't fit in 16 bits
2827  if (!isInt<16>(C->getSExtValue()))
2828  break;
2829  return;
2830  default:
2831  llvm_unreachable("Unhandled constant constraint");
2832  }
2833 
2834  Result = DAG.getTargetConstant(Val, SDLoc(Op), Op.getValueType());
2835  break;
2836  }
2837  default:
2838  break;
2839  }
2840  break;
2841  default:
2842  break;
2843  }
2844  }
2845 
2846  if (Result.getNode()) {
2847  Ops.push_back(Result);
2848  return;
2849  }
2850 
2851  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2852 }
2853 
2854 std::pair<unsigned, const TargetRegisterClass *>
2856  StringRef Constraint,
2857  MVT VT) const {
2858  if (Constraint.size() == 1) {
2859  switch (Constraint[0]) {
2860  case 'r':
2861  case 'd':
2862  switch (VT.SimpleTy) {
2863  case MVT::i8:
2864  return std::make_pair(0U, &M68k::DR8RegClass);
2865  case MVT::i16:
2866  return std::make_pair(0U, &M68k::DR16RegClass);
2867  case MVT::i32:
2868  return std::make_pair(0U, &M68k::DR32RegClass);
2869  default:
2870  break;
2871  }
2872  break;
2873  case 'a':
2874  switch (VT.SimpleTy) {
2875  case MVT::i16:
2876  return std::make_pair(0U, &M68k::AR16RegClass);
2877  case MVT::i32:
2878  return std::make_pair(0U, &M68k::AR32RegClass);
2879  default:
2880  break;
2881  }
2882  break;
2883  default:
2884  break;
2885  }
2886  }
2887 
2888  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2889 }
2890 
2891 /// Determines whether the callee is required to pop its own arguments.
2892 /// Callee pop is necessary to support tail calls.
2894  bool GuaranteeTCO) {
2895  return false;
2896 }
2897 
2898 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
2899 // together with other CMOV pseudo-opcodes into a single basic-block with
2900 // conditional jump around it.
2902  switch (MI.getOpcode()) {
2903  case M68k::CMOV8d:
2904  case M68k::CMOV16d:
2905  case M68k::CMOV32r:
2906  return true;
2907 
2908  default:
2909  return false;
2910  }
2911 }
2912 
2913 // The CCR operand of SelectItr might be missing a kill marker
2914 // because there were multiple uses of CCR, and ISel didn't know
2915 // which to mark. Figure out whether SelectItr should have had a
2916 // kill marker, and set it if it should. Returns the correct kill
2917 // marker value.
2920  const TargetRegisterInfo *TRI) {
2921  // Scan forward through BB for a use/def of CCR.
2922  MachineBasicBlock::iterator miI(std::next(SelectItr));
2923  for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
2924  const MachineInstr &mi = *miI;
2925  if (mi.readsRegister(M68k::CCR))
2926  return false;
2927  if (mi.definesRegister(M68k::CCR))
2928  break; // Should have kill-flag - update below.
2929  }
2930 
2931  // If we hit the end of the block, check whether CCR is live into a
2932  // successor.
2933  if (miI == BB->end())
2934  for (const auto *SBB : BB->successors())
2935  if (SBB->isLiveIn(M68k::CCR))
2936  return false;
2937 
2938  // We found a def, or hit the end of the basic block and CCR wasn't live
2939  // out. SelectMI should have a kill flag on CCR.
2940  SelectItr->addRegisterKilled(M68k::CCR, TRI);
2941  return true;
2942 }
2943 
2945 M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI,
2946  MachineBasicBlock *MBB) const {
2947  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
2948  DebugLoc DL = MI.getDebugLoc();
2949 
2950  // To "insert" a SELECT_CC instruction, we actually have to insert the
2951  // diamond control-flow pattern. The incoming instruction knows the
2952  // destination vreg to set, the condition code register to branch on, the
2953  // true/false values to select between, and a branch opcode to use.
2954  const BasicBlock *BB = MBB->getBasicBlock();
2956 
2957  // ThisMBB:
2958  // ...
2959  // TrueVal = ...
2960  // cmp ccX, r1, r2
2961  // bcc Copy1MBB
2962  // fallthrough --> Copy0MBB
2963  MachineBasicBlock *ThisMBB = MBB;
2965 
2966  // This code lowers all pseudo-CMOV instructions. Generally it lowers these
2967  // as described above, by inserting a MBB, and then making a PHI at the join
2968  // point to select the true and false operands of the CMOV in the PHI.
2969  //
2970  // The code also handles two different cases of multiple CMOV opcodes
2971  // in a row.
2972  //
2973  // Case 1:
2974  // In this case, there are multiple CMOVs in a row, all which are based on
2975  // the same condition setting (or the exact opposite condition setting).
2976  // In this case we can lower all the CMOVs using a single inserted MBB, and
2977  // then make a number of PHIs at the join point to model the CMOVs. The only
2978  // trickiness here, is that in a case like:
2979  //
2980  // t2 = CMOV cond1 t1, f1
2981  // t3 = CMOV cond1 t2, f2
2982  //
2983  // when rewriting this into PHIs, we have to perform some renaming on the
2984  // temps since you cannot have a PHI operand refer to a PHI result earlier
2985  // in the same block. The "simple" but wrong lowering would be:
2986  //
2987  // t2 = PHI t1(BB1), f1(BB2)
2988  // t3 = PHI t2(BB1), f2(BB2)
2989  //
2990  // but clearly t2 is not defined in BB1, so that is incorrect. The proper
2991  // renaming is to note that on the path through BB1, t2 is really just a
2992  // copy of t1, and do that renaming, properly generating:
2993  //
2994  // t2 = PHI t1(BB1), f1(BB2)
2995  // t3 = PHI t1(BB1), f2(BB2)
2996  //
2997  // Case 2, we lower cascaded CMOVs such as
2998  //
2999  // (CMOV (CMOV F, T, cc1), T, cc2)
3000  //
3001  // to two successives branches.
3002  MachineInstr *CascadedCMOV = nullptr;
3003  MachineInstr *LastCMOV = &MI;
3004  M68k::CondCode CC = M68k::CondCode(MI.getOperand(3).getImm());
3006  MachineBasicBlock::iterator NextMIIt =
3007  std::next(MachineBasicBlock::iterator(MI));
3008 
3009  // Check for case 1, where there are multiple CMOVs with the same condition
3010  // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
3011  // number of jumps the most.
3012 
3013  if (isCMOVPseudo(MI)) {
3014  // See if we have a string of CMOVS with the same condition.
3015  while (NextMIIt != MBB->end() && isCMOVPseudo(*NextMIIt) &&
3016  (NextMIIt->getOperand(3).getImm() == CC ||
3017  NextMIIt->getOperand(3).getImm() == OppCC)) {
3018  LastCMOV = &*NextMIIt;
3019  ++NextMIIt;
3020  }
3021  }
3022 
3023  // This checks for case 2, but only do this if we didn't already find
3024  // case 1, as indicated by LastCMOV == MI.
3025  if (LastCMOV == &MI && NextMIIt != MBB->end() &&
3026  NextMIIt->getOpcode() == MI.getOpcode() &&
3027  NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
3028  NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
3029  NextMIIt->getOperand(1).isKill()) {
3030  CascadedCMOV = &*NextMIIt;
3031  }
3032 
3033  MachineBasicBlock *Jcc1MBB = nullptr;
3034 
3035  // If we have a cascaded CMOV, we lower it to two successive branches to
3036  // the same block. CCR is used by both, so mark it as live in the second.
3037  if (CascadedCMOV) {
3038  Jcc1MBB = F->CreateMachineBasicBlock(BB);
3039  F->insert(It, Jcc1MBB);
3040  Jcc1MBB->addLiveIn(M68k::CCR);
3041  }
3042 
3043  MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(BB);
3044  MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(BB);
3045  F->insert(It, Copy0MBB);
3046  F->insert(It, SinkMBB);
3047 
3048  // If the CCR register isn't dead in the terminator, then claim that it's
3049  // live into the sink and copy blocks.
3050  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3051 
3052  MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
3053  if (!LastCCRSUser->killsRegister(M68k::CCR) &&
3054  !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) {
3055  Copy0MBB->addLiveIn(M68k::CCR);
3056  SinkMBB->addLiveIn(M68k::CCR);
3057  }
3058 
3059  // Transfer the remainder of MBB and its successor edges to SinkMBB.
3060  SinkMBB->splice(SinkMBB->begin(), MBB,
3061  std::next(MachineBasicBlock::iterator(LastCMOV)), MBB->end());
3063 
3064  // Add the true and fallthrough blocks as its successors.
3065  if (CascadedCMOV) {
3066  // The fallthrough block may be Jcc1MBB, if we have a cascaded CMOV.
3067  MBB->addSuccessor(Jcc1MBB);
3068 
3069  // In that case, Jcc1MBB will itself fallthrough the Copy0MBB, and
3070  // jump to the SinkMBB.
3071  Jcc1MBB->addSuccessor(Copy0MBB);
3072  Jcc1MBB->addSuccessor(SinkMBB);
3073  } else {
3074  MBB->addSuccessor(Copy0MBB);
3075  }
3076 
3077  // The true block target of the first (or only) branch is always SinkMBB.
3078  MBB->addSuccessor(SinkMBB);
3079 
3080  // Create the conditional branch instruction.
3081  unsigned Opc = M68k::GetCondBranchFromCond(CC);
3082  BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB);
3083 
3084  if (CascadedCMOV) {
3085  unsigned Opc2 = M68k::GetCondBranchFromCond(
3086  (M68k::CondCode)CascadedCMOV->getOperand(3).getImm());
3087  BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB);
3088  }
3089 
3090  // Copy0MBB:
3091  // %FalseValue = ...
3092  // # fallthrough to SinkMBB
3093  Copy0MBB->addSuccessor(SinkMBB);
3094 
3095  // SinkMBB:
3096  // %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
3097  // ...
3099  MachineBasicBlock::iterator MIItEnd =
3100  std::next(MachineBasicBlock::iterator(LastCMOV));
3101  MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
3103  MachineInstrBuilder MIB;
3104 
3105  // As we are creating the PHIs, we have to be careful if there is more than
3106  // one. Later CMOVs may reference the results of earlier CMOVs, but later
3107  // PHIs have to reference the individual true/false inputs from earlier PHIs.
3108  // That also means that PHI construction must work forward from earlier to
3109  // later, and that the code must maintain a mapping from earlier PHI's
3110  // destination registers, and the registers that went into the PHI.
3111 
3112  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
3113  Register DestReg = MIIt->getOperand(0).getReg();
3114  Register Op1Reg = MIIt->getOperand(1).getReg();
3115  Register Op2Reg = MIIt->getOperand(2).getReg();
3116 
3117  // If this CMOV we are generating is the opposite condition from
3118  // the jump we generated, then we have to swap the operands for the
3119  // PHI that is going to be generated.
3120  if (MIIt->getOperand(3).getImm() == OppCC)
3121  std::swap(Op1Reg, Op2Reg);
3122 
3123  if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
3124  Op1Reg = RegRewriteTable[Op1Reg].first;
3125 
3126  if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
3127  Op2Reg = RegRewriteTable[Op2Reg].second;
3128 
3129  MIB =
3130  BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg)
3131  .addReg(Op1Reg)
3132  .addMBB(Copy0MBB)
3133  .addReg(Op2Reg)
3134  .addMBB(ThisMBB);
3135 
3136  // Add this PHI to the rewrite table.
3137  RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
3138  }
3139 
3140  // If we have a cascaded CMOV, the second Jcc provides the same incoming
3141  // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
3142  if (CascadedCMOV) {
3143  MIB.addReg(MI.getOperand(2).getReg()).addMBB(Jcc1MBB);
3144  // Copy the PHI result to the register defined by the second CMOV.
3145  BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
3146  DL, TII->get(TargetOpcode::COPY),
3147  CascadedCMOV->getOperand(0).getReg())
3148  .addReg(MI.getOperand(0).getReg());
3149  CascadedCMOV->eraseFromParent();
3150  }
3151 
3152  // Now remove the CMOV(s).
3153  for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd;)
3154  (MIIt++)->eraseFromParent();
3155 
3156  return SinkMBB;
3157 }
3158 
3160 M68kTargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
3161  MachineBasicBlock *BB) const {
3162  llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on");
3163 }
3164 
3167  MachineBasicBlock *BB) const {
3168  switch (MI.getOpcode()) {
3169  default:
3170  llvm_unreachable("Unexpected instr type to insert");
3171  case M68k::CMOV8d:
3172  case M68k::CMOV16d:
3173  case M68k::CMOV32r:
3174  return EmitLoweredSelect(MI, BB);
3175  case M68k::SALLOCA:
3176  return EmitLoweredSegAlloca(MI, BB);
3177  }
3178 }
3179 
3180 SDValue M68kTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3181  MachineFunction &MF = DAG.getMachineFunction();
3182  auto PtrVT = getPointerTy(MF.getDataLayout());
3184 
3185  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3186  SDLoc DL(Op);
3187 
3188  // vastart just stores the address of the VarArgsFrameIndex slot into the
3189  // memory location argument.
3190  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3191  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3192  MachinePointerInfo(SV));
3193 }
3194 
3195 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3196 // Calls to _alloca are needed to probe the stack when allocating more than 4k
3197 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3198 // that the guard pages used by the OS virtual memory manager are allocated in
3199 // correct sequence.
3200 SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3201  SelectionDAG &DAG) const {
3202  MachineFunction &MF = DAG.getMachineFunction();
3203  bool SplitStack = MF.shouldSplitStack();
3204 
3205  SDLoc DL(Op);
3206 
3207  // Get the inputs.
3208  SDNode *Node = Op.getNode();
3209  SDValue Chain = Op.getOperand(0);
3210  SDValue Size = Op.getOperand(1);
3211  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3212  EVT VT = Node->getValueType(0);
3213 
3214  // Chain the dynamic stack allocation so that it doesn't modify the stack
3215  // pointer when other instructions are using the stack.
3216  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3217 
3218  SDValue Result;
3219  if (SplitStack) {
3220  auto &MRI = MF.getRegInfo();
3221  auto SPTy = getPointerTy(DAG.getDataLayout());
3222  auto *ARClass = getRegClassFor(SPTy);
3223  Register Vreg = MRI.createVirtualRegister(ARClass);
3224  Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size);
3225  Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain,
3226  DAG.getRegister(Vreg, SPTy));
3227  } else {
3228  auto &TLI = DAG.getTargetLoweringInfo();
3230  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
3231  " not tell us which reg is the stack pointer!");
3232 
3233  SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT);
3234  Chain = SP.getValue(1);
3235  const TargetFrameLowering &TFI = *Subtarget.getFrameLowering();
3236  unsigned StackAlign = TFI.getStackAlignment();
3237  Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value
3238  if (Align > StackAlign)
3239  Result = DAG.getNode(ISD::AND, DL, VT, Result,
3240  DAG.getConstant(-(uint64_t)Align, DL, VT));
3241  Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain
3242  }
3243 
3244  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
3245  DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
3246 
3247  SDValue Ops[2] = {Result, Chain};
3248  return DAG.getMergeValues(Ops, DL);
3249 }
3250 
3251 SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
3252  SelectionDAG &DAG) const {
3253  SDLoc DL(Op);
3254  SDValue Lo = Op.getOperand(0);
3255  SDValue Hi = Op.getOperand(1);
3256  SDValue Shamt = Op.getOperand(2);
3257  EVT VT = Lo.getValueType();
3258 
3259  // if Shamt - register size < 0: // Shamt < register size
3260  // Lo = Lo << Shamt
3261  // Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
3262  // else:
3263  // Lo = 0
3264  // Hi = Lo << (Shamt - register size)
3265 
3266  SDValue Zero = DAG.getConstant(0, DL, VT);
3267  SDValue One = DAG.getConstant(1, DL, VT);
3268  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3269  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3270  SDValue ShamtMinusRegisterSize =
3271  DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3272  SDValue RegisterSizeMinus1Shamt =
3273  DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3274 
3275  SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
3276  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
3277  SDValue ShiftRightLo =
3278  DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
3279  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
3280  SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
3281  SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
3282 
3283  SDValue CC =
3284  DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3285 
3286  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
3287  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3288 
3289  return DAG.getMergeValues({Lo, Hi}, DL);
3290 }
3291 
3292 SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
3293  bool IsSRA) const {
3294  SDLoc DL(Op);
3295  SDValue Lo = Op.getOperand(0);
3296  SDValue Hi = Op.getOperand(1);
3297  SDValue Shamt = Op.getOperand(2);
3298  EVT VT = Lo.getValueType();
3299 
3300  // SRA expansion:
3301  // if Shamt - register size < 0: // Shamt < register size
3302  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3303  // Hi = Hi >>s Shamt
3304  // else:
3305  // Lo = Hi >>s (Shamt - register size);
3306  // Hi = Hi >>s (register size - 1)
3307  //
3308  // SRL expansion:
3309  // if Shamt - register size < 0: // Shamt < register size
3310  // Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
3311  // Hi = Hi >>u Shamt
3312  // else:
3313  // Lo = Hi >>u (Shamt - register size);
3314  // Hi = 0;
3315 
3316  unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
3317 
3318  SDValue Zero = DAG.getConstant(0, DL, VT);
3319  SDValue One = DAG.getConstant(1, DL, VT);
3320  SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
3321  SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
3322  SDValue ShamtMinusRegisterSize =
3323  DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
3324  SDValue RegisterSizeMinus1Shamt =
3325  DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
3326 
3327  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
3328  SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
3329  SDValue ShiftLeftHi =
3330  DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
3331  SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
3332  SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
3333  SDValue LoFalse =
3334  DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
3335  SDValue HiFalse =
3336  IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
3337 
3338  SDValue CC =
3339  DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
3340 
3341  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
3342  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
3343 
3344  return DAG.getMergeValues({Lo, Hi}, DL);
3345 }
3346 
3347 //===----------------------------------------------------------------------===//
3348 // DAG Combine
3349 //===----------------------------------------------------------------------===//
3350 
3352  SelectionDAG &DAG) {
3353  return DAG.getNode(M68kISD::SETCC, dl, MVT::i8,
3354  DAG.getConstant(Cond, dl, MVT::i8), CCR);
3355 }
3356 // When legalizing carry, we create carries via add X, -1
3357 // If that comes from an actual carry, via setcc, we use the
3358 // carry directly.
3360  if (CCR.getOpcode() == M68kISD::ADD) {
3361  if (isAllOnesConstant(CCR.getOperand(1))) {
3362  SDValue Carry = CCR.getOperand(0);
3363  while (Carry.getOpcode() == ISD::TRUNCATE ||
3364  Carry.getOpcode() == ISD::ZERO_EXTEND ||
3365  Carry.getOpcode() == ISD::SIGN_EXTEND ||
3366  Carry.getOpcode() == ISD::ANY_EXTEND ||
3367  (Carry.getOpcode() == ISD::AND &&
3368  isOneConstant(Carry.getOperand(1))))
3369  Carry = Carry.getOperand(0);
3370  if (Carry.getOpcode() == M68kISD::SETCC ||
3371  Carry.getOpcode() == M68kISD::SETCC_CARRY) {
3372  if (Carry.getConstantOperandVal(0) == M68k::COND_CS)
3373  return Carry.getOperand(1);
3374  }
3375  }
3376  }
3377 
3378  return SDValue();
3379 }
3380 
3381 /// Optimize a CCR definition used according to the condition code \p CC into
3382 /// a simpler CCR value, potentially returning a new \p CC and replacing uses
3383 /// of chain values.
3385  SelectionDAG &DAG,
3386  const M68kSubtarget &Subtarget) {
3387  if (CC == M68k::COND_CS)
3388  if (SDValue Flags = combineCarryThroughADD(CCR))
3389  return Flags;
3390 
3391  return SDValue();
3392 }
3393 
3394 // Optimize RES = M68kISD::SETCC CONDCODE, CCR_INPUT
3396  const M68kSubtarget &Subtarget) {
3397  SDLoc DL(N);
3398  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(0));
3399  SDValue CCR = N->getOperand(1);
3400 
3401  // Try to simplify the CCR and condition code operands.
3402  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget))
3403  return getSETCC(CC, Flags, DL, DAG);
3404 
3405  return SDValue();
3406 }
3408  const M68kSubtarget &Subtarget) {
3409  SDLoc DL(N);
3410  M68k::CondCode CC = M68k::CondCode(N->getConstantOperandVal(2));
3411  SDValue CCR = N->getOperand(3);
3412 
3413  // Try to simplify the CCR and condition code operands.
3414  // Make sure to not keep references to operands, as combineSetCCCCR can
3415  // RAUW them under us.
3416  if (SDValue Flags = combineSetCCCCR(CCR, CC, DAG, Subtarget)) {
3417  SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
3418  return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0),
3419  N->getOperand(1), Cond, Flags);
3420  }
3421 
3422  return SDValue();
3423 }
3424 
3426  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3427  MVT VT = N->getSimpleValueType(0);
3428  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3429  return DAG.getNode(M68kISD::SUBX, SDLoc(N), VTs, N->getOperand(0),
3430  N->getOperand(1), Flags);
3431  }
3432 
3433  return SDValue();
3434 }
3435 
3436 // Optimize RES, CCR = M68kISD::ADDX LHS, RHS, CCR
3439  if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
3440  MVT VT = N->getSimpleValueType(0);
3441  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
3442  return DAG.getNode(M68kISD::ADDX, SDLoc(N), VTs, N->getOperand(0),
3443  N->getOperand(1), Flags);
3444  }
3445 
3446  return SDValue();
3447 }
3448 
3449 SDValue M68kTargetLowering::PerformDAGCombine(SDNode *N,
3450  DAGCombinerInfo &DCI) const {
3451  SelectionDAG &DAG = DCI.DAG;
3452  switch (N->getOpcode()) {
3453  case M68kISD::SUBX:
3454  return combineSUBX(N, DAG);
3455  case M68kISD::ADDX:
3456  return combineADDX(N, DAG, DCI);
3457  case M68kISD::SETCC:
3458  return combineM68kSetCC(N, DAG, Subtarget);
3459  case M68kISD::BRCOND:
3460  return combineM68kBrCond(N, DAG, Subtarget);
3461  }
3462 
3463  return SDValue();
3464 }
3465 
3466 //===----------------------------------------------------------------------===//
3467 // M68kISD Node Names
3468 //===----------------------------------------------------------------------===//
3469 const char *M68kTargetLowering::getTargetNodeName(unsigned Opcode) const {
3470  switch (Opcode) {
3471  case M68kISD::CALL:
3472  return "M68kISD::CALL";
3473  case M68kISD::TAIL_CALL:
3474  return "M68kISD::TAIL_CALL";
3475  case M68kISD::RET:
3476  return "M68kISD::RET";
3477  case M68kISD::TC_RETURN:
3478  return "M68kISD::TC_RETURN";
3479  case M68kISD::ADD:
3480  return "M68kISD::ADD";
3481  case M68kISD::SUB:
3482  return "M68kISD::SUB";
3483  case M68kISD::ADDX:
3484  return "M68kISD::ADDX";
3485  case M68kISD::SUBX:
3486  return "M68kISD::SUBX";
3487  case M68kISD::SMUL:
3488  return "M68kISD::SMUL";
3489  case M68kISD::UMUL:
3490  return "M68kISD::UMUL";
3491  case M68kISD::OR:
3492  return "M68kISD::OR";
3493  case M68kISD::XOR:
3494  return "M68kISD::XOR";
3495  case M68kISD::AND:
3496  return "M68kISD::AND";
3497  case M68kISD::CMP:
3498  return "M68kISD::CMP";
3499  case M68kISD::BTST:
3500  return "M68kISD::BTST";
3501  case M68kISD::SELECT:
3502  return "M68kISD::SELECT";
3503  case M68kISD::CMOV:
3504  return "M68kISD::CMOV";
3505  case M68kISD::BRCOND:
3506  return "M68kISD::BRCOND";
3507  case M68kISD::SETCC:
3508  return "M68kISD::SETCC";
3509  case M68kISD::SETCC_CARRY:
3510  return "M68kISD::SETCC_CARRY";
3512  return "M68kISD::GLOBAL_BASE_REG";
3513  case M68kISD::Wrapper:
3514  return "M68kISD::Wrapper";
3515  case M68kISD::WrapperPC:
3516  return "M68kISD::WrapperPC";
3517  case M68kISD::SEG_ALLOCA:
3518  return "M68kISD::SEG_ALLOCA";
3519  default:
3520  return NULL;
3521  }
3522 }
3523 
3525  bool IsVarArg) const {
3526  if (Return)
3527  return RetCC_M68k_C;
3528  else
3529  return CC_M68k_C;
3530 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::ArgFlagsTy::isInAlloca
bool isInAlloca() const
Definition: TargetCallingConv.h:91
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1417
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
llvm::MachineFrameInfo::isObjectZExt
bool isObjectZExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:526
ValueTypes.h
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::ISD::SETCCCARRY
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:744
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
llvm::M68kTargetLowering::getCCAssignFn
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: M68kISelLowering.cpp:3524
llvm::M68kTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: M68kISelLowering.cpp:2855
llvm::M68kISD::Wrapper
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
Definition: M68kISelLowering.h:87
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
Definition: TargetLowering.h:1784
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:940
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1428
TranslateIntegerM68kCC
static M68k::CondCode TranslateIntegerM68kCC(ISD::CondCode SetCCOpcode)
Definition: M68kISelLowering.cpp:1493
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::M68kTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: M68kISelLowering.cpp:2681
llvm::ISD::UMULO
@ UMULO
Definition: ISDOpcodes.h:332
llvm::M68kISD::SUBX
@ SUBX
Definition: M68kISelLowering.h:75
LowerAndToBTST
static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Result of 'and' is compared against zero. Change to a BTST node if possible.
Definition: M68kISelLowering.cpp:1445
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::M68kISD::BRCOND
@ BRCOND
M68k conditional branches.
Definition: M68kISelLowering.h:69
llvm::M68kTargetMachine
Definition: M68kTargetMachine.h:29
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::M68kMachineFunctionInfo::setArgumentStackSize
void setArgumentStackSize(unsigned size)
Definition: M68kMachineFunction.h:102
llvm::ISD::ArgFlagsTy::isSRet
bool isSRet() const
Definition: TargetCallingConv.h:82
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:221
llvm::TargetLowering::CallLoweringInfo::RetTy
Type * RetTy
Definition: TargetLowering.h:3954
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:764
M68kTargetMachine.h
llvm::M68kISD::SETCC
@ SETCC
M68k SetCC.
Definition: M68kISelLowering.h:53
llvm::M68k::CondCode
CondCode
Definition: M68kInstrInfo.h:34
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:205
llvm::ISD::SETGT
@ SETGT
Definition: ISDOpcodes.h:1425
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1429
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4362
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:984
llvm::M68kTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: M68kISelLowering.cpp:3166
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:747
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::isOneConstant
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
Definition: SelectionDAG.cpp:10452
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::M68kISD::SELECT
@ SELECT
M68k Select.
Definition: M68kISelLowering.h:49
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:969
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1798
llvm::ISD::ADDC
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
llvm::M68k::COND_PL
@ COND_PL
Definition: M68kInstrInfo.h:45
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1679
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1424
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1050
llvm::M68kISD::ADD
@ ADD
Definition: M68kISelLowering.h:72
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9037
TranslateM68kCC
static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, bool IsFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Do a one-to-one translation of a ISD::CondCode to the M68k-specific condition code,...
Definition: M68kISelLowering.cpp:1523
llvm::M68k::COND_GT
@ COND_GT
Definition: M68kInstrInfo.h:49
llvm::ISD::GlobalISel::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
Definition: SelectionDAG.cpp:518
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
ErrorHandling.h
llvm::M68kCCState
Custom state to propagate llvm type info to register CC assigner.
Definition: M68kCallingConv.h:27
llvm::isBitwiseNot
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
Definition: SelectionDAG.cpp:10480
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::M68k::COND_NE
@ COND_NE
Definition: M68kInstrInfo.h:41
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::SelectionDAG::ReplaceAllUsesWith
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
Definition: SelectionDAG.cpp:9909
llvm::M68kII::isPCRelBlockReference
static bool isPCRelBlockReference(unsigned char Flag)
Return True if the Block is referenced using PC.
Definition: M68kBaseInfo.h:167
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::CCValAssign::Indirect
@ Indirect
Definition: CallingConvLower.h:50
llvm::M68kRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: M68kRegisterInfo.h:108
llvm::SDNode::use_iterator
This class provides iterator support for SDUse operands that use a specific SDNode.
Definition: SelectionDAGNodes.h:733
llvm::M68kRegisterInfo
Definition: M68kRegisterInfo.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:232
LowerTruncateToBTST
static SDValue LowerTruncateToBTST(SDValue Op, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:1604
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::ISD::ArgFlagsTy::isZExt
bool isZExt() const
Definition: TargetCallingConv.h:73
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1419
MachineJumpTableInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7752
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
isXor1OfSetCC
static bool isXor1OfSetCC(SDValue Op)
Return true if node is an ISD::XOR of a M68kISD::SETCC and 1 and that the SETCC node has a single use...
Definition: M68kISelLowering.cpp:2244
llvm::CallBase::isMustTailCall
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Definition: Instructions.cpp:298
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:3979
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2400
llvm::M68kII::isDirectGlobalReference
static bool isDirectGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue is a direct reference for a symbol.
Definition: M68kBaseInfo.h:131
hasNonFlagsUse
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
Definition: M68kISelLowering.cpp:1619
llvm::M68k::COND_VS
@ COND_VS
Definition: M68kInstrInfo.h:44
llvm::ISD::MERGE_VALUES
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1079
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::MachineFunction::getJTISymbol
MCSymbol * getJTISymbol(unsigned JTI, MCContext &Ctx, bool isLinkerPrivate=false) const
getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
Definition: MachineFunction.cpp:704
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::M68kSubtarget::getRegisterInfo
const M68kRegisterInfo * getRegisterInfo() const override
Definition: M68kSubtarget.h:155
llvm::MCSymbolRefExpr::VK_GOTOFF
@ VK_GOTOFF
Definition: MCExpr.h:199
llvm::ISD::SETOEQ
@ SETOEQ
Definition: ISDOpcodes.h:1407
llvm::EVT::bitsLE
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
Definition: ValueTypes.h:280
llvm::M68kMachineFunctionInfo::getForwardedMustTailRegParms
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
Definition: M68kMachineFunction.h:104
llvm::M68kISD::CALL
@ CALL
Definition: M68kISelLowering.h:35
SelectionDAG.h
llvm::MachineJumpTableInfo::EK_Custom32
@ EK_Custom32
EK_Custom32 - Each entry is a 32-bit value that is custom lowered by the TargetLowering::LowerCustomJ...
Definition: MachineJumpTableInfo.h:76
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1415
combineCarryThroughADD
static SDValue combineCarryThroughADD(SDValue CCR)
Definition: M68kISelLowering.cpp:3359
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:459
llvm::M68k::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
Definition: M68kISelLowering.cpp:2893
llvm::M68kTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: M68kISelLowering.cpp:2677
F
#define F(x, y, z)
Definition: MD5.cpp:55
M68kTargetObjectFile.h
llvm::ISD::BRCOND
@ BRCOND
BRCOND - Conditional branch.
Definition: ISDOpcodes.h:994
MachineRegisterInfo.h
KnownBits.h
llvm::M68kTargetLowering::getPICJumpTableRelocBaseExpr
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
Definition: M68kISelLowering.cpp:2699
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::M68kII::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Return true if the specified TargetFlag operand is a reference to a stub for a global,...
Definition: M68kBaseInfo.h:119
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1422
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:747
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:57
shouldGuaranteeTCO
static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Return true if the function is being made into a tailcall target by changing its ABI.
Definition: M68kISelLowering.cpp:240
CommandLine.h
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7702
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:95
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3957
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::M68kSubtarget::classifyBlockAddressReference
unsigned char classifyBlockAddressReference() const
Classify a blockaddress reference for the current subtarget according to how we should reference it i...
Definition: M68kSubtarget.cpp:147
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:154
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ms_demangle::CallingConv
CallingConv
Definition: MicrosoftDemangleNodes.h:58
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition: M68kSubtarget.h:149
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::SelectionDAG::UpdateNodeOperands
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
Definition: SelectionDAG.cpp:9127
llvm::SDNode::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: SelectionDAGNodes.h:706
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2256
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:742
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1426
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::User
Definition: User.h:44
llvm::M68kISD::AND
@ AND
Definition: M68kISelLowering.h:80
llvm::M68kTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: M68kISelLowering.cpp:2688
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:455
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
NotStructReturn
@ NotStructReturn
Definition: M68kISelLowering.cpp:181
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::M68k::COND_GE
@ COND_GE
Definition: M68kInstrInfo.h:47
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3362
isAndOrOfSetCCs
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Return true if node is an ISD::AND or ISD::OR of two M68k::SETcc nodes each of which has no other use...
Definition: M68kISelLowering.cpp:2232
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
Definition: SelectionDAG.cpp:2528
StackStructReturn
@ StackStructReturn
Definition: M68kISelLowering.cpp:181
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3749
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:214
llvm::M68kMachineFunctionInfo::setSRetReturnReg
void setSRetReturnReg(unsigned Reg)
Definition: M68kMachineFunction.h:99
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1015
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2239
argsAreStructReturn
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Determines whether a function uses struct return semantics.
Definition: M68kISelLowering.cpp:198
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:651
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::TargetLowering::CallLoweringInfo::DoesNotReturn
bool DoesNotReturn
Definition: TargetLowering.h:3959
combineM68kSetCC
static SDValue combineM68kSetCC(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3395
llvm::M68kMachineFunctionInfo::setTCReturnAddrDelta
void setTCReturnAddrDelta(int delta)
Definition: M68kMachineFunction.h:87
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:279
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:307
llvm::FrameIndexSDNode
Definition: SelectionDAGNodes.h:1760
llvm::TargetLowering::C_Immediate
@ C_Immediate
Definition: TargetLowering.h:4367
M68kISelLowering.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::ISD::SMULO
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
llvm::ISD::SETOLT
@ SETOLT
Definition: ISDOpcodes.h:1410
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:1264
llvm::MachineInstr::definesRegister
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
Definition: MachineInstr.h:1377
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:1137
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::SDValue::getValueSizeInBits
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
Definition: SelectionDAGNodes.h:191
llvm::ISD::CopyFromReg
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:208
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1368
RegStructReturn
@ RegStructReturn
Definition: M68kISelLowering.cpp:181
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::ISD::USUBO
@ USUBO
Definition: ISDOpcodes.h:328
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::ISD::SETOLE
@ SETOLE
Definition: ISDOpcodes.h:1411
llvm::M68kMachineFunctionInfo::getSRetReturnReg
unsigned getSRetReturnReg() const
Definition: M68kMachineFunction.h:98
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1416
llvm::MVT::getScalarType
MVT getScalarType() const
If this is a vector, return the element type, otherwise return this.
Definition: MachineValueType.h:515
llvm::M68kISD::TC_RETURN
@ TC_RETURN
Definition: M68kISelLowering.h:38
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:695
llvm::M68kTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: M68kISelLowering.cpp:2739
checkAndUpdateCCRKill
static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
Definition: M68kISelLowering.cpp:2918
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: MachineValueType.h:340
llvm::M68kTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
Definition: M68kISelLowering.cpp:1321
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::M68kISD::XOR
@ XOR
Definition: M68kISelLowering.h:79
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:492
llvm::M68kISD::CMOV
@ CMOV
M68k conditional moves.
Definition: M68kISelLowering.h:63
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:3980
llvm::M68kISD::SUB
@ SUB
Definition: M68kISelLowering.h:73
llvm::ISD::SETUNE
@ SETUNE
Definition: ISDOpcodes.h:1420
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::CallingConv::M68k_INTR
@ M68k_INTR
M68k_INTR - Calling convention used for M68k interrupt routines.
Definition: CallingConv.h:253
llvm::ISD::SADDO
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
llvm::TargetLowering::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: TargetLowering.h:4106
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::M68k::COND_HI
@ COND_HI
Definition: M68kInstrInfo.h:37
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:394
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:35
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::M68kISD::SMUL
@ SMUL
Definition: M68kISelLowering.h:76
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:932
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::TargetLowering::CallLoweringInfo::Chain
SDValue Chain
Definition: TargetLowering.h:3953
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1572
llvm::M68kMachineFunctionInfo::getRAIndex
int getRAIndex() const
Definition: M68kMachineFunction.h:83
llvm::M68kISD::TAIL_CALL
@ TAIL_CALL
Definition: M68kISelLowering.h:37
llvm::ISD::AssertZext
@ AssertZext
Definition: ISDOpcodes.h:62
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::ForwardedRegister
Describes a register that needs to be forwarded from the prologue to a musttail call.
Definition: CallingConvLower.h:165
getBitTestCondition
static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC, const SDLoc &DL, SelectionDAG &DAG)
Create a BTST (Bit Test) node - Test bit BitNo in Src and set condition according to equal/not-equal ...
Definition: M68kISelLowering.cpp:1423
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::M68kII::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Return true if the specified global value reference is relative to a 32-bit PIC base (M68kISD::GLOBAL...
Definition: M68kBaseInfo.h:145
llvm::DenseMap
Definition: DenseMap.h:716
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:773
llvm::TargetLowering::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: TargetLowering.h:3974
llvm::codeview::FrameCookieKind::Copy
@ Copy
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2205
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:908
llvm::M68k::GetCondBranchFromCond
static unsigned GetCondBranchFromCond(M68k::CondCode CC)
Definition: M68kInstrInfo.h:97
llvm::FrameIndexSDNode::getIndex
int getIndex() const
Definition: SelectionDAGNodes.h:1771
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8786
combineM68kBrCond
static SDValue combineM68kBrCond(SDNode *N, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Definition: M68kISelLowering.cpp:3407
MatchingStackOffset
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo &MFI, const MachineRegisterInfo *MRI, const M68kInstrInfo *TII, const CCValAssign &VA)
Return true if the given stack call argument is already available in the same position (relatively) o...
Definition: M68kISelLowering.cpp:246
llvm::SelectionDAG::getNOT
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
Definition: SelectionDAG.cpp:1419
llvm::TargetLowering::CallLoweringInfo::DL
SDLoc DL
Definition: TargetLowering.h:3978
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: M68kISelLowering.cpp:228
llvm::M68kISD::BTST
@ BTST
M68k bit-test instructions.
Definition: M68kISelLowering.h:46
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
Definition: Function.h:644
llvm::Log2_64_Ceil
unsigned Log2_64_Ceil(uint64_t Value)
Return the ceil log base 2 of the specified value, 64 if the value is zero.
Definition: MathExtras.h:642
llvm::M68k::COND_INVALID
@ COND_INVALID
Definition: M68kInstrInfo.h:52
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
llvm::M68kII::isPCRelGlobalReference
static bool isPCRelGlobalReference(unsigned char Flag)
Return True if the specified GlobalValue requires PC addressing mode.
Definition: M68kBaseInfo.h:156
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:631
llvm::M68kSubtarget::getFrameLowering
const M68kFrameLowering * getFrameLowering() const override
Definition: M68kSubtarget.h:151
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::ISD::SETOGT
@ SETOGT
Definition: ISDOpcodes.h:1408
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3952
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
llvm::M68k::COND_LT
@ COND_LT
Definition: M68kInstrInfo.h:48
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1418
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
M68kCallingConv.h
llvm::M68k::COND_CC
@ COND_CC
Definition: M68kInstrInfo.h:39
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1404
llvm::Value::use_begin
use_iterator use_begin()
Definition: Value.h:360
llvm::SelectionDAG::getBitcast
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
Definition: SelectionDAG.cpp:2164
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::ISD::isNON_EXTLoad
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
Definition: SelectionDAGNodes.h:3022
llvm::M68kISD::SETCC_CARRY
@ SETCC_CARRY
Definition: M68kISelLowering.h:57
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::M68k::COND_VC
@ COND_VC
Definition: M68kInstrInfo.h:43
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
OP
#define OP(n)
Definition: regex2.h:73
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
Definition: SelectionDAG.cpp:2282
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1080
llvm::MachineInstr::readsRegister
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1347
combineSUBX
static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG)
Definition: M68kISelLowering.cpp:3425
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: M68kISelLowering.cpp:225
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:952
llvm::CCState::resultsCompatible
static bool resultsCompatible(CallingConv::ID CalleeCC, CallingConv::ID CallerCC, MachineFunction &MF, LLVMContext &C, const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn CalleeFn, CCAssignFn CallerFn)
Returns true if the results of the two calling conventions are compatible.
Definition: CallingConvLower.cpp:258
isM68kLogicalCmp
static bool isM68kLogicalCmp(SDValue Op)
Return true if opcode is a M68k logical comparison.
Definition: M68kISelLowering.cpp:2003
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:3982
llvm::ISD::ConstantPool
@ ConstantPool
Definition: ISDOpcodes.h:82
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:140
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::TargetLowering::CallLoweringInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3977
llvm::M68kMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int Index)
Definition: M68kMachineFunction.h:93
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:711
callIsStructReturn
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
Definition: M68kISelLowering.cpp:184
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:99
llvm::M68kISD::ADDX
@ ADDX
Definition: M68kISelLowering.h:74
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::M68kISD::RET
@ RET
Definition: M68kISelLowering.h:36
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::ConstantPoolSDNode
Definition: SelectionDAGNodes.h:1858
llvm::M68kTargetLowering::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: M68kISelLowering.cpp:171
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Definition: TargetLowering.cpp:4972
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:352
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::M68kMachineFunctionInfo
Definition: M68kMachineFunction.h:23
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::ms_demangle::IntrinsicFunctionKind::New
@ New
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:1133
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SDValue::hasOneUse
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
Definition: SelectionDAGNodes.h:1169
llvm::M68kSubtarget::getSlotSize
unsigned getSlotSize() const
getSlotSize - Stack slot size in bytes.
Definition: M68kSubtarget.h:139
llvm::HexagonInstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
Definition: HexagonInstrInfo.cpp:286
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5049
llvm::M68kSubtarget::classifyGlobalFunctionReference
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const Module &M) const
Classify a global function reference for the current subtarget.
Definition: M68kSubtarget.cpp:243
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2293
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:182
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::MachineFrameInfo::isObjectSExt
bool isObjectSExt(int ObjectIdx) const
Definition: MachineFrameInfo.h:538
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::M68kISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: M68kISelLowering.h:83
llvm::M68kISD::WrapperPC
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
Definition: M68kISelLowering.h:91
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4364
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:376
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:705
llvm::M68kInstrInfo
Definition: M68kInstrInfo.h:237
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::HexagonISD::CP
@ CP
Definition: HexagonISelLowering.h:53
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:345
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
llvm::TargetLowering::CallLoweringInfo::IsTailCall
bool IsTailCall
Definition: TargetLowering.h:3968
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1427
llvm::M68k::COND_LS
@ COND_LS
Definition: M68kInstrInfo.h:38
llvm::isAllOnesConstant
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
Definition: SelectionDAG.cpp:10447
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::M68kSubtarget::classifyLocalReference
unsigned char classifyLocalReference(const GlobalValue *GV) const
Classify a global variable reference for the current subtarget according to how we should reference i...
Definition: M68kSubtarget.cpp:153
llvm::M68kMachineFunctionInfo::setBytesToPopOnReturn
void setBytesToPopOnReturn(unsigned bytes)
Definition: M68kMachineFunction.h:81
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::SelectionDAG::computeKnownBits
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
Definition: SelectionDAG.cpp:2897
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
CallingConvLower.h
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
llvm::M68kTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: M68kISelLowering.cpp:3469
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::isNullConstant
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
Definition: SelectionDAG.cpp:10437
llvm::M68k::IsSETCC
static bool IsSETCC(unsigned SETCC)
Definition: M68kInstrInfo.h:185
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:326
llvm::ISD::BR
@ BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:975
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::M68kMachineFunctionInfo::setRAIndex
void setRAIndex(int Index)
Definition: M68kMachineFunction.h:84
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:528
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
Definition: SelectionDAG.cpp:491
GlobalVariable.h
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:452
llvm::MachineFrameInfo::setObjectSExt
void setObjectSExt(int ObjectIdx, bool IsSExt)
Definition: MachineFrameInfo.h:544
llvm::ISD::ArgFlagsTy::isSExt
bool isSExt() const
Definition: TargetCallingConv.h:76
M68kMachineFunction.h
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::ISD::SUBC
@ SUBC
Definition: ISDOpcodes.h:270
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1829
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
llvm::TargetLoweringBase::ZeroOrOneBooleanContent
@ ZeroOrOneBooleanContent
Definition: TargetLowering.h:232
llvm::M68k::COND_MI
@ COND_MI
Definition: M68kInstrInfo.h:46
llvm::ISD::STORE
@ STORE
Definition: ISDOpcodes.h:960
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1075
llvm::M68kISD::CMP
@ CMP
M68k compare and logical compare instructions.
Definition: M68kISelLowering.h:43
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
combineADDX
static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: M68kISelLowering.cpp:3437
llvm::ISD::SSUBO
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
llvm::M68kTargetLowering::M68kTargetLowering
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
Definition: M68kISelLowering.cpp:46
llvm::M68kMachineFunctionInfo::getBytesToPopOnReturn
unsigned getBytesToPopOnReturn() const
Definition: M68kMachineFunction.h:80
llvm::M68kRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: M68kRegisterInfo.cpp:65
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
isCMOVPseudo
static bool isCMOVPseudo(MachineInstr &MI)
Definition: M68kISelLowering.cpp:2901
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2173
llvm::ISD::SETOGE
@ SETOGE
Definition: ISDOpcodes.h:1409
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
isM68kCCUnsigned
static bool isM68kCCUnsigned(unsigned M68kCC)
Return true if the condition is an unsigned comparison operation.
Definition: M68kISelLowering.cpp:1853
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::TargetLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: TargetLowering.cpp:80
MachineInstrBuilder.h
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::M68kISD::OR
@ OR
Definition: M68kISelLowering.h:78
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::M68kSubtarget::getJumpTableEncoding
unsigned getJumpTableEncoding() const
Definition: M68kSubtarget.cpp:221
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1248
combineSetCCCCR
static SDValue combineSetCCCCR(SDValue CCR, M68k::CondCode &CC, SelectionDAG &DAG, const M68kSubtarget &Subtarget)
Optimize a CCR definition used according to the condition code CC into a simpler CCR value,...
Definition: M68kISelLowering.cpp:3384
llvm::M68k::COND_EQ
@ COND_EQ
Definition: M68kInstrInfo.h:42
llvm::ISD::SUBE
@ SUBE
Definition: ISDOpcodes.h:280
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::M68kTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
Definition: M68kISelLowering.cpp:165
M68kSubtarget.h
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2076
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:889
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:258
llvm::M68kTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
Definition: M68kISelLowering.cpp:2705