LLVM 17.0.0git
NVPTXTargetMachine.cpp
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1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/Triple.h"
26#include "llvm/CodeGen/Passes.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
31#include "llvm/Pass.h"
39#include <cassert>
40#include <optional>
41#include <string>
42
43using namespace llvm;
44
45// LSV is still relatively new; this switch lets us turn it off in case we
46// encounter (or suspect) a bug.
47static cl::opt<bool>
48 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
49 cl::desc("Disable load/store vectorizer"),
50 cl::init(false), cl::Hidden);
51
52// TODO: Remove this flag when we are confident with no regressions.
54 "disable-nvptx-require-structured-cfg",
55 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
56 "structured CFG. The requirement should be disabled only when "
57 "unexpected regressions happen."),
58 cl::init(false), cl::Hidden);
59
61 "nvptx-short-ptr",
63 "Use 32-bit pointers for accessing const/local/shared address spaces."),
64 cl::init(false), cl::Hidden);
65
66namespace llvm {
67
80
81} // end namespace llvm
82
84 // Register the target.
87
89 // FIXME: This pass is really intended to be invoked during IR optimization,
90 // but it's very NVPTX-specific.
104}
105
106static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
107 std::string Ret = "e";
108
109 if (!is64Bit)
110 Ret += "-p:32:32";
111 else if (UseShortPointers)
112 Ret += "-p3:32:32-p4:32:32-p5:32:32";
113
114 Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
115
116 return Ret;
117}
118
120 StringRef CPU, StringRef FS,
121 const TargetOptions &Options,
122 std::optional<Reloc::Model> RM,
123 std::optional<CodeModel::Model> CM,
124 CodeGenOpt::Level OL, bool is64bit)
125 // The pic relocation model is used regardless of what the client has
126 // specified, as it is the only relocation model currently supported.
128 CPU, FS, Options, Reloc::PIC_,
129 getEffectiveCodeModel(CM, CodeModel::Small), OL),
130 is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
131 TLOF(std::make_unique<NVPTXTargetObjectFile>()),
132 Subtarget(TT, std::string(CPU), std::string(FS), *this),
133 StrPool(StrAlloc) {
134 if (TT.getOS() == Triple::NVCL)
135 drvInterface = NVPTX::NVCL;
136 else
137 drvInterface = NVPTX::CUDA;
140 initAsmInfo();
141}
142
144
145void NVPTXTargetMachine32::anchor() {}
146
148 StringRef CPU, StringRef FS,
149 const TargetOptions &Options,
150 std::optional<Reloc::Model> RM,
151 std::optional<CodeModel::Model> CM,
152 CodeGenOpt::Level OL, bool JIT)
153 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
154
155void NVPTXTargetMachine64::anchor() {}
156
158 StringRef CPU, StringRef FS,
159 const TargetOptions &Options,
160 std::optional<Reloc::Model> RM,
161 std::optional<CodeModel::Model> CM,
162 CodeGenOpt::Level OL, bool JIT)
163 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
164
165namespace {
166
167class NVPTXPassConfig : public TargetPassConfig {
168public:
169 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
170 : TargetPassConfig(TM, PM) {}
171
172 NVPTXTargetMachine &getNVPTXTargetMachine() const {
173 return getTM<NVPTXTargetMachine>();
174 }
175
176 void addIRPasses() override;
177 bool addInstSelector() override;
178 void addPreRegAlloc() override;
179 void addPostRegAlloc() override;
180 void addMachineSSAOptimization() override;
181
182 FunctionPass *createTargetRegisterAllocator(bool) override;
183 void addFastRegAlloc() override;
184 void addOptimizedRegAlloc() override;
185
186 bool addRegAssignAndRewriteFast() override {
187 llvm_unreachable("should not be used");
188 }
189
190 bool addRegAssignAndRewriteOptimized() override {
191 llvm_unreachable("should not be used");
192 }
193
194private:
195 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
196 // function is only called in opt mode.
197 void addEarlyCSEOrGVNPass();
198
199 // Add passes that propagate special memory spaces.
200 void addAddressSpaceInferencePasses();
201
202 // Add passes that perform straight-line scalar optimizations.
203 void addStraightLineScalarOptimizationPasses();
204};
205
206} // end anonymous namespace
207
209 return new NVPTXPassConfig(*this, PM);
210}
211
213 BumpPtrAllocator &Allocator, const Function &F,
214 const TargetSubtargetInfo *STI) const {
215 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
216 F, STI);
217}
218
221}
222
227 if (PassName == "nvvm-reflect") {
229 return true;
230 }
231 if (PassName == "nvvm-intr-range") {
233 return true;
234 }
235 return false;
236 });
237
239 FAM.registerPass([&] { return NVPTXAA(); });
240 });
241
243 if (AAName == "nvptx-aa") {
245 return true;
246 }
247 return false;
248 });
249
251 [this](ModulePassManager &PM, OptimizationLevel Level) {
253 FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
254 // FIXME: NVVMIntrRangePass is causing numerical discrepancies,
255 // investigate and re-enable.
256 // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
257 PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
258 });
259}
260
263 return TargetTransformInfo(NVPTXTTIImpl(this, F));
264}
265
266std::pair<const Value *, unsigned>
268 if (auto *II = dyn_cast<IntrinsicInst>(V)) {
269 switch (II->getIntrinsicID()) {
270 case Intrinsic::nvvm_isspacep_const:
271 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_CONST);
272 case Intrinsic::nvvm_isspacep_global:
273 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_GLOBAL);
274 case Intrinsic::nvvm_isspacep_local:
275 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_LOCAL);
276 case Intrinsic::nvvm_isspacep_shared:
277 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_SHARED);
278 default:
279 break;
280 }
281 }
282 return std::make_pair(nullptr, -1);
283}
284
285void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
286 if (getOptLevel() == CodeGenOpt::Aggressive)
287 addPass(createGVNPass());
288 else
289 addPass(createEarlyCSEPass());
290}
291
292void NVPTXPassConfig::addAddressSpaceInferencePasses() {
293 // NVPTXLowerArgs emits alloca for byval parameters which can often
294 // be eliminated by SROA.
295 addPass(createSROAPass());
299}
300
301void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
304 // ReassociateGEPs exposes more opportunites for SLSR. See
305 // the example in reassociate-geps-and-slsr.ll.
307 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
308 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
309 // for some of our benchmarks.
310 addEarlyCSEOrGVNPass();
311 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
312 addPass(createNaryReassociatePass());
313 // NaryReassociate on GEPs creates redundant common expressions, so run
314 // EarlyCSE after it.
315 addPass(createEarlyCSEPass());
316}
317
318void NVPTXPassConfig::addIRPasses() {
319 // The following passes are known to not play well with virtual regs hanging
320 // around after register allocation (which in our case, is *all* registers).
321 // We explicitly disable them here. We do, however, need some functionality
322 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
323 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
324 disablePass(&PrologEpilogCodeInserterID);
325 disablePass(&MachineLateInstrsCleanupID);
326 disablePass(&MachineCopyPropagationID);
327 disablePass(&TailDuplicateID);
328 disablePass(&StackMapLivenessID);
329 disablePass(&LiveDebugValuesID);
330 disablePass(&PostRAMachineSinkingID);
331 disablePass(&PostRASchedulerID);
332 disablePass(&FuncletLayoutID);
333 disablePass(&PatchableFunctionID);
334 disablePass(&ShrinkWrapID);
335
336 addPass(createNVPTXAAWrapperPass());
337 addPass(createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
338 if (auto *WrapperPass = P.getAnalysisIfAvailable<NVPTXAAWrapperPass>())
339 AAR.addAAResult(WrapperPass->getResult());
340 }));
341
342 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
343 // it here does nothing. But since we need it for correctness when lowering
344 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
345 // call addEarlyAsPossiblePasses.
346 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
347 addPass(createNVVMReflectPass(ST.getSmVersion()));
348
349 if (getOptLevel() != CodeGenOpt::None)
352 addPass(createGenericToNVVMPass());
353
354 // NVPTXLowerArgs is required for correctness and should be run right
355 // before the address space inference passes.
356 addPass(createNVPTXLowerArgsPass());
357 if (getOptLevel() != CodeGenOpt::None) {
358 addAddressSpaceInferencePasses();
359 addStraightLineScalarOptimizationPasses();
360 }
361
362 addPass(createAtomicExpandPass());
363
364 // === LSR and other generic IR passes ===
366 // EarlyCSE is not always strong enough to clean up what LSR produces. For
367 // example, GVN can combine
368 //
369 // %0 = add %a, %b
370 // %1 = add %b, %a
371 //
372 // and
373 //
374 // %0 = shl nsw %a, 2
375 // %1 = shl %a, 2
376 //
377 // but EarlyCSE can do neither of them.
378 if (getOptLevel() != CodeGenOpt::None) {
379 addEarlyCSEOrGVNPass();
382 addPass(createSROAPass());
383 }
384}
385
386bool NVPTXPassConfig::addInstSelector() {
387 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
388
389 addPass(createLowerAggrCopies());
390 addPass(createAllocaHoisting());
391 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
392
393 if (!ST.hasImageHandles())
395
396 return false;
397}
398
399void NVPTXPassConfig::addPreRegAlloc() {
400 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
402}
403
404void NVPTXPassConfig::addPostRegAlloc() {
406 if (getOptLevel() != CodeGenOpt::None) {
407 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
408 // index with VRFrame register. NVPTXPeephole need to be run after that and
409 // will replace VRFrame with VRFrameLocal when possible.
410 addPass(createNVPTXPeephole());
411 }
412}
413
414FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
415 return nullptr; // No reg alloc
416}
417
418void NVPTXPassConfig::addFastRegAlloc() {
419 addPass(&PHIEliminationID);
421}
422
423void NVPTXPassConfig::addOptimizedRegAlloc() {
424 addPass(&ProcessImplicitDefsID);
425 addPass(&LiveVariablesID);
426 addPass(&MachineLoopInfoID);
427 addPass(&PHIEliminationID);
428
430 addPass(&RegisterCoalescerID);
431
432 // PreRA instruction scheduling.
433 if (addPass(&MachineSchedulerID))
434 printAndVerify("After Machine Scheduling");
435
436
437 addPass(&StackSlotColoringID);
438
439 // FIXME: Needs physical registers
440 //addPass(&MachineLICMID);
441
442 printAndVerify("After StackSlotColoring");
443}
444
445void NVPTXPassConfig::addMachineSSAOptimization() {
446 // Pre-ra tail duplication.
447 if (addPass(&EarlyTailDuplicateID))
448 printAndVerify("After Pre-RegAlloc TailDuplicate");
449
450 // Optimize PHIs before DCE: removing dead PHI cycles may make more
451 // instructions dead.
452 addPass(&OptimizePHIsID);
453
454 // This pass merges large allocas. StackSlotColoring is a different pass
455 // which merges spill slots.
456 addPass(&StackColoringID);
457
458 // If the target requests it, assign local variables to stack slots relative
459 // to one another and simplify frame index references where possible.
461
462 // With optimization, dead code should already be eliminated. However
463 // there is one known exception: lowered code for arguments that are only
464 // used by tail calls, where the tail calls reuse the incoming stack
465 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
467 printAndVerify("After codegen DCE pass");
468
469 // Allow targets to insert passes that improve instruction level parallelism,
470 // like if-conversion. Such passes will typically need dominator trees and
471 // loop info, just like LICM and CSE below.
472 if (addILPOpts())
473 printAndVerify("After ILP optimizations");
474
475 addPass(&EarlyMachineLICMID);
476 addPass(&MachineCSEID);
477
478 addPass(&MachineSinkingID);
479 printAndVerify("After Machine LICM, CSE and Sinking passes");
480
481 addPass(&PeepholeOptimizerID);
482 printAndVerify("After codegen peephole optimization pass");
483}
This header is deprecated in favour of llvm/TargetParser/Triple.h.
basic Basic Alias true
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file provides the interface for LLVM's Global Value Numbering pass which eliminates fully redund...
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
This is the NVPTX address space based alias analysis pass.
static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)
static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()
This file a TargetTransformInfo::Concept conforming object specific to the NVPTX target machine.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define P(N)
FunctionAnalysisManager FAM
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
Basic Register Allocator
This file contains some templates that are useful if you are working with the STL at all.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static bool is64Bit(const char *name)
static const char PassName[]
A manager for alias analyses.
void registerFunctionAnalysis()
Register a specific AA result.
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:620
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:836
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Legacy wrapper pass to provide the NVPTXAAResult object.
Analysis pass providing a never-invalidated alias analysis result.
unsigned int getSmVersion() const
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
void registerDefaultAliasAnalyses(AAManager &AAM) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
~NVPTXTargetMachine() override
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OP, bool is64bit)
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:100
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:458
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:510
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:518
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:540
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:544
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void setRequiresStructuredCFG(bool Value)
std::unique_ptr< const MCSubtargetInfo > STI
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ Aggressive
-O3
Definition: CodeGen.h:61
@ NVCL
Definition: NVPTX.h:72
@ CUDA
Definition: NVPTX.h:73
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeNVPTXLowerAllocaPass(PassRegistry &)
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
ModulePass * createNVPTXAssignValidGlobalNamesPass()
MachineFunctionPass * createNVPTXReplaceImageHandlesPass()
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1218
ModulePass * createGenericToNVVMPass()
FunctionPass * createNVVMReflectPass(unsigned int SmVersion)
Definition: NVVMReflect.cpp:65
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)
void initializeNVPTXExternalAAWrapperPass(PassRegistry &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ ADDRESS_SPACE_LOCAL
Definition: NVPTXBaseInfo.h:26
@ ADDRESS_SPACE_CONST
Definition: NVPTXBaseInfo.h:25
@ ADDRESS_SPACE_GLOBAL
Definition: NVPTXBaseInfo.h:23
@ ADDRESS_SPACE_SHARED
Definition: NVPTXBaseInfo.h:24
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
MachineFunctionPass * createNVPTXPrologEpilogPass()
MachineFunctionPass * createNVPTXProxyRegErasurePass()
void initializeNVPTXDAGToDAGISelPass(PassRegistry &)
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
FunctionPass * createNaryReassociatePass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
MachineFunctionPass * createNVPTXPeephole()
void initializeNVVMReflectPass(PassRegistry &)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & LiveDebugValuesID
LiveDebugValues pass.
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
void initializeNVPTXLowerArgsPass(PassRegistry &)
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
FunctionPass * createNVPTXLowerArgsPass()
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
void initializeGenericToNVVMPass(PassRegistry &)
void initializeNVPTXAAWrapperPassPass(PassRegistry &)
FunctionPass * createNVPTXImageOptimizerPass()
FunctionPass * createNVPTXLowerAllocaPass()
FunctionPass * createSpeculativeExecutionPass()
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createAllocaHoisting()
void initializeNVVMIntrRangePass(PassRegistry &)
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
FunctionPass * createLowerAggrCopies()
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:162
FunctionPass * createNVPTXAtomicLowerPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3211
void initializeNVPTXAllocaHoistingPass(PassRegistry &)
Target & getTheNVPTXTarget64()
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
ImmutablePass * createNVPTXAAWrapperPass()
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
FunctionPass * createStraightLineStrengthReducePass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1793
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
FunctionPass * createSROAPass(bool PreserveCFG=true)
Definition: SROA.cpp:5021
void initializeNVPTXAtomicLowerPass(PassRegistry &)
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...
Target & getTheNVPTXTarget32()
Definition: BitVector.h:851
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
RegisterTargetMachine - Helper template for registering a target machine implementation,...