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67 #define DEBUG_TYPE "twoaddressinstruction"
69 STATISTIC(NumTwoAddressInstrs,
"Number of two-address instructions");
70 STATISTIC(NumCommuted ,
"Number of instructions commuted to coalesce");
71 STATISTIC(NumAggrCommuted ,
"Number of instructions aggressively commuted");
72 STATISTIC(NumConvertedTo3Addr,
"Number of instructions promoted to 3-address");
73 STATISTIC(NumReSchedUps,
"Number of instructions re-scheduled up");
74 STATISTIC(NumReSchedDowns,
"Number of instructions re-scheduled down");
79 cl::desc(
"Coalesce copies by rescheduling (default=true)"),
86 cl::desc(
"Maximum number of dataflow edges to traverse when evaluating "
87 "the benefit of commuting operands"));
123 bool noUseAfterLastDef(
Register Reg,
unsigned Dist,
unsigned &LastDef);
129 unsigned RegBIdx,
unsigned RegCIdx,
unsigned Dist);
146 unsigned SrcIdx,
unsigned DstIdx,
147 unsigned Dist,
bool shouldOnlyCommute);
162 void processTiedPairs(
MachineInstr *
MI, TiedPairList&,
unsigned &Dist);
195 "Two-Address instruction pass",
false,
false)
224 bool TwoAddressInstructionPass::isRevCopyChain(
Register FromReg,
Register ToReg,
227 for (
int i = 0;
i < Maxlen;
i++) {
229 if (!
Def || !
Def->isCopy())
232 TmpReg =
Def->getOperand(1).getReg();
244 bool TwoAddressInstructionPass::noUseAfterLastDef(
Register Reg,
unsigned Dist,
247 unsigned LastUse = Dist;
250 if (
MI->getParent() !=
MBB ||
MI->isDebugValue())
253 if (DI == DistanceMap.
end())
255 if (MO.isUse() && DI->second < LastUse)
256 LastUse = DI->second;
257 if (MO.isDef() && DI->second > LastDef)
258 LastDef = DI->second;
261 return !(LastUse > LastDef && LastUse < Dist);
273 DstReg =
MI.getOperand(0).getReg();
274 SrcReg =
MI.getOperand(1).getReg();
275 }
else if (
MI.isInsertSubreg() ||
MI.isSubregToReg()) {
276 DstReg =
MI.getOperand(0).getReg();
277 SrcReg =
MI.getOperand(2).getReg();
306 assert(
I != LI.
end() &&
"Reg must be live-in to use.");
310 return MI->killsRegister(
Reg);
340 if (
Reg.isPhysical())
348 bool IsSrcPhys, IsDstPhys;
361 for (
unsigned i = 0, NumOps =
MI.getNumOperands();
i != NumOps; ++
i) {
366 if (
MI.isRegTiedToDefOperand(
i, &ti)) {
367 DstReg =
MI.getOperand(ti).getReg();
379 bool &IsCopy,
Register &DstReg,
bool &IsDstPhys) {
404 while (
Reg.isVirtual()) {
406 if (
SI == RegMap.
end())
410 if (
Reg.isPhysical())
428 for (
unsigned R : Set)
437 bool TwoAddressInstructionPass::isProfitableToCommute(
Register RegA,
487 if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
493 if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
499 unsigned LastDefC = 0;
500 if (!noUseAfterLastDef(RegC, Dist, LastDefC))
505 unsigned LastDefB = 0;
506 if (!noUseAfterLastDef(RegB, Dist, LastDefB))
532 return LastDefB && LastDefC && LastDefC > LastDefB;
537 bool TwoAddressInstructionPass::commuteInstruction(
MachineInstr *
MI,
542 Register RegC =
MI->getOperand(RegCIdx).getReg();
546 if (NewMI ==
nullptr) {
553 "TargetInstrInfo::commuteInstruction() should not return a new "
554 "instruction unless it was requested.");
559 Register RegA =
MI->getOperand(DstIdx).getReg();
560 SrcRegMap[RegA] = FromRegC;
568 bool TwoAddressInstructionPass::isProfitableToConv3Addr(
Register RegA,
585 bool TwoAddressInstructionPass::convertInstTo3Addr(
592 "convertToThreeAddress changed iterator reference");
603 if (
auto OldInstrNum = mi->peekDebugInstrNum()) {
605 assert(mi->getNumExplicitDefs() == 1);
609 auto OldIt = mi->defs().begin();
610 auto NewIt = NewMI->
defs().begin();
611 unsigned OldIdx = mi->getOperandNo(OldIt);
617 std::make_pair(NewInstrNum, NewIdx));
622 DistanceMap.
insert(std::make_pair(NewMI, Dist));
627 SrcRegMap.
erase(RegA);
628 DstRegMap.
erase(RegB);
634 void TwoAddressInstructionPass::scanUses(
Register DstReg) {
641 NewReg, IsDstPhys)) {
646 if (DI != DistanceMap.
end())
651 VirtRegPairs.push_back(NewReg);
654 bool isNew = SrcRegMap.
insert(std::make_pair(NewReg,
Reg)).second;
656 assert(SrcRegMap[NewReg] ==
Reg &&
"Can't map to two src registers!");
657 VirtRegPairs.push_back(NewReg);
661 if (!VirtRegPairs.empty()) {
662 unsigned ToReg = VirtRegPairs.back();
663 VirtRegPairs.pop_back();
664 while (!VirtRegPairs.empty()) {
665 unsigned FromReg = VirtRegPairs.back();
666 VirtRegPairs.pop_back();
667 bool isNew = DstRegMap.
insert(std::make_pair(FromReg, ToReg)).second;
669 assert(DstRegMap[FromReg] == ToReg &&
"Can't map to two dst registers!");
672 bool isNew = DstRegMap.
insert(std::make_pair(DstReg, ToReg)).second;
674 assert(DstRegMap[DstReg] == ToReg &&
"Can't map to two dst registers!");
694 bool IsSrcPhys, IsDstPhys;
699 if (IsDstPhys && !IsSrcPhys) {
700 DstRegMap.
insert(std::make_pair(SrcReg, DstReg));
701 }
else if (!IsDstPhys && IsSrcPhys) {
702 bool isNew = SrcRegMap.
insert(std::make_pair(DstReg, SrcReg)).second;
704 assert(SrcRegMap[DstReg] == SrcReg &&
705 "Can't map to two src physical registers!");
716 bool TwoAddressInstructionPass::rescheduleMIBelowKill(
726 if (DI == DistanceMap.
end())
734 "Reg should not have empty live interval.");
738 if (
I != LI.
end() &&
I->start < MBBEndIdx)
759 bool SeenStore =
true;
760 if (!
MI->isSafeToMove(AA, SeenStore))
777 Defs.push_back(MOReg);
779 Uses.push_back(MOReg);
780 if (MOReg !=
Reg && (MO.isKill() ||
782 Kills.push_back(MOReg);
790 while (End !=
MBB->
end()) {
793 Defs.push_back(End->getOperand(0).getReg());
800 unsigned NumVisited = 0;
805 if (OtherMI.isDebugOrPseudoInstr())
810 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
811 OtherMI.isBranch() || OtherMI.isTerminator())
838 if (MOReg ==
Reg && !isKill)
842 assert((MOReg !=
Reg || &OtherMI == KillMI) &&
843 "Found multiple kills of a register in a basic block");
849 while (Begin !=
MBB->
begin() && std::prev(Begin)->isDebugInstr())
858 auto CopyMI =
MBBI++;
868 DistanceMap.
erase(DI);
884 bool TwoAddressInstructionPass::isDefTooClose(
Register Reg,
unsigned Dist,
892 if (DDI == DistanceMap.
end())
894 unsigned DefDist = DDI->second;
895 assert(Dist > DefDist &&
"Visited def already?");
905 bool TwoAddressInstructionPass::rescheduleKillAboveMI(
915 if (DI == DistanceMap.
end())
923 "Reg should not have empty live interval.");
927 if (
I != LI.
end() &&
I->start < MBBEndIdx)
943 bool SeenStore =
true;
958 if (isDefTooClose(MOReg, DI->second,
MI))
960 bool isKill = MO.isKill() || (LIS &&
isPlainlyKilled(KillMI, MOReg, LIS));
961 if (MOReg ==
Reg && !isKill)
963 Uses.push_back(MOReg);
964 if (isKill && MOReg !=
Reg)
965 Kills.push_back(MOReg);
967 Defs.push_back(MOReg);
969 LiveDefs.push_back(MOReg);
974 unsigned NumVisited = 0;
978 if (OtherMI.isDebugOrPseudoInstr())
983 if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
984 OtherMI.isBranch() || OtherMI.isTerminator())
1002 if (&OtherMI !=
MI && MOReg ==
Reg &&
1007 OtherDefs.push_back(MOReg);
1011 for (
unsigned i = 0,
e = OtherDefs.size();
i !=
e; ++
i) {
1024 while (InsertPos !=
MBB->
begin() && std::prev(InsertPos)->isDebugInstr())
1028 while (std::prev(
From)->isDebugInstr())
1032 nmi = std::prev(InsertPos);
1033 DistanceMap.
erase(DI);
1059 bool TwoAddressInstructionPass::tryInstructionCommute(
MachineInstr *
MI,
1064 if (!
MI->isCommutable())
1067 bool MadeChange =
false;
1068 Register DstOpReg =
MI->getOperand(DstOpIdx).getReg();
1069 Register BaseOpReg =
MI->getOperand(BaseOpIdx).getReg();
1070 unsigned OpsNum =
MI->getDesc().getNumOperands();
1071 unsigned OtherOpIdx =
MI->getDesc().getNumDefs();
1072 for (; OtherOpIdx < OpsNum; OtherOpIdx++) {
1077 if (OtherOpIdx == BaseOpIdx || !
MI->getOperand(OtherOpIdx).isReg() ||
1078 !
TII->findCommutedOpIndices(*
MI, BaseOpIdx, OtherOpIdx))
1081 Register OtherOpReg =
MI->getOperand(OtherOpIdx).getReg();
1082 bool AggressiveCommute =
false;
1087 bool DoCommute = !BaseOpKilled && OtherOpKilled;
1090 isProfitableToCommute(DstOpReg, BaseOpReg, OtherOpReg,
MI, Dist)) {
1092 AggressiveCommute =
true;
1096 if (DoCommute && commuteInstruction(
MI, DstOpIdx, BaseOpIdx, OtherOpIdx,
1100 if (AggressiveCommute)
1107 BaseOpReg = OtherOpReg;
1108 BaseOpKilled = OtherOpKilled;
1111 OpsNum =
MI->getDesc().getNumOperands();
1124 bool TwoAddressInstructionPass::
1127 unsigned SrcIdx,
unsigned DstIdx,
1128 unsigned Dist,
bool shouldOnlyCommute) {
1133 Register regA =
MI.getOperand(DstIdx).getReg();
1134 Register regB =
MI.getOperand(SrcIdx).getReg();
1136 assert(regB.
isVirtual() &&
"cannot make instruction into two-address form");
1142 bool Commuted = tryInstructionCommute(&
MI, DstIdx, SrcIdx, regBKilled, Dist);
1152 if (Commuted && !
MI.isConvertibleTo3Addr())
1155 if (shouldOnlyCommute)
1168 regB =
MI.getOperand(SrcIdx).getReg();
1172 if (
MI.isConvertibleTo3Addr()) {
1175 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1177 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1178 ++NumConvertedTo3Addr;
1203 if (
MI.mayLoad() && !regBKilled) {
1205 unsigned LoadRegIndex;
1207 TII->getOpcodeAfterMemoryUnfold(
MI.getOpcode(),
1218 TII->getRegClass(UnfoldMCID, LoadRegIndex,
TRI, *MF));
1221 if (!
TII->unfoldMemoryOperand(*MF,
MI,
Reg,
1227 assert(NewMIs.size() == 2 &&
1228 "Unfolded a load into multiple instructions!");
1230 NewMIs[1]->addRegisterKilled(
Reg,
TRI);
1238 <<
"2addr: NEW INST: " << *NewMIs[1]);
1241 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1242 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1244 bool TransformResult =
1245 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist,
true);
1246 (void)TransformResult;
1247 assert(!TransformResult &&
1248 "tryInstructionTransform() should return false.");
1249 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1253 for (
unsigned i = 0,
e =
MI.getNumOperands();
i !=
e; ++
i) {
1258 if (NewMIs[0]->killsRegister(MO.
getReg()))
1262 "Kill missing after load unfold!");
1267 if (NewMIs[1]->registerDefIsDead(MO.
getReg()))
1271 "Dead flag missing after load unfold!");
1284 OrigRegs.push_back(MO.
getReg());
1288 MI.eraseFromParent();
1303 NewMIs[0]->eraseFromParent();
1304 NewMIs[1]->eraseFromParent();
1316 bool TwoAddressInstructionPass::
1317 collectTiedOperands(
MachineInstr *
MI, TiedOperandMap &TiedOperands) {
1319 bool AnyOps =
false;
1320 unsigned NumOps =
MI->getNumOperands();
1322 for (
unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1323 unsigned DstIdx = 0;
1324 if (!
MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1332 if (SrcReg == DstReg)
1335 assert(SrcReg && SrcMO.
isUse() &&
"two address instruction invalid");
1349 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1358 TiedPairList &TiedPairs,
1361 return MI->getOperand(TP.second).isEarlyClobber();
1362 }) != TiedPairs.end();
1364 bool RemovedKillFlag =
false;
1365 bool AllUsesCopied =
true;
1366 unsigned LastCopiedReg = 0;
1369 unsigned SubRegB = 0;
1370 for (
auto &TP : TiedPairs) {
1371 unsigned SrcIdx = TP.first;
1372 unsigned DstIdx = TP.second;
1379 RegB =
MI->getOperand(SrcIdx).getReg();
1380 SubRegB =
MI->getOperand(SrcIdx).getSubReg();
1386 AllUsesCopied =
false;
1389 LastCopiedReg = RegA;
1391 assert(RegB.
isVirtual() &&
"cannot make instruction into two-address form");
1397 for (
unsigned i = 0;
i !=
MI->getNumOperands(); ++
i)
1399 !
MI->getOperand(
i).isReg() ||
1400 MI->getOperand(
i).getReg() != RegA);
1405 TII->get(TargetOpcode::COPY), RegA);
1408 MIB.
addReg(RegB, 0, SubRegB);
1414 "tied subregister must be a truncation");
1419 &&
"tied subregister must be a truncation");
1426 DistanceMap.
insert(std::make_pair(&*PrevMI, Dist));
1427 DistanceMap[
MI] = ++Dist;
1437 LI.
addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
1445 "inconsistent operand info for 2-reg pass");
1448 RemovedKillFlag =
true;
1461 SrcRegMap[RegA] = RegB;
1464 if (AllUsesCopied) {
1465 bool ReplacedAllUntiedUses =
true;
1466 if (!IsEarlyClobber) {
1473 RemovedKillFlag =
true;
1475 MO.
setReg(LastCopiedReg);
1478 ReplacedAllUntiedUses =
false;
1485 if (RemovedKillFlag && ReplacedAllUntiedUses &&
1497 assert(
I != LI.
end() &&
"RegB must be live-in to use.");
1500 if (
I->end == UseIdx)
1503 }
else if (RemovedKillFlag) {
1518 bool TwoAddressInstructionPass::runOnMachineFunction(
MachineFunction &Func) {
1525 LV = getAnalysisIfAvailable<LiveVariables>();
1526 LIS = getAnalysisIfAvailable<LiveIntervals>();
1527 if (
auto *AAPass = getAnalysisIfAvailable<AAResultsWrapperPass>())
1528 AA = &AAPass->getAAResults();
1531 OptLevel =
TM.getOptLevel();
1534 if (skipFunction(
Func.getFunction()))
1537 bool MadeChange =
false;
1539 LLVM_DEBUG(
dbgs() <<
"********** REWRITING TWO-ADDR INSTRS **********\n");
1549 TiedOperandMap TiedOperands;
1553 DistanceMap.
clear();
1561 if (mi->isDebugInstr()) {
1568 if (mi->isRegSequence())
1569 eliminateRegSequence(mi);
1571 DistanceMap.
insert(std::make_pair(&*mi, ++Dist));
1577 if (!collectTiedOperands(&*mi, TiedOperands)) {
1582 ++NumTwoAddressInstrs;
1589 if (TiedOperands.size() == 1) {
1591 = TiedOperands.begin()->second;
1592 if (TiedPairs.size() == 1) {
1593 unsigned SrcIdx = TiedPairs[0].first;
1594 unsigned DstIdx = TiedPairs[0].second;
1595 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1596 Register DstReg = mi->getOperand(DstIdx).getReg();
1597 if (SrcReg != DstReg &&
1598 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist,
false)) {
1601 TiedOperands.clear();
1609 for (
auto &TO : TiedOperands) {
1610 processTiedPairs(&*mi, TO.second, Dist);
1615 if (mi->isInsertSubreg()) {
1618 unsigned SubIdx = mi->getOperand(3).getImm();
1619 mi->RemoveOperand(3);
1620 assert(mi->getOperand(0).getSubReg() == 0 &&
"Unexpected subreg idx");
1621 mi->getOperand(0).setSubReg(SubIdx);
1622 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1623 mi->RemoveOperand(1);
1624 mi->setDesc(
TII->get(TargetOpcode::COPY));
1630 TiedOperands.clear();
1636 MF->verify(
this,
"After two-address instruction pass");
1651 void TwoAddressInstructionPass::
1655 if (
MI.getOperand(0).getSubReg() || DstReg.
isPhysical() ||
1656 !(
MI.getNumOperands() & 1)) {
1663 OrigRegs.push_back(
MI.getOperand(0).getReg());
1664 for (
unsigned i = 1,
e =
MI.getNumOperands();
i <
e;
i += 2)
1665 OrigRegs.push_back(
MI.getOperand(
i).getReg());
1668 bool DefEmitted =
false;
1669 for (
unsigned i = 1,
e =
MI.getNumOperands();
i <
e;
i += 2) {
1672 unsigned SubIdx =
MI.getOperand(
i+1).getImm();
1679 bool isKill = UseMO.
isKill();
1681 for (
unsigned j =
i + 2;
j <
e;
j += 2)
1682 if (
MI.getOperand(
j).getReg() == SrcReg) {
1683 MI.getOperand(
j).setIsKill();
1691 TII->get(TargetOpcode::COPY))
1716 MI.setDesc(
TII->get(TargetOpcode::IMPLICIT_DEF));
1717 for (
int j =
MI.getNumOperands() - 1, ee = 0;
j > ee; --
j)
1718 MI.RemoveOperand(
j);
1721 MI.eraseFromParent();
iterator find(SlotIndex Pos)
find - Return an iterator pointing to the first segment that ends after Pos, or end().
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
void addVirtualRegisterKilled(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterKilled - Add information about the fact that the specified register is killed after...
void addVirtualRegisterDead(Register IncomingReg, MachineInstr &MI, bool AddIfNotFound=false)
addVirtualRegisterDead - Add information about the fact that the specified register is dead after bei...
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
def_iterator def_begin(Register RegNo) const
MachineInstrBuilder & UseMI
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
const MachineInstrBuilder & add(const MachineOperand &MO) const
virtual const TargetInstrInfo * getInstrInfo() const
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
void setIsKill(bool Val=true)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
bool erase(const KeyT &Val)
static bool regOverlapsSet(const SmallVectorImpl< Register > &Set, Register Reg, const TargetRegisterInfo *TRI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
unsigned const TargetRegisterInfo * TRI
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
MachineInstr * findKill(const MachineBasicBlock *MBB) const
findKill - Find a kill instruction in MBB. Return NULL if none is found.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SmallPtrSet< MachineInstr *, 2 > Uses
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
bool removeKill(MachineInstr &MI)
removeKill - Delete a kill corresponding to the specified machine instruction.
bool isCall(QueryType Type=AnyInBundle) const
TargetInstrInfo - Interface to description of machine instruction set.
static bool regsAreCompatible(Register RegA, Register RegB, const TargetRegisterInfo *TRI)
Return true if the two registers are equal or aliased.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool removeVirtualRegisterKilled(Register Reg, MachineInstr &MI)
removeVirtualRegisterKilled - Remove the specified kill of the virtual register from the live variabl...
const MachineOperand & getOperand(unsigned i) const
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Segments::const_iterator const_iterator
void setSubReg(unsigned subReg)
Represent the analysis usage information of a pass.
const MachineFunctionProperties & getProperties() const
Get the function properties.
const HexagonInstrInfo * TII
void replaceKillInstruction(Register Reg, MachineInstr &OldMI, MachineInstr &NewMI)
replaceKillInstruction - Update register kill info by replacing a kill instruction with a new one.
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
Two Address instruction pass
STATISTIC(NumFunctions, "Total number of functions")
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair)
Create a substitution between one <instr,operand> value to a different, new value.
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
@ Define
Register definition.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex - An opaque wrapper around machine indexes.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg)
Return true if the specified MI uses the specified register as a two-address use.
void erase_value(Container &C, ValueType V)
Wrapper function to remove a value from a container:
INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, DEBUG_TYPE, "Two-Address instruction pass", false, false) INITIALIZE_PASS_END(TwoAddressInstructionPass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
bool hasAtLeastOneValue() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
static MCRegister getMappedReg(Register Reg, DenseMap< Register, Register > &RegMap)
Return the physical register the specified virtual register might be mapped to.
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=false)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
iterator_range< def_instr_iterator > def_instructions(Register Reg) const
Two Address instruction static false bool isPlainlyKilled(MachineInstr *MI, Register Reg, LiveIntervals *LIS)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
initializer< Ty > init(const Ty &Val)
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
iterator_range< reg_iterator > reg_operands(Register Reg) const
iterator find(const_arg_type_t< KeyT > Val)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
static def_iterator def_end()
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
LiveInterval & getInterval(Register Reg)
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
static cl::opt< bool > EnableRescheduling("twoaddr-reschedule", cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
AnalysisUsage & addPreservedID(const void *ID)
MachineBasicBlock MachineBasicBlock::iterator MBBI
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setIsUndef(bool Val=true)
Since we know that Vector is byte aligned and we know the element offset of we should change the load into a lve *x instruction
self_iterator getIterator()
static MachineInstr * getSingleDef(Register Reg, MachineBasicBlock *BB, const MachineRegisterInfo *MRI)
Return the MachineInstr* if it is the single def of the Reg in current BB.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void initializeTwoAddressInstructionPassPass(PassRegistry &)
static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, Register &SrcReg, Register &DstReg, bool &IsSrcPhys, bool &IsDstPhys)
Return true if the specified MI is a copy instruction or an extract_subreg instruction.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Iterator for intrusive lists based on ilist_node.
static MachineInstr * findOnlyInterestingUse(Register Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, Register &DstReg, bool &IsDstPhys)
Given a register, if has a single in-basic block use, return the use instruction if it's a copy or a ...
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
static cl::opt< unsigned > MaxDataFlowEdge("dataflow-edge-limit", cl::Hidden, cl::init(3), cl::desc("Maximum number of dataflow edges to traverse when evaluating " "the benefit of commuting operands"))
VNInfo - Value Number Information.
void removeSegment(SlotIndex Start, SlotIndex End, bool RemoveDeadValNo=false)
Remove the specified segment from this range.
static bool isKilled(MachineInstr &MI, Register Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives)
Test if the given register value, which is used by the given instruction, is killed by the given inst...
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstrBuilder MachineInstrBuilder & DefMI
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void repairIntervalsInRange(MachineBasicBlock *MBB, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, ArrayRef< Register > OrigRegs)
Update live intervals for instructions in a range of iterators.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
BlockVerifier::State From
bool removeVirtualRegisterDead(Register Reg, MachineInstr &MI)
removeVirtualRegisterDead - Remove the specified kill of the virtual register from the live variable ...
iterator_range< mop_iterator > operands()
Itinerary data supplied by a subtarget to be used by a target.
VNInfo::Allocator & getVNInfoAllocator()
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
Wrapper class representing physical registers. Should be passed by value.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.