Go to the documentation of this file.
59 #define DEBUG_TYPE "machinelicm"
63 cl::desc(
"MachineLICM should avoid speculation"),
68 cl::desc(
"MachineLICM should hoist even cheap instructions"),
79 cl::desc(
"Do not hoist instructions if target"
80 "block is N times hotter than the source."),
87 cl::desc(
"Disable hoisting instructions to"
91 "disable the feature"),
93 "enable the feature when using profile data"),
95 "enable the feature with/wo profile data")));
98 "Number of machine instructions hoisted out of loops");
100 "Number of instructions hoisted in low reg pressure situation");
102 "Number of high latency instructions hoisted");
104 "Number of hoisted machine instructions CSEed");
106 "Number of machine instructions hoisted out of loops post regalloc");
108 "Number of stores of const phys reg hoisted out of loops");
110 "Number of instructions not hoisted due to block frequency");
166 unsigned SpeculationState;
169 MachineLICMBase(
char &PassID,
bool PreRegAlloc)
184 void releaseMemory()
override {
194 struct CandidateInfo {
200 :
MI(mi),
Def(def), FI(fi) {}
203 void HoistRegionPostRA();
240 void ExitScopeIfDone(
251 bool ConsiderUnseenAsDef);
254 bool ConsiderUnseenAsDef =
false);
259 std::vector<MachineInstr *> &PrevMIs);
263 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI);
276 class MachineLICM :
public MachineLICMBase {
279 MachineLICM() : MachineLICMBase(
ID,
false) {
284 class EarlyMachineLICM :
public MachineLICMBase {
287 EarlyMachineLICM() : MachineLICMBase(
ID,
true) {
301 "Machine Loop Invariant Code Motion",
false,
false)
321 if (!CurLoop->getLoopPredecessor())
325 if (L->getLoopPredecessor())
335 Changed = FirstInLoop =
false;
337 TII =
ST.getInstrInfo();
338 TLI =
ST.getTargetLowering();
339 TRI =
ST.getRegisterInfo();
359 for (
unsigned i = 0,
e = NumRPS;
i !=
e; ++
i)
365 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
366 MLI = &getAnalysis<MachineLoopInfo>();
367 DT = &getAnalysis<MachineDominatorTree>();
368 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
371 while (!Worklist.empty()) {
372 CurLoop = Worklist.pop_back_val();
373 CurPreheader =
nullptr;
379 Worklist.append(CurLoop->
begin(), CurLoop->
end());
408 if (
MI->memoperands_empty())
411 if (!
MemOp->isStore() || !
MemOp->getPseudoValue())
414 dyn_cast<FixedStackPseudoSourceValue>(
MemOp->getPseudoValue())) {
415 if (
Value->getFrameIndex() == FI)
429 bool RuledOut =
false;
430 bool HasNonInvariantUse =
false;
435 int FI = MO.getIndex();
436 if (!StoredFIs.
count(FI) &&
440 HasNonInvariantUse =
true;
446 if (MO.isRegMask()) {
457 "Not expecting virtual register!");
463 HasNonInvariantUse =
true;
467 if (MO.isImplicit()) {
469 PhysRegClobbers.
set(*AI);
489 if (PhysRegDefs.
test(*AS))
490 PhysRegClobbers.
set(*AS);
495 PhysRegDefs.
set(*AS);
505 if (
Def && !RuledOut) {
507 if ((!HasNonInvariantUse && IsLICMCandidate(*
MI)) ||
509 Candidates.push_back(CandidateInfo(
MI,
Def, FI));
515 void MachineLICMBase::HoistRegionPostRA() {
538 for (
const auto &LI :
BB->liveins()) {
540 PhysRegDefs.
set(*AI);
543 SpeculationState = SpeculateUnknown;
545 ProcessMI(&
MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
551 if (TI != Preheader->
end()) {
571 for (CandidateInfo &Candidate : Candidates) {
573 StoredFIs.
count(Candidate.FI))
576 unsigned Def = Candidate.Def;
577 if (!PhysRegClobbers.
test(
Def) && !TermRegs.test(
Def)) {
581 if (!MO.isReg() || MO.isDef() || !MO.getReg())
593 HoistPostRA(
MI, Candidate.Def);
602 if (!
BB->isLiveIn(
Reg))
606 if (!MO.isReg() || !MO.getReg() || MO.isDef())
continue;
632 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
647 if (SpeculationState != SpeculateUnknown)
648 return SpeculationState == SpeculateFalse;
656 SpeculationState = SpeculateTrue;
661 SpeculationState = SpeculateFalse;
669 bool MachineLICMBase::isTriviallyReMaterializable(
const MachineInstr &
MI,
671 if (!
TII->isTriviallyReMaterializable(
MI,
AA))
675 if (MO.isReg() && MO.isUse() && MO.getReg().isVirtual())
691 BackTrace.pop_back();
700 if (OpenChildren[Node])
704 ExitScope(Node->getBlock());
707 if (!Parent || --OpenChildren[Parent] != 0)
728 WorkList.push_back(HeaderN);
729 while (!WorkList.empty()) {
731 assert(Node &&
"Null dominator tree node?");
744 Scopes.push_back(Node);
745 unsigned NumChildren = Node->getNumChildren();
750 if (
BB->succ_size() >= 25)
753 OpenChildren[Node] = NumChildren;
759 ParentMap[Child] = Node;
760 WorkList.push_back(Child);
765 if (Scopes.size() == 0)
771 InitRegPressure(Preheader);
780 SpeculationState = SpeculateUnknown;
783 UpdateRegPressure(&
MI);
789 ExitScopeIfDone(Node, OpenChildren, ParentMap);
807 if (
BB->pred_size() == 1) {
811 InitRegPressure(*
BB->pred_begin());
815 UpdateRegPressure(&
MI,
true);
820 bool ConsiderUnseenAsDef) {
821 auto Cost = calcRegisterCost(
MI,
true, ConsiderUnseenAsDef);
822 for (
const auto &RPIdAndCost : Cost) {
823 unsigned Class = RPIdAndCost.first;
824 if (
static_cast<int>(
RegPressure[Class]) < -RPIdAndCost.second)
838 MachineLICMBase::calcRegisterCost(
const MachineInstr *
MI,
bool ConsiderSeen,
839 bool ConsiderUnseenAsDef) {
841 if (
MI->isImplicitDef())
843 for (
unsigned i = 0,
e =
MI->getDesc().getNumOperands();
i !=
e; ++
i) {
852 bool isNew = ConsiderSeen ? RegSeen.
insert(
Reg).second :
false;
858 RCCost =
W.RegWeight;
861 if (isNew && !isKill && ConsiderUnseenAsDef)
863 RCCost =
W.RegWeight;
864 else if (!isNew && isKill)
865 RCCost = -
W.RegWeight;
870 for (; *PS != -1; ++PS) {
871 if (Cost.
find(*PS) == Cost.
end())
883 assert(
MI.mayLoad() &&
"Expected MI that loads!");
887 if (
MI.memoperands_empty())
892 if (PSV->isGOT() || PSV->isConstantPool())
909 bool FoundCallerPresReg =
false;
910 if (!
MI.mayStore() ||
MI.hasUnmodeledSideEffects() ||
911 (
MI.getNumOperands() == 0))
927 FoundCallerPresReg =
true;
928 }
else if (!MO.
isImm()) {
932 return FoundCallerPresReg;
950 Register CopySrcReg =
MI.getOperand(1).getReg();
957 Register CopyDstReg =
MI.getOperand(0).getReg();
960 "copy dst is not a virtual reg");
973 bool DontMoveAcrossStore =
true;
974 if ((!
I.isSafeToMove(
AA, DontMoveAcrossStore)) &&
987 !IsGuaranteedToExecute(
I.getParent())) {
996 if (
I.isConvergent())
999 if (!
TII->shouldHoist(
I, CurLoop))
1006 bool MachineLICMBase::IsLoopInvariantInst(
MachineInstr &
I) {
1007 if (!IsLICMCandidate(
I)) {
1008 LLVM_DEBUG(
dbgs() <<
"LICM: Instruction not a LICM candidate\n");
1016 bool MachineLICMBase::HasLoopPHIUse(
const MachineInstr *
MI)
const {
1019 MI = Work.pop_back_val();
1028 if (
UseMI.isPHI()) {
1042 Work.push_back(&
UseMI);
1045 }
while (!Work.empty());
1051 bool MachineLICMBase::HasHighOperandLatency(
MachineInstr &
MI,
unsigned DefIdx,
1057 if (
UseMI.isCopyLike())
1061 for (
unsigned i = 0,
e =
UseMI.getNumOperands();
i !=
e; ++
i) {
1069 if (
TII->hasHighOperandLatency(SchedModel,
MRI,
MI, DefIdx,
UseMI,
i))
1082 bool MachineLICMBase::IsCheapInstruction(
MachineInstr &
MI)
const {
1086 bool isCheap =
false;
1087 unsigned NumDefs =
MI.getDesc().getNumDefs();
1088 for (
unsigned i = 0,
e =
MI.getNumOperands(); NumDefs &&
i !=
e; ++
i) {
1097 if (!
TII->hasLowDefLatency(SchedModel,
MI,
i))
1110 for (
const auto &RPIdAndCost : Cost) {
1111 if (RPIdAndCost.second <= 0)
1114 unsigned Class = RPIdAndCost.first;
1115 int Limit = RegLimit[
Class];
1122 for (
const auto &
RP : BackTrace)
1123 if (
static_cast<int>(
RP[Class]) + RPIdAndCost.second >= Limit)
1133 void MachineLICMBase::UpdateBackTraceRegPressure(
const MachineInstr *
MI) {
1136 auto Cost = calcRegisterCost(
MI,
false,
1140 for (
auto &
RP : BackTrace)
1141 for (
const auto &RPIdAndCost : Cost)
1142 RP[RPIdAndCost.first] += RPIdAndCost.second;
1148 if (
MI.isImplicitDef())
1166 bool CheapInstr = IsCheapInstruction(
MI);
1167 bool CreatesCopy = HasLoopPHIUse(&
MI);
1170 if (CheapInstr && CreatesCopy) {
1177 if (isTriviallyReMaterializable(
MI,
AA))
1182 for (
unsigned i = 0,
e =
MI.getDesc().getNumOperands();
i !=
e; ++
i) {
1189 if (MO.
isDef() && HasHighOperandLatency(
MI,
i,
Reg)) {
1202 auto Cost = calcRegisterCost(&
MI,
false,
1207 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1223 (!IsGuaranteedToExecute(
MI.getParent()) && !MayCSE(&
MI))) {
1230 if (!isTriviallyReMaterializable(
MI,
AA) &&
1231 !
MI.isDereferenceableInvariantLoad(
AA)) {
1244 if (
MI->canFoldAsLoad())
1250 if (!
MI->isDereferenceableInvariantLoad(
AA))
1254 unsigned LoadRegIndex;
1256 TII->getOpcodeAfterMemoryUnfold(
MI->getOpcode(),
1260 if (NewOpc == 0)
return nullptr;
1273 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1275 assert(NewMIs.size() == 2 &&
1276 "Unfolded a load into multiple instructions!");
1283 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1284 NewMIs[0]->eraseFromParent();
1285 NewMIs[1]->eraseFromParent();
1290 UpdateRegPressure(NewMIs[1]);
1295 if (
MI->shouldUpdateCallSiteInfo())
1298 MI->eraseFromParent();
1307 CSEMap[
MI.getOpcode()].push_back(&
MI);
1314 std::vector<MachineInstr *> &PrevMIs) {
1316 if (
TII->produceSameValue(*
MI, *PrevMI, (PreRegAlloc ?
MRI :
nullptr)))
1326 bool MachineLICMBase::EliminateCSE(
1328 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI) {
1331 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1340 for (
unsigned i = 0,
e =
MI->getNumOperands();
i !=
e; ++
i) {
1346 MO.
getReg() == Dup->getOperand(
i).getReg()) &&
1347 "Instructions with different phys regs are not identical!");
1355 for (
unsigned i = 0,
e = Defs.size();
i !=
e; ++
i) {
1356 unsigned Idx = Defs[
i];
1358 Register DupReg = Dup->getOperand(Idx).getReg();
1363 for (
unsigned j = 0;
j !=
i; ++
j)
1369 for (
unsigned Idx : Defs) {
1371 Register DupReg = Dup->getOperand(Idx).getReg();
1376 Dup->getOperand(Idx).setIsDead(
false);
1379 MI->eraseFromParent();
1389 unsigned Opcode =
MI->getOpcode();
1391 CSEMap.
find(Opcode);
1394 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1397 return LookForDuplicate(
MI, CI->second) !=
nullptr;
1409 isTgtHotterThanSrc(SrcBlock, Preheader)) {
1410 ++NumNotHoistedDueToHotness;
1414 if (!IsLoopInvariantInst(*
MI) || !IsProfitableToHoist(*
MI)) {
1416 MI = ExtractHoistableLoad(
MI);
1417 if (!
MI)
return false;
1428 dbgs() <<
"Hoisting " << *
MI;
1429 if (
MI->getParent()->getBasicBlock())
1439 InitCSEMap(Preheader);
1440 FirstInLoop =
false;
1444 unsigned Opcode =
MI->getOpcode();
1446 CSEMap.
find(Opcode);
1447 if (!EliminateCSE(
MI, CI)) {
1454 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
1458 UpdateBackTraceRegPressure(
MI);
1468 if (CI != CSEMap.
end())
1469 CI->second.push_back(
MI);
1471 CSEMap[Opcode].push_back(
MI);
1489 if (!CurPreheader) {
1491 if (!CurPreheader) {
1499 if (!CurPreheader) {
1505 return CurPreheader;
1520 double Ratio = (
double)DstBF / SrcBF;
This is an optimization pass for GlobalISel generic memory operations.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
MachineInstrBuilder & UseMI
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a single loop in the control flow graph.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
TLS Variable Hoist
When an instruction is found to use only loop invariant operands that are safe to hoist,...
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
BlockT * getLoopPredecessor() const
If the given loop's header has exactly one unique predecessor outside the loop, return it.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static cl::opt< UseBFI > DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", cl::desc("Disable hoisting instructions to" " hotter blocks"), cl::init(UseBFI::PGO), cl::Hidden, cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), clEnumValN(UseBFI::PGO, "pgo", "enable the feature when using profile data"), clEnumValN(UseBFI::All, "all", "enable the feature with/wo profile data")))
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
A description of a memory reference used in the backend.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
LLVM_NODISCARD T pop_back_val()
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
unsigned const TargetRegisterInfo * TRI
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Machine Loop Invariant Code Motion
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isAsCheapAsAMove(const MachineInstr &MI) const override
LoopT * getParentLoop() const
Return the parent loop if it exists or nullptr for top level loops.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
STATISTIC(NumFunctions, "Total number of functions")
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Special value supplied for machine level alias analysis.
static cl::opt< unsigned > BlockFrequencyRatioThreshold("block-freq-ratio-threshold", cl::desc("Do not hoist instructions if target" "block is N times hotter than the source."), cl::init(100), cl::Hidden)
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Machine Loop Invariant Code false early machinelicm
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
Provide an instruction scheduling machine model to CodeGen passes.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
void initializeEarlyMachineLICMPass(PassRegistry &)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
initializer< Ty > init(const Ty &Val)
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Register getReg() const
getReg - Returns the register number.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
SmallVector< MachineOperand, 4 > Cond
bool isEHPad() const
Returns true if the block is a landing pad.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE, "Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_END(MachineLICM
Base class for the actual dominator tree node.
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
void initializeMachineLICMPass(PassRegistry &)
bool test(unsigned Idx) const
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Function & getFunction()
Return the LLVM function that this machine code represents.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
BlockT * getHeader() const
Machine Loop Invariant Code false early Early Machine Loop Invariant Code static false bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop)
Test if the given loop is the outer-most loop that has a unique predecessor.
bool hasProfileData(bool IncludeSynthetic=false) const
Return true if the function is annotated with profile data.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
COFF::MachineTypes Machine
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too early
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
AnalysisUsage & addRequired()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
bool isLoopInvariant(MachineInstr &I) const
Returns true if the instruction is loop invariant.
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<>> *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
LLVM Value Representation.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.