59#define DEBUG_TYPE "machinelicm"
63 cl::desc(
"MachineLICM should avoid speculation"),
68 cl::desc(
"MachineLICM should hoist even cheap instructions"),
79 cl::desc(
"Do not hoist instructions if target"
80 "block is N times hotter than the source."),
87 cl::desc(
"Disable hoisting instructions to"
91 "disable the feature"),
93 "enable the feature when using profile data"),
95 "enable the feature with/wo profile data")));
98 "Number of machine instructions hoisted out of loops");
100 "Number of instructions hoisted in low reg pressure situation");
102 "Number of high latency instructions hoisted");
104 "Number of hoisted machine instructions CSEed");
106 "Number of machine instructions hoisted out of loops post regalloc");
108 "Number of stores of const phys reg hoisted out of loops");
110 "Number of instructions not hoisted due to block frequency");
121 bool PreRegAlloc =
false;
122 bool HasProfileData =
false;
131 bool Changed =
false;
132 bool FirstInLoop =
false;
166 unsigned SpeculationState = SpeculateUnknown;
169 MachineLICMBase(
char &PassID,
bool PreRegAlloc)
194 struct CandidateInfo {
200 :
MI(mi),
Def(def), FI(fi) {}
203 void HoistRegionPostRA();
239 void ExitScopeIfDone(
250 bool ConsiderUnseenAsDef);
253 bool ConsiderUnseenAsDef =
false);
258 std::vector<MachineInstr *> &PrevMIs);
262 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI);
275 class MachineLICM :
public MachineLICMBase {
278 MachineLICM() : MachineLICMBase(
ID,
false) {
283 class EarlyMachineLICM :
public MachineLICMBase {
286 EarlyMachineLICM() : MachineLICMBase(
ID,
true) {
294char EarlyMachineLICM::ID;
300 "Machine Loop Invariant Code Motion",
false,
false)
320 if (!CurLoop->getLoopPredecessor())
323 for (
MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop())
324 if (L->getLoopPredecessor())
334 Changed = FirstInLoop =
false;
336 TII =
ST.getInstrInfo();
337 TLI =
ST.getTargetLowering();
338 TRI =
ST.getRegisterInfo();
341 SchedModel.
init(&ST);
343 PreRegAlloc =
MRI->isSSA();
354 unsigned NumRPS =
TRI->getNumRegPressureSets();
358 for (
unsigned i = 0, e = NumRPS; i !=
e; ++i)
359 RegLimit[i] =
TRI->getRegPressureSetLimit(MF, i);
364 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
365 MLI = &getAnalysis<MachineLoopInfo>();
366 DT = &getAnalysis<MachineDominatorTree>();
367 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
370 while (!Worklist.empty()) {
371 CurLoop = Worklist.pop_back_val();
372 CurPreheader =
nullptr;
378 Worklist.append(CurLoop->
begin(), CurLoop->
end());
407 if (
MI->memoperands_empty())
410 if (!
MemOp->isStore() || !
MemOp->getPseudoValue())
413 dyn_cast<FixedStackPseudoSourceValue>(
MemOp->getPseudoValue())) {
414 if (
Value->getFrameIndex() == FI)
428 bool RuledOut =
false;
429 bool HasNonInvariantUse =
false;
434 int FI = MO.getIndex();
435 if (!StoredFIs.
count(FI) &&
439 HasNonInvariantUse =
true;
445 if (MO.isRegMask()) {
455 assert(
Reg.isPhysical() &&
"Not expecting virtual register!");
458 if (Reg && (PhysRegDefs.
test(Reg) || PhysRegClobbers.
test(Reg)))
461 HasNonInvariantUse =
true;
465 if (MO.isImplicit()) {
467 PhysRegClobbers.
set(*AI);
487 if (PhysRegDefs.
test(*AS))
488 PhysRegClobbers.
set(*AS);
493 PhysRegDefs.
set(*AS);
495 if (PhysRegClobbers.
test(Reg))
503 if (Def && !RuledOut) {
504 int FI = std::numeric_limits<int>::min();
505 if ((!HasNonInvariantUse && IsLICMCandidate(*
MI)) ||
513void MachineLICMBase::HoistRegionPostRA() {
518 unsigned NumRegs =
TRI->getNumRegs();
531 if (
ML &&
ML->getHeader()->isEHPad())
continue;
536 for (
const auto &LI : BB->liveins()) {
538 PhysRegDefs.
set(*AI);
542 if (
const uint32_t *Mask = BB->getBeginClobberMask(
TRI))
545 SpeculationState = SpeculateUnknown;
547 ProcessMI(&
MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
553 if (TI != Preheader->
end()) {
573 for (CandidateInfo &Candidate : Candidates) {
574 if (Candidate.FI != std::numeric_limits<int>::min() &&
575 StoredFIs.
count(Candidate.FI))
578 unsigned Def = Candidate.Def;
579 if (!PhysRegClobbers.
test(Def) && !TermRegs.test(Def)) {
586 if (PhysRegDefs.
test(Reg) ||
587 PhysRegClobbers.
test(Reg)) {
595 HoistPostRA(
MI, Candidate.Def);
602void MachineLICMBase::AddToLiveIns(
MCRegister Reg) {
604 if (!BB->isLiveIn(Reg))
610 if (
TRI->isSuperRegisterEq(Reg, MO.getReg()))
619void MachineLICMBase::HoistPostRA(
MachineInstr *
MI,
unsigned Def) {
635 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
650 if (SpeculationState != SpeculateUnknown)
651 return SpeculationState == SpeculateFalse;
658 if (!DT->
dominates(BB, CurrentLoopExitingBlock)) {
659 SpeculationState = SpeculateTrue;
664 SpeculationState = SpeculateFalse;
672bool MachineLICMBase::isTriviallyReMaterializable(
674 if (!
TII->isTriviallyReMaterializable(
MI))
678 if (MO.getReg().isVirtual())
703 if (OpenChildren[
Node])
707 ExitScope(
Node->getBlock());
710 if (!Parent || --OpenChildren[Parent] != 0)
732 while (!WorkList.
empty()) {
740 if (
ML &&
ML->getHeader()->isEHPad())
748 unsigned NumChildren =
Node->getNumChildren();
756 OpenChildren[
Node] = NumChildren;
762 ParentMap[Child] =
Node;
774 InitRegPressure(Preheader);
783 SpeculationState = SpeculateUnknown;
786 UpdateRegPressure(&
MI);
792 ExitScopeIfDone(
Node, OpenChildren, ParentMap);
818 UpdateRegPressure(&
MI,
true);
823 bool ConsiderUnseenAsDef) {
824 auto Cost = calcRegisterCost(
MI,
true, ConsiderUnseenAsDef);
825 for (
const auto &RPIdAndCost :
Cost) {
826 unsigned Class = RPIdAndCost.first;
827 if (
static_cast<int>(RegPressure[Class]) < -RPIdAndCost.second)
841MachineLICMBase::calcRegisterCost(
const MachineInstr *
MI,
bool ConsiderSeen,
842 bool ConsiderUnseenAsDef) {
844 if (
MI->isImplicitDef())
846 for (
unsigned i = 0, e =
MI->getDesc().getNumOperands(); i != e; ++i) {
851 if (!
Reg.isVirtual())
855 bool isNew = ConsiderSeen ? RegSeen.
insert(Reg).second :
false;
861 RCCost =
W.RegWeight;
864 if (isNew && !isKill && ConsiderUnseenAsDef)
866 RCCost =
W.RegWeight;
867 else if (!isNew && isKill)
868 RCCost = -
W.RegWeight;
872 const int *PS =
TRI->getRegClassPressureSets(RC);
873 for (; *PS != -1; ++PS) {
874 if (!
Cost.contains(*PS))
886 assert(
MI.mayLoad() &&
"Expected MI that loads!");
890 if (
MI.memoperands_empty())
895 if (PSV->isGOT() || PSV->isConstantPool())
912 bool FoundCallerPresReg =
false;
913 if (!
MI.mayStore() ||
MI.hasUnmodeledSideEffects() ||
914 (
MI.getNumOperands() == 0))
927 if (!
TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *
MI.getMF()))
930 FoundCallerPresReg =
true;
931 }
else if (!MO.
isImm()) {
935 return FoundCallerPresReg;
953 Register CopySrcReg =
MI.getOperand(1).getReg();
957 if (!
TRI->isCallerPreservedPhysReg(CopySrcReg.
asMCReg(), *MF))
960 Register CopyDstReg =
MI.getOperand(0).getReg();
975 bool DontMoveAcrossStore =
true;
976 if ((!
I.isSafeToMove(AA, DontMoveAcrossStore)) &&
989 !IsGuaranteedToExecute(
I.getParent())) {
998 if (
I.isConvergent())
1001 if (!
TII->shouldHoist(
I, CurLoop))
1009 if (!IsLICMCandidate(
I)) {
1010 LLVM_DEBUG(
dbgs() <<
"LICM: Instruction not a LICM candidate\n");
1018bool MachineLICMBase::HasLoopPHIUse(
const MachineInstr *
MI)
const {
1021 MI = Work.pop_back_val();
1024 if (!
Reg.isVirtual())
1028 if (
UseMI.isPHI()) {
1042 Work.push_back(&
UseMI);
1045 }
while (!Work.empty());
1051bool MachineLICMBase::HasHighOperandLatency(
MachineInstr &
MI,
unsigned DefIdx,
1053 if (
MRI->use_nodbg_empty(Reg))
1057 if (
UseMI.isCopyLike())
1061 for (
unsigned i = 0, e =
UseMI.getNumOperands(); i != e; ++i) {
1069 if (
TII->hasHighOperandLatency(SchedModel,
MRI,
MI, DefIdx,
UseMI, i))
1082bool MachineLICMBase::IsCheapInstruction(
MachineInstr &
MI)
const {
1086 bool isCheap =
false;
1087 unsigned NumDefs =
MI.getDesc().getNumDefs();
1088 for (
unsigned i = 0, e =
MI.getNumOperands(); NumDefs && i != e; ++i) {
1094 if (
Reg.isPhysical())
1097 if (!
TII->hasLowDefLatency(SchedModel,
MI, i))
1110 for (
const auto &RPIdAndCost :
Cost) {
1111 if (RPIdAndCost.second <= 0)
1114 unsigned Class = RPIdAndCost.first;
1115 int Limit = RegLimit[
Class];
1122 for (
const auto &RP : BackTrace)
1123 if (
static_cast<int>(RP[Class]) + RPIdAndCost.second >= Limit)
1133void MachineLICMBase::UpdateBackTraceRegPressure(
const MachineInstr *
MI) {
1136 auto Cost = calcRegisterCost(
MI,
false,
1140 for (
auto &RP : BackTrace)
1141 for (
const auto &RPIdAndCost :
Cost)
1142 RP[RPIdAndCost.first] += RPIdAndCost.second;
1148 if (
MI.isImplicitDef())
1166 bool CheapInstr = IsCheapInstruction(
MI);
1167 bool CreatesCopy = HasLoopPHIUse(&
MI);
1170 if (CheapInstr && CreatesCopy) {
1177 if (isTriviallyReMaterializable(
MI))
1182 for (
unsigned i = 0, e =
MI.getDesc().getNumOperands(); i != e; ++i) {
1187 if (!
Reg.isVirtual())
1189 if (MO.
isDef() && HasHighOperandLatency(
MI, i, Reg)) {
1202 auto Cost = calcRegisterCost(&
MI,
false,
1207 if (!CanCauseHighRegPressure(
Cost, CheapInstr)) {
1223 (!IsGuaranteedToExecute(
MI.getParent()) && !MayCSE(&
MI))) {
1230 if (!isTriviallyReMaterializable(
MI) &&
1231 !
MI.isDereferenceableInvariantLoad()) {
1244 if (
MI->canFoldAsLoad())
1250 if (!
MI->isDereferenceableInvariantLoad())
1254 unsigned LoadRegIndex;
1256 TII->getOpcodeAfterMemoryUnfold(
MI->getOpcode(),
1260 if (NewOpc == 0)
return nullptr;
1273 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1276 "Unfolded a load into multiple instructions!");
1283 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1284 NewMIs[0]->eraseFromParent();
1285 NewMIs[1]->eraseFromParent();
1290 UpdateRegPressure(NewMIs[1]);
1295 if (
MI->shouldUpdateCallSiteInfo())
1298 MI->eraseFromParent();
1307 CSEMap[
MI.getOpcode()].push_back(&
MI);
1314 std::vector<MachineInstr *> &PrevMIs) {
1316 if (
TII->produceSameValue(*
MI, *PrevMI, (PreRegAlloc ?
MRI :
nullptr)))
1326bool MachineLICMBase::EliminateCSE(
1328 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI) {
1331 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1340 for (
unsigned i = 0, e =
MI->getNumOperands(); i != e; ++i) {
1345 MO.
getReg() == Dup->getOperand(i).getReg()) &&
1346 "Instructions with different phys regs are not identical!");
1353 for (
unsigned i = 0, e = Defs.
size(); i != e; ++i) {
1354 unsigned Idx = Defs[i];
1359 if (!
MRI->constrainRegClass(DupReg,
MRI->getRegClass(Reg))) {
1361 for (
unsigned j = 0;
j != i; ++
j)
1362 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1367 for (
unsigned Idx : Defs) {
1370 MRI->replaceRegWith(Reg, DupReg);
1371 MRI->clearKillFlags(DupReg);
1373 if (!
MRI->use_nodbg_empty(DupReg))
1374 Dup->getOperand(
Idx).setIsDead(
false);
1377 MI->eraseFromParent();
1387 unsigned Opcode =
MI->getOpcode();
1389 CSEMap.
find(Opcode);
1392 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1395 return LookForDuplicate(
MI, CI->second) !=
nullptr;
1407 isTgtHotterThanSrc(SrcBlock, Preheader)) {
1408 ++NumNotHoistedDueToHotness;
1412 if (!IsLoopInvariantInst(*
MI) || !IsProfitableToHoist(*
MI)) {
1414 MI = ExtractHoistableLoad(
MI);
1415 if (!
MI)
return false;
1426 dbgs() <<
"Hoisting " << *
MI;
1427 if (
MI->getParent()->getBasicBlock())
1437 InitCSEMap(Preheader);
1438 FirstInLoop =
false;
1442 unsigned Opcode =
MI->getOpcode();
1444 CSEMap.
find(Opcode);
1445 if (!EliminateCSE(
MI, CI)) {
1452 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
1456 UpdateBackTraceRegPressure(
MI);
1466 if (CI != CSEMap.
end())
1467 CI->second.push_back(
MI);
1469 CSEMap[Opcode].push_back(
MI);
1487 if (!CurPreheader) {
1489 if (!CurPreheader) {
1497 if (!CurPreheader) {
1503 return CurPreheader;
1518 double Ratio = (double)DstBF / SrcBF;
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
This file implements the BitVector class.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
const HexagonInstrInfo * TII
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
Machine Loop Invariant Code false early machinelicm
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
static cl::opt< UseBFI > DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", cl::desc("Disable hoisting instructions to" " hotter blocks"), cl::init(UseBFI::PGO), cl::Hidden, cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), clEnumValN(UseBFI::PGO, "pgo", "enable the feature when using profile data"), clEnumValN(UseBFI::All, "all", "enable the feature with/wo profile data")))
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
Machine Loop Invariant Code false early Early Machine Loop Invariant Code static false bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop)
Test if the given loop is the outer-most loop that has a unique predecessor.
Machine Loop Invariant Code Motion
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
static cl::opt< unsigned > BlockFrequencyRatioThreshold("block-freq-ratio-threshold", cl::desc("Do not hoist instructions if target" "block is N times hotter than the source."), cl::init(100), cl::Hidden)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
TLS Variable Hoist
When an instruction is found to use only loop invariant operands that are safe to hoist,...
This file describes how to lower LLVM code to machine code.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
bool test(unsigned Idx) const
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
iterator find(const_arg_type_t< KeyT > Val)
Base class for the actual dominator tree node.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
bool hasProfileData(bool IncludeSynthetic=false) const
Return true if the function is annotated with profile data.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool isAsCheapAsAMove(const MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
BlockT * getHeader() const
BlockT * getLoopPredecessor() const
If the given loop's header has exactly one unique predecessor outside the loop, return it.
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Represents a single loop in the control flow graph.
Describe properties that are true of each instruction in the target description file.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
unsigned pred_size() const
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
pred_iterator pred_begin()
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<> > *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
Representation of each machine instruction.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
bool isLoopInvariant(MachineInstr &I) const
Returns true if the instruction is loop invariant.
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void releaseMemory()
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
TargetSubtargetInfo - Generic base class for all target subtargets.
LLVM Value Representation.
Reg
All possible values of the reg field in the ModR/M byte.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
initializer< Ty > init(const Ty &Val)
NodeAddr< DefNode * > Def
This is an optimization pass for GlobalISel generic memory operations.
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeMachineLICMPass(PassRegistry &)
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
void initializeEarlyMachineLICMPass(PassRegistry &)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...