Go to the documentation of this file.
59 #define DEBUG_TYPE "machinelicm"
63 cl::desc(
"MachineLICM should avoid speculation"),
68 cl::desc(
"MachineLICM should hoist even cheap instructions"),
79 cl::desc(
"Do not hoist instructions if target"
80 "block is N times hotter than the source."),
87 cl::desc(
"Disable hoisting instructions to"
91 "disable the feature"),
93 "enable the feature when using profile data"),
95 "enable the feature with/wo profile data")));
98 "Number of machine instructions hoisted out of loops");
100 "Number of instructions hoisted in low reg pressure situation");
102 "Number of high latency instructions hoisted");
104 "Number of hoisted machine instructions CSEed");
106 "Number of machine instructions hoisted out of loops post regalloc");
108 "Number of stores of const phys reg hoisted out of loops");
110 "Number of instructions not hoisted due to block frequency");
166 unsigned SpeculationState;
169 MachineLICMBase(
char &PassID,
bool PreRegAlloc)
184 void releaseMemory()
override {
194 struct CandidateInfo {
200 :
MI(mi),
Def(def), FI(fi) {}
203 void HoistRegionPostRA();
237 void ExitScopeIfDone(
248 bool ConsiderUnseenAsDef);
251 bool ConsiderUnseenAsDef =
false);
256 std::vector<MachineInstr *> &PrevMIs);
260 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI);
273 class MachineLICM :
public MachineLICMBase {
276 MachineLICM() : MachineLICMBase(
ID,
false) {
281 class EarlyMachineLICM :
public MachineLICMBase {
284 EarlyMachineLICM() : MachineLICMBase(
ID,
true) {
298 "Machine Loop Invariant Code Motion",
false,
false)
318 if (!CurLoop->getLoopPredecessor())
322 if (L->getLoopPredecessor())
332 Changed = FirstInLoop =
false;
334 TII =
ST.getInstrInfo();
335 TLI =
ST.getTargetLowering();
336 TRI =
ST.getRegisterInfo();
356 for (
unsigned i = 0,
e = NumRPS;
i !=
e; ++
i)
362 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
363 MLI = &getAnalysis<MachineLoopInfo>();
364 DT = &getAnalysis<MachineDominatorTree>();
365 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
368 while (!Worklist.empty()) {
369 CurLoop = Worklist.pop_back_val();
370 CurPreheader =
nullptr;
376 Worklist.append(CurLoop->
begin(), CurLoop->
end());
405 if (
MI->memoperands_empty())
408 if (!
MemOp->isStore() || !
MemOp->getPseudoValue())
411 dyn_cast<FixedStackPseudoSourceValue>(
MemOp->getPseudoValue())) {
412 if (
Value->getFrameIndex() == FI)
426 bool RuledOut =
false;
427 bool HasNonInvariantUse =
false;
432 int FI = MO.getIndex();
433 if (!StoredFIs.
count(FI) &&
437 HasNonInvariantUse =
true;
443 if (MO.isRegMask()) {
454 "Not expecting virtual register!");
460 HasNonInvariantUse =
true;
464 if (MO.isImplicit()) {
466 PhysRegClobbers.
set(*AI);
486 if (PhysRegDefs.
test(*AS))
487 PhysRegClobbers.
set(*AS);
492 PhysRegDefs.
set(*AS);
502 if (
Def && !RuledOut) {
504 if ((!HasNonInvariantUse && IsLICMCandidate(*
MI)) ||
506 Candidates.push_back(CandidateInfo(
MI,
Def, FI));
512 void MachineLICMBase::HoistRegionPostRA() {
535 for (
const auto &LI :
BB->liveins()) {
537 PhysRegDefs.
set(*AI);
540 SpeculationState = SpeculateUnknown;
542 ProcessMI(&
MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
548 if (TI != Preheader->
end()) {
568 for (CandidateInfo &Candidate : Candidates) {
570 StoredFIs.
count(Candidate.FI))
573 unsigned Def = Candidate.Def;
574 if (!PhysRegClobbers.
test(
Def) && !TermRegs.test(
Def)) {
578 if (!MO.isReg() || MO.isDef() || !MO.getReg())
590 HoistPostRA(
MI, Candidate.Def);
599 if (!
BB->isLiveIn(
Reg))
603 if (!MO.isReg() || !MO.getReg() || MO.isDef())
continue;
629 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
644 if (SpeculationState != SpeculateUnknown)
645 return SpeculationState == SpeculateFalse;
653 SpeculationState = SpeculateTrue;
658 SpeculationState = SpeculateFalse;
671 BackTrace.pop_back();
680 if (OpenChildren[Node])
684 ExitScope(Node->getBlock());
688 unsigned Left = --OpenChildren[Parent];
691 ExitScope(Parent->getBlock());
711 WorkList.push_back(HeaderN);
712 while (!WorkList.empty()) {
714 assert(Node &&
"Null dominator tree node?");
727 Scopes.push_back(Node);
728 unsigned NumChildren = Node->getNumChildren();
733 if (
BB->succ_size() >= 25)
736 OpenChildren[Node] = NumChildren;
742 ParentMap[Child] = Node;
743 WorkList.push_back(Child);
748 if (Scopes.size() == 0)
754 InitRegPressure(Preheader);
763 SpeculationState = SpeculateUnknown;
768 if (!Hoist(
MI, Preheader))
769 UpdateRegPressure(
MI);
776 ExitScopeIfDone(Node, OpenChildren, ParentMap);
794 if (
BB->pred_size() == 1) {
798 InitRegPressure(*
BB->pred_begin());
802 UpdateRegPressure(&
MI,
true);
807 bool ConsiderUnseenAsDef) {
808 auto Cost = calcRegisterCost(
MI,
true, ConsiderUnseenAsDef);
809 for (
const auto &RPIdAndCost : Cost) {
810 unsigned Class = RPIdAndCost.first;
811 if (
static_cast<int>(
RegPressure[Class]) < -RPIdAndCost.second)
825 MachineLICMBase::calcRegisterCost(
const MachineInstr *
MI,
bool ConsiderSeen,
826 bool ConsiderUnseenAsDef) {
828 if (
MI->isImplicitDef())
830 for (
unsigned i = 0,
e =
MI->getDesc().getNumOperands();
i !=
e; ++
i) {
839 bool isNew = ConsiderSeen ? RegSeen.
insert(
Reg).second :
false;
845 RCCost =
W.RegWeight;
848 if (isNew && !isKill && ConsiderUnseenAsDef)
850 RCCost =
W.RegWeight;
851 else if (!isNew && isKill)
852 RCCost = -
W.RegWeight;
857 for (; *PS != -1; ++PS) {
858 if (Cost.
find(*PS) == Cost.
end())
870 assert(
MI.mayLoad() &&
"Expected MI that loads!");
874 if (
MI.memoperands_empty())
879 if (PSV->isGOT() || PSV->isConstantPool())
896 bool FoundCallerPresReg =
false;
897 if (!
MI.mayStore() ||
MI.hasUnmodeledSideEffects() ||
898 (
MI.getNumOperands() == 0))
914 FoundCallerPresReg =
true;
915 }
else if (!MO.
isImm()) {
919 return FoundCallerPresReg;
937 Register CopySrcReg =
MI.getOperand(1).getReg();
944 Register CopyDstReg =
MI.getOperand(0).getReg();
947 "copy dst is not a virtual reg");
960 bool DontMoveAcrossStore =
true;
961 if ((!
I.isSafeToMove(AA, DontMoveAcrossStore)) &&
974 !IsGuaranteedToExecute(
I.getParent())) {
983 if (
I.isConvergent())
991 if (!IsLICMCandidate(
I)) {
1000 bool MachineLICMBase::HasLoopPHIUse(
const MachineInstr *
MI)
const {
1003 MI = Work.pop_back_val();
1012 if (
UseMI.isPHI()) {
1026 Work.push_back(&
UseMI);
1029 }
while (!Work.empty());
1035 bool MachineLICMBase::HasHighOperandLatency(
MachineInstr &
MI,
unsigned DefIdx,
1041 if (
UseMI.isCopyLike())
1045 for (
unsigned i = 0,
e =
UseMI.getNumOperands();
i !=
e; ++
i) {
1053 if (
TII->hasHighOperandLatency(SchedModel,
MRI,
MI, DefIdx,
UseMI,
i))
1066 bool MachineLICMBase::IsCheapInstruction(
MachineInstr &
MI)
const {
1067 if (
TII->isAsCheapAsAMove(
MI) ||
MI.isCopyLike())
1070 bool isCheap =
false;
1071 unsigned NumDefs =
MI.getDesc().getNumDefs();
1072 for (
unsigned i = 0,
e =
MI.getNumOperands(); NumDefs &&
i !=
e; ++
i) {
1081 if (!
TII->hasLowDefLatency(SchedModel,
MI,
i))
1094 for (
const auto &RPIdAndCost : Cost) {
1095 if (RPIdAndCost.second <= 0)
1098 unsigned Class = RPIdAndCost.first;
1099 int Limit = RegLimit[
Class];
1106 for (
const auto &
RP : BackTrace)
1107 if (
static_cast<int>(
RP[Class]) + RPIdAndCost.second >= Limit)
1117 void MachineLICMBase::UpdateBackTraceRegPressure(
const MachineInstr *
MI) {
1120 auto Cost = calcRegisterCost(
MI,
false,
1124 for (
auto &
RP : BackTrace)
1125 for (
const auto &RPIdAndCost : Cost)
1126 RP[RPIdAndCost.first] += RPIdAndCost.second;
1132 if (
MI.isImplicitDef())
1150 bool CheapInstr = IsCheapInstruction(
MI);
1151 bool CreatesCopy = HasLoopPHIUse(&
MI);
1154 if (CheapInstr && CreatesCopy) {
1161 if (
TII->isTriviallyReMaterializable(
MI, AA))
1166 for (
unsigned i = 0,
e =
MI.getDesc().getNumOperands();
i !=
e; ++
i) {
1173 if (MO.
isDef() && HasHighOperandLatency(
MI,
i,
Reg)) {
1186 auto Cost = calcRegisterCost(&
MI,
false,
1191 if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
1207 (!IsGuaranteedToExecute(
MI.getParent()) && !MayCSE(&
MI))) {
1214 if (!
TII->isTriviallyReMaterializable(
MI, AA) &&
1215 !
MI.isDereferenceableInvariantLoad(AA)) {
1228 if (
MI->canFoldAsLoad())
1234 if (!
MI->isDereferenceableInvariantLoad(AA))
1238 unsigned LoadRegIndex;
1240 TII->getOpcodeAfterMemoryUnfold(
MI->getOpcode(),
1244 if (NewOpc == 0)
return nullptr;
1257 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
1259 assert(NewMIs.size() == 2 &&
1260 "Unfolded a load into multiple instructions!");
1267 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1268 NewMIs[0]->eraseFromParent();
1269 NewMIs[1]->eraseFromParent();
1274 UpdateRegPressure(NewMIs[1]);
1279 if (
MI->shouldUpdateCallSiteInfo())
1282 MI->eraseFromParent();
1291 CSEMap[
MI.getOpcode()].push_back(&
MI);
1298 std::vector<MachineInstr *> &PrevMIs) {
1300 if (
TII->produceSameValue(*
MI, *PrevMI, (PreRegAlloc ?
MRI :
nullptr)))
1310 bool MachineLICMBase::EliminateCSE(
1312 DenseMap<
unsigned, std::vector<MachineInstr *>>::iterator &CI) {
1315 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1324 for (
unsigned i = 0,
e =
MI->getNumOperands();
i !=
e; ++
i) {
1330 MO.
getReg() == Dup->getOperand(
i).getReg()) &&
1331 "Instructions with different phys regs are not identical!");
1339 for (
unsigned i = 0,
e = Defs.size();
i !=
e; ++
i) {
1340 unsigned Idx = Defs[
i];
1342 Register DupReg = Dup->getOperand(Idx).getReg();
1347 for (
unsigned j = 0;
j !=
i; ++
j)
1353 for (
unsigned Idx : Defs) {
1355 Register DupReg = Dup->getOperand(Idx).getReg();
1360 Dup->getOperand(Idx).setIsDead(
false);
1363 MI->eraseFromParent();
1373 unsigned Opcode =
MI->getOpcode();
1375 CSEMap.
find(Opcode);
1378 if (CI == CSEMap.
end() ||
MI->isImplicitDef())
1381 return LookForDuplicate(
MI, CI->second) !=
nullptr;
1393 isTgtHotterThanSrc(SrcBlock, Preheader)) {
1394 ++NumNotHoistedDueToHotness;
1398 if (!IsLoopInvariantInst(*
MI) || !IsProfitableToHoist(*
MI)) {
1400 MI = ExtractHoistableLoad(
MI);
1401 if (!
MI)
return false;
1412 dbgs() <<
"Hoisting " << *
MI;
1413 if (
MI->getParent()->getBasicBlock())
1423 InitCSEMap(Preheader);
1424 FirstInLoop =
false;
1428 unsigned Opcode =
MI->getOpcode();
1430 CSEMap.
find(Opcode);
1431 if (!EliminateCSE(
MI, CI)) {
1438 assert(!
MI->isDebugInstr() &&
"Should not hoist debug inst");
1442 UpdateBackTraceRegPressure(
MI);
1452 if (CI != CSEMap.
end())
1453 CI->second.push_back(
MI);
1455 CSEMap[Opcode].push_back(
MI);
1473 if (!CurPreheader) {
1475 if (!CurPreheader) {
1483 if (!CurPreheader) {
1489 return CurPreheader;
1504 double Ratio = (
double)DstBF / SrcBF;
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
void setBitsNotInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsNotInMask - Add a bit to this vector for every '0' bit in Mask.
static bool InstructionStoresToFI(const MachineInstr *MI, int FI)
Return true if instruction stores to the specified frame.
MachineInstrBuilder & UseMI
void getExitBlocks(SmallVectorImpl< BlockT * > &ExitBlocks) const
Return all of the successor blocks of this loop.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a single loop in the control flow graph.
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in and only one load from a constant double
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
BlockT * getLoopPredecessor() const
If the given loop's header has exactly one unique predecessor outside the loop, return it.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static cl::opt< UseBFI > DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", cl::desc("Disable hoisting instructions to" " hotter blocks"), cl::init(UseBFI::PGO), cl::Hidden, cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), clEnumValN(UseBFI::PGO, "pgo", "enable the feature when using profile data"), clEnumValN(UseBFI::All, "all", "enable the feature with/wo profile data")))
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
A description of a memory reference used in the backend.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
LLVM_NODISCARD T pop_back_val()
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
static cl::opt< bool > HoistConstStores("hoist-const-stores", cl::desc("Hoist invariant stores"), cl::init(true), cl::Hidden)
char & MachineLICMID
This pass performs loop invariant code motion on machine instructions.
unsigned const TargetRegisterInfo * TRI
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Machine Loop Invariant Code Motion
static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI)
Return true if this machine instruction loads from global offset table or constant pool.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LoopT * getParentLoop() const
Return the parent loop if it exists or nullptr for top level loops.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
const HexagonInstrInfo * TII
Describe properties that are true of each instruction in the target description file.
MachineOperand class - Representation of each machine instruction operand.
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
STATISTIC(NumFunctions, "Total number of functions")
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Special value supplied for machine level alias analysis.
static cl::opt< unsigned > BlockFrequencyRatioThreshold("block-freq-ratio-threshold", cl::desc("Do not hoist instructions if target" "block is N times hotter than the source."), cl::init(100), cl::Hidden)
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Machine Loop Invariant Code false early machinelicm
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI)
Provide an instruction scheduling machine model to CodeGen passes.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
void initializeEarlyMachineLICMPass(PassRegistry &)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
initializer< Ty > init(const Ty &Val)
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Register getReg() const
getReg - Returns the register number.
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
SmallVector< MachineOperand, 4 > Cond
bool isEHPad() const
Returns true if the block is a landing pad.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
static bool isInvariantStore(const MachineInstr &MI, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI)
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
INITIALIZE_PASS_BEGIN(MachineLICM, DEBUG_TYPE, "Machine Loop Invariant Code Motion", false, false) INITIALIZE_PASS_END(MachineLICM
Base class for the actual dominator tree node.
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
void initializeMachineLICMPass(PassRegistry &)
bool test(unsigned Idx) const
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Function & getFunction()
Return the LLVM function that this machine code represents.
static bool isCopyFeedingInvariantStore(const MachineInstr &MI, const MachineRegisterInfo *MRI, const TargetRegisterInfo *TRI)
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
BlockT * getHeader() const
Machine Loop Invariant Code false early Early Machine Loop Invariant Code static false bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop)
Test if the given loop is the outer-most loop that has a unique predecessor.
bool hasProfileData(bool IncludeSynthetic=false) const
Return true if the function is annotated with profile data.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
static cl::opt< bool > HoistCheapInsts("hoist-cheap-insts", cl::desc("MachineLICM should hoist even cheap instructions"), cl::init(false), cl::Hidden)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
COFF::MachineTypes Machine
static bool isExitBlock(BasicBlock *BB, const SmallVectorImpl< BasicBlock * > &ExitBlocks)
Return true if the specified block is in the list.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
the custom lowered code happens to be but we shouldn t have to custom lower anything This is probably related to< 2 x i64 > ops being so bad LLVM currently generates stack realignment when it is not necessary needed The problem is that we need to know about stack alignment too early
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
AnalysisUsage & addRequired()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
void eraseCallSiteInfo(const MachineInstr *MI)
Following functions update call site info.
bool isLoopInvariant(MachineInstr &I) const
Returns true if the instruction is loop invariant.
static cl::opt< bool > AvoidSpeculation("avoid-speculation", cl::desc("MachineLICM should avoid speculation"), cl::init(true), cl::Hidden)
MachineBasicBlock * SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P, std::vector< SparseBitVector<>> *LiveInSets=nullptr)
Split the critical edge from this block to the given successor block, and return the newly created bl...
LLVM Value Representation.
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.