LLVM  15.0.0git
PPCPreEmitPeephole.cpp
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1 //===--------- PPCPreEmitPeephole.cpp - Late peephole optimizations -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // A pre-emit peephole for catching opportunities introduced by late passes such
10 // as MachineBlockPlacement.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "PPC.h"
15 #include "PPCInstrInfo.h"
16 #include "PPCSubtarget.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/Statistic.h"
25 #include "llvm/MC/MCContext.h"
27 #include "llvm/Support/Debug.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "ppc-pre-emit-peephole"
32 
33 STATISTIC(NumRRConvertedInPreEmit,
34  "Number of r+r instructions converted to r+i in pre-emit peephole");
35 STATISTIC(NumRemovedInPreEmit,
36  "Number of instructions deleted in pre-emit peephole");
37 STATISTIC(NumberOfSelfCopies,
38  "Number of self copy instructions eliminated");
39 STATISTIC(NumFrameOffFoldInPreEmit,
40  "Number of folding frame offset by using r+r in pre-emit peephole");
41 
42 static cl::opt<bool>
43 EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true),
44  cl::desc("enable PC Relative linker optimization"));
45 
46 static cl::opt<bool>
47 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
48  cl::desc("Run pre-emit peephole optimizations."));
49 
50 static cl::opt<uint64_t>
51 DSCRValue("ppc-set-dscr", cl::Hidden,
52  cl::desc("Set the Data Stream Control Register."));
53 
54 namespace {
55 
56 static bool hasPCRelativeForm(MachineInstr &Use) {
57  switch (Use.getOpcode()) {
58  default:
59  return false;
60  case PPC::LBZ:
61  case PPC::LBZ8:
62  case PPC::LHA:
63  case PPC::LHA8:
64  case PPC::LHZ:
65  case PPC::LHZ8:
66  case PPC::LWZ:
67  case PPC::LWZ8:
68  case PPC::STB:
69  case PPC::STB8:
70  case PPC::STH:
71  case PPC::STH8:
72  case PPC::STW:
73  case PPC::STW8:
74  case PPC::LD:
75  case PPC::STD:
76  case PPC::LWA:
77  case PPC::LXSD:
78  case PPC::LXSSP:
79  case PPC::LXV:
80  case PPC::STXSD:
81  case PPC::STXSSP:
82  case PPC::STXV:
83  case PPC::LFD:
84  case PPC::LFS:
85  case PPC::STFD:
86  case PPC::STFS:
87  case PPC::DFLOADf32:
88  case PPC::DFLOADf64:
89  case PPC::DFSTOREf32:
90  case PPC::DFSTOREf64:
91  return true;
92  }
93 }
94 
95  class PPCPreEmitPeephole : public MachineFunctionPass {
96  public:
97  static char ID;
98  PPCPreEmitPeephole() : MachineFunctionPass(ID) {
100  }
101 
102  void getAnalysisUsage(AnalysisUsage &AU) const override {
104  }
105 
106  MachineFunctionProperties getRequiredProperties() const override {
109  }
110 
111  // This function removes any redundant load immediates. It has two level
112  // loops - The outer loop finds the load immediates BBI that could be used
113  // to replace following redundancy. The inner loop scans instructions that
114  // after BBI to find redundancy and update kill/dead flags accordingly. If
115  // AfterBBI is the same as BBI, it is redundant, otherwise any instructions
116  // that modify the def register of BBI would break the scanning.
117  // DeadOrKillToUnset is a pointer to the previous operand that had the
118  // kill/dead flag set. It keeps track of the def register of BBI, the use
119  // registers of AfterBBIs and the def registers of AfterBBIs.
120  bool removeRedundantLIs(MachineBasicBlock &MBB,
121  const TargetRegisterInfo *TRI) {
122  LLVM_DEBUG(dbgs() << "Remove redundant load immediates from MBB:\n";
123  MBB.dump(); dbgs() << "\n");
124 
125  DenseSet<MachineInstr *> InstrsToErase;
126  for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
127  // Skip load immediate that is marked to be erased later because it
128  // cannot be used to replace any other instructions.
129  if (InstrsToErase.contains(&*BBI))
130  continue;
131  // Skip non-load immediate.
132  unsigned Opc = BBI->getOpcode();
133  if (Opc != PPC::LI && Opc != PPC::LI8 && Opc != PPC::LIS &&
134  Opc != PPC::LIS8)
135  continue;
136  // Skip load immediate, where the operand is a relocation (e.g., $r3 =
137  // LI target-flags(ppc-lo) %const.0).
138  if (!BBI->getOperand(1).isImm())
139  continue;
140  assert(BBI->getOperand(0).isReg() &&
141  "Expected a register for the first operand");
142 
143  LLVM_DEBUG(dbgs() << "Scanning after load immediate: "; BBI->dump(););
144 
145  Register Reg = BBI->getOperand(0).getReg();
146  int64_t Imm = BBI->getOperand(1).getImm();
147  MachineOperand *DeadOrKillToUnset = nullptr;
148  if (BBI->getOperand(0).isDead()) {
149  DeadOrKillToUnset = &BBI->getOperand(0);
150  LLVM_DEBUG(dbgs() << " Kill flag of " << *DeadOrKillToUnset
151  << " from load immediate " << *BBI
152  << " is a unsetting candidate\n");
153  }
154  // This loop scans instructions after BBI to see if there is any
155  // redundant load immediate.
156  for (auto AfterBBI = std::next(BBI); AfterBBI != MBB.instr_end();
157  ++AfterBBI) {
158  // Track the operand that kill Reg. We would unset the kill flag of
159  // the operand if there is a following redundant load immediate.
160  int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI);
161 
162  // We can't just clear implicit kills, so if we encounter one, stop
163  // looking further.
164  if (KillIdx != -1 && AfterBBI->getOperand(KillIdx).isImplicit()) {
165  LLVM_DEBUG(dbgs()
166  << "Encountered an implicit kill, cannot proceed: ");
167  LLVM_DEBUG(AfterBBI->dump());
168  break;
169  }
170 
171  if (KillIdx != -1) {
172  assert(!DeadOrKillToUnset && "Shouldn't kill same register twice");
173  DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
174  LLVM_DEBUG(dbgs()
175  << " Kill flag of " << *DeadOrKillToUnset << " from "
176  << *AfterBBI << " is a unsetting candidate\n");
177  }
178 
179  if (!AfterBBI->modifiesRegister(Reg, TRI))
180  continue;
181  // Finish scanning because Reg is overwritten by a non-load
182  // instruction.
183  if (AfterBBI->getOpcode() != Opc)
184  break;
185  assert(AfterBBI->getOperand(0).isReg() &&
186  "Expected a register for the first operand");
187  // Finish scanning because Reg is overwritten by a relocation or a
188  // different value.
189  if (!AfterBBI->getOperand(1).isImm() ||
190  AfterBBI->getOperand(1).getImm() != Imm)
191  break;
192 
193  // It loads same immediate value to the same Reg, which is redundant.
194  // We would unset kill flag in previous Reg usage to extend live range
195  // of Reg first, then remove the redundancy.
196  if (DeadOrKillToUnset) {
197  LLVM_DEBUG(dbgs()
198  << " Unset dead/kill flag of " << *DeadOrKillToUnset
199  << " from " << *DeadOrKillToUnset->getParent());
200  if (DeadOrKillToUnset->isDef())
201  DeadOrKillToUnset->setIsDead(false);
202  else
203  DeadOrKillToUnset->setIsKill(false);
204  }
205  DeadOrKillToUnset =
206  AfterBBI->findRegisterDefOperand(Reg, true, true, TRI);
207  if (DeadOrKillToUnset)
208  LLVM_DEBUG(dbgs()
209  << " Dead flag of " << *DeadOrKillToUnset << " from "
210  << *AfterBBI << " is a unsetting candidate\n");
211  InstrsToErase.insert(&*AfterBBI);
212  LLVM_DEBUG(dbgs() << " Remove redundant load immediate: ";
213  AfterBBI->dump());
214  }
215  }
216 
217  for (MachineInstr *MI : InstrsToErase) {
218  MI->eraseFromParent();
219  }
220  NumRemovedInPreEmit += InstrsToErase.size();
221  return !InstrsToErase.empty();
222  }
223 
224  // Check if this instruction is a PLDpc that is part of a GOT indirect
225  // access.
226  bool isGOTPLDpc(MachineInstr &Instr) {
227  if (Instr.getOpcode() != PPC::PLDpc)
228  return false;
229 
230  // The result must be a register.
231  const MachineOperand &LoadedAddressReg = Instr.getOperand(0);
232  if (!LoadedAddressReg.isReg())
233  return false;
234 
235  // Make sure that this is a global symbol.
236  const MachineOperand &SymbolOp = Instr.getOperand(1);
237  if (!SymbolOp.isGlobal())
238  return false;
239 
240  // Finally return true only if the GOT flag is present.
241  return (SymbolOp.getTargetFlags() & PPCII::MO_GOT_FLAG);
242  }
243 
244  bool addLinkerOpt(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) {
245  MachineFunction *MF = MBB.getParent();
246  // If the linker opt is disabled then just return.
248  return false;
249 
250  // Add this linker opt only if we are using PC Relative memops.
252  return false;
253 
254  // Struct to keep track of one def/use pair for a GOT indirect access.
255  struct GOTDefUsePair {
258  Register DefReg;
260  bool StillValid;
261  };
262  // Vector of def/ues pairs in this basic block.
265  bool MadeChange = false;
266 
267  // Run through all of the instructions in the basic block and try to
268  // collect potential pairs of GOT indirect access instructions.
269  for (auto BBI = MBB.instr_begin(); BBI != MBB.instr_end(); ++BBI) {
270  // Look for the initial GOT indirect load.
271  if (isGOTPLDpc(*BBI)) {
272  GOTDefUsePair CurrentPair{BBI, MachineBasicBlock::iterator(),
273  BBI->getOperand(0).getReg(),
274  PPC::NoRegister, true};
275  CandPairs.push_back(CurrentPair);
276  continue;
277  }
278 
279  // We haven't encountered any new PLD instructions, nothing to check.
280  if (CandPairs.empty())
281  continue;
282 
283  // Run through the candidate pairs and see if any of the registers
284  // defined in the PLD instructions are used by this instruction.
285  // Note: the size of CandPairs can change in the loop.
286  for (unsigned Idx = 0; Idx < CandPairs.size(); Idx++) {
287  GOTDefUsePair &Pair = CandPairs[Idx];
288  // The instruction does not use or modify this PLD's def reg,
289  // ignore it.
290  if (!BBI->readsRegister(Pair.DefReg, TRI) &&
291  !BBI->modifiesRegister(Pair.DefReg, TRI))
292  continue;
293 
294  // The use needs to be used in the address compuation and not
295  // as the register being stored for a store.
296  const MachineOperand *UseOp =
297  hasPCRelativeForm(*BBI) ? &BBI->getOperand(2) : nullptr;
298 
299  // Check for a valid use.
300  if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg &&
301  UseOp->isUse() && UseOp->isKill()) {
302  Pair.UseInst = BBI;
303  Pair.UseReg = BBI->getOperand(0).getReg();
304  ValidPairs.push_back(Pair);
305  }
306  CandPairs.erase(CandPairs.begin() + Idx);
307  }
308  }
309 
310  // Go through all of the pairs and check for any more valid uses.
311  for (auto Pair = ValidPairs.begin(); Pair != ValidPairs.end(); Pair++) {
312  // We shouldn't be here if we don't have a valid pair.
313  assert(Pair->UseInst.isValid() && Pair->StillValid &&
314  "Kept an invalid def/use pair for GOT PCRel opt");
315  // We have found a potential pair. Search through the instructions
316  // between the def and the use to see if it is valid to mark this as a
317  // linker opt.
318  MachineBasicBlock::iterator BBI = Pair->DefInst;
319  ++BBI;
320  for (; BBI != Pair->UseInst; ++BBI) {
321  if (BBI->readsRegister(Pair->UseReg, TRI) ||
322  BBI->modifiesRegister(Pair->UseReg, TRI)) {
323  Pair->StillValid = false;
324  break;
325  }
326  }
327 
328  if (!Pair->StillValid)
329  continue;
330 
331  // The load/store instruction that uses the address from the PLD will
332  // either use a register (for a store) or define a register (for the
333  // load). That register will be added as an implicit def to the PLD
334  // and as an implicit use on the second memory op. This is a precaution
335  // to prevent future passes from using that register between the two
336  // instructions.
337  MachineOperand ImplDef =
338  MachineOperand::CreateReg(Pair->UseReg, true, true);
339  MachineOperand ImplUse =
340  MachineOperand::CreateReg(Pair->UseReg, false, true);
341  Pair->DefInst->addOperand(ImplDef);
342  Pair->UseInst->addOperand(ImplUse);
343 
344  // Create the symbol.
345  MCContext &Context = MF->getContext();
346  MCSymbol *Symbol = Context.createNamedTempSymbol("pcrel");
347  MachineOperand PCRelLabel =
349  Pair->DefInst->addOperand(*MF, PCRelLabel);
350  Pair->UseInst->addOperand(*MF, PCRelLabel);
351  MadeChange |= true;
352  }
353  return MadeChange;
354  }
355 
356  // This function removes redundant pairs of accumulator prime/unprime
357  // instructions. In some situations, it's possible the compiler inserts an
358  // accumulator prime instruction followed by an unprime instruction (e.g.
359  // when we store an accumulator after restoring it from a spill). If the
360  // accumulator is not used between the two, they can be removed. This
361  // function removes these redundant pairs from basic blocks.
362  // The algorithm is quite straightforward - every time we encounter a prime
363  // instruction, the primed register is added to a candidate set. Any use
364  // other than a prime removes the candidate from the set and any de-prime
365  // of a current candidate marks both the prime and de-prime for removal.
366  // This way we ensure we only remove prime/de-prime *pairs* with no
367  // intervening uses.
368  bool removeAccPrimeUnprime(MachineBasicBlock &MBB) {
369  DenseSet<MachineInstr *> InstrsToErase;
370  // Initially, none of the acc registers are candidates.
372  PPC::UACCRCRegClass.getNumRegs(), nullptr);
373 
374  for (MachineInstr &BBI : MBB.instrs()) {
375  unsigned Opc = BBI.getOpcode();
376  // If we are visiting a xxmtacc instruction, we add it and its operand
377  // register to the candidate set.
378  if (Opc == PPC::XXMTACC) {
379  Register Acc = BBI.getOperand(0).getReg();
380  assert(PPC::ACCRCRegClass.contains(Acc) &&
381  "Unexpected register for XXMTACC");
382  Candidates[Acc - PPC::ACC0] = &BBI;
383  }
384  // If we are visiting a xxmfacc instruction and its operand register is
385  // in the candidate set, we mark the two instructions for removal.
386  else if (Opc == PPC::XXMFACC) {
387  Register Acc = BBI.getOperand(0).getReg();
388  assert(PPC::ACCRCRegClass.contains(Acc) &&
389  "Unexpected register for XXMFACC");
390  if (!Candidates[Acc - PPC::ACC0])
391  continue;
392  InstrsToErase.insert(&BBI);
393  InstrsToErase.insert(Candidates[Acc - PPC::ACC0]);
394  }
395  // If we are visiting an instruction using an accumulator register
396  // as operand, we remove it from the candidate set.
397  else {
398  for (MachineOperand &Operand : BBI.operands()) {
399  if (!Operand.isReg())
400  continue;
401  Register Reg = Operand.getReg();
402  if (PPC::ACCRCRegClass.contains(Reg))
403  Candidates[Reg - PPC::ACC0] = nullptr;
404  }
405  }
406  }
407 
408  for (MachineInstr *MI : InstrsToErase)
409  MI->eraseFromParent();
410  NumRemovedInPreEmit += InstrsToErase.size();
411  return !InstrsToErase.empty();
412  }
413 
414  bool runOnMachineFunction(MachineFunction &MF) override {
415  // If the user wants to set the DSCR using command-line options,
416  // load in the specified value at the start of main.
417  if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
419  DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
420  RegScavenger RS;
421  MachineBasicBlock &MBB = MF.front();
422  // Find an unused GPR according to register liveness
423  RS.enterBasicBlock(MBB);
424  unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass);
425  if (InDSCR) {
426  const PPCInstrInfo *TII =
427  MF.getSubtarget<PPCSubtarget>().getInstrInfo();
428  DebugLoc dl;
429  MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point
430  // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and
431  // ORI, then move to DSCR. If the requested DSCR value is contained
432  // in a 16-bit signed number, we can emit a single `LI`, but the
433  // impact of saving one instruction in one function does not warrant
434  // any additional complexity in the logic here.
435  BuildMI(MBB, IP, dl, TII->get(PPC::LIS), InDSCR)
436  .addImm(DSCRValue >> 16);
437  BuildMI(MBB, IP, dl, TII->get(PPC::ORI), InDSCR)
438  .addReg(InDSCR)
439  .addImm(DSCRValue & 0xFFFF);
440  BuildMI(MBB, IP, dl, TII->get(PPC::MTUDSCR))
441  .addReg(InDSCR, RegState::Kill);
442  } else
443  errs() << "Warning: Ran out of registers - Unable to set DSCR as "
444  "requested";
445  }
446 
447  if (skipFunction(MF.getFunction()) || !RunPreEmitPeephole) {
448  // Remove UNENCODED_NOP even when this pass is disabled.
449  // This needs to be done unconditionally so we don't emit zeros
450  // in the instruction stream.
451  SmallVector<MachineInstr *, 4> InstrsToErase;
452  for (MachineBasicBlock &MBB : MF)
453  for (MachineInstr &MI : MBB)
454  if (MI.getOpcode() == PPC::UNENCODED_NOP)
455  InstrsToErase.push_back(&MI);
456  for (MachineInstr *MI : InstrsToErase)
457  MI->eraseFromParent();
458  return false;
459  }
460  bool Changed = false;
461  const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
462  const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
463  SmallVector<MachineInstr *, 4> InstrsToErase;
464  for (MachineBasicBlock &MBB : MF) {
465  Changed |= removeRedundantLIs(MBB, TRI);
466  Changed |= addLinkerOpt(MBB, TRI);
467  Changed |= removeAccPrimeUnprime(MBB);
468  for (MachineInstr &MI : MBB) {
469  unsigned Opc = MI.getOpcode();
470  if (Opc == PPC::UNENCODED_NOP) {
471  InstrsToErase.push_back(&MI);
472  continue;
473  }
474  // Detect self copies - these can result from running AADB.
476  const MCInstrDesc &MCID = TII->get(Opc);
477  if (MCID.getNumOperands() == 3 &&
478  MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
479  MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
480  NumberOfSelfCopies++;
481  LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
482  LLVM_DEBUG(MI.dump());
483  InstrsToErase.push_back(&MI);
484  continue;
485  }
486  else if (MCID.getNumOperands() == 2 &&
487  MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
488  NumberOfSelfCopies++;
489  LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
490  LLVM_DEBUG(MI.dump());
491  InstrsToErase.push_back(&MI);
492  continue;
493  }
494  }
495  MachineInstr *DefMIToErase = nullptr;
496  if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
497  Changed = true;
498  NumRRConvertedInPreEmit++;
499  LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
500  LLVM_DEBUG(MI.dump());
501  if (DefMIToErase) {
502  InstrsToErase.push_back(DefMIToErase);
503  }
504  }
505  if (TII->foldFrameOffset(MI)) {
506  Changed = true;
507  NumFrameOffFoldInPreEmit++;
508  LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: ");
509  LLVM_DEBUG(MI.dump());
510  }
511  }
512 
513  // Eliminate conditional branch based on a constant CR bit by
514  // CRSET or CRUNSET. We eliminate the conditional branch or
515  // convert it into an unconditional branch. Also, if the CR bit
516  // is not used by other instructions, we eliminate CRSET as well.
517  auto I = MBB.getFirstInstrTerminator();
518  if (I == MBB.instr_end())
519  continue;
520  MachineInstr *Br = &*I;
521  if (Br->getOpcode() != PPC::BC && Br->getOpcode() != PPC::BCn)
522  continue;
523  MachineInstr *CRSetMI = nullptr;
524  Register CRBit = Br->getOperand(0).getReg();
525  unsigned CRReg = getCRFromCRBit(CRBit);
526  bool SeenUse = false;
528  for (It++; It != Er; It++) {
529  if (It->modifiesRegister(CRBit, TRI)) {
530  if ((It->getOpcode() == PPC::CRUNSET ||
531  It->getOpcode() == PPC::CRSET) &&
532  It->getOperand(0).getReg() == CRBit)
533  CRSetMI = &*It;
534  break;
535  }
536  if (It->readsRegister(CRBit, TRI))
537  SeenUse = true;
538  }
539  if (!CRSetMI) continue;
540 
541  unsigned CRSetOp = CRSetMI->getOpcode();
542  if ((Br->getOpcode() == PPC::BCn && CRSetOp == PPC::CRSET) ||
543  (Br->getOpcode() == PPC::BC && CRSetOp == PPC::CRUNSET)) {
544  // Remove this branch since it cannot be taken.
545  InstrsToErase.push_back(Br);
547  }
548  else {
549  // This conditional branch is always taken. So, remove all branches
550  // and insert an unconditional branch to the destination of this.
551  MachineBasicBlock::iterator It = Br, Er = MBB.end();
552  for (; It != Er; It++) {
553  if (It->isDebugInstr()) continue;
554  assert(It->isTerminator() && "Non-terminator after a terminator");
555  InstrsToErase.push_back(&*It);
556  }
557  if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) {
559  TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
560  NoCond, Br->getDebugLoc());
561  }
562  for (auto &Succ : MBB.successors())
563  if (Succ != Br->getOperand(1).getMBB()) {
564  MBB.removeSuccessor(Succ);
565  break;
566  }
567  }
568 
569  // If the CRBit is not used by another instruction, we can eliminate
570  // CRSET/CRUNSET instruction.
571  if (!SeenUse) {
572  // We need to check use of the CRBit in successors.
573  for (auto &SuccMBB : MBB.successors())
574  if (SuccMBB->isLiveIn(CRBit) || SuccMBB->isLiveIn(CRReg)) {
575  SeenUse = true;
576  break;
577  }
578  if (!SeenUse)
579  InstrsToErase.push_back(CRSetMI);
580  }
581  }
582  for (MachineInstr *MI : InstrsToErase) {
583  LLVM_DEBUG(dbgs() << "PPC pre-emit peephole: erasing instruction: ");
584  LLVM_DEBUG(MI->dump());
585  MI->eraseFromParent();
586  NumRemovedInPreEmit++;
587  }
588  return Changed;
589  }
590  };
591 }
592 
593 INITIALIZE_PASS(PPCPreEmitPeephole, DEBUG_TYPE, "PowerPC Pre-Emit Peephole",
594  false, false)
595 char PPCPreEmitPeephole::ID = 0;
596 
598  return new PPCPreEmitPeephole();
599 }
llvm::initializePPCPreEmitPeepholePass
void initializePPCPreEmitPeepholePass(PassRegistry &)
llvm::PPCII::MO_GOT_FLAG
@ MO_GOT_FLAG
MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.
Definition: PPC.h:116
llvm::getCRFromCRBit
static unsigned getCRFromCRBit(unsigned SrcReg)
Definition: PPCRegisterInfo.h:26
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SmallVectorImpl::erase
iterator erase(const_iterator CI)
Definition: SmallVector.h:724
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::GlobalValue::hasExternalLinkage
bool hasExternalLinkage() const
Definition: GlobalValue.h:433
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:592
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:272
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
contains
return AArch64::GPR64RegClass contains(Reg)
RunPreEmitPeephole
static cl::opt< bool > RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true), cl::desc("Run pre-emit peephole optimizations."))
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:509
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
MachineBasicBlock.h
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
DenseMap.h
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::RegScavenger::FindUnusedReg
Register FindUnusedReg(const TargetRegisterClass *RC) const
Find an unused register of the specified register class.
Definition: RegisterScavenging.cpp:266
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:291
DSCRValue
static cl::opt< uint64_t > DSCRValue("ppc-set-dscr", cl::Hidden, cl::desc("Set the Data Stream Control Register."))
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
PPCSubtarget.h
CommandLine.h
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:247
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:834
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
MCContext.h
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
IP
Definition: NVPTXLowerArgs.cpp:167
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:180
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:287
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:625
PPC.h
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::StringRef::equals
LLVM_NODISCARD bool equals(StringRef RHS) const
equals - Check for string equality, this is more efficient than compare() when the relative ordering ...
Definition: StringRef.h:187
llvm::PPCISD::XXMFACC
@ XXMFACC
XXMFACC = This corresponds to the xxmfacc instruction.
Definition: PPCISelLowering.h:488
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::cl::opt< bool >
llvm::PPCInstrInfo::isSameClassPhysRegCopy
static bool isSameClassPhysRegCopy(unsigned Opcode)
Definition: PPCInstrInfo.h:391
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:420
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
UseReg
static Register UseReg(const MachineOperand &MO)
Definition: HexagonCopyToCombine.cpp:254
PPCInstrInfo.h
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
DEBUG_TYPE
#define DEBUG_TYPE
Definition: PPCPreEmitPeephole.cpp:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:913
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:261
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:263
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::createPPCPreEmitPeepholePass
FunctionPass * createPPCPreEmitPeepholePass()
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:364
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
uint32_t
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:135
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:82
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:785
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:913
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:256
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::PPCII::MO_PCREL_OPT_FLAG
@ MO_PCREL_OPT_FLAG
Definition: PPC.h:120
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
EnablePCRelLinkerOpt
static cl::opt< bool > EnablePCRelLinkerOpt("ppc-pcrel-linker-opt", cl::Hidden, cl::init(true), cl::desc("enable PC Relative linker optimization"))
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:405
RegisterScavenging.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
LivePhysRegs.h