#include "SIFrameLowering.h"
#include "AMDGPU.h"
#include "AMDGPULaneMaskUtils.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "SIMachineFunctionInfo.h"
#include "SISpillUtils.h"
#include "llvm/BinaryFormat/Dwarf.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/LEB128.h"
#include "llvm/Target/TargetMachine.h"

Classes
class	llvm::PrologEpilogSGPRSpillBuilder

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE "frame-info"

Functions
static MCRegister	findUnusedRegister (MachineRegisterInfo &MRI, const LiveRegUnits &LiveUnits, const TargetRegisterClass &RC)
static void	encodeDwarfRegisterLocation (int DwarfReg, raw_ostream &OS)
static MCCFIInstruction	createScaledCFAInPrivateWave (const GCNSubtarget &ST, MCRegister DwarfStackPtrReg)
static MCRegister	findScratchNonCalleeSaveRegister (MachineRegisterInfo &MRI, LiveRegUnits &LiveUnits, const TargetRegisterClass &RC, bool Unused=false)
static void	getVGPRSpillLaneOrTempRegister (MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR, const TargetRegisterClass &RC=AMDGPU::SReg_32_XM0_XEXECRegClass, bool IncludeScratchCopy=true)
	Query target location for spilling SGPRs `IncludeScratchCopy` : Also look for free scratch SGPRs.
static void	buildPrologSpill (const GCNSubtarget &ST, const SIRegisterInfo &TRI, const SIMachineFunctionInfo &FuncInfo, LiveRegUnits &LiveUnits, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SpillReg, int FI, Register FrameReg, int64_t DwordOff=0)
static void	buildEpilogRestore (const GCNSubtarget &ST, const SIRegisterInfo &TRI, const SIMachineFunctionInfo &FuncInfo, LiveRegUnits &LiveUnits, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SpillReg, int FI, Register FrameReg, int64_t DwordOff=0)
static void	buildGitPtr (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, const SIInstrInfo *TII, Register TargetReg)
static void	initLiveUnits (LiveRegUnits &LiveUnits, const SIRegisterInfo &TRI, const SIMachineFunctionInfo *FuncInfo, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsProlog)
static bool	allStackObjectsAreDead (const MachineFrameInfo &MFI)
static unsigned	getScratchScaleFactor (const GCNSubtarget &ST)
static Register	buildScratchExecCopy (LiveRegUnits &LiveUnits, MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool IsProlog, bool EnableInactiveLanes)
static bool	allSGPRSpillsAreDead (const MachineFunction &MF)
static void	assignSlotsUsingVGPRBlocks (MachineFunction &MF, const GCNSubtarget &ST, std::vector< CalleeSavedInfo > &CSI)
static SparseBitVector	buildLiveInRoots (const MachineBasicBlock &MBB, const SIRegisterInfo &TRI)
	Return the set of all root registers of regunits live-in to `MBB`.
static bool	isAnyRootLiveIn (const SparseBitVector<> &LiveInRoots, const SIRegisterInfo &TRI, MCRegister Reg)
	Returns true iff any root of `Reg` is in `LiveInRoots` (see `buildLiveInRoots`).
static bool	frameTriviallyRequiresSP (const MachineFrameInfo &MFI)
	Returns true if the frame will require a reference to the stack pointer.

Variables
static cl::opt< bool >	EnableSpillVGPRToAGPR ("amdgpu-spill-vgpr-to-agpr", cl::desc("Enable spilling VGPRs to AGPRs"), cl::ReallyHidden, cl::init(true))
static constexpr unsigned	SGPRBitSize = 32
static constexpr unsigned	SGPRByteSize = SGPRBitSize / 8
static constexpr unsigned	VGPRLaneBitSize = 32

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "frame-info"

Definition at line 26 of file SIFrameLowering.cpp.

Function Documentation

◆ allSGPRSpillsAreDead()

bool allSGPRSpillsAreDead ( const MachineFunction & MF )

static

Definition at line 1683 of file SIFrameLowering.cpp.

References llvm::SIMachineFunctionInfo::checkIndexInPrologEpilogSGPRSpills(), E(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectIndexEnd(), llvm::MachineFrameInfo::getStackID(), I, llvm::MachineFrameInfo::isDeadObjectIndex(), and llvm::TargetStackID::SGPRSpill.

Referenced by llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ allStackObjectsAreDead()

bool allStackObjectsAreDead ( const MachineFrameInfo & MFI )

static

Definition at line 678 of file SIFrameLowering.cpp.

References E(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectIndexEnd(), I, and llvm::MachineFrameInfo::isDeadObjectIndex().

Referenced by llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), and llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ assignSlotsUsingVGPRBlocks()

void assignSlotsUsingVGPRBlocks	(	MachineFunction &	MF,
		const GCNSubtarget &	ST,
		std::vector< CalleeSavedInfo > &	CSI )

static

Definition at line 2082 of file SIFrameLowering.cpp.

References A(), llvm::alignDown(), assert(), B(), BlockSize, llvm::countl_zero(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::CalleeSavedInfo::getReg(), llvm::is_sorted(), llvm::SIMachineFunctionInfo::isWWMReservedRegister(), Reg, llvm::SIMachineFunctionInfo::setMaskForVGPRBlockOps(), and TRI.

Referenced by llvm::SIFrameLowering::assignCalleeSavedSpillSlots().

◆ buildEpilogRestore()

void buildEpilogRestore	(	const GCNSubtarget &	ST,
		const SIRegisterInfo &	TRI,
		const SIMachineFunctionInfo &	FuncInfo,
		LiveRegUnits &	LiveUnits,
		MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	SpillReg,
		int	FI,
		Register	FrameReg,
		int64_t	DwordOff = 0 )

static

Definition at line 232 of file SIFrameLowering.cpp.

References DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), I, MBB, llvm::MachineMemOperand::MOLoad, Opc, and TRI.

Referenced by llvm::SIFrameLowering::emitCSRSpillRestores().

◆ buildGitPtr()

void buildGitPtr	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		const SIInstrInfo *	TII,
		Register	TargetReg )

static

Definition at line 252 of file SIFrameLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineRegisterInfo::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::SIMachineFunctionInfo::getGITPtrHigh(), llvm::SIMachineFunctionInfo::getGITPtrLoReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), I, llvm::ImplicitDefine, MBB, TII, and TRI.

◆ buildLiveInRoots()

SparseBitVector buildLiveInRoots	(	const MachineBasicBlock &	MBB,
		const SIRegisterInfo &	TRI )

static

Return the set of all root registers of regunits live-in to MBB.

Intended to avoid using the expensive MCRegAliasIterator when deciding if a register to be spilled is already live-in (see isAnyRootLiveIn).

Definition at line 2249 of file SIFrameLowering.cpp.

References llvm::MCRegUnitRootIterator::isValid(), MBB, MI, llvm::SparseBitVector< ElementSize >::set(), and TRI.

Referenced by llvm::SIFrameLowering::spillCalleeSavedRegisters().

◆ buildPrologSpill()

void buildPrologSpill	(	const GCNSubtarget &	ST,
		const SIRegisterInfo &	TRI,
		const SIMachineFunctionInfo &	FuncInfo,
		LiveRegUnits &	LiveUnits,
		MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	SpillReg,
		int	FI,
		Register	FrameReg,
		int64_t	DwordOff = 0 )

static

Definition at line 209 of file SIFrameLowering.cpp.

References llvm::LiveRegUnits::addReg(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), I, MBB, llvm::MachineMemOperand::MOStore, Opc, llvm::LiveRegUnits::removeReg(), and TRI.

Referenced by llvm::SIFrameLowering::emitCSRSpillStores().

◆ buildScratchExecCopy()

Register buildScratchExecCopy	(	LiveRegUnits &	LiveUnits,
		MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		bool	IsProlog,
		bool	EnableInactiveLanes )

static

◆ createScaledCFAInPrivateWave()

MCCFIInstruction createScaledCFAInPrivateWave	(	const GCNSubtarget &	ST,
		MCRegister	DwarfStackPtrReg )

static

Definition at line 65 of file SIFrameLowering.cpp.

References assert(), llvm::Block, llvm::MCCFIInstruction::createEscape(), encodeDwarfRegisterLocation(), llvm::encodeULEB128(), SGPRByteSize, and llvm::raw_svector_ostream::str().

◆ encodeDwarfRegisterLocation()

void encodeDwarfRegisterLocation	(	int	DwarfReg,
		raw_ostream &	OS )

static

Definition at line 54 of file SIFrameLowering.cpp.

References assert(), and llvm::encodeULEB128().

Referenced by createScaledCFAInPrivateWave().

◆ findScratchNonCalleeSaveRegister()

MCRegister findScratchNonCalleeSaveRegister	(	MachineRegisterInfo &	MRI,
		LiveRegUnits &	LiveUnits,
		const TargetRegisterClass &	RC,
		bool	Unused = false )

static

Definition at line 124 of file SIFrameLowering.cpp.

References llvm::LiveRegUnits::addReg(), llvm::LiveRegUnits::available(), findUnusedRegister(), llvm::MachineRegisterInfo::getCalleeSavedRegs(), llvm::MachineRegisterInfo::isReserved(), and Reg.

Referenced by buildScratchExecCopy(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ findUnusedRegister()

MCRegister findUnusedRegister	(	MachineRegisterInfo &	MRI,
		const LiveRegUnits &	LiveUnits,
		const TargetRegisterClass &	RC )

static

Definition at line 43 of file SIFrameLowering.cpp.

References llvm::LiveRegUnits::available(), llvm::MachineRegisterInfo::isPhysRegUsed(), llvm::MachineRegisterInfo::isReserved(), and Reg.

Referenced by llvm::SIFrameLowering::determinePrologEpilogSGPRSaves(), findScratchNonCalleeSaveRegister(), and getVGPRSpillLaneOrTempRegister().

◆ frameTriviallyRequiresSP()

bool frameTriviallyRequiresSP ( const MachineFrameInfo & MFI )

static

Returns true if the frame will require a reference to the stack pointer.

This is the set of conditions common to setting up the stack pointer in a kernel, and for using a frame pointer in a callable function.

FIXME: Should also check hasOpaqueSPAdjustment and if any inline asm references SP.

Definition at line 2464 of file SIFrameLowering.cpp.

References llvm::MachineFrameInfo::hasPatchPoint(), llvm::MachineFrameInfo::hasStackMap(), and llvm::MachineFrameInfo::hasVarSizedObjects().

Referenced by llvm::SIFrameLowering::hasFPImpl(), and llvm::SIFrameLowering::requiresStackPointerReference().

◆ getScratchScaleFactor()

unsigned getScratchScaleFactor ( const GCNSubtarget & ST )

static

Definition at line 742 of file SIFrameLowering.cpp.

Referenced by llvm::SIFrameLowering::eliminateCallFramePseudoInstr(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), and llvm::SIFrameLowering::emitPrologue().

◆ getVGPRSpillLaneOrTempRegister()

void getVGPRSpillLaneOrTempRegister	(	MachineFunction &	MF,
		LiveRegUnits &	LiveUnits,
		Register	SGPR,
		const TargetRegisterClass &	RC = AMDGPU::SReg_32_XM0_XEXECRegClass,
		bool	IncludeScratchCopy = true )

static

Query target location for spilling SGPRs IncludeScratchCopy : Also look for free scratch SGPRs.

Definition at line 147 of file SIFrameLowering.cpp.

References llvm::LiveRegUnits::addReg(), llvm::SIMachineFunctionInfo::addToPrologEpilogSGPRSpills(), llvm::SIMachineFunctionInfo::allocateSGPRSpillToVGPRLane(), llvm::COPY_TO_SCRATCH_SGPR, llvm::dbgs(), findUnusedRegister(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getSGPRSpillToPhysicalVGPRLanes(), llvm::MachineFunction::getSubtarget(), LLVM_DEBUG, llvm::printReg(), llvm::MachineFrameInfo::RemoveStackObject(), llvm::TargetStackID::SGPRSpill, Size, llvm::SPILL_TO_MEM, llvm::SPILL_TO_VGPR_LANE, and TRI.

Referenced by llvm::SIFrameLowering::determinePrologEpilogSGPRSaves().

◆ initLiveUnits()

void initLiveUnits	(	LiveRegUnits &	LiveUnits,
		const SIRegisterInfo &	TRI,
		const SIMachineFunctionInfo *	FuncInfo,
		MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		bool	IsProlog )

static

Definition at line 277 of file SIFrameLowering.cpp.

References llvm::LiveRegUnits::addLiveIns(), llvm::LiveRegUnits::addLiveOuts(), llvm::LiveRegUnits::empty(), llvm::LiveRegUnits::init(), MBB, MBBI, llvm::LiveRegUnits::stepBackward(), and TRI.

Referenced by buildScratchExecCopy(), llvm::SIFrameLowering::emitEpilogue(), and llvm::SIFrameLowering::emitPrologue().

◆ isAnyRootLiveIn()

bool isAnyRootLiveIn	(	const SparseBitVector<> &	LiveInRoots,
		const SIRegisterInfo &	TRI,
		MCRegister	Reg )

static

Returns true iff any root of Reg is in LiveInRoots (see buildLiveInRoots).

Definition at line 2266 of file SIFrameLowering.cpp.

References llvm::MCRegUnitIterator::isValid(), llvm::MCRegUnitRootIterator::isValid(), Reg, llvm::SparseBitVector< ElementSize >::test(), and TRI.

Variable Documentation

◆ EnableSpillVGPRToAGPR

cl::opt< bool > EnableSpillVGPRToAGPR("amdgpu-spill-vgpr-to-agpr", cl::desc("Enable spilling VGPRs to AGPRs"), cl::ReallyHidden, cl::init(true))	(	"amdgpu-spill-vgpr-to-agpr"	,
		cl::desc("Enable spilling VGPRs to AGPRs")	,
		cl::ReallyHidden	,
		cl::init(true)	)

static

Referenced by llvm::SIFrameLowering::emitPrologue(), and llvm::SIFrameLowering::processFunctionBeforeFrameFinalized().

◆ SGPRBitSize

unsigned SGPRBitSize = 32

staticconstexpr

Definition at line 34 of file SIFrameLowering.cpp.

Referenced by llvm::SIFrameLowering::buildCFIForRegToSGPRPairSpill().

◆ SGPRByteSize

unsigned SGPRByteSize = SGPRBitSize / 8

staticconstexpr

Definition at line 35 of file SIFrameLowering.cpp.

Referenced by createScaledCFAInPrivateWave().

◆ VGPRLaneBitSize

unsigned VGPRLaneBitSize = 32

staticconstexpr

Definition at line 36 of file SIFrameLowering.cpp.

Referenced by llvm::SIFrameLowering::buildCFIForSGPRToVGPRSpill(), llvm::SIFrameLowering::buildCFIForSGPRToVGPRSpill(), llvm::SIFrameLowering::buildCFIForVGPRToVMEMSpill(), and llvm::SIFrameLowering::buildCFIForVRegToVRegSpill().

Classes

Namespaces

Macros

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ allSGPRSpillsAreDead()

◆ allStackObjectsAreDead()

◆ assignSlotsUsingVGPRBlocks()

◆ buildEpilogRestore()

◆ buildGitPtr()

◆ buildLiveInRoots()

◆ buildPrologSpill()

◆ buildScratchExecCopy()

◆ createScaledCFAInPrivateWave()

◆ encodeDwarfRegisterLocation()

◆ findScratchNonCalleeSaveRegister()

◆ findUnusedRegister()

◆ frameTriviallyRequiresSP()

◆ getScratchScaleFactor()

◆ getVGPRSpillLaneOrTempRegister()

◆ initLiveUnits()

◆ isAnyRootLiveIn()

Variable Documentation

◆ EnableSpillVGPRToAGPR

◆ SGPRBitSize

◆ SGPRByteSize

◆ VGPRLaneBitSize