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HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
10 // into a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonISelLowering.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/DiagnosticInfo.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/IntrinsicsHexagon.h"
47 #include "llvm/IR/IRBuilder.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/IR/Value.h"
51 #include "llvm/MC/MCRegisterInfo.h"
52 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/CodeGen.h"
55 #include "llvm/Support/Debug.h"
60 #include <algorithm>
61 #include <cassert>
62 #include <cstddef>
63 #include <cstdint>
64 #include <limits>
65 #include <utility>
66 
67 using namespace llvm;
68 
69 #define DEBUG_TYPE "hexagon-lowering"
70 
71 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
72  cl::init(true), cl::Hidden,
73  cl::desc("Control jump table emission on Hexagon target"));
74 
75 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
77  cl::desc("Enable Hexagon SDNode scheduling"));
78 
79 static cl::opt<bool> EnableFastMath("ffast-math",
81  cl::desc("Enable Fast Math processing"));
82 
83 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
85  cl::desc("Set minimum jump tables"));
86 
87 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
89  cl::desc("Max #stores to inline memcpy"));
90 
91 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
93  cl::desc("Max #stores to inline memcpy"));
94 
95 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
97  cl::desc("Max #stores to inline memmove"));
98 
99 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
101  cl::desc("Max #stores to inline memmove"));
102 
103 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
105  cl::desc("Max #stores to inline memset"));
106 
107 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
109  cl::desc("Max #stores to inline memset"));
110 
111 static cl::opt<bool> AlignLoads("hexagon-align-loads",
112  cl::Hidden, cl::init(false),
113  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
114 
115 static cl::opt<bool>
116  DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden,
117  cl::init(false),
118  cl::desc("Disable minimum alignment of 1 for "
119  "arguments passed by value on stack"));
120 
121 namespace {
122 
123  class HexagonCCState : public CCState {
124  unsigned NumNamedVarArgParams = 0;
125 
126  public:
127  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
129  unsigned NumNamedArgs)
130  : CCState(CC, IsVarArg, MF, locs, C),
131  NumNamedVarArgParams(NumNamedArgs) {}
132  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
133  };
134 
135 } // end anonymous namespace
136 
137 
138 // Implement calling convention for Hexagon.
139 
140 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
141  CCValAssign::LocInfo &LocInfo,
142  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
143  static const MCPhysReg ArgRegs[] = {
144  Hexagon::R0, Hexagon::R1, Hexagon::R2,
145  Hexagon::R3, Hexagon::R4, Hexagon::R5
146  };
147  const unsigned NumArgRegs = array_lengthof(ArgRegs);
148  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
149 
150  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
151  if (RegNum != NumArgRegs && RegNum % 2 == 1)
152  State.AllocateReg(ArgRegs[RegNum]);
153 
154  // Always return false here, as this function only makes sure that the first
155  // unallocated register has an even register number and does not actually
156  // allocate a register for the current argument.
157  return false;
158 }
159 
160 #include "HexagonGenCallingConv.inc"
161 
162 
163 SDValue
165  const {
166  return SDValue();
167 }
168 
169 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
170 /// by "Src" to address "Dst" of size "Size". Alignment information is
171 /// specified by the specific parameter attribute. The copy will be passed as
172 /// a byval function parameter. Sometimes what we are copying is the end of a
173 /// larger object, the part that does not fit in registers.
175  SDValue Chain, ISD::ArgFlagsTy Flags,
176  SelectionDAG &DAG, const SDLoc &dl) {
177  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
178  return DAG.getMemcpy(
179  Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
180  /*isVolatile=*/false, /*AlwaysInline=*/false,
181  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
182 }
183 
184 bool
186  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
188  LLVMContext &Context) const {
190  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
191 
193  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
194  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
195 }
196 
197 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
198 // passed by value, the function prototype is modified to return void and
199 // the value is stored in memory pointed by a pointer passed by caller.
200 SDValue
202  bool IsVarArg,
204  const SmallVectorImpl<SDValue> &OutVals,
205  const SDLoc &dl, SelectionDAG &DAG) const {
206  // CCValAssign - represent the assignment of the return value to locations.
208 
209  // CCState - Info about the registers and stack slot.
210  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
211  *DAG.getContext());
212 
213  // Analyze return values of ISD::RET
214  if (Subtarget.useHVXOps())
215  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
216  else
217  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
218 
219  SDValue Flag;
220  SmallVector<SDValue, 4> RetOps(1, Chain);
221 
222  // Copy the result values into the output registers.
223  for (unsigned i = 0; i != RVLocs.size(); ++i) {
224  CCValAssign &VA = RVLocs[i];
225  SDValue Val = OutVals[i];
226 
227  switch (VA.getLocInfo()) {
228  default:
229  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
230  llvm_unreachable("Unknown loc info!");
231  case CCValAssign::Full:
232  break;
233  case CCValAssign::BCvt:
234  Val = DAG.getBitcast(VA.getLocVT(), Val);
235  break;
236  case CCValAssign::SExt:
237  Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
238  break;
239  case CCValAssign::ZExt:
240  Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
241  break;
242  case CCValAssign::AExt:
243  Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
244  break;
245  }
246 
247  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag);
248 
249  // Guarantee that all emitted copies are stuck together with flags.
250  Flag = Chain.getValue(1);
251  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
252  }
253 
254  RetOps[0] = Chain; // Update chain.
255 
256  // Add the flag if we have it.
257  if (Flag.getNode())
258  RetOps.push_back(Flag);
259 
260  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
261 }
262 
264  // If either no tail call or told not to tail call at all, don't.
265  return CI->isTailCall();
266 }
267 
269  const char* RegName, LLT VT, const MachineFunction &) const {
270  // Just support r19, the linux kernel uses it.
272  .Case("r0", Hexagon::R0)
273  .Case("r1", Hexagon::R1)
274  .Case("r2", Hexagon::R2)
275  .Case("r3", Hexagon::R3)
276  .Case("r4", Hexagon::R4)
277  .Case("r5", Hexagon::R5)
278  .Case("r6", Hexagon::R6)
279  .Case("r7", Hexagon::R7)
280  .Case("r8", Hexagon::R8)
281  .Case("r9", Hexagon::R9)
282  .Case("r10", Hexagon::R10)
283  .Case("r11", Hexagon::R11)
284  .Case("r12", Hexagon::R12)
285  .Case("r13", Hexagon::R13)
286  .Case("r14", Hexagon::R14)
287  .Case("r15", Hexagon::R15)
288  .Case("r16", Hexagon::R16)
289  .Case("r17", Hexagon::R17)
290  .Case("r18", Hexagon::R18)
291  .Case("r19", Hexagon::R19)
292  .Case("r20", Hexagon::R20)
293  .Case("r21", Hexagon::R21)
294  .Case("r22", Hexagon::R22)
295  .Case("r23", Hexagon::R23)
296  .Case("r24", Hexagon::R24)
297  .Case("r25", Hexagon::R25)
298  .Case("r26", Hexagon::R26)
299  .Case("r27", Hexagon::R27)
300  .Case("r28", Hexagon::R28)
301  .Case("r29", Hexagon::R29)
302  .Case("r30", Hexagon::R30)
303  .Case("r31", Hexagon::R31)
304  .Case("r1:0", Hexagon::D0)
305  .Case("r3:2", Hexagon::D1)
306  .Case("r5:4", Hexagon::D2)
307  .Case("r7:6", Hexagon::D3)
308  .Case("r9:8", Hexagon::D4)
309  .Case("r11:10", Hexagon::D5)
310  .Case("r13:12", Hexagon::D6)
311  .Case("r15:14", Hexagon::D7)
312  .Case("r17:16", Hexagon::D8)
313  .Case("r19:18", Hexagon::D9)
314  .Case("r21:20", Hexagon::D10)
315  .Case("r23:22", Hexagon::D11)
316  .Case("r25:24", Hexagon::D12)
317  .Case("r27:26", Hexagon::D13)
318  .Case("r29:28", Hexagon::D14)
319  .Case("r31:30", Hexagon::D15)
320  .Case("sp", Hexagon::R29)
321  .Case("fp", Hexagon::R30)
322  .Case("lr", Hexagon::R31)
323  .Case("p0", Hexagon::P0)
324  .Case("p1", Hexagon::P1)
325  .Case("p2", Hexagon::P2)
326  .Case("p3", Hexagon::P3)
327  .Case("sa0", Hexagon::SA0)
328  .Case("lc0", Hexagon::LC0)
329  .Case("sa1", Hexagon::SA1)
330  .Case("lc1", Hexagon::LC1)
331  .Case("m0", Hexagon::M0)
332  .Case("m1", Hexagon::M1)
333  .Case("usr", Hexagon::USR)
334  .Case("ugp", Hexagon::UGP)
335  .Case("cs0", Hexagon::CS0)
336  .Case("cs1", Hexagon::CS1)
337  .Default(Register());
338  if (Reg)
339  return Reg;
340 
341  report_fatal_error("Invalid register name global variable");
342 }
343 
344 /// LowerCallResult - Lower the result values of an ISD::CALL into the
345 /// appropriate copies out of appropriate physical registers. This assumes that
346 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
347 /// being lowered. Returns a SDNode with the same number of values as the
348 /// ISD::CALL.
350  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
351  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
353  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
354  // Assign locations to each value returned by this call.
356 
357  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
358  *DAG.getContext());
359 
360  if (Subtarget.useHVXOps())
361  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
362  else
363  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
364 
365  // Copy all of the result registers out of their specified physreg.
366  for (unsigned i = 0; i != RVLocs.size(); ++i) {
367  SDValue RetVal;
368  if (RVLocs[i].getValVT() == MVT::i1) {
369  // Return values of type MVT::i1 require special handling. The reason
370  // is that MVT::i1 is associated with the PredRegs register class, but
371  // values of that type are still returned in R0. Generate an explicit
372  // copy into a predicate register from R0, and treat the value of the
373  // predicate register as the call result.
374  auto &MRI = DAG.getMachineFunction().getRegInfo();
375  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
376  MVT::i32, Glue);
377  // FR0 = (Value, Chain, Glue)
378  Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
379  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
380  FR0.getValue(0), FR0.getValue(2));
381  // TPR = (Chain, Glue)
382  // Don't glue this CopyFromReg, because it copies from a virtual
383  // register. If it is glued to the call, InstrEmitter will add it
384  // as an implicit def to the call (EmitMachineNode).
385  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
386  Glue = TPR.getValue(1);
387  Chain = TPR.getValue(0);
388  } else {
389  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
390  RVLocs[i].getValVT(), Glue);
391  Glue = RetVal.getValue(2);
392  Chain = RetVal.getValue(1);
393  }
394  InVals.push_back(RetVal.getValue(0));
395  }
396 
397  return Chain;
398 }
399 
400 /// LowerCall - Functions arguments are copied from virtual regs to
401 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
402 SDValue
404  SmallVectorImpl<SDValue> &InVals) const {
405  SelectionDAG &DAG = CLI.DAG;
406  SDLoc &dl = CLI.DL;
408  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
410  SDValue Chain = CLI.Chain;
411  SDValue Callee = CLI.Callee;
412  CallingConv::ID CallConv = CLI.CallConv;
413  bool IsVarArg = CLI.IsVarArg;
414  bool DoesNotReturn = CLI.DoesNotReturn;
415 
416  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
418  MachineFrameInfo &MFI = MF.getFrameInfo();
419  auto PtrVT = getPointerTy(MF.getDataLayout());
420 
421  unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0;
422  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
423  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
424 
425  // Linux ABI treats var-arg calls the same way as regular ones.
426  bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
427 
428  // Analyze operands of the call, assigning locations to each operand.
430  HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(),
431  NumParams);
432 
433  if (Subtarget.useHVXOps())
434  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
435  else if (DisableArgsMinAlignment)
436  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_Legacy);
437  else
438  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
439 
440  if (CLI.IsTailCall) {
441  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
443  IsVarArg, IsStructRet, StructAttrFlag, Outs,
444  OutVals, Ins, DAG);
445  for (const CCValAssign &VA : ArgLocs) {
446  if (VA.isMemLoc()) {
447  CLI.IsTailCall = false;
448  break;
449  }
450  }
451  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
452  : "Argument must be passed on stack. "
453  "Not eligible for Tail Call\n"));
454  }
455  // Get a count of how many bytes are to be pushed on the stack.
456  unsigned NumBytes = CCInfo.getNextStackOffset();
458  SmallVector<SDValue, 8> MemOpChains;
459 
460  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
461  SDValue StackPtr =
462  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
463 
464  bool NeedsArgAlign = false;
465  Align LargestAlignSeen;
466  // Walk the register/memloc assignments, inserting copies/loads.
467  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
468  CCValAssign &VA = ArgLocs[i];
469  SDValue Arg = OutVals[i];
470  ISD::ArgFlagsTy Flags = Outs[i].Flags;
471  // Record if we need > 8 byte alignment on an argument.
472  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
473  NeedsArgAlign |= ArgAlign;
474 
475  // Promote the value if needed.
476  switch (VA.getLocInfo()) {
477  default:
478  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
479  llvm_unreachable("Unknown loc info!");
480  case CCValAssign::Full:
481  break;
482  case CCValAssign::BCvt:
483  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
484  break;
485  case CCValAssign::SExt:
486  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
487  break;
488  case CCValAssign::ZExt:
489  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
490  break;
491  case CCValAssign::AExt:
492  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
493  break;
494  }
495 
496  if (VA.isMemLoc()) {
497  unsigned LocMemOffset = VA.getLocMemOffset();
498  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
499  StackPtr.getValueType());
500  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
501  if (ArgAlign)
502  LargestAlignSeen = std::max(
503  LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8));
504  if (Flags.isByVal()) {
505  // The argument is a struct passed by value. According to LLVM, "Arg"
506  // is a pointer.
507  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
508  Flags, DAG, dl));
509  } else {
511  DAG.getMachineFunction(), LocMemOffset);
512  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
513  MemOpChains.push_back(S);
514  }
515  continue;
516  }
517 
518  // Arguments that can be passed on register must be kept at RegsToPass
519  // vector.
520  if (VA.isRegLoc())
521  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
522  }
523 
524  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
525  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
526  Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
527  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
528  MFI.ensureMaxAlignment(LargestAlignSeen);
529  }
530  // Transform all store nodes into one single node because all store
531  // nodes are independent of each other.
532  if (!MemOpChains.empty())
533  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
534 
535  SDValue Glue;
536  if (!CLI.IsTailCall) {
537  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
538  Glue = Chain.getValue(1);
539  }
540 
541  // Build a sequence of copy-to-reg nodes chained together with token
542  // chain and flag operands which copy the outgoing args into registers.
543  // The Glue is necessary since all emitted instructions must be
544  // stuck together.
545  if (!CLI.IsTailCall) {
546  for (const auto &R : RegsToPass) {
547  Chain = DAG.getCopyToReg(Chain, dl, R.first, R.second, Glue);
548  Glue = Chain.getValue(1);
549  }
550  } else {
551  // For tail calls lower the arguments to the 'real' stack slot.
552  //
553  // Force all the incoming stack arguments to be loaded from the stack
554  // before any new outgoing arguments are stored to the stack, because the
555  // outgoing stack slots may alias the incoming argument stack slots, and
556  // the alias isn't otherwise explicit. This is slightly more conservative
557  // than necessary, because it means that each store effectively depends
558  // on every argument instead of just those arguments it would clobber.
559  //
560  // Do not flag preceding copytoreg stuff together with the following stuff.
561  Glue = SDValue();
562  for (const auto &R : RegsToPass) {
563  Chain = DAG.getCopyToReg(Chain, dl, R.first, R.second, Glue);
564  Glue = Chain.getValue(1);
565  }
566  Glue = SDValue();
567  }
568 
569  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
570  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
571 
572  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
573  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
574  // node so that legalize doesn't hack it.
575  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
576  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
577  } else if (ExternalSymbolSDNode *S =
578  dyn_cast<ExternalSymbolSDNode>(Callee)) {
579  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
580  }
581 
582  // Returns a chain & a flag for retval copy to use.
583  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
585  Ops.push_back(Chain);
586  Ops.push_back(Callee);
587 
588  // Add argument registers to the end of the list so that they are
589  // known live into the call.
590  for (const auto &R : RegsToPass)
591  Ops.push_back(DAG.getRegister(R.first, R.second.getValueType()));
592 
593  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
594  assert(Mask && "Missing call preserved mask for calling convention");
595  Ops.push_back(DAG.getRegisterMask(Mask));
596 
597  if (Glue.getNode())
598  Ops.push_back(Glue);
599 
600  if (CLI.IsTailCall) {
601  MFI.setHasTailCall();
602  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
603  }
604 
605  // Set this here because we need to know this for "hasFP" in frame lowering.
606  // The target-independent code calls getFrameRegister before setting it, and
607  // getFrameRegister uses hasFP to determine whether the function has FP.
608  MFI.setHasCalls(true);
609 
610  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
611  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
612  Glue = Chain.getValue(1);
613 
614  // Create the CALLSEQ_END node.
615  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
616  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
617  Glue = Chain.getValue(1);
618 
619  // Handle result values, copying them out of physregs into vregs that we
620  // return.
621  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
622  InVals, OutVals, Callee);
623 }
624 
625 /// Returns true by value, base pointer and offset pointer and addressing
626 /// mode by reference if this node can be combined with a load / store to
627 /// form a post-indexed load / store.
629  SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM,
630  SelectionDAG &DAG) const {
631  LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
632  if (!LSN)
633  return false;
634  EVT VT = LSN->getMemoryVT();
635  if (!VT.isSimple())
636  return false;
637  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
638  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
639  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
640  VT == MVT::v4i16 || VT == MVT::v8i8 ||
641  Subtarget.isHVXVectorType(VT.getSimpleVT());
642  if (!IsLegalType)
643  return false;
644 
645  if (Op->getOpcode() != ISD::ADD)
646  return false;
647  Base = Op->getOperand(0);
648  Offset = Op->getOperand(1);
649  if (!isa<ConstantSDNode>(Offset.getNode()))
650  return false;
651  AM = ISD::POST_INC;
652 
653  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
654  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
655 }
656 
657 SDValue
660  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
661  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
662  unsigned LR = HRI.getRARegister();
663 
664  if ((Op.getOpcode() != ISD::INLINEASM &&
665  Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
666  return Op;
667 
668  unsigned NumOps = Op.getNumOperands();
669  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
670  --NumOps; // Ignore the flag operand.
671 
672  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
673  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
674  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
675  ++i; // Skip the ID value.
676 
677  switch (InlineAsm::getKind(Flags)) {
678  default:
679  llvm_unreachable("Bad flags!");
681  case InlineAsm::Kind_Imm:
682  case InlineAsm::Kind_Mem:
683  i += NumVals;
684  break;
688  for (; NumVals; --NumVals, ++i) {
689  Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
690  if (Reg != LR)
691  continue;
692  HMFI.setHasClobberLR(true);
693  return Op;
694  }
695  break;
696  }
697  }
698  }
699 
700  return Op;
701 }
702 
703 // Need to transform ISD::PREFETCH into something that doesn't inherit
704 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
705 // SDNPMayStore.
707  SelectionDAG &DAG) const {
708  SDValue Chain = Op.getOperand(0);
709  SDValue Addr = Op.getOperand(1);
710  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
711  // if the "reg" is fed by an "add".
712  SDLoc DL(Op);
713  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
714  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
715 }
716 
717 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
718 // is marked as having side-effects, while the register read on Hexagon does
719 // not have any. TableGen refuses to accept the direct pattern from that node
720 // to the A4_tfrcpp.
722  SelectionDAG &DAG) const {
723  SDValue Chain = Op.getOperand(0);
724  SDLoc dl(Op);
726  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
727 }
728 
730  SelectionDAG &DAG) const {
731  SDValue Chain = Op.getOperand(0);
732  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
733  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
734  if (IntNo == Intrinsic::hexagon_prefetch) {
735  SDValue Addr = Op.getOperand(2);
736  SDLoc DL(Op);
737  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
738  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
739  }
740  return SDValue();
741 }
742 
743 SDValue
745  SelectionDAG &DAG) const {
746  SDValue Chain = Op.getOperand(0);
747  SDValue Size = Op.getOperand(1);
748  SDValue Align = Op.getOperand(2);
749  SDLoc dl(Op);
750 
751  ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
752  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
753 
754  unsigned A = AlignConst->getSExtValue();
755  auto &HFI = *Subtarget.getFrameLowering();
756  // "Zero" means natural stack alignment.
757  if (A == 0)
758  A = HFI.getStackAlign().value();
759 
760  LLVM_DEBUG({
761  dbgs () << __func__ << " Align: " << A << " Size: ";
762  Size.getNode()->dump(&DAG);
763  dbgs() << "\n";
764  });
765 
766  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
768  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
769 
771  return AA;
772 }
773 
775  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
776  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
777  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
779  MachineFrameInfo &MFI = MF.getFrameInfo();
781 
782  // Linux ABI treats var-arg calls the same way as regular ones.
783  bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
784 
785  // Assign locations to all of the incoming arguments.
787  HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs,
788  *DAG.getContext(),
790 
791  if (Subtarget.useHVXOps())
792  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
793  else if (DisableArgsMinAlignment)
794  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy);
795  else
796  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
797 
798  // For LLVM, in the case when returning a struct by value (>8byte),
799  // the first argument is a pointer that points to the location on caller's
800  // stack where the return value will be stored. For Hexagon, the location on
801  // caller's stack is passed only when the struct size is smaller than (and
802  // equal to) 8 bytes. If not, no address will be passed into callee and
803  // callee return the result direclty through R0/R1.
804  auto NextSingleReg = [] (const TargetRegisterClass &RC, unsigned Reg) {
805  switch (RC.getID()) {
806  case Hexagon::IntRegsRegClassID:
807  return Reg - Hexagon::R0 + 1;
808  case Hexagon::DoubleRegsRegClassID:
809  return (Reg - Hexagon::D0 + 1) * 2;
810  case Hexagon::HvxVRRegClassID:
811  return Reg - Hexagon::V0 + 1;
812  case Hexagon::HvxWRRegClassID:
813  return (Reg - Hexagon::W0 + 1) * 2;
814  }
815  llvm_unreachable("Unexpected register class");
816  };
817 
818  auto &HFL = const_cast<HexagonFrameLowering&>(*Subtarget.getFrameLowering());
819  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
820  HFL.FirstVarArgSavedReg = 0;
822 
823  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
824  CCValAssign &VA = ArgLocs[i];
825  ISD::ArgFlagsTy Flags = Ins[i].Flags;
826  bool ByVal = Flags.isByVal();
827 
828  // Arguments passed in registers:
829  // 1. 32- and 64-bit values and HVX vectors are passed directly,
830  // 2. Large structs are passed via an address, and the address is
831  // passed in a register.
832  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
833  llvm_unreachable("ByValSize must be bigger than 8 bytes");
834 
835  bool InReg = VA.isRegLoc() &&
836  (!ByVal || (ByVal && Flags.getByValSize() > 8));
837 
838  if (InReg) {
839  MVT RegVT = VA.getLocVT();
840  if (VA.getLocInfo() == CCValAssign::BCvt)
841  RegVT = VA.getValVT();
842 
843  const TargetRegisterClass *RC = getRegClassFor(RegVT);
845  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
846 
847  // Treat values of type MVT::i1 specially: they are passed in
848  // registers of type i32, but they need to remain as values of
849  // type i1 for consistency of the argument lowering.
850  if (VA.getValVT() == MVT::i1) {
851  assert(RegVT.getSizeInBits() <= 32);
852  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
853  Copy, DAG.getConstant(1, dl, RegVT));
854  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
855  ISD::SETNE);
856  } else {
857 #ifndef NDEBUG
858  unsigned RegSize = RegVT.getSizeInBits();
859  assert(RegSize == 32 || RegSize == 64 ||
860  Subtarget.isHVXVectorType(RegVT));
861 #endif
862  }
863  InVals.push_back(Copy);
864  MRI.addLiveIn(VA.getLocReg(), VReg);
865  HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg());
866  } else {
867  assert(VA.isMemLoc() && "Argument should be passed in memory");
868 
869  // If it's a byval parameter, then we need to compute the
870  // "real" size, not the size of the pointer.
871  unsigned ObjSize = Flags.isByVal()
872  ? Flags.getByValSize()
873  : VA.getLocVT().getStoreSizeInBits() / 8;
874 
875  // Create the frame index object for this incoming parameter.
876  int Offset = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
877  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
878  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
879 
880  if (Flags.isByVal()) {
881  // If it's a pass-by-value aggregate, then do not dereference the stack
882  // location. Instead, we should generate a reference to the stack
883  // location.
884  InVals.push_back(FIN);
885  } else {
886  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
888  InVals.push_back(L);
889  }
890  }
891  }
892 
893  if (IsVarArg && Subtarget.isEnvironmentMusl()) {
894  for (int i = HFL.FirstVarArgSavedReg; i < 6; i++)
895  MRI.addLiveIn(Hexagon::R0+i);
896  }
897 
898  if (IsVarArg && Subtarget.isEnvironmentMusl()) {
899  HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
900  HMFI.setLastNamedArgFrameIndex(-int(MFI.getNumFixedObjects()));
901 
902  // Create Frame index for the start of register saved area.
903  int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
904  bool RequiresPadding = (NumVarArgRegs & 1);
905  int RegSaveAreaSizePlusPadding = RequiresPadding
906  ? (NumVarArgRegs + 1) * 4
907  : NumVarArgRegs * 4;
908 
909  if (RegSaveAreaSizePlusPadding > 0) {
910  // The offset to saved register area should be 8 byte aligned.
911  int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
912  if (!(RegAreaStart % 8))
913  RegAreaStart = (RegAreaStart + 7) & -8;
914 
915  int RegSaveAreaFrameIndex =
916  MFI.CreateFixedObject(RegSaveAreaSizePlusPadding, RegAreaStart, true);
917  HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex);
918 
919  // This will point to the next argument passed via stack.
920  int Offset = RegAreaStart + RegSaveAreaSizePlusPadding;
921  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
922  HMFI.setVarArgsFrameIndex(FI);
923  } else {
924  // This will point to the next argument passed via stack, when
925  // there is no saved register area.
926  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
927  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
928  HMFI.setRegSavedAreaStartFrameIndex(FI);
929  HMFI.setVarArgsFrameIndex(FI);
930  }
931  }
932 
933 
934  if (IsVarArg && !Subtarget.isEnvironmentMusl()) {
935  // This will point to the next argument passed via stack.
936  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
937  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
938  HMFI.setVarArgsFrameIndex(FI);
939  }
940 
941  return Chain;
942 }
943 
944 SDValue
946  // VASTART stores the address of the VarArgsFrameIndex slot into the
947  // memory location argument.
951  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
952 
953  if (!Subtarget.isEnvironmentMusl()) {
954  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
955  MachinePointerInfo(SV));
956  }
957  auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
958  auto &HFL = *Subtarget.getFrameLowering();
959  SDLoc DL(Op);
961 
962  // Get frame index of va_list.
963  SDValue FIN = Op.getOperand(1);
964 
965  // If first Vararg register is odd, add 4 bytes to start of
966  // saved register area to point to the first register location.
967  // This is because the saved register area has to be 8 byte aligned.
968  // Incase of an odd start register, there will be 4 bytes of padding in
969  // the beginning of saved register area. If all registers area used up,
970  // the following condition will handle it correctly.
971  SDValue SavedRegAreaStartFrameIndex =
972  DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32);
973 
974  auto PtrVT = getPointerTy(DAG.getDataLayout());
975 
976  if (HFL.FirstVarArgSavedReg & 1)
977  SavedRegAreaStartFrameIndex =
978  DAG.getNode(ISD::ADD, DL, PtrVT,
979  DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(),
980  MVT::i32),
981  DAG.getIntPtrConstant(4, DL));
982 
983  // Store the saved register area start pointer.
984  SDValue Store =
985  DAG.getStore(Op.getOperand(0), DL,
986  SavedRegAreaStartFrameIndex,
987  FIN, MachinePointerInfo(SV));
988  MemOps.push_back(Store);
989 
990  // Store saved register area end pointer.
991  FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
992  FIN, DAG.getIntPtrConstant(4, DL));
993  Store = DAG.getStore(Op.getOperand(0), DL,
994  DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
995  PtrVT),
996  FIN, MachinePointerInfo(SV, 4));
997  MemOps.push_back(Store);
998 
999  // Store overflow area pointer.
1000  FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
1001  FIN, DAG.getIntPtrConstant(4, DL));
1002  Store = DAG.getStore(Op.getOperand(0), DL,
1003  DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
1004  PtrVT),
1005  FIN, MachinePointerInfo(SV, 8));
1006  MemOps.push_back(Store);
1007 
1008  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1009 }
1010 
1011 SDValue
1013  // Assert that the linux ABI is enabled for the current compilation.
1014  assert(Subtarget.isEnvironmentMusl() && "Linux ABI should be enabled");
1015  SDValue Chain = Op.getOperand(0);
1016  SDValue DestPtr = Op.getOperand(1);
1017  SDValue SrcPtr = Op.getOperand(2);
1018  const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1019  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1020  SDLoc DL(Op);
1021  // Size of the va_list is 12 bytes as it has 3 pointers. Therefore,
1022  // we need to memcopy 12 bytes from va_list to another similar list.
1023  return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr,
1024  DAG.getIntPtrConstant(12, DL), Align(4),
1025  /*isVolatile*/ false, false, false,
1026  MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
1027 }
1028 
1030  const SDLoc &dl(Op);
1031  SDValue LHS = Op.getOperand(0);
1032  SDValue RHS = Op.getOperand(1);
1033  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1034  MVT ResTy = ty(Op);
1035  MVT OpTy = ty(LHS);
1036 
1037  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1038  MVT ElemTy = OpTy.getVectorElementType();
1039  assert(ElemTy.isScalarInteger());
1040  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1041  OpTy.getVectorNumElements());
1042  return DAG.getSetCC(dl, ResTy,
1043  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
1044  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
1045  }
1046 
1047  // Treat all other vector types as legal.
1048  if (ResTy.isVector())
1049  return Op;
1050 
1051  // Comparisons of short integers should use sign-extend, not zero-extend,
1052  // since we can represent small negative values in the compare instructions.
1053  // The LLVM default is to use zero-extend arbitrarily in these cases.
1054  auto isSExtFree = [this](SDValue N) {
1055  switch (N.getOpcode()) {
1056  case ISD::TRUNCATE: {
1057  // A sign-extend of a truncate of a sign-extend is free.
1058  SDValue Op = N.getOperand(0);
1059  if (Op.getOpcode() != ISD::AssertSext)
1060  return false;
1061  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
1062  unsigned ThisBW = ty(N).getSizeInBits();
1063  unsigned OrigBW = OrigTy.getSizeInBits();
1064  // The type that was sign-extended to get the AssertSext must be
1065  // narrower than the type of N (so that N has still the same value
1066  // as the original).
1067  return ThisBW >= OrigBW;
1068  }
1069  case ISD::LOAD:
1070  // We have sign-extended loads.
1071  return true;
1072  }
1073  return false;
1074  };
1075 
1076  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1077  ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1078  bool IsNegative = C && C->getAPIntValue().isNegative();
1079  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
1080  return DAG.getSetCC(dl, ResTy,
1082  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
1083  }
1084 
1085  return SDValue();
1086 }
1087 
1088 SDValue
1090  SDValue PredOp = Op.getOperand(0);
1091  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1092  MVT OpTy = ty(Op1);
1093  const SDLoc &dl(Op);
1094 
1095  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1096  MVT ElemTy = OpTy.getVectorElementType();
1097  assert(ElemTy.isScalarInteger());
1098  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1099  OpTy.getVectorNumElements());
1100  // Generate (trunc (select (_, sext, sext))).
1101  return DAG.getSExtOrTrunc(
1102  DAG.getSelect(dl, WideTy, PredOp,
1103  DAG.getSExtOrTrunc(Op1, dl, WideTy),
1104  DAG.getSExtOrTrunc(Op2, dl, WideTy)),
1105  dl, OpTy);
1106  }
1107 
1108  return SDValue();
1109 }
1110 
1111 SDValue
1113  EVT ValTy = Op.getValueType();
1114  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1115  Constant *CVal = nullptr;
1116  bool isVTi1Type = false;
1117  if (auto *CV = dyn_cast<ConstantVector>(CPN->getConstVal())) {
1118  if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) {
1119  IRBuilder<> IRB(CV->getContext());
1120  SmallVector<Constant*, 128> NewConst;
1121  unsigned VecLen = CV->getNumOperands();
1122  assert(isPowerOf2_32(VecLen) &&
1123  "conversion only supported for pow2 VectorSize");
1124  for (unsigned i = 0; i < VecLen; ++i)
1125  NewConst.push_back(IRB.getInt8(CV->getOperand(i)->isZeroValue()));
1126 
1127  CVal = ConstantVector::get(NewConst);
1128  isVTi1Type = true;
1129  }
1130  }
1131  Align Alignment = CPN->getAlign();
1132  bool IsPositionIndependent = isPositionIndependent();
1133  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1134 
1135  unsigned Offset = 0;
1136  SDValue T;
1137  if (CPN->isMachineConstantPoolEntry())
1138  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Alignment,
1139  Offset, TF);
1140  else if (isVTi1Type)
1141  T = DAG.getTargetConstantPool(CVal, ValTy, Alignment, Offset, TF);
1142  else
1143  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Alignment, Offset,
1144  TF);
1145 
1146  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1147  "Inconsistent target flag encountered");
1148 
1149  if (IsPositionIndependent)
1150  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1151  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1152 }
1153 
1154 SDValue
1156  EVT VT = Op.getValueType();
1157  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1158  if (isPositionIndependent()) {
1160  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1161  }
1162 
1163  SDValue T = DAG.getTargetJumpTable(Idx, VT);
1164  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1165 }
1166 
1167 SDValue
1169  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1170  MachineFunction &MF = DAG.getMachineFunction();
1171  MachineFrameInfo &MFI = MF.getFrameInfo();
1172  MFI.setReturnAddressIsTaken(true);
1173 
1175  return SDValue();
1176 
1177  EVT VT = Op.getValueType();
1178  SDLoc dl(Op);
1179  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1180  if (Depth) {
1181  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1182  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1183  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1184  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1185  MachinePointerInfo());
1186  }
1187 
1188  // Return LR, which contains the return address. Mark it an implicit live-in.
1190  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1191 }
1192 
1193 SDValue
1195  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1197  MFI.setFrameAddressIsTaken(true);
1198 
1199  EVT VT = Op.getValueType();
1200  SDLoc dl(Op);
1201  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1202  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1203  HRI.getFrameRegister(), VT);
1204  while (Depth--)
1205  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1206  MachinePointerInfo());
1207  return FrameAddr;
1208 }
1209 
1210 SDValue
1212  SDLoc dl(Op);
1213  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1214 }
1215 
1216 SDValue
1218  SDLoc dl(Op);
1219  auto *GAN = cast<GlobalAddressSDNode>(Op);
1220  auto PtrVT = getPointerTy(DAG.getDataLayout());
1221  auto *GV = GAN->getGlobal();
1222  int64_t Offset = GAN->getOffset();
1223 
1224  auto &HLOF = *HTM.getObjFileLowering();
1226 
1227  if (RM == Reloc::Static) {
1228  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1229  const GlobalObject *GO = GV->getAliaseeObject();
1230  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1231  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1232  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1233  }
1234 
1235  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1236  if (UsePCRel) {
1237  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1239  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1240  }
1241 
1242  // Use GOT index.
1243  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1244  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1245  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1246  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1247 }
1248 
1249 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1250 SDValue
1252  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1253  SDLoc dl(Op);
1254  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1255 
1257  if (RM == Reloc::Static) {
1258  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1259  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1260  }
1261 
1262  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1263  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1264 }
1265 
1266 SDValue
1268  const {
1269  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1272  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1273 }
1274 
1275 SDValue
1277  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1278  unsigned char OperandFlags) const {
1279  MachineFunction &MF = DAG.getMachineFunction();
1280  MachineFrameInfo &MFI = MF.getFrameInfo();
1281  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1282  SDLoc dl(GA);
1283  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1284  GA->getValueType(0),
1285  GA->getOffset(),
1286  OperandFlags);
1287  // Create Operands for the call.The Operands should have the following:
1288  // 1. Chain SDValue
1289  // 2. Callee which in this case is the Global address value.
1290  // 3. Registers live into the call.In this case its R0, as we
1291  // have just one argument to be passed.
1292  // 4. Glue.
1293  // Note: The order is important.
1294 
1295  const auto &HRI = *Subtarget.getRegisterInfo();
1296  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1297  assert(Mask && "Missing call preserved mask for calling convention");
1298  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1299  DAG.getRegisterMask(Mask), Glue };
1300  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1301 
1302  // Inform MFI that function has calls.
1303  MFI.setAdjustsStack(true);
1304 
1305  Glue = Chain.getValue(1);
1306  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1307 }
1308 
1309 //
1310 // Lower using the intial executable model for TLS addresses
1311 //
1312 SDValue
1314  SelectionDAG &DAG) const {
1315  SDLoc dl(GA);
1316  int64_t Offset = GA->getOffset();
1317  auto PtrVT = getPointerTy(DAG.getDataLayout());
1318 
1319  // Get the thread pointer.
1320  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1321 
1322  bool IsPositionIndependent = isPositionIndependent();
1323  unsigned char TF =
1324  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1325 
1326  // First generate the TLS symbol address
1327  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1328  Offset, TF);
1329 
1330  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1331 
1332  if (IsPositionIndependent) {
1333  // Generate the GOT pointer in case of position independent code
1334  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1335 
1336  // Add the TLS Symbol address to GOT pointer.This gives
1337  // GOT relative relocation for the symbol.
1338  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1339  }
1340 
1341  // Load the offset value for TLS symbol.This offset is relative to
1342  // thread pointer.
1343  SDValue LoadOffset =
1344  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1345 
1346  // Address of the thread local variable is the add of thread
1347  // pointer and the offset of the variable.
1348  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1349 }
1350 
1351 //
1352 // Lower using the local executable model for TLS addresses
1353 //
1354 SDValue
1356  SelectionDAG &DAG) const {
1357  SDLoc dl(GA);
1358  int64_t Offset = GA->getOffset();
1359  auto PtrVT = getPointerTy(DAG.getDataLayout());
1360 
1361  // Get the thread pointer.
1362  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1363  // Generate the TLS symbol address
1364  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1366  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1367 
1368  // Address of the thread local variable is the add of thread
1369  // pointer and the offset of the variable.
1370  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1371 }
1372 
1373 //
1374 // Lower using the general dynamic model for TLS addresses
1375 //
1376 SDValue
1378  SelectionDAG &DAG) const {
1379  SDLoc dl(GA);
1380  int64_t Offset = GA->getOffset();
1381  auto PtrVT = getPointerTy(DAG.getDataLayout());
1382 
1383  // First generate the TLS symbol address
1384  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1386 
1387  // Then, generate the GOT pointer
1388  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1389 
1390  // Add the TLS symbol and the GOT pointer
1391  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1392  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1393 
1394  // Copy over the argument to R0
1395  SDValue InFlag;
1396  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1397  InFlag = Chain.getValue(1);
1398 
1399  unsigned Flags =
1400  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1403 
1404  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1405  Hexagon::R0, Flags);
1406 }
1407 
1408 //
1409 // Lower TLS addresses.
1410 //
1411 // For now for dynamic models, we only support the general dynamic model.
1412 //
1413 SDValue
1415  SelectionDAG &DAG) const {
1416  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1417 
1418  switch (HTM.getTLSModel(GA->getGlobal())) {
1421  return LowerToTLSGeneralDynamicModel(GA, DAG);
1422  case TLSModel::InitialExec:
1423  return LowerToTLSInitialExecModel(GA, DAG);
1424  case TLSModel::LocalExec:
1425  return LowerToTLSLocalExecModel(GA, DAG);
1426  }
1427  llvm_unreachable("Bogus TLS model");
1428 }
1429 
1430 //===----------------------------------------------------------------------===//
1431 // TargetLowering Implementation
1432 //===----------------------------------------------------------------------===//
1433 
1435  const HexagonSubtarget &ST)
1436  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1437  Subtarget(ST) {
1438  auto &HRI = *Subtarget.getRegisterInfo();
1439 
1443  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1446 
1449 
1452  else
1454 
1455  // Limits for inline expansion of memcpy/memmove
1462 
1463  //
1464  // Set up register classes.
1465  //
1466 
1467  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1468  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1469  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1470  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1471  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1472  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1473  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1474  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1475  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1476  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1477  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1478 
1479  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1480  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1481 
1482  //
1483  // Handling of scalar operations.
1484  //
1485  // All operations default to "legal", except:
1486  // - indexed loads and stores (pre-/post-incremented),
1487  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1488  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1489  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1490  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1491  // which default to "expand" for at least one type.
1492 
1493  // Misc operations.
1510 
1511  // Custom legalize GlobalAddress nodes into CONST32.
1515 
1516  // Hexagon needs to optimize cases with negative constants.
1521 
1522  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1526  if (Subtarget.isEnvironmentMusl())
1528  else
1530 
1534 
1535  if (EmitJumpTables)
1537  else
1540 
1541  for (unsigned LegalIntOp :
1543  setOperationAction(LegalIntOp, MVT::i32, Legal);
1544  setOperationAction(LegalIntOp, MVT::i64, Legal);
1545  }
1546 
1547  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1548  // but they only operate on i64.
1549  for (MVT VT : MVT::integer_valuetypes()) {
1556  }
1559 
1564 
1565  // Popcount can count # of 1s in i64 but returns i32.
1570 
1575 
1580 
1581  for (unsigned IntExpOp :
1586  for (MVT VT : MVT::integer_valuetypes())
1587  setOperationAction(IntExpOp, VT, Expand);
1588  }
1589 
1590  for (unsigned FPExpOp :
1593  for (MVT VT : MVT::fp_valuetypes())
1594  setOperationAction(FPExpOp, VT, Expand);
1595  }
1596 
1597  // No extending loads from i32.
1598  for (MVT VT : MVT::integer_valuetypes()) {
1602  }
1603  // Turn FP truncstore into trunc + store.
1605  // Turn FP extload into load/fpextend.
1606  for (MVT VT : MVT::fp_valuetypes())
1608 
1609  // Expand BR_CC and SELECT_CC for all integer and fp types.
1610  for (MVT VT : MVT::integer_valuetypes()) {
1613  }
1614  for (MVT VT : MVT::fp_valuetypes()) {
1617  }
1619 
1620  //
1621  // Handling of vector operations.
1622  //
1623 
1624  // Set the action for vector operations to "expand", then override it with
1625  // either "custom" or "legal" for specific cases.
1626  static const unsigned VectExpOps[] = {
1627  // Integer arithmetic:
1631  // Logical/bit:
1634  // Floating point arithmetic/math functions:
1641  // Misc:
1643  // Vector:
1649  };
1650 
1651  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1652  for (unsigned VectExpOp : VectExpOps)
1653  setOperationAction(VectExpOp, VT, Expand);
1654 
1655  // Expand all extending loads and truncating stores:
1656  for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
1657  if (TargetVT == VT)
1658  continue;
1659  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1660  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1661  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1662  setTruncStoreAction(VT, TargetVT, Expand);
1663  }
1664 
1665  // Normalize all inputs to SELECT to be vectors of i32.
1666  if (VT.getVectorElementType() != MVT::i32) {
1667  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1669  AddPromotedToType(ISD::SELECT, VT, VT32);
1670  }
1674  }
1675 
1676  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1677  // are legal.
1684 
1688 
1689  // Types natively supported:
1690  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1698 
1699  setOperationAction(ISD::ADD, NativeVT, Legal);
1700  setOperationAction(ISD::SUB, NativeVT, Legal);
1701  setOperationAction(ISD::MUL, NativeVT, Legal);
1702  setOperationAction(ISD::AND, NativeVT, Legal);
1703  setOperationAction(ISD::OR, NativeVT, Legal);
1704  setOperationAction(ISD::XOR, NativeVT, Legal);
1705 
1706  if (NativeVT.getVectorElementType() != MVT::i1)
1708  }
1709 
1710  for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1715  }
1716 
1717  // Custom lower unaligned loads.
1718  // Also, for both loads and stores, verify the alignment of the address
1719  // in case it is a compile-time constant. This is a usability feature to
1720  // provide a meaningful error message to users.
1725  }
1726 
1727  // Custom-lower load/stores of boolean vectors.
1728  for (MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1731  }
1732 
1734  MVT::v2i32}) {
1742  }
1743 
1744  // Custom-lower bitcasts from i8 to v8i1.
1752 
1753  // V5+.
1758 
1761 
1774 
1775  // Special handling for half-precision floating point conversions.
1776  // Lower half float conversions into library calls.
1781 
1786 
1787  // Handling of indexed loads/stores: default is "expand".
1788  //
1793  }
1794 
1795  // Subtarget-specific operation actions.
1796  //
1797  if (Subtarget.hasV60Ops()) {
1802  }
1803  if (Subtarget.hasV66Ops()) {
1806  }
1807  if (Subtarget.hasV67Ops()) {
1811  }
1812 
1814 
1815  if (Subtarget.useHVXOps())
1816  initializeHVXLowering();
1817 
1819 
1820  //
1821  // Library calls for unsupported operations
1822  //
1823  bool FastMath = EnableFastMath;
1824 
1825  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1826  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1827  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1828  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1829  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1830  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1831  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1832  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1833 
1834  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1835  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1836  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1837  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1838  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1839  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1840 
1841  // This is the only fast library function for sqrtd.
1842  if (FastMath)
1843  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1844 
1845  // Prefix is: nothing for "slow-math",
1846  // "fast2_" for V5+ fast-math double-precision
1847  // (actually, keep fast-math and fast-math2 separate for now)
1848  if (FastMath) {
1849  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1850  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1851  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1852  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1853  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1854  } else {
1855  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1856  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1857  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1858  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1859  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1860  }
1861 
1862  if (FastMath)
1863  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1864  else
1865  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1866 
1867  // Routines to handle fp16 storage type.
1868  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
1869  setLibcallName(RTLIB::FPROUND_F64_F16, "__truncdfhf2");
1870  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
1871 
1872  // These cause problems when the shift amount is non-constant.
1873  setLibcallName(RTLIB::SHL_I128, nullptr);
1874  setLibcallName(RTLIB::SRL_I128, nullptr);
1875  setLibcallName(RTLIB::SRA_I128, nullptr);
1876 }
1877 
1878 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1879  switch ((HexagonISD::NodeType)Opcode) {
1880  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1881  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1882  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1883  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1884  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1885  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1886  case HexagonISD::CALL: return "HexagonISD::CALL";
1887  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1888  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1889  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1890  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1891  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1892  case HexagonISD::CP: return "HexagonISD::CP";
1893  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1894  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1895  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1896  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1897  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1898  case HexagonISD::JT: return "HexagonISD::JT";
1899  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1900  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1901  case HexagonISD::VASL: return "HexagonISD::VASL";
1902  case HexagonISD::VASR: return "HexagonISD::VASR";
1903  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1904  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1905  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1906  case HexagonISD::VROR: return "HexagonISD::VROR";
1907  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1908  case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1909  case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1910  case HexagonISD::D2P: return "HexagonISD::D2P";
1911  case HexagonISD::P2D: return "HexagonISD::P2D";
1912  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1913  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1914  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1915  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1916  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1917  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1918  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1919  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1920  case HexagonISD::VPACKL: return "HexagonISD::VPACKL";
1921  case HexagonISD::VUNPACK: return "HexagonISD::VUNPACK";
1922  case HexagonISD::VUNPACKU: return "HexagonISD::VUNPACKU";
1923  case HexagonISD::ISEL: return "HexagonISD::ISEL";
1924  case HexagonISD::OP_END: break;
1925  }
1926  return nullptr;
1927 }
1928 
1929 bool
1930 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign,
1931  const SDLoc &dl, SelectionDAG &DAG) const {
1932  auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1933  if (!CA)
1934  return true;
1935  unsigned Addr = CA->getZExtValue();
1936  Align HaveAlign =
1937  Addr != 0 ? Align(1ull << countTrailingZeros(Addr)) : NeedAlign;
1938  if (HaveAlign >= NeedAlign)
1939  return true;
1940 
1941  static int DK_MisalignedTrap = llvm::getNextAvailablePluginDiagnosticKind();
1942 
1943  struct DiagnosticInfoMisalignedTrap : public DiagnosticInfo {
1944  DiagnosticInfoMisalignedTrap(StringRef M)
1945  : DiagnosticInfo(DK_MisalignedTrap, DS_Remark), Msg(M) {}
1946  void print(DiagnosticPrinter &DP) const override {
1947  DP << Msg;
1948  }
1949  static bool classof(const DiagnosticInfo *DI) {
1950  return DI->getKind() == DK_MisalignedTrap;
1951  }
1952  StringRef Msg;
1953  };
1954 
1955  std::string ErrMsg;
1956  raw_string_ostream O(ErrMsg);
1957  O << "Misaligned constant address: " << format_hex(Addr, 10)
1958  << " has alignment " << HaveAlign.value()
1959  << ", but the memory access requires " << NeedAlign.value();
1960  if (DebugLoc DL = dl.getDebugLoc())
1961  DL.print(O << ", at ");
1962  O << ". The instruction has been replaced with a trap.";
1963 
1964  DAG.getContext()->diagnose(DiagnosticInfoMisalignedTrap(O.str()));
1965  return false;
1966 }
1967 
1968 SDValue
1969 HexagonTargetLowering::replaceMemWithUndef(SDValue Op, SelectionDAG &DAG)
1970  const {
1971  const SDLoc &dl(Op);
1972  auto *LS = cast<LSBaseSDNode>(Op.getNode());
1973  assert(!LS->isIndexed() && "Not expecting indexed ops on constant address");
1974 
1975  SDValue Chain = LS->getChain();
1976  SDValue Trap = DAG.getNode(ISD::TRAP, dl, MVT::Other, Chain);
1977  if (LS->getOpcode() == ISD::LOAD)
1978  return DAG.getMergeValues({DAG.getUNDEF(ty(Op)), Trap}, dl);
1979  return Trap;
1980 }
1981 
1982 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1983 // intrinsic.
1984 static bool isBrevLdIntrinsic(const Value *Inst) {
1985  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1986  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1987  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1988  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1989  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1990  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1991  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1992 }
1993 
1994 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1995 // instruction. So far we only handle bitcast, extract value and bit reverse
1996 // load intrinsic instructions. Should we handle CGEP ?
1998  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1999  Operator::getOpcode(V) == Instruction::BitCast)
2000  V = cast<Operator>(V)->getOperand(0);
2001  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
2002  V = cast<Instruction>(V)->getOperand(0);
2003  return V;
2004 }
2005 
2006 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
2007 // a back edge. If the back edge comes from the intrinsic itself, the incoming
2008 // edge is returned.
2009 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
2010  const BasicBlock *Parent = PN->getParent();
2011  int Idx = -1;
2012  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
2013  BasicBlock *Blk = PN->getIncomingBlock(i);
2014  // Determine if the back edge is originated from intrinsic.
2015  if (Blk == Parent) {
2016  Value *BackEdgeVal = PN->getIncomingValue(i);
2017  Value *BaseVal;
2018  // Loop over till we return the same Value or we hit the IntrBaseVal.
2019  do {
2020  BaseVal = BackEdgeVal;
2021  BackEdgeVal = getBrevLdObject(BackEdgeVal);
2022  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
2023  // If the getBrevLdObject returns IntrBaseVal, we should return the
2024  // incoming edge.
2025  if (IntrBaseVal == BackEdgeVal)
2026  continue;
2027  Idx = i;
2028  break;
2029  } else // Set the node to incoming edge.
2030  Idx = i;
2031  }
2032  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
2033  return PN->getIncomingValue(Idx);
2034 }
2035 
2036 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
2037 // pointer points to, for the bit-reverse load intrinsic. Setting this to
2038 // memoperand might help alias analysis to figure out the dependencies.
2040  Value *IntrBaseVal = V;
2041  Value *BaseVal;
2042  // Loop over till we return the same Value, implies we either figure out
2043  // the object or we hit a PHI
2044  do {
2045  BaseVal = V;
2046  V = getBrevLdObject(V);
2047  } while (BaseVal != V);
2048 
2049  // Identify the object from PHINode.
2050  if (const PHINode *PN = dyn_cast<PHINode>(V))
2051  return returnEdge(PN, IntrBaseVal);
2052  // For non PHI nodes, the object is the last value returned by getBrevLdObject
2053  else
2054  return V;
2055 }
2056 
2057 /// Given an intrinsic, checks if on the target the intrinsic will need to map
2058 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
2059 /// true and store the intrinsic information into the IntrinsicInfo that was
2060 /// passed to the function.
2062  const CallInst &I,
2063  MachineFunction &MF,
2064  unsigned Intrinsic) const {
2065  switch (Intrinsic) {
2066  case Intrinsic::hexagon_L2_loadrd_pbr:
2067  case Intrinsic::hexagon_L2_loadri_pbr:
2068  case Intrinsic::hexagon_L2_loadrh_pbr:
2069  case Intrinsic::hexagon_L2_loadruh_pbr:
2070  case Intrinsic::hexagon_L2_loadrb_pbr:
2071  case Intrinsic::hexagon_L2_loadrub_pbr: {
2073  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
2074  auto &Cont = I.getCalledFunction()->getParent()->getContext();
2075  // The intrinsic function call is of the form { ElTy, i8* }
2076  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
2077  // should be derived from ElTy.
2078  Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
2079  Info.memVT = MVT::getVT(ElTy);
2080  llvm::Value *BasePtrVal = I.getOperand(0);
2081  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
2082  // The offset value comes through Modifier register. For now, assume the
2083  // offset is 0.
2084  Info.offset = 0;
2085  Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont));
2087  return true;
2088  }
2089  case Intrinsic::hexagon_V6_vgathermw:
2090  case Intrinsic::hexagon_V6_vgathermw_128B:
2091  case Intrinsic::hexagon_V6_vgathermh:
2092  case Intrinsic::hexagon_V6_vgathermh_128B:
2093  case Intrinsic::hexagon_V6_vgathermhw:
2094  case Intrinsic::hexagon_V6_vgathermhw_128B:
2095  case Intrinsic::hexagon_V6_vgathermwq:
2096  case Intrinsic::hexagon_V6_vgathermwq_128B:
2097  case Intrinsic::hexagon_V6_vgathermhq:
2098  case Intrinsic::hexagon_V6_vgathermhq_128B:
2099  case Intrinsic::hexagon_V6_vgathermhwq:
2100  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
2101  const Module &M = *I.getParent()->getParent()->getParent();
2103  Type *VecTy = I.getArgOperand(1)->getType();
2104  Info.memVT = MVT::getVT(VecTy);
2105  Info.ptrVal = I.getArgOperand(0);
2106  Info.offset = 0;
2107  Info.align =
2108  MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
2112  return true;
2113  }
2114  default:
2115  break;
2116  }
2117  return false;
2118 }
2119 
2121  return X.getValueType().isScalarInteger(); // 'tstbit'
2122 }
2123 
2125  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
2126 }
2127 
2129  if (!VT1.isSimple() || !VT2.isSimple())
2130  return false;
2131  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
2132 }
2133 
2135  const MachineFunction &MF, EVT VT) const {
2136  return isOperationLegalOrCustom(ISD::FMA, VT);
2137 }
2138 
2139 // Should we expand the build vector with shuffles?
2141  unsigned DefinedValues) const {
2142  return false;
2143 }
2144 
2146  EVT VT) const {
2147  return true;
2148 }
2149 
2152  unsigned VecLen = VT.getVectorMinNumElements();
2153  MVT ElemTy = VT.getVectorElementType();
2154 
2155  if (VecLen == 1 || VT.isScalableVector())
2157 
2158  if (Subtarget.useHVXOps()) {
2159  unsigned Action = getPreferredHvxVectorAction(VT);
2160  if (Action != ~0u)
2161  return static_cast<TargetLoweringBase::LegalizeTypeAction>(Action);
2162  }
2163 
2164  // Always widen (remaining) vectors of i1.
2165  if (ElemTy == MVT::i1)
2167 
2169 }
2170 
2171 std::pair<SDValue, int>
2172 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
2173  if (Addr.getOpcode() == ISD::ADD) {
2174  SDValue Op1 = Addr.getOperand(1);
2175  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
2176  return { Addr.getOperand(0), CN->getSExtValue() };
2177  }
2178  return { Addr, 0 };
2179 }
2180 
2181 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2182 // to select data from, V3 is the permutation.
2183 SDValue
2185  const {
2186  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
2187  ArrayRef<int> AM = SVN->getMask();
2188  assert(AM.size() <= 8 && "Unexpected shuffle mask");
2189  unsigned VecLen = AM.size();
2190 
2191  MVT VecTy = ty(Op);
2192  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
2193  "HVX shuffles should be legal");
2194  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
2195 
2196  SDValue Op0 = Op.getOperand(0);
2197  SDValue Op1 = Op.getOperand(1);
2198  const SDLoc &dl(Op);
2199 
2200  // If the inputs are not the same as the output, bail. This is not an
2201  // error situation, but complicates the handling and the default expansion
2202  // (into BUILD_VECTOR) should be adequate.
2203  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
2204  return SDValue();
2205 
2206  // Normalize the mask so that the first non-negative index comes from
2207  // the first operand.
2208  SmallVector<int,8> Mask(AM.begin(), AM.end());
2209  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
2210  if (F == AM.size())
2211  return DAG.getUNDEF(VecTy);
2212  if (AM[F] >= int(VecLen)) {
2214  std::swap(Op0, Op1);
2215  }
2216 
2217  // Express the shuffle mask in terms of bytes.
2218  SmallVector<int,8> ByteMask;
2219  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
2220  for (int M : Mask) {
2221  if (M < 0) {
2222  for (unsigned j = 0; j != ElemBytes; ++j)
2223  ByteMask.push_back(-1);
2224  } else {
2225  for (unsigned j = 0; j != ElemBytes; ++j)
2226  ByteMask.push_back(M*ElemBytes + j);
2227  }
2228  }
2229  assert(ByteMask.size() <= 8);
2230 
2231  // All non-undef (non-negative) indexes are well within [0..127], so they
2232  // fit in a single byte. Build two 64-bit words:
2233  // - MaskIdx where each byte is the corresponding index (for non-negative
2234  // indexes), and 0xFF for negative indexes, and
2235  // - MaskUnd that has 0xFF for each negative index.
2236  uint64_t MaskIdx = 0;
2237  uint64_t MaskUnd = 0;
2238  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
2239  unsigned S = 8*i;
2240  uint64_t M = ByteMask[i] & 0xFF;
2241  if (M == 0xFF)
2242  MaskUnd |= M << S;
2243  MaskIdx |= M << S;
2244  }
2245 
2246  if (ByteMask.size() == 4) {
2247  // Identity.
2248  if (MaskIdx == (0x03020100 | MaskUnd))
2249  return Op0;
2250  // Byte swap.
2251  if (MaskIdx == (0x00010203 | MaskUnd)) {
2252  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2253  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2254  return DAG.getBitcast(VecTy, T1);
2255  }
2256 
2257  // Byte packs.
2258  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
2259  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
2260  if (MaskIdx == (0x06040200 | MaskUnd))
2261  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2262  if (MaskIdx == (0x07050301 | MaskUnd))
2263  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2264 
2265  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
2266  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
2267  if (MaskIdx == (0x02000604 | MaskUnd))
2268  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2269  if (MaskIdx == (0x03010705 | MaskUnd))
2270  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2271  }
2272 
2273  if (ByteMask.size() == 8) {
2274  // Identity.
2275  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2276  return Op0;
2277  // Byte swap.
2278  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2279  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2280  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2281  return DAG.getBitcast(VecTy, T1);
2282  }
2283 
2284  // Halfword picks.
2285  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2286  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2287  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2288  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2289  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2290  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2291  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2292  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2293  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2294  VectorPair P = opSplit(Op0, dl, DAG);
2295  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2296  }
2297 
2298  // Byte packs.
2299  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2300  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2301  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2302  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2303  }
2304 
2305  return SDValue();
2306 }
2307 
2308 // Create a Hexagon-specific node for shifting a vector by an integer.
2309 SDValue
2310 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2311  const {
2312  unsigned NewOpc;
2313  switch (Op.getOpcode()) {
2314  case ISD::SHL:
2315  NewOpc = HexagonISD::VASL;
2316  break;
2317  case ISD::SRA:
2318  NewOpc = HexagonISD::VASR;
2319  break;
2320  case ISD::SRL:
2321  NewOpc = HexagonISD::VLSR;
2322  break;
2323  default:
2324  llvm_unreachable("Unexpected shift opcode");
2325  }
2326 
2327  SDValue Op0 = Op.getOperand(0);
2328  SDValue Op1 = Op.getOperand(1);
2329  const SDLoc &dl(Op);
2330 
2331  switch (Op1.getOpcode()) {
2332  case ISD::BUILD_VECTOR:
2333  if (SDValue S = cast<BuildVectorSDNode>(Op1)->getSplatValue())
2334  return DAG.getNode(NewOpc, dl, ty(Op), Op0, S);
2335  break;
2336  case ISD::SPLAT_VECTOR:
2337  return DAG.getNode(NewOpc, dl, ty(Op), Op0, Op1.getOperand(0));
2338  }
2339  return SDValue();
2340 }
2341 
2342 SDValue
2344  return getVectorShiftByInt(Op, DAG);
2345 }
2346 
2347 SDValue
2349  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2350  return Op;
2351  return SDValue();
2352 }
2353 
2354 SDValue
2356  MVT ResTy = ty(Op);
2357  SDValue InpV = Op.getOperand(0);
2358  MVT InpTy = ty(InpV);
2359  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2360  const SDLoc &dl(Op);
2361 
2362  // Handle conversion from i8 to v8i1.
2363  if (InpTy == MVT::i8) {
2364  if (ResTy == MVT::v8i1) {
2365  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2366  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2367  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2368  }
2369  return SDValue();
2370  }
2371 
2372  return Op;
2373 }
2374 
2375 bool
2376 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2377  MVT VecTy, SelectionDAG &DAG,
2378  MutableArrayRef<ConstantInt*> Consts) const {
2379  MVT ElemTy = VecTy.getVectorElementType();
2380  unsigned ElemWidth = ElemTy.getSizeInBits();
2381  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2382  bool AllConst = true;
2383 
2384  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2385  SDValue V = Values[i];
2386  if (V.isUndef()) {
2387  Consts[i] = ConstantInt::get(IntTy, 0);
2388  continue;
2389  }
2390  // Make sure to always cast to IntTy.
2391  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2392  const ConstantInt *CI = CN->getConstantIntValue();
2393  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2394  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2395  const ConstantFP *CF = CN->getConstantFPValue();
2396  APInt A = CF->getValueAPF().bitcastToAPInt();
2397  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2398  } else {
2399  AllConst = false;
2400  }
2401  }
2402  return AllConst;
2403 }
2404 
2405 SDValue
2406 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2407  MVT VecTy, SelectionDAG &DAG) const {
2408  MVT ElemTy = VecTy.getVectorElementType();
2409  assert(VecTy.getVectorNumElements() == Elem.size());
2410 
2411  SmallVector<ConstantInt*,4> Consts(Elem.size());
2412  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2413 
2414  unsigned First, Num = Elem.size();
2415  for (First = 0; First != Num; ++First) {
2416  if (!isUndef(Elem[First]))
2417  break;
2418  }
2419  if (First == Num)
2420  return DAG.getUNDEF(VecTy);
2421 
2422  if (AllConst &&
2423  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2424  return getZero(dl, VecTy, DAG);
2425 
2426  if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2427  assert(Elem.size() == 2);
2428  if (AllConst) {
2429  // The 'Consts' array will have all values as integers regardless
2430  // of the vector element type.
2431  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2432  Consts[1]->getZExtValue() << 16;
2433  return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32));
2434  }
2435  SDValue E0, E1;
2436  if (ElemTy == MVT::f16) {
2437  E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32);
2438  E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32);
2439  } else {
2440  E0 = Elem[0];
2441  E1 = Elem[1];
2442  }
2443  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG);
2444  return DAG.getBitcast(VecTy, N);
2445  }
2446 
2447  if (ElemTy == MVT::i8) {
2448  // First try generating a constant.
2449  if (AllConst) {
2450  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2451  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2452  (Consts[2]->getZExtValue() & 0xFF) << 16 |
2453  Consts[3]->getZExtValue() << 24;
2454  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2455  }
2456 
2457  // Then try splat.
2458  bool IsSplat = true;
2459  for (unsigned i = First+1; i != Num; ++i) {
2460  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2461  continue;
2462  IsSplat = false;
2463  break;
2464  }
2465  if (IsSplat) {
2466  // Legalize the operand of SPLAT_VECTOR.
2467  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2468  return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2469  }
2470 
2471  // Generate
2472  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2473  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2474  assert(Elem.size() == 4);
2475  SDValue Vs[4];
2476  for (unsigned i = 0; i != 4; ++i) {
2477  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2478  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2479  }
2480  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2481  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2482  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2483  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2484  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2485 
2486  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2487  return DAG.getBitcast(MVT::v4i8, R);
2488  }
2489 
2490 #ifndef NDEBUG
2491  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2492 #endif
2493  llvm_unreachable("Unexpected vector element type");
2494 }
2495 
2496 SDValue
2497 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2498  MVT VecTy, SelectionDAG &DAG) const {
2499  MVT ElemTy = VecTy.getVectorElementType();
2500  assert(VecTy.getVectorNumElements() == Elem.size());
2501 
2502  SmallVector<ConstantInt*,8> Consts(Elem.size());
2503  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2504 
2505  unsigned First, Num = Elem.size();
2506  for (First = 0; First != Num; ++First) {
2507  if (!isUndef(Elem[First]))
2508  break;
2509  }
2510  if (First == Num)
2511  return DAG.getUNDEF(VecTy);
2512 
2513  if (AllConst &&
2514  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2515  return getZero(dl, VecTy, DAG);
2516 
2517  // First try splat if possible.
2518  if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2519  bool IsSplat = true;
2520  for (unsigned i = First+1; i != Num; ++i) {
2521  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2522  continue;
2523  IsSplat = false;
2524  break;
2525  }
2526  if (IsSplat) {
2527  // Legalize the operand of SPLAT_VECTOR
2528  SDValue S = ElemTy == MVT::f16 ? DAG.getBitcast(MVT::i16, Elem[First])
2529  : Elem[First];
2530  SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32);
2531  return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2532  }
2533  }
2534 
2535  // Then try constant.
2536  if (AllConst) {
2537  uint64_t Val = 0;
2538  unsigned W = ElemTy.getSizeInBits();
2539  uint64_t Mask = (1ull << W) - 1;
2540  for (unsigned i = 0; i != Num; ++i)
2541  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2542  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2543  return DAG.getBitcast(VecTy, V0);
2544  }
2545 
2546  // Build two 32-bit vectors and concatenate.
2547  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2548  SDValue L = (ElemTy == MVT::i32)
2549  ? Elem[0]
2550  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2551  SDValue H = (ElemTy == MVT::i32)
2552  ? Elem[1]
2553  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2554  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2555 }
2556 
2557 SDValue
2558 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2559  const SDLoc &dl, MVT ValTy, MVT ResTy,
2560  SelectionDAG &DAG) const {
2561  MVT VecTy = ty(VecV);
2562  assert(!ValTy.isVector() ||
2563  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2564  unsigned VecWidth = VecTy.getSizeInBits();
2565  unsigned ValWidth = ValTy.getSizeInBits();
2566  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2567  assert((VecWidth % ElemWidth) == 0);
2568  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2569 
2570  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2571  // without any coprocessors).
2572  if (ElemWidth == 1) {
2573  assert(VecWidth == VecTy.getVectorNumElements() &&
2574  "Vector elements should equal vector width size");
2575  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2576  // Check if this is an extract of the lowest bit.
2577  if (IdxN) {
2578  // Extracting the lowest bit is a no-op, but it changes the type,
2579  // so it must be kept as an operation to avoid errors related to
2580  // type mismatches.
2581  if (IdxN->isZero() && ValTy.getSizeInBits() == 1)
2582  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2583  }
2584 
2585  // If the value extracted is a single bit, use tstbit.
2586  if (ValWidth == 1) {
2587  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2588  SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2589  SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2590  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2591  }
2592 
2593  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2594  // a predicate register. The elements of the vector are repeated
2595  // in the register (if necessary) so that the total number is 8.
2596  // The extracted subvector will need to be expanded in such a way.
2597  unsigned Scale = VecWidth / ValWidth;
2598 
2599  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2600  // position 0.
2601  assert(ty(IdxV) == MVT::i32);
2602  unsigned VecRep = 8 / VecWidth;
2603  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2604  DAG.getConstant(8*VecRep, dl, MVT::i32));
2605  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2606  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2607  while (Scale > 1) {
2608  // The longest possible subvector is at most 32 bits, so it is always
2609  // contained in the low subregister.
2610  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2611  T1 = expandPredicate(T1, dl, DAG);
2612  Scale /= 2;
2613  }
2614 
2615  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2616  }
2617 
2618  assert(VecWidth == 32 || VecWidth == 64);
2619 
2620  // Cast everything to scalar integer types.
2621  MVT ScalarTy = tyScalar(VecTy);
2622  VecV = DAG.getBitcast(ScalarTy, VecV);
2623 
2624  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2625  SDValue ExtV;
2626 
2627  if (IdxN) {
2628  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2629  if (VecWidth == 64 && ValWidth == 32) {
2630  assert(Off == 0 || Off == 32);
2631  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2632  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2633  } else if (Off == 0 && (ValWidth % 8) == 0) {
2634  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2635  } else {
2636  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2637  // The return type of EXTRACTU must be the same as the type of the
2638  // input vector.
2639  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2640  {VecV, WidthV, OffV});
2641  }
2642  } else {
2643  if (ty(IdxV) != MVT::i32)
2644  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2645  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2646  DAG.getConstant(ElemWidth, dl, MVT::i32));
2647  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2648  {VecV, WidthV, OffV});
2649  }
2650 
2651  // Cast ExtV to the requested result type.
2652  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2653  ExtV = DAG.getBitcast(ResTy, ExtV);
2654  return ExtV;
2655 }
2656 
2657 SDValue
2658 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2659  const SDLoc &dl, MVT ValTy,
2660  SelectionDAG &DAG) const {
2661  MVT VecTy = ty(VecV);
2662  if (VecTy.getVectorElementType() == MVT::i1) {
2663  MVT ValTy = ty(ValV);
2664  assert(ValTy.getVectorElementType() == MVT::i1);
2665  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2666  unsigned VecLen = VecTy.getVectorNumElements();
2667  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2668  assert(Scale > 1);
2669 
2670  for (unsigned R = Scale; R > 1; R /= 2) {
2671  ValR = contractPredicate(ValR, dl, DAG);
2672  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2673  DAG.getUNDEF(MVT::i32), ValR);
2674  }
2675  // The longest possible subvector is at most 32 bits, so it is always
2676  // contained in the low subregister.
2677  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2678 
2679  unsigned ValBytes = 64 / Scale;
2680  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2681  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2682  DAG.getConstant(8, dl, MVT::i32));
2683  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2685  {VecR, ValR, Width, Idx});
2686  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2687  }
2688 
2689  unsigned VecWidth = VecTy.getSizeInBits();
2690  unsigned ValWidth = ValTy.getSizeInBits();
2691  assert(VecWidth == 32 || VecWidth == 64);
2692  assert((VecWidth % ValWidth) == 0);
2693 
2694  // Cast everything to scalar integer types.
2695  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2696  // The actual type of ValV may be different than ValTy (which is related
2697  // to the vector type).
2698  unsigned VW = ty(ValV).getSizeInBits();
2699  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2700  VecV = DAG.getBitcast(ScalarTy, VecV);
2701  if (VW != VecWidth)
2702  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2703 
2704  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2705  SDValue InsV;
2706 
2707  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2708  unsigned W = C->getZExtValue() * ValWidth;
2709  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2710  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2711  {VecV, ValV, WidthV, OffV});
2712  } else {
2713  if (ty(IdxV) != MVT::i32)
2714  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2715  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2716  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2717  {VecV, ValV, WidthV, OffV});
2718  }
2719 
2720  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2721 }
2722 
2723 SDValue
2724 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2725  SelectionDAG &DAG) const {
2726  assert(ty(Vec32).getSizeInBits() == 32);
2727  if (isUndef(Vec32))
2728  return DAG.getUNDEF(MVT::i64);
2729  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2730 }
2731 
2732 SDValue
2733 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2734  SelectionDAG &DAG) const {
2735  assert(ty(Vec64).getSizeInBits() == 64);
2736  if (isUndef(Vec64))
2737  return DAG.getUNDEF(MVT::i32);
2738  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2739 }
2740 
2741 SDValue
2742 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2743  const {
2744  if (Ty.isVector()) {
2745  unsigned W = Ty.getSizeInBits();
2746  if (W <= 64)
2747  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2748  return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG));
2749  }
2750 
2751  if (Ty.isInteger())
2752  return DAG.getConstant(0, dl, Ty);
2753  if (Ty.isFloatingPoint())
2754  return DAG.getConstantFP(0.0, dl, Ty);
2755  llvm_unreachable("Invalid type for zero");
2756 }
2757 
2758 SDValue
2759 HexagonTargetLowering::appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG)
2760  const {
2761  MVT ValTy = ty(Val);
2762  assert(ValTy.getVectorElementType() == ResTy.getVectorElementType());
2763 
2764  unsigned ValLen = ValTy.getVectorNumElements();
2765  unsigned ResLen = ResTy.getVectorNumElements();
2766  if (ValLen == ResLen)
2767  return Val;
2768 
2769  const SDLoc &dl(Val);
2770  assert(ValLen < ResLen);
2771  assert(ResLen % ValLen == 0);
2772 
2773  SmallVector<SDValue, 4> Concats = {Val};
2774  for (unsigned i = 1, e = ResLen / ValLen; i < e; ++i)
2775  Concats.push_back(DAG.getUNDEF(ValTy));
2776 
2777  return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats);
2778 }
2779 
2780 SDValue
2782  MVT VecTy = ty(Op);
2783  unsigned BW = VecTy.getSizeInBits();
2784  const SDLoc &dl(Op);
2786  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2787  Ops.push_back(Op.getOperand(i));
2788 
2789  if (BW == 32)
2790  return buildVector32(Ops, dl, VecTy, DAG);
2791  if (BW == 64)
2792  return buildVector64(Ops, dl, VecTy, DAG);
2793 
2794  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2795  // Check if this is a special case or all-0 or all-1.
2796  bool All0 = true, All1 = true;
2797  for (SDValue P : Ops) {
2798  auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
2799  if (CN == nullptr) {
2800  All0 = All1 = false;
2801  break;
2802  }
2803  uint32_t C = CN->getZExtValue();
2804  All0 &= (C == 0);
2805  All1 &= (C == 1);
2806  }
2807  if (All0)
2808  return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
2809  if (All1)
2810  return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);
2811 
2812  // For each i1 element in the resulting predicate register, put 1
2813  // shifted by the index of the element into a general-purpose register,
2814  // then or them together and transfer it back into a predicate register.
2815  SDValue Rs[8];
2816  SDValue Z = getZero(dl, MVT::i32, DAG);
2817  // Always produce 8 bits, repeat inputs if necessary.
2818  unsigned Rep = 8 / VecTy.getVectorNumElements();
2819  for (unsigned i = 0; i != 8; ++i) {
2820  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2821  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2822  }
2823  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2824  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2825  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2826  }
2827  // Move the value directly to a predicate register.
2828  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2829  }
2830 
2831  return SDValue();
2832 }
2833 
2834 SDValue
2836  SelectionDAG &DAG) const {
2837  MVT VecTy = ty(Op);
2838  const SDLoc &dl(Op);
2839  if (VecTy.getSizeInBits() == 64) {
2840  assert(Op.getNumOperands() == 2);
2841  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2842  Op.getOperand(0));
2843  }
2844 
2845  MVT ElemTy = VecTy.getVectorElementType();
2846  if (ElemTy == MVT::i1) {
2847  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2848  MVT OpTy = ty(Op.getOperand(0));
2849  // Scale is how many times the operands need to be contracted to match
2850  // the representation in the target register.
2851  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2852  assert(Scale == Op.getNumOperands() && Scale > 1);
2853 
2854  // First, convert all bool vectors to integers, then generate pairwise
2855  // inserts to form values of doubled length. Up until there are only
2856  // two values left to concatenate, all of these values will fit in a
2857  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2858  SmallVector<SDValue,4> Words[2];
2859  unsigned IdxW = 0;
2860 
2861  for (SDValue P : Op.getNode()->op_values()) {
2862  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2863  for (unsigned R = Scale; R > 1; R /= 2) {
2864  W = contractPredicate(W, dl, DAG);
2866  DAG.getUNDEF(MVT::i32), W);
2867  }
2868  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2869  Words[IdxW].push_back(W);
2870  }
2871 
2872  while (Scale > 2) {
2873  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2874  Words[IdxW ^ 1].clear();
2875 
2876  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2877  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2878  // Insert W1 into W0 right next to the significant bits of W0.
2880  {W0, W1, WidthV, WidthV});
2881  Words[IdxW ^ 1].push_back(T);
2882  }
2883  IdxW ^= 1;
2884  Scale /= 2;
2885  }
2886 
2887  // At this point there should only be two words left, and Scale should be 2.
2888  assert(Scale == 2 && Words[IdxW].size() == 2);
2889 
2891  Words[IdxW][1], Words[IdxW][0]);
2892  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2893  }
2894 
2895  return SDValue();
2896 }
2897 
2898 SDValue
2900  SelectionDAG &DAG) const {
2901  SDValue Vec = Op.getOperand(0);
2902  MVT ElemTy = ty(Vec).getVectorElementType();
2903  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2904 }
2905 
2906 SDValue
2908  SelectionDAG &DAG) const {
2909  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2910  ty(Op), ty(Op), DAG);
2911 }
2912 
2913 SDValue
2915  SelectionDAG &DAG) const {
2916  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2917  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2918 }
2919 
2920 SDValue
2922  SelectionDAG &DAG) const {
2923  SDValue ValV = Op.getOperand(1);
2924  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2925  SDLoc(Op), ty(ValV), DAG);
2926 }
2927 
2928 bool
2930  // Assuming the caller does not have either a signext or zeroext modifier, and
2931  // only one value is accepted, any reasonable truncation is allowed.
2932  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2933  return false;
2934 
2935  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2936  // fragile at the moment: any support for multiple value returns would be
2937  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2938  return Ty1->getPrimitiveSizeInBits() <= 32;
2939 }
2940 
2941 SDValue
2943  MVT Ty = ty(Op);
2944  const SDLoc &dl(Op);
2945  // Lower loads of scalar predicate vectors (v2i1, v4i1, v8i1) to loads of i1
2946  // followed by a TYPECAST.
2947  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2948  bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1);
2949  if (DoCast) {
2950  SDValue NL = DAG.getLoad(
2951  LN->getAddressingMode(), LN->getExtensionType(), MVT::i1, dl,
2952  LN->getChain(), LN->getBasePtr(), LN->getOffset(), LN->getPointerInfo(),
2953  /*MemoryVT*/ MVT::i1, LN->getAlign(), LN->getMemOperand()->getFlags(),
2954  LN->getAAInfo(), LN->getRanges());
2955  LN = cast<LoadSDNode>(NL.getNode());
2956  }
2957 
2958  Align ClaimAlign = LN->getAlign();
2959  if (!validateConstPtrAlignment(LN->getBasePtr(), ClaimAlign, dl, DAG))
2960  return replaceMemWithUndef(Op, DAG);
2961 
2962  // Call LowerUnalignedLoad for all loads, it recognizes loads that
2963  // don't need extra aligning.
2964  SDValue LU = LowerUnalignedLoad(SDValue(LN, 0), DAG);
2965  if (DoCast) {
2966  SDValue TC = DAG.getNode(HexagonISD::TYPECAST, dl, Ty, LU);
2967  SDValue Ch = cast<LoadSDNode>(LU.getNode())->getChain();
2968  return DAG.getMergeValues({TC, Ch}, dl);
2969  }
2970  return LU;
2971 }
2972 
2973 SDValue
2975  const SDLoc &dl(Op);
2976  StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2977  SDValue Val = SN->getValue();
2978  MVT Ty = ty(Val);
2979 
2980  bool DoCast = (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1);
2981  if (DoCast) {
2982  SDValue TC = DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, Val);
2983  SDValue NS = DAG.getStore(SN->getChain(), dl, TC, SN->getBasePtr(),
2984  SN->getMemOperand());
2985  if (SN->isIndexed()) {
2986  NS = DAG.getIndexedStore(NS, dl, SN->getBasePtr(), SN->getOffset(),
2987  SN->getAddressingMode());
2988  }
2989  SN = cast<StoreSDNode>(NS.getNode());
2990  }
2991 
2992  Align ClaimAlign = SN->getAlign();
2993  if (!validateConstPtrAlignment(SN->getBasePtr(), ClaimAlign, dl, DAG))
2994  return replaceMemWithUndef(Op, DAG);
2995 
2996  MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2997  Align NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2998  if (ClaimAlign < NeedAlign)
2999  return expandUnalignedStore(SN, DAG);
3000  return SDValue(SN, 0);
3001 }
3002 
3003 SDValue
3005  const {
3006  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
3007  MVT LoadTy = ty(Op);
3008  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).value();
3009  unsigned HaveAlign = LN->getAlign().value();
3010  if (HaveAlign >= NeedAlign)
3011  return Op;
3012 
3013  const SDLoc &dl(Op);
3014  const DataLayout &DL = DAG.getDataLayout();
3015  LLVMContext &Ctx = *DAG.getContext();
3016 
3017  // If the load aligning is disabled or the load can be broken up into two
3018  // smaller legal loads, do the default (target-independent) expansion.
3019  bool DoDefault = false;
3020  // Handle it in the default way if this is an indexed load.
3021  if (!LN->isUnindexed())
3022  DoDefault = true;
3023 
3024  if (!AlignLoads) {
3026  *LN->getMemOperand()))
3027  return Op;
3028  DoDefault = true;
3029  }
3030  if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
3031  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
3032  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
3033  : MVT::getVectorVT(MVT::i8, HaveAlign);
3034  DoDefault =
3035  allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
3036  }
3037  if (DoDefault) {
3038  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
3039  return DAG.getMergeValues({P.first, P.second}, dl);
3040  }
3041 
3042  // The code below generates two loads, both aligned as NeedAlign, and
3043  // with the distance of NeedAlign between them. For that to cover the
3044  // bits that need to be loaded (and without overlapping), the size of
3045  // the loads should be equal to NeedAlign. This is true for all loadable
3046  // types, but add an assertion in case something changes in the future.
3047  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
3048 
3049  unsigned LoadLen = NeedAlign;
3050  SDValue Base = LN->getBasePtr();
3051  SDValue Chain = LN->getChain();
3052  auto BO = getBaseAndOffset(Base);
3053  unsigned BaseOpc = BO.first.getOpcode();
3054  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
3055  return Op;
3056 
3057  if (BO.second % LoadLen != 0) {
3058  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
3059  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
3060  BO.second -= BO.second % LoadLen;
3061  }
3062  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
3063  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
3064  DAG.getConstant(NeedAlign, dl, MVT::i32))
3065  : BO.first;
3066  SDValue Base0 =
3067  DAG.getMemBasePlusOffset(BaseNoOff, TypeSize::Fixed(BO.second), dl);
3068  SDValue Base1 = DAG.getMemBasePlusOffset(
3069  BaseNoOff, TypeSize::Fixed(BO.second + LoadLen), dl);
3070 
3071  MachineMemOperand *WideMMO = nullptr;
3072  if (MachineMemOperand *MMO = LN->getMemOperand()) {
3073  MachineFunction &MF = DAG.getMachineFunction();
3074  WideMMO = MF.getMachineMemOperand(
3075  MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen, Align(LoadLen),
3076  MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
3077  MMO->getSuccessOrdering(), MMO->getFailureOrdering());
3078  }
3079 
3080  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
3081  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
3082 
3083  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
3084  {Load1, Load0, BaseNoOff.getOperand(0)});
3085  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3086  Load0.getValue(1), Load1.getValue(1));
3087  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
3088  return M;
3089 }
3090 
3091 SDValue
3093  SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
3094  auto *CY = dyn_cast<ConstantSDNode>(Y);
3095  if (!CY)
3096  return SDValue();
3097 
3098  const SDLoc &dl(Op);
3099  SDVTList VTs = Op.getNode()->getVTList();
3100  assert(VTs.NumVTs == 2);
3101  assert(VTs.VTs[1] == MVT::i1);
3102  unsigned Opc = Op.getOpcode();
3103 
3104  if (CY) {
3105  uint32_t VY = CY->getZExtValue();
3106  assert(VY != 0 && "This should have been folded");
3107  // X +/- 1
3108  if (VY != 1)
3109  return SDValue();
3110 
3111  if (Opc == ISD::UADDO) {
3112  SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
3113  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
3114  ISD::SETEQ);
3115  return DAG.getMergeValues({Op, Ov}, dl);
3116  }
3117  if (Opc == ISD::USUBO) {
3118  SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
3119  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
3120  DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
3121  return DAG.getMergeValues({Op, Ov}, dl);
3122  }
3123  }
3124 
3125  return SDValue();
3126 }
3127 
3128 SDValue
3130  const SDLoc &dl(Op);
3131  unsigned Opc = Op.getOpcode();
3132  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
3133 
3134  if (Opc == ISD::ADDCARRY)
3135  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
3136  { X, Y, C });
3137 
3138  EVT CarryTy = C.getValueType();
3139  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
3140  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
3141  SDValue Out[] = { SubC.getValue(0),
3142  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
3143  return DAG.getMergeValues(Out, dl);
3144 }
3145 
3146 SDValue
3148  SDValue Chain = Op.getOperand(0);
3149  SDValue Offset = Op.getOperand(1);
3150  SDValue Handler = Op.getOperand(2);
3151  SDLoc dl(Op);
3152  auto PtrVT = getPointerTy(DAG.getDataLayout());
3153 
3154  // Mark function as containing a call to EH_RETURN.
3155  HexagonMachineFunctionInfo *FuncInfo =
3157  FuncInfo->setHasEHReturn();
3158 
3159  unsigned OffsetReg = Hexagon::R28;
3160 
3161  SDValue StoreAddr =
3162  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
3163  DAG.getIntPtrConstant(4, dl));
3164  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
3165  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
3166 
3167  // Not needed we already use it as explict input to EH_RETURN.
3168  // MF.getRegInfo().addLiveOut(OffsetReg);
3169 
3170  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
3171 }
3172 
3173 SDValue
3175  unsigned Opc = Op.getOpcode();
3176 
3177  // Handle INLINEASM first.
3178  if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
3179  return LowerINLINEASM(Op, DAG);
3180 
3181  if (isHvxOperation(Op.getNode(), DAG)) {
3182  // If HVX lowering returns nothing, try the default lowering.
3183  if (SDValue V = LowerHvxOperation(Op, DAG))
3184  return V;
3185  }
3186 
3187  switch (Opc) {
3188  default:
3189 #ifndef NDEBUG
3190  Op.getNode()->dumpr(&DAG);
3191  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
3192  errs() << "Error: check for a non-legal type in this operation\n";
3193 #endif
3194  llvm_unreachable("Should not custom lower this!");
3195  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3196  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
3200  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3201  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3202  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
3203  case ISD::LOAD: return LowerLoad(Op, DAG);
3204  case ISD::STORE: return LowerStore(Op, DAG);
3205  case ISD::UADDO:
3206  case ISD::USUBO: return LowerUAddSubO(Op, DAG);
3207  case ISD::ADDCARRY:
3208  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
3209  case ISD::SRA:
3210  case ISD::SHL:
3211  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
3212  case ISD::ROTL: return LowerROTL(Op, DAG);
3213  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3214  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3215  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
3216  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3217  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3218  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3219  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
3220  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
3221  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3223  case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3224  case ISD::VASTART: return LowerVASTART(Op, DAG);
3226  case ISD::SETCC: return LowerSETCC(Op, DAG);
3227  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3229  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3230  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3231  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
3232  break;
3233  }
3234 
3235  return SDValue();
3236 }
3237 
3238 void
3241  SelectionDAG &DAG) const {
3242  if (isHvxOperation(N, DAG)) {
3243  LowerHvxOperationWrapper(N, Results, DAG);
3244  if (!Results.empty())
3245  return;
3246  }
3247 
3248  // We are only custom-lowering stores to verify the alignment of the
3249  // address if it is a compile-time constant. Since a store can be modified
3250  // during type-legalization (the value being stored may need legalization),
3251  // return empty Results here to indicate that we don't really make any
3252  // changes in the custom lowering.
3253  if (N->getOpcode() != ISD::STORE)
3255 }
3256 
3257 void
3260  SelectionDAG &DAG) const {
3261  if (isHvxOperation(N, DAG)) {
3262  ReplaceHvxNodeResults(N, Results, DAG);
3263  if (!Results.empty())
3264  return;
3265  }
3266 
3267  const SDLoc &dl(N);
3268  switch (N->getOpcode()) {
3269  case ISD::SRL:
3270  case ISD::SRA:
3271  case ISD::SHL:
3272  return;
3273  case ISD::BITCAST:
3274  // Handle a bitcast from v8i1 to i8.
3275  if (N->getValueType(0) == MVT::i8) {
3276  if (N->getOperand(0).getValueType() == MVT::v8i1) {
3277  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3278  N->getOperand(0), DAG);
3279  SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
3280  Results.push_back(T);
3281  }
3282  }
3283  break;
3284  }
3285 }
3286 
3287 SDValue
3289  const {
3290  if (isHvxOperation(N, DCI.DAG)) {
3291  if (SDValue V = PerformHvxDAGCombine(N, DCI))
3292  return V;
3293  return SDValue();
3294  }
3295 
3296  if (DCI.isBeforeLegalizeOps())
3297  return SDValue();
3298 
3299  SDValue Op(N, 0);
3300  const SDLoc &dl(Op);
3301  unsigned Opc = Op.getOpcode();
3302 
3303  if (Opc == HexagonISD::P2D) {
3304  SDValue P = Op.getOperand(0);
3305  switch (P.getOpcode()) {
3306  case HexagonISD::PTRUE:
3307  return DCI.DAG.getConstant(-1, dl, ty(Op));
3308  case HexagonISD::PFALSE:
3309  return getZero(dl, ty(Op), DCI.DAG);
3310  default:
3311  break;
3312  }
3313  } else if (Opc == ISD::VSELECT) {
3314  // This is pretty much duplicated in HexagonISelLoweringHVX...
3315  //
3316  // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3317  SDValue Cond = Op.getOperand(0);
3318  if (Cond->getOpcode() == ISD::XOR) {
3319  SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
3320  if (C1->getOpcode() == HexagonISD::PTRUE) {
3321  SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
3322  Op.getOperand(2), Op.getOperand(1));
3323  return VSel;
3324  }
3325  }
3326  }
3327 
3328  return SDValue();
3329 }
3330 
3331 /// Returns relocation base for the given PIC jumptable.
3332 SDValue
3334  SelectionDAG &DAG) const {
3335  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3336  EVT VT = Table.getValueType();
3338  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3339 }
3340 
3341 //===----------------------------------------------------------------------===//
3342 // Inline Assembly Support
3343 //===----------------------------------------------------------------------===//
3344 
3347  if (Constraint.size() == 1) {
3348  switch (Constraint[0]) {
3349  case 'q':
3350  case 'v':
3351  if (Subtarget.useHVXOps())
3352  return C_RegisterClass;
3353  break;
3354  case 'a':
3355  return C_RegisterClass;
3356  default:
3357  break;
3358  }
3359  }
3360  return TargetLowering::getConstraintType(Constraint);
3361 }
3362 
3363 std::pair<unsigned, const TargetRegisterClass*>
3365  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3366 
3367  if (Constraint.size() == 1) {
3368  switch (Constraint[0]) {
3369  case 'r': // R0-R31
3370  switch (VT.SimpleTy) {
3371  default:
3372  return {0u, nullptr};
3373  case MVT::i1:
3374  case MVT::i8:
3375  case MVT::i16:
3376  case MVT::i32:
3377  case MVT::f32:
3378  return {0u, &Hexagon::IntRegsRegClass};
3379  case MVT::i64:
3380  case MVT::f64:
3381  return {0u, &Hexagon::DoubleRegsRegClass};
3382  }
3383  break;
3384  case 'a': // M0-M1
3385  if (VT != MVT::i32)
3386  return {0u, nullptr};
3387  return {0u, &Hexagon::ModRegsRegClass};
3388  case 'q': // q0-q3
3389  switch (VT.getSizeInBits()) {
3390  default:
3391  return {0u, nullptr};
3392  case 64:
3393  case 128:
3394  return {0u, &Hexagon::HvxQRRegClass};
3395  }
3396  break;
3397  case 'v': // V0-V31
3398  switch (VT.getSizeInBits()) {
3399  default:
3400  return {0u, nullptr};
3401  case 512:
3402  return {0u, &Hexagon::HvxVRRegClass};
3403  case 1024:
3404  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3405  return {0u, &Hexagon::HvxVRRegClass};
3406  return {0u, &Hexagon::HvxWRRegClass};
3407  case 2048:
3408  return {0u, &Hexagon::HvxWRRegClass};
3409  }
3410  break;
3411  default:
3412  return {0u, nullptr};
3413  }
3414  }
3415 
3416  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3417 }
3418 
3419 /// isFPImmLegal - Returns true if the target can instruction select the
3420 /// specified FP immediate natively. If false, the legalizer will
3421 /// materialize the FP immediate as a load from a constant pool.
3423  bool ForCodeSize) const {
3424  return true;
3425 }
3426 
3427 /// isLegalAddressingMode - Return true if the addressing mode represented by
3428 /// AM is legal for this target, for a load/store of the specified type.
3430  const AddrMode &AM, Type *Ty,
3431  unsigned AS, Instruction *I) const {
3432  if (Ty->isSized()) {
3433  // When LSR detects uses of the same base address to access different
3434  // types (e.g. unions), it will assume a conservative type for these
3435  // uses:
3436  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3437  // The type Ty passed here would then be "void". Skip the alignment
3438  // checks, but do not return false right away, since that confuses
3439  // LSR into crashing.
3440  Align A = DL.getABITypeAlign(Ty);
3441  // The base offset must be a multiple of the alignment.
3442  if (!isAligned(A, AM.BaseOffs))
3443  return false;
3444  // The shifted offset must fit in 11 bits.
3445  if (!isInt<11>(AM.BaseOffs >> Log2(A)))
3446  return false;
3447  }
3448 
3449  // No global is ever allowed as a base.
3450  if (AM.BaseGV)
3451  return false;
3452 
3453  int Scale = AM.Scale;
3454  if (Scale < 0)
3455  Scale = -Scale;
3456  switch (Scale) {
3457  case 0: // No scale reg, "r+i", "r", or just "i".
3458  break;
3459  default: // No scaled addressing mode.
3460  return false;
3461  }
3462  return true;
3463 }
3464 
3465 /// Return true if folding a constant offset with the given GlobalAddress is
3466 /// legal. It is frequently not legal in PIC relocation models.
3468  const {
3469  return HTM.getRelocationModel() == Reloc::Static;
3470 }
3471 
3472 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3473 /// icmp immediate, that is the target has icmp instructions which can compare
3474 /// a register against the immediate without having to materialize the
3475 /// immediate into a register.
3477  return Imm >= -512 && Imm <= 511;
3478 }
3479 
3480 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3481 /// for tail call optimization. Targets which want to do tail call
3482 /// optimization should implement this function.
3484  SDValue Callee,
3485  CallingConv::ID CalleeCC,
3486  bool IsVarArg,
3487  bool IsCalleeStructRet,
3488  bool IsCallerStructRet,
3489  const SmallVectorImpl<ISD::OutputArg> &Outs,
3490  const SmallVectorImpl<SDValue> &OutVals,
3492  SelectionDAG& DAG) const {
3493  const Function &CallerF = DAG.getMachineFunction().getFunction();
3494  CallingConv::ID CallerCC = CallerF.getCallingConv();
3495  bool CCMatch = CallerCC == CalleeCC;
3496 
3497  // ***************************************************************************
3498  // Look for obvious safe cases to perform tail call optimization that do not
3499  // require ABI changes.
3500  // ***************************************************************************
3501 
3502  // If this is a tail call via a function pointer, then don't do it!
3503  if (!isa<GlobalAddressSDNode>(Callee) &&
3504  !isa<ExternalSymbolSDNode>(Callee)) {
3505  return false;
3506  }
3507 
3508  // Do not optimize if the calling conventions do not match and the conventions
3509  // used are not C or Fast.
3510  if (!CCMatch) {
3511  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3512  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3513  // If R & E, then ok.
3514  if (!R || !E)
3515  return false;
3516  }
3517 
3518  // Do not tail call optimize vararg calls.
3519  if (IsVarArg)
3520  return false;
3521 
3522  // Also avoid tail call optimization if either caller or callee uses struct
3523  // return semantics.
3524  if (IsCalleeStructRet || IsCallerStructRet)
3525  return false;
3526 
3527  // In addition to the cases above, we also disable Tail Call Optimization if
3528  // the calling convention code that at least one outgoing argument needs to
3529  // go on the stack. We cannot check that here because at this point that
3530  // information is not available.
3531  return true;
3532 }
3533 
3534 /// Returns the target specific optimal type for load and store operations as
3535 /// a result of memset, memcpy, and memmove lowering.
3536 ///
3537 /// If DstAlign is zero that means it's safe to destination alignment can
3538 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3539 /// a need to check it against alignment requirement, probably because the
3540 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3541 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3542 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3543 /// does not need to be loaded. It returns EVT::Other if the type should be
3544 /// determined using generic target-independent logic.
3546  const MemOp &Op, const AttributeList &FuncAttributes) const {
3547  if (Op.size() >= 8 && Op.isAligned(Align(8)))
3548  return MVT::i64;
3549  if (Op.size() >= 4 && Op.isAligned(Align(4)))
3550  return MVT::i32;
3551  if (Op.size() >= 2 && Op.isAligned(Align(2)))
3552  return MVT::i16;
3553  return MVT::Other;
3554 }
3555 
3557  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
3558  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
3559  MVT SVT = VT.getSimpleVT();
3560  if (Subtarget.isHVXVectorType(SVT, true))
3561  return allowsHvxMemoryAccess(SVT, Flags, Fast);
3563  Context, DL, VT, AddrSpace, Alignment, Flags, Fast);
3564 }
3565 
3567  EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
3568  bool *Fast) const {
3569  MVT SVT = VT.getSimpleVT();
3570  if (Subtarget.isHVXVectorType(SVT, true))
3571  return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
3572  if (Fast)
3573  *Fast = false;
3574  return false;
3575 }
3576 
3577 std::pair<const TargetRegisterClass*, uint8_t>
3578 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3579  MVT VT) const {
3580  if (Subtarget.isHVXVectorType(VT, true)) {
3581  unsigned BitWidth = VT.getSizeInBits();
3582  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3583 
3584  if (VT.getVectorElementType() == MVT::i1)
3585  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3586  if (BitWidth == VecWidth)
3587  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3588  assert(BitWidth == 2 * VecWidth);
3589  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3590  }
3591 
3593 }
3594 
3596  ISD::LoadExtType ExtTy, EVT NewVT) const {
3597  // TODO: This may be worth removing. Check regression tests for diffs.
3598  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3599  return false;
3600 
3601  auto *L = cast<LoadSDNode>(Load);
3602  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3603  // Small-data object, do not shrink.
3604  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3605  return false;
3606  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3607  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3608  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3609  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3610  }
3611  return true;
3612 }
3613 
3615  Type *ValueTy, Value *Addr,
3616  AtomicOrdering Ord) const {
3617  BasicBlock *BB = Builder.GetInsertBlock();
3618  Module *M = BB->getParent()->getParent();
3619  unsigned SZ = ValueTy->getPrimitiveSizeInBits();
3620  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3621  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3622  : Intrinsic::hexagon_L4_loadd_locked;
3623  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3624 
3625  auto PtrTy = cast<PointerType>(Addr->getType());
3626  PointerType *NewPtrTy =
3627  Builder.getIntNTy(SZ)->getPointerTo(PtrTy->getAddressSpace());
3628  Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3629 
3630  Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3631 
3632  return Builder.CreateBitCast(Call, ValueTy);
3633 }
3634 
3635 /// Perform a store-conditional operation to Addr. Return the status of the
3636 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3638  Value *Val, Value *Addr,
3639  AtomicOrdering Ord) const {
3640  BasicBlock *BB = Builder.GetInsertBlock();
3641  Module *M = BB->getParent()->getParent();
3642  Type *Ty = Val->getType();
3643  unsigned SZ = Ty->getPrimitiveSizeInBits();
3644 
3645  Type *CastTy = Builder.getIntNTy(SZ);
3646  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3647  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3648  : Intrinsic::hexagon_S4_stored_locked;
3649  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3650 
3651  unsigned AS = Addr->getType()->getPointerAddressSpace();
3652  Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3653  Val = Builder.CreateBitCast(Val, CastTy);
3654 
3655  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3656  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3657  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3658  return Ext;
3659 }
3660 
3663  // Do not expand loads and stores that don't exceed 64 bits.
3664  return LI->getType()->getPrimitiveSizeInBits() > 64
3667 }
3668 
3671  // Do not expand loads and stores that don't exceed 64 bits.
3672  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64
3675 }
3676 
3679  AtomicCmpXchgInst *AI) const {
3681 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:981
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1417
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:295
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3315
llvm::LoadSDNode::getOffset
const SDValue & getOffset() const
Definition: SelectionDAGNodes.h:2334
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:36
ValueTypes.h
llvm::HexagonISD::QFALSE
@ QFALSE
Definition: HexagonISelLowering.h:81
llvm::HexagonTargetLowering::shouldExpandAtomicStoreInIR
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: HexagonISelLowering.cpp:3670
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1564
llvm::HexagonTargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1168
llvm::StoreSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2364
llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
Definition: HexagonISelLowering.cpp:3483
llvm::Type::isSized
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
MinimumJumpTables
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
llvm::TargetLowering::LowerOperationWrapper
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SelectionDAGBuilder.cpp:10081
llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
Definition: HexagonISelLowering.cpp:2134
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2222
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:586
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2408
llvm::HexagonTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1112
llvm::HexagonTargetLowering::LowerEH_RETURN
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:3147
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:940
B1
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: HexagonISelLowering.cpp:3678
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1428
llvm::ISD::INTRINSIC_VOID
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:199
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1353
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::HexagonSubtarget::useSmallData
bool useSmallData() const
Definition: HexagonSubtarget.h:209
llvm::HexagonMachineFunctionInfo::setHasEHReturn
void setHasEHReturn(bool H=true)
Definition: HexagonMachineFunctionInfo.h:79
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Definition: SelectionDAGNodes.h:970
llvm::HexagonSubtarget::getFrameLowering
const HexagonFrameLowering * getFrameLowering() const override
Definition: HexagonSubtarget.h:131
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::MVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: MachineValueType.h:350
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:189
llvm::Intrinsic::getDeclaration
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1410
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1429
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::getNumFixedObjects
unsigned getNumFixedObjects() const
Return the number of fixed objects.
Definition: MachineFrameInfo.h:412
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:377
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4392
llvm::HexagonII::MO_GDGOT
@ MO_GDGOT
Definition: HexagonBaseInfo.h:194
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:984
IntrinsicInst.h
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:936
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:61
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:747
llvm::Function::empty
bool empty() const
Definition: Function.h:731
llvm::HexagonTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: HexagonISelLowering.cpp:3614
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
T
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:126
llvm::HexagonISD::EH_RETURN
@ EH_RETURN
Definition: HexagonISelLowering.h:67
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
llvm::HexagonTargetLowering::emitStoreConditional
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
Definition: HexagonISelLowering.cpp:3637
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:542
llvm::HexagonTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: HexagonISelLowering.cpp:3346
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::HexagonTargetLowering::LowerINLINEASM
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:658
llvm::HexagonISD::INSERT
@ INSERT
Definition: HexagonISelLowering.h:61
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::HexagonTargetLowering::LowerVECTOR_SHIFT
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2343
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:324
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:969
llvm::HexagonMachineFunctionInfo::setFirstNamedArgFrameIndex
void setFirstNamedArgFrameIndex(int v)
Definition: HexagonMachineFunctionInfo.h:55
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::HexagonTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: HexagonISelLowering.cpp:3333
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3313
llvm::TLSModel::GeneralDynamic
@ GeneralDynamic
Definition: CodeGen.h:43
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:696
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::TargetLoweringBase::setMinCmpXchgSizeInBits
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition: TargetLowering.h:2462
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1679
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::HexagonMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex()
Definition: HexagonMachineFunctionInfo.h:50
llvm::InlineAsm::Kind_Imm
@ Kind_Imm
Definition: InlineAsm.h:242
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1424
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:241
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
InlineAsm.h
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1050
llvm::HexagonISD::QCAT
@ QCAT
Definition: HexagonISelLowering.h:79
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9055
llvm::HexagonTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: HexagonISelLowering.cpp:3288
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:456
llvm::MVT::v2i1
@ v2i1
Definition: MachineValueType.h:65
llvm::HexagonTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: HexagonISelLowering.cpp:3174
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1490
llvm::SDVTList::NumVTs
unsigned int NumVTs
Definition: SelectionDAGNodes.h:80
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::HexagonISD::PFALSE
@ PFALSE
Definition: HexagonISelLowering.h:71
llvm::HexagonISD::READCYCLE
@ READCYCLE
Definition: HexagonISelLowering.h:69
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:371
ErrorHandling.h
llvm::HexagonRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: HexagonRegisterInfo.cpp:415
llvm::HexagonISD::COMBINE
@ COMBINE
Definition: HexagonISelLowering.h:55
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::IRBuilder<>
llvm::HexagonTargetLowering::HexagonTargetLowering
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
Definition: HexagonISelLowering.cpp:1434
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1341
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:913
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1364
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:766
llvm::DiagnosticInfo::getKind
int getKind() const
Definition: DiagnosticInfo.h:122
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1221
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:482
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3785
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2314
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
llvm::MemOp
Definition: TargetLowering.h:111
llvm::HexagonISD::SUBC
@ SUBC
Definition: HexagonISelLowering.h:40
llvm::SelectionDAG::getMemBasePlusOffset
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
Definition: SelectionDAG.cpp:6591
R4
#define R4(n)
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1267
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1419
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:68
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
NL
#define NL
Definition: DetailedRecordsBackend.cpp:31
llvm::HexagonTargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: HexagonISelLowering.cpp:2124
AlignLoads
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
Module.h
llvm::HexagonTargetLowering::LowerToTLSLocalExecModel
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1355
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::AttributeList
Definition: Attributes.h:408
llvm::SelectionDAG::getZeroExtendInReg
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition: SelectionDAG.cpp:1388
llvm::HexagonTargetObjectFile::isGlobalInSmallSection
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Definition: HexagonTargetObjectFile.cpp:198
llvm::HexagonTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
Definition: HexagonISelLowering.cpp:403
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
getUnderLyingObjectForBrevLdIntr
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
Definition: HexagonISelLowering.cpp:2039
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7756
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1254
llvm::HexagonISD::D2P
@ D2P
Definition: HexagonISelLowering.h:72
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::HexagonTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: HexagonISelLowering.cpp:185
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:736
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:297
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:4009
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2430
llvm::HexagonISD::OP_BEGIN
@ OP_BEGIN
Definition: HexagonISelLowering.h:35
MaxStoresPerMemmoveOptSizeCL
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
llvm::HexagonISD::VUNPACKU
@ VUNPACKU
Definition: HexagonISelLowering.h:94
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
llvm::MachineFrameInfo::setAdjustsStack
void setAdjustsStack(bool V)
Definition: MachineFrameInfo.h:602
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::HexagonTargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: HexagonISelLowering.cpp:3595
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1079
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:238
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::HexagonISD::TC_RETURN
@ TC_RETURN
Definition: HexagonISelLowering.h:66
llvm::HexagonTargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1029
llvm::LSBaseSDNode::isIndexed
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
Definition: SelectionDAGNodes.h:2302
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::HexagonTargetLowering::LowerROTL
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2348
llvm::SelectionDAG::getZExtOrTrunc
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
Definition: SelectionDAG.cpp:1373
HexagonTargetMachine.h
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:491
llvm::HexagonTargetLowering::LowerPREFETCH
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:706
llvm::ConstantPoolSDNode::getAlign
Align getAlign() const
Definition: SelectionDAGNodes.h:1909
CC_SkipOdd
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition: HexagonISelLowering.cpp:140
SelectionDAG.h
llvm::HexagonISD::RET_FLAG
@ RET_FLAG
Definition: HexagonISelLowering.h:50
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::SelectionDAG::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:454
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::SelectionDAG::getIndexedStore
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
Definition: SelectionDAG.cpp:7875
HEXAGON_LRFP_SIZE
#define HEXAGON_LRFP_SIZE
Definition: HexagonMCTargetDesc.h:30
llvm::HexagonII::MO_GOT
@ MO_GOT
MO_GOT - Indicates a GOT-relative relocation.
Definition: HexagonBaseInfo.h:183
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:661
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2350
llvm::TargetLowering::expandUnalignedStore
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
Definition: TargetLowering.cpp:8331
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:459
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::HexagonISD::V2Q
@ V2Q
Definition: HexagonISelLowering.h:74
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:905
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:161
llvm::HexagonISD::VINSERTW0
@ VINSERTW0
Definition: HexagonISelLowering.h:64
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:240
MachineRegisterInfo.h
llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2899
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
Definition: TargetLowering.h:2333
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1018
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:694
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Definition: TargetLowering.h:2422
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:115
llvm::MVT::integer_valuetypes
static auto integer_valuetypes()
Definition: MachineValueType.h:1422
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:923
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1384
llvm::HexagonTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: HexagonISelLowering.cpp:2151
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::TargetLoweringBase::AtomicExpansionKind::Expand
@ Expand
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:220
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:697
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7706
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1607
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3987
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:37
llvm::HexagonTargetLowering::LowerGLOBALADDRESS
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1217
llvm::HexagonTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: HexagonISelLowering.cpp:3364
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition: TargetLowering.h:1158
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
GlobalValue.h
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1125
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
TargetMachine.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::HexagonISD::VALIGNADDR
@ VALIGNADDR
Definition: HexagonISelLowering.h:86
llvm::DXIL::OpCode
OpCode
Definition: DXILConstants.h:18
EnableHexSDNodeSched
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:713
llvm::HexagonTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: HexagonISelLowering.cpp:3258
llvm::HexagonII::MO_IEGOT
@ MO_IEGOT
Definition: HexagonBaseInfo.h:206
llvm::HexagonTargetLowering::LowerATOMIC_FENCE
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1211
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2286
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::PHINode::getIncomingValue
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
Definition: Instructions.h:2760
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
EnableFastMath
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Fast Math processing"))
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85