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HexagonISelLowering.cpp
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1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
10 // into a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonISelLowering.h"
15 #include "Hexagon.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/APInt.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/IR/BasicBlock.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/DataLayout.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalValue.h"
40 #include "llvm/IR/InlineAsm.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/IntrinsicInst.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/IntrinsicsHexagon.h"
45 #include "llvm/IR/Module.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/IR/Value.h"
48 #include "llvm/MC/MCRegisterInfo.h"
49 #include "llvm/Support/Casting.h"
50 #include "llvm/Support/CodeGen.h"
52 #include "llvm/Support/Debug.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <cstddef>
60 #include <cstdint>
61 #include <limits>
62 #include <utility>
63 
64 using namespace llvm;
65 
66 #define DEBUG_TYPE "hexagon-lowering"
67 
68 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
69  cl::init(true), cl::Hidden,
70  cl::desc("Control jump table emission on Hexagon target"));
71 
72 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
74  cl::desc("Enable Hexagon SDNode scheduling"));
75 
76 static cl::opt<bool> EnableFastMath("ffast-math",
78  cl::desc("Enable Fast Math processing"));
79 
80 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
82  cl::desc("Set minimum jump tables"));
83 
84 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
86  cl::desc("Max #stores to inline memcpy"));
87 
88 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
90  cl::desc("Max #stores to inline memcpy"));
91 
92 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
94  cl::desc("Max #stores to inline memmove"));
95 
96 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
98  cl::desc("Max #stores to inline memmove"));
99 
100 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
102  cl::desc("Max #stores to inline memset"));
103 
104 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
106  cl::desc("Max #stores to inline memset"));
107 
108 static cl::opt<bool> AlignLoads("hexagon-align-loads",
109  cl::Hidden, cl::init(false),
110  cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
111 
112 static cl::opt<bool>
113  DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden,
114  cl::init(false),
115  cl::desc("Disable minimum alignment of 1 for "
116  "arguments passed by value on stack"));
117 
118 namespace {
119 
120  class HexagonCCState : public CCState {
121  unsigned NumNamedVarArgParams = 0;
122 
123  public:
124  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
126  unsigned NumNamedArgs)
127  : CCState(CC, IsVarArg, MF, locs, C),
128  NumNamedVarArgParams(NumNamedArgs) {}
129  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
130  };
131 
132 } // end anonymous namespace
133 
134 
135 // Implement calling convention for Hexagon.
136 
137 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
138  CCValAssign::LocInfo &LocInfo,
139  ISD::ArgFlagsTy &ArgFlags, CCState &State) {
140  static const MCPhysReg ArgRegs[] = {
141  Hexagon::R0, Hexagon::R1, Hexagon::R2,
142  Hexagon::R3, Hexagon::R4, Hexagon::R5
143  };
144  const unsigned NumArgRegs = array_lengthof(ArgRegs);
145  unsigned RegNum = State.getFirstUnallocated(ArgRegs);
146 
147  // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
148  if (RegNum != NumArgRegs && RegNum % 2 == 1)
149  State.AllocateReg(ArgRegs[RegNum]);
150 
151  // Always return false here, as this function only makes sure that the first
152  // unallocated register has an even register number and does not actually
153  // allocate a register for the current argument.
154  return false;
155 }
156 
157 #include "HexagonGenCallingConv.inc"
158 
159 
160 SDValue
162  const {
163  return SDValue();
164 }
165 
166 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
167 /// by "Src" to address "Dst" of size "Size". Alignment information is
168 /// specified by the specific parameter attribute. The copy will be passed as
169 /// a byval function parameter. Sometimes what we are copying is the end of a
170 /// larger object, the part that does not fit in registers.
172  SDValue Chain, ISD::ArgFlagsTy Flags,
173  SelectionDAG &DAG, const SDLoc &dl) {
174  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
175  return DAG.getMemcpy(
176  Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(),
177  /*isVolatile=*/false, /*AlwaysInline=*/false,
178  /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo());
179 }
180 
181 bool
183  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
185  LLVMContext &Context) const {
187  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
188 
190  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
191  return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
192 }
193 
194 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
195 // passed by value, the function prototype is modified to return void and
196 // the value is stored in memory pointed by a pointer passed by caller.
197 SDValue
199  bool IsVarArg,
201  const SmallVectorImpl<SDValue> &OutVals,
202  const SDLoc &dl, SelectionDAG &DAG) const {
203  // CCValAssign - represent the assignment of the return value to locations.
205 
206  // CCState - Info about the registers and stack slot.
207  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
208  *DAG.getContext());
209 
210  // Analyze return values of ISD::RET
211  if (Subtarget.useHVXOps())
212  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
213  else
214  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
215 
216  SDValue Flag;
217  SmallVector<SDValue, 4> RetOps(1, Chain);
218 
219  // Copy the result values into the output registers.
220  for (unsigned i = 0; i != RVLocs.size(); ++i) {
221  CCValAssign &VA = RVLocs[i];
222 
223  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
224 
225  // Guarantee that all emitted copies are stuck together with flags.
226  Flag = Chain.getValue(1);
227  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
228  }
229 
230  RetOps[0] = Chain; // Update chain.
231 
232  // Add the flag if we have it.
233  if (Flag.getNode())
234  RetOps.push_back(Flag);
235 
236  return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
237 }
238 
240  // If either no tail call or told not to tail call at all, don't.
241  return CI->isTailCall();
242 }
243 
245  const char* RegName, LLT VT, const MachineFunction &) const {
246  // Just support r19, the linux kernel uses it.
248  .Case("r0", Hexagon::R0)
249  .Case("r1", Hexagon::R1)
250  .Case("r2", Hexagon::R2)
251  .Case("r3", Hexagon::R3)
252  .Case("r4", Hexagon::R4)
253  .Case("r5", Hexagon::R5)
254  .Case("r6", Hexagon::R6)
255  .Case("r7", Hexagon::R7)
256  .Case("r8", Hexagon::R8)
257  .Case("r9", Hexagon::R9)
258  .Case("r10", Hexagon::R10)
259  .Case("r11", Hexagon::R11)
260  .Case("r12", Hexagon::R12)
261  .Case("r13", Hexagon::R13)
262  .Case("r14", Hexagon::R14)
263  .Case("r15", Hexagon::R15)
264  .Case("r16", Hexagon::R16)
265  .Case("r17", Hexagon::R17)
266  .Case("r18", Hexagon::R18)
267  .Case("r19", Hexagon::R19)
268  .Case("r20", Hexagon::R20)
269  .Case("r21", Hexagon::R21)
270  .Case("r22", Hexagon::R22)
271  .Case("r23", Hexagon::R23)
272  .Case("r24", Hexagon::R24)
273  .Case("r25", Hexagon::R25)
274  .Case("r26", Hexagon::R26)
275  .Case("r27", Hexagon::R27)
276  .Case("r28", Hexagon::R28)
277  .Case("r29", Hexagon::R29)
278  .Case("r30", Hexagon::R30)
279  .Case("r31", Hexagon::R31)
280  .Case("r1:0", Hexagon::D0)
281  .Case("r3:2", Hexagon::D1)
282  .Case("r5:4", Hexagon::D2)
283  .Case("r7:6", Hexagon::D3)
284  .Case("r9:8", Hexagon::D4)
285  .Case("r11:10", Hexagon::D5)
286  .Case("r13:12", Hexagon::D6)
287  .Case("r15:14", Hexagon::D7)
288  .Case("r17:16", Hexagon::D8)
289  .Case("r19:18", Hexagon::D9)
290  .Case("r21:20", Hexagon::D10)
291  .Case("r23:22", Hexagon::D11)
292  .Case("r25:24", Hexagon::D12)
293  .Case("r27:26", Hexagon::D13)
294  .Case("r29:28", Hexagon::D14)
295  .Case("r31:30", Hexagon::D15)
296  .Case("sp", Hexagon::R29)
297  .Case("fp", Hexagon::R30)
298  .Case("lr", Hexagon::R31)
299  .Case("p0", Hexagon::P0)
300  .Case("p1", Hexagon::P1)
301  .Case("p2", Hexagon::P2)
302  .Case("p3", Hexagon::P3)
303  .Case("sa0", Hexagon::SA0)
304  .Case("lc0", Hexagon::LC0)
305  .Case("sa1", Hexagon::SA1)
306  .Case("lc1", Hexagon::LC1)
307  .Case("m0", Hexagon::M0)
308  .Case("m1", Hexagon::M1)
309  .Case("usr", Hexagon::USR)
310  .Case("ugp", Hexagon::UGP)
311  .Case("cs0", Hexagon::CS0)
312  .Case("cs1", Hexagon::CS1)
313  .Default(Register());
314  if (Reg)
315  return Reg;
316 
317  report_fatal_error("Invalid register name global variable");
318 }
319 
320 /// LowerCallResult - Lower the result values of an ISD::CALL into the
321 /// appropriate copies out of appropriate physical registers. This assumes that
322 /// Chain/Glue are the input chain/glue to use, and that TheCall is the call
323 /// being lowered. Returns a SDNode with the same number of values as the
324 /// ISD::CALL.
326  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
327  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
329  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
330  // Assign locations to each value returned by this call.
332 
333  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
334  *DAG.getContext());
335 
336  if (Subtarget.useHVXOps())
337  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
338  else
339  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
340 
341  // Copy all of the result registers out of their specified physreg.
342  for (unsigned i = 0; i != RVLocs.size(); ++i) {
343  SDValue RetVal;
344  if (RVLocs[i].getValVT() == MVT::i1) {
345  // Return values of type MVT::i1 require special handling. The reason
346  // is that MVT::i1 is associated with the PredRegs register class, but
347  // values of that type are still returned in R0. Generate an explicit
348  // copy into a predicate register from R0, and treat the value of the
349  // predicate register as the call result.
350  auto &MRI = DAG.getMachineFunction().getRegInfo();
351  SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
352  MVT::i32, Glue);
353  // FR0 = (Value, Chain, Glue)
354  Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
355  SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
356  FR0.getValue(0), FR0.getValue(2));
357  // TPR = (Chain, Glue)
358  // Don't glue this CopyFromReg, because it copies from a virtual
359  // register. If it is glued to the call, InstrEmitter will add it
360  // as an implicit def to the call (EmitMachineNode).
361  RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
362  Glue = TPR.getValue(1);
363  Chain = TPR.getValue(0);
364  } else {
365  RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
366  RVLocs[i].getValVT(), Glue);
367  Glue = RetVal.getValue(2);
368  Chain = RetVal.getValue(1);
369  }
370  InVals.push_back(RetVal.getValue(0));
371  }
372 
373  return Chain;
374 }
375 
376 /// LowerCall - Functions arguments are copied from virtual regs to
377 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
378 SDValue
380  SmallVectorImpl<SDValue> &InVals) const {
381  SelectionDAG &DAG = CLI.DAG;
382  SDLoc &dl = CLI.DL;
384  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
386  SDValue Chain = CLI.Chain;
387  SDValue Callee = CLI.Callee;
388  CallingConv::ID CallConv = CLI.CallConv;
389  bool IsVarArg = CLI.IsVarArg;
390  bool DoesNotReturn = CLI.DoesNotReturn;
391 
392  bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
394  MachineFrameInfo &MFI = MF.getFrameInfo();
395  auto PtrVT = getPointerTy(MF.getDataLayout());
396 
397  unsigned NumParams = CLI.CB ? CLI.CB->getFunctionType()->getNumParams() : 0;
398  if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
399  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
400 
401  // Linux ABI treats var-arg calls the same way as regular ones.
402  bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
403 
404  // Analyze operands of the call, assigning locations to each operand.
406  HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs, *DAG.getContext(),
407  NumParams);
408 
409  if (Subtarget.useHVXOps())
410  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
411  else if (DisableArgsMinAlignment)
412  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_Legacy);
413  else
414  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
415 
416  if (CLI.IsTailCall) {
417  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
419  IsVarArg, IsStructRet, StructAttrFlag, Outs,
420  OutVals, Ins, DAG);
421  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
422  CCValAssign &VA = ArgLocs[i];
423  if (VA.isMemLoc()) {
424  CLI.IsTailCall = false;
425  break;
426  }
427  }
428  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
429  : "Argument must be passed on stack. "
430  "Not eligible for Tail Call\n"));
431  }
432  // Get a count of how many bytes are to be pushed on the stack.
433  unsigned NumBytes = CCInfo.getNextStackOffset();
435  SmallVector<SDValue, 8> MemOpChains;
436 
437  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
438  SDValue StackPtr =
439  DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
440 
441  bool NeedsArgAlign = false;
442  Align LargestAlignSeen;
443  // Walk the register/memloc assignments, inserting copies/loads.
444  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
445  CCValAssign &VA = ArgLocs[i];
446  SDValue Arg = OutVals[i];
447  ISD::ArgFlagsTy Flags = Outs[i].Flags;
448  // Record if we need > 8 byte alignment on an argument.
449  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
450  NeedsArgAlign |= ArgAlign;
451 
452  // Promote the value if needed.
453  switch (VA.getLocInfo()) {
454  default:
455  // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
456  llvm_unreachable("Unknown loc info!");
457  case CCValAssign::Full:
458  break;
459  case CCValAssign::BCvt:
460  Arg = DAG.getBitcast(VA.getLocVT(), Arg);
461  break;
462  case CCValAssign::SExt:
463  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
464  break;
465  case CCValAssign::ZExt:
466  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
467  break;
468  case CCValAssign::AExt:
469  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
470  break;
471  }
472 
473  if (VA.isMemLoc()) {
474  unsigned LocMemOffset = VA.getLocMemOffset();
475  SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
476  StackPtr.getValueType());
477  MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
478  if (ArgAlign)
479  LargestAlignSeen = std::max(
480  LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8));
481  if (Flags.isByVal()) {
482  // The argument is a struct passed by value. According to LLVM, "Arg"
483  // is a pointer.
484  MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
485  Flags, DAG, dl));
486  } else {
488  DAG.getMachineFunction(), LocMemOffset);
489  SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
490  MemOpChains.push_back(S);
491  }
492  continue;
493  }
494 
495  // Arguments that can be passed on register must be kept at RegsToPass
496  // vector.
497  if (VA.isRegLoc())
498  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
499  }
500 
501  if (NeedsArgAlign && Subtarget.hasV60Ops()) {
502  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
503  Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass));
504  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
505  MFI.ensureMaxAlignment(LargestAlignSeen);
506  }
507  // Transform all store nodes into one single node because all store
508  // nodes are independent of each other.
509  if (!MemOpChains.empty())
510  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
511 
512  SDValue Glue;
513  if (!CLI.IsTailCall) {
514  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
515  Glue = Chain.getValue(1);
516  }
517 
518  // Build a sequence of copy-to-reg nodes chained together with token
519  // chain and flag operands which copy the outgoing args into registers.
520  // The Glue is necessary since all emitted instructions must be
521  // stuck together.
522  if (!CLI.IsTailCall) {
523  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
524  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
525  RegsToPass[i].second, Glue);
526  Glue = Chain.getValue(1);
527  }
528  } else {
529  // For tail calls lower the arguments to the 'real' stack slot.
530  //
531  // Force all the incoming stack arguments to be loaded from the stack
532  // before any new outgoing arguments are stored to the stack, because the
533  // outgoing stack slots may alias the incoming argument stack slots, and
534  // the alias isn't otherwise explicit. This is slightly more conservative
535  // than necessary, because it means that each store effectively depends
536  // on every argument instead of just those arguments it would clobber.
537  //
538  // Do not flag preceding copytoreg stuff together with the following stuff.
539  Glue = SDValue();
540  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
541  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
542  RegsToPass[i].second, Glue);
543  Glue = Chain.getValue(1);
544  }
545  Glue = SDValue();
546  }
547 
548  bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
549  unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
550 
551  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
552  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
553  // node so that legalize doesn't hack it.
554  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
555  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
556  } else if (ExternalSymbolSDNode *S =
557  dyn_cast<ExternalSymbolSDNode>(Callee)) {
558  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
559  }
560 
561  // Returns a chain & a flag for retval copy to use.
562  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
564  Ops.push_back(Chain);
565  Ops.push_back(Callee);
566 
567  // Add argument registers to the end of the list so that they are
568  // known live into the call.
569  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
570  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
571  RegsToPass[i].second.getValueType()));
572  }
573 
574  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
575  assert(Mask && "Missing call preserved mask for calling convention");
576  Ops.push_back(DAG.getRegisterMask(Mask));
577 
578  if (Glue.getNode())
579  Ops.push_back(Glue);
580 
581  if (CLI.IsTailCall) {
582  MFI.setHasTailCall();
583  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
584  }
585 
586  // Set this here because we need to know this for "hasFP" in frame lowering.
587  // The target-independent code calls getFrameRegister before setting it, and
588  // getFrameRegister uses hasFP to determine whether the function has FP.
589  MFI.setHasCalls(true);
590 
591  unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
592  Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
593  Glue = Chain.getValue(1);
594 
595  // Create the CALLSEQ_END node.
596  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
597  DAG.getIntPtrConstant(0, dl, true), Glue, dl);
598  Glue = Chain.getValue(1);
599 
600  // Handle result values, copying them out of physregs into vregs that we
601  // return.
602  return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
603  InVals, OutVals, Callee);
604 }
605 
606 /// Returns true by value, base pointer and offset pointer and addressing
607 /// mode by reference if this node can be combined with a load / store to
608 /// form a post-indexed load / store.
611  SelectionDAG &DAG) const {
612  LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
613  if (!LSN)
614  return false;
615  EVT VT = LSN->getMemoryVT();
616  if (!VT.isSimple())
617  return false;
618  bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
619  VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
620  VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
621  VT == MVT::v4i16 || VT == MVT::v8i8 ||
622  Subtarget.isHVXVectorType(VT.getSimpleVT());
623  if (!IsLegalType)
624  return false;
625 
626  if (Op->getOpcode() != ISD::ADD)
627  return false;
628  Base = Op->getOperand(0);
629  Offset = Op->getOperand(1);
630  if (!isa<ConstantSDNode>(Offset.getNode()))
631  return false;
632  AM = ISD::POST_INC;
633 
634  int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
635  return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
636 }
637 
638 SDValue
641  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
642  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
643  unsigned LR = HRI.getRARegister();
644 
645  if ((Op.getOpcode() != ISD::INLINEASM &&
646  Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
647  return Op;
648 
649  unsigned NumOps = Op.getNumOperands();
650  if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
651  --NumOps; // Ignore the flag operand.
652 
653  for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
654  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
655  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
656  ++i; // Skip the ID value.
657 
658  switch (InlineAsm::getKind(Flags)) {
659  default:
660  llvm_unreachable("Bad flags!");
662  case InlineAsm::Kind_Imm:
663  case InlineAsm::Kind_Mem:
664  i += NumVals;
665  break;
669  for (; NumVals; --NumVals, ++i) {
670  unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
671  if (Reg != LR)
672  continue;
673  HMFI.setHasClobberLR(true);
674  return Op;
675  }
676  break;
677  }
678  }
679  }
680 
681  return Op;
682 }
683 
684 // Need to transform ISD::PREFETCH into something that doesn't inherit
685 // all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
686 // SDNPMayStore.
688  SelectionDAG &DAG) const {
689  SDValue Chain = Op.getOperand(0);
690  SDValue Addr = Op.getOperand(1);
691  // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
692  // if the "reg" is fed by an "add".
693  SDLoc DL(Op);
694  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
695  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
696 }
697 
698 // Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
699 // is marked as having side-effects, while the register read on Hexagon does
700 // not have any. TableGen refuses to accept the direct pattern from that node
701 // to the A4_tfrcpp.
703  SelectionDAG &DAG) const {
704  SDValue Chain = Op.getOperand(0);
705  SDLoc dl(Op);
707  return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
708 }
709 
711  SelectionDAG &DAG) const {
712  SDValue Chain = Op.getOperand(0);
713  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
714  // Lower the hexagon_prefetch builtin to DCFETCH, as above.
715  if (IntNo == Intrinsic::hexagon_prefetch) {
716  SDValue Addr = Op.getOperand(2);
717  SDLoc DL(Op);
718  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
719  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
720  }
721  return SDValue();
722 }
723 
724 SDValue
726  SelectionDAG &DAG) const {
727  SDValue Chain = Op.getOperand(0);
728  SDValue Size = Op.getOperand(1);
729  SDValue Align = Op.getOperand(2);
730  SDLoc dl(Op);
731 
732  ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
733  assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
734 
735  unsigned A = AlignConst->getSExtValue();
736  auto &HFI = *Subtarget.getFrameLowering();
737  // "Zero" means natural stack alignment.
738  if (A == 0)
739  A = HFI.getStackAlign().value();
740 
741  LLVM_DEBUG({
742  dbgs () << __func__ << " Align: " << A << " Size: ";
743  Size.getNode()->dump(&DAG);
744  dbgs() << "\n";
745  });
746 
747  SDValue AC = DAG.getConstant(A, dl, MVT::i32);
749  SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
750 
751  DAG.ReplaceAllUsesOfValueWith(Op, AA);
752  return AA;
753 }
754 
756  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
757  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
758  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
760  MachineFrameInfo &MFI = MF.getFrameInfo();
762 
763  // Linux ABI treats var-arg calls the same way as regular ones.
764  bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
765 
766  // Assign locations to all of the incoming arguments.
768  HexagonCCState CCInfo(CallConv, TreatAsVarArg, MF, ArgLocs,
769  *DAG.getContext(),
771 
772  if (Subtarget.useHVXOps())
773  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
774  else if (DisableArgsMinAlignment)
775  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_Legacy);
776  else
777  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
778 
779  // For LLVM, in the case when returning a struct by value (>8byte),
780  // the first argument is a pointer that points to the location on caller's
781  // stack where the return value will be stored. For Hexagon, the location on
782  // caller's stack is passed only when the struct size is smaller than (and
783  // equal to) 8 bytes. If not, no address will be passed into callee and
784  // callee return the result direclty through R0/R1.
785  auto NextSingleReg = [] (const TargetRegisterClass &RC, unsigned Reg) {
786  switch (RC.getID()) {
787  case Hexagon::IntRegsRegClassID:
788  return Reg - Hexagon::R0 + 1;
789  case Hexagon::DoubleRegsRegClassID:
790  return (Reg - Hexagon::D0 + 1) * 2;
791  case Hexagon::HvxVRRegClassID:
792  return Reg - Hexagon::V0 + 1;
793  case Hexagon::HvxWRRegClassID:
794  return (Reg - Hexagon::W0 + 1) * 2;
795  }
796  llvm_unreachable("Unexpected register class");
797  };
798 
799  auto &HFL = const_cast<HexagonFrameLowering&>(*Subtarget.getFrameLowering());
800  auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
801  HFL.FirstVarArgSavedReg = 0;
803 
804  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
805  CCValAssign &VA = ArgLocs[i];
806  ISD::ArgFlagsTy Flags = Ins[i].Flags;
807  bool ByVal = Flags.isByVal();
808 
809  // Arguments passed in registers:
810  // 1. 32- and 64-bit values and HVX vectors are passed directly,
811  // 2. Large structs are passed via an address, and the address is
812  // passed in a register.
813  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
814  llvm_unreachable("ByValSize must be bigger than 8 bytes");
815 
816  bool InReg = VA.isRegLoc() &&
817  (!ByVal || (ByVal && Flags.getByValSize() > 8));
818 
819  if (InReg) {
820  MVT RegVT = VA.getLocVT();
821  if (VA.getLocInfo() == CCValAssign::BCvt)
822  RegVT = VA.getValVT();
823 
824  const TargetRegisterClass *RC = getRegClassFor(RegVT);
826  SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
827 
828  // Treat values of type MVT::i1 specially: they are passed in
829  // registers of type i32, but they need to remain as values of
830  // type i1 for consistency of the argument lowering.
831  if (VA.getValVT() == MVT::i1) {
832  assert(RegVT.getSizeInBits() <= 32);
833  SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
834  Copy, DAG.getConstant(1, dl, RegVT));
835  Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
836  ISD::SETNE);
837  } else {
838 #ifndef NDEBUG
839  unsigned RegSize = RegVT.getSizeInBits();
840  assert(RegSize == 32 || RegSize == 64 ||
841  Subtarget.isHVXVectorType(RegVT));
842 #endif
843  }
844  InVals.push_back(Copy);
845  MRI.addLiveIn(VA.getLocReg(), VReg);
846  HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.getLocReg());
847  } else {
848  assert(VA.isMemLoc() && "Argument should be passed in memory");
849 
850  // If it's a byval parameter, then we need to compute the
851  // "real" size, not the size of the pointer.
852  unsigned ObjSize = Flags.isByVal()
853  ? Flags.getByValSize()
854  : VA.getLocVT().getStoreSizeInBits() / 8;
855 
856  // Create the frame index object for this incoming parameter.
858  int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
859  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
860 
861  if (Flags.isByVal()) {
862  // If it's a pass-by-value aggregate, then do not dereference the stack
863  // location. Instead, we should generate a reference to the stack
864  // location.
865  InVals.push_back(FIN);
866  } else {
867  SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
869  InVals.push_back(L);
870  }
871  }
872  }
873 
874  if (IsVarArg && Subtarget.isEnvironmentMusl()) {
875  for (int i = HFL.FirstVarArgSavedReg; i < 6; i++)
876  MRI.addLiveIn(Hexagon::R0+i);
877  }
878 
879  if (IsVarArg && Subtarget.isEnvironmentMusl()) {
880  HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
881  HMFI.setLastNamedArgFrameIndex(-int(MFI.getNumFixedObjects()));
882 
883  // Create Frame index for the start of register saved area.
884  int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
885  bool RequiresPadding = (NumVarArgRegs & 1);
886  int RegSaveAreaSizePlusPadding = RequiresPadding
887  ? (NumVarArgRegs + 1) * 4
888  : NumVarArgRegs * 4;
889 
890  if (RegSaveAreaSizePlusPadding > 0) {
891  // The offset to saved register area should be 8 byte aligned.
892  int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
893  if (!(RegAreaStart % 8))
894  RegAreaStart = (RegAreaStart + 7) & -8;
895 
896  int RegSaveAreaFrameIndex =
897  MFI.CreateFixedObject(RegSaveAreaSizePlusPadding, RegAreaStart, true);
898  HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex);
899 
900  // This will point to the next argument passed via stack.
901  int Offset = RegAreaStart + RegSaveAreaSizePlusPadding;
902  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
903  HMFI.setVarArgsFrameIndex(FI);
904  } else {
905  // This will point to the next argument passed via stack, when
906  // there is no saved register area.
907  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
908  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
909  HMFI.setRegSavedAreaStartFrameIndex(FI);
910  HMFI.setVarArgsFrameIndex(FI);
911  }
912  }
913 
914 
915  if (IsVarArg && !Subtarget.isEnvironmentMusl()) {
916  // This will point to the next argument passed via stack.
917  int Offset = HEXAGON_LRFP_SIZE + CCInfo.getNextStackOffset();
918  int FI = MFI.CreateFixedObject(Hexagon_PointerSize, Offset, true);
919  HMFI.setVarArgsFrameIndex(FI);
920  }
921 
922  return Chain;
923 }
924 
925 SDValue
927  // VASTART stores the address of the VarArgsFrameIndex slot into the
928  // memory location argument.
932  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
933 
934  if (!Subtarget.isEnvironmentMusl()) {
935  return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
936  MachinePointerInfo(SV));
937  }
938  auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
939  auto &HFL = *Subtarget.getFrameLowering();
940  SDLoc DL(Op);
942 
943  // Get frame index of va_list.
944  SDValue FIN = Op.getOperand(1);
945 
946  // If first Vararg register is odd, add 4 bytes to start of
947  // saved register area to point to the first register location.
948  // This is because the saved register area has to be 8 byte aligned.
949  // Incase of an odd start register, there will be 4 bytes of padding in
950  // the beginning of saved register area. If all registers area used up,
951  // the following condition will handle it correctly.
952  SDValue SavedRegAreaStartFrameIndex =
953  DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32);
954 
955  auto PtrVT = getPointerTy(DAG.getDataLayout());
956 
957  if (HFL.FirstVarArgSavedReg & 1)
958  SavedRegAreaStartFrameIndex =
959  DAG.getNode(ISD::ADD, DL, PtrVT,
960  DAG.getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(),
961  MVT::i32),
962  DAG.getIntPtrConstant(4, DL));
963 
964  // Store the saved register area start pointer.
965  SDValue Store =
966  DAG.getStore(Op.getOperand(0), DL,
967  SavedRegAreaStartFrameIndex,
968  FIN, MachinePointerInfo(SV));
969  MemOps.push_back(Store);
970 
971  // Store saved register area end pointer.
972  FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
973  FIN, DAG.getIntPtrConstant(4, DL));
974  Store = DAG.getStore(Op.getOperand(0), DL,
975  DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
976  PtrVT),
977  FIN, MachinePointerInfo(SV, 4));
978  MemOps.push_back(Store);
979 
980  // Store overflow area pointer.
981  FIN = DAG.getNode(ISD::ADD, DL, PtrVT,
982  FIN, DAG.getIntPtrConstant(4, DL));
983  Store = DAG.getStore(Op.getOperand(0), DL,
984  DAG.getFrameIndex(FuncInfo.getVarArgsFrameIndex(),
985  PtrVT),
986  FIN, MachinePointerInfo(SV, 8));
987  MemOps.push_back(Store);
988 
989  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
990 }
991 
992 SDValue
994  // Assert that the linux ABI is enabled for the current compilation.
995  assert(Subtarget.isEnvironmentMusl() && "Linux ABI should be enabled");
996  SDValue Chain = Op.getOperand(0);
997  SDValue DestPtr = Op.getOperand(1);
998  SDValue SrcPtr = Op.getOperand(2);
999  const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1000  const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1001  SDLoc DL(Op);
1002  // Size of the va_list is 12 bytes as it has 3 pointers. Therefore,
1003  // we need to memcopy 12 bytes from va_list to another similar list.
1004  return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr,
1005  DAG.getIntPtrConstant(12, DL), Align(4),
1006  /*isVolatile*/ false, false, false,
1007  MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
1008 }
1009 
1011  const SDLoc &dl(Op);
1012  SDValue LHS = Op.getOperand(0);
1013  SDValue RHS = Op.getOperand(1);
1014  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1015  MVT ResTy = ty(Op);
1016  MVT OpTy = ty(LHS);
1017 
1018  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1019  MVT ElemTy = OpTy.getVectorElementType();
1020  assert(ElemTy.isScalarInteger());
1021  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1022  OpTy.getVectorNumElements());
1023  return DAG.getSetCC(dl, ResTy,
1024  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
1025  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
1026  }
1027 
1028  // Treat all other vector types as legal.
1029  if (ResTy.isVector())
1030  return Op;
1031 
1032  // Comparisons of short integers should use sign-extend, not zero-extend,
1033  // since we can represent small negative values in the compare instructions.
1034  // The LLVM default is to use zero-extend arbitrarily in these cases.
1035  auto isSExtFree = [this](SDValue N) {
1036  switch (N.getOpcode()) {
1037  case ISD::TRUNCATE: {
1038  // A sign-extend of a truncate of a sign-extend is free.
1039  SDValue Op = N.getOperand(0);
1040  if (Op.getOpcode() != ISD::AssertSext)
1041  return false;
1042  EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
1043  unsigned ThisBW = ty(N).getSizeInBits();
1044  unsigned OrigBW = OrigTy.getSizeInBits();
1045  // The type that was sign-extended to get the AssertSext must be
1046  // narrower than the type of N (so that N has still the same value
1047  // as the original).
1048  return ThisBW >= OrigBW;
1049  }
1050  case ISD::LOAD:
1051  // We have sign-extended loads.
1052  return true;
1053  }
1054  return false;
1055  };
1056 
1057  if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1058  ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1059  bool IsNegative = C && C->getAPIntValue().isNegative();
1060  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
1061  return DAG.getSetCC(dl, ResTy,
1062  DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
1063  DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
1064  }
1065 
1066  return SDValue();
1067 }
1068 
1069 SDValue
1071  SDValue PredOp = Op.getOperand(0);
1072  SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1073  MVT OpTy = ty(Op1);
1074  const SDLoc &dl(Op);
1075 
1076  if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1077  MVT ElemTy = OpTy.getVectorElementType();
1078  assert(ElemTy.isScalarInteger());
1079  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
1080  OpTy.getVectorNumElements());
1081  // Generate (trunc (select (_, sext, sext))).
1082  return DAG.getSExtOrTrunc(
1083  DAG.getSelect(dl, WideTy, PredOp,
1084  DAG.getSExtOrTrunc(Op1, dl, WideTy),
1085  DAG.getSExtOrTrunc(Op2, dl, WideTy)),
1086  dl, OpTy);
1087  }
1088 
1089  return SDValue();
1090 }
1091 
1092 SDValue
1094  EVT ValTy = Op.getValueType();
1095  ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1096  Constant *CVal = nullptr;
1097  bool isVTi1Type = false;
1098  if (auto *CV = dyn_cast<ConstantVector>(CPN->getConstVal())) {
1099  if (cast<VectorType>(CV->getType())->getElementType()->isIntegerTy(1)) {
1100  IRBuilder<> IRB(CV->getContext());
1101  SmallVector<Constant*, 128> NewConst;
1102  unsigned VecLen = CV->getNumOperands();
1103  assert(isPowerOf2_32(VecLen) &&
1104  "conversion only supported for pow2 VectorSize");
1105  for (unsigned i = 0; i < VecLen; ++i)
1106  NewConst.push_back(IRB.getInt8(CV->getOperand(i)->isZeroValue()));
1107 
1108  CVal = ConstantVector::get(NewConst);
1109  isVTi1Type = true;
1110  }
1111  }
1112  Align Alignment = CPN->getAlign();
1113  bool IsPositionIndependent = isPositionIndependent();
1114  unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1115 
1116  unsigned Offset = 0;
1117  SDValue T;
1118  if (CPN->isMachineConstantPoolEntry())
1119  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Alignment,
1120  Offset, TF);
1121  else if (isVTi1Type)
1122  T = DAG.getTargetConstantPool(CVal, ValTy, Alignment, Offset, TF);
1123  else
1124  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Alignment, Offset,
1125  TF);
1126 
1127  assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&
1128  "Inconsistent target flag encountered");
1129 
1130  if (IsPositionIndependent)
1131  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1132  return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1133 }
1134 
1135 SDValue
1137  EVT VT = Op.getValueType();
1138  int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1139  if (isPositionIndependent()) {
1141  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1142  }
1143 
1144  SDValue T = DAG.getTargetJumpTable(Idx, VT);
1145  return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1146 }
1147 
1148 SDValue
1150  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1151  MachineFunction &MF = DAG.getMachineFunction();
1152  MachineFrameInfo &MFI = MF.getFrameInfo();
1153  MFI.setReturnAddressIsTaken(true);
1154 
1156  return SDValue();
1157 
1158  EVT VT = Op.getValueType();
1159  SDLoc dl(Op);
1160  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1161  if (Depth) {
1162  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1163  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1164  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1165  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1166  MachinePointerInfo());
1167  }
1168 
1169  // Return LR, which contains the return address. Mark it an implicit live-in.
1170  unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1171  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1172 }
1173 
1174 SDValue
1176  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1178  MFI.setFrameAddressIsTaken(true);
1179 
1180  EVT VT = Op.getValueType();
1181  SDLoc dl(Op);
1182  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1183  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1184  HRI.getFrameRegister(), VT);
1185  while (Depth--)
1186  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1187  MachinePointerInfo());
1188  return FrameAddr;
1189 }
1190 
1191 SDValue
1193  SDLoc dl(Op);
1194  return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1195 }
1196 
1197 SDValue
1199  SDLoc dl(Op);
1200  auto *GAN = cast<GlobalAddressSDNode>(Op);
1201  auto PtrVT = getPointerTy(DAG.getDataLayout());
1202  auto *GV = GAN->getGlobal();
1203  int64_t Offset = GAN->getOffset();
1204 
1205  auto &HLOF = *HTM.getObjFileLowering();
1207 
1208  if (RM == Reloc::Static) {
1209  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1210  const GlobalObject *GO = GV->getBaseObject();
1211  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1212  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1213  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1214  }
1215 
1216  bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1217  if (UsePCRel) {
1218  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1220  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1221  }
1222 
1223  // Use GOT index.
1224  SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1225  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1226  SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1227  return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1228 }
1229 
1230 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1231 SDValue
1233  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1234  SDLoc dl(Op);
1235  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1236 
1238  if (RM == Reloc::Static) {
1239  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1240  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1241  }
1242 
1243  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1244  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1245 }
1246 
1247 SDValue
1249  const {
1250  EVT PtrVT = getPointerTy(DAG.getDataLayout());
1253  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1254 }
1255 
1256 SDValue
1258  GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1259  unsigned char OperandFlags) const {
1260  MachineFunction &MF = DAG.getMachineFunction();
1261  MachineFrameInfo &MFI = MF.getFrameInfo();
1262  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1263  SDLoc dl(GA);
1264  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1265  GA->getValueType(0),
1266  GA->getOffset(),
1267  OperandFlags);
1268  // Create Operands for the call.The Operands should have the following:
1269  // 1. Chain SDValue
1270  // 2. Callee which in this case is the Global address value.
1271  // 3. Registers live into the call.In this case its R0, as we
1272  // have just one argument to be passed.
1273  // 4. Glue.
1274  // Note: The order is important.
1275 
1276  const auto &HRI = *Subtarget.getRegisterInfo();
1277  const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1278  assert(Mask && "Missing call preserved mask for calling convention");
1279  SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1280  DAG.getRegisterMask(Mask), Glue };
1281  Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1282 
1283  // Inform MFI that function has calls.
1284  MFI.setAdjustsStack(true);
1285 
1286  Glue = Chain.getValue(1);
1287  return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1288 }
1289 
1290 //
1291 // Lower using the intial executable model for TLS addresses
1292 //
1293 SDValue
1295  SelectionDAG &DAG) const {
1296  SDLoc dl(GA);
1297  int64_t Offset = GA->getOffset();
1298  auto PtrVT = getPointerTy(DAG.getDataLayout());
1299 
1300  // Get the thread pointer.
1301  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1302 
1303  bool IsPositionIndependent = isPositionIndependent();
1304  unsigned char TF =
1305  IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1306 
1307  // First generate the TLS symbol address
1308  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1309  Offset, TF);
1310 
1311  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1312 
1313  if (IsPositionIndependent) {
1314  // Generate the GOT pointer in case of position independent code
1315  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1316 
1317  // Add the TLS Symbol address to GOT pointer.This gives
1318  // GOT relative relocation for the symbol.
1319  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1320  }
1321 
1322  // Load the offset value for TLS symbol.This offset is relative to
1323  // thread pointer.
1324  SDValue LoadOffset =
1325  DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1326 
1327  // Address of the thread local variable is the add of thread
1328  // pointer and the offset of the variable.
1329  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1330 }
1331 
1332 //
1333 // Lower using the local executable model for TLS addresses
1334 //
1335 SDValue
1337  SelectionDAG &DAG) const {
1338  SDLoc dl(GA);
1339  int64_t Offset = GA->getOffset();
1340  auto PtrVT = getPointerTy(DAG.getDataLayout());
1341 
1342  // Get the thread pointer.
1343  SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1344  // Generate the TLS symbol address
1345  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1347  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1348 
1349  // Address of the thread local variable is the add of thread
1350  // pointer and the offset of the variable.
1351  return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1352 }
1353 
1354 //
1355 // Lower using the general dynamic model for TLS addresses
1356 //
1357 SDValue
1359  SelectionDAG &DAG) const {
1360  SDLoc dl(GA);
1361  int64_t Offset = GA->getOffset();
1362  auto PtrVT = getPointerTy(DAG.getDataLayout());
1363 
1364  // First generate the TLS symbol address
1365  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1367 
1368  // Then, generate the GOT pointer
1369  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1370 
1371  // Add the TLS symbol and the GOT pointer
1372  SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1373  SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1374 
1375  // Copy over the argument to R0
1376  SDValue InFlag;
1377  Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1378  InFlag = Chain.getValue(1);
1379 
1380  unsigned Flags =
1381  static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1384 
1385  return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1386  Hexagon::R0, Flags);
1387 }
1388 
1389 //
1390 // Lower TLS addresses.
1391 //
1392 // For now for dynamic models, we only support the general dynamic model.
1393 //
1394 SDValue
1396  SelectionDAG &DAG) const {
1397  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1398 
1399  switch (HTM.getTLSModel(GA->getGlobal())) {
1402  return LowerToTLSGeneralDynamicModel(GA, DAG);
1403  case TLSModel::InitialExec:
1404  return LowerToTLSInitialExecModel(GA, DAG);
1405  case TLSModel::LocalExec:
1406  return LowerToTLSLocalExecModel(GA, DAG);
1407  }
1408  llvm_unreachable("Bogus TLS model");
1409 }
1410 
1411 //===----------------------------------------------------------------------===//
1412 // TargetLowering Implementation
1413 //===----------------------------------------------------------------------===//
1414 
1416  const HexagonSubtarget &ST)
1417  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1418  Subtarget(ST) {
1419  auto &HRI = *Subtarget.getRegisterInfo();
1420 
1424  setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1427 
1430 
1433  else
1435 
1436  // Limits for inline expansion of memcpy/memmove
1443 
1444  //
1445  // Set up register classes.
1446  //
1447 
1448  addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1449  addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1450  addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1451  addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1452  addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1453  addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1454  addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1455  addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1456  addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1457  addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1458  addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1459 
1460  addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1461  addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1462 
1463  //
1464  // Handling of scalar operations.
1465  //
1466  // All operations default to "legal", except:
1467  // - indexed loads and stores (pre-/post-incremented),
1468  // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1469  // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1470  // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1471  // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1472  // which default to "expand" for at least one type.
1473 
1474  // Misc operations.
1491 
1492  // Custom legalize GlobalAddress nodes into CONST32.
1496 
1497  // Hexagon needs to optimize cases with negative constants.
1502 
1503  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1507  if (Subtarget.isEnvironmentMusl())
1509  else
1511 
1515 
1516  if (EmitJumpTables)
1518  else
1521 
1522  for (unsigned LegalIntOp :
1524  setOperationAction(LegalIntOp, MVT::i32, Legal);
1525  setOperationAction(LegalIntOp, MVT::i64, Legal);
1526  }
1527 
1528  // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1529  // but they only operate on i64.
1530  for (MVT VT : MVT::integer_valuetypes()) {
1537  }
1540 
1545 
1546  // Popcount can count # of 1s in i64 but returns i32.
1551 
1556 
1561 
1562  for (unsigned IntExpOp :
1567  for (MVT VT : MVT::integer_valuetypes())
1568  setOperationAction(IntExpOp, VT, Expand);
1569  }
1570 
1571  for (unsigned FPExpOp :
1574  for (MVT VT : MVT::fp_valuetypes())
1575  setOperationAction(FPExpOp, VT, Expand);
1576  }
1577 
1578  // No extending loads from i32.
1579  for (MVT VT : MVT::integer_valuetypes()) {
1583  }
1584  // Turn FP truncstore into trunc + store.
1586  // Turn FP extload into load/fpextend.
1587  for (MVT VT : MVT::fp_valuetypes())
1589 
1590  // Expand BR_CC and SELECT_CC for all integer and fp types.
1591  for (MVT VT : MVT::integer_valuetypes()) {
1594  }
1595  for (MVT VT : MVT::fp_valuetypes()) {
1598  }
1600 
1601  //
1602  // Handling of vector operations.
1603  //
1604 
1605  // Set the action for vector operations to "expand", then override it with
1606  // either "custom" or "legal" for specific cases.
1607  static const unsigned VectExpOps[] = {
1608  // Integer arithmetic:
1612  // Logical/bit:
1615  // Floating point arithmetic/math functions:
1622  // Misc:
1624  // Vector:
1630  };
1631 
1632  for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1633  for (unsigned VectExpOp : VectExpOps)
1634  setOperationAction(VectExpOp, VT, Expand);
1635 
1636  // Expand all extending loads and truncating stores:
1637  for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
1638  if (TargetVT == VT)
1639  continue;
1640  setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1641  setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1642  setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1643  setTruncStoreAction(VT, TargetVT, Expand);
1644  }
1645 
1646  // Normalize all inputs to SELECT to be vectors of i32.
1647  if (VT.getVectorElementType() != MVT::i32) {
1648  MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1650  AddPromotedToType(ISD::SELECT, VT, VT32);
1651  }
1655  }
1656 
1657  // Extending loads from (native) vectors of i8 into (native) vectors of i16
1658  // are legal.
1665 
1669 
1670  // Types natively supported:
1671  for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1679 
1680  setOperationAction(ISD::ADD, NativeVT, Legal);
1681  setOperationAction(ISD::SUB, NativeVT, Legal);
1682  setOperationAction(ISD::MUL, NativeVT, Legal);
1683  setOperationAction(ISD::AND, NativeVT, Legal);
1684  setOperationAction(ISD::OR, NativeVT, Legal);
1685  setOperationAction(ISD::XOR, NativeVT, Legal);
1686 
1687  if (NativeVT.getVectorElementType() != MVT::i1)
1689  }
1690 
1691  for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1696  }
1697 
1698  // Custom lower unaligned loads.
1699  // Also, for both loads and stores, verify the alignment of the address
1700  // in case it is a compile-time constant. This is a usability feature to
1701  // provide a meaningful error message to users.
1706  }
1707 
1709  MVT::v2i32}) {
1717  }
1718 
1719  // Custom-lower bitcasts from i8 to v8i1.
1727 
1728  // V5+.
1733 
1736 
1749 
1750  // Handling of indexed loads/stores: default is "expand".
1751  //
1756  }
1757 
1758  // Subtarget-specific operation actions.
1759  //
1760  if (Subtarget.hasV60Ops()) {
1765  }
1766  if (Subtarget.hasV66Ops()) {
1769  }
1770  if (Subtarget.hasV67Ops()) {
1774  }
1775 
1777 
1778  if (Subtarget.useHVXOps())
1779  initializeHVXLowering();
1780 
1782 
1783  //
1784  // Library calls for unsupported operations
1785  //
1786  bool FastMath = EnableFastMath;
1787 
1788  setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1789  setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1790  setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1791  setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1792  setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1793  setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1794  setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1795  setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1796 
1797  setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1798  setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1799  setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1800  setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1801  setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1802  setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1803 
1804  // This is the only fast library function for sqrtd.
1805  if (FastMath)
1806  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1807 
1808  // Prefix is: nothing for "slow-math",
1809  // "fast2_" for V5+ fast-math double-precision
1810  // (actually, keep fast-math and fast-math2 separate for now)
1811  if (FastMath) {
1812  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1813  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1814  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1815  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1816  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1817  } else {
1818  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1819  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1820  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1821  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1822  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1823  }
1824 
1825  if (FastMath)
1826  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1827  else
1828  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1829 
1830  // These cause problems when the shift amount is non-constant.
1831  setLibcallName(RTLIB::SHL_I128, nullptr);
1832  setLibcallName(RTLIB::SRL_I128, nullptr);
1833  setLibcallName(RTLIB::SRA_I128, nullptr);
1834 }
1835 
1836 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1837  switch ((HexagonISD::NodeType)Opcode) {
1838  case HexagonISD::ADDC: return "HexagonISD::ADDC";
1839  case HexagonISD::SUBC: return "HexagonISD::SUBC";
1840  case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1841  case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1842  case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1843  case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1844  case HexagonISD::CALL: return "HexagonISD::CALL";
1845  case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1846  case HexagonISD::CALLR: return "HexagonISD::CALLR";
1847  case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1848  case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1849  case HexagonISD::CONST32: return "HexagonISD::CONST32";
1850  case HexagonISD::CP: return "HexagonISD::CP";
1851  case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1852  case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1853  case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1854  case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1855  case HexagonISD::INSERT: return "HexagonISD::INSERT";
1856  case HexagonISD::JT: return "HexagonISD::JT";
1857  case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1858  case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1859  case HexagonISD::VASL: return "HexagonISD::VASL";
1860  case HexagonISD::VASR: return "HexagonISD::VASR";
1861  case HexagonISD::VLSR: return "HexagonISD::VLSR";
1862  case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1863  case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1864  case HexagonISD::VROR: return "HexagonISD::VROR";
1865  case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1866  case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1867  case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1868  case HexagonISD::D2P: return "HexagonISD::D2P";
1869  case HexagonISD::P2D: return "HexagonISD::P2D";
1870  case HexagonISD::V2Q: return "HexagonISD::V2Q";
1871  case HexagonISD::Q2V: return "HexagonISD::Q2V";
1872  case HexagonISD::QCAT: return "HexagonISD::QCAT";
1873  case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1874  case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1875  case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1876  case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1877  case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1878  case HexagonISD::VPACKL: return "HexagonISD::VPACKL";
1879  case HexagonISD::VUNPACK: return "HexagonISD::VUNPACK";
1880  case HexagonISD::VUNPACKU: return "HexagonISD::VUNPACKU";
1881  case HexagonISD::ISEL: return "HexagonISD::ISEL";
1882  case HexagonISD::OP_END: break;
1883  }
1884  return nullptr;
1885 }
1886 
1887 void
1888 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
1889  unsigned NeedAlign) const {
1890  auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1891  if (!CA)
1892  return;
1893  unsigned Addr = CA->getZExtValue();
1894  unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
1895  if (HaveAlign < NeedAlign) {
1896  std::string ErrMsg;
1897  raw_string_ostream O(ErrMsg);
1898  O << "Misaligned constant address: " << format_hex(Addr, 10)
1899  << " has alignment " << HaveAlign
1900  << ", but the memory access requires " << NeedAlign;
1901  if (DebugLoc DL = dl.getDebugLoc())
1902  DL.print(O << ", at ");
1903  report_fatal_error(O.str());
1904  }
1905 }
1906 
1907 // Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1908 // intrinsic.
1909 static bool isBrevLdIntrinsic(const Value *Inst) {
1910  unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1911  return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1912  ID == Intrinsic::hexagon_L2_loadri_pbr ||
1913  ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1914  ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1915  ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1916  ID == Intrinsic::hexagon_L2_loadrub_pbr);
1917 }
1918 
1919 // Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1920 // instruction. So far we only handle bitcast, extract value and bit reverse
1921 // load intrinsic instructions. Should we handle CGEP ?
1923  if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1924  Operator::getOpcode(V) == Instruction::BitCast)
1925  V = cast<Operator>(V)->getOperand(0);
1926  else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1927  V = cast<Instruction>(V)->getOperand(0);
1928  return V;
1929 }
1930 
1931 // Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1932 // a back edge. If the back edge comes from the intrinsic itself, the incoming
1933 // edge is returned.
1934 static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1935  const BasicBlock *Parent = PN->getParent();
1936  int Idx = -1;
1937  for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1938  BasicBlock *Blk = PN->getIncomingBlock(i);
1939  // Determine if the back edge is originated from intrinsic.
1940  if (Blk == Parent) {
1941  Value *BackEdgeVal = PN->getIncomingValue(i);
1942  Value *BaseVal;
1943  // Loop over till we return the same Value or we hit the IntrBaseVal.
1944  do {
1945  BaseVal = BackEdgeVal;
1946  BackEdgeVal = getBrevLdObject(BackEdgeVal);
1947  } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1948  // If the getBrevLdObject returns IntrBaseVal, we should return the
1949  // incoming edge.
1950  if (IntrBaseVal == BackEdgeVal)
1951  continue;
1952  Idx = i;
1953  break;
1954  } else // Set the node to incoming edge.
1955  Idx = i;
1956  }
1957  assert(Idx >= 0 && "Unexpected index to incoming argument in PHI");
1958  return PN->getIncomingValue(Idx);
1959 }
1960 
1961 // Bit-reverse Load Intrinsic: Figure out the underlying object the base
1962 // pointer points to, for the bit-reverse load intrinsic. Setting this to
1963 // memoperand might help alias analysis to figure out the dependencies.
1965  Value *IntrBaseVal = V;
1966  Value *BaseVal;
1967  // Loop over till we return the same Value, implies we either figure out
1968  // the object or we hit a PHI
1969  do {
1970  BaseVal = V;
1971  V = getBrevLdObject(V);
1972  } while (BaseVal != V);
1973 
1974  // Identify the object from PHINode.
1975  if (const PHINode *PN = dyn_cast<PHINode>(V))
1976  return returnEdge(PN, IntrBaseVal);
1977  // For non PHI nodes, the object is the last value returned by getBrevLdObject
1978  else
1979  return V;
1980 }
1981 
1982 /// Given an intrinsic, checks if on the target the intrinsic will need to map
1983 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1984 /// true and store the intrinsic information into the IntrinsicInfo that was
1985 /// passed to the function.
1987  const CallInst &I,
1988  MachineFunction &MF,
1989  unsigned Intrinsic) const {
1990  switch (Intrinsic) {
1991  case Intrinsic::hexagon_L2_loadrd_pbr:
1992  case Intrinsic::hexagon_L2_loadri_pbr:
1993  case Intrinsic::hexagon_L2_loadrh_pbr:
1994  case Intrinsic::hexagon_L2_loadruh_pbr:
1995  case Intrinsic::hexagon_L2_loadrb_pbr:
1996  case Intrinsic::hexagon_L2_loadrub_pbr: {
1998  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1999  auto &Cont = I.getCalledFunction()->getParent()->getContext();
2000  // The intrinsic function call is of the form { ElTy, i8* }
2001  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
2002  // should be derived from ElTy.
2003  Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
2004  Info.memVT = MVT::getVT(ElTy);
2005  llvm::Value *BasePtrVal = I.getOperand(0);
2006  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
2007  // The offset value comes through Modifier register. For now, assume the
2008  // offset is 0.
2009  Info.offset = 0;
2010  Info.align = DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont));
2012  return true;
2013  }
2014  case Intrinsic::hexagon_V6_vgathermw:
2015  case Intrinsic::hexagon_V6_vgathermw_128B:
2016  case Intrinsic::hexagon_V6_vgathermh:
2017  case Intrinsic::hexagon_V6_vgathermh_128B:
2018  case Intrinsic::hexagon_V6_vgathermhw:
2019  case Intrinsic::hexagon_V6_vgathermhw_128B:
2020  case Intrinsic::hexagon_V6_vgathermwq:
2021  case Intrinsic::hexagon_V6_vgathermwq_128B:
2022  case Intrinsic::hexagon_V6_vgathermhq:
2023  case Intrinsic::hexagon_V6_vgathermhq_128B:
2024  case Intrinsic::hexagon_V6_vgathermhwq:
2025  case Intrinsic::hexagon_V6_vgathermhwq_128B: {
2026  const Module &M = *I.getParent()->getParent()->getParent();
2028  Type *VecTy = I.getArgOperand(1)->getType();
2029  Info.memVT = MVT::getVT(VecTy);
2030  Info.ptrVal = I.getArgOperand(0);
2031  Info.offset = 0;
2032  Info.align =
2033  MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
2037  return true;
2038  }
2039  default:
2040  break;
2041  }
2042  return false;
2043 }
2044 
2046  return X.getValueType().isScalarInteger(); // 'tstbit'
2047 }
2048 
2050  return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
2051 }
2052 
2054  if (!VT1.isSimple() || !VT2.isSimple())
2055  return false;
2056  return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
2057 }
2058 
2060  const MachineFunction &MF, EVT VT) const {
2061  return isOperationLegalOrCustom(ISD::FMA, VT);
2062 }
2063 
2064 // Should we expand the build vector with shuffles?
2066  unsigned DefinedValues) const {
2067  return false;
2068 }
2069 
2071  EVT VT) const {
2072  return true;
2073 }
2074 
2077  unsigned VecLen = VT.getVectorNumElements();
2078  MVT ElemTy = VT.getVectorElementType();
2079 
2080  if (VecLen == 1 || VT.isScalableVector())
2082 
2083  if (Subtarget.useHVXOps()) {
2084  unsigned Action = getPreferredHvxVectorAction(VT);
2085  if (Action != ~0u)
2086  return static_cast<TargetLoweringBase::LegalizeTypeAction>(Action);
2087  }
2088 
2089  // Always widen (remaining) vectors of i1.
2090  if (ElemTy == MVT::i1)
2092 
2094 }
2095 
2096 std::pair<SDValue, int>
2097 HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
2098  if (Addr.getOpcode() == ISD::ADD) {
2099  SDValue Op1 = Addr.getOperand(1);
2100  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
2101  return { Addr.getOperand(0), CN->getSExtValue() };
2102  }
2103  return { Addr, 0 };
2104 }
2105 
2106 // Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2107 // to select data from, V3 is the permutation.
2108 SDValue
2110  const {
2111  const auto *SVN = cast<ShuffleVectorSDNode>(Op);
2112  ArrayRef<int> AM = SVN->getMask();
2113  assert(AM.size() <= 8 && "Unexpected shuffle mask");
2114  unsigned VecLen = AM.size();
2115 
2116  MVT VecTy = ty(Op);
2117  assert(!Subtarget.isHVXVectorType(VecTy, true) &&
2118  "HVX shuffles should be legal");
2119  assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length");
2120 
2121  SDValue Op0 = Op.getOperand(0);
2122  SDValue Op1 = Op.getOperand(1);
2123  const SDLoc &dl(Op);
2124 
2125  // If the inputs are not the same as the output, bail. This is not an
2126  // error situation, but complicates the handling and the default expansion
2127  // (into BUILD_VECTOR) should be adequate.
2128  if (ty(Op0) != VecTy || ty(Op1) != VecTy)
2129  return SDValue();
2130 
2131  // Normalize the mask so that the first non-negative index comes from
2132  // the first operand.
2133  SmallVector<int,8> Mask(AM.begin(), AM.end());
2134  unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
2135  if (F == AM.size())
2136  return DAG.getUNDEF(VecTy);
2137  if (AM[F] >= int(VecLen)) {
2139  std::swap(Op0, Op1);
2140  }
2141 
2142  // Express the shuffle mask in terms of bytes.
2143  SmallVector<int,8> ByteMask;
2144  unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
2145  for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
2146  int M = Mask[i];
2147  if (M < 0) {
2148  for (unsigned j = 0; j != ElemBytes; ++j)
2149  ByteMask.push_back(-1);
2150  } else {
2151  for (unsigned j = 0; j != ElemBytes; ++j)
2152  ByteMask.push_back(M*ElemBytes + j);
2153  }
2154  }
2155  assert(ByteMask.size() <= 8);
2156 
2157  // All non-undef (non-negative) indexes are well within [0..127], so they
2158  // fit in a single byte. Build two 64-bit words:
2159  // - MaskIdx where each byte is the corresponding index (for non-negative
2160  // indexes), and 0xFF for negative indexes, and
2161  // - MaskUnd that has 0xFF for each negative index.
2162  uint64_t MaskIdx = 0;
2163  uint64_t MaskUnd = 0;
2164  for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
2165  unsigned S = 8*i;
2166  uint64_t M = ByteMask[i] & 0xFF;
2167  if (M == 0xFF)
2168  MaskUnd |= M << S;
2169  MaskIdx |= M << S;
2170  }
2171 
2172  if (ByteMask.size() == 4) {
2173  // Identity.
2174  if (MaskIdx == (0x03020100 | MaskUnd))
2175  return Op0;
2176  // Byte swap.
2177  if (MaskIdx == (0x00010203 | MaskUnd)) {
2178  SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2179  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2180  return DAG.getBitcast(VecTy, T1);
2181  }
2182 
2183  // Byte packs.
2184  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
2185  typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
2186  if (MaskIdx == (0x06040200 | MaskUnd))
2187  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2188  if (MaskIdx == (0x07050301 | MaskUnd))
2189  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2190 
2191  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
2192  typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
2193  if (MaskIdx == (0x02000604 | MaskUnd))
2194  return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2195  if (MaskIdx == (0x03010705 | MaskUnd))
2196  return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2197  }
2198 
2199  if (ByteMask.size() == 8) {
2200  // Identity.
2201  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2202  return Op0;
2203  // Byte swap.
2204  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2205  SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2206  SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2207  return DAG.getBitcast(VecTy, T1);
2208  }
2209 
2210  // Halfword picks.
2211  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2212  return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2213  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2214  return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2215  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2216  return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2217  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2218  return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2219  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2220  VectorPair P = opSplit(Op0, dl, DAG);
2221  return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2222  }
2223 
2224  // Byte packs.
2225  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2226  return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2227  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2228  return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2229  }
2230 
2231  return SDValue();
2232 }
2233 
2234 // Create a Hexagon-specific node for shifting a vector by an integer.
2235 SDValue
2236 HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2237  const {
2238  unsigned NewOpc;
2239  switch (Op.getOpcode()) {
2240  case ISD::SHL:
2241  NewOpc = HexagonISD::VASL;
2242  break;
2243  case ISD::SRA:
2244  NewOpc = HexagonISD::VASR;
2245  break;
2246  case ISD::SRL:
2247  NewOpc = HexagonISD::VLSR;
2248  break;
2249  default:
2250  llvm_unreachable("Unexpected shift opcode");
2251  }
2252 
2253  SDValue Op0 = Op.getOperand(0);
2254  SDValue Op1 = Op.getOperand(1);
2255  const SDLoc &dl(Op);
2256 
2257  switch (Op1.getOpcode()) {
2258  case ISD::BUILD_VECTOR:
2259  if (SDValue S = cast<BuildVectorSDNode>(Op1)->getSplatValue())
2260  return DAG.getNode(NewOpc, dl, ty(Op), Op0, S);
2261  break;
2262  case ISD::SPLAT_VECTOR:
2263  return DAG.getNode(NewOpc, dl, ty(Op), Op0, Op1.getOperand(0));
2264  }
2265  return SDValue();
2266 }
2267 
2268 SDValue
2270  return getVectorShiftByInt(Op, DAG);
2271 }
2272 
2273 SDValue
2275  if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2276  return Op;
2277  return SDValue();
2278 }
2279 
2280 SDValue
2282  MVT ResTy = ty(Op);
2283  SDValue InpV = Op.getOperand(0);
2284  MVT InpTy = ty(InpV);
2285  assert(ResTy.getSizeInBits() == InpTy.getSizeInBits());
2286  const SDLoc &dl(Op);
2287 
2288  // Handle conversion from i8 to v8i1.
2289  if (InpTy == MVT::i8) {
2290  if (ResTy == MVT::v8i1) {
2291  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2292  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2293  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2294  }
2295  return SDValue();
2296  }
2297 
2298  return Op;
2299 }
2300 
2301 bool
2302 HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2303  MVT VecTy, SelectionDAG &DAG,
2304  MutableArrayRef<ConstantInt*> Consts) const {
2305  MVT ElemTy = VecTy.getVectorElementType();
2306  unsigned ElemWidth = ElemTy.getSizeInBits();
2307  IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2308  bool AllConst = true;
2309 
2310  for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2311  SDValue V = Values[i];
2312  if (V.isUndef()) {
2313  Consts[i] = ConstantInt::get(IntTy, 0);
2314  continue;
2315  }
2316  // Make sure to always cast to IntTy.
2317  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2318  const ConstantInt *CI = CN->getConstantIntValue();
2319  Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2320  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2321  const ConstantFP *CF = CN->getConstantFPValue();
2322  APInt A = CF->getValueAPF().bitcastToAPInt();
2323  Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2324  } else {
2325  AllConst = false;
2326  }
2327  }
2328  return AllConst;
2329 }
2330 
2331 SDValue
2332 HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2333  MVT VecTy, SelectionDAG &DAG) const {
2334  MVT ElemTy = VecTy.getVectorElementType();
2335  assert(VecTy.getVectorNumElements() == Elem.size());
2336 
2337  SmallVector<ConstantInt*,4> Consts(Elem.size());
2338  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2339 
2340  unsigned First, Num = Elem.size();
2341  for (First = 0; First != Num; ++First) {
2342  if (!isUndef(Elem[First]))
2343  break;
2344  }
2345  if (First == Num)
2346  return DAG.getUNDEF(VecTy);
2347 
2348  if (AllConst &&
2349  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2350  return getZero(dl, VecTy, DAG);
2351 
2352  if (ElemTy == MVT::i16) {
2353  assert(Elem.size() == 2);
2354  if (AllConst) {
2355  uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2356  Consts[1]->getZExtValue() << 16;
2357  return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2358  }
2359  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2360  {Elem[1], Elem[0]}, DAG);
2361  return DAG.getBitcast(MVT::v2i16, N);
2362  }
2363 
2364  if (ElemTy == MVT::i8) {
2365  // First try generating a constant.
2366  if (AllConst) {
2367  int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2368  (Consts[1]->getZExtValue() & 0xFF) << 8 |
2369  (Consts[1]->getZExtValue() & 0xFF) << 16 |
2370  Consts[2]->getZExtValue() << 24;
2371  return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2372  }
2373 
2374  // Then try splat.
2375  bool IsSplat = true;
2376  for (unsigned i = First+1; i != Num; ++i) {
2377  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2378  continue;
2379  IsSplat = false;
2380  break;
2381  }
2382  if (IsSplat) {
2383  // Legalize the operand of SPLAT_VECTOR.
2384  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2385  return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2386  }
2387 
2388  // Generate
2389  // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2390  // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2391  assert(Elem.size() == 4);
2392  SDValue Vs[4];
2393  for (unsigned i = 0; i != 4; ++i) {
2394  Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2395  Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2396  }
2397  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2398  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2399  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2400  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2401  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2402 
2403  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2404  return DAG.getBitcast(MVT::v4i8, R);
2405  }
2406 
2407 #ifndef NDEBUG
2408  dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2409 #endif
2410  llvm_unreachable("Unexpected vector element type");
2411 }
2412 
2413 SDValue
2414 HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2415  MVT VecTy, SelectionDAG &DAG) const {
2416  MVT ElemTy = VecTy.getVectorElementType();
2417  assert(VecTy.getVectorNumElements() == Elem.size());
2418 
2419  SmallVector<ConstantInt*,8> Consts(Elem.size());
2420  bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2421 
2422  unsigned First, Num = Elem.size();
2423  for (First = 0; First != Num; ++First) {
2424  if (!isUndef(Elem[First]))
2425  break;
2426  }
2427  if (First == Num)
2428  return DAG.getUNDEF(VecTy);
2429 
2430  if (AllConst &&
2431  llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2432  return getZero(dl, VecTy, DAG);
2433 
2434  // First try splat if possible.
2435  if (ElemTy == MVT::i16) {
2436  bool IsSplat = true;
2437  for (unsigned i = First+1; i != Num; ++i) {
2438  if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2439  continue;
2440  IsSplat = false;
2441  break;
2442  }
2443  if (IsSplat) {
2444  // Legalize the operand of SPLAT_VECTOR
2445  SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2446  return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext);
2447  }
2448  }
2449 
2450  // Then try constant.
2451  if (AllConst) {
2452  uint64_t Val = 0;
2453  unsigned W = ElemTy.getSizeInBits();
2454  uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2455  : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2456  for (unsigned i = 0; i != Num; ++i)
2457  Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2458  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2459  return DAG.getBitcast(VecTy, V0);
2460  }
2461 
2462  // Build two 32-bit vectors and concatenate.
2463  MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2464  SDValue L = (ElemTy == MVT::i32)
2465  ? Elem[0]
2466  : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2467  SDValue H = (ElemTy == MVT::i32)
2468  ? Elem[1]
2469  : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2470  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2471 }
2472 
2473 SDValue
2474 HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2475  const SDLoc &dl, MVT ValTy, MVT ResTy,
2476  SelectionDAG &DAG) const {
2477  MVT VecTy = ty(VecV);
2478  assert(!ValTy.isVector() ||
2479  VecTy.getVectorElementType() == ValTy.getVectorElementType());
2480  unsigned VecWidth = VecTy.getSizeInBits();
2481  unsigned ValWidth = ValTy.getSizeInBits();
2482  unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2483  assert((VecWidth % ElemWidth) == 0);
2484  auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2485 
2486  // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2487  // without any coprocessors).
2488  if (ElemWidth == 1) {
2489  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure");
2490  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2491  // Check if this is an extract of the lowest bit.
2492  if (IdxN) {
2493  // Extracting the lowest bit is a no-op, but it changes the type,
2494  // so it must be kept as an operation to avoid errors related to
2495  // type mismatches.
2496  if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2497  return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2498  }
2499 
2500  // If the value extracted is a single bit, use tstbit.
2501  if (ValWidth == 1) {
2502  SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2503  SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2504  SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2505  return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2506  }
2507 
2508  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2509  // a predicate register. The elements of the vector are repeated
2510  // in the register (if necessary) so that the total number is 8.
2511  // The extracted subvector will need to be expanded in such a way.
2512  unsigned Scale = VecWidth / ValWidth;
2513 
2514  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2515  // position 0.
2516  assert(ty(IdxV) == MVT::i32);
2517  unsigned VecRep = 8 / VecWidth;
2518  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2519  DAG.getConstant(8*VecRep, dl, MVT::i32));
2520  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2521  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2522  while (Scale > 1) {
2523  // The longest possible subvector is at most 32 bits, so it is always
2524  // contained in the low subregister.
2525  T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2526  T1 = expandPredicate(T1, dl, DAG);
2527  Scale /= 2;
2528  }
2529 
2530  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2531  }
2532 
2533  assert(VecWidth == 32 || VecWidth == 64);
2534 
2535  // Cast everything to scalar integer types.
2536  MVT ScalarTy = tyScalar(VecTy);
2537  VecV = DAG.getBitcast(ScalarTy, VecV);
2538 
2539  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2540  SDValue ExtV;
2541 
2542  if (IdxN) {
2543  unsigned Off = IdxN->getZExtValue() * ElemWidth;
2544  if (VecWidth == 64 && ValWidth == 32) {
2545  assert(Off == 0 || Off == 32);
2546  unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2547  ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2548  } else if (Off == 0 && (ValWidth % 8) == 0) {
2549  ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2550  } else {
2551  SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2552  // The return type of EXTRACTU must be the same as the type of the
2553  // input vector.
2554  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2555  {VecV, WidthV, OffV});
2556  }
2557  } else {
2558  if (ty(IdxV) != MVT::i32)
2559  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2560  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2561  DAG.getConstant(ElemWidth, dl, MVT::i32));
2562  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2563  {VecV, WidthV, OffV});
2564  }
2565 
2566  // Cast ExtV to the requested result type.
2567  ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2568  ExtV = DAG.getBitcast(ResTy, ExtV);
2569  return ExtV;
2570 }
2571 
2572 SDValue
2573 HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2574  const SDLoc &dl, MVT ValTy,
2575  SelectionDAG &DAG) const {
2576  MVT VecTy = ty(VecV);
2577  if (VecTy.getVectorElementType() == MVT::i1) {
2578  MVT ValTy = ty(ValV);
2579  assert(ValTy.getVectorElementType() == MVT::i1);
2580  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2581  unsigned VecLen = VecTy.getVectorNumElements();
2582  unsigned Scale = VecLen / ValTy.getVectorNumElements();
2583  assert(Scale > 1);
2584 
2585  for (unsigned R = Scale; R > 1; R /= 2) {
2586  ValR = contractPredicate(ValR, dl, DAG);
2587  ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2588  DAG.getUNDEF(MVT::i32), ValR);
2589  }
2590  // The longest possible subvector is at most 32 bits, so it is always
2591  // contained in the low subregister.
2592  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2593 
2594  unsigned ValBytes = 64 / Scale;
2595  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2596  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2597  DAG.getConstant(8, dl, MVT::i32));
2598  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2600  {VecR, ValR, Width, Idx});
2601  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2602  }
2603 
2604  unsigned VecWidth = VecTy.getSizeInBits();
2605  unsigned ValWidth = ValTy.getSizeInBits();
2606  assert(VecWidth == 32 || VecWidth == 64);
2607  assert((VecWidth % ValWidth) == 0);
2608 
2609  // Cast everything to scalar integer types.
2610  MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2611  // The actual type of ValV may be different than ValTy (which is related
2612  // to the vector type).
2613  unsigned VW = ty(ValV).getSizeInBits();
2614  ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2615  VecV = DAG.getBitcast(ScalarTy, VecV);
2616  if (VW != VecWidth)
2617  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2618 
2619  SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2620  SDValue InsV;
2621 
2622  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2623  unsigned W = C->getZExtValue() * ValWidth;
2624  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2625  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2626  {VecV, ValV, WidthV, OffV});
2627  } else {
2628  if (ty(IdxV) != MVT::i32)
2629  IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2630  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2631  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2632  {VecV, ValV, WidthV, OffV});
2633  }
2634 
2635  return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2636 }
2637 
2638 SDValue
2639 HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2640  SelectionDAG &DAG) const {
2641  assert(ty(Vec32).getSizeInBits() == 32);
2642  if (isUndef(Vec32))
2643  return DAG.getUNDEF(MVT::i64);
2644  return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2645 }
2646 
2647 SDValue
2648 HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2649  SelectionDAG &DAG) const {
2650  assert(ty(Vec64).getSizeInBits() == 64);
2651  if (isUndef(Vec64))
2652  return DAG.getUNDEF(MVT::i32);
2653  return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2654 }
2655 
2656 SDValue
2657 HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2658  const {
2659  if (Ty.isVector()) {
2660  assert(Ty.isInteger() && "Only integer vectors are supported here");
2661  unsigned W = Ty.getSizeInBits();
2662  if (W <= 64)
2663  return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2664  return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG));
2665  }
2666 
2667  if (Ty.isInteger())
2668  return DAG.getConstant(0, dl, Ty);
2669  if (Ty.isFloatingPoint())
2670  return DAG.getConstantFP(0.0, dl, Ty);
2671  llvm_unreachable("Invalid type for zero");
2672 }
2673 
2674 SDValue
2675 HexagonTargetLowering::appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG)
2676  const {
2677  MVT ValTy = ty(Val);
2678  assert(ValTy.getVectorElementType() == ResTy.getVectorElementType());
2679 
2680  unsigned ValLen = ValTy.getVectorNumElements();
2681  unsigned ResLen = ResTy.getVectorNumElements();
2682  if (ValLen == ResLen)
2683  return Val;
2684 
2685  const SDLoc &dl(Val);
2686  assert(ValLen < ResLen);
2687  assert(ResLen % ValLen == 0);
2688 
2689  SmallVector<SDValue, 4> Concats = {Val};
2690  for (unsigned i = 1, e = ResLen / ValLen; i < e; ++i)
2691  Concats.push_back(DAG.getUNDEF(ValTy));
2692 
2693  return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, Concats);
2694 }
2695 
2696 SDValue
2698  MVT VecTy = ty(Op);
2699  unsigned BW = VecTy.getSizeInBits();
2700  const SDLoc &dl(Op);
2702  for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2703  Ops.push_back(Op.getOperand(i));
2704 
2705  if (BW == 32)
2706  return buildVector32(Ops, dl, VecTy, DAG);
2707  if (BW == 64)
2708  return buildVector64(Ops, dl, VecTy, DAG);
2709 
2710  if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2711  // Check if this is a special case or all-0 or all-1.
2712  bool All0 = true, All1 = true;
2713  for (SDValue P : Ops) {
2714  auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
2715  if (CN == nullptr) {
2716  All0 = All1 = false;
2717  break;
2718  }
2719  uint32_t C = CN->getZExtValue();
2720  All0 &= (C == 0);
2721  All1 &= (C == 1);
2722  }
2723  if (All0)
2724  return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
2725  if (All1)
2726  return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);
2727 
2728  // For each i1 element in the resulting predicate register, put 1
2729  // shifted by the index of the element into a general-purpose register,
2730  // then or them together and transfer it back into a predicate register.
2731  SDValue Rs[8];
2732  SDValue Z = getZero(dl, MVT::i32, DAG);
2733  // Always produce 8 bits, repeat inputs if necessary.
2734  unsigned Rep = 8 / VecTy.getVectorNumElements();
2735  for (unsigned i = 0; i != 8; ++i) {
2736  SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2737  Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2738  }
2739  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2740  for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2741  Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2742  }
2743  // Move the value directly to a predicate register.
2744  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2745  }
2746 
2747  return SDValue();
2748 }
2749 
2750 SDValue
2752  SelectionDAG &DAG) const {
2753  MVT VecTy = ty(Op);
2754  const SDLoc &dl(Op);
2755  if (VecTy.getSizeInBits() == 64) {
2756  assert(Op.getNumOperands() == 2);
2757  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2758  Op.getOperand(0));
2759  }
2760 
2761  MVT ElemTy = VecTy.getVectorElementType();
2762  if (ElemTy == MVT::i1) {
2763  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2764  MVT OpTy = ty(Op.getOperand(0));
2765  // Scale is how many times the operands need to be contracted to match
2766  // the representation in the target register.
2767  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2768  assert(Scale == Op.getNumOperands() && Scale > 1);
2769 
2770  // First, convert all bool vectors to integers, then generate pairwise
2771  // inserts to form values of doubled length. Up until there are only
2772  // two values left to concatenate, all of these values will fit in a
2773  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2774  SmallVector<SDValue,4> Words[2];
2775  unsigned IdxW = 0;
2776 
2777  for (SDValue P : Op.getNode()->op_values()) {
2778  SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2779  for (unsigned R = Scale; R > 1; R /= 2) {
2780  W = contractPredicate(W, dl, DAG);
2782  DAG.getUNDEF(MVT::i32), W);
2783  }
2784  W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2785  Words[IdxW].push_back(W);
2786  }
2787 
2788  while (Scale > 2) {
2789  SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2790  Words[IdxW ^ 1].clear();
2791 
2792  for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2793  SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2794  // Insert W1 into W0 right next to the significant bits of W0.
2796  {W0, W1, WidthV, WidthV});
2797  Words[IdxW ^ 1].push_back(T);
2798  }
2799  IdxW ^= 1;
2800  Scale /= 2;
2801  }
2802 
2803  // Another sanity check. At this point there should only be two words
2804  // left, and Scale should be 2.
2805  assert(Scale == 2 && Words[IdxW].size() == 2);
2806 
2808  Words[IdxW][1], Words[IdxW][0]);
2809  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2810  }
2811 
2812  return SDValue();
2813 }
2814 
2815 SDValue
2817  SelectionDAG &DAG) const {
2818  SDValue Vec = Op.getOperand(0);
2819  MVT ElemTy = ty(Vec).getVectorElementType();
2820  return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2821 }
2822 
2823 SDValue
2825  SelectionDAG &DAG) const {
2826  return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2827  ty(Op), ty(Op), DAG);
2828 }
2829 
2830 SDValue
2832  SelectionDAG &DAG) const {
2833  return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2834  SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2835 }
2836 
2837 SDValue
2839  SelectionDAG &DAG) const {
2840  SDValue ValV = Op.getOperand(1);
2841  return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2842  SDLoc(Op), ty(ValV), DAG);
2843 }
2844 
2845 bool
2847  // Assuming the caller does not have either a signext or zeroext modifier, and
2848  // only one value is accepted, any reasonable truncation is allowed.
2849  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2850  return false;
2851 
2852  // FIXME: in principle up to 64-bit could be made safe, but it would be very
2853  // fragile at the moment: any support for multiple value returns would be
2854  // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2855  return Ty1->getPrimitiveSizeInBits() <= 32;
2856 }
2857 
2858 SDValue
2860  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2861  unsigned ClaimAlign = LN->getAlignment();
2862  validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
2863  // Call LowerUnalignedLoad for all loads, it recognizes loads that
2864  // don't need extra aligning.
2865  return LowerUnalignedLoad(Op, DAG);
2866 }
2867 
2868 SDValue
2870  StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2871  unsigned ClaimAlign = SN->getAlignment();
2872  SDValue Ptr = SN->getBasePtr();
2873  const SDLoc &dl(Op);
2874  validateConstPtrAlignment(Ptr, dl, ClaimAlign);
2875 
2876  MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2877  unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2878  if (ClaimAlign < NeedAlign)
2879  return expandUnalignedStore(SN, DAG);
2880  return Op;
2881 }
2882 
2883 SDValue
2885  const {
2886  LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2887  MVT LoadTy = ty(Op);
2888  unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2889  unsigned HaveAlign = LN->getAlignment();
2890  if (HaveAlign >= NeedAlign)
2891  return Op;
2892 
2893  const SDLoc &dl(Op);
2894  const DataLayout &DL = DAG.getDataLayout();
2895  LLVMContext &Ctx = *DAG.getContext();
2896 
2897  // If the load aligning is disabled or the load can be broken up into two
2898  // smaller legal loads, do the default (target-independent) expansion.
2899  bool DoDefault = false;
2900  // Handle it in the default way if this is an indexed load.
2901  if (!LN->isUnindexed())
2902  DoDefault = true;
2903 
2904  if (!AlignLoads) {
2906  *LN->getMemOperand()))
2907  return Op;
2908  DoDefault = true;
2909  }
2910  if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
2911  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2912  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
2913  : MVT::getVectorVT(MVT::i8, HaveAlign);
2914  DoDefault =
2915  allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
2916  }
2917  if (DoDefault) {
2918  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2919  return DAG.getMergeValues({P.first, P.second}, dl);
2920  }
2921 
2922  // The code below generates two loads, both aligned as NeedAlign, and
2923  // with the distance of NeedAlign between them. For that to cover the
2924  // bits that need to be loaded (and without overlapping), the size of
2925  // the loads should be equal to NeedAlign. This is true for all loadable
2926  // types, but add an assertion in case something changes in the future.
2927  assert(LoadTy.getSizeInBits() == 8*NeedAlign);
2928 
2929  unsigned LoadLen = NeedAlign;
2930  SDValue Base = LN->getBasePtr();
2931  SDValue Chain = LN->getChain();
2932  auto BO = getBaseAndOffset(Base);
2933  unsigned BaseOpc = BO.first.getOpcode();
2934  if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2935  return Op;
2936 
2937  if (BO.second % LoadLen != 0) {
2938  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2939  DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2940  BO.second -= BO.second % LoadLen;
2941  }
2942  SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2943  ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2944  DAG.getConstant(NeedAlign, dl, MVT::i32))
2945  : BO.first;
2946  SDValue Base0 =
2947  DAG.getMemBasePlusOffset(BaseNoOff, TypeSize::Fixed(BO.second), dl);
2948  SDValue Base1 = DAG.getMemBasePlusOffset(
2949  BaseNoOff, TypeSize::Fixed(BO.second + LoadLen), dl);
2950 
2951  MachineMemOperand *WideMMO = nullptr;
2952  if (MachineMemOperand *MMO = LN->getMemOperand()) {
2953  MachineFunction &MF = DAG.getMachineFunction();
2954  WideMMO = MF.getMachineMemOperand(
2955  MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen, Align(LoadLen),
2956  MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
2957  MMO->getOrdering(), MMO->getFailureOrdering());
2958  }
2959 
2960  SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2961  SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2962 
2963  SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2964  {Load1, Load0, BaseNoOff.getOperand(0)});
2965  SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2966  Load0.getValue(1), Load1.getValue(1));
2967  SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2968  return M;
2969 }
2970 
2971 SDValue
2973  SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
2974  auto *CY = dyn_cast<ConstantSDNode>(Y);
2975  if (!CY)
2976  return SDValue();
2977 
2978  const SDLoc &dl(Op);
2979  SDVTList VTs = Op.getNode()->getVTList();
2980  assert(VTs.NumVTs == 2);
2981  assert(VTs.VTs[1] == MVT::i1);
2982  unsigned Opc = Op.getOpcode();
2983 
2984  if (CY) {
2985  uint32_t VY = CY->getZExtValue();
2986  assert(VY != 0 && "This should have been folded");
2987  // X +/- 1
2988  if (VY != 1)
2989  return SDValue();
2990 
2991  if (Opc == ISD::UADDO) {
2992  SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
2993  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
2994  ISD::SETEQ);
2995  return DAG.getMergeValues({Op, Ov}, dl);
2996  }
2997  if (Opc == ISD::USUBO) {
2998  SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
2999  SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
3000  DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
3001  return DAG.getMergeValues({Op, Ov}, dl);
3002  }
3003  }
3004 
3005  return SDValue();
3006 }
3007 
3008 SDValue
3010  const SDLoc &dl(Op);
3011  unsigned Opc = Op.getOpcode();
3012  SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
3013 
3014  if (Opc == ISD::ADDCARRY)
3015  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
3016  { X, Y, C });
3017 
3018  EVT CarryTy = C.getValueType();
3019  SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
3020  { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
3021  SDValue Out[] = { SubC.getValue(0),
3022  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
3023  return DAG.getMergeValues(Out, dl);
3024 }
3025 
3026 SDValue
3028  SDValue Chain = Op.getOperand(0);
3029  SDValue Offset = Op.getOperand(1);
3030  SDValue Handler = Op.getOperand(2);
3031  SDLoc dl(Op);
3032  auto PtrVT = getPointerTy(DAG.getDataLayout());
3033 
3034  // Mark function as containing a call to EH_RETURN.
3035  HexagonMachineFunctionInfo *FuncInfo =
3037  FuncInfo->setHasEHReturn();
3038 
3039  unsigned OffsetReg = Hexagon::R28;
3040 
3041  SDValue StoreAddr =
3042  DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
3043  DAG.getIntPtrConstant(4, dl));
3044  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
3045  Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
3046 
3047  // Not needed we already use it as explict input to EH_RETURN.
3048  // MF.getRegInfo().addLiveOut(OffsetReg);
3049 
3050  return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
3051 }
3052 
3053 SDValue
3055  unsigned Opc = Op.getOpcode();
3056 
3057  // Handle INLINEASM first.
3058  if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
3059  return LowerINLINEASM(Op, DAG);
3060 
3061  if (isHvxOperation(Op.getNode(), DAG)) {
3062  // If HVX lowering returns nothing, try the default lowering.
3063  if (SDValue V = LowerHvxOperation(Op, DAG))
3064  return V;
3065  }
3066 
3067  switch (Opc) {
3068  default:
3069 #ifndef NDEBUG
3070  Op.getNode()->dumpr(&DAG);
3071  if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
3072  errs() << "Error: check for a non-legal type in this operation\n";
3073 #endif
3074  llvm_unreachable("Should not custom lower this!");
3075  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3076  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
3080  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3081  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3082  case ISD::BITCAST: return LowerBITCAST(Op, DAG);
3083  case ISD::LOAD: return LowerLoad(Op, DAG);
3084  case ISD::STORE: return LowerStore(Op, DAG);
3085  case ISD::UADDO:
3086  case ISD::USUBO: return LowerUAddSubO(Op, DAG);
3087  case ISD::ADDCARRY:
3088  case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
3089  case ISD::SRA:
3090  case ISD::SHL:
3091  case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
3092  case ISD::ROTL: return LowerROTL(Op, DAG);
3093  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3094  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3095  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
3096  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3097  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3098  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3099  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
3100  case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
3101  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3103  case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3104  case ISD::VASTART: return LowerVASTART(Op, DAG);
3106  case ISD::SETCC: return LowerSETCC(Op, DAG);
3107  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3109  case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3110  case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3111  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
3112  break;
3113  }
3114 
3115  return SDValue();
3116 }
3117 
3118 void
3121  SelectionDAG &DAG) const {
3122  if (isHvxOperation(N, DAG)) {
3123  LowerHvxOperationWrapper(N, Results, DAG);
3124  if (!Results.empty())
3125  return;
3126  }
3127 
3128  // We are only custom-lowering stores to verify the alignment of the
3129  // address if it is a compile-time constant. Since a store can be modified
3130  // during type-legalization (the value being stored may need legalization),
3131  // return empty Results here to indicate that we don't really make any
3132  // changes in the custom lowering.
3133  if (N->getOpcode() != ISD::STORE)
3135 }
3136 
3137 void
3140  SelectionDAG &DAG) const {
3141  if (isHvxOperation(N, DAG)) {
3142  ReplaceHvxNodeResults(N, Results, DAG);
3143  if (!Results.empty())
3144  return;
3145  }
3146 
3147  const SDLoc &dl(N);
3148  switch (N->getOpcode()) {
3149  case ISD::SRL:
3150  case ISD::SRA:
3151  case ISD::SHL:
3152  return;
3153  case ISD::BITCAST:
3154  // Handle a bitcast from v8i1 to i8.
3155  if (N->getValueType(0) == MVT::i8) {
3156  if (N->getOperand(0).getValueType() == MVT::v8i1) {
3157  SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3158  N->getOperand(0), DAG);
3159  SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
3160  Results.push_back(T);
3161  }
3162  }
3163  break;
3164  }
3165 }
3166 
3167 SDValue
3169  const {
3170  if (isHvxOperation(N, DCI.DAG)) {
3171  if (SDValue V = PerformHvxDAGCombine(N, DCI))
3172  return V;
3173  return SDValue();
3174  }
3175 
3176  if (DCI.isBeforeLegalizeOps())
3177  return SDValue();
3178 
3179  SDValue Op(N, 0);
3180  const SDLoc &dl(Op);
3181  unsigned Opc = Op.getOpcode();
3182 
3183  if (Opc == HexagonISD::P2D) {
3184  SDValue P = Op.getOperand(0);
3185  switch (P.getOpcode()) {
3186  case HexagonISD::PTRUE:
3187  return DCI.DAG.getConstant(-1, dl, ty(Op));
3188  case HexagonISD::PFALSE:
3189  return getZero(dl, ty(Op), DCI.DAG);
3190  default:
3191  break;
3192  }
3193  } else if (Opc == ISD::VSELECT) {
3194  // This is pretty much duplicated in HexagonISelLoweringHVX...
3195  //
3196  // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3197  SDValue Cond = Op.getOperand(0);
3198  if (Cond->getOpcode() == ISD::XOR) {
3199  SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
3200  if (C1->getOpcode() == HexagonISD::PTRUE) {
3201  SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
3202  Op.getOperand(2), Op.getOperand(1));
3203  return VSel;
3204  }
3205  }
3206  }
3207 
3208  return SDValue();
3209 }
3210 
3211 /// Returns relocation base for the given PIC jumptable.
3212 SDValue
3214  SelectionDAG &DAG) const {
3215  int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3216  EVT VT = Table.getValueType();
3218  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3219 }
3220 
3221 //===----------------------------------------------------------------------===//
3222 // Inline Assembly Support
3223 //===----------------------------------------------------------------------===//
3224 
3227  if (Constraint.size() == 1) {
3228  switch (Constraint[0]) {
3229  case 'q':
3230  case 'v':
3231  if (Subtarget.useHVXOps())
3232  return C_RegisterClass;
3233  break;
3234  case 'a':
3235  return C_RegisterClass;
3236  default:
3237  break;
3238  }
3239  }
3240  return TargetLowering::getConstraintType(Constraint);
3241 }
3242 
3243 std::pair<unsigned, const TargetRegisterClass*>
3245  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3246 
3247  if (Constraint.size() == 1) {
3248  switch (Constraint[0]) {
3249  case 'r': // R0-R31
3250  switch (VT.SimpleTy) {
3251  default:
3252  return {0u, nullptr};
3253  case MVT::i1:
3254  case MVT::i8:
3255  case MVT::i16:
3256  case MVT::i32:
3257  case MVT::f32:
3258  return {0u, &Hexagon::IntRegsRegClass};
3259  case MVT::i64:
3260  case MVT::f64:
3261  return {0u, &Hexagon::DoubleRegsRegClass};
3262  }
3263  break;
3264  case 'a': // M0-M1
3265  if (VT != MVT::i32)
3266  return {0u, nullptr};
3267  return {0u, &Hexagon::ModRegsRegClass};
3268  case 'q': // q0-q3
3269  switch (VT.getSizeInBits()) {
3270  default:
3271  return {0u, nullptr};
3272  case 64:
3273  case 128:
3274  return {0u, &Hexagon::HvxQRRegClass};
3275  }
3276  break;
3277  case 'v': // V0-V31
3278  switch (VT.getSizeInBits()) {
3279  default:
3280  return {0u, nullptr};
3281  case 512:
3282  return {0u, &Hexagon::HvxVRRegClass};
3283  case 1024:
3284  if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3285  return {0u, &Hexagon::HvxVRRegClass};
3286  return {0u, &Hexagon::HvxWRRegClass};
3287  case 2048:
3288  return {0u, &Hexagon::HvxWRRegClass};
3289  }
3290  break;
3291  default:
3292  return {0u, nullptr};
3293  }
3294  }
3295 
3296  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3297 }
3298 
3299 /// isFPImmLegal - Returns true if the target can instruction select the
3300 /// specified FP immediate natively. If false, the legalizer will
3301 /// materialize the FP immediate as a load from a constant pool.
3303  bool ForCodeSize) const {
3304  return true;
3305 }
3306 
3307 /// isLegalAddressingMode - Return true if the addressing mode represented by
3308 /// AM is legal for this target, for a load/store of the specified type.
3310  const AddrMode &AM, Type *Ty,
3311  unsigned AS, Instruction *I) const {
3312  if (Ty->isSized()) {
3313  // When LSR detects uses of the same base address to access different
3314  // types (e.g. unions), it will assume a conservative type for these
3315  // uses:
3316  // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3317  // The type Ty passed here would then be "void". Skip the alignment
3318  // checks, but do not return false right away, since that confuses
3319  // LSR into crashing.
3320  Align A = DL.getABITypeAlign(Ty);
3321  // The base offset must be a multiple of the alignment.
3322  if (!isAligned(A, AM.BaseOffs))
3323  return false;
3324  // The shifted offset must fit in 11 bits.
3325  if (!isInt<11>(AM.BaseOffs >> Log2(A)))
3326  return false;
3327  }
3328 
3329  // No global is ever allowed as a base.
3330  if (AM.BaseGV)
3331  return false;
3332 
3333  int Scale = AM.Scale;
3334  if (Scale < 0)
3335  Scale = -Scale;
3336  switch (Scale) {
3337  case 0: // No scale reg, "r+i", "r", or just "i".
3338  break;
3339  default: // No scaled addressing mode.
3340  return false;
3341  }
3342  return true;
3343 }
3344 
3345 /// Return true if folding a constant offset with the given GlobalAddress is
3346 /// legal. It is frequently not legal in PIC relocation models.
3348  const {
3349  return HTM.getRelocationModel() == Reloc::Static;
3350 }
3351 
3352 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3353 /// icmp immediate, that is the target has icmp instructions which can compare
3354 /// a register against the immediate without having to materialize the
3355 /// immediate into a register.
3357  return Imm >= -512 && Imm <= 511;
3358 }
3359 
3360 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3361 /// for tail call optimization. Targets which want to do tail call
3362 /// optimization should implement this function.
3364  SDValue Callee,
3365  CallingConv::ID CalleeCC,
3366  bool IsVarArg,
3367  bool IsCalleeStructRet,
3368  bool IsCallerStructRet,
3369  const SmallVectorImpl<ISD::OutputArg> &Outs,
3370  const SmallVectorImpl<SDValue> &OutVals,
3372  SelectionDAG& DAG) const {
3373  const Function &CallerF = DAG.getMachineFunction().getFunction();
3374  CallingConv::ID CallerCC = CallerF.getCallingConv();
3375  bool CCMatch = CallerCC == CalleeCC;
3376 
3377  // ***************************************************************************
3378  // Look for obvious safe cases to perform tail call optimization that do not
3379  // require ABI changes.
3380  // ***************************************************************************
3381 
3382  // If this is a tail call via a function pointer, then don't do it!
3383  if (!isa<GlobalAddressSDNode>(Callee) &&
3384  !isa<ExternalSymbolSDNode>(Callee)) {
3385  return false;
3386  }
3387 
3388  // Do not optimize if the calling conventions do not match and the conventions
3389  // used are not C or Fast.
3390  if (!CCMatch) {
3391  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3392  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3393  // If R & E, then ok.
3394  if (!R || !E)
3395  return false;
3396  }
3397 
3398  // Do not tail call optimize vararg calls.
3399  if (IsVarArg)
3400  return false;
3401 
3402  // Also avoid tail call optimization if either caller or callee uses struct
3403  // return semantics.
3404  if (IsCalleeStructRet || IsCallerStructRet)
3405  return false;
3406 
3407  // In addition to the cases above, we also disable Tail Call Optimization if
3408  // the calling convention code that at least one outgoing argument needs to
3409  // go on the stack. We cannot check that here because at this point that
3410  // information is not available.
3411  return true;
3412 }
3413 
3414 /// Returns the target specific optimal type for load and store operations as
3415 /// a result of memset, memcpy, and memmove lowering.
3416 ///
3417 /// If DstAlign is zero that means it's safe to destination alignment can
3418 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3419 /// a need to check it against alignment requirement, probably because the
3420 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
3421 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3422 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3423 /// does not need to be loaded. It returns EVT::Other if the type should be
3424 /// determined using generic target-independent logic.
3426  const MemOp &Op, const AttributeList &FuncAttributes) const {
3427  if (Op.size() >= 8 && Op.isAligned(Align(8)))
3428  return MVT::i64;
3429  if (Op.size() >= 4 && Op.isAligned(Align(4)))
3430  return MVT::i32;
3431  if (Op.size() >= 2 && Op.isAligned(Align(2)))
3432  return MVT::i16;
3433  return MVT::Other;
3434 }
3435 
3437  LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
3438  Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const {
3439  MVT SVT = VT.getSimpleVT();
3440  if (Subtarget.isHVXVectorType(SVT, true))
3441  return allowsHvxMemoryAccess(SVT, Flags, Fast);
3443  Context, DL, VT, AddrSpace, Alignment, Flags, Fast);
3444 }
3445 
3447  EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
3448  bool *Fast) const {
3449  MVT SVT = VT.getSimpleVT();
3450  if (Subtarget.isHVXVectorType(SVT, true))
3451  return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
3452  if (Fast)
3453  *Fast = false;
3454  return false;
3455 }
3456 
3457 std::pair<const TargetRegisterClass*, uint8_t>
3458 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3459  MVT VT) const {
3460  if (Subtarget.isHVXVectorType(VT, true)) {
3461  unsigned BitWidth = VT.getSizeInBits();
3462  unsigned VecWidth = Subtarget.getVectorLength() * 8;
3463 
3464  if (VT.getVectorElementType() == MVT::i1)
3465  return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3466  if (BitWidth == VecWidth)
3467  return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3468  assert(BitWidth == 2 * VecWidth);
3469  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3470  }
3471 
3473 }
3474 
3476  ISD::LoadExtType ExtTy, EVT NewVT) const {
3477  // TODO: This may be worth removing. Check regression tests for diffs.
3478  if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3479  return false;
3480 
3481  auto *L = cast<LoadSDNode>(Load);
3482  std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3483  // Small-data object, do not shrink.
3484  if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3485  return false;
3486  if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3487  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3488  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3489  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3490  }
3491  return true;
3492 }
3493 
3495  AtomicOrdering Ord) const {
3496  BasicBlock *BB = Builder.GetInsertBlock();
3497  Module *M = BB->getParent()->getParent();
3498  auto PT = cast<PointerType>(Addr->getType());
3499  Type *Ty = PT->getElementType();
3500  unsigned SZ = Ty->getPrimitiveSizeInBits();
3501  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
3502  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3503  : Intrinsic::hexagon_L4_loadd_locked;
3504  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3505 
3506  PointerType *NewPtrTy
3507  = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
3508  Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3509 
3510  Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3511 
3512  return Builder.CreateBitCast(Call, Ty);
3513 }
3514 
3515 /// Perform a store-conditional operation to Addr. Return the status of the
3516 /// store. This should be 0 if the store succeeded, non-zero otherwise.
3518  Value *Val, Value *Addr, AtomicOrdering Ord) const {
3519  BasicBlock *BB = Builder.GetInsertBlock();
3520  Module *M = BB->getParent()->getParent();
3521  Type *Ty = Val->getType();
3522  unsigned SZ = Ty->getPrimitiveSizeInBits();
3523 
3524  Type *CastTy = Builder.getIntNTy(SZ);
3525  assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
3526  Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3527  : Intrinsic::hexagon_S4_stored_locked;
3528  Function *Fn = Intrinsic::getDeclaration(M, IntID);
3529 
3530  unsigned AS = Addr->getType()->getPointerAddressSpace();
3531  Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3532  Val = Builder.CreateBitCast(Val, CastTy);
3533 
3534  Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3535  Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3536  Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3537  return Ext;
3538 }
3539 
3542  // Do not expand loads and stores that don't exceed 64 bits.
3543  return LI->getType()->getPrimitiveSizeInBits() > 64
3546 }
3547 
3549  // Do not expand loads and stores that don't exceed 64 bits.
3550  return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3551 }
3552 
3555  AtomicCmpXchgInst *AI) const {
3557 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:929
llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
Definition: SelectionDAG.h:960
i
i
Definition: README.txt:29
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1349
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:273
llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
Definition: TargetLowering.h:3064
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
ValueTypes.h
llvm::HexagonISD::QFALSE
@ QFALSE
Definition: HexagonISelLowering.h:81
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1536
llvm::HexagonTargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1149
llvm::StoreSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:2305
llvm::HexagonTargetLowering::IsEligibleForTailCallOptimization
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
Definition: HexagonISelLowering.cpp:3363
llvm::Type::isSized
bool isSized(SmallPtrSetImpl< Type * > *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:272
MinimumJumpTables
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::ZeroOrMore, cl::init(5), cl::desc("Set minimum jump tables"))
llvm::TargetLowering::LowerOperationWrapper
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Definition: SelectionDAGBuilder.cpp:9672
llvm::HexagonTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
Definition: HexagonISelLowering.cpp:2059
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2093
llvm::ISD::VECTOR_SHUFFLE
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:557
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:499
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
Definition: TargetLowering.h:2240
llvm::HexagonTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1093
llvm::HexagonTargetLowering::LowerEH_RETURN
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:3027
llvm::InlineAsm::Op_FirstOperand
@ Op_FirstOperand
Definition: InlineAsm.h:213
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:919
B1
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:148
llvm::HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: HexagonISelLowering.cpp:3554
llvm::ISD::SETLE
@ SETLE
Definition: ISDOpcodes.h:1360
llvm::ISD::INTRINSIC_VOID
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition: ISDOpcodes.h:192
llvm::ISD::MemIndexedMode
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1285
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
Definition: AllocatorList.h:23
llvm::HexagonSubtarget::useSmallData
bool useSmallData() const
Definition: HexagonSubtarget.h:196
llvm::HexagonMachineFunctionInfo::setHasEHReturn
void setHasEHReturn(bool H=true)
Definition: HexagonMachineFunctionInfo.h:79
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:74
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Definition: SelectionDAGNodes.h:958
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::HexagonSubtarget::getFrameLowering
const HexagonFrameLowering * getFrameLowering() const override
Definition: HexagonSubtarget.h:126
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:36
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:193
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:618
llvm::MVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: MachineValueType.h:331
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:833
llvm::Intrinsic::getDeclaration
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1291
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1361
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineFrameInfo::getNumFixedObjects
unsigned getNumFixedObjects() const
Return the number of fixed objects.
Definition: MachineFrameInfo.h:394
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:373
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4101
llvm::HexagonII::MO_GDGOT
@ MO_GDGOT
Definition: HexagonBaseInfo.h:195
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:931
IntrinsicInst.h
llvm::HexagonTargetLowering::emitLoadLinked
Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
Definition: HexagonISelLowering.cpp:3494
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::ISD::FMINNUM
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:883
llvm::ISD::AssertSext
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition: ISDOpcodes.h:59
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:735
llvm::Function::empty
bool empty() const
Definition: Function.h:770
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:152
llvm::HexagonISD::EH_RETURN
@ EH_RETURN
Definition: HexagonISelLowering.h:67
llvm::Function
Definition: Function.h:61
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
llvm::ISD::CONCAT_VECTORS
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:513
llvm::HexagonTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: HexagonISelLowering.cpp:3226
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::HexagonTargetLowering::LowerINLINEASM
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:639
llvm::HexagonISD::INSERT
@ INSERT
Definition: HexagonISelLowering.h:61
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:651
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::HexagonTargetLowering::LowerVECTOR_SHIFT
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2269
llvm::ISD::UADDO
@ UADDO
Definition: ISDOpcodes.h:304
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:916
llvm::HexagonMachineFunctionInfo::setFirstNamedArgFrameIndex
void setFirstNamedArgFrameIndex(int v)
Definition: HexagonMachineFunctionInfo.h:55
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
Definition: SelectionDAG.cpp:6622
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:614
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::HexagonTargetLowering::getPICJumpTableRelocBase
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
Definition: HexagonISelLowering.cpp:3213
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:3062
llvm::TLSModel::GeneralDynamic
@ GeneralDynamic
Definition: CodeGen.h:43
llvm::ISD::FSHL
@ FSHL
Definition: ISDOpcodes.h:647
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:131
llvm::TargetLoweringBase::setMinCmpXchgSizeInBits
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Definition: TargetLowering.h:2289
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1577
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::HexagonMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex()
Definition: HexagonMachineFunctionInfo.h:50
llvm::HexagonTargetLowering::shouldExpandAtomicStoreInIR
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns true if the given (atomic) store should be expanded by the IR-level AtomicExpand pass into an...
Definition: HexagonISelLowering.cpp:3548
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1356
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:130
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:347
InlineAsm.h
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:997
llvm::HexagonISD::QCAT
@ QCAT
Definition: HexagonISelLowering.h:79
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:7965
llvm::HexagonTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: HexagonISelLowering.cpp:3168
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::MVT::v2i1
@ v2i1
Definition: MachineValueType.h:62
llvm::HexagonTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: HexagonISelLowering.cpp:3054
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1643
llvm::SDVTList::NumVTs
unsigned int NumVTs
Definition: SelectionDAGNodes.h:81
HexagonSubtarget.h
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::HexagonISD::PFALSE
@ PFALSE
Definition: HexagonISelLowering.h:71
llvm::HexagonISD::READCYCLE
@ READCYCLE
Definition: HexagonISelLowering.h:69
llvm::getSplatValue
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
Definition: VectorUtils.cpp:350
ErrorHandling.h
llvm::HexagonRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: HexagonRegisterInfo.cpp:415
llvm::HexagonISD::COMBINE
@ COMBINE
Definition: HexagonISelLowering.h:55
llvm::IRBuilder<>
llvm::HexagonTargetLowering::HexagonTargetLowering
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
Definition: HexagonISelLowering.cpp:1415
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1325
llvm::ISD::FLOG2
@ FLOG2
Definition: ISDOpcodes.h:860
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1348
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:717
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
Definition: TargetLoweringBase.cpp:1228
llvm::ISD::FMA
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition: ISDOpcodes.h:460
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:770
llvm::TargetLowering::DAGCombinerInfo::DAG
SelectionDAG & DAG
Definition: TargetLowering.h:3495
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:233
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2255
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:247
llvm::MemOp
Definition: TargetLowering.h:108
llvm::HexagonISD::SUBC
@ SUBC
Definition: HexagonISelLowering.h:40
llvm::SelectionDAG::getMemBasePlusOffset
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
Definition: SelectionDAG.cpp:6151
R4
#define R4(n)
APInt.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
llvm::HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1248
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1351
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
Definition: TargetMachine.cpp:70
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::HexagonTargetLowering::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: HexagonISelLowering.cpp:2049
AlignLoads
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
Module.h
llvm::HexagonTargetLowering::LowerToTLSLocalExecModel
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1336
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:700
llvm::AttributeList
Definition: Attributes.h:375
llvm::SelectionDAG::getZeroExtendInReg
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
Definition: SelectionDAG.cpp:1288
llvm::HexagonTargetObjectFile::isGlobalInSmallSection
bool isGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const
Return true if this global value should be placed into small data/bss section.
Definition: HexagonTargetObjectFile.cpp:199
llvm::HexagonTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
Definition: HexagonISelLowering.cpp:379
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
getUnderLyingObjectForBrevLdIntr
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
Definition: HexagonISelLowering.cpp:1964
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7294
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1244
llvm::HexagonISD::D2P
@ D2P
Definition: HexagonISelLowering.h:72
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:234
T1
#define T1
Definition: Mips16ISelLowering.cpp:340
llvm::HexagonTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: HexagonISelLowering.cpp:182
llvm::ISD::SETCC
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:687
llvm::MVT::integer_valuetypes
static mvt_range integer_valuetypes()
Definition: MachineValueType.h:1362
llvm::ConstantFP::getValueAPF
const APFloat & getValueAPF() const
Definition: Constants.h:295
llvm::TargetLowering::CallLoweringInfo::CB
const CallBase * CB
Definition: TargetLowering.h:3719
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:46
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2260
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::HexagonISD::OP_BEGIN
@ OP_BEGIN
Definition: HexagonISelLowering.h:35
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
MaxStoresPerMemmoveOptSizeCL
static cl::opt< int > MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, cl::ZeroOrMore, cl::init(4), cl::desc("Max #stores to inline memmove"))
llvm::HexagonISD::VUNPACKU
@ VUNPACKU
Definition: HexagonISelLowering.h:94
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::MachineFrameInfo::setAdjustsStack
void setAdjustsStack(bool V)
Definition: MachineFrameInfo.h:599
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:894
llvm::HexagonTargetLowering::shouldReduceLoadWidth
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
Definition: HexagonISelLowering.cpp:3475
llvm::FunctionType::getNumParams
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1026
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1316
llvm::HexagonISD::TC_RETURN
@ TC_RETURN
Definition: HexagonISelLowering.h:66
llvm::HexagonTargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1010
llvm::HexagonTargetLowering::LowerROTL
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2274
llvm::SelectionDAG::getZExtOrTrunc
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
Definition: SelectionDAG.cpp:1273
HexagonTargetMachine.h
llvm::isPowerOf2_32
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:492
llvm::HexagonTargetLowering::LowerPREFETCH
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:687
llvm::ConstantPoolSDNode::getAlign
Align getAlign() const
Definition: SelectionDAGNodes.h:1867
CC_SkipOdd
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
Definition: HexagonISelLowering.cpp:137
SelectionDAG.h
llvm::HexagonISD::RET_FLAG
@ RET_FLAG
Definition: HexagonISelLowering.h:50
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SelectionDAG::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:442
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:204
HEXAGON_LRFP_SIZE
#define HEXAGON_LRFP_SIZE
Definition: HexagonMCTargetDesc.h:30
llvm::HexagonII::MO_GOT
@ MO_GOT
MO_GOT - Indicates a GOT-relative relocation.
Definition: HexagonBaseInfo.h:184
llvm::ISD::SMAX
@ SMAX
Definition: ISDOpcodes.h:612
llvm::TargetLowering::expandUnalignedStore
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
Definition: TargetLowering.cpp:7541
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::HexagonISD::V2Q
@ V2Q
Definition: HexagonISelLowering.h:74
llvm::ISD::FABS
@ FABS
Definition: ISDOpcodes.h:852
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:160
llvm::HexagonISD::VINSERTW0
@ VINSERTW0
Definition: HexagonISelLowering.h:64
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:283
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:129
MachineRegisterInfo.h
llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2816
llvm::HexagonSubtarget::getTypeAlignment
unsigned getTypeAlignment(MVT Ty) const
Definition: HexagonSubtarget.h:291
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:354
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1952
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:965
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::ISD::ROTL
@ ROTL
Definition: ISDOpcodes.h:645
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:110
llvm::ISD::FFLOOR
@ FFLOOR
Definition: ISDOpcodes.h:870
CommandLine.h
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1316
llvm::HexagonTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: HexagonISelLowering.cpp:2076
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:948
llvm::ISD::FSHR
@ FSHR
Definition: ISDOpcodes.h:648
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7244
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1505
llvm::TargetLowering::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: TargetLowering.h:3697
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CCValAssign::AExt
@ AExt
Definition: CallingConvLower.h:39
llvm::HexagonTargetLowering::LowerGLOBALADDRESS
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1198
llvm::HexagonTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: HexagonISelLowering.cpp:3244
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
Definition: TargetLowering.h:1100
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:71
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:679
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2148
GlobalValue.h
llvm::SDValue::getValueType
EVT getValueType() const
Return the ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:1113
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
TargetMachine.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:653
llvm::HexagonISD::VALIGNADDR
@ VALIGNADDR
Definition: HexagonISelLowering.h:86
EnableHexSDNodeSched
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Hexagon SDNode scheduling"))
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::ISD::SELECT
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:664
llvm::HexagonTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: HexagonISelLowering.cpp:3138
llvm::HexagonII::MO_IEGOT
@ MO_IEGOT
Definition: HexagonBaseInfo.h:207
llvm::HexagonTargetLowering::LowerATOMIC_FENCE
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1192
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:714
llvm::PHINode::getIncomingValue
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
Definition: Instructions.h:2666
llvm::HexagonMachineFunctionInfo
Hexagon target-specific information for each MachineFunction.
Definition: HexagonMachineFunctionInfo.h:25
EnableFastMath
static cl::opt< bool > EnableFastMath("ffast-math", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enable Fast Math processing"))
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:88
llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps
bool isBeforeLegalizeOps() const
Definition: TargetLowering.h:3501
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:730
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:625
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1358
llvm::MachineFrameInfo::ensureMaxAlignment
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
Definition: MachineFrameInfo.cpp:31
P2
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::HexagonISD::ISEL
@ ISEL
Definition: HexagonISelLowering.h:95
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::MCOI::OperandFlags
OperandFlags
These are flags set on operands, but should be considered private, all access should go through the M...
Definition: MCInstrDesc.h:49
llvm::HexagonISD::Q2V
@ Q2V
Definition: HexagonISelLowering.h:75
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:947
llvm::ISD::SIGN_EXTEND_INREG
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:732
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
Intrinsics.h
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARM_PROC::A
@ A
Definition: ARMBaseInfo.h:34
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1346
llvm::HexagonTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
Definition: HexagonISelLowering.cpp:3309
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:217
llvm::GlobalObject
Definition: GlobalObject.h:30
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
llvm::HexagonTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: HexagonISelLowering.cpp:2065
llvm::HexagonTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: HexagonISelLowering.cpp:2070
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::HexagonTargetLowering::getPostIndexedAddressParts
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
Definition: HexagonISelLowering.cpp:609
llvm::HexagonTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: HexagonISelLowering.cpp:239
llvm::HexagonISD::QTRUE
@ QTRUE
Definition: HexagonISelLowering.h:80
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::ISD::FROUND
@ FROUND
Definition: ISDOpcodes.h:868
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3489
llvm::HexagonTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: HexagonISelLowering.cpp:3347
llvm::CCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
Definition: CallingConvLower.cpp:118
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:720
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:302
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:643
llvm::HexagonTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: HexagonISelLowering.cpp:1986
llvm::HexagonTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: HexagonISelLowering.cpp:244
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:231
llvm::ISD::GLOBAL_OFFSET_TABLE
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition: ISDOpcodes.h:80
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:249
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2140
llvm::TypeSize::Fixed
static TypeSize Fixed(ScalarTy MinVal)
Definition: TypeSize.h:423
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::MVT::v8i1
@ v8i1
Definition: MachineValueType.h:64
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:203
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::HexagonRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: HexagonRegisterInfo.cpp:401
llvm::Instruction
Definition: Instruction.h:45
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::TargetLowering::CallLoweringInfo::DoesNotReturn
bool DoesNotReturn
Definition: TargetLowering.h:3699
llvm::HexagonTargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:1136
llvm::Operator::getOpcode
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:40
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
Definition: TargetLowering.h:2197
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:724
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::HexagonISD::NodeType
NodeType
Definition: HexagonISelLowering.h:34
llvm::HexagonISD::VLSR
@ VLSR
Definition: HexagonISelLowering.h:58
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
llvm::ISD::FNEARBYINT
@ FNEARBYINT
Definition: ISDOpcodes.h:867
llvm::ISD::FRINT
@ FRINT
Definition: ISDOpcodes.h:866
llvm::LSBaseSDNode::isUnindexed
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
Definition: SelectionDAGNodes.h:2246
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:885
llvm::HexagonISD::VEXTRACTW
@ VEXTRACTW
Definition: HexagonISelLowering.h:63
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
Definition: TargetLowering.h:3077
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::HexagonTargetLowering::LowerINSERT_SUBVECTOR
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: HexagonISelLowering.cpp:2838
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:617
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::HexagonISD::TYPECAST
@ TYPECAST
Definition: HexagonISelLowering.h:82
llvm::ISD::SPLAT_VECTOR
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:584
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1704
llvm::APFloat::bitcastToAPInt
APInt bitcastToAPInt() const
Definition: APFloat.h:1132
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:900
getBrevLdObject
static Value * getBrevLdObject(Value *V)
Definition: HexagonISel