LLVM  13.0.0git
MipsISelLowering.cpp
Go to the documentation of this file.
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsISelLowering.h"
18 #include "MipsCCState.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "MipsTargetObjectFile.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/StringSwitch.h"
50 #include "llvm/IR/CallingConv.h"
51 #include "llvm/IR/Constants.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/DebugLoc.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/Function.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
64 #include "llvm/Support/Compiler.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
87  cl::desc("MIPS: Don't trap on integer division by zero."),
88  cl::init(false));
89 
91 
92 static const MCPhysReg Mips64DPRegs[8] = {
93  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
95 };
96 
97 // If I is a shifted mask, set the size (Size) and the first bit of the
98 // mask (Pos), and return true.
99 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
100 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
101  if (!isShiftedMask_64(I))
102  return false;
103 
105  Pos = countTrailingZeros(I);
106  return true;
107 }
108 
109 // The MIPS MSA ABI passes vector arguments in the integer register set.
110 // The number of integer registers used is dependant on the ABI used.
112  CallingConv::ID CC,
113  EVT VT) const {
114  if (!VT.isVector())
115  return getRegisterType(Context, VT);
116 
117  return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
118  : MVT::i64;
119 }
120 
122  CallingConv::ID CC,
123  EVT VT) const {
124  if (VT.isVector())
125  return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
127 }
128 
130  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
131  unsigned &NumIntermediates, MVT &RegisterVT) const {
132  // Break down vector types to either 2 i64s or 4 i32s.
133  RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
134  IntermediateVT = RegisterVT;
135  NumIntermediates =
136  VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits()
137  ? VT.getVectorNumElements()
138  : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits());
139  return NumIntermediates;
140 }
141 
145  return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty);
146 }
147 
148 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
149  SelectionDAG &DAG,
150  unsigned Flag) const {
151  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
152 }
153 
154 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
155  SelectionDAG &DAG,
156  unsigned Flag) const {
157  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
158 }
159 
160 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
161  SelectionDAG &DAG,
162  unsigned Flag) const {
163  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
164 }
165 
166 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
167  SelectionDAG &DAG,
168  unsigned Flag) const {
169  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
170 }
171 
172 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
173  SelectionDAG &DAG,
174  unsigned Flag) const {
175  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
176  N->getOffset(), Flag);
177 }
178 
179 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
180  switch ((MipsISD::NodeType)Opcode) {
181  case MipsISD::FIRST_NUMBER: break;
182  case MipsISD::JmpLink: return "MipsISD::JmpLink";
183  case MipsISD::TailCall: return "MipsISD::TailCall";
184  case MipsISD::Highest: return "MipsISD::Highest";
185  case MipsISD::Higher: return "MipsISD::Higher";
186  case MipsISD::Hi: return "MipsISD::Hi";
187  case MipsISD::Lo: return "MipsISD::Lo";
188  case MipsISD::GotHi: return "MipsISD::GotHi";
189  case MipsISD::TlsHi: return "MipsISD::TlsHi";
190  case MipsISD::GPRel: return "MipsISD::GPRel";
191  case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
192  case MipsISD::Ret: return "MipsISD::Ret";
193  case MipsISD::ERet: return "MipsISD::ERet";
194  case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
195  case MipsISD::FMS: return "MipsISD::FMS";
196  case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
197  case MipsISD::FPCmp: return "MipsISD::FPCmp";
198  case MipsISD::FSELECT: return "MipsISD::FSELECT";
199  case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
200  case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
201  case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
202  case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
203  case MipsISD::MFHI: return "MipsISD::MFHI";
204  case MipsISD::MFLO: return "MipsISD::MFLO";
205  case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
206  case MipsISD::Mult: return "MipsISD::Mult";
207  case MipsISD::Multu: return "MipsISD::Multu";
208  case MipsISD::MAdd: return "MipsISD::MAdd";
209  case MipsISD::MAddu: return "MipsISD::MAddu";
210  case MipsISD::MSub: return "MipsISD::MSub";
211  case MipsISD::MSubu: return "MipsISD::MSubu";
212  case MipsISD::DivRem: return "MipsISD::DivRem";
213  case MipsISD::DivRemU: return "MipsISD::DivRemU";
214  case MipsISD::DivRem16: return "MipsISD::DivRem16";
215  case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
216  case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
217  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
218  case MipsISD::Wrapper: return "MipsISD::Wrapper";
219  case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
220  case MipsISD::Sync: return "MipsISD::Sync";
221  case MipsISD::Ext: return "MipsISD::Ext";
222  case MipsISD::Ins: return "MipsISD::Ins";
223  case MipsISD::CIns: return "MipsISD::CIns";
224  case MipsISD::LWL: return "MipsISD::LWL";
225  case MipsISD::LWR: return "MipsISD::LWR";
226  case MipsISD::SWL: return "MipsISD::SWL";
227  case MipsISD::SWR: return "MipsISD::SWR";
228  case MipsISD::LDL: return "MipsISD::LDL";
229  case MipsISD::LDR: return "MipsISD::LDR";
230  case MipsISD::SDL: return "MipsISD::SDL";
231  case MipsISD::SDR: return "MipsISD::SDR";
232  case MipsISD::EXTP: return "MipsISD::EXTP";
233  case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
234  case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
235  case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
236  case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
237  case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
238  case MipsISD::SHILO: return "MipsISD::SHILO";
239  case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
240  case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
241  case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
242  case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
243  case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
244  case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
245  case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
246  case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
247  case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
248  case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
249  case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
250  case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
251  case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
252  case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
253  case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
254  case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
255  case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
256  case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
257  case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
258  case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
259  case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
260  case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
261  case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
262  case MipsISD::MULT: return "MipsISD::MULT";
263  case MipsISD::MULTU: return "MipsISD::MULTU";
264  case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
265  case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
266  case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
267  case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
268  case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
269  case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
270  case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
271  case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
272  case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
273  case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
274  case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
275  case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
276  case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
277  case MipsISD::VCEQ: return "MipsISD::VCEQ";
278  case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
279  case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
280  case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
281  case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
282  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
283  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
284  case MipsISD::VNOR: return "MipsISD::VNOR";
285  case MipsISD::VSHF: return "MipsISD::VSHF";
286  case MipsISD::SHF: return "MipsISD::SHF";
287  case MipsISD::ILVEV: return "MipsISD::ILVEV";
288  case MipsISD::ILVOD: return "MipsISD::ILVOD";
289  case MipsISD::ILVL: return "MipsISD::ILVL";
290  case MipsISD::ILVR: return "MipsISD::ILVR";
291  case MipsISD::PCKEV: return "MipsISD::PCKEV";
292  case MipsISD::PCKOD: return "MipsISD::PCKOD";
293  case MipsISD::INSVE: return "MipsISD::INSVE";
294  }
295  return nullptr;
296 }
297 
299  const MipsSubtarget &STI)
300  : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
301  // Mips does not have i1 type, so use i32 for
302  // setcc operations results (slt, sgt, ...).
305  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
306  // does. Integer booleans still use 0 and 1.
307  if (Subtarget.hasMips32r6())
310 
311  // Load extented operations for i1 types must be promoted
312  for (MVT VT : MVT::integer_valuetypes()) {
316  }
317 
318  // MIPS doesn't have extending float->double load/store. Set LoadExtAction
319  // for f32, f16
320  for (MVT VT : MVT::fp_valuetypes()) {
323  }
324 
325  // Set LoadExtAction for f16 vectors to Expand
327  MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
328  if (F16VT.isValid())
329  setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
330  }
331 
334 
336 
337  // Used by legalize types to correctly generate the setcc result.
338  // Without this, every float setcc comes with a AND/OR with the result,
339  // we don't want this, since the fpcmp result goes to a flag register,
340  // which is used implicitly by brcond and select operations.
342 
343  // Mips Custom Operations
359 
360  if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) {
363  }
364 
365  if (Subtarget.isGP64bit()) {
378  }
379 
380  if (!Subtarget.isGP64bit()) {
384  }
385 
387  if (Subtarget.isGP64bit())
389 
398 
399  // Operations not directly supported by Mips.
413  if (Subtarget.hasCnMips()) {
416  } else {
419  }
426 
427  if (!Subtarget.hasMips32r2())
429 
430  if (!Subtarget.hasMips64r2())
432 
449 
450  // Lower f16 conversion operations into library calls
455 
457 
462 
463  // Use the default for now
466 
467  if (!Subtarget.isGP64bit()) {
470  }
471 
472  if (!Subtarget.hasMips32r2()) {
475  }
476 
477  // MIPS16 lacks MIPS32's clz and clo instructions.
480  if (!Subtarget.hasMips64())
482 
483  if (!Subtarget.hasMips32r2())
485  if (!Subtarget.hasMips64r2())
487 
488  if (Subtarget.isGP64bit()) {
493  }
494 
496 
506 
507  if (ABI.IsO32()) {
508  // These libcalls are not available in 32-bit.
509  setLibcallName(RTLIB::SHL_I128, nullptr);
510  setLibcallName(RTLIB::SRL_I128, nullptr);
511  setLibcallName(RTLIB::SRA_I128, nullptr);
512  }
513 
515 
516  // The arguments on the stack are defined in terms of 4-byte slots on O32
517  // and 8-byte slots on N32/N64.
519  : Align(4));
520 
521  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
522 
523  MaxStoresPerMemcpy = 16;
524 
525  isMicroMips = Subtarget.inMicroMipsMode();
526 }
527 
528 const MipsTargetLowering *
530  const MipsSubtarget &STI) {
531  if (STI.inMips16Mode())
532  return createMips16TargetLowering(TM, STI);
533 
534  return createMipsSETargetLowering(TM, STI);
535 }
536 
537 // Create a fast isel object.
538 FastISel *
540  const TargetLibraryInfo *libInfo) const {
541  const MipsTargetMachine &TM =
542  static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
543 
544  // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
545  bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
548 
549  // Disable if either of the following is true:
550  // We do not generate PIC, the ABI is not O32, XGOT is being used.
551  if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
552  Subtarget.useXGOT())
553  UseFastISel = false;
554 
555  return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
556 }
557 
559  EVT VT) const {
560  if (!VT.isVector())
561  return MVT::i32;
563 }
564 
567  const MipsSubtarget &Subtarget) {
568  if (DCI.isBeforeLegalizeOps())
569  return SDValue();
570 
571  EVT Ty = N->getValueType(0);
572  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
573  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
574  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
576  SDLoc DL(N);
577 
578  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
579  N->getOperand(0), N->getOperand(1));
580  SDValue InChain = DAG.getEntryNode();
581  SDValue InGlue = DivRem;
582 
583  // insert MFLO
584  if (N->hasAnyUseOfValue(0)) {
585  SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
586  InGlue);
587  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
588  InChain = CopyFromLo.getValue(1);
589  InGlue = CopyFromLo.getValue(2);
590  }
591 
592  // insert MFHI
593  if (N->hasAnyUseOfValue(1)) {
594  SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
595  HI, Ty, InGlue);
596  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
597  }
598 
599  return SDValue();
600 }
601 
603  switch (CC) {
604  default: llvm_unreachable("Unknown fp condition code!");
605  case ISD::SETEQ:
606  case ISD::SETOEQ: return Mips::FCOND_OEQ;
607  case ISD::SETUNE: return Mips::FCOND_UNE;
608  case ISD::SETLT:
609  case ISD::SETOLT: return Mips::FCOND_OLT;
610  case ISD::SETGT:
611  case ISD::SETOGT: return Mips::FCOND_OGT;
612  case ISD::SETLE:
613  case ISD::SETOLE: return Mips::FCOND_OLE;
614  case ISD::SETGE:
615  case ISD::SETOGE: return Mips::FCOND_OGE;
616  case ISD::SETULT: return Mips::FCOND_ULT;
617  case ISD::SETULE: return Mips::FCOND_ULE;
618  case ISD::SETUGT: return Mips::FCOND_UGT;
619  case ISD::SETUGE: return Mips::FCOND_UGE;
620  case ISD::SETUO: return Mips::FCOND_UN;
621  case ISD::SETO: return Mips::FCOND_OR;
622  case ISD::SETNE:
623  case ISD::SETONE: return Mips::FCOND_ONE;
624  case ISD::SETUEQ: return Mips::FCOND_UEQ;
625  }
626 }
627 
628 /// This function returns true if the floating point conditional branches and
629 /// conditional moves which use condition code CC should be inverted.
631  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
632  return false;
633 
634  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
635  "Illegal Condition Code");
636 
637  return true;
638 }
639 
640 // Creates and returns an FPCmp node from a setcc node.
641 // Returns Op if setcc is not a floating point comparison.
642 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
643  // must be a SETCC node
644  if (Op.getOpcode() != ISD::SETCC)
645  return Op;
646 
647  SDValue LHS = Op.getOperand(0);
648 
649  if (!LHS.getValueType().isFloatingPoint())
650  return Op;
651 
652  SDValue RHS = Op.getOperand(1);
653  SDLoc DL(Op);
654 
655  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
656  // node if necessary.
657  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
658 
659  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
660  DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
661 }
662 
663 // Creates and returns a CMovFPT/F node.
665  SDValue False, const SDLoc &DL) {
666  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
667  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
668  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
669 
670  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
671  True.getValueType(), True, FCC0, False, Cond);
672 }
673 
676  const MipsSubtarget &Subtarget) {
677  if (DCI.isBeforeLegalizeOps())
678  return SDValue();
679 
680  SDValue SetCC = N->getOperand(0);
681 
682  if ((SetCC.getOpcode() != ISD::SETCC) ||
683  !SetCC.getOperand(0).getValueType().isInteger())
684  return SDValue();
685 
686  SDValue False = N->getOperand(2);
687  EVT FalseTy = False.getValueType();
688 
689  if (!FalseTy.isInteger())
690  return SDValue();
691 
692  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
693 
694  // If the RHS (False) is 0, we swap the order of the operands
695  // of ISD::SELECT (obviously also inverting the condition) so that we can
696  // take advantage of conditional moves using the $0 register.
697  // Example:
698  // return (a != 0) ? x : 0;
699  // load $reg, x
700  // movz $reg, $0, a
701  if (!FalseC)
702  return SDValue();
703 
704  const SDLoc DL(N);
705 
706  if (!FalseC->getZExtValue()) {
707  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
708  SDValue True = N->getOperand(1);
709 
710  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
711  SetCC.getOperand(1),
712  ISD::getSetCCInverse(CC, SetCC.getValueType()));
713 
714  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
715  }
716 
717  // If both operands are integer constants there's a possibility that we
718  // can do some interesting optimizations.
719  SDValue True = N->getOperand(1);
720  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
721 
722  if (!TrueC || !True.getValueType().isInteger())
723  return SDValue();
724 
725  // We'll also ignore MVT::i64 operands as this optimizations proves
726  // to be ineffective because of the required sign extensions as the result
727  // of a SETCC operator is always MVT::i32 for non-vector types.
728  if (True.getValueType() == MVT::i64)
729  return SDValue();
730 
731  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
732 
733  // 1) (a < x) ? y : y-1
734  // slti $reg1, a, x
735  // addiu $reg2, $reg1, y-1
736  if (Diff == 1)
737  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
738 
739  // 2) (a < x) ? y-1 : y
740  // slti $reg1, a, x
741  // xor $reg1, $reg1, 1
742  // addiu $reg2, $reg1, y-1
743  if (Diff == -1) {
744  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
745  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
746  SetCC.getOperand(1),
747  ISD::getSetCCInverse(CC, SetCC.getValueType()));
748  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
749  }
750 
751  // Could not optimize.
752  return SDValue();
753 }
754 
757  const MipsSubtarget &Subtarget) {
758  if (DCI.isBeforeLegalizeOps())
759  return SDValue();
760 
761  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
762 
763  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
764  if (!FalseC || FalseC->getZExtValue())
765  return SDValue();
766 
767  // Since RHS (False) is 0, we swap the order of the True/False operands
768  // (obviously also inverting the condition) so that we can
769  // take advantage of conditional moves using the $0 register.
770  // Example:
771  // return (a != 0) ? x : 0;
772  // load $reg, x
773  // movz $reg, $0, a
774  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
776 
777  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
778  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
779  ValueIfFalse, FCC, ValueIfTrue, Glue);
780 }
781 
784  const MipsSubtarget &Subtarget) {
785  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
786  return SDValue();
787 
788  SDValue FirstOperand = N->getOperand(0);
789  unsigned FirstOperandOpc = FirstOperand.getOpcode();
790  SDValue Mask = N->getOperand(1);
791  EVT ValTy = N->getValueType(0);
792  SDLoc DL(N);
793 
794  uint64_t Pos = 0, SMPos, SMSize;
795  ConstantSDNode *CN;
796  SDValue NewOperand;
797  unsigned Opc;
798 
799  // Op's second operand must be a shifted mask.
800  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
801  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
802  return SDValue();
803 
804  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
805  // Pattern match EXT.
806  // $dst = and ((sra or srl) $src , pos), (2**size - 1)
807  // => ext $dst, $src, pos, size
808 
809  // The second operand of the shift must be an immediate.
810  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
811  return SDValue();
812 
813  Pos = CN->getZExtValue();
814 
815  // Return if the shifted mask does not start at bit 0 or the sum of its size
816  // and Pos exceeds the word's size.
817  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
818  return SDValue();
819 
820  Opc = MipsISD::Ext;
821  NewOperand = FirstOperand.getOperand(0);
822  } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
823  // Pattern match CINS.
824  // $dst = and (shl $src , pos), mask
825  // => cins $dst, $src, pos, size
826  // mask is a shifted mask with consecutive 1's, pos = shift amount,
827  // size = population count.
828 
829  // The second operand of the shift must be an immediate.
830  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
831  return SDValue();
832 
833  Pos = CN->getZExtValue();
834 
835  if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
836  Pos + SMSize > ValTy.getSizeInBits())
837  return SDValue();
838 
839  NewOperand = FirstOperand.getOperand(0);
840  // SMSize is 'location' (position) in this case, not size.
841  SMSize--;
842  Opc = MipsISD::CIns;
843  } else {
844  // Pattern match EXT.
845  // $dst = and $src, (2**size - 1) , if size > 16
846  // => ext $dst, $src, pos, size , pos = 0
847 
848  // If the mask is <= 0xffff, andi can be used instead.
849  if (CN->getZExtValue() <= 0xffff)
850  return SDValue();
851 
852  // Return if the mask doesn't start at position 0.
853  if (SMPos)
854  return SDValue();
855 
856  Opc = MipsISD::Ext;
857  NewOperand = FirstOperand;
858  }
859  return DAG.getNode(Opc, DL, ValTy, NewOperand,
860  DAG.getConstant(Pos, DL, MVT::i32),
861  DAG.getConstant(SMSize, DL, MVT::i32));
862 }
863 
866  const MipsSubtarget &Subtarget) {
867  // Pattern match INS.
868  // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
869  // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
870  // => ins $dst, $src, size, pos, $src1
871  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
872  return SDValue();
873 
874  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
875  uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
876  ConstantSDNode *CN, *CN1;
877 
878  // See if Op's first operand matches (and $src1 , mask0).
879  if (And0.getOpcode() != ISD::AND)
880  return SDValue();
881 
882  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
883  !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
884  return SDValue();
885 
886  // See if Op's second operand matches (and (shl $src, pos), mask1).
887  if (And1.getOpcode() == ISD::AND &&
888  And1.getOperand(0).getOpcode() == ISD::SHL) {
889 
890  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
891  !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
892  return SDValue();
893 
894  // The shift masks must have the same position and size.
895  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
896  return SDValue();
897 
898  SDValue Shl = And1.getOperand(0);
899 
900  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
901  return SDValue();
902 
903  unsigned Shamt = CN->getZExtValue();
904 
905  // Return if the shift amount and the first bit position of mask are not the
906  // same.
907  EVT ValTy = N->getValueType(0);
908  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
909  return SDValue();
910 
911  SDLoc DL(N);
912  return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
913  DAG.getConstant(SMPos0, DL, MVT::i32),
914  DAG.getConstant(SMSize0, DL, MVT::i32),
915  And0.getOperand(0));
916  } else {
917  // Pattern match DINS.
918  // $dst = or (and $src, mask0), mask1
919  // where mask0 = ((1 << SMSize0) -1) << SMPos0
920  // => dins $dst, $src, pos, size
921  if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
922  ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
923  (SMSize0 + SMPos0 <= 32))) {
924  // Check if AND instruction has constant as argument
925  bool isConstCase = And1.getOpcode() != ISD::AND;
926  if (And1.getOpcode() == ISD::AND) {
927  if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
928  return SDValue();
929  } else {
930  if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
931  return SDValue();
932  }
933  // Don't generate INS if constant OR operand doesn't fit into bits
934  // cleared by constant AND operand.
935  if (CN->getSExtValue() & CN1->getSExtValue())
936  return SDValue();
937 
938  SDLoc DL(N);
939  EVT ValTy = N->getOperand(0)->getValueType(0);
940  SDValue Const1;
941  SDValue SrlX;
942  if (!isConstCase) {
943  Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
944  SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
945  }
946  return DAG.getNode(
947  MipsISD::Ins, DL, N->getValueType(0),
948  isConstCase
949  ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
950  : SrlX,
951  DAG.getConstant(SMPos0, DL, MVT::i32),
952  DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
953  : SMSize0,
954  DL, MVT::i32),
955  And0->getOperand(0));
956 
957  }
958  return SDValue();
959  }
960 }
961 
963  const MipsSubtarget &Subtarget) {
964  // ROOTNode must have a multiplication as an operand for the match to be
965  // successful.
966  if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
967  ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
968  return SDValue();
969 
970  // We don't handle vector types here.
971  if (ROOTNode->getValueType(0).isVector())
972  return SDValue();
973 
974  // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
975  // arithmetic. E.g.
976  // (add (mul a b) c) =>
977  // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
978  // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
979  // or
980  // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
981  //
982  // The overhead of setting up the Hi/Lo registers and reassembling the
983  // result makes this a dubious optimzation for MIPS64. The core of the
984  // problem is that Hi/Lo contain the upper and lower 32 bits of the
985  // operand and result.
986  //
987  // It requires a chain of 4 add/mul for MIPS64R2 to get better code
988  // density than doing it naively, 5 for MIPS64. Additionally, using
989  // madd/msub on MIPS64 requires the operands actually be 32 bit sign
990  // extended operands, not true 64 bit values.
991  //
992  // FIXME: For the moment, disable this completely for MIPS64.
993  if (Subtarget.hasMips64())
994  return SDValue();
995 
996  SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
997  ? ROOTNode->getOperand(0)
998  : ROOTNode->getOperand(1);
999 
1000  SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1001  ? ROOTNode->getOperand(1)
1002  : ROOTNode->getOperand(0);
1003 
1004  // Transform this to a MADD only if the user of this node is the add.
1005  // If there are other users of the mul, this function returns here.
1006  if (!Mult.hasOneUse())
1007  return SDValue();
1008 
1009  // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1010  // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1011  // of the multiply must have 32 or more sign bits, otherwise we cannot
1012  // perform this optimization. We have to check this here as we're performing
1013  // this optimization pre-legalization.
1014  SDValue MultLHS = Mult->getOperand(0);
1015  SDValue MultRHS = Mult->getOperand(1);
1016 
1017  bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1018  MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1019  bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1020  MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1021 
1022  if (!IsSigned && !IsUnsigned)
1023  return SDValue();
1024 
1025  // Initialize accumulator.
1026  SDLoc DL(ROOTNode);
1027  SDValue TopHalf;
1028  SDValue BottomHalf;
1029  BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1030  CurDAG.getIntPtrConstant(0, DL));
1031 
1032  TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1033  CurDAG.getIntPtrConstant(1, DL));
1034  SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1035  BottomHalf,
1036  TopHalf);
1037 
1038  // Create MipsMAdd(u) / MipsMSub(u) node.
1039  bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1040  unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1041  : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1042  SDValue MAddOps[3] = {
1043  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1044  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1045  EVT VTs[2] = {MVT::i32, MVT::i32};
1046  SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1047 
1048  SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1049  SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1050  SDValue Combined =
1051  CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1052  return Combined;
1053 }
1054 
1057  const MipsSubtarget &Subtarget) {
1058  // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1059  if (DCI.isBeforeLegalizeOps()) {
1060  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1061  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1062  return performMADD_MSUBCombine(N, DAG, Subtarget);
1063 
1064  return SDValue();
1065  }
1066 
1067  return SDValue();
1068 }
1069 
1072  const MipsSubtarget &Subtarget) {
1073  // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1074  if (DCI.isBeforeLegalizeOps()) {
1075  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1076  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1077  return performMADD_MSUBCombine(N, DAG, Subtarget);
1078 
1079  return SDValue();
1080  }
1081 
1082  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1083  SDValue Add = N->getOperand(1);
1084 
1085  if (Add.getOpcode() != ISD::ADD)
1086  return SDValue();
1087 
1088  SDValue Lo = Add.getOperand(1);
1089 
1090  if ((Lo.getOpcode() != MipsISD::Lo) ||
1091  (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1092  return SDValue();
1093 
1094  EVT ValTy = N->getValueType(0);
1095  SDLoc DL(N);
1096 
1097  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1098  Add.getOperand(0));
1099  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1100 }
1101 
1104  const MipsSubtarget &Subtarget) {
1105  // Pattern match CINS.
1106  // $dst = shl (and $src , imm), pos
1107  // => cins $dst, $src, pos, size
1108 
1109  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1110  return SDValue();
1111 
1112  SDValue FirstOperand = N->getOperand(0);
1113  unsigned FirstOperandOpc = FirstOperand.getOpcode();
1114  SDValue SecondOperand = N->getOperand(1);
1115  EVT ValTy = N->getValueType(0);
1116  SDLoc DL(N);
1117 
1118  uint64_t Pos = 0, SMPos, SMSize;
1119  ConstantSDNode *CN;
1120  SDValue NewOperand;
1121 
1122  // The second operand of the shift must be an immediate.
1123  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1124  return SDValue();
1125 
1126  Pos = CN->getZExtValue();
1127 
1128  if (Pos >= ValTy.getSizeInBits())
1129  return SDValue();
1130 
1131  if (FirstOperandOpc != ISD::AND)
1132  return SDValue();
1133 
1134  // AND's second operand must be a shifted mask.
1135  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1136  !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1137  return SDValue();
1138 
1139  // Return if the shifted mask does not start at bit 0 or the sum of its size
1140  // and Pos exceeds the word's size.
1141  if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1142  return SDValue();
1143 
1144  NewOperand = FirstOperand.getOperand(0);
1145  // SMSize is 'location' (position) in this case, not size.
1146  SMSize--;
1147 
1148  return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1149  DAG.getConstant(Pos, DL, MVT::i32),
1150  DAG.getConstant(SMSize, DL, MVT::i32));
1151 }
1152 
1154  const {
1155  SelectionDAG &DAG = DCI.DAG;
1156  unsigned Opc = N->getOpcode();
1157 
1158  switch (Opc) {
1159  default: break;
1160  case ISD::SDIVREM:
1161  case ISD::UDIVREM:
1162  return performDivRemCombine(N, DAG, DCI, Subtarget);
1163  case ISD::SELECT:
1164  return performSELECTCombine(N, DAG, DCI, Subtarget);
1165  case MipsISD::CMovFP_F:
1166  case MipsISD::CMovFP_T:
1167  return performCMovFPCombine(N, DAG, DCI, Subtarget);
1168  case ISD::AND:
1169  return performANDCombine(N, DAG, DCI, Subtarget);
1170  case ISD::OR:
1171  return performORCombine(N, DAG, DCI, Subtarget);
1172  case ISD::ADD:
1173  return performADDCombine(N, DAG, DCI, Subtarget);
1174  case ISD::SHL:
1175  return performSHLCombine(N, DAG, DCI, Subtarget);
1176  case ISD::SUB:
1177  return performSUBCombine(N, DAG, DCI, Subtarget);
1178  }
1179 
1180  return SDValue();
1181 }
1182 
1184  return Subtarget.hasMips32();
1185 }
1186 
1188  return Subtarget.hasMips32();
1189 }
1190 
1192  const SDNode *N, CombineLevel Level) const {
1193  if (N->getOperand(0).getValueType().isVector())
1194  return false;
1195  return true;
1196 }
1197 
1198 void
1201  SelectionDAG &DAG) const {
1202  return LowerOperationWrapper(N, Results, DAG);
1203 }
1204 
1207 {
1208  switch (Op.getOpcode())
1209  {
1210  case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1211  case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1212  case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1213  case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1214  case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1215  case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1216  case ISD::SELECT: return lowerSELECT(Op, DAG);
1217  case ISD::SETCC: return lowerSETCC(Op, DAG);
1218  case ISD::VASTART: return lowerVASTART(Op, DAG);
1219  case ISD::VAARG: return lowerVAARG(Op, DAG);
1220  case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1221  case ISD::FABS: return lowerFABS(Op, DAG);
1222  case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1223  case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1224  case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1225  case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1226  case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1227  case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1228  case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1229  case ISD::LOAD: return lowerLOAD(Op, DAG);
1230  case ISD::STORE: return lowerSTORE(Op, DAG);
1231  case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1232  case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1233  }
1234  return SDValue();
1235 }
1236 
1237 //===----------------------------------------------------------------------===//
1238 // Lower helper functions
1239 //===----------------------------------------------------------------------===//
1240 
1241 // addLiveIn - This helper function adds the specified physical register to the
1242 // MachineFunction as a live in value. It also creates a corresponding
1243 // virtual register for it.
1244 static unsigned
1245 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1246 {
1247  Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1248  MF.getRegInfo().addLiveIn(PReg, VReg);
1249  return VReg;
1250 }
1251 
1254  const TargetInstrInfo &TII,
1255  bool Is64Bit, bool IsMicroMips) {
1256  if (NoZeroDivCheck)
1257  return &MBB;
1258 
1259  // Insert instruction "teq $divisor_reg, $zero, 7".
1261  MachineInstrBuilder MIB;
1262  MachineOperand &Divisor = MI.getOperand(2);
1263  MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1264  TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1265  .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1266  .addReg(Mips::ZERO)
1267  .addImm(7);
1268 
1269  // Use the 32-bit sub-register if this is a 64-bit division.
1270  if (Is64Bit)
1271  MIB->getOperand(0).setSubReg(Mips::sub_32);
1272 
1273  // Clear Divisor's kill flag.
1274  Divisor.setIsKill(false);
1275 
1276  // We would normally delete the original instruction here but in this case
1277  // we only needed to inject an additional instruction rather than replace it.
1278 
1279  return &MBB;
1280 }
1281 
1284  MachineBasicBlock *BB) const {
1285  switch (MI.getOpcode()) {
1286  default:
1287  llvm_unreachable("Unexpected instr type to insert");
1288  case Mips::ATOMIC_LOAD_ADD_I8:
1289  return emitAtomicBinaryPartword(MI, BB, 1);
1290  case Mips::ATOMIC_LOAD_ADD_I16:
1291  return emitAtomicBinaryPartword(MI, BB, 2);
1292  case Mips::ATOMIC_LOAD_ADD_I32:
1293  return emitAtomicBinary(MI, BB);
1294  case Mips::ATOMIC_LOAD_ADD_I64:
1295  return emitAtomicBinary(MI, BB);
1296 
1297  case Mips::ATOMIC_LOAD_AND_I8:
1298  return emitAtomicBinaryPartword(MI, BB, 1);
1299  case Mips::ATOMIC_LOAD_AND_I16:
1300  return emitAtomicBinaryPartword(MI, BB, 2);
1301  case Mips::ATOMIC_LOAD_AND_I32:
1302  return emitAtomicBinary(MI, BB);
1303  case Mips::ATOMIC_LOAD_AND_I64:
1304  return emitAtomicBinary(MI, BB);
1305 
1306  case Mips::ATOMIC_LOAD_OR_I8:
1307  return emitAtomicBinaryPartword(MI, BB, 1);
1308  case Mips::ATOMIC_LOAD_OR_I16:
1309  return emitAtomicBinaryPartword(MI, BB, 2);
1310  case Mips::ATOMIC_LOAD_OR_I32:
1311  return emitAtomicBinary(MI, BB);
1312  case Mips::ATOMIC_LOAD_OR_I64:
1313  return emitAtomicBinary(MI, BB);
1314 
1315  case Mips::ATOMIC_LOAD_XOR_I8:
1316  return emitAtomicBinaryPartword(MI, BB, 1);
1317  case Mips::ATOMIC_LOAD_XOR_I16:
1318  return emitAtomicBinaryPartword(MI, BB, 2);
1319  case Mips::ATOMIC_LOAD_XOR_I32:
1320  return emitAtomicBinary(MI, BB);
1321  case Mips::ATOMIC_LOAD_XOR_I64:
1322  return emitAtomicBinary(MI, BB);
1323 
1324  case Mips::ATOMIC_LOAD_NAND_I8:
1325  return emitAtomicBinaryPartword(MI, BB, 1);
1326  case Mips::ATOMIC_LOAD_NAND_I16:
1327  return emitAtomicBinaryPartword(MI, BB, 2);
1328  case Mips::ATOMIC_LOAD_NAND_I32:
1329  return emitAtomicBinary(MI, BB);
1330  case Mips::ATOMIC_LOAD_NAND_I64:
1331  return emitAtomicBinary(MI, BB);
1332 
1333  case Mips::ATOMIC_LOAD_SUB_I8:
1334  return emitAtomicBinaryPartword(MI, BB, 1);
1335  case Mips::ATOMIC_LOAD_SUB_I16:
1336  return emitAtomicBinaryPartword(MI, BB, 2);
1337  case Mips::ATOMIC_LOAD_SUB_I32:
1338  return emitAtomicBinary(MI, BB);
1339  case Mips::ATOMIC_LOAD_SUB_I64:
1340  return emitAtomicBinary(MI, BB);
1341 
1342  case Mips::ATOMIC_SWAP_I8:
1343  return emitAtomicBinaryPartword(MI, BB, 1);
1344  case Mips::ATOMIC_SWAP_I16:
1345  return emitAtomicBinaryPartword(MI, BB, 2);
1346  case Mips::ATOMIC_SWAP_I32:
1347  return emitAtomicBinary(MI, BB);
1348  case Mips::ATOMIC_SWAP_I64:
1349  return emitAtomicBinary(MI, BB);
1350 
1351  case Mips::ATOMIC_CMP_SWAP_I8:
1352  return emitAtomicCmpSwapPartword(MI, BB, 1);
1353  case Mips::ATOMIC_CMP_SWAP_I16:
1354  return emitAtomicCmpSwapPartword(MI, BB, 2);
1355  case Mips::ATOMIC_CMP_SWAP_I32:
1356  return emitAtomicCmpSwap(MI, BB);
1357  case Mips::ATOMIC_CMP_SWAP_I64:
1358  return emitAtomicCmpSwap(MI, BB);
1359 
1360  case Mips::ATOMIC_LOAD_MIN_I8:
1361  return emitAtomicBinaryPartword(MI, BB, 1);
1362  case Mips::ATOMIC_LOAD_MIN_I16:
1363  return emitAtomicBinaryPartword(MI, BB, 2);
1364  case Mips::ATOMIC_LOAD_MIN_I32:
1365  return emitAtomicBinary(MI, BB);
1366  case Mips::ATOMIC_LOAD_MIN_I64:
1367  return emitAtomicBinary(MI, BB);
1368 
1369  case Mips::ATOMIC_LOAD_MAX_I8:
1370  return emitAtomicBinaryPartword(MI, BB, 1);
1371  case Mips::ATOMIC_LOAD_MAX_I16:
1372  return emitAtomicBinaryPartword(MI, BB, 2);
1373  case Mips::ATOMIC_LOAD_MAX_I32:
1374  return emitAtomicBinary(MI, BB);
1375  case Mips::ATOMIC_LOAD_MAX_I64:
1376  return emitAtomicBinary(MI, BB);
1377 
1378  case Mips::ATOMIC_LOAD_UMIN_I8:
1379  return emitAtomicBinaryPartword(MI, BB, 1);
1380  case Mips::ATOMIC_LOAD_UMIN_I16:
1381  return emitAtomicBinaryPartword(MI, BB, 2);
1382  case Mips::ATOMIC_LOAD_UMIN_I32:
1383  return emitAtomicBinary(MI, BB);
1384  case Mips::ATOMIC_LOAD_UMIN_I64:
1385  return emitAtomicBinary(MI, BB);
1386 
1387  case Mips::ATOMIC_LOAD_UMAX_I8:
1388  return emitAtomicBinaryPartword(MI, BB, 1);
1389  case Mips::ATOMIC_LOAD_UMAX_I16:
1390  return emitAtomicBinaryPartword(MI, BB, 2);
1391  case Mips::ATOMIC_LOAD_UMAX_I32:
1392  return emitAtomicBinary(MI, BB);
1393  case Mips::ATOMIC_LOAD_UMAX_I64:
1394  return emitAtomicBinary(MI, BB);
1395 
1396  case Mips::PseudoSDIV:
1397  case Mips::PseudoUDIV:
1398  case Mips::DIV:
1399  case Mips::DIVU:
1400  case Mips::MOD:
1401  case Mips::MODU:
1402  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1403  false);
1404  case Mips::SDIV_MM_Pseudo:
1405  case Mips::UDIV_MM_Pseudo:
1406  case Mips::SDIV_MM:
1407  case Mips::UDIV_MM:
1408  case Mips::DIV_MMR6:
1409  case Mips::DIVU_MMR6:
1410  case Mips::MOD_MMR6:
1411  case Mips::MODU_MMR6:
1412  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1413  case Mips::PseudoDSDIV:
1414  case Mips::PseudoDUDIV:
1415  case Mips::DDIV:
1416  case Mips::DDIVU:
1417  case Mips::DMOD:
1418  case Mips::DMODU:
1419  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1420 
1421  case Mips::PseudoSELECT_I:
1422  case Mips::PseudoSELECT_I64:
1423  case Mips::PseudoSELECT_S:
1424  case Mips::PseudoSELECT_D32:
1425  case Mips::PseudoSELECT_D64:
1426  return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1427  case Mips::PseudoSELECTFP_F_I:
1428  case Mips::PseudoSELECTFP_F_I64:
1429  case Mips::PseudoSELECTFP_F_S:
1430  case Mips::PseudoSELECTFP_F_D32:
1431  case Mips::PseudoSELECTFP_F_D64:
1432  return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1433  case Mips::PseudoSELECTFP_T_I:
1434  case Mips::PseudoSELECTFP_T_I64:
1435  case Mips::PseudoSELECTFP_T_S:
1436  case Mips::PseudoSELECTFP_T_D32:
1437  case Mips::PseudoSELECTFP_T_D64:
1438  return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1439  case Mips::PseudoD_SELECT_I:
1440  case Mips::PseudoD_SELECT_I64:
1441  return emitPseudoD_SELECT(MI, BB);
1442  case Mips::LDR_W:
1443  return emitLDR_W(MI, BB);
1444  case Mips::LDR_D:
1445  return emitLDR_D(MI, BB);
1446  case Mips::STR_W:
1447  return emitSTR_W(MI, BB);
1448  case Mips::STR_D:
1449  return emitSTR_D(MI, BB);
1450  }
1451 }
1452 
1453 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1454 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1456 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1457  MachineBasicBlock *BB) const {
1458 
1459  MachineFunction *MF = BB->getParent();
1460  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1462  DebugLoc DL = MI.getDebugLoc();
1463 
1464  unsigned AtomicOp;
1465  bool NeedsAdditionalReg = false;
1466  switch (MI.getOpcode()) {
1467  case Mips::ATOMIC_LOAD_ADD_I32:
1468  AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1469  break;
1470  case Mips::ATOMIC_LOAD_SUB_I32:
1471  AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1472  break;
1473  case Mips::ATOMIC_LOAD_AND_I32:
1474  AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1475  break;
1476  case Mips::ATOMIC_LOAD_OR_I32:
1477  AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1478  break;
1479  case Mips::ATOMIC_LOAD_XOR_I32:
1480  AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1481  break;
1482  case Mips::ATOMIC_LOAD_NAND_I32:
1483  AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1484  break;
1485  case Mips::ATOMIC_SWAP_I32:
1486  AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1487  break;
1488  case Mips::ATOMIC_LOAD_ADD_I64:
1489  AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1490  break;
1491  case Mips::ATOMIC_LOAD_SUB_I64:
1492  AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1493  break;
1494  case Mips::ATOMIC_LOAD_AND_I64:
1495  AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1496  break;
1497  case Mips::ATOMIC_LOAD_OR_I64:
1498  AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1499  break;
1500  case Mips::ATOMIC_LOAD_XOR_I64:
1501  AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1502  break;
1503  case Mips::ATOMIC_LOAD_NAND_I64:
1504  AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1505  break;
1506  case Mips::ATOMIC_SWAP_I64:
1507  AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1508  break;
1509  case Mips::ATOMIC_LOAD_MIN_I32:
1510  AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1511  NeedsAdditionalReg = true;
1512  break;
1513  case Mips::ATOMIC_LOAD_MAX_I32:
1514  AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1515  NeedsAdditionalReg = true;
1516  break;
1517  case Mips::ATOMIC_LOAD_UMIN_I32:
1518  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1519  NeedsAdditionalReg = true;
1520  break;
1521  case Mips::ATOMIC_LOAD_UMAX_I32:
1522  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1523  NeedsAdditionalReg = true;
1524  break;
1525  case Mips::ATOMIC_LOAD_MIN_I64:
1526  AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1527  NeedsAdditionalReg = true;
1528  break;
1529  case Mips::ATOMIC_LOAD_MAX_I64:
1530  AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1531  NeedsAdditionalReg = true;
1532  break;
1533  case Mips::ATOMIC_LOAD_UMIN_I64:
1534  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1535  NeedsAdditionalReg = true;
1536  break;
1537  case Mips::ATOMIC_LOAD_UMAX_I64:
1538  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1539  NeedsAdditionalReg = true;
1540  break;
1541  default:
1542  llvm_unreachable("Unknown pseudo atomic for replacement!");
1543  }
1544 
1545  Register OldVal = MI.getOperand(0).getReg();
1546  Register Ptr = MI.getOperand(1).getReg();
1547  Register Incr = MI.getOperand(2).getReg();
1548  Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1549 
1551 
1552  // The scratch registers here with the EarlyClobber | Define | Implicit
1553  // flags is used to persuade the register allocator and the machine
1554  // verifier to accept the usage of this register. This has to be a real
1555  // register which has an UNDEF value but is dead after the instruction which
1556  // is unique among the registers chosen for the instruction.
1557 
1558  // The EarlyClobber flag has the semantic properties that the operand it is
1559  // attached to is clobbered before the rest of the inputs are read. Hence it
1560  // must be unique among the operands to the instruction.
1561  // The Define flag is needed to coerce the machine verifier that an Undef
1562  // value isn't a problem.
1563  // The Dead flag is needed as the value in scratch isn't used by any other
1564  // instruction. Kill isn't used as Dead is more precise.
1565  // The implicit flag is here due to the interaction between the other flags
1566  // and the machine verifier.
1567 
1568  // For correctness purpose, a new pseudo is introduced here. We need this
1569  // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1570  // that is spread over >1 basic blocks. A register allocator which
1571  // introduces (or any codegen infact) a store, can violate the expectations
1572  // of the hardware.
1573  //
1574  // An atomic read-modify-write sequence starts with a linked load
1575  // instruction and ends with a store conditional instruction. The atomic
1576  // read-modify-write sequence fails if any of the following conditions
1577  // occur between the execution of ll and sc:
1578  // * A coherent store is completed by another process or coherent I/O
1579  // module into the block of synchronizable physical memory containing
1580  // the word. The size and alignment of the block is
1581  // implementation-dependent.
1582  // * A coherent store is executed between an LL and SC sequence on the
1583  // same processor to the block of synchornizable physical memory
1584  // containing the word.
1585  //
1586 
1587  Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1588  Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1589 
1590  BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1591  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1592 
1593  MachineInstrBuilder MIB =
1594  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1596  .addReg(PtrCopy)
1597  .addReg(IncrCopy)
1600  if (NeedsAdditionalReg) {
1601  Register Scratch2 =
1602  RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1605  }
1606 
1607  MI.eraseFromParent();
1608 
1609  return BB;
1610 }
1611 
1612 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1613  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1614  unsigned SrcReg) const {
1616  const DebugLoc &DL = MI.getDebugLoc();
1617 
1618  if (Subtarget.hasMips32r2() && Size == 1) {
1619  BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1620  return BB;
1621  }
1622 
1623  if (Subtarget.hasMips32r2() && Size == 2) {
1624  BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1625  return BB;
1626  }
1627 
1628  MachineFunction *MF = BB->getParent();
1629  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1631  Register ScrReg = RegInfo.createVirtualRegister(RC);
1632 
1633  assert(Size < 32);
1634  int64_t ShiftImm = 32 - (Size * 8);
1635 
1636  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1637  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1638 
1639  return BB;
1640 }
1641 
1642 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1643  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1644  assert((Size == 1 || Size == 2) &&
1645  "Unsupported size for EmitAtomicBinaryPartial.");
1646 
1647  MachineFunction *MF = BB->getParent();
1648  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1650  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1651  const TargetRegisterClass *RCp =
1652  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1654  DebugLoc DL = MI.getDebugLoc();
1655 
1656  Register Dest = MI.getOperand(0).getReg();
1657  Register Ptr = MI.getOperand(1).getReg();
1658  Register Incr = MI.getOperand(2).getReg();
1659 
1660  Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1661  Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1662  Register Mask = RegInfo.createVirtualRegister(RC);
1663  Register Mask2 = RegInfo.createVirtualRegister(RC);
1664  Register Incr2 = RegInfo.createVirtualRegister(RC);
1665  Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1666  Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1667  Register MaskUpper = RegInfo.createVirtualRegister(RC);
1668  Register Scratch = RegInfo.createVirtualRegister(RC);
1669  Register Scratch2 = RegInfo.createVirtualRegister(RC);
1670  Register Scratch3 = RegInfo.createVirtualRegister(RC);
1671 
1672  unsigned AtomicOp = 0;
1673  bool NeedsAdditionalReg = false;
1674  switch (MI.getOpcode()) {
1675  case Mips::ATOMIC_LOAD_NAND_I8:
1676  AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1677  break;
1678  case Mips::ATOMIC_LOAD_NAND_I16:
1679  AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1680  break;
1681  case Mips::ATOMIC_SWAP_I8:
1682  AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1683  break;
1684  case Mips::ATOMIC_SWAP_I16:
1685  AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1686  break;
1687  case Mips::ATOMIC_LOAD_ADD_I8:
1688  AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1689  break;
1690  case Mips::ATOMIC_LOAD_ADD_I16:
1691  AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1692  break;
1693  case Mips::ATOMIC_LOAD_SUB_I8:
1694  AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1695  break;
1696  case Mips::ATOMIC_LOAD_SUB_I16:
1697  AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1698  break;
1699  case Mips::ATOMIC_LOAD_AND_I8:
1700  AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1701  break;
1702  case Mips::ATOMIC_LOAD_AND_I16:
1703  AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1704  break;
1705  case Mips::ATOMIC_LOAD_OR_I8:
1706  AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1707  break;
1708  case Mips::ATOMIC_LOAD_OR_I16:
1709  AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1710  break;
1711  case Mips::ATOMIC_LOAD_XOR_I8:
1712  AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1713  break;
1714  case Mips::ATOMIC_LOAD_XOR_I16:
1715  AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1716  break;
1717  case Mips::ATOMIC_LOAD_MIN_I8:
1718  AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1719  NeedsAdditionalReg = true;
1720  break;
1721  case Mips::ATOMIC_LOAD_MIN_I16:
1722  AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1723  NeedsAdditionalReg = true;
1724  break;
1725  case Mips::ATOMIC_LOAD_MAX_I8:
1726  AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1727  NeedsAdditionalReg = true;
1728  break;
1729  case Mips::ATOMIC_LOAD_MAX_I16:
1730  AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1731  NeedsAdditionalReg = true;
1732  break;
1733  case Mips::ATOMIC_LOAD_UMIN_I8:
1734  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1735  NeedsAdditionalReg = true;
1736  break;
1737  case Mips::ATOMIC_LOAD_UMIN_I16:
1738  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1739  NeedsAdditionalReg = true;
1740  break;
1741  case Mips::ATOMIC_LOAD_UMAX_I8:
1742  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1743  NeedsAdditionalReg = true;
1744  break;
1745  case Mips::ATOMIC_LOAD_UMAX_I16:
1746  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1747  NeedsAdditionalReg = true;
1748  break;
1749  default:
1750  llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1751  }
1752 
1753  // insert new blocks after the current block
1754  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1755  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1756  MachineFunction::iterator It = ++BB->getIterator();
1757  MF->insert(It, exitMBB);
1758 
1759  // Transfer the remainder of BB and its successor edges to exitMBB.
1760  exitMBB->splice(exitMBB->begin(), BB,
1761  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1763 
1764  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1765 
1766  // thisMBB:
1767  // addiu masklsb2,$0,-4 # 0xfffffffc
1768  // and alignedaddr,ptr,masklsb2
1769  // andi ptrlsb2,ptr,3
1770  // sll shiftamt,ptrlsb2,3
1771  // ori maskupper,$0,255 # 0xff
1772  // sll mask,maskupper,shiftamt
1773  // nor mask2,$0,mask
1774  // sll incr2,incr,shiftamt
1775 
1776  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1777  BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1778  .addReg(ABI.GetNullPtr()).addImm(-4);
1779  BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1780  .addReg(Ptr).addReg(MaskLSB2);
1781  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1782  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1783  if (Subtarget.isLittle()) {
1784  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1785  } else {
1786  Register Off = RegInfo.createVirtualRegister(RC);
1787  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1788  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1789  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1790  }
1791  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1792  .addReg(Mips::ZERO).addImm(MaskImm);
1793  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1794  .addReg(MaskUpper).addReg(ShiftAmt);
1795  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1796  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1797 
1798 
1799  // The purposes of the flags on the scratch registers is explained in
1800  // emitAtomicBinary. In summary, we need a scratch register which is going to
1801  // be undef, that is unique among registers chosen for the instruction.
1802 
1803  MachineInstrBuilder MIB =
1804  BuildMI(BB, DL, TII->get(AtomicOp))
1806  .addReg(AlignedAddr)
1807  .addReg(Incr2)
1808  .addReg(Mask)
1809  .addReg(Mask2)
1810  .addReg(ShiftAmt)
1817  if (NeedsAdditionalReg) {
1818  Register Scratch4 = RegInfo.createVirtualRegister(RC);
1821  }
1822 
1823  MI.eraseFromParent(); // The instruction is gone now.
1824 
1825  return exitMBB;
1826 }
1827 
1828 // Lower atomic compare and swap to a pseudo instruction, taking care to
1829 // define a scratch register for the pseudo instruction's expansion. The
1830 // instruction is expanded after the register allocator as to prevent
1831 // the insertion of stores between the linked load and the store conditional.
1832 
1834 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1835  MachineBasicBlock *BB) const {
1836 
1837  assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1838  MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1839  "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1840 
1841  const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1842 
1843  MachineFunction *MF = BB->getParent();
1847  DebugLoc DL = MI.getDebugLoc();
1848 
1849  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1850  ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1851  : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1852  Register Dest = MI.getOperand(0).getReg();
1853  Register Ptr = MI.getOperand(1).getReg();
1854  Register OldVal = MI.getOperand(2).getReg();
1855  Register NewVal = MI.getOperand(3).getReg();
1856 
1857  Register Scratch = MRI.createVirtualRegister(RC);
1859 
1860  // We need to create copies of the various registers and kill them at the
1861  // atomic pseudo. If the copies are not made, when the atomic is expanded
1862  // after fast register allocation, the spills will end up outside of the
1863  // blocks that their values are defined in, causing livein errors.
1864 
1866  Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1867  Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1868 
1869  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1870  BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1871  BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1872 
1873  // The purposes of the flags on the scratch registers is explained in
1874  // emitAtomicBinary. In summary, we need a scratch register which is going to
1875  // be undef, that is unique among registers chosen for the instruction.
1876 
1877  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1879  .addReg(PtrCopy, RegState::Kill)
1880  .addReg(OldValCopy, RegState::Kill)
1881  .addReg(NewValCopy, RegState::Kill)
1884 
1885  MI.eraseFromParent(); // The instruction is gone now.
1886 
1887  return BB;
1888 }
1889 
1890 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1891  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1892  assert((Size == 1 || Size == 2) &&
1893  "Unsupported size for EmitAtomicCmpSwapPartial.");
1894 
1895  MachineFunction *MF = BB->getParent();
1896  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1898  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1899  const TargetRegisterClass *RCp =
1900  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1902  DebugLoc DL = MI.getDebugLoc();
1903 
1904  Register Dest = MI.getOperand(0).getReg();
1905  Register Ptr = MI.getOperand(1).getReg();
1906  Register CmpVal = MI.getOperand(2).getReg();
1907  Register NewVal = MI.getOperand(3).getReg();
1908 
1909  Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1910  Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1911  Register Mask = RegInfo.createVirtualRegister(RC);
1912  Register Mask2 = RegInfo.createVirtualRegister(RC);
1913  Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1914  Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1915  Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1916  Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1917  Register MaskUpper = RegInfo.createVirtualRegister(RC);
1918  Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1919  Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1920  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1921  ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1922  : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1923 
1924  // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1925  // flags are used to coerce the register allocator and the machine verifier to
1926  // accept the usage of these registers.
1927  // The EarlyClobber flag has the semantic properties that the operand it is
1928  // attached to is clobbered before the rest of the inputs are read. Hence it
1929  // must be unique among the operands to the instruction.
1930  // The Define flag is needed to coerce the machine verifier that an Undef
1931  // value isn't a problem.
1932  // The Dead flag is needed as the value in scratch isn't used by any other
1933  // instruction. Kill isn't used as Dead is more precise.
1934  Register Scratch = RegInfo.createVirtualRegister(RC);
1935  Register Scratch2 = RegInfo.createVirtualRegister(RC);
1936 
1937  // insert new blocks after the current block
1938  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1939  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1940  MachineFunction::iterator It = ++BB->getIterator();
1941  MF->insert(It, exitMBB);
1942 
1943  // Transfer the remainder of BB and its successor edges to exitMBB.
1944  exitMBB->splice(exitMBB->begin(), BB,
1945  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1947 
1948  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1949 
1950  // thisMBB:
1951  // addiu masklsb2,$0,-4 # 0xfffffffc
1952  // and alignedaddr,ptr,masklsb2
1953  // andi ptrlsb2,ptr,3
1954  // xori ptrlsb2,ptrlsb2,3 # Only for BE
1955  // sll shiftamt,ptrlsb2,3
1956  // ori maskupper,$0,255 # 0xff
1957  // sll mask,maskupper,shiftamt
1958  // nor mask2,$0,mask
1959  // andi maskedcmpval,cmpval,255
1960  // sll shiftedcmpval,maskedcmpval,shiftamt
1961  // andi maskednewval,newval,255
1962  // sll shiftednewval,maskednewval,shiftamt
1963  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1964  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1965  .addReg(ABI.GetNullPtr()).addImm(-4);
1966  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1967  .addReg(Ptr).addReg(MaskLSB2);
1968  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1969  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1970  if (Subtarget.isLittle()) {
1971  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1972  } else {
1973  Register Off = RegInfo.createVirtualRegister(RC);
1974  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1975  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1976  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1977  }
1978  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1979  .addReg(Mips::ZERO).addImm(MaskImm);
1980  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1981  .addReg(MaskUpper).addReg(ShiftAmt);
1982  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1983  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1984  .addReg(CmpVal).addImm(MaskImm);
1985  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1986  .addReg(MaskedCmpVal).addReg(ShiftAmt);
1987  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1988  .addReg(NewVal).addImm(MaskImm);
1989  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1990  .addReg(MaskedNewVal).addReg(ShiftAmt);
1991 
1992  // The purposes of the flags on the scratch registers are explained in
1993  // emitAtomicBinary. In summary, we need a scratch register which is going to
1994  // be undef, that is unique among the register chosen for the instruction.
1995 
1996  BuildMI(BB, DL, TII->get(AtomicOp))
1998  .addReg(AlignedAddr)
1999  .addReg(Mask)
2000  .addReg(ShiftedCmpVal)
2001  .addReg(Mask2)
2002  .addReg(ShiftedNewVal)
2003  .addReg(ShiftAmt)
2008 
2009  MI.eraseFromParent(); // The instruction is gone now.
2010 
2011  return exitMBB;
2012 }
2013 
2014 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2015  // The first operand is the chain, the second is the condition, the third is
2016  // the block to branch to if the condition is true.
2017  SDValue Chain = Op.getOperand(0);
2018  SDValue Dest = Op.getOperand(2);
2019  SDLoc DL(Op);
2020 
2022  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
2023 
2024  // Return if flag is not set by a floating point comparison.
2025  if (CondRes.getOpcode() != MipsISD::FPCmp)
2026  return Op;
2027 
2028  SDValue CCNode = CondRes.getOperand(2);
2029  Mips::CondCode CC =
2030  (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2031  unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
2032  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
2033  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2034  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
2035  FCC0, Dest, CondRes);
2036 }
2037 
2038 SDValue MipsTargetLowering::
2039 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
2040 {
2042  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
2043 
2044  // Return if flag is not set by a floating point comparison.
2045  if (Cond.getOpcode() != MipsISD::FPCmp)
2046  return Op;
2047 
2048  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2049  SDLoc(Op));
2050 }
2051 
2052 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2054  SDValue Cond = createFPCmp(DAG, Op);
2055 
2056  assert(Cond.getOpcode() == MipsISD::FPCmp &&
2057  "Floating point operand expected.");
2058 
2059  SDLoc DL(Op);
2060  SDValue True = DAG.getConstant(1, DL, MVT::i32);
2061  SDValue False = DAG.getConstant(0, DL, MVT::i32);
2062 
2063  return createCMovFP(DAG, Cond, True, False, DL);
2064 }
2065 
2066 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2067  SelectionDAG &DAG) const {
2068  EVT Ty = Op.getValueType();
2069  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2070  const GlobalValue *GV = N->getGlobal();
2071 
2072  if (!isPositionIndependent()) {
2073  const MipsTargetObjectFile *TLOF =
2074  static_cast<const MipsTargetObjectFile *>(
2076  const GlobalObject *GO = GV->getBaseObject();
2077  if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2078  // %gp_rel relocation
2079  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2080 
2081  // %hi/%lo relocation
2082  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2083  // %highest/%higher/%hi/%lo relocation
2084  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2085  }
2086 
2087  // Every other architecture would use shouldAssumeDSOLocal in here, but
2088  // mips is special.
2089  // * In PIC code mips requires got loads even for local statics!
2090  // * To save on got entries, for local statics the got entry contains the
2091  // page and an additional add instruction takes care of the low bits.
2092  // * It is legal to access a hidden symbol with a non hidden undefined,
2093  // so one cannot guarantee that all access to a hidden symbol will know
2094  // it is hidden.
2095  // * Mips linkers don't support creating a page and a full got entry for
2096  // the same symbol.
2097  // * Given all that, we have to use a full got entry for hidden symbols :-(
2098  if (GV->hasLocalLinkage())
2099  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2100 
2101  if (Subtarget.useXGOT())
2102  return getAddrGlobalLargeGOT(
2104  DAG.getEntryNode(),
2105  MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2106 
2107  return getAddrGlobal(
2108  N, SDLoc(N), Ty, DAG,
2110  DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2111 }
2112 
2113 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2114  SelectionDAG &DAG) const {
2115  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2116  EVT Ty = Op.getValueType();
2117 
2118  if (!isPositionIndependent())
2119  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2120  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2121 
2122  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2123 }
2124 
2125 SDValue MipsTargetLowering::
2126 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2127 {
2128  // If the relocation model is PIC, use the General Dynamic TLS Model or
2129  // Local Dynamic TLS model, otherwise use the Initial Exec or
2130  // Local Exec TLS Model.
2131 
2132  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2133  if (DAG.getTarget().useEmulatedTLS())
2134  return LowerToTLSEmulatedModel(GA, DAG);
2135 
2136  SDLoc DL(GA);
2137  const GlobalValue *GV = GA->getGlobal();
2138  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2139 
2141 
2143  // General Dynamic and Local Dynamic TLS Model.
2145  : MipsII::MO_TLSGD;
2146 
2147  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2148  SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2149  getGlobalReg(DAG, PtrVT), TGA);
2150  unsigned PtrSize = PtrVT.getSizeInBits();
2151  IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2152 
2153  SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2154 
2155  ArgListTy Args;
2156  ArgListEntry Entry;
2157  Entry.Node = Argument;
2158  Entry.Ty = PtrTy;
2159  Args.push_back(Entry);
2160 
2162  CLI.setDebugLoc(DL)
2163  .setChain(DAG.getEntryNode())
2164  .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2165  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2166 
2167  SDValue Ret = CallResult.first;
2168 
2170  return Ret;
2171 
2172  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2174  SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2175  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2177  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2178  SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2179  return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2180  }
2181 
2182  SDValue Offset;
2183  if (model == TLSModel::InitialExec) {
2184  // Initial Exec TLS Model
2185  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2187  TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2188  TGA);
2189  Offset =
2190  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2191  } else {
2192  // Local Exec TLS Model
2194  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2196  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2198  SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2199  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2200  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2201  }
2202 
2204  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2205 }
2206 
2207 SDValue MipsTargetLowering::
2208 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2209 {
2210  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2211  EVT Ty = Op.getValueType();
2212 
2213  if (!isPositionIndependent())
2214  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2215  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2216 
2217  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2218 }
2219 
2220 SDValue MipsTargetLowering::
2221 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2222 {
2223  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2224  EVT Ty = Op.getValueType();
2225 
2226  if (!isPositionIndependent()) {
2227  const MipsTargetObjectFile *TLOF =
2228  static_cast<const MipsTargetObjectFile *>(
2230 
2231  if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2232  getTargetMachine()))
2233  // %gp_rel relocation
2234  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2235 
2236  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2237  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2238  }
2239 
2240  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2241 }
2242 
2243 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2244  MachineFunction &MF = DAG.getMachineFunction();
2245  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2246 
2247  SDLoc DL(Op);
2248  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2249  getPointerTy(MF.getDataLayout()));
2250 
2251  // vastart just stores the address of the VarArgsFrameIndex slot into the
2252  // memory location argument.
2253  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2254  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2255  MachinePointerInfo(SV));
2256 }
2257 
2258 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2259  SDNode *Node = Op.getNode();
2260  EVT VT = Node->getValueType(0);
2261  SDValue Chain = Node->getOperand(0);
2262  SDValue VAListPtr = Node->getOperand(1);
2263  const Align Align =
2264  llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
2265  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2266  SDLoc DL(Node);
2267  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2268 
2269  SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2270  VAListPtr, MachinePointerInfo(SV));
2271  SDValue VAList = VAListLoad;
2272 
2273  // Re-align the pointer if necessary.
2274  // It should only ever be necessary for 64-bit types on O32 since the minimum
2275  // argument alignment is the same as the maximum type alignment for N32/N64.
2276  //
2277  // FIXME: We currently align too often. The code generator doesn't notice
2278  // when the pointer is still aligned from the last va_arg (or pair of
2279  // va_args for the i64 on O32 case).
2281  VAList = DAG.getNode(
2282  ISD::ADD, DL, VAList.getValueType(), VAList,
2283  DAG.getConstant(Align.value() - 1, DL, VAList.getValueType()));
2284 
2285  VAList = DAG.getNode(
2286  ISD::AND, DL, VAList.getValueType(), VAList,
2287  DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType()));
2288  }
2289 
2290  // Increment the pointer, VAList, to the next vaarg.
2291  auto &TD = DAG.getDataLayout();
2292  unsigned ArgSizeInBytes =
2293  TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2294  SDValue Tmp3 =
2295  DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2296  DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2297  DL, VAList.getValueType()));
2298  // Store the incremented VAList to the legalized pointer
2299  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2300  MachinePointerInfo(SV));
2301 
2302  // In big-endian mode we must adjust the pointer when the load size is smaller
2303  // than the argument slot size. We must also reduce the known alignment to
2304  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2305  // the correct half of the slot, and reduce the alignment from 8 (slot
2306  // alignment) down to 4 (type alignment).
2307  if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2308  unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2309  VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2310  DAG.getIntPtrConstant(Adjustment, DL));
2311  }
2312  // Load the actual argument out of the pointer VAList
2313  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2314 }
2315 
2317  bool HasExtractInsert) {
2318  EVT TyX = Op.getOperand(0).getValueType();
2319  EVT TyY = Op.getOperand(1).getValueType();
2320  SDLoc DL(Op);
2321  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2322  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2323  SDValue Res;
2324 
2325  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2326  // to i32.
2327  SDValue X = (TyX == MVT::f32) ?
2328  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2329  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2330  Const1);
2331  SDValue Y = (TyY == MVT::f32) ?
2332  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2333  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2334  Const1);
2335 
2336  if (HasExtractInsert) {
2337  // ext E, Y, 31, 1 ; extract bit31 of Y
2338  // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2339  SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2340  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2341  } else {
2342  // sll SllX, X, 1
2343  // srl SrlX, SllX, 1
2344  // srl SrlY, Y, 31
2345  // sll SllY, SrlX, 31
2346  // or Or, SrlX, SllY
2347  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2348  SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2349  SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2350  SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2351  Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2352  }
2353 
2354  if (TyX == MVT::f32)
2355  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2356 
2358  Op.getOperand(0),
2359  DAG.getConstant(0, DL, MVT::i32));
2360  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2361 }
2362 
2364  bool HasExtractInsert) {
2365  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2366  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2367  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2368  SDLoc DL(Op);
2369  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2370 
2371  // Bitcast to integer nodes.
2372  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2373  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2374 
2375  if (HasExtractInsert) {
2376  // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2377  // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2378  SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2379  DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2380 
2381  if (WidthX > WidthY)
2382  E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2383  else if (WidthY > WidthX)
2384  E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2385 
2386  SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2387  DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2388  X);
2389  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2390  }
2391 
2392  // (d)sll SllX, X, 1
2393  // (d)srl SrlX, SllX, 1
2394  // (d)srl SrlY, Y, width(Y)-1
2395  // (d)sll SllY, SrlX, width(Y)-1
2396  // or Or, SrlX, SllY
2397  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2398  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2399  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2400  DAG.getConstant(WidthY - 1, DL, MVT::i32));
2401 
2402  if (WidthX > WidthY)
2403  SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2404  else if (WidthY > WidthX)
2405  SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2406 
2407  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2408  DAG.getConstant(WidthX - 1, DL, MVT::i32));
2409  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2410  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2411 }
2412 
2413 SDValue
2414 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2415  if (Subtarget.isGP64bit())
2417 
2419 }
2420 
2422  bool HasExtractInsert) {
2423  SDLoc DL(Op);
2424  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2425 
2426  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2427  // to i32.
2428  SDValue X = (Op.getValueType() == MVT::f32)
2429  ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2431  Op.getOperand(0), Const1);
2432 
2433  // Clear MSB.
2434  if (HasExtractInsert)
2435  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2436  DAG.getRegister(Mips::ZERO, MVT::i32),
2437  DAG.getConstant(31, DL, MVT::i32), Const1, X);
2438  else {
2439  // TODO: Provide DAG patterns which transform (and x, cst)
2440  // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2441  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2442  Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2443  }
2444 
2445  if (Op.getValueType() == MVT::f32)
2446  return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2447 
2448  // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2449  // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2450  // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2451  // place.
2452  SDValue LowX =
2453  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2454  DAG.getConstant(0, DL, MVT::i32));
2455  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2456 }
2457 
2459  bool HasExtractInsert) {
2460  SDLoc DL(Op);
2461  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2462 
2463  // Bitcast to integer node.
2464  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2465 
2466  // Clear MSB.
2467  if (HasExtractInsert)
2468  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2469  DAG.getRegister(Mips::ZERO_64, MVT::i64),
2470  DAG.getConstant(63, DL, MVT::i32), Const1, X);
2471  else {
2472  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2473  Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2474  }
2475 
2476  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2477 }
2478 
2479 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2480  if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2481  return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2482 
2483  return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2484 }
2485 
2486 SDValue MipsTargetLowering::
2487 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2488  // check the depth
2489  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2490  DAG.getContext()->emitError(
2491  "return address can be determined only for current frame");
2492  return SDValue();
2493  }
2494 
2496  MFI.setFrameAddressIsTaken(true);
2497  EVT VT = Op.getValueType();
2498  SDLoc DL(Op);
2499  SDValue FrameAddr = DAG.getCopyFromReg(
2500  DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2501  return FrameAddr;
2502 }
2503 
2504 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2505  SelectionDAG &DAG) const {
2507  return SDValue();
2508 
2509  // check the depth
2510  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2511  DAG.getContext()->emitError(
2512  "return address can be determined only for current frame");
2513  return SDValue();
2514  }
2515 
2516  MachineFunction &MF = DAG.getMachineFunction();
2517  MachineFrameInfo &MFI = MF.getFrameInfo();
2518  MVT VT = Op.getSimpleValueType();
2519  unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2520  MFI.setReturnAddressIsTaken(true);
2521 
2522  // Return RA, which contains the return address. Mark it an implicit live-in.
2523  unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2524  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2525 }
2526 
2527 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2528 // generated from __builtin_eh_return (offset, handler)
2529 // The effect of this is to adjust the stack pointer by "offset"
2530 // and then branch to "handler".
2531 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2532  const {
2533  MachineFunction &MF = DAG.getMachineFunction();
2534  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2535 
2536  MipsFI->setCallsEhReturn();
2537  SDValue Chain = Op.getOperand(0);
2538  SDValue Offset = Op.getOperand(1);
2539  SDValue Handler = Op.getOperand(2);
2540  SDLoc DL(Op);
2541  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2542 
2543  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2544  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2545  unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2546  unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2547  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2548  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2549  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2550  DAG.getRegister(OffsetReg, Ty),
2551  DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2552  Chain.getValue(1));
2553 }
2554 
2555 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2556  SelectionDAG &DAG) const {
2557  // FIXME: Need pseudo-fence for 'singlethread' fences
2558  // FIXME: Set SType for weaker fences where supported/appropriate.
2559  unsigned SType = 0;
2560  SDLoc DL(Op);
2561  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2562  DAG.getConstant(SType, DL, MVT::i32));
2563 }
2564 
2565 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2566  SelectionDAG &DAG) const {
2567  SDLoc DL(Op);
2569 
2570  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2571  SDValue Shamt = Op.getOperand(2);
2572  // if shamt < (VT.bits):
2573  // lo = (shl lo, shamt)
2574  // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2575  // else:
2576  // lo = 0
2577  // hi = (shl lo, shamt[4:0])
2578  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2579  DAG.getConstant(-1, DL, MVT::i32));
2580  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2581  DAG.getConstant(1, DL, VT));
2582  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2583  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2584  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2585  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2586  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2587  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2588  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2589  DAG.getConstant(0, DL, VT), ShiftLeftLo);
2590  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2591 
2592  SDValue Ops[2] = {Lo, Hi};
2593  return DAG.getMergeValues(Ops, DL);
2594 }
2595 
2596 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2597  bool IsSRA) const {
2598  SDLoc DL(Op);
2599  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2600  SDValue Shamt = Op.getOperand(2);
2602 
2603  // if shamt < (VT.bits):
2604  // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2605  // if isSRA:
2606  // hi = (sra hi, shamt)
2607  // else:
2608  // hi = (srl hi, shamt)
2609  // else:
2610  // if isSRA:
2611  // lo = (sra hi, shamt[4:0])
2612  // hi = (sra hi, 31)
2613  // else:
2614  // lo = (srl hi, shamt[4:0])
2615  // hi = 0
2616  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2617  DAG.getConstant(-1, DL, MVT::i32));
2618  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2619  DAG.getConstant(1, DL, VT));
2620  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2621  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2622  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2623  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2624  DL, VT, Hi, Shamt);
2625  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2626  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2627  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2628  DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2629 
2630  if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2631  SDVTList VTList = DAG.getVTList(VT, VT);
2632  return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
2633  : Mips::PseudoD_SELECT_I,
2634  DL, VTList, Cond, ShiftRightHi,
2635  IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2636  ShiftRightHi);
2637  }
2638 
2639  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2640  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2641  IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2642 
2643  SDValue Ops[2] = {Lo, Hi};
2644  return DAG.getMergeValues(Ops, DL);
2645 }
2646 
2647 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2648  SDValue Chain, SDValue Src, unsigned Offset) {
2649  SDValue Ptr = LD->getBasePtr();
2650  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2651  EVT BasePtrVT = Ptr.getValueType();
2652  SDLoc DL(LD);
2653  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2654 
2655  if (Offset)
2656  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2657  DAG.getConstant(Offset, DL, BasePtrVT));
2658 
2659  SDValue Ops[] = { Chain, Ptr, Src };
2660  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2661  LD->getMemOperand());
2662 }
2663 
2664 // Expand an unaligned 32 or 64-bit integer load node.
2666  LoadSDNode *LD = cast<LoadSDNode>(Op);
2667  EVT MemVT = LD->getMemoryVT();
2668 
2670  return Op;
2671 
2672  // Return if load is aligned or if MemVT is neither i32 nor i64.
2673  if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2674  ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2675  return SDValue();
2676 
2677  bool IsLittle = Subtarget.isLittle();
2678  EVT VT = Op.getValueType();
2679  ISD::LoadExtType ExtType = LD->getExtensionType();
2680  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2681 
2682  assert((VT == MVT::i32) || (VT == MVT::i64));
2683 
2684  // Expand
2685  // (set dst, (i64 (load baseptr)))
2686  // to
2687  // (set tmp, (ldl (add baseptr, 7), undef))
2688  // (set dst, (ldr baseptr, tmp))
2689  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2690  SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2691  IsLittle ? 7 : 0);
2692  return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2693  IsLittle ? 0 : 7);
2694  }
2695 
2696  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2697  IsLittle ? 3 : 0);
2698  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2699  IsLittle ? 0 : 3);
2700 
2701  // Expand
2702  // (set dst, (i32 (load baseptr))) or
2703  // (set dst, (i64 (sextload baseptr))) or
2704  // (set dst, (i64 (extload baseptr)))
2705  // to
2706  // (set tmp, (lwl (add baseptr, 3), undef))
2707  // (set dst, (lwr baseptr, tmp))
2708  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2709  (ExtType == ISD::EXTLOAD))
2710  return LWR;
2711 
2712  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2713 
2714  // Expand
2715  // (set dst, (i64 (zextload baseptr)))
2716  // to
2717  // (set tmp0, (lwl (add baseptr, 3), undef))
2718  // (set tmp1, (lwr baseptr, tmp0))
2719  // (set tmp2, (shl tmp1, 32))
2720  // (set dst, (srl tmp2, 32))
2721  SDLoc DL(LD);
2722  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2723  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2724  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2725  SDValue Ops[] = { SRL, LWR.getValue(1) };
2726  return DAG.getMergeValues(Ops, DL);
2727 }
2728 
2729 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2730  SDValue Chain, unsigned Offset) {
2731  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2732  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2733  SDLoc DL(SD);
2734  SDVTList VTList = DAG.getVTList(MVT::Other);
2735 
2736  if (Offset)
2737  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2738  DAG.getConstant(Offset, DL, BasePtrVT));
2739 
2740  SDValue Ops[] = { Chain, Value, Ptr };
2741  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2742  SD->getMemOperand());
2743 }
2744 
2745 // Expand an unaligned 32 or 64-bit integer store node.
2747  bool IsLittle) {
2748  SDValue Value = SD->getValue(), Chain = SD->getChain();
2749  EVT VT = Value.getValueType();
2750 
2751  // Expand
2752  // (store val, baseptr) or
2753  // (truncstore val, baseptr)
2754  // to
2755  // (swl val, (add baseptr, 3))
2756  // (swr val, baseptr)
2757  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2758  SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2759  IsLittle ? 3 : 0);
2760  return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2761  }
2762 
2763  assert(VT == MVT::i64);
2764 
2765  // Expand
2766  // (store val, baseptr)
2767  // to
2768  // (sdl val, (add baseptr, 7))
2769  // (sdr val, baseptr)
2770  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2771  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2772 }
2773 
2774 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2776  bool SingleFloat) {
2777  SDValue Val = SD->getValue();
2778 
2779  if (Val.getOpcode() != ISD::FP_TO_SINT ||
2780  (Val.getValueSizeInBits() > 32 && SingleFloat))
2781  return SDValue();
2782 
2784  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2785  Val.getOperand(0));
2786  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2787  SD->getPointerInfo(), SD->getAlignment(),
2788  SD->getMemOperand()->getFlags());
2789 }
2790 
2792  StoreSDNode *SD = cast<StoreSDNode>(Op);
2793  EVT MemVT = SD->getMemoryVT();
2794 
2795  // Lower unaligned integer stores.
2797  (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2798  ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2799  return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2800 
2801  return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2802 }
2803 
2804 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2805  SelectionDAG &DAG) const {
2806 
2807  // Return a fixed StackObject with offset 0 which points to the old stack
2808  // pointer.
2810  EVT ValTy = Op->getValueType(0);
2811  int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2812  return DAG.getFrameIndex(FI, ValTy);
2813 }
2814 
2815 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2816  SelectionDAG &DAG) const {
2817  if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
2818  return SDValue();
2819 
2820  EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2821  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2822  Op.getOperand(0));
2823  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2824 }
2825 
2826 //===----------------------------------------------------------------------===//
2827 // Calling Convention Implementation
2828 //===----------------------------------------------------------------------===//
2829 
2830 //===----------------------------------------------------------------------===//
2831 // TODO: Implement a generic logic using tblgen that can support this.
2832 // Mips O32 ABI rules:
2833 // ---
2834 // i32 - Passed in A0, A1, A2, A3 and stack
2835 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2836 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2837 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2838 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2839 // not used, it must be shadowed. If only A3 is available, shadow it and
2840 // go to stack.
2841 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2842 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2843 // with the remainder spilled to the stack.
2844 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2845 // spilling the remainder to the stack.
2846 //
2847 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2848 //===----------------------------------------------------------------------===//
2849 
2850 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2851  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2852  CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2853  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2854  State.getMachineFunction().getSubtarget());
2855 
2856  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2857 
2858  const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2859 
2860  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2861 
2862  static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2863 
2864  // Do not process byval args here.
2865  if (ArgFlags.isByVal())
2866  return true;
2867 
2868  // Promote i8 and i16
2869  if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2870  if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2871  LocVT = MVT::i32;
2872  if (ArgFlags.isSExt())
2873  LocInfo = CCValAssign::SExtUpper;
2874  else if (ArgFlags.isZExt())
2875  LocInfo = CCValAssign::ZExtUpper;
2876  else
2877  LocInfo = CCValAssign::AExtUpper;
2878  }
2879  }
2880 
2881  // Promote i8 and i16
2882  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2883  LocVT = MVT::i32;
2884  if (ArgFlags.isSExt())
2885  LocInfo = CCValAssign::SExt;
2886  else if (ArgFlags.isZExt())
2887  LocInfo = CCValAssign::ZExt;
2888  else
2889  LocInfo = CCValAssign::AExt;
2890  }
2891 
2892  unsigned Reg;
2893 
2894  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2895  // is true: function is vararg, argument is 3rd or higher, there is previous
2896  // argument which is not f32 or f64.
2897  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2898  State.getFirstUnallocated(F32Regs) != ValNo;
2899  Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
2900  bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
2901  bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2902 
2903  // The MIPS vector ABI for floats passes them in a pair of registers
2904  if (ValVT == MVT::i32 && isVectorFloat) {
2905  // This is the start of an vector that was scalarized into an unknown number
2906  // of components. It doesn't matter how many there are. Allocate one of the
2907  // notional 8 byte aligned registers which map onto the argument stack, and
2908  // shadow the register lost to alignment requirements.
2909  if (ArgFlags.isSplit()) {
2910  Reg = State.AllocateReg(FloatVectorIntRegs);
2911  if (Reg == Mips::A2)
2912  State.AllocateReg(Mips::A1);
2913  else if (Reg == 0)
2914  State.AllocateReg(Mips::A3);
2915  } else {
2916  // If we're an intermediate component of the split, we can just attempt to
2917  // allocate a register directly.
2918  Reg = State.AllocateReg(IntRegs);
2919  }
2920  } else if (ValVT == MVT::i32 ||
2921  (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2922  Reg = State.AllocateReg(IntRegs);
2923  // If this is the first part of an i64 arg,
2924  // the allocated register must be either A0 or A2.
2925  if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2926  Reg = State.AllocateReg(IntRegs);
2927  LocVT = MVT::i32;
2928  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2929  // Allocate int register and shadow next int register. If first
2930  // available register is Mips::A1 or Mips::A3, shadow it too.
2931  Reg = State.AllocateReg(IntRegs);
2932  if (Reg == Mips::A1 || Reg == Mips::A3)
2933  Reg = State.AllocateReg(IntRegs);
2934  State.AllocateReg(IntRegs);
2935  LocVT = MVT::i32;
2936  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2937  // we are guaranteed to find an available float register
2938  if (ValVT == MVT::f32) {
2939  Reg = State.AllocateReg(F32Regs);
2940  // Shadow int register
2941  State.AllocateReg(IntRegs);
2942  } else {
2943  Reg = State.AllocateReg(F64Regs);
2944  // Shadow int registers
2945  unsigned Reg2 = State.AllocateReg(IntRegs);
2946  if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2947  State.AllocateReg(IntRegs);
2948  State.AllocateReg(IntRegs);
2949  }
2950  } else
2951  llvm_unreachable("Cannot handle this ValVT.");
2952 
2953  if (!Reg) {
2954  unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2955  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2956  } else
2957  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2958 
2959  return false;
2960 }
2961 
2962 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2963  MVT LocVT, CCValAssign::LocInfo LocInfo,
2964  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2965  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2966 
2967  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2968 }
2969 
2970 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2971  MVT LocVT, CCValAssign::LocInfo LocInfo,
2972  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2973  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2974 
2975  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2976 }
2977 
2978 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2979  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2981 
2982 #include "MipsGenCallingConv.inc"
2983 
2985  return CC_Mips_FixedArg;
2986  }
2987 
2989  return RetCC_Mips;
2990  }
2991 //===----------------------------------------------------------------------===//
2992 // Call Calling Convention Implementation
2993 //===----------------------------------------------------------------------===//
2994 
2995 // Return next O32 integer argument register.
2996 static unsigned getNextIntArgReg(unsigned Reg) {
2997  assert((Reg == Mips::A0) || (Reg == Mips::A2));
2998  return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2999 }
3000 
3001 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3002  SDValue Chain, SDValue Arg,
3003  const SDLoc &DL, bool IsTailCall,
3004  SelectionDAG &DAG) const {
3005  if (!IsTailCall) {
3006  SDValue PtrOff =
3007  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
3008  DAG.getIntPtrConstant(Offset, DL));
3009  return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
3010  }
3011 
3013  int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3014  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3015  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(),
3017 }
3018 
3021  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3022  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
3023  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
3024  SDValue Chain) const {
3025  // Insert node "GP copy globalreg" before call to function.
3026  //
3027  // R_MIPS_CALL* operators (emitted when non-internal functions are called
3028  // in PIC mode) allow symbols to be resolved via lazy binding.
3029  // The lazy binding stub requires GP to point to the GOT.
3030  // Note that we don't need GP to point to the GOT for indirect calls
3031  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3032  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
3033  // used for the function (that is, Mips linker doesn't generate lazy binding
3034  // stub for a function whose address is taken in the program).
3035  if (IsPICCall && !InternalLinkage && IsCallReloc) {
3036  unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3037  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
3038  RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
3039  }
3040 
3041  // Build a sequence of copy-to-reg nodes chained together with token
3042  // chain and flag operands which copy the outgoing args into registers.
3043  // The InFlag in necessary since all emitted instructions must be
3044  // stuck together.
3045  SDValue InFlag;
3046 
3047  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3048  Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
3049  RegsToPass[i].second, InFlag);
3050  InFlag = Chain.getValue(1);
3051  }
3052 
3053  // Add argument registers to the end of the list so that they are
3054  // known live into the call.
3055  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3056  Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
3057  RegsToPass[i].second.getValueType()));
3058 
3059  // Add a register mask operand representing the call-preserved registers.
3061  const uint32_t *Mask =
3063  assert(Mask && "Missing call preserved mask for calling convention");
3064  if (Subtarget.inMips16HardFloat()) {
3065  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
3066  StringRef Sym = G->getGlobal()->getName();
3067  Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3068  if (F && F->hasFnAttribute("__Mips16RetHelper")) {
3070  }
3071  }
3072  }
3073  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
3074 
3075  if (InFlag.getNode())
3076  Ops.push_back(InFlag);
3077 }
3078 
3080  SDNode *Node) const {
3081  switch (MI.getOpcode()) {
3082  default:
3083  return;
3084  case Mips::JALR:
3085  case Mips::JALRPseudo:
3086  case Mips::JALR64:
3087  case Mips::JALR64Pseudo:
3088  case Mips::JALR16_MM:
3089  case Mips::JALRC16_MMR6:
3090  case Mips::TAILCALLREG:
3091  case Mips::TAILCALLREG64:
3092  case Mips::TAILCALLR6REG:
3093  case Mips::TAILCALL64R6REG:
3094  case Mips::TAILCALLREG_MM:
3095  case Mips::TAILCALLREG_MMR6: {
3096  if (!EmitJalrReloc ||
3097  Subtarget.inMips16Mode() ||
3098  !isPositionIndependent() ||
3099  Node->getNumOperands() < 1 ||
3100  Node->getOperand(0).getNumOperands() < 2) {
3101  return;
3102  }
3103  // We are after the callee address, set by LowerCall().
3104  // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
3105  // symbol.
3106  const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3107  StringRef Sym;
3108  if (const GlobalAddressSDNode *G =
3109  dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3110  // We must not emit the R_MIPS_JALR relocation against data symbols
3111  // since this will cause run-time crashes if the linker replaces the
3112  // call instruction with a relative branch to the data symbol.
3113  if (!isa<Function>(G->getGlobal())) {
3114  LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3115  << G->getGlobal()->getName() << "\n");
3116  return;
3117  }
3118  Sym = G->getGlobal()->getName();
3119  }
3120  else if (const ExternalSymbolSDNode *ES =
3121  dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3122  Sym = ES->getSymbol();
3123  }
3124 
3125  if (Sym.empty())
3126  return;
3127 
3128  MachineFunction *MF = MI.getParent()->getParent();
3129  MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3130  LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3132  }
3133  }
3134 }
3135 
3136 /// LowerCall - functions arguments are copied from virtual regs to
3137 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3138 SDValue
3139 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3140  SmallVectorImpl<SDValue> &InVals) const {
3141  SelectionDAG &DAG = CLI.DAG;
3142  SDLoc DL = CLI.DL;
3144  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3146  SDValue Chain = CLI.Chain;
3147  SDValue Callee = CLI.Callee;
3148  bool &IsTailCall = CLI.IsTailCall;
3149  CallingConv::ID CallConv = CLI.CallConv;
3150  bool IsVarArg = CLI.IsVarArg;
3151 
3152  MachineFunction &MF = DAG.getMachineFunction();
3153  MachineFrameInfo &MFI = MF.getFrameInfo();
3155  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3156  bool IsPIC = isPositionIndependent();
3157 
3158  // Analyze operands of the call, assigning locations to each operand.
3160  MipsCCState CCInfo(
3161  CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3163 
3164  const ExternalSymbolSDNode *ES =
3165  dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3166 
3167  // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3168  // is during the lowering of a call with a byval argument which produces
3169  // a call to memcpy. For the O32 case, this causes the caller to allocate
3170  // stack space for the reserved argument area for the callee, then recursively
3171  // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3172  // ABIs mandate that the callee allocates the reserved argument area. We do
3173  // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3174  //
3175  // If the callee has a byval argument and memcpy is used, we are mandated
3176  // to already have produced a reserved argument area for the callee for O32.
3177  // Therefore, the reserved argument area can be reused for both calls.
3178  //
3179  // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3180  // present, as we have yet to hook that node onto the chain.
3181  //
3182  // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3183  // case. GCC does a similar trick, in that wherever possible, it calculates
3184  // the maximum out going argument area (including the reserved area), and
3185  // preallocates the stack space on entrance to the caller.
3186  //
3187  // FIXME: We should do the same for efficiency and space.
3188 
3189  // Note: The check on the calling convention below must match
3190  // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3191  bool MemcpyInByVal = ES &&
3192  StringRef(ES->getSymbol()) == StringRef("memcpy") &&
3193  CallConv != CallingConv::Fast &&
3194  Chain.getOpcode() == ISD::CALLSEQ_START;
3195 
3196  // Allocate the reserved argument area. It seems strange to do this from the
3197  // caller side but removing it breaks the frame size calculation.
3198  unsigned ReservedArgArea =
3199  MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3200  CCInfo.AllocateStack(ReservedArgArea, Align(1));
3201 
3202  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3203  ES ? ES->getSymbol() : nullptr);
3204 
3205  // Get a count of how many bytes are to be pushed on the stack.
3206  unsigned NextStackOffset = CCInfo.getNextStackOffset();
3207 
3208  // Call site info for function parameters tracking.
3210 
3211  // Check if it's really possible to do a tail call. Restrict it to functions
3212  // that are part of this compilation unit.
3213  bool InternalLinkage = false;
3214  if (IsTailCall) {
3215  IsTailCall = isEligibleForTailCallOptimization(
3216  CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3217  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3218  InternalLinkage = G->getGlobal()->hasInternalLinkage();
3219  IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3220  G->getGlobal()->hasPrivateLinkage() ||
3221  G->getGlobal()->hasHiddenVisibility() ||
3222  G->getGlobal()->hasProtectedVisibility());
3223  }
3224  }
3225  if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
3226  report_fatal_error("failed to perform tail call elimination on a call "
3227  "site marked musttail");
3228 
3229  if (IsTailCall)
3230  ++NumTailCalls;
3231 
3232  // Chain is the output chain of the last Load/Store or CopyToReg node.
3233  // ByValChain is the output chain of the last Memcpy node created for copying
3234  // byval arguments to the stack.
3235  unsigned StackAlignment = TFL->getStackAlignment();
3236  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3237  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3238 
3239  if (!(IsTailCall || MemcpyInByVal))
3240  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3241 
3242  SDValue StackPtr =
3243  DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3244  getPointerTy(DAG.getDataLayout()));
3245 
3246  std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3247  SmallVector<SDValue, 8> MemOpChains;
3248 
3249  CCInfo.rewindByValRegsInfo();
3250 
3251  // Walk the register/memloc assignments, inserting copies/loads.
3252  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3253  SDValue Arg = OutVals[i];
3254  CCValAssign &VA = ArgLocs[i];
3255  MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3256  ISD::ArgFlagsTy Flags = Outs[i].Flags;
3257  bool UseUpperBits = false;
3258 
3259  // ByVal Arg.
3260  if (Flags.isByVal()) {
3261  unsigned FirstByValReg, LastByValReg;
3262  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3263  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3264 
3265  assert(Flags.getByValSize() &&
3266  "ByVal args of size 0 should have been ignored by front-end.");
3267  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3268  assert(!IsTailCall &&
3269  "Do not tail-call optimize if there is a byval argument.");
3270  passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3271  FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3272  VA);
3273  CCInfo.nextInRegsParam();
3274  continue;
3275  }
3276 
3277  // Promote the value if needed.
3278  switch (VA.getLocInfo()) {
3279  default:
3280  llvm_unreachable("Unknown loc info!");
3281  case CCValAssign::Full:
3282  if (VA.isRegLoc()) {
3283  if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3284  (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3285  (ValVT == MVT::i64 && LocVT == MVT::f64))
3286  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3287  else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3289  Arg, DAG.getConstant(0, DL, MVT::i32));
3291  Arg, DAG.getConstant(1, DL, MVT::i32));
3292  if (!Subtarget.isLittle())
3293  std::swap(Lo, Hi);
3294  Register LocRegLo = VA.getLocReg();
3295  unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3296  RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3297  RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3298  continue;
3299  }
3300  }
3301  break;
3302  case CCValAssign::BCvt:
3303  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3304  break;
3306  UseUpperBits = true;
3308  case CCValAssign::SExt:
3309  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3310  break;
3312  UseUpperBits = true;
3314  case CCValAssign::ZExt:
3315  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3316  break;
3318  UseUpperBits = true;
3320  case CCValAssign::AExt:
3321  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3322  break;
3323  }
3324 
3325  if (UseUpperBits) {
3326  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3327  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3328  Arg = DAG.getNode(
3329  ISD::SHL, DL, VA.getLocVT(), Arg,
3330  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3331  }
3332 
3333  // Arguments that can be passed on register must be kept at
3334  // RegsToPass vector
3335  if (VA.isRegLoc()) {
3336  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3337 
3338  // If the parameter is passed through reg $D, which splits into
3339  // two physical registers, avoid creating call site info.
3340  if (Mips::AFGR64RegClass.contains(VA.getLocReg()))
3341  continue;
3342 
3343  // Collect CSInfo about which register passes which parameter.
3344  const TargetOptions &Options = DAG.getTarget().Options;
3345  if (Options.SupportsDebugEntryValues)
3346  CSInfo.emplace_back(VA.getLocReg(), i);
3347 
3348  continue;
3349  }
3350 
3351  // Register can't get to this point...
3352  assert(VA.isMemLoc());
3353 
3354  // emit ISD::STORE whichs stores the
3355  // parameter value to a stack Location
3356  MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3357  Chain, Arg, DL, IsTailCall, DAG));
3358  }
3359 
3360  // Transform all store nodes into one single node because all store
3361  // nodes are independent of each other.
3362  if (!MemOpChains.empty())
3363  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3364 
3365  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3366  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3367  // node so that legalize doesn't hack it.
3368 
3369  EVT Ty = Callee.getValueType();
3370  bool GlobalOrExternal = false, IsCallReloc = false;
3371 
3372  // The long-calls feature is ignored in case of PIC.
3373  // While we do not support -mshared / -mno-shared properly,
3374  // ignore long-calls in case of -mabicalls too.
3375  if (!Subtarget.isABICalls() && !IsPIC) {
3376  // If the function should be called using "long call",
3377  // get its address into a register to prevent using
3378  // of the `jal` instruction for the direct call.
3379  if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3380  if (Subtarget.useLongCalls())
3382  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3383  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3384  } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3385  bool UseLongCalls = Subtarget.useLongCalls();
3386  // If the function has long-call/far/near attribute
3387  // it overrides command line switch pased to the backend.
3388  if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3389  if (F->hasFnAttribute("long-call"))
3390  UseLongCalls = true;
3391  else if (F->hasFnAttribute("short-call"))
3392  UseLongCalls = false;
3393  }
3394  if (UseLongCalls)
3396  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3397  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3398  }
3399  }
3400 
3401  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3402  if (IsPIC) {
3403  const GlobalValue *Val = G->getGlobal();
3404  InternalLinkage = Val->hasInternalLinkage();
3405 
3406  if (InternalLinkage)
3407  Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3408  else if (Subtarget.useXGOT()) {
3410  MipsII::MO_CALL_LO16, Chain,
3411  FuncInfo->callPtrInfo(MF, Val));
3412  IsCallReloc = true;
3413  } else {
3414  Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3415  FuncInfo->callPtrInfo(MF, Val));
3416  IsCallReloc = true;
3417  }
3418  } else
3419  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3420  getPointerTy(DAG.getDataLayout()), 0,
3422  GlobalOrExternal = true;
3423  }
3424  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3425  const char *Sym = S->getSymbol();
3426 
3427  if (!IsPIC) // static
3430  else if (Subtarget.useXGOT()) {
3432  MipsII::MO_CALL_LO16, Chain,
3433  FuncInfo->callPtrInfo(MF, Sym));
3434  IsCallReloc = true;
3435  } else { // PIC
3436  Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3437  FuncInfo->callPtrInfo(MF, Sym));
3438  IsCallReloc = true;
3439  }
3440 
3441  GlobalOrExternal = true;
3442  }
3443 
3444  SmallVector<SDValue, 8> Ops(1, Chain);
3445  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3446 
3447  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3448  IsCallReloc, CLI, Callee, Chain);
3449 
3450  if (IsTailCall) {
3453  DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
3454  return Ret;
3455  }
3456 
3457  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3458  SDValue InFlag = Chain.getValue(1);
3459 
3460  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
3461 
3462  // Create the CALLSEQ_END node in the case of where it is not a call to
3463  // memcpy.
3464  if (!(MemcpyInByVal)) {
3465  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3466  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3467  InFlag = Chain.getValue(1);
3468  }
3469 
3470  // Handle result values, copying them out of physregs into vregs that we
3471  // return.
3472  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3473  InVals, CLI);
3474 }
3475 
3476 /// LowerCallResult - Lower the result values of a call into the
3477 /// appropriate copies out of appropriate physical registers.
3478 SDValue MipsTargetLowering::LowerCallResult(
3479  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3480  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3481  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3482  TargetLowering::CallLoweringInfo &CLI) const {
3483  // Assign locations to each value returned by this call.
3485  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3486  *DAG.getContext());
3487 
3488  const ExternalSymbolSDNode *ES =
3489  dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3490  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3491  ES ? ES->getSymbol() : nullptr);
3492 
3493  // Copy all of the result registers out of their specified physreg.
3494  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3495  CCValAssign &VA = RVLocs[i];
3496  assert(VA.isRegLoc() && "Can only return in registers!");
3497 
3498  SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3499  RVLocs[i].getLocVT(), InFlag);
3500  Chain = Val.getValue(1);
3501  InFlag = Val.getValue(2);
3502 
3503  if (VA.isUpperBitsInLoc()) {
3504  unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3505  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3506  unsigned Shift =
3508  Val = DAG.getNode(
3509  Shift, DL, VA.getLocVT(), Val,
3510  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3511  }
3512 
3513  switch (VA.getLocInfo()) {
3514  default:
3515  llvm_unreachable("Unknown loc info!");
3516  case CCValAssign::Full:
3517  break;
3518  case CCValAssign::BCvt:
3519  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3520  break;
3521  case CCValAssign::AExt:
3523  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3524  break;
3525  case CCValAssign::ZExt:
3527  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3528  DAG.getValueType(VA.getValVT()));
3529  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3530  break;
3531  case CCValAssign::SExt:
3533  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3534  DAG.getValueType(VA.getValVT()));
3535  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3536  break;
3537  }
3538 
3539  InVals.push_back(Val);
3540  }
3541 
3542  return Chain;
3543 }
3544 
3546  EVT ArgVT, const SDLoc &DL,
3547  SelectionDAG &DAG) {
3548  MVT LocVT = VA.getLocVT();
3549  EVT ValVT = VA.getValVT();
3550 
3551  // Shift into the upper bits if necessary.
3552  switch (VA.getLocInfo()) {
3553  default:
3554  break;
3557  case CCValAssign::ZExtUpper: {
3558  unsigned ValSizeInBits = ArgVT.getSizeInBits();
3559  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3560  unsigned Opcode =
3562  Val = DAG.getNode(
3563  Opcode, DL, VA.getLocVT(), Val,
3564  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3565  break;
3566  }
3567  }
3568 
3569  // If this is an value smaller than the argument slot size (32-bit for O32,
3570  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3571  // size. Extract the value and insert any appropriate assertions regarding
3572  // sign/zero extension.
3573  switch (VA.getLocInfo()) {
3574  default:
3575  llvm_unreachable("Unknown loc info!");
3576  case CCValAssign::Full:
3577  break;
3579  case CCValAssign::AExt:
3580  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3581  break;
3583  case CCValAssign::SExt:
3584  Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3585  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3586  break;
3588  case CCValAssign::ZExt:
3589  Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3590  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3591  break;
3592  case CCValAssign::BCvt:
3593  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3594  break;
3595  }
3596 
3597  return Val;
3598 }
3599 
3600 //===----------------------------------------------------------------------===//
3601 // Formal Arguments Calling Convention Implementation
3602 //===----------------------------------------------------------------------===//
3603 /// LowerFormalArguments - transform physical registers into virtual registers
3604 /// and generate load operations for arguments places on the stack.
3605 SDValue MipsTargetLowering::LowerFormalArguments(
3606  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3607  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3608  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3609  MachineFunction &MF = DAG.getMachineFunction();
3610  MachineFrameInfo &MFI = MF.getFrameInfo();
3611  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3612 
3613  MipsFI->setVarArgsFrameIndex(0);
3614 
3615  // Used with vargs to acumulate store chains.
3616  std::vector<SDValue> OutChains;
3617 
3618  // Assign locations to all of the incoming arguments.
3620  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3621  *DAG.getContext());
3622  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1));
3623  const Function &Func = DAG.getMachineFunction().getFunction();
3624  Function::const_arg_iterator FuncArg = Func.arg_begin();
3625 
3626  if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3628  "Functions with the interrupt attribute cannot have arguments!");
3629 
3630  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3631  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3632  CCInfo.getInRegsParamsCount() > 0);
3633 
3634  unsigned CurArgIdx = 0;
3635  CCInfo.rewindByValRegsInfo();
3636 
3637  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3638  CCValAssign &VA = ArgLocs[i];
3639  if (Ins[i].isOrigArg()) {
3640  std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3641  CurArgIdx = Ins[i].getOrigArgIndex();
3642  }
3643  EVT ValVT = VA.getValVT();
3644  ISD::ArgFlagsTy Flags = Ins[i].Flags;
3645  bool IsRegLoc = VA.isRegLoc();
3646 
3647  if (Flags.isByVal()) {
3648  assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3649  unsigned FirstByValReg, LastByValReg;
3650  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3651  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3652 
3653  assert(Flags.getByValSize() &&
3654  "ByVal args of size 0 should have been ignored by front-end.");
3655  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3656  copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3657  FirstByValReg, LastByValReg, VA, CCInfo);
3658  CCInfo.nextInRegsParam();
3659  continue;
3660  }
3661 
3662  // Arguments stored on registers
3663  if (IsRegLoc) {
3664  MVT RegVT = VA.getLocVT();
3665  Register ArgReg = VA.getLocReg();
3666  const TargetRegisterClass *RC = getRegClassFor(RegVT);
3667 
3668  // Transform the arguments stored on
3669  // physical registers into virtual ones
3670  unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3671  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3672 
3673  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3674 
3675  // Handle floating point arguments passed in integer registers and
3676  // long double arguments passed in floating point registers.
3677  if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3678  (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3679  (RegVT == MVT::f64 && ValVT == MVT::i64))
3680  ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3681  else if (ABI.IsO32() && RegVT == MVT::i32 &&
3682  ValVT == MVT::f64) {
3683  unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3684  getNextIntArgReg(ArgReg), RC);
3685  SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3686  if (!Subtarget.isLittle())
3687  std::swap(ArgValue, ArgValue2);
3688  ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3689  ArgValue, ArgValue2);
3690  }
3691 
3692  InVals.push_back(ArgValue);
3693  } else { // VA.isRegLoc()
3694  MVT LocVT = VA.getLocVT();
3695 
3696  if (ABI.IsO32()) {
3697  // We ought to be able to use LocVT directly but O32 sets it to i32
3698  // when allocating floating point values to integer registers.
3699  // This shouldn't influence how we load the value into registers unless
3700  // we are targeting softfloat.
3702  LocVT = VA.getValVT();
3703  }
3704 
3705  // sanity check
3706  assert(VA.isMemLoc());
3707 
3708  // The stack pointer offset is relative to the caller stack frame.
3709  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3710  VA.getLocMemOffset(), true);
3711 
3712  // Create load nodes to retrieve arguments from the stack
3713  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3714  SDValue ArgValue = DAG.getLoad(
3715  LocVT, DL, Chain, FIN,
3717  OutChains.push_back(ArgValue.getValue(1));
3718 
3719  ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3720 
3721  InVals.push_back(ArgValue);
3722  }
3723  }
3724 
3725  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3726  // The mips ABIs for returning structs by value requires that we copy
3727  // the sret argument into $v0 for the return. Save the argument into
3728  // a virtual register so that we can access it from the return points.
3729  if (Ins[i].Flags.isSRet()) {
3730  unsigned Reg = MipsFI->getSRetReturnReg();
3731  if (!Reg) {
3734  MipsFI->setSRetReturnReg(Reg);
3735  }
3736  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3737  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3738  break;
3739  }
3740  }
3741 
3742  if (IsVarArg)
3743  writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3744 
3745  // All stores are grouped in one node to allow the matching between
3746  // the size of Ins and InVals. This only happens when on varg functions
3747  if (!OutChains.empty()) {
3748  OutChains.push_back(Chain);
3749  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3750  }
3751 
3752  return Chain;
3753 }
3754 
3755 //===----------------------------------------------------------------------===//
3756 // Return Value Calling Convention Implementation
3757 //===----------------------------------------------------------------------===//
3758 
3759 bool
3760 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3761  MachineFunction &MF, bool IsVarArg,
3762  const SmallVectorImpl<ISD::OutputArg> &Outs,
3763  LLVMContext &Context) const {
3765  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3766  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3767 }
3768 
3769 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type,
3770  bool IsSigned) const {
3771  if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3772  return true;
3773 
3774  return IsSigned;
3775 }
3776 
3777 SDValue
3778 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3779  const SDLoc &DL,
3780  SelectionDAG &DAG) const {
3781  MachineFunction &MF = DAG.getMachineFunction();
3782  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3783 
3784  MipsFI->setISR();
3785 
3786  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3787 }
3788 
3789 SDValue
3790 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3791  bool IsVarArg,
3792  const SmallVectorImpl<ISD::OutputArg> &Outs,
3793  const SmallVectorImpl<SDValue> &OutVals,
3794  const SDLoc &DL, SelectionDAG &DAG) const {
3795  // CCValAssign - represent the assignment of
3796  // the return value to a location
3798  MachineFunction &MF = DAG.getMachineFunction();
3799 
3800  // CCState - Info about the registers and stack slot.
3801  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3802 
3803  // Analyze return values.
3804  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3805 
3806  SDValue Flag;
3807  SmallVector<SDValue, 4> RetOps(1, Chain);
3808 
3809  // Copy the result values into the output registers.
3810  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3811  SDValue Val = OutVals[i];
3812  CCValAssign &VA = RVLocs[i];
3813  assert(VA.isRegLoc() && "Can only return in registers!");
3814  bool UseUpperBits = false;
3815 
3816  switch (VA.getLocInfo()) {
3817  default:
3818  llvm_unreachable("Unknown loc info!");
3819  case CCValAssign::Full:
3820  break;
3821  case CCValAssign::BCvt:
3822  Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3823  break;
3825  UseUpperBits = true;
3827  case CCValAssign::AExt:
3828  Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3829  break;
3831  UseUpperBits = true;
3833  case CCValAssign::ZExt:
3834  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3835  break;
3837  UseUpperBits = true;
3839  case CCValAssign::SExt:
3840  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3841  break;
3842  }
3843 
3844  if (UseUpperBits) {
3845  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3846  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3847  Val = DAG.getNode(
3848  ISD::SHL, DL, VA.getLocVT(), Val,
3849  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3850  }
3851 
3852  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3853 
3854  // Guarantee that all emitted copies are stuck together with flags.
3855  Flag = Chain.getValue(1);
3856  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3857  }
3858 
3859  // The mips ABIs for returning structs by value requires that we copy
3860  // the sret argument into $v0 for the return. We saved the argument into
3861  // a virtual register in the entry block, so now we copy the value out
3862  // and into $v0.
3863  if (MF.getFunction().hasStructRetAttr()) {
3864  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3865  unsigned Reg = MipsFI->getSRetReturnReg();
3866 
3867  if (!Reg)
3868  llvm_unreachable("sret virtual register not created in the entry block");
3869  SDValue Val =
3870  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3871  unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3872 
3873  Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3874  Flag = Chain.getValue(1);
3875  RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3876  }
3877 
3878  RetOps[0] = Chain; // Update chain.
3879 
3880  // Add the flag if we have it.
3881  if (Flag.getNode())
3882  RetOps.push_back(Flag);
3883 
3884  // ISRs must use "eret".
3885  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3886  return LowerInterruptReturn(RetOps, DL, DAG);
3887 
3888  // Standard return on Mips is a "jr $ra"
3889  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3890 }
3891 
3892 //===----------------------------------------------------------------------===//
3893 // Mips Inline Assembly Support
3894 //===----------------------------------------------------------------------===//
3895 
3896 /// getConstraintType - Given a constraint letter, return the type of
3897 /// constraint it is for this target.
3899 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3900  // Mips specific constraints
3901  // GCC config/mips/constraints.md
3902  //
3903  // 'd' : An address register. Equivalent to r
3904  // unless generating MIPS16 code.
3905  // 'y' : Equivalent to r; retained for
3906  // backwards compatibility.
3907  // 'c' : A register suitable for use in an indirect
3908  // jump. This will always be $25 for -mabicalls.
3909  // 'l' : The lo register. 1 word storage.
3910  // 'x' : The hilo register pair. Double word storage.
3911  if (Constraint.size() == 1) {
3912  switch (Constraint[0]) {
3913  default : break;
3914  case 'd':
3915  case 'y':
3916  case 'f':
3917  case 'c':
3918  case 'l':
3919  case 'x':
3920  return C_RegisterClass;
3921  case 'R':
3922  return C_Memory;
3923  }
3924  }
3925 
3926  if (Constraint == "ZC")
3927  return C_Memory;
3928 
3929  return TargetLowering::getConstraintType(Constraint);
3930 }
3931 
3932 /// Examine constraint type and operand type and determine a weight value.
3933 /// This object must already have been set up with the operand type
3934 /// and the current alternative constraint selected.
3936 MipsTargetLowering::getSingleConstraintMatchWeight(
3937  AsmOperandInfo &info, const char *constraint) const {
3938  ConstraintWeight weight = CW_Invalid;
3939  Value *CallOperandVal = info.CallOperandVal;
3940  // If we don't have a value, we can't do a match,
3941  // but allow it at the lowest weight.
3942  if (!CallOperandVal)
3943  return CW_Default;
3944  Type *type = CallOperandVal->getType();
3945  // Look at the constraint type.
3946  switch (*constraint) {
3947  default:
3949  break;
3950  case 'd':
3951  case 'y':
3952  if (type->isIntegerTy())
3953  weight = CW_Register;
3954  break;
3955  case 'f': // FPU or MSA register
3956  if (Subtarget.hasMSA() && type->isVectorTy() &&
3957  type->getPrimitiveSizeInBits().getFixedSize() == 128)
3958  weight = CW_Register;
3959  else if (type->isFloatTy())
3960  weight = CW_Register;
3961  break;
3962  case 'c': // $25 for indirect jumps
3963  case 'l': // lo register
3964  case 'x': // hilo register pair
3965  if (type->isIntegerTy())
3966  weight = CW_SpecificReg;
3967  break;
3968  case 'I': // signed 16 bit immediate
3969  case 'J': // integer zero
3970  case 'K': // unsigned 16 bit immediate
3971  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3972  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3973  case 'O': // signed 15 bit immediate (+- 16383)
3974  case 'P': // immediate in the range of 65535 to 1 (inclusive)
3975  if (isa<ConstantInt>(CallOperandVal))
3976  weight = CW_Constant;
3977  break;
3978  case 'R':
3979  weight = CW_Memory;
3980  break;
3981  }
3982  return weight;
3983 }
3984 
3985 /// This is a helper function to parse a physical register string and split it
3986 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3987 /// that is returned indicates whether parsing was successful. The second flag
3988 /// is true if the numeric part exists.
3989 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3990  unsigned long long &Reg) {
3991  if (C.front() != '{' || C.back() != '}')
3992  return std::make_pair(false, false);
3993 
3994  // Search for the first numeric character.
3995  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3996  I = std::find_if(B, E, isdigit);
3997 
3998  Prefix = StringRef(B, I - B);
3999 
4000  // The second flag is set to false if no numeric characters were found.
4001  if (I == E)
4002  return std::make_pair(true, false);
4003 
4004  // Parse the numeric characters.
4005  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
4006  true);
4007 }
4008 
4010  ISD::NodeType) const {
4011  bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
4013  return VT.bitsLT(MinVT) ? MinVT : VT;
4014 }
4015 
4016 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4017 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
4018  const TargetRegisterInfo *TRI =
4020  const TargetRegisterClass *RC;
4021  StringRef Prefix;
4022  unsigned long long Reg;
4023 
4024  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
4025 
4026  if (!R.first)
4027  return std::make_p