81#define DEBUG_TYPE "mips-lower"
87 cl::desc(
"MIPS: Don't trap on integer division by zero."),
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
125 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
130 return NumIntermediates;
146 unsigned Flag)
const {
152 unsigned Flag)
const {
158 unsigned Flag)
const {
164 unsigned Flag)
const {
170 unsigned Flag)
const {
172 N->getOffset(), Flag);
567 if (!
TM.isPositionIndependent() || !
TM.getABI().IsO32() ||
587 EVT Ty =
N->getValueType(0);
588 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
589 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
595 N->getOperand(0),
N->getOperand(1));
600 if (
N->hasAnyUseOfValue(0)) {
609 if (
N->hasAnyUseOfValue(1)) {
651 "Illegal Condition Code");
665 if (!
LHS.getValueType().isFloatingPoint())
777 SDValue ValueIfTrue =
N->getOperand(0), ValueIfFalse =
N->getOperand(2);
793 SDValue FCC =
N->getOperand(1), Glue =
N->getOperand(3);
794 return DAG.
getNode(Opc,
SDLoc(
N), ValueIfFalse.getValueType(),
795 ValueIfFalse, FCC, ValueIfTrue, Glue);
804 SDValue FirstOperand =
N->getOperand(0);
805 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
807 EVT ValTy =
N->getValueType(0);
811 unsigned SMPos, SMSize;
817 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
827 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
847 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))))
852 if (SMPos != Pos || Pos >= ValTy.
getSizeInBits() || SMSize >= 32 ||
874 NewOperand = FirstOperand;
876 return DAG.
getNode(Opc,
DL, ValTy, NewOperand,
891 SDValue And0 =
N->getOperand(0), And1 =
N->getOperand(1);
892 unsigned SMPos0, SMSize0, SMPos1, SMSize1;
899 if (!(CN = dyn_cast<ConstantSDNode>(And0.
getOperand(1))) ||
905 And1.getOperand(0).getOpcode() ==
ISD::SHL) {
907 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
912 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
917 if (!(CN = dyn_cast<ConstantSDNode>(Shl.
getOperand(1))))
924 EVT ValTy =
N->getValueType(0);
925 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.
getSizeInBits()))
938 if (~CN->
getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
939 ((SMSize0 + SMPos0 <= 64 && Subtarget.
hasMips64r2()) ||
940 (SMSize0 + SMPos0 <= 32))) {
944 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
947 if (!(CN1 = dyn_cast<ConstantSDNode>(
N->getOperand(1))))
956 EVT ValTy =
N->getOperand(0)->getValueType(0);
1031 if (!Mult.hasOneUse())
1039 SDValue MultLHS = Mult->getOperand(0);
1040 SDValue MultRHS = Mult->getOperand(1);
1047 if (!IsSigned && !IsUnsigned)
1053 std::tie(BottomHalf, TopHalf) =
1065 EVT VTs[2] = {MVT::i32, MVT::i32};
1081 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1096 !Subtarget.
inMips16Mode() &&
N->getValueType(0) == MVT::i64)
1114 EVT ValTy =
N->getValueType(0);
1132 SDValue FirstOperand =
N->getOperand(0);
1133 unsigned FirstOperandOpc = FirstOperand.
getOpcode();
1134 SDValue SecondOperand =
N->getOperand(1);
1135 EVT ValTy =
N->getValueType(0);
1139 unsigned SMPos, SMSize;
1144 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1156 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.
getOperand(1))) ||
1162 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.
getSizeInBits())
1177 unsigned Opc =
N->getOpcode();
1216 if (
auto *
C = dyn_cast<ConstantSDNode>(
Y))
1217 return C->getAPIntValue().ule(15);
1225 N->getOperand(0).getOpcode() ==
ISD::SRL) ||
1227 N->getOperand(0).getOpcode() ==
ISD::SHL)) &&
1228 "Expected shift-shift mask");
1230 if (
N->getOperand(0).getValueType().isVector())
1245 switch (
Op.getOpcode())
1292 bool Is64Bit,
bool IsMicroMips) {
1301 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1322 switch (
MI.getOpcode()) {
1325 case Mips::ATOMIC_LOAD_ADD_I8:
1326 return emitAtomicBinaryPartword(
MI, BB, 1);
1327 case Mips::ATOMIC_LOAD_ADD_I16:
1328 return emitAtomicBinaryPartword(
MI, BB, 2);
1329 case Mips::ATOMIC_LOAD_ADD_I32:
1330 return emitAtomicBinary(
MI, BB);
1331 case Mips::ATOMIC_LOAD_ADD_I64:
1332 return emitAtomicBinary(
MI, BB);
1334 case Mips::ATOMIC_LOAD_AND_I8:
1335 return emitAtomicBinaryPartword(
MI, BB, 1);
1336 case Mips::ATOMIC_LOAD_AND_I16:
1337 return emitAtomicBinaryPartword(
MI, BB, 2);
1338 case Mips::ATOMIC_LOAD_AND_I32:
1339 return emitAtomicBinary(
MI, BB);
1340 case Mips::ATOMIC_LOAD_AND_I64:
1341 return emitAtomicBinary(
MI, BB);
1343 case Mips::ATOMIC_LOAD_OR_I8:
1344 return emitAtomicBinaryPartword(
MI, BB, 1);
1345 case Mips::ATOMIC_LOAD_OR_I16:
1346 return emitAtomicBinaryPartword(
MI, BB, 2);
1347 case Mips::ATOMIC_LOAD_OR_I32:
1348 return emitAtomicBinary(
MI, BB);
1349 case Mips::ATOMIC_LOAD_OR_I64:
1350 return emitAtomicBinary(
MI, BB);
1352 case Mips::ATOMIC_LOAD_XOR_I8:
1353 return emitAtomicBinaryPartword(
MI, BB, 1);
1354 case Mips::ATOMIC_LOAD_XOR_I16:
1355 return emitAtomicBinaryPartword(
MI, BB, 2);
1356 case Mips::ATOMIC_LOAD_XOR_I32:
1357 return emitAtomicBinary(
MI, BB);
1358 case Mips::ATOMIC_LOAD_XOR_I64:
1359 return emitAtomicBinary(
MI, BB);
1361 case Mips::ATOMIC_LOAD_NAND_I8:
1362 return emitAtomicBinaryPartword(
MI, BB, 1);
1363 case Mips::ATOMIC_LOAD_NAND_I16:
1364 return emitAtomicBinaryPartword(
MI, BB, 2);
1365 case Mips::ATOMIC_LOAD_NAND_I32:
1366 return emitAtomicBinary(
MI, BB);
1367 case Mips::ATOMIC_LOAD_NAND_I64:
1368 return emitAtomicBinary(
MI, BB);
1370 case Mips::ATOMIC_LOAD_SUB_I8:
1371 return emitAtomicBinaryPartword(
MI, BB, 1);
1372 case Mips::ATOMIC_LOAD_SUB_I16:
1373 return emitAtomicBinaryPartword(
MI, BB, 2);
1374 case Mips::ATOMIC_LOAD_SUB_I32:
1375 return emitAtomicBinary(
MI, BB);
1376 case Mips::ATOMIC_LOAD_SUB_I64:
1377 return emitAtomicBinary(
MI, BB);
1379 case Mips::ATOMIC_SWAP_I8:
1380 return emitAtomicBinaryPartword(
MI, BB, 1);
1381 case Mips::ATOMIC_SWAP_I16:
1382 return emitAtomicBinaryPartword(
MI, BB, 2);
1383 case Mips::ATOMIC_SWAP_I32:
1384 return emitAtomicBinary(
MI, BB);
1385 case Mips::ATOMIC_SWAP_I64:
1386 return emitAtomicBinary(
MI, BB);
1388 case Mips::ATOMIC_CMP_SWAP_I8:
1389 return emitAtomicCmpSwapPartword(
MI, BB, 1);
1390 case Mips::ATOMIC_CMP_SWAP_I16:
1391 return emitAtomicCmpSwapPartword(
MI, BB, 2);
1392 case Mips::ATOMIC_CMP_SWAP_I32:
1393 return emitAtomicCmpSwap(
MI, BB);
1394 case Mips::ATOMIC_CMP_SWAP_I64:
1395 return emitAtomicCmpSwap(
MI, BB);
1397 case Mips::ATOMIC_LOAD_MIN_I8:
1398 return emitAtomicBinaryPartword(
MI, BB, 1);
1399 case Mips::ATOMIC_LOAD_MIN_I16:
1400 return emitAtomicBinaryPartword(
MI, BB, 2);
1401 case Mips::ATOMIC_LOAD_MIN_I32:
1402 return emitAtomicBinary(
MI, BB);
1403 case Mips::ATOMIC_LOAD_MIN_I64:
1404 return emitAtomicBinary(
MI, BB);
1406 case Mips::ATOMIC_LOAD_MAX_I8:
1407 return emitAtomicBinaryPartword(
MI, BB, 1);
1408 case Mips::ATOMIC_LOAD_MAX_I16:
1409 return emitAtomicBinaryPartword(
MI, BB, 2);
1410 case Mips::ATOMIC_LOAD_MAX_I32:
1411 return emitAtomicBinary(
MI, BB);
1412 case Mips::ATOMIC_LOAD_MAX_I64:
1413 return emitAtomicBinary(
MI, BB);
1415 case Mips::ATOMIC_LOAD_UMIN_I8:
1416 return emitAtomicBinaryPartword(
MI, BB, 1);
1417 case Mips::ATOMIC_LOAD_UMIN_I16:
1418 return emitAtomicBinaryPartword(
MI, BB, 2);
1419 case Mips::ATOMIC_LOAD_UMIN_I32:
1420 return emitAtomicBinary(
MI, BB);
1421 case Mips::ATOMIC_LOAD_UMIN_I64:
1422 return emitAtomicBinary(
MI, BB);
1424 case Mips::ATOMIC_LOAD_UMAX_I8:
1425 return emitAtomicBinaryPartword(
MI, BB, 1);
1426 case Mips::ATOMIC_LOAD_UMAX_I16:
1427 return emitAtomicBinaryPartword(
MI, BB, 2);
1428 case Mips::ATOMIC_LOAD_UMAX_I32:
1429 return emitAtomicBinary(
MI, BB);
1430 case Mips::ATOMIC_LOAD_UMAX_I64:
1431 return emitAtomicBinary(
MI, BB);
1433 case Mips::PseudoSDIV:
1434 case Mips::PseudoUDIV:
1441 case Mips::SDIV_MM_Pseudo:
1442 case Mips::UDIV_MM_Pseudo:
1445 case Mips::DIV_MMR6:
1446 case Mips::DIVU_MMR6:
1447 case Mips::MOD_MMR6:
1448 case Mips::MODU_MMR6:
1450 case Mips::PseudoDSDIV:
1451 case Mips::PseudoDUDIV:
1458 case Mips::PseudoSELECT_I:
1459 case Mips::PseudoSELECT_I64:
1460 case Mips::PseudoSELECT_S:
1461 case Mips::PseudoSELECT_D32:
1462 case Mips::PseudoSELECT_D64:
1463 return emitPseudoSELECT(
MI, BB,
false, Mips::BNE);
1464 case Mips::PseudoSELECTFP_F_I:
1465 case Mips::PseudoSELECTFP_F_I64:
1466 case Mips::PseudoSELECTFP_F_S:
1467 case Mips::PseudoSELECTFP_F_D32:
1468 case Mips::PseudoSELECTFP_F_D64:
1469 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1F);
1470 case Mips::PseudoSELECTFP_T_I:
1471 case Mips::PseudoSELECTFP_T_I64:
1472 case Mips::PseudoSELECTFP_T_S:
1473 case Mips::PseudoSELECTFP_T_D32:
1474 case Mips::PseudoSELECTFP_T_D64:
1475 return emitPseudoSELECT(
MI, BB,
true, Mips::BC1T);
1476 case Mips::PseudoD_SELECT_I:
1477 case Mips::PseudoD_SELECT_I64:
1478 return emitPseudoD_SELECT(
MI, BB);
1480 return emitLDR_W(
MI, BB);
1482 return emitLDR_D(
MI, BB);
1484 return emitSTR_W(
MI, BB);
1486 return emitSTR_D(
MI, BB);
1502 bool NeedsAdditionalReg =
false;
1503 switch (
MI.getOpcode()) {
1504 case Mips::ATOMIC_LOAD_ADD_I32:
1505 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1507 case Mips::ATOMIC_LOAD_SUB_I32:
1508 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1510 case Mips::ATOMIC_LOAD_AND_I32:
1511 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1513 case Mips::ATOMIC_LOAD_OR_I32:
1514 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1516 case Mips::ATOMIC_LOAD_XOR_I32:
1517 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1519 case Mips::ATOMIC_LOAD_NAND_I32:
1520 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1522 case Mips::ATOMIC_SWAP_I32:
1523 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1525 case Mips::ATOMIC_LOAD_ADD_I64:
1526 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1528 case Mips::ATOMIC_LOAD_SUB_I64:
1529 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1531 case Mips::ATOMIC_LOAD_AND_I64:
1532 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1534 case Mips::ATOMIC_LOAD_OR_I64:
1535 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1537 case Mips::ATOMIC_LOAD_XOR_I64:
1538 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1540 case Mips::ATOMIC_LOAD_NAND_I64:
1541 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1543 case Mips::ATOMIC_SWAP_I64:
1544 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1546 case Mips::ATOMIC_LOAD_MIN_I32:
1547 AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1548 NeedsAdditionalReg =
true;
1550 case Mips::ATOMIC_LOAD_MAX_I32:
1551 AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1552 NeedsAdditionalReg =
true;
1554 case Mips::ATOMIC_LOAD_UMIN_I32:
1555 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1556 NeedsAdditionalReg =
true;
1558 case Mips::ATOMIC_LOAD_UMAX_I32:
1559 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1560 NeedsAdditionalReg =
true;
1562 case Mips::ATOMIC_LOAD_MIN_I64:
1563 AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1564 NeedsAdditionalReg =
true;
1566 case Mips::ATOMIC_LOAD_MAX_I64:
1567 AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1568 NeedsAdditionalReg =
true;
1570 case Mips::ATOMIC_LOAD_UMIN_I64:
1571 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1572 NeedsAdditionalReg =
true;
1574 case Mips::ATOMIC_LOAD_UMAX_I64:
1575 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1576 NeedsAdditionalReg =
true;
1637 if (NeedsAdditionalReg) {
1644 MI.eraseFromParent();
1651 unsigned SrcReg)
const {
1671 int64_t ShiftImm = 32 - (
Size * 8);
1682 "Unsupported size for EmitAtomicBinaryPartial.");
1709 unsigned AtomicOp = 0;
1710 bool NeedsAdditionalReg =
false;
1711 switch (
MI.getOpcode()) {
1712 case Mips::ATOMIC_LOAD_NAND_I8:
1713 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1715 case Mips::ATOMIC_LOAD_NAND_I16:
1716 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1718 case Mips::ATOMIC_SWAP_I8:
1719 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1721 case Mips::ATOMIC_SWAP_I16:
1722 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1724 case Mips::ATOMIC_LOAD_ADD_I8:
1725 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1727 case Mips::ATOMIC_LOAD_ADD_I16:
1728 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1730 case Mips::ATOMIC_LOAD_SUB_I8:
1731 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1733 case Mips::ATOMIC_LOAD_SUB_I16:
1734 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1736 case Mips::ATOMIC_LOAD_AND_I8:
1737 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1739 case Mips::ATOMIC_LOAD_AND_I16:
1740 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1742 case Mips::ATOMIC_LOAD_OR_I8:
1743 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1745 case Mips::ATOMIC_LOAD_OR_I16:
1746 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1748 case Mips::ATOMIC_LOAD_XOR_I8:
1749 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1751 case Mips::ATOMIC_LOAD_XOR_I16:
1752 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1754 case Mips::ATOMIC_LOAD_MIN_I8:
1755 AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1756 NeedsAdditionalReg =
true;
1758 case Mips::ATOMIC_LOAD_MIN_I16:
1759 AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1760 NeedsAdditionalReg =
true;
1762 case Mips::ATOMIC_LOAD_MAX_I8:
1763 AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1764 NeedsAdditionalReg =
true;
1766 case Mips::ATOMIC_LOAD_MAX_I16:
1767 AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1768 NeedsAdditionalReg =
true;
1770 case Mips::ATOMIC_LOAD_UMIN_I8:
1771 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1772 NeedsAdditionalReg =
true;
1774 case Mips::ATOMIC_LOAD_UMIN_I16:
1775 AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1776 NeedsAdditionalReg =
true;
1778 case Mips::ATOMIC_LOAD_UMAX_I8:
1779 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1780 NeedsAdditionalReg =
true;
1782 case Mips::ATOMIC_LOAD_UMAX_I16:
1783 AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1784 NeedsAdditionalReg =
true;
1813 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
1854 if (NeedsAdditionalReg) {
1860 MI.eraseFromParent();
1874 assert((
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1875 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1876 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1878 const unsigned Size =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1886 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1887 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1888 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1903 Register OldValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(OldVal));
1904 Register NewValCopy =
MRI.createVirtualRegister(
MRI.getRegClass(NewVal));
1922 MI.eraseFromParent();
1930 "Unsupported size for EmitAtomicCmpSwapPartial.");
1957 unsigned AtomicOp =
MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1958 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1959 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
2000 int64_t MaskImm = (
Size == 1) ? 255 : 65535;
2001 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
2003 BuildMI(BB,
DL,
TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2046 MI.eraseFromParent();
2071 FCC0, Dest, CondRes);
2093 "Floating point operand expected.");
2104 EVT Ty =
Op.getValueType();
2152 EVT Ty =
Op.getValueType();
2195 Args.push_back(Entry);
2200 .setLibCallee(
CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2201 std::pair<SDValue, SDValue> CallResult =
LowerCallTo(CLI);
2247 EVT Ty =
Op.getValueType();
2260 EVT Ty =
Op.getValueType();
2289 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
2296 EVT VT =
Node->getValueType(0);
2301 const Value *SV = cast<SrcValueSDNode>(
Node->getOperand(2))->getValue();
2328 unsigned ArgSizeInBytes =
2344 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2353 bool HasExtractInsert) {
2354 EVT TyX =
Op.getOperand(0).getValueType();
2355 EVT TyY =
Op.getOperand(1).getValueType();
2372 if (HasExtractInsert) {
2390 if (TyX == MVT::f32)
2400 bool HasExtractInsert) {
2401 unsigned WidthX =
Op.getOperand(0).getValueSizeInBits();
2402 unsigned WidthY =
Op.getOperand(1).getValueSizeInBits();
2411 if (HasExtractInsert) {
2417 if (WidthX > WidthY)
2419 else if (WidthY > WidthX)
2438 if (WidthX > WidthY)
2440 else if (WidthY > WidthX)
2458 bool HasExtractInsert)
const {
2470 Op.getOperand(0), Const1);
2473 if (HasExtractInsert)
2484 if (
Op.getValueType() == MVT::f32)
2498 bool HasExtractInsert)
const {
2509 if (HasExtractInsert)
2531 if (
Op.getConstantOperandVal(0) != 0) {
2533 "return address can be determined only for current frame");
2539 EVT VT =
Op.getValueType();
2552 if (
Op.getConstantOperandVal(0) != 0) {
2554 "return address can be determined only for current frame");
2560 MVT VT =
Op.getSimpleValueType();
2561 unsigned RA =
ABI.
IsN64() ? Mips::RA_64 : Mips::RA;
2587 unsigned OffsetReg =
ABI.
IsN64() ? Mips::V1_64 : Mips::V1;
2588 unsigned AddrReg =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
2678 DL, VTList,
Cond, ShiftRightHi,
2694 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2695 EVT BasePtrVT =
Ptr.getValueType();
2705 LD->getMemOperand());
2711 EVT MemVT = LD->getMemoryVT();
2717 if ((LD->getAlign().value() >= (MemVT.
getSizeInBits() / 8)) ||
2718 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2722 EVT VT =
Op.getValueType();
2726 assert((VT == MVT::i32) || (VT == MVT::i64));
2769 SDValue Ops[] = { SRL, LWR.getValue(1) };
2842 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2854 EVT ValTy =
Op->getValueType(0);
2900 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2906 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2914 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2918 else if (ArgFlags.
isZExt())
2926 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2930 else if (ArgFlags.
isZExt())
2941 bool AllocateFloatsInIntReg = State.
isVarArg() || ValNo > 1 ||
2944 bool isI64 = (ValVT == MVT::i32 && OrigAlign ==
Align(8));
2948 if (ValVT == MVT::i32 && isVectorFloat) {
2955 if (Reg == Mips::A2)
2964 }
else if (ValVT == MVT::i32 ||
2965 (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2969 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2972 }
else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2976 if (Reg == Mips::A1 || Reg == Mips::A3)
2992 if (ValVT == MVT::f32) {
3000 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
3019 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
3021 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3027 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
3029 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
3036#include "MipsGenCallingConv.inc"
3039 return CC_Mips_FixedArg;
3051 const SDLoc &
DL,
bool IsTailCall,
3069 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3070 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
3083 if (IsPICCall && !InternalLinkage && IsCallReloc) {
3084 unsigned GPReg =
ABI.
IsN64() ? Mips::GP_64 : Mips::GP;
3086 RegsToPass.push_back(std::make_pair(GPReg,
getGlobalReg(CLI.
DAG, Ty)));
3095 for (
auto &R : RegsToPass) {
3102 for (
auto &R : RegsToPass)
3109 assert(Mask &&
"Missing call preserved mask for calling convention");
3113 Function *
F =
G->getGlobal()->getParent()->getFunction(
Sym);
3114 if (
F &&
F->hasFnAttribute(
"__Mips16RetHelper")) {
3127 switch (
MI.getOpcode()) {
3131 case Mips::JALRPseudo:
3133 case Mips::JALR64Pseudo:
3134 case Mips::JALR16_MM:
3135 case Mips::JALRC16_MMR6:
3136 case Mips::TAILCALLREG:
3137 case Mips::TAILCALLREG64:
3138 case Mips::TAILCALLR6REG:
3139 case Mips::TAILCALL64R6REG:
3140 case Mips::TAILCALLREG_MM:
3141 case Mips::TAILCALLREG_MMR6: {
3145 Node->getNumOperands() < 1 ||
3146 Node->getOperand(0).getNumOperands() < 2) {
3152 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3155 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3159 if (!isa<Function>(
G->getGlobal())) {
3160 LLVM_DEBUG(
dbgs() <<
"Not adding R_MIPS_JALR against data symbol "
3161 <<
G->getGlobal()->getName() <<
"\n");
3164 Sym =
G->getGlobal()->getName();
3167 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3168 Sym = ES->getSymbol();
3211 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3237 bool MemcpyInByVal = ES &&
3244 unsigned ReservedArgArea =
3246 CCInfo.AllocateStack(ReservedArgArea,
Align(1));
3252 unsigned StackSize = CCInfo.getStackSize();
3259 bool InternalLinkage =
false;
3261 IsTailCall = isEligibleForTailCallOptimization(
3264 InternalLinkage =
G->getGlobal()->hasInternalLinkage();
3265 IsTailCall &= (InternalLinkage ||
G->getGlobal()->hasLocalLinkage() ||
3266 G->getGlobal()->hasPrivateLinkage() ||
3267 G->getGlobal()->hasHiddenVisibility() ||
3268 G->getGlobal()->hasProtectedVisibility());
3273 "site marked musttail");
3282 StackSize =
alignTo(StackSize, StackAlignment);
3284 if (!(IsTailCall || MemcpyInByVal))
3291 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3294 CCInfo.rewindByValRegsInfo();
3297 for (
unsigned i = 0, e = ArgLocs.
size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3298 SDValue Arg = OutVals[OutIdx];
3302 bool UseUpperBits =
false;
3305 if (
Flags.isByVal()) {
3306 unsigned FirstByValReg, LastByValReg;
3307 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3308 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3311 "ByVal args of size 0 should have been ignored by front-end.");
3312 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3314 "Do not tail-call optimize if there is a byval argument.");
3315 passByValArg(Chain,
DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3318 CCInfo.nextInRegsParam();
3328 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3329 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3330 (ValVT == MVT::i64 && LocVT == MVT::f64))
3332 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3343 Register LocRegHigh = ArgLocs[++i].getLocReg();
3344 RegsToPass.
push_back(std::make_pair(LocRegLo,
Lo));
3345 RegsToPass.push_back(std::make_pair(LocRegHigh,
Hi));
3354 UseUpperBits =
true;
3360 UseUpperBits =
true;
3366 UseUpperBits =
true;
3374 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3384 RegsToPass.push_back(std::make_pair(VA.
getLocReg(), Arg));
3405 Chain, Arg,
DL, IsTailCall, DAG));
3410 if (!MemOpChains.
empty())
3418 bool GlobalOrExternal =
false, IsCallReloc =
false;
3427 if (
auto *
N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3432 }
else if (
auto *
N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3436 if (
auto *
F = dyn_cast<Function>(
N->getGlobal())) {
3437 if (
F->hasFnAttribute(
"long-call"))
3438 UseLongCalls =
true;
3439 else if (
F->hasFnAttribute(
"short-call"))
3440 UseLongCalls =
false;
3454 if (InternalLinkage)
3470 GlobalOrExternal =
true;
3473 const char *
Sym = S->getSymbol();
3489 GlobalOrExternal =
true;
3495 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3496 IsCallReloc, CLI, Callee, Chain);
3512 if (!(MemcpyInByVal)) {
3519 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins,
DL, DAG,
3525SDValue MipsTargetLowering::LowerCallResult(
3536 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.
Callee.
getNode());
3537 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.
RetTy,
3541 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3546 RVLocs[i].getLocVT(), InGlue);
3551 unsigned ValSizeInBits =
Ins[i].ArgVT.getSizeInBits();
3652SDValue MipsTargetLowering::LowerFormalArguments(
3663 std::vector<SDValue> OutChains;
3673 if (
Func.hasFnAttribute(
"interrupt") && !
Func.arg_empty())
3675 "Functions with the interrupt attribute cannot have arguments!");
3677 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3679 CCInfo.getInRegsParamsCount() > 0);
3681 unsigned CurArgIdx = 0;
3682 CCInfo.rewindByValRegsInfo();
3684 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3686 if (Ins[InsIdx].isOrigArg()) {
3687 std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3688 CurArgIdx =
Ins[InsIdx].getOrigArgIndex();
3694 if (
Flags.isByVal()) {
3695 assert(Ins[InsIdx].isOrigArg() &&
"Byval arguments cannot be implicit");
3696 unsigned FirstByValReg, LastByValReg;
3697 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3698 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3701 "ByVal args of size 0 should have been ignored by front-end.");
3702 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3703 copyByValRegs(Chain,
DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3704 FirstByValReg, LastByValReg, VA, CCInfo);
3705 CCInfo.nextInRegsParam();
3725 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3726 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3727 (RegVT == MVT::f64 && ValVT == MVT::i64))
3729 else if (
ABI.
IsO32() && RegVT == MVT::i32 &&
3730 ValVT == MVT::f64) {
3739 ArgValue, ArgValue2);
3758 LocVT,
DL, Chain, FIN,
3760 OutChains.push_back(ArgValue.
getValue(1));
3769 for (
unsigned i = 0, e = ArgLocs.
size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3771 if (ArgLocs[i].needsCustom()) {
3779 if (Ins[InsIdx].
Flags.isSRet()) {
3793 writeVarArgRegs(OutChains, Chain,
DL, DAG, CCInfo);
3797 if (!OutChains.empty()) {
3798 OutChains.push_back(Chain);
3815 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3816 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3819bool MipsTargetLowering::shouldSignExtendTypeInLibCall(
EVT Type,
3820 bool IsSigned)
const {
3854 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3860 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
3864 bool UseUpperBits =
false;
3875 UseUpperBits =
true;
3881 UseUpperBits =
true;
3887 UseUpperBits =
true;
3895 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3921 unsigned V0 =
ABI.
IsN64() ? Mips::V0_64 : Mips::V0;
3936 return LowerInterruptReturn(RetOps,
DL, DAG);
3949MipsTargetLowering::getConstraintType(
StringRef Constraint)
const {
3961 if (Constraint.
size() == 1) {
3962 switch (Constraint[0]) {
3976 if (Constraint ==
"ZC")
3986MipsTargetLowering::getSingleConstraintMatchWeight(
3987 AsmOperandInfo &
info,
const char *constraint)
const {
3989 Value *CallOperandVal =
info.CallOperandVal;
3992 if (!CallOperandVal)
3996 switch (*constraint) {
4025 if (isa<ConstantInt>(CallOperandVal))
4040 unsigned long long &Reg) {
4041 if (
C.front() !=
'{' ||
C.back() !=
'}')
4042 return std::make_pair(
false,
false);
4046 I = std::find_if(
B, E, isdigit);
4052 return std::make_pair(
true,
false);
4063 return VT.
bitsLT(MinVT) ? MinVT : VT;
4066std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4072 unsigned long long Reg;
4077 return std::make_pair(0U,
nullptr);
4079 if ((Prefix ==
"hi" || Prefix ==
"lo")) {
4082 return std::make_pair(0U,
nullptr);
4084 RC =
TRI->getRegClass(Prefix ==
"hi" ?
4085 Mips::HI32RegClassID : Mips::LO32RegClassID);
4086 return std::make_pair(*(RC->
begin()), RC);
4087 }
else if (Prefix.starts_with(
"$msa")) {
4092 return std::make_pair(0U,
nullptr);
4095 .
Case(
"$msair", Mips::MSAIR)
4096 .
Case(
"$msacsr", Mips::MSACSR)
4097 .
Case(
"$msaaccess", Mips::MSAAccess)
4098 .
Case(
"$msasave", Mips::MSASave)
4099 .
Case(
"$msamodify", Mips::MSAModify)
4100 .
Case(
"$msarequest", Mips::MSARequest)
4101 .
Case(
"$msamap", Mips::MSAMap)
4102 .
Case(
"$msaunmap", Mips::MSAUnmap)
4106 return std::make_pair(0U,
nullptr);
4108 RC =
TRI->getRegClass(Mips::MSACtrlRegClassID);
4109 return std::make_pair(Reg, RC);
4113 return std::make_pair(0U,
nullptr);
4115 if (Prefix ==
"$f") {
4118 if (VT == MVT::Other)
4123 if (RC == &Mips::AFGR64RegClass) {
4127 }
else if (Prefix ==
"$fcc")
4128 RC =
TRI->getRegClass(Mips::FCCRegClassID);
4129 else if (Prefix ==
"$w") {
4136 assert(Reg < RC->getNumRegs());
4137 return std::make_pair(*(RC->
begin() + Reg), RC);
4143std::pair<unsigned, const TargetRegisterClass *>
4147 if (Constraint.
size() == 1) {
4148 switch (Constraint[0]) {
4152 if ((VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8 ||
4156 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
4157 return std::make_pair(0U, &Mips::GPR32RegClass);
4161 return std::make_pair(0U, &Mips::GPR32RegClass);
4164 return std::make_pair(0U, &Mips::GPR64RegClass);
4166 return std::make_pair(0U,
nullptr);
4168 if (VT == MVT::v16i8)
4169 return std::make_pair(0U, &Mips::MSA128BRegClass);
4170 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
4171 return std::make_pair(0U, &Mips::MSA128HRegClass);
4172 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
4173 return std::make_pair(0U, &Mips::MSA128WRegClass);
4174 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
4175 return std::make_pair(0U, &Mips::MSA128DRegClass);
4176 else if (VT == MVT::f32)
4177 return std::make_pair(0U, &Mips::FGR32RegClass);
4180 return std::make_pair(0U, &Mips::FGR64RegClass);
4181 return std::make_pair(0U, &Mips::AFGR64RegClass);
4186 return std::make_pair((
unsigned)Mips::T9, &Mips::GPR32RegClass);
4188 return std::make_pair((
unsigned)Mips::T9_64, &Mips::GPR64RegClass);
4190 return std::make_pair(0U,
nullptr);
4193 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
4194 return std::make_pair((
unsigned)Mips::LO0, &Mips::LO32RegClass);
4195 return std::make_pair((
unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4200 return std::make_pair(0U,
nullptr);
4204 if (!Constraint.
empty()) {
4205 std::pair<unsigned, const TargetRegisterClass *>
R;
4206 R = parseRegForInlineAsmConstraint(Constraint, VT);
4217void MipsTargetLowering::LowerAsmOperandForConstraint(
SDValue Op,
4219 std::vector<SDValue> &Ops,
4225 if (Constraint.
size() > 1)
4228 char ConstraintLetter = Constraint[0];
4229 switch (ConstraintLetter) {
4235 int64_t Val =
C->getSExtValue();
4236 if (isInt<16>(Val)) {
4245 int64_t Val =
C->getZExtValue();
4256 if (isUInt<16>(Val)) {
4265 int64_t Val =
C->getSExtValue();
4266 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4275 int64_t Val =
C->getSExtValue();
4276 if ((Val >= -65535) && (Val <= -1)) {
4285 int64_t Val =
C->getSExtValue();
4286 if ((isInt<15>(Val))) {
4295 int64_t Val =
C->getSExtValue();
4296 if ((Val <= 65535) && (Val >= 1)) {
4305 Ops.push_back(Result);
4312bool MipsTargetLowering::isLegalAddressingMode(
const DataLayout &
DL,
4340EVT MipsTargetLowering::getOptimalMemOpType(
4348bool MipsTargetLowering::isFPImmLegal(
const APFloat &Imm,
EVT VT,
4349 bool ForCodeSize)
const {
4350 if (VT != MVT::f32 && VT != MVT::f64)
4352 if (
Imm.isNegZero())
4354 return Imm.isZero();
4357unsigned MipsTargetLowering::getJumpTableEncoding()
const {
4366bool MipsTargetLowering::useSoftFloat()
const {
4370void MipsTargetLowering::copyByValRegs(
4374 unsigned FirstReg,
unsigned LastReg,
const CCValAssign &VA,
4379 unsigned NumRegs = LastReg - FirstReg;
4380 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4381 unsigned FrameObjSize = std::max(
Flags.getByValSize(), RegAreaSize);
4388 (
int)((ByValArgRegs.
size() - FirstReg) * GPRSizeInBytes);
4410 for (
unsigned I = 0;
I < NumRegs; ++
I) {
4411 unsigned ArgReg = ByValArgRegs[FirstReg +
I];
4412 unsigned VReg =
addLiveIn(MF, ArgReg, RC);
4413 unsigned Offset =
I * GPRSizeInBytes;
4418 OutChains.push_back(Store);
4423void MipsTargetLowering::passByValArg(
4425 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4430 unsigned ByValSizeInBytes =
Flags.getByValSize();
4431 unsigned OffsetInBytes = 0;
4434 std::min(
Flags.getNonZeroByValAlign(),
Align(RegSizeInBytes));
4437 unsigned NumRegs = LastReg - FirstReg;
4441 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4445 for (;
I < NumRegs - LeftoverBytes; ++
I, OffsetInBytes += RegSizeInBytes) {
4451 unsigned ArgReg = ArgRegs[FirstReg +
I];
4452 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4456 if (ByValSizeInBytes == OffsetInBytes)
4460 if (LeftoverBytes) {
4463 for (
unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4464 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4465 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4467 if (RemainingSizeInBytes < LoadSizeInBytes)
4483 Shamt = TotalBytesLoaded * 8;
4485 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4495 OffsetInBytes += LoadSizeInBytes;
4496 TotalBytesLoaded += LoadSizeInBytes;
4497 Alignment = std::min(Alignment,
Align(LoadSizeInBytes));
4500 unsigned ArgReg = ArgRegs[FirstReg +
I];
4501 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4507 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4514 Align(Alignment),
false,
false,
4519void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4540 (
int)(RegSizeInBytes * (ArgRegs.
size() -
Idx));
4552 for (
unsigned I =
Idx;
I < ArgRegs.
size();
4553 ++
I, VaArgOffset += RegSizeInBytes) {
4560 cast<StoreSDNode>(
Store.getNode())->getMemOperand()->setValue(
4562 OutChains.push_back(Store);
4567 Align Alignment)
const {
4570 assert(
Size &&
"Byval argument's size shouldn't be 0.");
4574 unsigned FirstReg = 0;
4575 unsigned NumRegs = 0;
4587 Alignment >=
Align(RegSizeInBytes) &&
4588 "Byval argument's alignment should be a multiple of RegSizeInBytes.");
4596 if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) {
4597 State->
AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4603 for (
unsigned I = FirstReg;
Size > 0 && (
I < IntArgRegs.
size());
4604 Size -= RegSizeInBytes, ++
I, ++NumRegs)
4614 unsigned Opc)
const {
4616 "Subtarget already supports SELECT nodes with the use of"
4617 "conditional-move instructions.");
4640 F->insert(It, copy0MBB);
4641 F->insert(It, sinkMBB);
4684 MI.eraseFromParent();
4693 "Subtarget already supports SELECT nodes with the use of"
4694 "conditional-move instructions.");
4717 F->insert(It, copy0MBB);
4718 F->insert(It, sinkMBB);
4760 MI.eraseFromParent();
4773 .
Case(
"$28", Mips::GP_64)
4774 .
Case(
"sp", Mips::SP_64)
4780 .
Case(
"$28", Mips::GP)
4781 .
Case(
"sp", Mips::SP)
4799 unsigned Imm =
MI.getOperand(2).getImm();
4805 Register Temp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4814 Register LoadHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4815 Register LoadFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4816 Register Undef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4821 .
addImm(Imm + (IsLittle ? 0 : 3))
4826 .
addImm(Imm + (IsLittle ? 3 : 0))
4831 MI.eraseFromParent();
4845 unsigned Imm =
MI.getOperand(2).getImm();
4852 Register Temp =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
4859 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4860 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4861 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4865 .
addImm(Imm + (IsLittle ? 0 : 4));
4869 .
addImm(Imm + (IsLittle ? 4 : 0));
4879 Register LoHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4880 Register LoFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4881 Register LoUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4882 Register HiHalf =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4883 Register HiFull =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4884 Register HiUndef =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4885 Register Wtemp =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4890 .
addImm(Imm + (IsLittle ? 0 : 7))
4895 .
addImm(Imm + (IsLittle ? 3 : 4))
4901 .
addImm(Imm + (IsLittle ? 4 : 3))
4906 .
addImm(Imm + (IsLittle ? 7 : 0))
4915 MI.eraseFromParent();
4927 Register StoreVal =
MI.getOperand(0).getReg();
4929 unsigned Imm =
MI.getOperand(2).getImm();
4935 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
4936 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4949 Register Tmp =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
4957 .
addImm(Imm + (IsLittle ? 0 : 3));
4961 .
addImm(Imm + (IsLittle ? 3 : 0));
4964 MI.eraseFromParent();
4977 Register StoreVal =
MI.getOperand(0).getReg();
4979 unsigned Imm =
MI.getOperand(2).getImm();
4986 Register BitcastD =
MRI.createVirtualRegister(&Mips::MSA128DRegClass);
4987 Register Lo =
MRI.createVirtualRegister(&Mips::GPR64RegClass);
5000 Register BitcastW =
MRI.createVirtualRegister(&Mips::MSA128WRegClass);
5001 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5002 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5017 .
addImm(Imm + (IsLittle ? 0 : 4));
5021 .
addImm(Imm + (IsLittle ? 4 : 0));
5027 Register Lo =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5028 Register Hi =
MRI.createVirtualRegister(&Mips::GPR32RegClass);
5041 .
addImm(Imm + (IsLittle ? 0 : 3));
5045 .
addImm(Imm + (IsLittle ? 3 : 0));
5049 .
addImm(Imm + (IsLittle ? 4 : 7));
5053 .
addImm(Imm + (IsLittle ? 7 : 4));
5056 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget, const AArch64TargetLowering &TLI)
static SDValue performANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_ATTRIBUTE_UNUSED
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static MachineBasicBlock * insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock *MBB)
unsigned const TargetRegisterInfo * TRI
cl::opt< bool > EmitJalrReloc
static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) LLVM_ATTRIBUTE_UNUSED
static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, ArrayRef< MCPhysReg > F64Regs)
static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, const MipsSubtarget &Subtarget)
static bool invertFPCondCodeUser(Mips::CondCode CC)
This function returns true if the floating point conditional branches and conditional moves which use...
static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG, bool SingleFloat)
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static const MCPhysReg Mips64DPRegs[8]
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, bool IsLittle)
static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset)
static unsigned addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
static std::pair< bool, bool > parsePhysicalReg(StringRef C, StringRef &Prefix, unsigned long long &Reg)
This is a helper function to parse a physical register string and split it into non-numeric and numer...
static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset)
static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
cl::opt< bool > EmitJalrReloc
static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op)
static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert)
static cl::opt< bool > NoZeroDivCheck("mno-check-zero-division", cl::Hidden, cl::desc("MIPS: Don't trap on integer division by zero."), cl::init(false))
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget)
static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, EVT ArgVT, const SDLoc &DL, SelectionDAG &DAG)
static Mips::CondCode condCodeToFCC(ISD::CondCode CC)
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
This file defines the SmallVector class.
static const MCPhysReg IntRegs[32]
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static const MCPhysReg F32Regs[64]
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class represents an incoming formal argument to a Function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
static BranchProbability getOne()
CCState - This class holds information needed while lowering arguments and return values.
MachineFunction & getMachineFunction() const
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
CallingConv::ID getCallingConv() const
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
int64_t AllocateStack(unsigned Size, Align Alignment)
AllocateStack - Allocate a chunk of stack space with the specified size and alignment.
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
void addInRegsParamInfo(unsigned RegBegin, unsigned RegEnd)
void addLoc(const CCValAssign &V)
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
bool isUpperBitsInLoc() const
static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
int64_t getLocMemOffset() const
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
const char * getSymbol() const
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalValue * getGlobal() const
bool hasLocalLinkage() const
const GlobalObject * getAliaseeObject() const
bool hasInternalLinkage() const
Class to represent integer types.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
This class is used to represent ISD::LOAD nodes.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
static auto fp_fixedlen_vector_valuetypes()
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
const MachineOperand & getOperand(unsigned i) const
@ EK_GPRel64BlockAddress
EK_GPRel64BlockAddress - Each entry is an address of block, encoded with a relocation as gp-relative,...
@ MOVolatile
The memory access is volatile.
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
void setSubReg(unsigned subReg)
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
void setIsKill(bool Val=true)
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
ArrayRef< MCPhysReg > GetVarArgRegs() const
The registers to use for the variable argument list.
bool ArePtrs64bit() const
unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const
Obtain the size of the area allocated by the callee for arguments.
unsigned GetPtrAddiuOp() const
unsigned GetPtrAndOp() const
ArrayRef< MCPhysReg > GetByValArgRegs() const
The registers to use for byval arguments.
unsigned GetNullPtr() const
bool WasOriginalArgVectorFloat(unsigned ValNo) const
static SpecialCallingConvType getSpecialCallingConvForCallee(const SDNode *Callee, const MipsSubtarget &Subtarget)
Determine the SpecialCallingConvType for the given callee.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
void setVarArgsFrameIndex(int Index)
unsigned getSRetReturnReg() const
int getVarArgsFrameIndex() const
MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES)
Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue object representing a GOT ent...
Register getGlobalBaseReg(MachineFunction &MF)
void setSRetReturnReg(unsigned Reg)
void setFormalArgInfo(unsigned Size, bool HasByval)
static const uint32_t * getMips16RetHelperMask()
bool inMicroMipsMode() const
bool useSoftFloat() const
const MipsInstrInfo * getInstrInfo() const override
bool inMips16Mode() const
bool inAbs2008Mode() const
const MipsRegisterInfo * getRegisterInfo() const override
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
bool isSingleFloat() const
bool useLongCalls() const
unsigned getGPRSizeInBytes() const
bool inMips16HardFloat() const
const TargetFrameLowering * getFrameLowering() const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static const MipsTargetLowering * create(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Break down vectors to the correct number of gpr sized integers.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific
SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - get the ISD::SETCC result ValueType
SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
createFastISel - This method returns a target specific FastISel object, or null if the target does no...
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
CCAssignFn * CCAssignFnForReturn() const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
CCAssignFn * CCAssignFnForCall() const
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG) const
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
virtual void getOpndList(SmallVectorImpl< SDValue > &Ops, std::deque< std::pair< unsigned, SDValue > > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const
This function fills Ops, which is the list of operands that will later be used when a function call n...
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool shouldFoldConstantShiftPairToMask(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to fold a pair of shifts into a mask.
SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN32OrN64) const
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const
const MipsSubtarget & Subtarget
void HandleByVal(CCState *, unsigned &, Align) const override
Target-specific cleanup for formal ByVal parameters.
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const
bool IsConstantInSmallSection(const DataLayout &DL, const Constant *CN, const TargetMachine &TM) const
Return true if this constant should be placed into small data section.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getRegisterMask(const uint32_t *RegMask)
void addCallSiteInfo(const SDNode *Node, CallSiteInfo &&CallInfo)
Set CallSiteInfo to be associated with Node.
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getValue() const
bool isTruncatingStore() const
Return true if the op does a truncation before store.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
virtual TargetLoweringObjectFile * getObjFileLowering() const
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr ScalarTy getFixedValue() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SHL
Shift and rotation operations.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
@ MO_GOT
MO_GOT - Represents the offset into the global offset table at which the address the relocation entry...
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ EarlyClobber
Register definition happens before uses.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
const MipsTargetLowering * createMips16TargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Create MipsTargetLowering objects.
@ Or
Bitwise or logical OR of integers.
unsigned getKillRegState(bool B)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
DWARFExpression::Operation Op
const MipsTargetLowering * createMipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
bool getAsUnsignedInteger(StringRef Str, unsigned Radix, unsigned long long &Result)
Helper functions for StringRef::getAsInteger.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getFloatingPointVT(unsigned BitWidth)
Returns the EVT that represents a floating-point type with the given number of bits.
bool isVector() const
Return true if this is a vector value type.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Align getNonZeroOrigAlign() const
SmallVector< ArgRegPair, 1 > ArgRegPairs
Vector of call argument and its forwarding register.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const
