LLVM  15.0.0git
MipsISelLowering.cpp
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1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsISelLowering.h"
18 #include "MipsCCState.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "MipsTargetObjectFile.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/StringSwitch.h"
50 #include "llvm/IR/CallingConv.h"
51 #include "llvm/IR/Constants.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/DebugLoc.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/Function.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
64 #include "llvm/Support/Compiler.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78 
79 using namespace llvm;
80 
81 #define DEBUG_TYPE "mips-lower"
82 
83 STATISTIC(NumTailCalls, "Number of tail calls");
84 
85 static cl::opt<bool>
86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
87  cl::desc("MIPS: Don't trap on integer division by zero."),
88  cl::init(false));
89 
91 
92 static const MCPhysReg Mips64DPRegs[8] = {
93  Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94  Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
95 };
96 
97 // The MIPS MSA ABI passes vector arguments in the integer register set.
98 // The number of integer registers used is dependant on the ABI used.
100  CallingConv::ID CC,
101  EVT VT) const {
102  if (!VT.isVector())
103  return getRegisterType(Context, VT);
104 
105  return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
106  : MVT::i64;
107 }
108 
110  CallingConv::ID CC,
111  EVT VT) const {
112  if (VT.isVector())
113  return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
115 }
116 
118  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
119  unsigned &NumIntermediates, MVT &RegisterVT) const {
120  // Break down vector types to either 2 i64s or 4 i32s.
121  RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
122  IntermediateVT = RegisterVT;
123  NumIntermediates =
124  VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits()
125  ? VT.getVectorNumElements()
126  : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits());
127  return NumIntermediates;
128 }
129 
133  return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty);
134 }
135 
136 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
137  SelectionDAG &DAG,
138  unsigned Flag) const {
139  return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
140 }
141 
142 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
143  SelectionDAG &DAG,
144  unsigned Flag) const {
145  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
146 }
147 
148 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
149  SelectionDAG &DAG,
150  unsigned Flag) const {
151  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
152 }
153 
154 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
155  SelectionDAG &DAG,
156  unsigned Flag) const {
157  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
158 }
159 
160 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
161  SelectionDAG &DAG,
162  unsigned Flag) const {
163  return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
164  N->getOffset(), Flag);
165 }
166 
167 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
168  switch ((MipsISD::NodeType)Opcode) {
169  case MipsISD::FIRST_NUMBER: break;
170  case MipsISD::JmpLink: return "MipsISD::JmpLink";
171  case MipsISD::TailCall: return "MipsISD::TailCall";
172  case MipsISD::Highest: return "MipsISD::Highest";
173  case MipsISD::Higher: return "MipsISD::Higher";
174  case MipsISD::Hi: return "MipsISD::Hi";
175  case MipsISD::Lo: return "MipsISD::Lo";
176  case MipsISD::GotHi: return "MipsISD::GotHi";
177  case MipsISD::TlsHi: return "MipsISD::TlsHi";
178  case MipsISD::GPRel: return "MipsISD::GPRel";
179  case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
180  case MipsISD::Ret: return "MipsISD::Ret";
181  case MipsISD::ERet: return "MipsISD::ERet";
182  case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
183  case MipsISD::FAbs: return "MipsISD::FAbs";
184  case MipsISD::FMS: return "MipsISD::FMS";
185  case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
186  case MipsISD::FPCmp: return "MipsISD::FPCmp";
187  case MipsISD::FSELECT: return "MipsISD::FSELECT";
188  case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
189  case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
190  case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
191  case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
192  case MipsISD::MFHI: return "MipsISD::MFHI";
193  case MipsISD::MFLO: return "MipsISD::MFLO";
194  case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
195  case MipsISD::Mult: return "MipsISD::Mult";
196  case MipsISD::Multu: return "MipsISD::Multu";
197  case MipsISD::MAdd: return "MipsISD::MAdd";
198  case MipsISD::MAddu: return "MipsISD::MAddu";
199  case MipsISD::MSub: return "MipsISD::MSub";
200  case MipsISD::MSubu: return "MipsISD::MSubu";
201  case MipsISD::DivRem: return "MipsISD::DivRem";
202  case MipsISD::DivRemU: return "MipsISD::DivRemU";
203  case MipsISD::DivRem16: return "MipsISD::DivRem16";
204  case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
205  case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
206  case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
207  case MipsISD::Wrapper: return "MipsISD::Wrapper";
208  case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
209  case MipsISD::Sync: return "MipsISD::Sync";
210  case MipsISD::Ext: return "MipsISD::Ext";
211  case MipsISD::Ins: return "MipsISD::Ins";
212  case MipsISD::CIns: return "MipsISD::CIns";
213  case MipsISD::LWL: return "MipsISD::LWL";
214  case MipsISD::LWR: return "MipsISD::LWR";
215  case MipsISD::SWL: return "MipsISD::SWL";
216  case MipsISD::SWR: return "MipsISD::SWR";
217  case MipsISD::LDL: return "MipsISD::LDL";
218  case MipsISD::LDR: return "MipsISD::LDR";
219  case MipsISD::SDL: return "MipsISD::SDL";
220  case MipsISD::SDR: return "MipsISD::SDR";
221  case MipsISD::EXTP: return "MipsISD::EXTP";
222  case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
223  case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
224  case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
225  case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
226  case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
227  case MipsISD::SHILO: return "MipsISD::SHILO";
228  case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
229  case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
230  case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
231  case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
232  case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
233  case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
234  case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
235  case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
236  case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
237  case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
238  case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
239  case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
240  case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
241  case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
242  case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
243  case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
244  case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
245  case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
246  case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
247  case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
248  case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
249  case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
250  case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
251  case MipsISD::MULT: return "MipsISD::MULT";
252  case MipsISD::MULTU: return "MipsISD::MULTU";
253  case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
254  case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
255  case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
256  case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
257  case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
258  case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
259  case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
260  case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
261  case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
262  case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
263  case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
264  case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
265  case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
266  case MipsISD::VCEQ: return "MipsISD::VCEQ";
267  case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
268  case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
269  case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
270  case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
271  case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
272  case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
273  case MipsISD::VNOR: return "MipsISD::VNOR";
274  case MipsISD::VSHF: return "MipsISD::VSHF";
275  case MipsISD::SHF: return "MipsISD::SHF";
276  case MipsISD::ILVEV: return "MipsISD::ILVEV";
277  case MipsISD::ILVOD: return "MipsISD::ILVOD";
278  case MipsISD::ILVL: return "MipsISD::ILVL";
279  case MipsISD::ILVR: return "MipsISD::ILVR";
280  case MipsISD::PCKEV: return "MipsISD::PCKEV";
281  case MipsISD::PCKOD: return "MipsISD::PCKOD";
282  case MipsISD::INSVE: return "MipsISD::INSVE";
283  }
284  return nullptr;
285 }
286 
288  const MipsSubtarget &STI)
289  : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
290  // Mips does not have i1 type, so use i32 for
291  // setcc operations results (slt, sgt, ...).
294  // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
295  // does. Integer booleans still use 0 and 1.
296  if (Subtarget.hasMips32r6())
299 
300  // Load extented operations for i1 types must be promoted
301  for (MVT VT : MVT::integer_valuetypes()) {
305  }
306 
307  // MIPS doesn't have extending float->double load/store. Set LoadExtAction
308  // for f32, f16
309  for (MVT VT : MVT::fp_valuetypes()) {
312  }
313 
314  // Set LoadExtAction for f16 vectors to Expand
316  MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
317  if (F16VT.isValid())
318  setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
319  }
320 
323 
325 
326  // Used by legalize types to correctly generate the setcc result.
327  // Without this, every float setcc comes with a AND/OR with the result,
328  // we don't want this, since the fpcmp result goes to a flag register,
329  // which is used implicitly by brcond and select operations.
331 
332  // Mips Custom Operations
350 
351  if (Subtarget.isGP64bit()) {
364  }
365 
366  if (!Subtarget.isGP64bit()) {
370  }
371 
373  if (Subtarget.isGP64bit())
375 
384 
385  // Operations not directly supported by Mips.
399  if (Subtarget.hasCnMips()) {
402  } else {
405  }
412 
413  if (!Subtarget.hasMips32r2())
415 
416  if (!Subtarget.hasMips64r2())
418 
435 
436  // Lower f16 conversion operations into library calls
441 
443 
448 
449  // Use the default for now
452 
453  if (!Subtarget.isGP64bit()) {
456  }
457 
458  if (!Subtarget.hasMips32r2()) {
461  }
462 
463  // MIPS16 lacks MIPS32's clz and clo instructions.
466  if (!Subtarget.hasMips64())
468 
469  if (!Subtarget.hasMips32r2())
471  if (!Subtarget.hasMips64r2())
473 
474  if (Subtarget.isGP64bit()) {
479  }
480 
482 
485 
486  if (ABI.IsO32()) {
487  // These libcalls are not available in 32-bit.
488  setLibcallName(RTLIB::SHL_I128, nullptr);
489  setLibcallName(RTLIB::SRL_I128, nullptr);
490  setLibcallName(RTLIB::SRA_I128, nullptr);
491  setLibcallName(RTLIB::MUL_I128, nullptr);
492  setLibcallName(RTLIB::MULO_I64, nullptr);
493  setLibcallName(RTLIB::MULO_I128, nullptr);
494  }
495 
497 
498  // The arguments on the stack are defined in terms of 4-byte slots on O32
499  // and 8-byte slots on N32/N64.
501  : Align(4));
502 
503  setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
504 
505  MaxStoresPerMemcpy = 16;
506 
507  isMicroMips = Subtarget.inMicroMipsMode();
508 }
509 
510 const MipsTargetLowering *
512  const MipsSubtarget &STI) {
513  if (STI.inMips16Mode())
514  return createMips16TargetLowering(TM, STI);
515 
516  return createMipsSETargetLowering(TM, STI);
517 }
518 
519 // Create a fast isel object.
520 FastISel *
522  const TargetLibraryInfo *libInfo) const {
523  const MipsTargetMachine &TM =
524  static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
525 
526  // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
527  bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
530 
531  // Disable if either of the following is true:
532  // We do not generate PIC, the ABI is not O32, XGOT is being used.
533  if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
534  Subtarget.useXGOT())
535  UseFastISel = false;
536 
537  return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
538 }
539 
541  EVT VT) const {
542  if (!VT.isVector())
543  return MVT::i32;
545 }
546 
549  const MipsSubtarget &Subtarget) {
550  if (DCI.isBeforeLegalizeOps())
551  return SDValue();
552 
553  EVT Ty = N->getValueType(0);
554  unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
555  unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
556  unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
558  SDLoc DL(N);
559 
560  SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
561  N->getOperand(0), N->getOperand(1));
562  SDValue InChain = DAG.getEntryNode();
563  SDValue InGlue = DivRem;
564 
565  // insert MFLO
566  if (N->hasAnyUseOfValue(0)) {
567  SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
568  InGlue);
569  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
570  InChain = CopyFromLo.getValue(1);
571  InGlue = CopyFromLo.getValue(2);
572  }
573 
574  // insert MFHI
575  if (N->hasAnyUseOfValue(1)) {
576  SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
577  HI, Ty, InGlue);
578  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
579  }
580 
581  return SDValue();
582 }
583 
585  switch (CC) {
586  default: llvm_unreachable("Unknown fp condition code!");
587  case ISD::SETEQ:
588  case ISD::SETOEQ: return Mips::FCOND_OEQ;
589  case ISD::SETUNE: return Mips::FCOND_UNE;
590  case ISD::SETLT:
591  case ISD::SETOLT: return Mips::FCOND_OLT;
592  case ISD::SETGT:
593  case ISD::SETOGT: return Mips::FCOND_OGT;
594  case ISD::SETLE:
595  case ISD::SETOLE: return Mips::FCOND_OLE;
596  case ISD::SETGE:
597  case ISD::SETOGE: return Mips::FCOND_OGE;
598  case ISD::SETULT: return Mips::FCOND_ULT;
599  case ISD::SETULE: return Mips::FCOND_ULE;
600  case ISD::SETUGT: return Mips::FCOND_UGT;
601  case ISD::SETUGE: return Mips::FCOND_UGE;
602  case ISD::SETUO: return Mips::FCOND_UN;
603  case ISD::SETO: return Mips::FCOND_OR;
604  case ISD::SETNE:
605  case ISD::SETONE: return Mips::FCOND_ONE;
606  case ISD::SETUEQ: return Mips::FCOND_UEQ;
607  }
608 }
609 
610 /// This function returns true if the floating point conditional branches and
611 /// conditional moves which use condition code CC should be inverted.
613  if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
614  return false;
615 
616  assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
617  "Illegal Condition Code");
618 
619  return true;
620 }
621 
622 // Creates and returns an FPCmp node from a setcc node.
623 // Returns Op if setcc is not a floating point comparison.
624 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
625  // must be a SETCC node
626  if (Op.getOpcode() != ISD::SETCC)
627  return Op;
628 
629  SDValue LHS = Op.getOperand(0);
630 
631  if (!LHS.getValueType().isFloatingPoint())
632  return Op;
633 
634  SDValue RHS = Op.getOperand(1);
635  SDLoc DL(Op);
636 
637  // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
638  // node if necessary.
639  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
640 
641  return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
642  DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
643 }
644 
645 // Creates and returns a CMovFPT/F node.
647  SDValue False, const SDLoc &DL) {
648  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
649  bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
650  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
651 
652  return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
653  True.getValueType(), True, FCC0, False, Cond);
654 }
655 
658  const MipsSubtarget &Subtarget) {
659  if (DCI.isBeforeLegalizeOps())
660  return SDValue();
661 
662  SDValue SetCC = N->getOperand(0);
663 
664  if ((SetCC.getOpcode() != ISD::SETCC) ||
665  !SetCC.getOperand(0).getValueType().isInteger())
666  return SDValue();
667 
668  SDValue False = N->getOperand(2);
669  EVT FalseTy = False.getValueType();
670 
671  if (!FalseTy.isInteger())
672  return SDValue();
673 
674  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
675 
676  // If the RHS (False) is 0, we swap the order of the operands
677  // of ISD::SELECT (obviously also inverting the condition) so that we can
678  // take advantage of conditional moves using the $0 register.
679  // Example:
680  // return (a != 0) ? x : 0;
681  // load $reg, x
682  // movz $reg, $0, a
683  if (!FalseC)
684  return SDValue();
685 
686  const SDLoc DL(N);
687 
688  if (!FalseC->getZExtValue()) {
689  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
690  SDValue True = N->getOperand(1);
691 
692  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
693  SetCC.getOperand(1),
694  ISD::getSetCCInverse(CC, SetCC.getValueType()));
695 
696  return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
697  }
698 
699  // If both operands are integer constants there's a possibility that we
700  // can do some interesting optimizations.
701  SDValue True = N->getOperand(1);
702  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
703 
704  if (!TrueC || !True.getValueType().isInteger())
705  return SDValue();
706 
707  // We'll also ignore MVT::i64 operands as this optimizations proves
708  // to be ineffective because of the required sign extensions as the result
709  // of a SETCC operator is always MVT::i32 for non-vector types.
710  if (True.getValueType() == MVT::i64)
711  return SDValue();
712 
713  int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
714 
715  // 1) (a < x) ? y : y-1
716  // slti $reg1, a, x
717  // addiu $reg2, $reg1, y-1
718  if (Diff == 1)
719  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
720 
721  // 2) (a < x) ? y-1 : y
722  // slti $reg1, a, x
723  // xor $reg1, $reg1, 1
724  // addiu $reg2, $reg1, y-1
725  if (Diff == -1) {
726  ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
727  SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
728  SetCC.getOperand(1),
729  ISD::getSetCCInverse(CC, SetCC.getValueType()));
730  return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
731  }
732 
733  // Could not optimize.
734  return SDValue();
735 }
736 
739  const MipsSubtarget &Subtarget) {
740  if (DCI.isBeforeLegalizeOps())
741  return SDValue();
742 
743  SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
744 
745  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
746  if (!FalseC || FalseC->getZExtValue())
747  return SDValue();
748 
749  // Since RHS (False) is 0, we swap the order of the True/False operands
750  // (obviously also inverting the condition) so that we can
751  // take advantage of conditional moves using the $0 register.
752  // Example:
753  // return (a != 0) ? x : 0;
754  // load $reg, x
755  // movz $reg, $0, a
756  unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
758 
759  SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
760  return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
761  ValueIfFalse, FCC, ValueIfTrue, Glue);
762 }
763 
766  const MipsSubtarget &Subtarget) {
767  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
768  return SDValue();
769 
770  SDValue FirstOperand = N->getOperand(0);
771  unsigned FirstOperandOpc = FirstOperand.getOpcode();
772  SDValue Mask = N->getOperand(1);
773  EVT ValTy = N->getValueType(0);
774  SDLoc DL(N);
775 
776  uint64_t Pos = 0;
777  unsigned SMPos, SMSize;
778  ConstantSDNode *CN;
779  SDValue NewOperand;
780  unsigned Opc;
781 
782  // Op's second operand must be a shifted mask.
783  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
784  !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
785  return SDValue();
786 
787  if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
788  // Pattern match EXT.
789  // $dst = and ((sra or srl) $src , pos), (2**size - 1)
790  // => ext $dst, $src, pos, size
791 
792  // The second operand of the shift must be an immediate.
793  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
794  return SDValue();
795 
796  Pos = CN->getZExtValue();
797 
798  // Return if the shifted mask does not start at bit 0 or the sum of its size
799  // and Pos exceeds the word's size.
800  if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
801  return SDValue();
802 
803  Opc = MipsISD::Ext;
804  NewOperand = FirstOperand.getOperand(0);
805  } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
806  // Pattern match CINS.
807  // $dst = and (shl $src , pos), mask
808  // => cins $dst, $src, pos, size
809  // mask is a shifted mask with consecutive 1's, pos = shift amount,
810  // size = population count.
811 
812  // The second operand of the shift must be an immediate.
813  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
814  return SDValue();
815 
816  Pos = CN->getZExtValue();
817 
818  if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
819  Pos + SMSize > ValTy.getSizeInBits())
820  return SDValue();
821 
822  NewOperand = FirstOperand.getOperand(0);
823  // SMSize is 'location' (position) in this case, not size.
824  SMSize--;
825  Opc = MipsISD::CIns;
826  } else {
827  // Pattern match EXT.
828  // $dst = and $src, (2**size - 1) , if size > 16
829  // => ext $dst, $src, pos, size , pos = 0
830 
831  // If the mask is <= 0xffff, andi can be used instead.
832  if (CN->getZExtValue() <= 0xffff)
833  return SDValue();
834 
835  // Return if the mask doesn't start at position 0.
836  if (SMPos)
837  return SDValue();
838 
839  Opc = MipsISD::Ext;
840  NewOperand = FirstOperand;
841  }
842  return DAG.getNode(Opc, DL, ValTy, NewOperand,
843  DAG.getConstant(Pos, DL, MVT::i32),
844  DAG.getConstant(SMSize, DL, MVT::i32));
845 }
846 
849  const MipsSubtarget &Subtarget) {
850  // Pattern match INS.
851  // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
852  // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
853  // => ins $dst, $src, size, pos, $src1
854  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
855  return SDValue();
856 
857  SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
858  unsigned SMPos0, SMSize0, SMPos1, SMSize1;
859  ConstantSDNode *CN, *CN1;
860 
861  // See if Op's first operand matches (and $src1 , mask0).
862  if (And0.getOpcode() != ISD::AND)
863  return SDValue();
864 
865  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
866  !isShiftedMask_64(~CN->getSExtValue(), SMPos0, SMSize0))
867  return SDValue();
868 
869  // See if Op's second operand matches (and (shl $src, pos), mask1).
870  if (And1.getOpcode() == ISD::AND &&
871  And1.getOperand(0).getOpcode() == ISD::SHL) {
872 
873  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
874  !isShiftedMask_64(CN->getZExtValue(), SMPos1, SMSize1))
875  return SDValue();
876 
877  // The shift masks must have the same position and size.
878  if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
879  return SDValue();
880 
881  SDValue Shl = And1.getOperand(0);
882 
883  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
884  return SDValue();
885 
886  unsigned Shamt = CN->getZExtValue();
887 
888  // Return if the shift amount and the first bit position of mask are not the
889  // same.
890  EVT ValTy = N->getValueType(0);
891  if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
892  return SDValue();
893 
894  SDLoc DL(N);
895  return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
896  DAG.getConstant(SMPos0, DL, MVT::i32),
897  DAG.getConstant(SMSize0, DL, MVT::i32),
898  And0.getOperand(0));
899  } else {
900  // Pattern match DINS.
901  // $dst = or (and $src, mask0), mask1
902  // where mask0 = ((1 << SMSize0) -1) << SMPos0
903  // => dins $dst, $src, pos, size
904  if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
905  ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
906  (SMSize0 + SMPos0 <= 32))) {
907  // Check if AND instruction has constant as argument
908  bool isConstCase = And1.getOpcode() != ISD::AND;
909  if (And1.getOpcode() == ISD::AND) {
910  if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
911  return SDValue();
912  } else {
913  if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
914  return SDValue();
915  }
916  // Don't generate INS if constant OR operand doesn't fit into bits
917  // cleared by constant AND operand.
918  if (CN->getSExtValue() & CN1->getSExtValue())
919  return SDValue();
920 
921  SDLoc DL(N);
922  EVT ValTy = N->getOperand(0)->getValueType(0);
923  SDValue Const1;
924  SDValue SrlX;
925  if (!isConstCase) {
926  Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
927  SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
928  }
929  return DAG.getNode(
930  MipsISD::Ins, DL, N->getValueType(0),
931  isConstCase
932  ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
933  : SrlX,
934  DAG.getConstant(SMPos0, DL, MVT::i32),
935  DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
936  : SMSize0,
937  DL, MVT::i32),
938  And0->getOperand(0));
939 
940  }
941  return SDValue();
942  }
943 }
944 
946  const MipsSubtarget &Subtarget) {
947  // ROOTNode must have a multiplication as an operand for the match to be
948  // successful.
949  if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
950  ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
951  return SDValue();
952 
953  // In the case where we have a multiplication as the left operand of
954  // of a subtraction, we can't combine into a MipsISD::MSub node as the
955  // the instruction definition of msub(u) places the multiplication on
956  // on the right.
957  if (ROOTNode->getOpcode() == ISD::SUB &&
958  ROOTNode->getOperand(0).getOpcode() == ISD::MUL)
959  return SDValue();
960 
961  // We don't handle vector types here.
962  if (ROOTNode->getValueType(0).isVector())
963  return SDValue();
964 
965  // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
966  // arithmetic. E.g.
967  // (add (mul a b) c) =>
968  // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
969  // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
970  // or
971  // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
972  //
973  // The overhead of setting up the Hi/Lo registers and reassembling the
974  // result makes this a dubious optimzation for MIPS64. The core of the
975  // problem is that Hi/Lo contain the upper and lower 32 bits of the
976  // operand and result.
977  //
978  // It requires a chain of 4 add/mul for MIPS64R2 to get better code
979  // density than doing it naively, 5 for MIPS64. Additionally, using
980  // madd/msub on MIPS64 requires the operands actually be 32 bit sign
981  // extended operands, not true 64 bit values.
982  //
983  // FIXME: For the moment, disable this completely for MIPS64.
984  if (Subtarget.hasMips64())
985  return SDValue();
986 
987  SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
988  ? ROOTNode->getOperand(0)
989  : ROOTNode->getOperand(1);
990 
991  SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
992  ? ROOTNode->getOperand(1)
993  : ROOTNode->getOperand(0);
994 
995  // Transform this to a MADD only if the user of this node is the add.
996  // If there are other users of the mul, this function returns here.
997  if (!Mult.hasOneUse())
998  return SDValue();
999 
1000  // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1001  // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1002  // of the multiply must have 32 or more sign bits, otherwise we cannot
1003  // perform this optimization. We have to check this here as we're performing
1004  // this optimization pre-legalization.
1005  SDValue MultLHS = Mult->getOperand(0);
1006  SDValue MultRHS = Mult->getOperand(1);
1007 
1008  bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1009  MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1010  bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1011  MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1012 
1013  if (!IsSigned && !IsUnsigned)
1014  return SDValue();
1015 
1016  // Initialize accumulator.
1017  SDLoc DL(ROOTNode);
1018  SDValue TopHalf;
1019  SDValue BottomHalf;
1020  BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1021  CurDAG.getIntPtrConstant(0, DL));
1022 
1023  TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1024  CurDAG.getIntPtrConstant(1, DL));
1025  SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1026  BottomHalf,
1027  TopHalf);
1028 
1029  // Create MipsMAdd(u) / MipsMSub(u) node.
1030  bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1031  unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1032  : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1033  SDValue MAddOps[3] = {
1034  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1035  CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1036  EVT VTs[2] = {MVT::i32, MVT::i32};
1037  SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1038 
1039  SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1040  SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1041  SDValue Combined =
1042  CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1043  return Combined;
1044 }
1045 
1048  const MipsSubtarget &Subtarget) {
1049  // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1050  if (DCI.isBeforeLegalizeOps()) {
1051  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1052  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1053  return performMADD_MSUBCombine(N, DAG, Subtarget);
1054 
1055  return SDValue();
1056  }
1057 
1058  return SDValue();
1059 }
1060 
1063  const MipsSubtarget &Subtarget) {
1064  // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1065  if (DCI.isBeforeLegalizeOps()) {
1066  if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1067  !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1068  return performMADD_MSUBCombine(N, DAG, Subtarget);
1069 
1070  return SDValue();
1071  }
1072 
1073  // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1074  SDValue Add = N->getOperand(1);
1075 
1076  if (Add.getOpcode() != ISD::ADD)
1077  return SDValue();
1078 
1079  SDValue Lo = Add.getOperand(1);
1080 
1081  if ((Lo.getOpcode() != MipsISD::Lo) ||
1082  (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1083  return SDValue();
1084 
1085  EVT ValTy = N->getValueType(0);
1086  SDLoc DL(N);
1087 
1088  SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1089  Add.getOperand(0));
1090  return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1091 }
1092 
1095  const MipsSubtarget &Subtarget) {
1096  // Pattern match CINS.
1097  // $dst = shl (and $src , imm), pos
1098  // => cins $dst, $src, pos, size
1099 
1100  if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1101  return SDValue();
1102 
1103  SDValue FirstOperand = N->getOperand(0);
1104  unsigned FirstOperandOpc = FirstOperand.getOpcode();
1105  SDValue SecondOperand = N->getOperand(1);
1106  EVT ValTy = N->getValueType(0);
1107  SDLoc DL(N);
1108 
1109  uint64_t Pos = 0;
1110  unsigned SMPos, SMSize;
1111  ConstantSDNode *CN;
1112  SDValue NewOperand;
1113 
1114  // The second operand of the shift must be an immediate.
1115  if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1116  return SDValue();
1117 
1118  Pos = CN->getZExtValue();
1119 
1120  if (Pos >= ValTy.getSizeInBits())
1121  return SDValue();
1122 
1123  if (FirstOperandOpc != ISD::AND)
1124  return SDValue();
1125 
1126  // AND's second operand must be a shifted mask.
1127  if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1128  !isShiftedMask_64(CN->getZExtValue(), SMPos, SMSize))
1129  return SDValue();
1130 
1131  // Return if the shifted mask does not start at bit 0 or the sum of its size
1132  // and Pos exceeds the word's size.
1133  if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1134  return SDValue();
1135 
1136  NewOperand = FirstOperand.getOperand(0);
1137  // SMSize is 'location' (position) in this case, not size.
1138  SMSize--;
1139 
1140  return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1141  DAG.getConstant(Pos, DL, MVT::i32),
1142  DAG.getConstant(SMSize, DL, MVT::i32));
1143 }
1144 
1146  const {
1147  SelectionDAG &DAG = DCI.DAG;
1148  unsigned Opc = N->getOpcode();
1149 
1150  switch (Opc) {
1151  default: break;
1152  case ISD::SDIVREM:
1153  case ISD::UDIVREM:
1154  return performDivRemCombine(N, DAG, DCI, Subtarget);
1155  case ISD::SELECT:
1156  return performSELECTCombine(N, DAG, DCI, Subtarget);
1157  case MipsISD::CMovFP_F:
1158  case MipsISD::CMovFP_T:
1159  return performCMovFPCombine(N, DAG, DCI, Subtarget);
1160  case ISD::AND:
1161  return performANDCombine(N, DAG, DCI, Subtarget);
1162  case ISD::OR:
1163  return performORCombine(N, DAG, DCI, Subtarget);
1164  case ISD::ADD:
1165  return performADDCombine(N, DAG, DCI, Subtarget);
1166  case ISD::SHL:
1167  return performSHLCombine(N, DAG, DCI, Subtarget);
1168  case ISD::SUB:
1169  return performSUBCombine(N, DAG, DCI, Subtarget);
1170  }
1171 
1172  return SDValue();
1173 }
1174 
1176  return Subtarget.hasMips32();
1177 }
1178 
1180  return Subtarget.hasMips32();
1181 }
1182 
1184  // We can use ANDI+SLTIU as a bit test. Y contains the bit position.
1185  // For MIPSR2 or later, we may be able to use the `ext` instruction or its'
1186  // double-word variants.
1187  if (auto *C = dyn_cast<ConstantSDNode>(Y))
1188  return C->getAPIntValue().ule(15);
1189 
1190  return false;
1191 }
1192 
1194  const SDNode *N, CombineLevel Level) const {
1195  if (N->getOperand(0).getValueType().isVector())
1196  return false;
1197  return true;
1198 }
1199 
1200 void
1203  SelectionDAG &DAG) const {
1204  return LowerOperationWrapper(N, Results, DAG);
1205 }
1206 
1209 {
1210  switch (Op.getOpcode())
1211  {
1212  case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1213  case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1214  case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1215  case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1216  case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1217  case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1218  case ISD::SELECT: return lowerSELECT(Op, DAG);
1219  case ISD::SETCC: return lowerSETCC(Op, DAG);
1220  case ISD::VASTART: return lowerVASTART(Op, DAG);
1221  case ISD::VAARG: return lowerVAARG(Op, DAG);
1222  case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1223  case ISD::FABS: return lowerFABS(Op, DAG);
1224  case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1225  case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1226  case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1227  case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1228  case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1229  case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1230  case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1231  case ISD::LOAD: return lowerLOAD(Op, DAG);
1232  case ISD::STORE: return lowerSTORE(Op, DAG);
1233  case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1234  case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1235  }
1236  return SDValue();
1237 }
1238 
1239 //===----------------------------------------------------------------------===//
1240 // Lower helper functions
1241 //===----------------------------------------------------------------------===//
1242 
1243 // addLiveIn - This helper function adds the specified physical register to the
1244 // MachineFunction as a live in value. It also creates a corresponding
1245 // virtual register for it.
1246 static unsigned
1247 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1248 {
1249  Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1250  MF.getRegInfo().addLiveIn(PReg, VReg);
1251  return VReg;
1252 }
1253 
1256  const TargetInstrInfo &TII,
1257  bool Is64Bit, bool IsMicroMips) {
1258  if (NoZeroDivCheck)
1259  return &MBB;
1260 
1261  // Insert instruction "teq $divisor_reg, $zero, 7".
1263  MachineInstrBuilder MIB;
1264  MachineOperand &Divisor = MI.getOperand(2);
1265  MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1266  TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1267  .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1268  .addReg(Mips::ZERO)
1269  .addImm(7);
1270 
1271  // Use the 32-bit sub-register if this is a 64-bit division.
1272  if (Is64Bit)
1273  MIB->getOperand(0).setSubReg(Mips::sub_32);
1274 
1275  // Clear Divisor's kill flag.
1276  Divisor.setIsKill(false);
1277 
1278  // We would normally delete the original instruction here but in this case
1279  // we only needed to inject an additional instruction rather than replace it.
1280 
1281  return &MBB;
1282 }
1283 
1286  MachineBasicBlock *BB) const {
1287  switch (MI.getOpcode()) {
1288  default:
1289  llvm_unreachable("Unexpected instr type to insert");
1290  case Mips::ATOMIC_LOAD_ADD_I8:
1291  return emitAtomicBinaryPartword(MI, BB, 1);
1292  case Mips::ATOMIC_LOAD_ADD_I16:
1293  return emitAtomicBinaryPartword(MI, BB, 2);
1294  case Mips::ATOMIC_LOAD_ADD_I32:
1295  return emitAtomicBinary(MI, BB);
1296  case Mips::ATOMIC_LOAD_ADD_I64:
1297  return emitAtomicBinary(MI, BB);
1298 
1299  case Mips::ATOMIC_LOAD_AND_I8:
1300  return emitAtomicBinaryPartword(MI, BB, 1);
1301  case Mips::ATOMIC_LOAD_AND_I16:
1302  return emitAtomicBinaryPartword(MI, BB, 2);
1303  case Mips::ATOMIC_LOAD_AND_I32:
1304  return emitAtomicBinary(MI, BB);
1305  case Mips::ATOMIC_LOAD_AND_I64:
1306  return emitAtomicBinary(MI, BB);
1307 
1308  case Mips::ATOMIC_LOAD_OR_I8:
1309  return emitAtomicBinaryPartword(MI, BB, 1);
1310  case Mips::ATOMIC_LOAD_OR_I16:
1311  return emitAtomicBinaryPartword(MI, BB, 2);
1312  case Mips::ATOMIC_LOAD_OR_I32:
1313  return emitAtomicBinary(MI, BB);
1314  case Mips::ATOMIC_LOAD_OR_I64:
1315  return emitAtomicBinary(MI, BB);
1316 
1317  case Mips::ATOMIC_LOAD_XOR_I8:
1318  return emitAtomicBinaryPartword(MI, BB, 1);
1319  case Mips::ATOMIC_LOAD_XOR_I16:
1320  return emitAtomicBinaryPartword(MI, BB, 2);
1321  case Mips::ATOMIC_LOAD_XOR_I32:
1322  return emitAtomicBinary(MI, BB);
1323  case Mips::ATOMIC_LOAD_XOR_I64:
1324  return emitAtomicBinary(MI, BB);
1325 
1326  case Mips::ATOMIC_LOAD_NAND_I8:
1327  return emitAtomicBinaryPartword(MI, BB, 1);
1328  case Mips::ATOMIC_LOAD_NAND_I16:
1329  return emitAtomicBinaryPartword(MI, BB, 2);
1330  case Mips::ATOMIC_LOAD_NAND_I32:
1331  return emitAtomicBinary(MI, BB);
1332  case Mips::ATOMIC_LOAD_NAND_I64:
1333  return emitAtomicBinary(MI, BB);
1334 
1335  case Mips::ATOMIC_LOAD_SUB_I8:
1336  return emitAtomicBinaryPartword(MI, BB, 1);
1337  case Mips::ATOMIC_LOAD_SUB_I16:
1338  return emitAtomicBinaryPartword(MI, BB, 2);
1339  case Mips::ATOMIC_LOAD_SUB_I32:
1340  return emitAtomicBinary(MI, BB);
1341  case Mips::ATOMIC_LOAD_SUB_I64:
1342  return emitAtomicBinary(MI, BB);
1343 
1344  case Mips::ATOMIC_SWAP_I8:
1345  return emitAtomicBinaryPartword(MI, BB, 1);
1346  case Mips::ATOMIC_SWAP_I16:
1347  return emitAtomicBinaryPartword(MI, BB, 2);
1348  case Mips::ATOMIC_SWAP_I32:
1349  return emitAtomicBinary(MI, BB);
1350  case Mips::ATOMIC_SWAP_I64:
1351  return emitAtomicBinary(MI, BB);
1352 
1353  case Mips::ATOMIC_CMP_SWAP_I8:
1354  return emitAtomicCmpSwapPartword(MI, BB, 1);
1355  case Mips::ATOMIC_CMP_SWAP_I16:
1356  return emitAtomicCmpSwapPartword(MI, BB, 2);
1357  case Mips::ATOMIC_CMP_SWAP_I32:
1358  return emitAtomicCmpSwap(MI, BB);
1359  case Mips::ATOMIC_CMP_SWAP_I64:
1360  return emitAtomicCmpSwap(MI, BB);
1361 
1362  case Mips::ATOMIC_LOAD_MIN_I8:
1363  return emitAtomicBinaryPartword(MI, BB, 1);
1364  case Mips::ATOMIC_LOAD_MIN_I16:
1365  return emitAtomicBinaryPartword(MI, BB, 2);
1366  case Mips::ATOMIC_LOAD_MIN_I32:
1367  return emitAtomicBinary(MI, BB);
1368  case Mips::ATOMIC_LOAD_MIN_I64:
1369  return emitAtomicBinary(MI, BB);
1370 
1371  case Mips::ATOMIC_LOAD_MAX_I8:
1372  return emitAtomicBinaryPartword(MI, BB, 1);
1373  case Mips::ATOMIC_LOAD_MAX_I16:
1374  return emitAtomicBinaryPartword(MI, BB, 2);
1375  case Mips::ATOMIC_LOAD_MAX_I32:
1376  return emitAtomicBinary(MI, BB);
1377  case Mips::ATOMIC_LOAD_MAX_I64:
1378  return emitAtomicBinary(MI, BB);
1379 
1380  case Mips::ATOMIC_LOAD_UMIN_I8:
1381  return emitAtomicBinaryPartword(MI, BB, 1);
1382  case Mips::ATOMIC_LOAD_UMIN_I16:
1383  return emitAtomicBinaryPartword(MI, BB, 2);
1384  case Mips::ATOMIC_LOAD_UMIN_I32:
1385  return emitAtomicBinary(MI, BB);
1386  case Mips::ATOMIC_LOAD_UMIN_I64:
1387  return emitAtomicBinary(MI, BB);
1388 
1389  case Mips::ATOMIC_LOAD_UMAX_I8:
1390  return emitAtomicBinaryPartword(MI, BB, 1);
1391  case Mips::ATOMIC_LOAD_UMAX_I16:
1392  return emitAtomicBinaryPartword(MI, BB, 2);
1393  case Mips::ATOMIC_LOAD_UMAX_I32:
1394  return emitAtomicBinary(MI, BB);
1395  case Mips::ATOMIC_LOAD_UMAX_I64:
1396  return emitAtomicBinary(MI, BB);
1397 
1398  case Mips::PseudoSDIV:
1399  case Mips::PseudoUDIV:
1400  case Mips::DIV:
1401  case Mips::DIVU:
1402  case Mips::MOD:
1403  case Mips::MODU:
1404  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1405  false);
1406  case Mips::SDIV_MM_Pseudo:
1407  case Mips::UDIV_MM_Pseudo:
1408  case Mips::SDIV_MM:
1409  case Mips::UDIV_MM:
1410  case Mips::DIV_MMR6:
1411  case Mips::DIVU_MMR6:
1412  case Mips::MOD_MMR6:
1413  case Mips::MODU_MMR6:
1414  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1415  case Mips::PseudoDSDIV:
1416  case Mips::PseudoDUDIV:
1417  case Mips::DDIV:
1418  case Mips::DDIVU:
1419  case Mips::DMOD:
1420  case Mips::DMODU:
1421  return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1422 
1423  case Mips::PseudoSELECT_I:
1424  case Mips::PseudoSELECT_I64:
1425  case Mips::PseudoSELECT_S:
1426  case Mips::PseudoSELECT_D32:
1427  case Mips::PseudoSELECT_D64:
1428  return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1429  case Mips::PseudoSELECTFP_F_I:
1430  case Mips::PseudoSELECTFP_F_I64:
1431  case Mips::PseudoSELECTFP_F_S:
1432  case Mips::PseudoSELECTFP_F_D32:
1433  case Mips::PseudoSELECTFP_F_D64:
1434  return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1435  case Mips::PseudoSELECTFP_T_I:
1436  case Mips::PseudoSELECTFP_T_I64:
1437  case Mips::PseudoSELECTFP_T_S:
1438  case Mips::PseudoSELECTFP_T_D32:
1439  case Mips::PseudoSELECTFP_T_D64:
1440  return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1441  case Mips::PseudoD_SELECT_I:
1442  case Mips::PseudoD_SELECT_I64:
1443  return emitPseudoD_SELECT(MI, BB);
1444  case Mips::LDR_W:
1445  return emitLDR_W(MI, BB);
1446  case Mips::LDR_D:
1447  return emitLDR_D(MI, BB);
1448  case Mips::STR_W:
1449  return emitSTR_W(MI, BB);
1450  case Mips::STR_D:
1451  return emitSTR_D(MI, BB);
1452  }
1453 }
1454 
1455 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1456 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1458 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1459  MachineBasicBlock *BB) const {
1460 
1461  MachineFunction *MF = BB->getParent();
1462  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1464  DebugLoc DL = MI.getDebugLoc();
1465 
1466  unsigned AtomicOp;
1467  bool NeedsAdditionalReg = false;
1468  switch (MI.getOpcode()) {
1469  case Mips::ATOMIC_LOAD_ADD_I32:
1470  AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1471  break;
1472  case Mips::ATOMIC_LOAD_SUB_I32:
1473  AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1474  break;
1475  case Mips::ATOMIC_LOAD_AND_I32:
1476  AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1477  break;
1478  case Mips::ATOMIC_LOAD_OR_I32:
1479  AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1480  break;
1481  case Mips::ATOMIC_LOAD_XOR_I32:
1482  AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1483  break;
1484  case Mips::ATOMIC_LOAD_NAND_I32:
1485  AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1486  break;
1487  case Mips::ATOMIC_SWAP_I32:
1488  AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1489  break;
1490  case Mips::ATOMIC_LOAD_ADD_I64:
1491  AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1492  break;
1493  case Mips::ATOMIC_LOAD_SUB_I64:
1494  AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1495  break;
1496  case Mips::ATOMIC_LOAD_AND_I64:
1497  AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1498  break;
1499  case Mips::ATOMIC_LOAD_OR_I64:
1500  AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1501  break;
1502  case Mips::ATOMIC_LOAD_XOR_I64:
1503  AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1504  break;
1505  case Mips::ATOMIC_LOAD_NAND_I64:
1506  AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1507  break;
1508  case Mips::ATOMIC_SWAP_I64:
1509  AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1510  break;
1511  case Mips::ATOMIC_LOAD_MIN_I32:
1512  AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA;
1513  NeedsAdditionalReg = true;
1514  break;
1515  case Mips::ATOMIC_LOAD_MAX_I32:
1516  AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA;
1517  NeedsAdditionalReg = true;
1518  break;
1519  case Mips::ATOMIC_LOAD_UMIN_I32:
1520  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA;
1521  NeedsAdditionalReg = true;
1522  break;
1523  case Mips::ATOMIC_LOAD_UMAX_I32:
1524  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA;
1525  NeedsAdditionalReg = true;
1526  break;
1527  case Mips::ATOMIC_LOAD_MIN_I64:
1528  AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA;
1529  NeedsAdditionalReg = true;
1530  break;
1531  case Mips::ATOMIC_LOAD_MAX_I64:
1532  AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA;
1533  NeedsAdditionalReg = true;
1534  break;
1535  case Mips::ATOMIC_LOAD_UMIN_I64:
1536  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA;
1537  NeedsAdditionalReg = true;
1538  break;
1539  case Mips::ATOMIC_LOAD_UMAX_I64:
1540  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA;
1541  NeedsAdditionalReg = true;
1542  break;
1543  default:
1544  llvm_unreachable("Unknown pseudo atomic for replacement!");
1545  }
1546 
1547  Register OldVal = MI.getOperand(0).getReg();
1548  Register Ptr = MI.getOperand(1).getReg();
1549  Register Incr = MI.getOperand(2).getReg();
1550  Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1551 
1553 
1554  // The scratch registers here with the EarlyClobber | Define | Implicit
1555  // flags is used to persuade the register allocator and the machine
1556  // verifier to accept the usage of this register. This has to be a real
1557  // register which has an UNDEF value but is dead after the instruction which
1558  // is unique among the registers chosen for the instruction.
1559 
1560  // The EarlyClobber flag has the semantic properties that the operand it is
1561  // attached to is clobbered before the rest of the inputs are read. Hence it
1562  // must be unique among the operands to the instruction.
1563  // The Define flag is needed to coerce the machine verifier that an Undef
1564  // value isn't a problem.
1565  // The Dead flag is needed as the value in scratch isn't used by any other
1566  // instruction. Kill isn't used as Dead is more precise.
1567  // The implicit flag is here due to the interaction between the other flags
1568  // and the machine verifier.
1569 
1570  // For correctness purpose, a new pseudo is introduced here. We need this
1571  // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1572  // that is spread over >1 basic blocks. A register allocator which
1573  // introduces (or any codegen infact) a store, can violate the expectations
1574  // of the hardware.
1575  //
1576  // An atomic read-modify-write sequence starts with a linked load
1577  // instruction and ends with a store conditional instruction. The atomic
1578  // read-modify-write sequence fails if any of the following conditions
1579  // occur between the execution of ll and sc:
1580  // * A coherent store is completed by another process or coherent I/O
1581  // module into the block of synchronizable physical memory containing
1582  // the word. The size and alignment of the block is
1583  // implementation-dependent.
1584  // * A coherent store is executed between an LL and SC sequence on the
1585  // same processor to the block of synchornizable physical memory
1586  // containing the word.
1587  //
1588 
1589  Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1590  Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1591 
1592  BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1593  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1594 
1595  MachineInstrBuilder MIB =
1596  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1598  .addReg(PtrCopy)
1599  .addReg(IncrCopy)
1602  if (NeedsAdditionalReg) {
1603  Register Scratch2 =
1604  RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1607  }
1608 
1609  MI.eraseFromParent();
1610 
1611  return BB;
1612 }
1613 
1614 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1615  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1616  unsigned SrcReg) const {
1618  const DebugLoc &DL = MI.getDebugLoc();
1619 
1620  if (Subtarget.hasMips32r2() && Size == 1) {
1621  BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1622  return BB;
1623  }
1624 
1625  if (Subtarget.hasMips32r2() && Size == 2) {
1626  BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1627  return BB;
1628  }
1629 
1630  MachineFunction *MF = BB->getParent();
1631  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1633  Register ScrReg = RegInfo.createVirtualRegister(RC);
1634 
1635  assert(Size < 32);
1636  int64_t ShiftImm = 32 - (Size * 8);
1637 
1638  BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1639  BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1640 
1641  return BB;
1642 }
1643 
1644 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1645  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1646  assert((Size == 1 || Size == 2) &&
1647  "Unsupported size for EmitAtomicBinaryPartial.");
1648 
1649  MachineFunction *MF = BB->getParent();
1650  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1652  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1653  const TargetRegisterClass *RCp =
1654  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1656  DebugLoc DL = MI.getDebugLoc();
1657 
1658  Register Dest = MI.getOperand(0).getReg();
1659  Register Ptr = MI.getOperand(1).getReg();
1660  Register Incr = MI.getOperand(2).getReg();
1661 
1662  Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1663  Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1664  Register Mask = RegInfo.createVirtualRegister(RC);
1665  Register Mask2 = RegInfo.createVirtualRegister(RC);
1666  Register Incr2 = RegInfo.createVirtualRegister(RC);
1667  Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1668  Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1669  Register MaskUpper = RegInfo.createVirtualRegister(RC);
1670  Register Scratch = RegInfo.createVirtualRegister(RC);
1671  Register Scratch2 = RegInfo.createVirtualRegister(RC);
1672  Register Scratch3 = RegInfo.createVirtualRegister(RC);
1673 
1674  unsigned AtomicOp = 0;
1675  bool NeedsAdditionalReg = false;
1676  switch (MI.getOpcode()) {
1677  case Mips::ATOMIC_LOAD_NAND_I8:
1678  AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1679  break;
1680  case Mips::ATOMIC_LOAD_NAND_I16:
1681  AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1682  break;
1683  case Mips::ATOMIC_SWAP_I8:
1684  AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1685  break;
1686  case Mips::ATOMIC_SWAP_I16:
1687  AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1688  break;
1689  case Mips::ATOMIC_LOAD_ADD_I8:
1690  AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1691  break;
1692  case Mips::ATOMIC_LOAD_ADD_I16:
1693  AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1694  break;
1695  case Mips::ATOMIC_LOAD_SUB_I8:
1696  AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1697  break;
1698  case Mips::ATOMIC_LOAD_SUB_I16:
1699  AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1700  break;
1701  case Mips::ATOMIC_LOAD_AND_I8:
1702  AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1703  break;
1704  case Mips::ATOMIC_LOAD_AND_I16:
1705  AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1706  break;
1707  case Mips::ATOMIC_LOAD_OR_I8:
1708  AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1709  break;
1710  case Mips::ATOMIC_LOAD_OR_I16:
1711  AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1712  break;
1713  case Mips::ATOMIC_LOAD_XOR_I8:
1714  AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1715  break;
1716  case Mips::ATOMIC_LOAD_XOR_I16:
1717  AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1718  break;
1719  case Mips::ATOMIC_LOAD_MIN_I8:
1720  AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA;
1721  NeedsAdditionalReg = true;
1722  break;
1723  case Mips::ATOMIC_LOAD_MIN_I16:
1724  AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA;
1725  NeedsAdditionalReg = true;
1726  break;
1727  case Mips::ATOMIC_LOAD_MAX_I8:
1728  AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA;
1729  NeedsAdditionalReg = true;
1730  break;
1731  case Mips::ATOMIC_LOAD_MAX_I16:
1732  AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA;
1733  NeedsAdditionalReg = true;
1734  break;
1735  case Mips::ATOMIC_LOAD_UMIN_I8:
1736  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA;
1737  NeedsAdditionalReg = true;
1738  break;
1739  case Mips::ATOMIC_LOAD_UMIN_I16:
1740  AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA;
1741  NeedsAdditionalReg = true;
1742  break;
1743  case Mips::ATOMIC_LOAD_UMAX_I8:
1744  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA;
1745  NeedsAdditionalReg = true;
1746  break;
1747  case Mips::ATOMIC_LOAD_UMAX_I16:
1748  AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA;
1749  NeedsAdditionalReg = true;
1750  break;
1751  default:
1752  llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1753  }
1754 
1755  // insert new blocks after the current block
1756  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1757  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1758  MachineFunction::iterator It = ++BB->getIterator();
1759  MF->insert(It, exitMBB);
1760 
1761  // Transfer the remainder of BB and its successor edges to exitMBB.
1762  exitMBB->splice(exitMBB->begin(), BB,
1763  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1765 
1766  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1767 
1768  // thisMBB:
1769  // addiu masklsb2,$0,-4 # 0xfffffffc
1770  // and alignedaddr,ptr,masklsb2
1771  // andi ptrlsb2,ptr,3
1772  // sll shiftamt,ptrlsb2,3
1773  // ori maskupper,$0,255 # 0xff
1774  // sll mask,maskupper,shiftamt
1775  // nor mask2,$0,mask
1776  // sll incr2,incr,shiftamt
1777 
1778  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1779  BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1780  .addReg(ABI.GetNullPtr()).addImm(-4);
1781  BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1782  .addReg(Ptr).addReg(MaskLSB2);
1783  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1784  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1785  if (Subtarget.isLittle()) {
1786  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1787  } else {
1788  Register Off = RegInfo.createVirtualRegister(RC);
1789  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1790  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1791  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1792  }
1793  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1794  .addReg(Mips::ZERO).addImm(MaskImm);
1795  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1796  .addReg(MaskUpper).addReg(ShiftAmt);
1797  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1798  BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1799 
1800 
1801  // The purposes of the flags on the scratch registers is explained in
1802  // emitAtomicBinary. In summary, we need a scratch register which is going to
1803  // be undef, that is unique among registers chosen for the instruction.
1804 
1805  MachineInstrBuilder MIB =
1806  BuildMI(BB, DL, TII->get(AtomicOp))
1808  .addReg(AlignedAddr)
1809  .addReg(Incr2)
1810  .addReg(Mask)
1811  .addReg(Mask2)
1812  .addReg(ShiftAmt)
1819  if (NeedsAdditionalReg) {
1820  Register Scratch4 = RegInfo.createVirtualRegister(RC);
1823  }
1824 
1825  MI.eraseFromParent(); // The instruction is gone now.
1826 
1827  return exitMBB;
1828 }
1829 
1830 // Lower atomic compare and swap to a pseudo instruction, taking care to
1831 // define a scratch register for the pseudo instruction's expansion. The
1832 // instruction is expanded after the register allocator as to prevent
1833 // the insertion of stores between the linked load and the store conditional.
1834 
1836 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1837  MachineBasicBlock *BB) const {
1838 
1839  assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1840  MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1841  "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1842 
1843  const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1844 
1845  MachineFunction *MF = BB->getParent();
1847  const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1849  DebugLoc DL = MI.getDebugLoc();
1850 
1851  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1852  ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1853  : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1854  Register Dest = MI.getOperand(0).getReg();
1855  Register Ptr = MI.getOperand(1).getReg();
1856  Register OldVal = MI.getOperand(2).getReg();
1857  Register NewVal = MI.getOperand(3).getReg();
1858 
1859  Register Scratch = MRI.createVirtualRegister(RC);
1861 
1862  // We need to create copies of the various registers and kill them at the
1863  // atomic pseudo. If the copies are not made, when the atomic is expanded
1864  // after fast register allocation, the spills will end up outside of the
1865  // blocks that their values are defined in, causing livein errors.
1866 
1868  Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1869  Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1870 
1871  BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1872  BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1873  BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1874 
1875  // The purposes of the flags on the scratch registers is explained in
1876  // emitAtomicBinary. In summary, we need a scratch register which is going to
1877  // be undef, that is unique among registers chosen for the instruction.
1878 
1879  BuildMI(*BB, II, DL, TII->get(AtomicOp))
1881  .addReg(PtrCopy, RegState::Kill)
1882  .addReg(OldValCopy, RegState::Kill)
1883  .addReg(NewValCopy, RegState::Kill)
1886 
1887  MI.eraseFromParent(); // The instruction is gone now.
1888 
1889  return BB;
1890 }
1891 
1892 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1893  MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1894  assert((Size == 1 || Size == 2) &&
1895  "Unsupported size for EmitAtomicCmpSwapPartial.");
1896 
1897  MachineFunction *MF = BB->getParent();
1898  MachineRegisterInfo &RegInfo = MF->getRegInfo();
1900  const bool ArePtrs64bit = ABI.ArePtrs64bit();
1901  const TargetRegisterClass *RCp =
1902  getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1904  DebugLoc DL = MI.getDebugLoc();
1905 
1906  Register Dest = MI.getOperand(0).getReg();
1907  Register Ptr = MI.getOperand(1).getReg();
1908  Register CmpVal = MI.getOperand(2).getReg();
1909  Register NewVal = MI.getOperand(3).getReg();
1910 
1911  Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1912  Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1913  Register Mask = RegInfo.createVirtualRegister(RC);
1914  Register Mask2 = RegInfo.createVirtualRegister(RC);
1915  Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1916  Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1917  Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1918  Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1919  Register MaskUpper = RegInfo.createVirtualRegister(RC);
1920  Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1921  Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1922  unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1923  ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1924  : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1925 
1926  // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1927  // flags are used to coerce the register allocator and the machine verifier to
1928  // accept the usage of these registers.
1929  // The EarlyClobber flag has the semantic properties that the operand it is
1930  // attached to is clobbered before the rest of the inputs are read. Hence it
1931  // must be unique among the operands to the instruction.
1932  // The Define flag is needed to coerce the machine verifier that an Undef
1933  // value isn't a problem.
1934  // The Dead flag is needed as the value in scratch isn't used by any other
1935  // instruction. Kill isn't used as Dead is more precise.
1936  Register Scratch = RegInfo.createVirtualRegister(RC);
1937  Register Scratch2 = RegInfo.createVirtualRegister(RC);
1938 
1939  // insert new blocks after the current block
1940  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1941  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1942  MachineFunction::iterator It = ++BB->getIterator();
1943  MF->insert(It, exitMBB);
1944 
1945  // Transfer the remainder of BB and its successor edges to exitMBB.
1946  exitMBB->splice(exitMBB->begin(), BB,
1947  std::next(MachineBasicBlock::iterator(MI)), BB->end());
1949 
1950  BB->addSuccessor(exitMBB, BranchProbability::getOne());
1951 
1952  // thisMBB:
1953  // addiu masklsb2,$0,-4 # 0xfffffffc
1954  // and alignedaddr,ptr,masklsb2
1955  // andi ptrlsb2,ptr,3
1956  // xori ptrlsb2,ptrlsb2,3 # Only for BE
1957  // sll shiftamt,ptrlsb2,3
1958  // ori maskupper,$0,255 # 0xff
1959  // sll mask,maskupper,shiftamt
1960  // nor mask2,$0,mask
1961  // andi maskedcmpval,cmpval,255
1962  // sll shiftedcmpval,maskedcmpval,shiftamt
1963  // andi maskednewval,newval,255
1964  // sll shiftednewval,maskednewval,shiftamt
1965  int64_t MaskImm = (Size == 1) ? 255 : 65535;
1966  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1967  .addReg(ABI.GetNullPtr()).addImm(-4);
1968  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1969  .addReg(Ptr).addReg(MaskLSB2);
1970  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1971  .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1972  if (Subtarget.isLittle()) {
1973  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1974  } else {
1975  Register Off = RegInfo.createVirtualRegister(RC);
1976  BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1977  .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1978  BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1979  }
1980  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1981  .addReg(Mips::ZERO).addImm(MaskImm);
1982  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1983  .addReg(MaskUpper).addReg(ShiftAmt);
1984  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1985  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1986  .addReg(CmpVal).addImm(MaskImm);
1987  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1988  .addReg(MaskedCmpVal).addReg(ShiftAmt);
1989  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1990  .addReg(NewVal).addImm(MaskImm);
1991  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1992  .addReg(MaskedNewVal).addReg(ShiftAmt);
1993 
1994  // The purposes of the flags on the scratch registers are explained in
1995  // emitAtomicBinary. In summary, we need a scratch register which is going to
1996  // be undef, that is unique among the register chosen for the instruction.
1997 
1998  BuildMI(BB, DL, TII->get(AtomicOp))
2000  .addReg(AlignedAddr)
2001  .addReg(Mask)
2002  .addReg(ShiftedCmpVal)
2003  .addReg(Mask2)
2004  .addReg(ShiftedNewVal)
2005  .addReg(ShiftAmt)
2010 
2011  MI.eraseFromParent(); // The instruction is gone now.
2012 
2013  return exitMBB;
2014 }
2015 
2016 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2017  // The first operand is the chain, the second is the condition, the third is
2018  // the block to branch to if the condition is true.
2019  SDValue Chain = Op.getOperand(0);
2020  SDValue Dest = Op.getOperand(2);
2021  SDLoc DL(Op);
2022 
2024  SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
2025 
2026  // Return if flag is not set by a floating point comparison.
2027  if (CondRes.getOpcode() != MipsISD::FPCmp)
2028  return Op;
2029 
2030  SDValue CCNode = CondRes.getOperand(2);
2031  Mips::CondCode CC =
2032  (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
2033  unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
2034  SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
2035  SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
2036  return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
2037  FCC0, Dest, CondRes);
2038 }
2039 
2040 SDValue MipsTargetLowering::
2041 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
2042 {
2044  SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
2045 
2046  // Return if flag is not set by a floating point comparison.
2047  if (Cond.getOpcode() != MipsISD::FPCmp)
2048  return Op;
2049 
2050  return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
2051  SDLoc(Op));
2052 }
2053 
2054 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2056  SDValue Cond = createFPCmp(DAG, Op);
2057 
2058  assert(Cond.getOpcode() == MipsISD::FPCmp &&
2059  "Floating point operand expected.");
2060 
2061  SDLoc DL(Op);
2062  SDValue True = DAG.getConstant(1, DL, MVT::i32);
2063  SDValue False = DAG.getConstant(0, DL, MVT::i32);
2064 
2065  return createCMovFP(DAG, Cond, True, False, DL);
2066 }
2067 
2068 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2069  SelectionDAG &DAG) const {
2070  EVT Ty = Op.getValueType();
2071  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2072  const GlobalValue *GV = N->getGlobal();
2073 
2074  if (!isPositionIndependent()) {
2075  const MipsTargetObjectFile *TLOF =
2076  static_cast<const MipsTargetObjectFile *>(
2078  const GlobalObject *GO = GV->getAliaseeObject();
2079  if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2080  // %gp_rel relocation
2081  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2082 
2083  // %hi/%lo relocation
2084  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2085  // %highest/%higher/%hi/%lo relocation
2086  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2087  }
2088 
2089  // Every other architecture would use shouldAssumeDSOLocal in here, but
2090  // mips is special.
2091  // * In PIC code mips requires got loads even for local statics!
2092  // * To save on got entries, for local statics the got entry contains the
2093  // page and an additional add instruction takes care of the low bits.
2094  // * It is legal to access a hidden symbol with a non hidden undefined,
2095  // so one cannot guarantee that all access to a hidden symbol will know
2096  // it is hidden.
2097  // * Mips linkers don't support creating a page and a full got entry for
2098  // the same symbol.
2099  // * Given all that, we have to use a full got entry for hidden symbols :-(
2100  if (GV->hasLocalLinkage())
2101  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2102 
2103  if (Subtarget.useXGOT())
2104  return getAddrGlobalLargeGOT(
2106  DAG.getEntryNode(),
2107  MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2108 
2109  return getAddrGlobal(
2110  N, SDLoc(N), Ty, DAG,
2112  DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2113 }
2114 
2115 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2116  SelectionDAG &DAG) const {
2117  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2118  EVT Ty = Op.getValueType();
2119 
2120  if (!isPositionIndependent())
2121  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2122  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2123 
2124  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2125 }
2126 
2127 SDValue MipsTargetLowering::
2128 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2129 {
2130  // If the relocation model is PIC, use the General Dynamic TLS Model or
2131  // Local Dynamic TLS model, otherwise use the Initial Exec or
2132  // Local Exec TLS Model.
2133 
2134  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2135  if (DAG.getTarget().useEmulatedTLS())
2136  return LowerToTLSEmulatedModel(GA, DAG);
2137 
2138  SDLoc DL(GA);
2139  const GlobalValue *GV = GA->getGlobal();
2140  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2141 
2143 
2145  // General Dynamic and Local Dynamic TLS Model.
2147  : MipsII::MO_TLSGD;
2148 
2149  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2150  SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2151  getGlobalReg(DAG, PtrVT), TGA);
2152  unsigned PtrSize = PtrVT.getSizeInBits();
2153  IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2154 
2155  SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2156 
2157  ArgListTy Args;
2158  ArgListEntry Entry;
2159  Entry.Node = Argument;
2160  Entry.Ty = PtrTy;
2161  Args.push_back(Entry);
2162 
2164  CLI.setDebugLoc(DL)
2165  .setChain(DAG.getEntryNode())
2166  .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2167  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2168 
2169  SDValue Ret = CallResult.first;
2170 
2172  return Ret;
2173 
2174  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2176  SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2177  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2179  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2180  SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2181  return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2182  }
2183 
2184  SDValue Offset;
2185  if (model == TLSModel::InitialExec) {
2186  // Initial Exec TLS Model
2187  SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2189  TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2190  TGA);
2191  Offset =
2192  DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2193  } else {
2194  // Local Exec TLS Model
2196  SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2198  SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2200  SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2201  SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2202  Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2203  }
2204 
2206  return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2207 }
2208 
2209 SDValue MipsTargetLowering::
2210 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2211 {
2212  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2213  EVT Ty = Op.getValueType();
2214 
2215  if (!isPositionIndependent())
2216  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2217  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2218 
2219  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2220 }
2221 
2222 SDValue MipsTargetLowering::
2223 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2224 {
2225  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2226  EVT Ty = Op.getValueType();
2227 
2228  if (!isPositionIndependent()) {
2229  const MipsTargetObjectFile *TLOF =
2230  static_cast<const MipsTargetObjectFile *>(
2232 
2233  if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2234  getTargetMachine()))
2235  // %gp_rel relocation
2236  return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2237 
2238  return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2239  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2240  }
2241 
2242  return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2243 }
2244 
2245 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2246  MachineFunction &MF = DAG.getMachineFunction();
2247  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2248 
2249  SDLoc DL(Op);
2250  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2251  getPointerTy(MF.getDataLayout()));
2252 
2253  // vastart just stores the address of the VarArgsFrameIndex slot into the
2254  // memory location argument.
2255  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2256  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2257  MachinePointerInfo(SV));
2258 }
2259 
2260 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2261  SDNode *Node = Op.getNode();
2262  EVT VT = Node->getValueType(0);
2263  SDValue Chain = Node->getOperand(0);
2264  SDValue VAListPtr = Node->getOperand(1);
2265  const Align Align =
2266  llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
2267  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2268  SDLoc DL(Node);
2269  unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2270 
2271  SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2272  VAListPtr, MachinePointerInfo(SV));
2273  SDValue VAList = VAListLoad;
2274 
2275  // Re-align the pointer if necessary.
2276  // It should only ever be necessary for 64-bit types on O32 since the minimum
2277  // argument alignment is the same as the maximum type alignment for N32/N64.
2278  //
2279  // FIXME: We currently align too often. The code generator doesn't notice
2280  // when the pointer is still aligned from the last va_arg (or pair of
2281  // va_args for the i64 on O32 case).
2283  VAList = DAG.getNode(
2284  ISD::ADD, DL, VAList.getValueType(), VAList,
2285  DAG.getConstant(Align.value() - 1, DL, VAList.getValueType()));
2286 
2287  VAList = DAG.getNode(
2288  ISD::AND, DL, VAList.getValueType(), VAList,
2289  DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType()));
2290  }
2291 
2292  // Increment the pointer, VAList, to the next vaarg.
2293  auto &TD = DAG.getDataLayout();
2294  unsigned ArgSizeInBytes =
2295  TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2296  SDValue Tmp3 =
2297  DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2298  DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2299  DL, VAList.getValueType()));
2300  // Store the incremented VAList to the legalized pointer
2301  Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2302  MachinePointerInfo(SV));
2303 
2304  // In big-endian mode we must adjust the pointer when the load size is smaller
2305  // than the argument slot size. We must also reduce the known alignment to
2306  // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2307  // the correct half of the slot, and reduce the alignment from 8 (slot
2308  // alignment) down to 4 (type alignment).
2309  if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2310  unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2311  VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2312  DAG.getIntPtrConstant(Adjustment, DL));
2313  }
2314  // Load the actual argument out of the pointer VAList
2315  return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2316 }
2317 
2319  bool HasExtractInsert) {
2320  EVT TyX = Op.getOperand(0).getValueType();
2321  EVT TyY = Op.getOperand(1).getValueType();
2322  SDLoc DL(Op);
2323  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2324  SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2325  SDValue Res;
2326 
2327  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2328  // to i32.
2329  SDValue X = (TyX == MVT::f32) ?
2330  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2331  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2332  Const1);
2333  SDValue Y = (TyY == MVT::f32) ?
2334  DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2335  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2336  Const1);
2337 
2338  if (HasExtractInsert) {
2339  // ext E, Y, 31, 1 ; extract bit31 of Y
2340  // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2341  SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2342  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2343  } else {
2344  // sll SllX, X, 1
2345  // srl SrlX, SllX, 1
2346  // srl SrlY, Y, 31
2347  // sll SllY, SrlX, 31
2348  // or Or, SrlX, SllY
2349  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2350  SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2351  SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2352  SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2353  Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2354  }
2355 
2356  if (TyX == MVT::f32)
2357  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2358 
2360  Op.getOperand(0),
2361  DAG.getConstant(0, DL, MVT::i32));
2362  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2363 }
2364 
2366  bool HasExtractInsert) {
2367  unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2368  unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2369  EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2370  SDLoc DL(Op);
2371  SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2372 
2373  // Bitcast to integer nodes.
2374  SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2375  SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2376 
2377  if (HasExtractInsert) {
2378  // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2379  // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2380  SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2381  DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2382 
2383  if (WidthX > WidthY)
2384  E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2385  else if (WidthY > WidthX)
2386  E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2387 
2388  SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2389  DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2390  X);
2391  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2392  }
2393 
2394  // (d)sll SllX, X, 1
2395  // (d)srl SrlX, SllX, 1
2396  // (d)srl SrlY, Y, width(Y)-1
2397  // (d)sll SllY, SrlX, width(Y)-1
2398  // or Or, SrlX, SllY
2399  SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2400  SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2401  SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2402  DAG.getConstant(WidthY - 1, DL, MVT::i32));
2403 
2404  if (WidthX > WidthY)
2405  SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2406  else if (WidthY > WidthX)
2407  SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2408 
2409  SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2410  DAG.getConstant(WidthX - 1, DL, MVT::i32));
2411  SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2412  return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2413 }
2414 
2415 SDValue
2416 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2417  if (Subtarget.isGP64bit())
2419 
2421 }
2422 
2423 SDValue MipsTargetLowering::lowerFABS32(SDValue Op, SelectionDAG &DAG,
2424  bool HasExtractInsert) const {
2425  SDLoc DL(Op);
2426  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2427 
2429  return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2430 
2431  // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2432  // to i32.
2433  SDValue X = (Op.getValueType() == MVT::f32)
2434  ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2436  Op.getOperand(0), Const1);
2437 
2438  // Clear MSB.
2439  if (HasExtractInsert)
2440  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2441  DAG.getRegister(Mips::ZERO, MVT::i32),
2442  DAG.getConstant(31, DL, MVT::i32), Const1, X);
2443  else {
2444  // TODO: Provide DAG patterns which transform (and x, cst)
2445  // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2446  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2447  Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2448  }
2449 
2450  if (Op.getValueType() == MVT::f32)
2451  return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2452 
2453  // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2454  // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2455  // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2456  // place.
2457  SDValue LowX =
2458  DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2459  DAG.getConstant(0, DL, MVT::i32));
2460  return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2461 }
2462 
2463 SDValue MipsTargetLowering::lowerFABS64(SDValue Op, SelectionDAG &DAG,
2464  bool HasExtractInsert) const {
2465  SDLoc DL(Op);
2466  SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2467 
2469  return DAG.getNode(MipsISD::FAbs, DL, Op.getValueType(), Op.getOperand(0));
2470 
2471  // Bitcast to integer node.
2472  SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2473 
2474  // Clear MSB.
2475  if (HasExtractInsert)
2476  Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2477  DAG.getRegister(Mips::ZERO_64, MVT::i64),
2478  DAG.getConstant(63, DL, MVT::i32), Const1, X);
2479  else {
2480  SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2481  Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2482  }
2483 
2484  return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2485 }
2486 
2487 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2488  if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2489  return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2490 
2491  return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2492 }
2493 
2494 SDValue MipsTargetLowering::
2495 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2496  // check the depth
2497  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2498  DAG.getContext()->emitError(
2499  "return address can be determined only for current frame");
2500  return SDValue();
2501  }
2502 
2504  MFI.setFrameAddressIsTaken(true);
2505  EVT VT = Op.getValueType();
2506  SDLoc DL(Op);
2507  SDValue FrameAddr = DAG.getCopyFromReg(
2508  DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2509  return FrameAddr;
2510 }
2511 
2512 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2513  SelectionDAG &DAG) const {
2515  return SDValue();
2516 
2517  // check the depth
2518  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2519  DAG.getContext()->emitError(
2520  "return address can be determined only for current frame");
2521  return SDValue();
2522  }
2523 
2524  MachineFunction &MF = DAG.getMachineFunction();
2525  MachineFrameInfo &MFI = MF.getFrameInfo();
2526  MVT VT = Op.getSimpleValueType();
2527  unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2528  MFI.setReturnAddressIsTaken(true);
2529 
2530  // Return RA, which contains the return address. Mark it an implicit live-in.
2531  Register Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2532  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2533 }
2534 
2535 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2536 // generated from __builtin_eh_return (offset, handler)
2537 // The effect of this is to adjust the stack pointer by "offset"
2538 // and then branch to "handler".
2539 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2540  const {
2541  MachineFunction &MF = DAG.getMachineFunction();
2542  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2543 
2544  MipsFI->setCallsEhReturn();
2545  SDValue Chain = Op.getOperand(0);
2546  SDValue Offset = Op.getOperand(1);
2547  SDValue Handler = Op.getOperand(2);
2548  SDLoc DL(Op);
2549  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2550 
2551  // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2552  // EH_RETURN nodes, so that instructions are emitted back-to-back.
2553  unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2554  unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2555  Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2556  Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2557  return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2558  DAG.getRegister(OffsetReg, Ty),
2559  DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2560  Chain.getValue(1));
2561 }
2562 
2563 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2564  SelectionDAG &DAG) const {
2565  // FIXME: Need pseudo-fence for 'singlethread' fences
2566  // FIXME: Set SType for weaker fences where supported/appropriate.
2567  unsigned SType = 0;
2568  SDLoc DL(Op);
2569  return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2570  DAG.getConstant(SType, DL, MVT::i32));
2571 }
2572 
2573 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2574  SelectionDAG &DAG) const {
2575  SDLoc DL(Op);
2577 
2578  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2579  SDValue Shamt = Op.getOperand(2);
2580  // if shamt < (VT.bits):
2581  // lo = (shl lo, shamt)
2582  // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2583  // else:
2584  // lo = 0
2585  // hi = (shl lo, shamt[4:0])
2586  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2587  DAG.getConstant(-1, DL, MVT::i32));
2588  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2589  DAG.getConstant(1, DL, VT));
2590  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2591  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2592  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2593  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2594  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2595  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2596  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2597  DAG.getConstant(0, DL, VT), ShiftLeftLo);
2598  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2599 
2600  SDValue Ops[2] = {Lo, Hi};
2601  return DAG.getMergeValues(Ops, DL);
2602 }
2603 
2604 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2605  bool IsSRA) const {
2606  SDLoc DL(Op);
2607  SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2608  SDValue Shamt = Op.getOperand(2);
2610 
2611  // if shamt < (VT.bits):
2612  // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2613  // if isSRA:
2614  // hi = (sra hi, shamt)
2615  // else:
2616  // hi = (srl hi, shamt)
2617  // else:
2618  // if isSRA:
2619  // lo = (sra hi, shamt[4:0])
2620  // hi = (sra hi, 31)
2621  // else:
2622  // lo = (srl hi, shamt[4:0])
2623  // hi = 0
2624  SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2625  DAG.getConstant(-1, DL, MVT::i32));
2626  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2627  DAG.getConstant(1, DL, VT));
2628  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2629  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2630  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2631  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2632  DL, VT, Hi, Shamt);
2633  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2634  DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2635  SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2636  DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2637 
2638  if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2639  SDVTList VTList = DAG.getVTList(VT, VT);
2640  return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
2641  : Mips::PseudoD_SELECT_I,
2642  DL, VTList, Cond, ShiftRightHi,
2643  IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2644  ShiftRightHi);
2645  }
2646 
2647  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2648  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2649  IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2650 
2651  SDValue Ops[2] = {Lo, Hi};
2652  return DAG.getMergeValues(Ops, DL);
2653 }
2654 
2655 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2656  SDValue Chain, SDValue Src, unsigned Offset) {
2657  SDValue Ptr = LD->getBasePtr();
2658  EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2659  EVT BasePtrVT = Ptr.getValueType();
2660  SDLoc DL(LD);
2661  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2662 
2663  if (Offset)
2664  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2665  DAG.getConstant(Offset, DL, BasePtrVT));
2666 
2667  SDValue Ops[] = { Chain, Ptr, Src };
2668  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2669  LD->getMemOperand());
2670 }
2671 
2672 // Expand an unaligned 32 or 64-bit integer load node.
2674  LoadSDNode *LD = cast<LoadSDNode>(Op);
2675  EVT MemVT = LD->getMemoryVT();
2676 
2678  return Op;
2679 
2680  // Return if load is aligned or if MemVT is neither i32 nor i64.
2681  if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) ||
2682  ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2683  return SDValue();
2684 
2685  bool IsLittle = Subtarget.isLittle();
2686  EVT VT = Op.getValueType();
2687  ISD::LoadExtType ExtType = LD->getExtensionType();
2688  SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2689 
2690  assert((VT == MVT::i32) || (VT == MVT::i64));
2691 
2692  // Expand
2693  // (set dst, (i64 (load baseptr)))
2694  // to
2695  // (set tmp, (ldl (add baseptr, 7), undef))
2696  // (set dst, (ldr baseptr, tmp))
2697  if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2698  SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2699  IsLittle ? 7 : 0);
2700  return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2701  IsLittle ? 0 : 7);
2702  }
2703 
2704  SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2705  IsLittle ? 3 : 0);
2706  SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2707  IsLittle ? 0 : 3);
2708 
2709  // Expand
2710  // (set dst, (i32 (load baseptr))) or
2711  // (set dst, (i64 (sextload baseptr))) or
2712  // (set dst, (i64 (extload baseptr)))
2713  // to
2714  // (set tmp, (lwl (add baseptr, 3), undef))
2715  // (set dst, (lwr baseptr, tmp))
2716  if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2717  (ExtType == ISD::EXTLOAD))
2718  return LWR;
2719 
2720  assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2721 
2722  // Expand
2723  // (set dst, (i64 (zextload baseptr)))
2724  // to
2725  // (set tmp0, (lwl (add baseptr, 3), undef))
2726  // (set tmp1, (lwr baseptr, tmp0))
2727  // (set tmp2, (shl tmp1, 32))
2728  // (set dst, (srl tmp2, 32))
2729  SDLoc DL(LD);
2730  SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2731  SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2732  SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2733  SDValue Ops[] = { SRL, LWR.getValue(1) };
2734  return DAG.getMergeValues(Ops, DL);
2735 }
2736 
2737 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2738  SDValue Chain, unsigned Offset) {
2739  SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2740  EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2741  SDLoc DL(SD);
2742  SDVTList VTList = DAG.getVTList(MVT::Other);
2743 
2744  if (Offset)
2745  Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2746  DAG.getConstant(Offset, DL, BasePtrVT));
2747 
2748  SDValue Ops[] = { Chain, Value, Ptr };
2749  return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2750  SD->getMemOperand());
2751 }
2752 
2753 // Expand an unaligned 32 or 64-bit integer store node.
2755  bool IsLittle) {
2756  SDValue Value = SD->getValue(), Chain = SD->getChain();
2757  EVT VT = Value.getValueType();
2758 
2759  // Expand
2760  // (store val, baseptr) or
2761  // (truncstore val, baseptr)
2762  // to
2763  // (swl val, (add baseptr, 3))
2764  // (swr val, baseptr)
2765  if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2766  SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2767  IsLittle ? 3 : 0);
2768  return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2769  }
2770 
2771  assert(VT == MVT::i64);
2772 
2773  // Expand
2774  // (store val, baseptr)
2775  // to
2776  // (sdl val, (add baseptr, 7))
2777  // (sdr val, baseptr)
2778  SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2779  return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2780 }
2781 
2782 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2784  bool SingleFloat) {
2785  SDValue Val = SD->getValue();
2786 
2787  if (Val.getOpcode() != ISD::FP_TO_SINT ||
2788  (Val.getValueSizeInBits() > 32 && SingleFloat))
2789  return SDValue();
2790 
2792  SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2793  Val.getOperand(0));
2794  return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2795  SD->getPointerInfo(), SD->getAlign(),
2796  SD->getMemOperand()->getFlags());
2797 }
2798 
2800  StoreSDNode *SD = cast<StoreSDNode>(Op);
2801  EVT MemVT = SD->getMemoryVT();
2802 
2803  // Lower unaligned integer stores.
2805  (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) &&
2806  ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2807  return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2808 
2809  return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2810 }
2811 
2812 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2813  SelectionDAG &DAG) const {
2814 
2815  // Return a fixed StackObject with offset 0 which points to the old stack
2816  // pointer.
2818  EVT ValTy = Op->getValueType(0);
2819  int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2820  return DAG.getFrameIndex(FI, ValTy);
2821 }
2822 
2823 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2824  SelectionDAG &DAG) const {
2825  if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
2826  return SDValue();
2827 
2828  EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2829  SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2830  Op.getOperand(0));
2831  return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2832 }
2833 
2834 //===----------------------------------------------------------------------===//
2835 // Calling Convention Implementation
2836 //===----------------------------------------------------------------------===//
2837 
2838 //===----------------------------------------------------------------------===//
2839 // TODO: Implement a generic logic using tblgen that can support this.
2840 // Mips O32 ABI rules:
2841 // ---
2842 // i32 - Passed in A0, A1, A2, A3 and stack
2843 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2844 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2845 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2846 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2847 // not used, it must be shadowed. If only A3 is available, shadow it and
2848 // go to stack.
2849 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2850 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2851 // with the remainder spilled to the stack.
2852 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2853 // spilling the remainder to the stack.
2854 //
2855 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2856 //===----------------------------------------------------------------------===//
2857 
2858 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2859  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2860  CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2861  const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2862  State.getMachineFunction().getSubtarget());
2863 
2864  static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2865 
2866  const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2867 
2868  static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2869 
2870  static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2871 
2872  // Do not process byval args here.
2873  if (ArgFlags.isByVal())
2874  return true;
2875 
2876  // Promote i8 and i16
2877  if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2878  if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2879  LocVT = MVT::i32;
2880  if (ArgFlags.isSExt())
2881  LocInfo = CCValAssign::SExtUpper;
2882  else if (ArgFlags.isZExt())
2883  LocInfo = CCValAssign::ZExtUpper;
2884  else
2885  LocInfo = CCValAssign::AExtUpper;
2886  }
2887  }
2888 
2889  // Promote i8 and i16
2890  if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2891  LocVT = MVT::i32;
2892  if (ArgFlags.isSExt())
2893  LocInfo = CCValAssign::SExt;
2894  else if (ArgFlags.isZExt())
2895  LocInfo = CCValAssign::ZExt;
2896  else
2897  LocInfo = CCValAssign::AExt;
2898  }
2899 
2900  unsigned Reg;
2901 
2902  // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2903  // is true: function is vararg, argument is 3rd or higher, there is previous
2904  // argument which is not f32 or f64.
2905  bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2906  State.getFirstUnallocated(F32Regs) != ValNo;
2907  Align OrigAlign = ArgFlags.getNonZeroOrigAlign();
2908  bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8));
2909  bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2910 
2911  // The MIPS vector ABI for floats passes them in a pair of registers
2912  if (ValVT == MVT::i32 && isVectorFloat) {
2913  // This is the start of an vector that was scalarized into an unknown number
2914  // of components. It doesn't matter how many there are. Allocate one of the
2915  // notional 8 byte aligned registers which map onto the argument stack, and
2916  // shadow the register lost to alignment requirements.
2917  if (ArgFlags.isSplit()) {
2918  Reg = State.AllocateReg(FloatVectorIntRegs);
2919  if (Reg == Mips::A2)
2920  State.AllocateReg(Mips::A1);
2921  else if (Reg == 0)
2922  State.AllocateReg(Mips::A3);
2923  } else {
2924  // If we're an intermediate component of the split, we can just attempt to
2925  // allocate a register directly.
2926  Reg = State.AllocateReg(IntRegs);
2927  }
2928  } else if (ValVT == MVT::i32 ||
2929  (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2930  Reg = State.AllocateReg(IntRegs);
2931  // If this is the first part of an i64 arg,
2932  // the allocated register must be either A0 or A2.
2933  if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2934  Reg = State.AllocateReg(IntRegs);
2935  LocVT = MVT::i32;
2936  } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2937  LocVT = MVT::i32;
2938 
2939  // Allocate int register and shadow next int register. If first
2940  // available register is Mips::A1 or Mips::A3, shadow it too.
2941  Reg = State.AllocateReg(IntRegs);
2942  if (Reg == Mips::A1 || Reg == Mips::A3)
2943  Reg = State.AllocateReg(IntRegs);
2944 
2945  if (Reg) {
2946  State.addLoc(
2947  CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2948  MCRegister HiReg = State.AllocateReg(IntRegs);
2949  assert(HiReg);
2950  State.addLoc(
2951  CCValAssign::getCustomReg(ValNo, ValVT, HiReg, LocVT, LocInfo));
2952  return false;
2953  }
2954  } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2955  // we are guaranteed to find an available float register
2956  if (ValVT == MVT::f32) {
2957  Reg = State.AllocateReg(F32Regs);
2958  // Shadow int register
2959  State.AllocateReg(IntRegs);
2960  } else {
2961  Reg = State.AllocateReg(F64Regs);
2962  // Shadow int registers
2963  unsigned Reg2 = State.AllocateReg(IntRegs);
2964  if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2965  State.AllocateReg(IntRegs);
2966  State.AllocateReg(IntRegs);
2967  }
2968  } else
2969  llvm_unreachable("Cannot handle this ValVT.");
2970 
2971  if (!Reg) {
2972  unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2973  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2974  } else
2975  State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2976 
2977  return false;
2978 }
2979 
2980 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2981  MVT LocVT, CCValAssign::LocInfo LocInfo,
2982  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2983  static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2984 
2985  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2986 }
2987 
2988 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2989  MVT LocVT, CCValAssign::LocInfo LocInfo,
2990  ISD::ArgFlagsTy ArgFlags, CCState &State) {
2991  static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2992 
2993  return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2994 }
2995 
2996 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2997  CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2999 
3000 #include "MipsGenCallingConv.inc"
3001 
3003  return CC_Mips_FixedArg;
3004  }
3005 
3007  return RetCC_Mips;
3008  }
3009 //===----------------------------------------------------------------------===//
3010 // Call Calling Convention Implementation
3011 //===----------------------------------------------------------------------===//
3012 
3013 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
3014  SDValue Chain, SDValue Arg,
3015  const SDLoc &DL, bool IsTailCall,
3016  SelectionDAG &DAG) const {
3017  if (!IsTailCall) {
3018  SDValue PtrOff =
3019  DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
3020  DAG.getIntPtrConstant(Offset, DL));
3021  return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
3022  }
3023 
3025  int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
3026  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3027  return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), MaybeAlign(),
3029 }
3030 
3033  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3034  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
3035  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
3036  SDValue Chain) const {
3037  // Insert node "GP copy globalreg" before call to function.
3038  //
3039  // R_MIPS_CALL* operators (emitted when non-internal functions are called
3040  // in PIC mode) allow symbols to be resolved via lazy binding.
3041  // The lazy binding stub requires GP to point to the GOT.
3042  // Note that we don't need GP to point to the GOT for indirect calls
3043  // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
3044  // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
3045  // used for the function (that is, Mips linker doesn't generate lazy binding
3046  // stub for a function whose address is taken in the program).
3047  if (IsPICCall && !InternalLinkage && IsCallReloc) {
3048  unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
3049  EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
3050  RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
3051  }
3052 
3053  // Build a sequence of copy-to-reg nodes chained together with token
3054  // chain and flag operands which copy the outgoing args into registers.
3055  // The InFlag in necessary since all emitted instructions must be
3056  // stuck together.
3057  SDValue InFlag;
3058 
3059  for (auto &R : RegsToPass) {
3060  Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InFlag);
3061  InFlag = Chain.getValue(1);
3062  }
3063 
3064  // Add argument registers to the end of the list so that they are
3065  // known live into the call.
3066  for (auto &R : RegsToPass)
3067  Ops.push_back(CLI.DAG.getRegister(R.first, R.second.getValueType()));
3068 
3069  // Add a register mask operand representing the call-preserved registers.
3071  const uint32_t *Mask =
3073  assert(Mask && "Missing call preserved mask for calling convention");
3074  if (Subtarget.inMips16HardFloat()) {
3075  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
3076  StringRef Sym = G->getGlobal()->getName();
3077  Function *F = G->getGlobal()->getParent()->getFunction(Sym);
3078  if (F && F->hasFnAttribute("__Mips16RetHelper")) {
3080  }
3081  }
3082  }
3083  Ops.push_back(CLI.DAG.getRegisterMask(Mask));
3084 
3085  if (InFlag.getNode())
3086  Ops.push_back(InFlag);
3087 }
3088 
3090  SDNode *Node) const {
3091  switch (MI.getOpcode()) {
3092  default:
3093  return;
3094  case Mips::JALR:
3095  case Mips::JALRPseudo:
3096  case Mips::JALR64:
3097  case Mips::JALR64Pseudo:
3098  case Mips::JALR16_MM:
3099  case Mips::JALRC16_MMR6:
3100  case Mips::TAILCALLREG:
3101  case Mips::TAILCALLREG64:
3102  case Mips::TAILCALLR6REG:
3103  case Mips::TAILCALL64R6REG:
3104  case Mips::TAILCALLREG_MM:
3105  case Mips::TAILCALLREG_MMR6: {
3106  if (!EmitJalrReloc ||
3107  Subtarget.inMips16Mode() ||
3108  !isPositionIndependent() ||
3109  Node->getNumOperands() < 1 ||
3110  Node->getOperand(0).getNumOperands() < 2) {
3111  return;
3112  }
3113  // We are after the callee address, set by LowerCall().
3114  // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
3115  // symbol.
3116  const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
3117  StringRef Sym;
3118  if (const GlobalAddressSDNode *G =
3119  dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
3120  // We must not emit the R_MIPS_JALR relocation against data symbols
3121  // since this will cause run-time crashes if the linker replaces the
3122  // call instruction with a relative branch to the data symbol.
3123  if (!isa<Function>(G->getGlobal())) {
3124  LLVM_DEBUG(dbgs() << "Not adding R_MIPS_JALR against data symbol "
3125  << G->getGlobal()->getName() << "\n");
3126  return;
3127  }
3128  Sym = G->getGlobal()->getName();
3129  }
3130  else if (const ExternalSymbolSDNode *ES =
3131  dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3132  Sym = ES->getSymbol();
3133  }
3134 
3135  if (Sym.empty())
3136  return;
3137 
3138  MachineFunction *MF = MI.getParent()->getParent();
3139  MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3140  LLVM_DEBUG(dbgs() << "Adding R_MIPS_JALR against " << Sym << "\n");
3142  }
3143  }
3144 }
3145 
3146 /// LowerCall - functions arguments are copied from virtual regs to
3147 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3148 SDValue
3149 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3150  SmallVectorImpl<SDValue> &InVals) const {
3151  SelectionDAG &DAG = CLI.DAG;
3152  SDLoc DL = CLI.DL;
3154  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3156  SDValue Chain = CLI.Chain;
3157  SDValue Callee = CLI.Callee;
3158  bool &IsTailCall = CLI.IsTailCall;
3159  CallingConv::ID CallConv = CLI.CallConv;
3160  bool IsVarArg = CLI.IsVarArg;
3161 
3162  MachineFunction &MF = DAG.getMachineFunction();
3163  MachineFrameInfo &MFI = MF.getFrameInfo();
3165  MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3166  bool IsPIC = isPositionIndependent();
3167 
3168  // Analyze operands of the call, assigning locations to each operand.
3170  MipsCCState CCInfo(
3171  CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3173 
3174  const ExternalSymbolSDNode *ES =
3175  dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3176 
3177  // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3178  // is during the lowering of a call with a byval argument which produces
3179  // a call to memcpy. For the O32 case, this causes the caller to allocate
3180  // stack space for the reserved argument area for the callee, then recursively
3181  // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3182  // ABIs mandate that the callee allocates the reserved argument area. We do
3183  // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3184  //
3185  // If the callee has a byval argument and memcpy is used, we are mandated
3186  // to already have produced a reserved argument area for the callee for O32.
3187  // Therefore, the reserved argument area can be reused for both calls.
3188  //
3189  // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3190  // present, as we have yet to hook that node onto the chain.
3191  //
3192  // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3193  // case. GCC does a similar trick, in that wherever possible, it calculates
3194  // the maximum out going argument area (including the reserved area), and
3195  // preallocates the stack space on entrance to the caller.
3196  //
3197  // FIXME: We should do the same for efficiency and space.
3198 
3199  // Note: The check on the calling convention below must match
3200  // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3201  bool MemcpyInByVal = ES &&
3202  StringRef(ES->getSymbol()) == StringRef("memcpy") &&
3203  CallConv != CallingConv::Fast &&
3204  Chain.getOpcode() == ISD::CALLSEQ_START;
3205 
3206  // Allocate the reserved argument area. It seems strange to do this from the
3207  // caller side but removing it breaks the frame size calculation.
3208  unsigned ReservedArgArea =
3209  MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3210  CCInfo.AllocateStack(ReservedArgArea, Align(1));
3211 
3212  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3213  ES ? ES->getSymbol() : nullptr);
3214 
3215  // Get a count of how many bytes are to be pushed on the stack.
3216  unsigned NextStackOffset = CCInfo.getNextStackOffset();
3217 
3218  // Call site info for function parameters tracking.
3220 
3221  // Check if it's really possible to do a tail call. Restrict it to functions
3222  // that are part of this compilation unit.
3223  bool InternalLinkage = false;
3224  if (IsTailCall) {
3225  IsTailCall = isEligibleForTailCallOptimization(
3226  CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3227  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3228  InternalLinkage = G->getGlobal()->hasInternalLinkage();
3229  IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3230  G->getGlobal()->hasPrivateLinkage() ||
3231  G->getGlobal()->hasHiddenVisibility() ||
3232  G->getGlobal()->hasProtectedVisibility());
3233  }
3234  }
3235  if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall())
3236  report_fatal_error("failed to perform tail call elimination on a call "
3237  "site marked musttail");
3238 
3239  if (IsTailCall)
3240  ++NumTailCalls;
3241 
3242  // Chain is the output chain of the last Load/Store or CopyToReg node.
3243  // ByValChain is the output chain of the last Memcpy node created for copying
3244  // byval arguments to the stack.
3245  unsigned StackAlignment = TFL->getStackAlignment();
3246  NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3247  SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3248 
3249  if (!(IsTailCall || MemcpyInByVal))
3250  Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3251 
3252  SDValue StackPtr =
3253  DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3254  getPointerTy(DAG.getDataLayout()));
3255 
3256  std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3257  SmallVector<SDValue, 8> MemOpChains;
3258 
3259  CCInfo.rewindByValRegsInfo();
3260 
3261  // Walk the register/memloc assignments, inserting copies/loads.
3262  for (unsigned i = 0, e = ArgLocs.size(), OutIdx = 0; i != e; ++i, ++OutIdx) {
3263  SDValue Arg = OutVals[OutIdx];
3264  CCValAssign &VA = ArgLocs[i];
3265  MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3266  ISD::ArgFlagsTy Flags = Outs[OutIdx].Flags;
3267  bool UseUpperBits = false;
3268 
3269  // ByVal Arg.
3270  if (Flags.isByVal()) {
3271  unsigned FirstByValReg, LastByValReg;
3272  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3273  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3274 
3275  assert(Flags.getByValSize() &&
3276  "ByVal args of size 0 should have been ignored by front-end.");
3277  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3278  assert(!IsTailCall &&
3279  "Do not tail-call optimize if there is a byval argument.");
3280  passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3281  FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3282  VA);
3283  CCInfo.nextInRegsParam();
3284  continue;
3285  }
3286 
3287  // Promote the value if needed.
3288  switch (VA.getLocInfo()) {
3289  default:
3290  llvm_unreachable("Unknown loc info!");
3291  case CCValAssign::Full:
3292  if (VA.isRegLoc()) {
3293  if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3294  (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3295  (ValVT == MVT::i64 && LocVT == MVT::f64))
3296  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3297  else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3299  Arg, DAG.getConstant(0, DL, MVT::i32));
3301  Arg, DAG.getConstant(1, DL, MVT::i32));
3302  if (!Subtarget.isLittle())
3303  std::swap(Lo, Hi);
3304 
3305  assert(VA.needsCustom());
3306 
3307  Register LocRegLo = VA.getLocReg();
3308  Register LocRegHigh = ArgLocs[++i].getLocReg();
3309  RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3310  RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3311  continue;
3312  }
3313  }
3314  break;
3315  case CCValAssign::BCvt:
3316  Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3317  break;
3319  UseUpperBits = true;
3321  case CCValAssign::SExt:
3322  Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3323  break;
3325  UseUpperBits = true;
3327  case CCValAssign::ZExt:
3328  Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3329  break;
3331  UseUpperBits = true;
3333  case CCValAssign::AExt:
3334  Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3335  break;
3336  }
3337 
3338  if (UseUpperBits) {
3339  unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits();
3340  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3341  Arg = DAG.getNode(
3342  ISD::SHL, DL, VA.getLocVT(), Arg,
3343  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3344  }
3345 
3346  // Arguments that can be passed on register must be kept at
3347  // RegsToPass vector
3348  if (VA.isRegLoc()) {
3349  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3350 
3351  // If the parameter is passed through reg $D, which splits into
3352  // two physical registers, avoid creating call site info.
3353  if (Mips::AFGR64RegClass.contains(VA.getLocReg()))
3354  continue;
3355 
3356  // Collect CSInfo about which register passes which parameter.
3357  const TargetOptions &Options = DAG.getTarget().Options;
3358  if (Options.SupportsDebugEntryValues)
3359  CSInfo.emplace_back(VA.getLocReg(), i);
3360 
3361  continue;
3362  }
3363 
3364  // Register can't get to this point...
3365  assert(VA.isMemLoc());
3366 
3367  // emit ISD::STORE whichs stores the
3368  // parameter value to a stack Location
3369  MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3370  Chain, Arg, DL, IsTailCall, DAG));
3371  }
3372 
3373  // Transform all store nodes into one single node because all store
3374  // nodes are independent of each other.
3375  if (!MemOpChains.empty())
3376  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3377 
3378  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3379  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3380  // node so that legalize doesn't hack it.
3381 
3382  EVT Ty = Callee.getValueType();
3383  bool GlobalOrExternal = false, IsCallReloc = false;
3384 
3385  // The long-calls feature is ignored in case of PIC.
3386  // While we do not support -mshared / -mno-shared properly,
3387  // ignore long-calls in case of -mabicalls too.
3388  if (!Subtarget.isABICalls() && !IsPIC) {
3389  // If the function should be called using "long call",
3390  // get its address into a register to prevent using
3391  // of the `jal` instruction for the direct call.
3392  if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3393  if (Subtarget.useLongCalls())
3395  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3396  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3397  } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3398  bool UseLongCalls = Subtarget.useLongCalls();
3399  // If the function has long-call/far/near attribute
3400  // it overrides command line switch pased to the backend.
3401  if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3402  if (F->hasFnAttribute("long-call"))
3403  UseLongCalls = true;
3404  else if (F->hasFnAttribute("short-call"))
3405  UseLongCalls = false;
3406  }
3407  if (UseLongCalls)
3409  ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3410  : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3411  }
3412  }
3413 
3414  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3415  if (IsPIC) {
3416  const GlobalValue *Val = G->getGlobal();
3417  InternalLinkage = Val->hasInternalLinkage();
3418 
3419  if (InternalLinkage)
3420  Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3421  else if (Subtarget.useXGOT()) {
3423  MipsII::MO_CALL_LO16, Chain,
3424  FuncInfo->callPtrInfo(MF, Val));
3425  IsCallReloc = true;
3426  } else {
3427  Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3428  FuncInfo->callPtrInfo(MF, Val));
3429  IsCallReloc = true;
3430  }
3431  } else
3432  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3433  getPointerTy(DAG.getDataLayout()), 0,
3435  GlobalOrExternal = true;
3436  }
3437  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3438  const char *Sym = S->getSymbol();
3439 
3440  if (!IsPIC) // static
3443  else if (Subtarget.useXGOT()) {
3445  MipsII::MO_CALL_LO16, Chain,
3446  FuncInfo->callPtrInfo(MF, Sym));
3447  IsCallReloc = true;
3448  } else { // PIC
3449  Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3450  FuncInfo->callPtrInfo(MF, Sym));
3451  IsCallReloc = true;
3452  }
3453 
3454  GlobalOrExternal = true;
3455  }
3456 
3457  SmallVector<SDValue, 8> Ops(1, Chain);
3458  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3459 
3460  getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3461  IsCallReloc, CLI, Callee, Chain);
3462 
3463  if (IsTailCall) {
3466  DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
3467  return Ret;
3468  }
3469 
3470  Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3471  SDValue InFlag = Chain.getValue(1);
3472 
3473  DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
3474 
3475  // Create the CALLSEQ_END node in the case of where it is not a call to
3476  // memcpy.
3477  if (!(MemcpyInByVal)) {
3478  Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3479  DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3480  InFlag = Chain.getValue(1);
3481  }
3482 
3483  // Handle result values, copying them out of physregs into vregs that we
3484  // return.
3485  return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3486  InVals, CLI);
3487 }
3488 
3489 /// LowerCallResult - Lower the result values of a call into the
3490 /// appropriate copies out of appropriate physical registers.
3491 SDValue MipsTargetLowering::LowerCallResult(
3492  SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3493  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3494  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3495  TargetLowering::CallLoweringInfo &CLI) const {
3496  // Assign locations to each value returned by this call.
3498  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3499  *DAG.getContext());
3500 
3501  const ExternalSymbolSDNode *ES =
3502  dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3503  CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3504  ES ? ES->getSymbol() : nullptr);
3505 
3506  // Copy all of the result registers out of their specified physreg.
3507  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3508  CCValAssign &VA = RVLocs[i];
3509  assert(VA.isRegLoc() && "Can only return in registers!");
3510 
3511  SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3512  RVLocs[i].getLocVT(), InFlag);
3513  Chain = Val.getValue(1);
3514  InFlag = Val.getValue(2);
3515 
3516  if (VA.isUpperBitsInLoc()) {
3517  unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3518  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3519  unsigned Shift =
3521  Val = DAG.getNode(
3522  Shift, DL, VA.getLocVT(), Val,
3523  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3524  }
3525 
3526  switch (VA.getLocInfo()) {
3527  default:
3528  llvm_unreachable("Unknown loc info!");
3529  case CCValAssign::Full:
3530  break;
3531  case CCValAssign::BCvt:
3532  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3533  break;
3534  case CCValAssign::AExt:
3536  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3537  break;
3538  case CCValAssign::ZExt:
3540  Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3541  DAG.getValueType(VA.getValVT()));
3542  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3543  break;
3544  case CCValAssign::SExt:
3546  Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3547  DAG.getValueType(VA.getValVT()));
3548  Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3549  break;
3550  }
3551 
3552  InVals.push_back(Val);
3553  }
3554 
3555  return Chain;
3556 }
3557 
3559  EVT ArgVT, const SDLoc &DL,
3560  SelectionDAG &DAG) {
3561  MVT LocVT = VA.getLocVT();
3562  EVT ValVT = VA.getValVT();
3563 
3564  // Shift into the upper bits if necessary.
3565  switch (VA.getLocInfo()) {
3566  default:
3567  break;
3570  case CCValAssign::ZExtUpper: {
3571  unsigned ValSizeInBits = ArgVT.getSizeInBits();
3572  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3573  unsigned Opcode =
3575  Val = DAG.getNode(
3576  Opcode, DL, VA.getLocVT(), Val,
3577  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3578  break;
3579  }
3580  }
3581 
3582  // If this is an value smaller than the argument slot size (32-bit for O32,
3583  // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3584  // size. Extract the value and insert any appropriate assertions regarding
3585  // sign/zero extension.
3586  switch (VA.getLocInfo()) {
3587  default:
3588  llvm_unreachable("Unknown loc info!");
3589  case CCValAssign::Full:
3590  break;
3592  case CCValAssign::AExt:
3593  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3594  break;
3596  case CCValAssign::SExt:
3597  Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3598  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3599  break;
3601  case CCValAssign::ZExt:
3602  Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3603  Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3604  break;
3605  case CCValAssign::BCvt:
3606  Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3607  break;
3608  }
3609 
3610  return Val;
3611 }
3612 
3613 //===----------------------------------------------------------------------===//
3614 // Formal Arguments Calling Convention Implementation
3615 //===----------------------------------------------------------------------===//
3616 /// LowerFormalArguments - transform physical registers into virtual registers
3617 /// and generate load operations for arguments places on the stack.
3618 SDValue MipsTargetLowering::LowerFormalArguments(
3619  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3620  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3621  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3622  MachineFunction &MF = DAG.getMachineFunction();
3623  MachineFrameInfo &MFI = MF.getFrameInfo();
3624  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3625 
3626  MipsFI->setVarArgsFrameIndex(0);
3627 
3628  // Used with vargs to acumulate store chains.
3629  std::vector<SDValue> OutChains;
3630 
3631  // Assign locations to all of the incoming arguments.
3633  MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3634  *DAG.getContext());
3635  CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1));
3636  const Function &Func = DAG.getMachineFunction().getFunction();
3637  Function::const_arg_iterator FuncArg = Func.arg_begin();
3638 
3639  if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3641  "Functions with the interrupt attribute cannot have arguments!");
3642 
3643  CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3644  MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3645  CCInfo.getInRegsParamsCount() > 0);
3646 
3647  unsigned CurArgIdx = 0;
3648  CCInfo.rewindByValRegsInfo();
3649 
3650  for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3651  CCValAssign &VA = ArgLocs[i];
3652  if (Ins[InsIdx].isOrigArg()) {
3653  std::advance(FuncArg, Ins[InsIdx].getOrigArgIndex() - CurArgIdx);
3654  CurArgIdx = Ins[InsIdx].getOrigArgIndex();
3655  }
3656  EVT ValVT = VA.getValVT();
3657  ISD::ArgFlagsTy Flags = Ins[InsIdx].Flags;
3658  bool IsRegLoc = VA.isRegLoc();
3659 
3660  if (Flags.isByVal()) {
3661  assert(Ins[InsIdx].isOrigArg() && "Byval arguments cannot be implicit");
3662  unsigned FirstByValReg, LastByValReg;
3663  unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3664  CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3665 
3666  assert(Flags.getByValSize() &&
3667  "ByVal args of size 0 should have been ignored by front-end.");
3668  assert(ByValIdx < CCInfo.getInRegsParamsCount());
3669  copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3670  FirstByValReg, LastByValReg, VA, CCInfo);
3671  CCInfo.nextInRegsParam();
3672  continue;
3673  }
3674 
3675  // Arguments stored on registers
3676  if (IsRegLoc) {
3677  MVT RegVT = VA.getLocVT();
3678  Register ArgReg = VA.getLocReg();
3679  const TargetRegisterClass *RC = getRegClassFor(RegVT);
3680 
3681  // Transform the arguments stored on
3682  // physical registers into virtual ones
3683  unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3684  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3685 
3686  ArgValue =
3687  UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3688 
3689  // Handle floating point arguments passed in integer registers and
3690  // long double arguments passed in floating point registers.
3691  if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3692  (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3693  (RegVT == MVT::f64 && ValVT == MVT::i64))
3694  ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3695  else if (ABI.IsO32() && RegVT == MVT::i32 &&
3696  ValVT == MVT::f64) {
3697  assert(VA.needsCustom() && "Expected custom argument for f64 split");
3698  CCValAssign &NextVA = ArgLocs[++i];
3699  unsigned Reg2 =
3700  addLiveIn(DAG.getMachineFunction(), NextVA.getLocReg(), RC);
3701  SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3702  if (!Subtarget.isLittle())
3703  std::swap(ArgValue, ArgValue2);
3704  ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3705  ArgValue, ArgValue2);
3706  }
3707 
3708  InVals.push_back(ArgValue);
3709  } else { // VA.isRegLoc()
3710  MVT LocVT = VA.getLocVT();
3711 
3712  assert(!VA.needsCustom() && "unexpected custom memory argument");
3713 
3714  if (ABI.IsO32()) {
3715  // We ought to be able to use LocVT directly but O32 sets it to i32
3716  // when allocating floating point values to integer registers.
3717  // This shouldn't influence how we load the value into registers unless
3718  // we are targeting softfloat.
3720  LocVT = VA.getValVT();
3721  }
3722 
3723  // Only arguments pased on the stack should make it here.
3724  assert(VA.isMemLoc());
3725 
3726  // The stack pointer offset is relative to the caller stack frame.
3727  int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3728  VA.getLocMemOffset(), true);
3729 
3730  // Create load nodes to retrieve arguments from the stack
3731  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3732  SDValue ArgValue = DAG.getLoad(
3733  LocVT, DL, Chain, FIN,
3735  OutChains.push_back(ArgValue.getValue(1));
3736 
3737  ArgValue =
3738  UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG);
3739 
3740  InVals.push_back(ArgValue);
3741  }
3742  }
3743 
3744  for (unsigned i = 0, e = ArgLocs.size(), InsIdx = 0; i != e; ++i, ++InsIdx) {
3745 
3746  if (ArgLocs[i].needsCustom()) {
3747  ++i;
3748  continue;
3749  }
3750 
3751  // The mips ABIs for returning structs by value requires that we copy
3752  // the sret argument into $v0 for the return. Save the argument into
3753  // a virtual register so that we can access it from the return points.
3754  if (Ins[InsIdx].Flags.isSRet()) {
3755  unsigned Reg = MipsFI->getSRetReturnReg();
3756  if (!Reg) {
3759  MipsFI->setSRetReturnReg(Reg);
3760  }
3761  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3762  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3763  break;
3764  }
3765  }
3766 
3767  if (IsVarArg)
3768  writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3769 
3770  // All stores are grouped in one node to allow the matching between
3771  // the size of Ins and InVals. This only happens when on varg functions
3772  if (!OutChains.empty()) {
3773  OutChains.push_back(Chain);
3774  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3775  }
3776 
3777  return Chain;
3778 }
3779 
3780 //===----------------------------------------------------------------------===//
3781 // Return Value Calling Convention Implementation
3782 //===----------------------------------------------------------------------===//
3783 
3784 bool
3785 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3786  MachineFunction &MF, bool IsVarArg,
3787  const SmallVectorImpl<ISD::OutputArg> &Outs,
3788  LLVMContext &Context) const {
3790  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3791  return CCInfo.CheckReturn(Outs, RetCC_Mips);
3792 }
3793 
3794 bool MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type,
3795  bool IsSigned) const {
3796  if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3797  return true;
3798 
3799  return IsSigned;
3800 }
3801 
3802 SDValue
3803 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3804  const SDLoc &DL,
3805  SelectionDAG &DAG) const {
3806  MachineFunction &MF = DAG.getMachineFunction();
3807  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3808 
3809  MipsFI->setISR();
3810 
3811  return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3812 }
3813 
3814 SDValue
3815 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3816  bool IsVarArg,
3817  const SmallVectorImpl<ISD::OutputArg> &Outs,
3818  const SmallVectorImpl<SDValue> &OutVals,
3819  const SDLoc &DL, SelectionDAG &DAG) const {
3820  // CCValAssign - represent the assignment of
3821  // the return value to a location
3823  MachineFunction &MF = DAG.getMachineFunction();
3824 
3825  // CCState - Info about the registers and stack slot.
3826  MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3827 
3828  // Analyze return values.
3829  CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3830 
3831  SDValue Flag;
3832  SmallVector<SDValue, 4> RetOps(1, Chain);
3833 
3834  // Copy the result values into the output registers.
3835  for (unsigned i = 0; i != RVLocs.size(); ++i) {
3836  SDValue Val = OutVals[i];
3837  CCValAssign &VA = RVLocs[i];
3838  assert(VA.isRegLoc() && "Can only return in registers!");
3839  bool UseUpperBits = false;
3840 
3841  switch (VA.getLocInfo()) {
3842  default:
3843  llvm_unreachable("Unknown loc info!");
3844  case CCValAssign::Full:
3845  break;
3846  case CCValAssign::BCvt:
3847  Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3848  break;
3850  UseUpperBits = true;
3852  case CCValAssign::AExt:
3853  Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3854  break;
3856  UseUpperBits = true;
3858  case CCValAssign::ZExt:
3859  Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3860  break;
3862  UseUpperBits = true;
3864  case CCValAssign::SExt:
3865  Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3866  break;
3867  }
3868 
3869  if (UseUpperBits) {
3870  unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3871  unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3872  Val = DAG.getNode(
3873  ISD::SHL, DL, VA.getLocVT(), Val,
3874  DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3875  }
3876 
3877  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3878 
3879  // Guarantee that all emitted copies are stuck together with flags.
3880  Flag = Chain.getValue(1);
3881  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3882  }
3883 
3884  // The mips ABIs for returning structs by value requires that we copy
3885  // the sret argument into $v0 for the return. We saved the argument into
3886  // a virtual register in the entry block, so now we copy the value out
3887  // and into $v0.
3888  if (MF.getFunction().hasStructRetAttr()) {
3889  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3890  unsigned Reg = MipsFI->getSRetReturnReg();
3891 
3892  if (!Reg)
3893  llvm_unreachable("sret virtual register not created in the entry block");
3894  SDValue Val =
3895  DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3896  unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3897 
3898  Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3899  Flag = Chain.getValue(1);
3900  RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3901  }
3902 
3903  RetOps[0] = Chain; // Update chain.
3904 
3905  // Add the flag if we have it.
3906  if (Flag.getNode())
3907  RetOps.push_back(Flag);
3908 
3909  // ISRs must use "eret".
3910  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3911  return LowerInterruptReturn(RetOps, DL, DAG);
3912 
3913  // Standard return on Mips is a "jr $ra"
3914  return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3915 }
3916 
3917 //===----------------------------------------------------------------------===//
3918 // Mips Inline Assembly Support
3919 //===----------------------------------------------------------------------===//
3920 
3921 /// getConstraintType - Given a constraint letter, return the type of
3922 /// constraint it is for this target.
3924 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3925  // Mips specific constraints
3926  // GCC config/mips/constraints.md
3927  //
3928  // 'd' : An address register. Equivalent to r
3929  // unless generating MIPS16 code.
3930  // 'y' : Equivalent to r; retained for
3931  // backwards compatibility.
3932  // 'c' : A register suitable for use in an indirect
3933  // jump. This will always be $25 for -mabicalls.
3934  // 'l' : The lo register. 1 word storage.
3935  // 'x' : The hilo register pair. Double word storage.
3936  if (Constraint.size() == 1) {
3937  switch (Constraint[0]) {
3938  default : break;
3939  case 'd':
3940  case 'y':
3941  case 'f':
3942  case 'c':
3943  case 'l':
3944  case 'x':
3945  return C_RegisterClass;
3946  case 'R':
3947  return C_Memory;
3948  }
3949  }
3950 
3951  if (Constraint == "ZC")
3952  return C_Memory;
3953 
3954  return TargetLowering::getConstraintType(Constraint);
3955 }
3956 
3957 /// Examine constraint type and operand type and determine a weight value.
3958 /// This object must already have been set up with the operand type
3959 /// and the current alternative constraint selected.
3961 MipsTargetLowering::getSingleConstraintMatchWeight(
3962  AsmOperandInfo &info, const char *constraint) const {
3963  ConstraintWeight weight = CW_Invalid;
3964  Value *CallOperandVal = info.CallOperandVal;
3965  // If we don't have a value, we can't do a match,
3966  // but allow it at the lowest weight.
3967  if (!CallOperandVal)
3968  return CW_Default;
3969  Type *type = CallOperandVal->getType();
3970  // Look at the constraint type.
3971  switch (*constraint) {
3972  default:
3974  break;
3975  case 'd':
3976  case 'y':
3977  if (type->isIntegerTy())
3978  weight = CW_Register;
3979  break;
3980  case 'f': // FPU or MSA register
3981  if (Subtarget.hasMSA() && type->isVectorTy() &&
3982  type->getPrimitiveSizeInBits().getFixedSize() == 128)
3983  weight = CW_Register;
3984  else if (type->isFloatTy())
3985  weight = CW_Register;
3986  break;
3987  case 'c': // $25 for indirect jumps
3988  case 'l': // lo register
3989  case 'x': // hilo register pair
3990  if (type->isIntegerTy())
3991  weight = CW_SpecificReg;
3992  break;
3993  case 'I': // signed 16 bit immediate
3994  case 'J': // integer zero
3995  case 'K': // unsigned 16 bit immediate
3996  case 'L': // signed 32 bit immediate where lower 16 bits are 0
3997  case 'N': // immediate in the range of -65535 to -1 (inclusive)
3998  case 'O': // signed 15 bit immediate (+- 16383)
3999  case 'P': // immediate in the range of 65535 to 1 (inclusive)
4000  if (isa<ConstantInt>(CallOperandVal))
4001  weight = CW_Constant;
4002  break;
4003  case 'R':
4004  weight = CW_Memory;
4005  break;
4006  }
4007  return weight;
4008 }
4009 
4010 /// This is a helper function to parse a physical register string and split it
4011 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
4012 /// that is returned indicates whether parsing was successful. The second flag
4013 /// is true if the numeric part exists.
4014 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
4015  unsigned long long &Reg) {
4016  if (C.front() != '{' || C.back() != '}')
4017  return std::make_pair(false, false);
4018 
4019  // Search for the first numeric character.
4020  StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
4021  I = std::find_if(B, E, isdigit);
4022 
4023  Prefix = StringRef(B, I - B);
4024 
4025  // The second flag is set to false if no numeric characters were found.
4026  if (I == E)
4027  return std::make_pair(true, false);
4028 
4029  // Parse the numeric characters.
4030  return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
4031  true);
4032 }
4033 
4035  ISD::NodeType) const {
4036  bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
4038  return VT.bitsLT(MinVT) ? MinVT : VT;
4039 }
4040 
4041 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
4042 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
4043  const TargetRegisterInfo *TRI =
4045  const TargetRegisterClass *RC;
4046  StringRef Prefix;
4047  unsigned long long Reg;
4048 
4049  std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
4050 
4051  if (!R.first)