PPCISelDAGToDAG.cpp File Reference

#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <new>
#include <tuple>
#include <utility>
#include "PPCGenDAGISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "ppc-isel"
#define	PASS_NAME   "PowerPC DAG->DAG Pattern Instruction Selection"

Enumerations
enum	ICmpInGPRType {   ICGPR_All , ICGPR_None , ICGPR_I32 , ICGPR_I64 ,   ICGPR_NonExtIn , ICGPR_Zext , ICGPR_Sext , ICGPR_ZextI32 ,   ICGPR_SextI32 , ICGPR_ZextI64 , ICGPR_SextI64 }

Functions
	STATISTIC (NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (SignExtensionsAdded, "Number of sign extensions for compare inputs added.")
	STATISTIC (ZeroExtensionsAdded, "Number of zero extensions for compare inputs added.")
	STATISTIC (NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR.")
	STATISTIC (OmittedForNonExtendUses, "Number of compares not eliminated as they have non-extending uses.")
	STATISTIC (NumP9Setb, "Number of compares lowered to setb.")
static bool	hasTocDataAttr (SDValue Val, unsigned PointerSize)
static bool	isInt32Immediate (SDNode *N, unsigned &Imm)
	isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
static bool	isInt64Immediate (SDNode *N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.
static bool	isInt32Immediate (SDValue N, unsigned &Imm)
static bool	isInt64Immediate (SDValue N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.
static unsigned	getBranchHint (unsigned PCC, const FunctionLoweringInfo &FuncInfo, const SDValue &DestMBB)
static bool	isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static bool	isThreadPointerAcquisitionNode (SDValue Base, SelectionDAG *CurDAG)
static bool	canOptimizeTLSDFormToXForm (SelectionDAG *CurDAG, SDValue Base)
static unsigned	allUsesTruncate (SelectionDAG *CurDAG, SDNode *N)
static int	findContiguousZerosAtLeast (uint64_t Imm, unsigned Num)
static SDNode *	selectI64ImmDirect (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)
static SDNode *	selectI64ImmDirectPrefix (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned *InstCnt=nullptr)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, SDNode *N)
static PPC::Predicate	getPredicateForSetCC (ISD::CondCode CC, const EVT &VT, const PPCSubtarget *Subtarget)
static unsigned	getCRIdxForSetCC (ISD::CondCode CC, bool &Invert)
	getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.
static unsigned int	getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
static bool	mayUseP9Setb (SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, bool &NeedSwapOps, bool &IsUnCmp)
static bool	isSWTestOp (SDValue N)
static bool	PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote)
static bool	isVSXSwap (SDValue N)
static bool	isLaneInsensitive (SDValue N)
static void	reduceVSXSwap (SDNode *N, SelectionDAG *DAG)

Variables
cl::opt< bool >	ANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
static cl::opt< bool >	UseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
static cl::opt< bool >	BPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)
static cl::opt< bool >	EnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static cl::opt< bool >	EnableTLSOpt ("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden)
static cl::opt< ICmpInGPRType >	CmpInGPR ("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "ppc-isel"

Definition at line 72 of file PPCISelDAGToDAG.cpp.

PASS_NAME

#define PASS_NAME   "PowerPC DAG->DAG Pattern Instruction Selection"

Definition at line 73 of file PPCISelDAGToDAG.cpp.

Enumeration Type Documentation

ICmpInGPRType

enum ICmpInGPRType

Enumerator
ICGPR_All
ICGPR_None
ICGPR_I32
ICGPR_I64
ICGPR_NonExtIn
ICGPR_Zext
ICGPR_Sext
ICGPR_ZextI32
ICGPR_SextI32
ICGPR_ZextI64
ICGPR_SextI64

Definition at line 114 of file PPCISelDAGToDAG.cpp.

Function Documentation

allUsesTruncate()

static unsigned allUsesTruncate ( SelectionDAG *  CurDAG, SDNode *  N  )

static

Definition at line 965 of file PPCISelDAGToDAG.cpp.

References llvm::MemSDNode::getMemoryVT(), llvm::Use::getOperandNo(), llvm::EVT::getSizeInBits(), N, llvm::ISD::STORE, and llvm::ISD::TRUNCATE.

Referenced by selectI64Imm().

canOptimizeTLSDFormToXForm()

static bool canOptimizeTLSDFormToXForm ( SelectionDAG *  CurDAG, SDValue  Base  )

static

Definition at line 756 of file PPCISelDAGToDAG.cpp.

References llvm::PPCISD::ADD_TLS, llvm::sampleprof::Base, llvm::TargetMachine::getOptLevel(), llvm::SelectionDAG::getTarget(), isThreadPointerAcquisitionNode(), and llvm::PPCISD::TLS_LOCAL_EXEC_MAT_ADDR.

findContiguousZerosAtLeast()

static int findContiguousZerosAtLeast ( uint64_t  Imm, unsigned  Num  )

static

Definition at line 1023 of file PPCISelDAGToDAG.cpp.

References llvm::Hi_32(), and llvm::Lo_32().

Referenced by selectI64ImmDirect().

getBranchHint()

static unsigned getBranchHint ( unsigned  PCC, const FunctionLoweringInfo &  FuncInfo, const SDValue &  DestMBB  )

static

Definition at line 596 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::FunctionLoweringInfo::BPI, llvm::PPC::BR_NO_HINT, llvm::PPC::BR_NONTAKEN_HINT, llvm::PPC::BR_TAKEN_HINT, llvm::dbgs(), llvm::FunctionLoweringInfo::Fn, llvm::MachineBasicBlock::getBasicBlock(), llvm::BasicBlockSDNode::getBasicBlock(), llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::MachineBasicBlock::getName(), llvm::Value::getName(), llvm::Instruction::getNumSuccessors(), llvm::Instruction::getSuccessor(), llvm::BasicBlock::getTerminator(), LLVM_DEBUG, llvm::FunctionLoweringInfo::MBB, std::swap(), and TBB.

getCRIdxForSetCC()

static unsigned getCRIdxForSetCC ( ISD::CondCode  CC, bool &  Invert  )

static

getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.

That is, lt = 0; ge = 0 inverted.

Definition at line 4326 of file PPCISelDAGToDAG.cpp.

References CC, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

getPredicateForSetCC()

static PPC::Predicate getPredicateForSetCC ( ISD::CondCode  CC, const EVT &  VT, const PPCSubtarget *  Subtarget  )

static

Definition at line 4285 of file PPCISelDAGToDAG.cpp.

References CC, llvm::EVT::isFloatingPoint(), llvm_unreachable, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::PPC::PRED_NU, llvm::PPC::PRED_UN, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

getVCmpInst()

static unsigned int getVCmpInst ( MVT  VecVT, ISD::CondCode  CC, bool  HasVSX, bool &  Swap, bool &  Negate  )

static

Definition at line 4359 of file PPCISelDAGToDAG.cpp.

References CC, llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUNE.

hasTocDataAttr()

static bool hasTocDataAttr ( SDValue  Val, unsigned  PointerSize  )

static

Definition at line 513 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::GlobalObject::getAlign(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getPrimitiveSizeInBits(), llvm::GlobalValue::getValueType(), llvm::GlobalVariable::hasAttribute(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::hasLocalLinkage(), llvm::GlobalValue::hasPrivateLinkage(), llvm::Type::isArrayTy(), llvm::Type::isSized(), llvm::Type::isStructTy(), llvm::Type::isVectorTy(), llvm::report_fatal_error(), llvm::Align::value(), and llvm::MaybeAlign::valueOrOne().

isInt32Immediate() [1/2]

static bool isInt32Immediate ( SDNode *  N, unsigned &  Imm  )

static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 566 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, and N.

Referenced by isInt32Immediate(), and isOpcWithIntImmediate().

isInt32Immediate() [2/2]

static bool isInt32Immediate ( SDValue  N, unsigned &  Imm  )

static

Definition at line 586 of file PPCISelDAGToDAG.cpp.

References isInt32Immediate(), and N.

isInt64Immediate() [1/2]

static bool isInt64Immediate ( SDNode *  N, uint64_t &  Imm  )

static

isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 576 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, and N.

Referenced by isInt64Immediate().

isInt64Immediate() [2/2]

static bool isInt64Immediate ( SDValue  N, uint64_t &  Imm  )

static

isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 592 of file PPCISelDAGToDAG.cpp.

References isInt64Immediate(), and N.

isLaneInsensitive()

static bool isLaneInsensitive ( SDValue  N )

static

Definition at line 7491 of file PPCISelDAGToDAG.cpp.

References N.

Referenced by reduceVSXSwap().

isOpcWithIntImmediate()

static bool isOpcWithIntImmediate ( SDNode *  N, unsigned  Opc, unsigned &  Imm  )

static

Definition at line 650 of file PPCISelDAGToDAG.cpp.

References isInt32Immediate(), and N.

isSWTestOp()

static bool isSWTestOp ( SDValue  N )

static

Definition at line 4819 of file PPCISelDAGToDAG.cpp.

References llvm::PPCISD::FTSQRT, llvm::ISD::INTRINSIC_WO_CHAIN, and N.

isThreadPointerAcquisitionNode()

static bool isThreadPointerAcquisitionNode ( SDValue  Base, SelectionDAG *  CurDAG  )

static

Definition at line 712 of file PPCISelDAGToDAG.cpp.

References llvm::PPCISD::ADD_TLS, assert(), llvm::sampleprof::Base, llvm::PPCISD::GET_TPOINTER, llvm::SelectionDAG::getMachineFunction(), llvm::RegisterSDNode::getReg(), llvm::MachineFunction::getSubtarget(), llvm::PPCSubtarget::getThreadPointerRegister(), llvm::PPCISD::LD_GOT_TPREL_L, and llvm::PPCISD::MAT_PCREL_ADDR.

Referenced by canOptimizeTLSDFormToXForm().

isVSXSwap()

static bool isVSXSwap ( SDValue  N )

static

Definition at line 7471 of file PPCISelDAGToDAG.cpp.

References N.

Referenced by reduceVSXSwap().

mayUseP9Setb()

static bool mayUseP9Setb ( SDNode *  N, const ISD::CondCode &  CC, SelectionDAG *  DAG, bool &  NeedSwapOps, bool &  IsUnCmp  )

static

Definition at line 4679 of file PPCISelDAGToDAG.cpp.

References assert(), CC, llvm::dbgs(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::hasOneUse(), LHS, LLVM_DEBUG, N, RHS, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, std::swap(), and llvm::ISD::ZERO_EXTEND.

PeepholePPC64ZExtGather()

static bool PeepholePPC64ZExtGather ( SDValue  Op32, SmallPtrSetImpl< SDNode * > &  ToPromote  )

static

Definition at line 7159 of file PPCISelDAGToDAG.cpp.

References B, llvm::SmallPtrSetImpl< PtrType >::begin(), llvm::SmallPtrSetImpl< PtrType >::end(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDValue::isMachineOpcode(), and PeepholePPC64ZExtGather().

Referenced by PeepholePPC64ZExtGather().

reduceVSXSwap()

static void reduceVSXSwap ( SDNode *  N, SelectionDAG *  DAG  )

static

Definition at line 7540 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getOperand(), isLaneInsensitive(), isVSXSwap(), LHS, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and RHS.

selectI64Imm() [1/2]

static SDNode * selectI64Imm ( SelectionDAG *  CurDAG, const SDLoc &  dl, uint64_t  Imm, unsigned *  InstCnt = nullptr  )

static

Definition at line 1393 of file PPCISelDAGToDAG.cpp.

References llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::Hi_32(), llvm::Lo_32(), selectI64ImmDirect(), and selectI64ImmDirectPrefix().

Referenced by selectI64Imm().

selectI64Imm() [2/2]

static SDNode * selectI64Imm ( SelectionDAG *  CurDAG, SDNode *  N  )

static

Definition at line 1499 of file PPCISelDAGToDAG.cpp.

References allUsesTruncate(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), N, selectI64Imm(), and llvm::SignExtend64().

selectI64ImmDirect()

static SDNode * selectI64ImmDirect ( SelectionDAG *  CurDAG, const SDLoc &  dl, uint64_t  Imm, unsigned &  InstCnt  )

static

Definition at line 1032 of file PPCISelDAGToDAG.cpp.

References assert(), findContiguousZerosAtLeast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), llvm::Lo_32(), and llvm::APInt::rotr().

Referenced by selectI64Imm().

selectI64ImmDirectPrefix()

static SDNode * selectI64ImmDirectPrefix ( SelectionDAG *  CurDAG, const SDLoc &  dl, uint64_t  Imm, unsigned &  InstCnt  )

static

Definition at line 1273 of file PPCISelDAGToDAG.cpp.

References llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), llvm::Lo_32(), llvm::APInt::rotr(), and llvm::APInt::sext().

Referenced by selectI64Imm().

STATISTIC() [1/7]

STATISTIC	(	NumLogicOpsOnComparison	,
		"Number of logical ops on i1 values calculated in GPR."
	)

STATISTIC() [2/7]

STATISTIC	(	NumP9Setb	,
		"Number of compares lowered to setb."
	)

STATISTIC() [3/7]

STATISTIC	(	NumSextSetcc	,
		"Number of (sext(setcc)) nodes expanded into GPR sequence."
	)

STATISTIC() [4/7]

STATISTIC	(	NumZextSetcc	,
		"Number of (zext(setcc)) nodes expanded into GPR sequence."
	)

STATISTIC() [5/7]

STATISTIC	(	OmittedForNonExtendUses	,
		"Number of compares not eliminated as they have non-extending uses."
	)

STATISTIC() [6/7]

STATISTIC	(	SignExtensionsAdded	,
		"Number of sign extensions for compare inputs added."
	)

STATISTIC() [7/7]

STATISTIC	(	ZeroExtensionsAdded	,
		"Number of zero extensions for compare inputs added."
	)

Variable Documentation

ANDIGlueBug

cl::opt< bool > ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)	(	"expose-ppc-andi-glue-bug"	,
		cl::desc("expose the ANDI glue bug on PPC")	,
		cl::Hidden
	)

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

BPermRewriterNoMasking

cl::opt< bool > BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden) ( "ppc-bit-perm-rewriter-stress-rotates"  , cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations")  , cl::Hidden    )

static

CmpInGPR

cl::opt< ICmpInGPRType > CmpInGPR("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result."))) ( "ppc-gpr-icmps"  , cl::Hidden  , cl::init(ICGPR_All)  , cl::desc("Specify the types of comparisons to emit GPR-only code for.")  , cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result."))    )

static

EnableBranchHint

cl::opt< bool > EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden) ( "ppc-use-branch-hint"  , cl::init(true)  , cl::desc("Enable static hinting of branches on ppc")  , cl::Hidden    )

static

EnableTLSOpt

cl::opt< bool > EnableTLSOpt("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden) ( "ppc-tls-opt"  , cl::init(true)  , cl::desc("Enable tls optimization peephole")  , cl::Hidden    )

static

UseBitPermRewriter

cl::opt< bool > UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden) ( "ppc-use-bit-perm-rewriter"  , cl::init(true)  , cl::desc("use aggressive ppc isel for bit permutations")  , cl::Hidden    )

static