LLVM
15.0.0git
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#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <new>
#include <tuple>
#include <utility>
#include "PPCGenDAGISel.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "ppc-codegen" |
Enumerations | |
enum | ICmpInGPRType { ICGPR_All, ICGPR_None, ICGPR_I32, ICGPR_I64, ICGPR_NonExtIn, ICGPR_Zext, ICGPR_Sext, ICGPR_ZextI32, ICGPR_SextI32, ICGPR_ZextI64, ICGPR_SextI64 } |
Functions | |
STATISTIC (NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence.") | |
STATISTIC (NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence.") | |
STATISTIC (SignExtensionsAdded, "Number of sign extensions for compare inputs added.") | |
STATISTIC (ZeroExtensionsAdded, "Number of zero extensions for compare inputs added.") | |
STATISTIC (NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR.") | |
STATISTIC (OmittedForNonExtendUses, "Number of compares not eliminated as they have non-extending uses.") | |
STATISTIC (NumP9Setb, "Number of compares lowered to setb.") | |
static bool | hasTocDataAttr (SDValue Val, unsigned PointerSize) |
static bool | isInt32Immediate (SDNode *N, unsigned &Imm) |
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More... | |
static bool | isInt64Immediate (SDNode *N, uint64_t &Imm) |
isInt64Immediate - This method tests to see if the node is a 64-bit constant operand. More... | |
static bool | isInt32Immediate (SDValue N, unsigned &Imm) |
static bool | isInt64Immediate (SDValue N, uint64_t &Imm) |
isInt64Immediate - This method tests to see if the value is a 64-bit constant operand. More... | |
static unsigned | getBranchHint (unsigned PCC, const FunctionLoweringInfo &FuncInfo, const SDValue &DestMBB) |
static bool | isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm) |
static unsigned | allUsesTruncate (SelectionDAG *CurDAG, SDNode *N) |
static int | findContiguousZerosAtLeast (uint64_t Imm, unsigned Num) |
static SDNode * | selectI64ImmDirect (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt) |
static SDNode * | selectI64ImmDirectPrefix (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt) |
static SDNode * | selectI64Imm (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned *InstCnt=nullptr) |
static SDNode * | selectI64Imm (SelectionDAG *CurDAG, SDNode *N) |
static PPC::Predicate | getPredicateForSetCC (ISD::CondCode CC, const EVT &VT, const PPCSubtarget *Subtarget) |
static unsigned | getCRIdxForSetCC (ISD::CondCode CC, bool &Invert) |
getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted. More... | |
static unsigned int | getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate) |
static bool | mayUseP9Setb (SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, bool &NeedSwapOps, bool &IsUnCmp) |
static bool | isSWTestOp (SDValue N) |
static bool | PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote) |
static bool | isVSXSwap (SDValue N) |
static bool | isLaneInsensitive (SDValue N) |
static void | reduceVSXSwap (SDNode *N, SelectionDAG *DAG) |
Variables | |
cl::opt< bool > | ANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden) |
static cl::opt< bool > | UseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden) |
static cl::opt< bool > | BPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden) |
static cl::opt< bool > | EnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden) |
static cl::opt< bool > | EnableTLSOpt ("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden) |
static cl::opt< ICmpInGPRType > | CmpInGPR ("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result."))) |
#define DEBUG_TYPE "ppc-codegen" |
Definition at line 71 of file PPCISelDAGToDAG.cpp.
enum ICmpInGPRType |
Enumerator | |
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ICGPR_All | |
ICGPR_None | |
ICGPR_I32 | |
ICGPR_I64 | |
ICGPR_NonExtIn | |
ICGPR_Zext | |
ICGPR_Sext | |
ICGPR_ZextI32 | |
ICGPR_SextI32 | |
ICGPR_ZextI64 | |
ICGPR_SextI64 |
Definition at line 112 of file PPCISelDAGToDAG.cpp.
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Definition at line 861 of file PPCISelDAGToDAG.cpp.
References llvm::MemSDNode::getMemoryVT(), llvm::Use::getOperandNo(), llvm::EVT::getSizeInBits(), llvm::max(), N, llvm::ISD::STORE, and llvm::ISD::TRUNCATE.
Referenced by selectI64Imm().
Definition at line 919 of file PPCISelDAGToDAG.cpp.
References llvm::Hi_32(), and llvm::Lo_32().
Referenced by selectI64ImmDirect().
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Definition at line 584 of file PPCISelDAGToDAG.cpp.
References assert(), BB, llvm::FunctionLoweringInfo::BPI, llvm::PPC::BR_NO_HINT, llvm::PPC::BR_NONTAKEN_HINT, llvm::PPC::BR_TAKEN_HINT, llvm::dbgs(), llvm::FunctionLoweringInfo::Fn, llvm::MachineBasicBlock::getBasicBlock(), llvm::BasicBlockSDNode::getBasicBlock(), llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::Value::getName(), llvm::Instruction::getNumSuccessors(), llvm::Instruction::getSuccessor(), LLVM_DEBUG, llvm::max(), llvm::FunctionLoweringInfo::MBB, llvm::min(), and std::swap().
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getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.
That is, lt = 0; ge = 0 inverted.
Definition at line 4153 of file PPCISelDAGToDAG.cpp.
References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
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Definition at line 4112 of file PPCISelDAGToDAG.cpp.
References llvm::PPCSubtarget::hasSPE(), llvm::EVT::isFloatingPoint(), llvm_unreachable, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::PPC::PRED_NU, llvm::PPC::PRED_UN, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.
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Definition at line 4186 of file PPCISelDAGToDAG.cpp.
References llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::MVT::v16i8, llvm::MVT::v1i128, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::MVT::v4i32, and llvm::MVT::v8i16.
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Definition at line 501 of file PPCISelDAGToDAG.cpp.
References assert(), llvm::GlobalObject::getAlign(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getPrimitiveSizeInBits(), llvm::GlobalValue::getValueType(), llvm::GlobalVariable::hasAttribute(), llvm::GlobalValue::hasCommonLinkage(), llvm::GlobalValue::hasLocalLinkage(), llvm::GlobalValue::hasPrivateLinkage(), llvm::Type::isArrayTy(), llvm::Type::isSized(), llvm::Type::isStructTy(), llvm::Type::isVectorTy(), llvm::jitlink::x86_64::PointerSize, llvm::report_fatal_error(), llvm::Align::value(), and llvm::MaybeAlign::valueOrOne().
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isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
If so Imm will receive the 32-bit value.
Definition at line 554 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::MVT::i32, and N.
Referenced by isInt32Immediate(), and isOpcWithIntImmediate().
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Definition at line 574 of file PPCISelDAGToDAG.cpp.
References isInt32Immediate(), and N.
isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.
If so Imm will receive the 64-bit value.
Definition at line 564 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::MVT::i64, and N.
Referenced by isInt64Immediate().
isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.
If so Imm will receive the 64-bit value.
Definition at line 580 of file PPCISelDAGToDAG.cpp.
References isInt64Immediate(), and N.
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Definition at line 7190 of file PPCISelDAGToDAG.cpp.
References N, and llvm::MipsISD::VNOR.
Referenced by reduceVSXSwap().
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Definition at line 638 of file PPCISelDAGToDAG.cpp.
References isInt32Immediate(), and N.
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Definition at line 4646 of file PPCISelDAGToDAG.cpp.
References llvm::PPCISD::FTSQRT, and N.
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Definition at line 7170 of file PPCISelDAGToDAG.cpp.
References N, and llvm::PPCISD::XXPERMDI.
Referenced by reduceVSXSwap().
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Definition at line 4506 of file PPCISelDAGToDAG.cpp.
References assert(), llvm::dbgs(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MVT::i64, LHS, LLVM_DEBUG, LLVM_FALLTHROUGH, N, RHS, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, std::swap(), and llvm::ISD::ZERO_EXTEND.
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Definition at line 6858 of file PPCISelDAGToDAG.cpp.
References llvm::ISD::AND, B, llvm::SmallPtrSetImpl< PtrType >::begin(), llvm::SmallPtrSetImpl< PtrType >::end(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDValue::isMachineOpcode(), and llvm::ISD::OR.
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Definition at line 7239 of file PPCISelDAGToDAG.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), isLaneInsensitive(), llvm::SDNode::isMachineOpcode(), llvm::SDNode::isOnlyUserOf(), isVSXSwap(), LHS, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), RHS, llvm::SDNode::use_begin(), and llvm::SDNode::use_empty().
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Definition at line 1277 of file PPCISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::PPCSubtarget::hasPrefixInstrs(), llvm::MVT::i32, llvm::MVT::i64, llvm::Lo_32(), selectI64ImmDirect(), and selectI64ImmDirectPrefix().
Referenced by selectI64Imm().
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Definition at line 1333 of file PPCISelDAGToDAG.cpp.
References allUsesTruncate(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i64, llvm::isInt< 16 >(), N, selectI64Imm(), and llvm::SignExtend64().
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Definition at line 928 of file PPCISelDAGToDAG.cpp.
References assert(), findContiguousZerosAtLeast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), llvm::MVT::i32, llvm::MVT::i64, llvm::isInt< 16 >(), llvm::isInt< 32 >(), llvm::AArch64CC::LO, llvm::Lo_32(), llvm::APInt::rotr(), and Shift.
Referenced by selectI64Imm().
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Definition at line 1157 of file PPCISelDAGToDAG.cpp.
References llvm::SelectionDAG::getMachineNode(), llvm::APInt::getRawData(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), llvm::MVT::i32, llvm::MVT::i64, llvm::Lo_32(), llvm::APInt::rotr(), llvm::APInt::sext(), and Shift.
Referenced by selectI64Imm().
STATISTIC | ( | OmittedForNonExtendUses | , |
"Number of compares not eliminated as they have non-extending uses." | |||
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cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden) |
Referenced by llvm::PPCTargetLowering::PPCTargetLowering().
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