LLVM 19.0.0git
X86MCInstLower.cpp
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1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower X86 MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
20#include "X86AsmPrinter.h"
22#include "X86RegisterInfo.h"
24#include "X86Subtarget.h"
25#include "llvm/ADT/STLExtras.h"
33#include "llvm/IR/DataLayout.h"
34#include "llvm/IR/GlobalValue.h"
35#include "llvm/IR/Mangler.h"
36#include "llvm/MC/MCAsmInfo.h"
38#include "llvm/MC/MCContext.h"
39#include "llvm/MC/MCExpr.h"
40#include "llvm/MC/MCFixup.h"
41#include "llvm/MC/MCInst.h"
43#include "llvm/MC/MCSection.h"
45#include "llvm/MC/MCStreamer.h"
46#include "llvm/MC/MCSymbol.h"
47#include "llvm/MC/MCSymbolELF.h"
53#include <string>
54
55using namespace llvm;
56
57namespace {
58
59/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
60class X86MCInstLower {
61 MCContext &Ctx;
62 const MachineFunction &MF;
63 const TargetMachine &TM;
64 const MCAsmInfo &MAI;
66
67public:
68 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
69
70 MCOperand LowerMachineOperand(const MachineInstr *MI,
71 const MachineOperand &MO) const;
72 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
73
76
77private:
78 MachineModuleInfoMachO &getMachOMMI() const;
79};
80
81} // end anonymous namespace
82
83/// A RAII helper which defines a region of instructions which can't have
84/// padding added between them for correctness.
89 : OS(OS), OldAllowAutoPadding(OS.getAllowAutoPadding()) {
90 changeAndComment(false);
91 }
93 void changeAndComment(bool b) {
94 if (b == OS.getAllowAutoPadding())
95 return;
97 if (b)
98 OS.emitRawComment("autopadding");
99 else
100 OS.emitRawComment("noautopadding");
101 }
102};
103
104// Emit a minimal sequence of nops spanning NumBytes bytes.
105static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
106 const X86Subtarget *Subtarget);
107
108void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
109 const MCSubtargetInfo &STI,
110 MCCodeEmitter *CodeEmitter) {
111 if (InShadow) {
114 CodeEmitter->encodeInstruction(Inst, Code, Fixups, STI);
115 CurrentShadowSize += Code.size();
116 if (CurrentShadowSize >= RequiredShadowSize)
117 InShadow = false; // The shadow is big enough. Stop counting.
118 }
119}
120
121void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
122 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
123 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
124 InShadow = false;
125 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
126 &MF->getSubtarget<X86Subtarget>());
127 }
128}
129
130void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
131 OutStreamer->emitInstruction(Inst, getSubtargetInfo());
132 SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
133}
134
135X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
136 X86AsmPrinter &asmprinter)
137 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
138 AsmPrinter(asmprinter) {}
139
140MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
141 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
142}
143
144/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
145/// operand to an MCSymbol.
146MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
147 const Triple &TT = TM.getTargetTriple();
148 if (MO.isGlobal() && TT.isOSBinFormatELF())
150
151 const DataLayout &DL = MF.getDataLayout();
152 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
153 "Isn't a symbol reference");
154
155 MCSymbol *Sym = nullptr;
157 StringRef Suffix;
158
159 switch (MO.getTargetFlags()) {
161 // Handle dllimport linkage.
162 Name += "__imp_";
163 break;
165 Name += ".refptr.";
166 break;
169 Suffix = "$non_lazy_ptr";
170 break;
171 }
172
173 if (!Suffix.empty())
174 Name += DL.getPrivateGlobalPrefix();
175
176 if (MO.isGlobal()) {
177 const GlobalValue *GV = MO.getGlobal();
179 } else if (MO.isSymbol()) {
181 } else if (MO.isMBB()) {
182 assert(Suffix.empty());
183 Sym = MO.getMBB()->getSymbol();
184 }
185
186 Name += Suffix;
187 if (!Sym)
188 Sym = Ctx.getOrCreateSymbol(Name);
189
190 // If the target flags on the operand changes the name of the symbol, do that
191 // before we return the symbol.
192 switch (MO.getTargetFlags()) {
193 default:
194 break;
195 case X86II::MO_COFFSTUB: {
196 MachineModuleInfoCOFF &MMICOFF =
197 MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
199 if (!StubSym.getPointer()) {
200 assert(MO.isGlobal() && "Extern symbol not handled yet");
202 AsmPrinter.getSymbol(MO.getGlobal()), true);
203 }
204 break;
205 }
209 getMachOMMI().getGVStubEntry(Sym);
210 if (!StubSym.getPointer()) {
211 assert(MO.isGlobal() && "Extern symbol not handled yet");
215 }
216 break;
217 }
218 }
219
220 return Sym;
221}
222
223MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
224 MCSymbol *Sym) const {
225 // FIXME: We would like an efficient form for this, so we don't have to do a
226 // lot of extra uniquing.
227 const MCExpr *Expr = nullptr;
229
230 switch (MO.getTargetFlags()) {
231 default:
232 llvm_unreachable("Unknown target flag on GV operand");
233 case X86II::MO_NO_FLAG: // No flag.
234 // These affect the name of the symbol, not any suffix.
238 break;
239
240 case X86II::MO_TLVP:
241 RefKind = MCSymbolRefExpr::VK_TLVP;
242 break;
245 // Subtract the pic base.
247 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
248 break;
249 case X86II::MO_SECREL:
251 break;
252 case X86II::MO_TLSGD:
254 break;
255 case X86II::MO_TLSLD:
257 break;
258 case X86II::MO_TLSLDM:
260 break;
263 break;
266 break;
267 case X86II::MO_TPOFF:
269 break;
270 case X86II::MO_DTPOFF:
272 break;
273 case X86II::MO_NTPOFF:
275 break;
278 break;
281 break;
284 break;
285 case X86II::MO_GOT:
286 RefKind = MCSymbolRefExpr::VK_GOT;
287 break;
288 case X86II::MO_GOTOFF:
290 break;
291 case X86II::MO_PLT:
292 RefKind = MCSymbolRefExpr::VK_PLT;
293 break;
294 case X86II::MO_ABS8:
296 break;
299 Expr = MCSymbolRefExpr::create(Sym, Ctx);
300 // Subtract the pic base.
302 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
303 if (MO.isJTI()) {
304 assert(MAI.doesSetDirectiveSuppressReloc());
305 // If .set directive is supported, use it to reduce the number of
306 // relocations the assembler will generate for differences between
307 // local labels. This is only safe when the symbols are in the same
308 // section so we are restricting it to jumptable references.
309 MCSymbol *Label = Ctx.createTempSymbol();
310 AsmPrinter.OutStreamer->emitAssignment(Label, Expr);
311 Expr = MCSymbolRefExpr::create(Label, Ctx);
312 }
313 break;
314 }
315
316 if (!Expr)
317 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
318
319 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
321 Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
322 return MCOperand::createExpr(Expr);
323}
324
325static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
326 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
327}
328
329MCOperand X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
330 const MachineOperand &MO) const {
331 switch (MO.getType()) {
332 default:
333 MI->print(errs());
334 llvm_unreachable("unknown operand type");
336 // Ignore all implicit register operands.
337 if (MO.isImplicit())
338 return MCOperand();
339 return MCOperand::createReg(MO.getReg());
341 return MCOperand::createImm(MO.getImm());
347 return LowerSymbolOperand(MO, MO.getMCSymbol());
353 return LowerSymbolOperand(
356 // Ignore call clobbers.
357 return MCOperand();
358 }
359}
360
361// Replace TAILJMP opcodes with their equivalent opcodes that have encoding
362// information.
363static unsigned convertTailJumpOpcode(unsigned Opcode) {
364 switch (Opcode) {
365 case X86::TAILJMPr:
366 Opcode = X86::JMP32r;
367 break;
368 case X86::TAILJMPm:
369 Opcode = X86::JMP32m;
370 break;
371 case X86::TAILJMPr64:
372 Opcode = X86::JMP64r;
373 break;
374 case X86::TAILJMPm64:
375 Opcode = X86::JMP64m;
376 break;
377 case X86::TAILJMPr64_REX:
378 Opcode = X86::JMP64r_REX;
379 break;
380 case X86::TAILJMPm64_REX:
381 Opcode = X86::JMP64m_REX;
382 break;
383 case X86::TAILJMPd:
384 case X86::TAILJMPd64:
385 Opcode = X86::JMP_1;
386 break;
387 case X86::TAILJMPd_CC:
388 case X86::TAILJMPd64_CC:
389 Opcode = X86::JCC_1;
390 break;
391 }
392
393 return Opcode;
394}
395
396void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
397 OutMI.setOpcode(MI->getOpcode());
398
399 for (const MachineOperand &MO : MI->operands())
400 if (auto Op = LowerMachineOperand(MI, MO); Op.isValid())
401 OutMI.addOperand(Op);
402
403 bool In64BitMode = AsmPrinter.getSubtarget().is64Bit();
404 if (X86::optimizeInstFromVEX3ToVEX2(OutMI, MI->getDesc()) ||
407 X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) ||
408 X86::optimizeMOV(OutMI, In64BitMode) ||
410 return;
411
412 // Handle a few special cases to eliminate operand modifiers.
413 switch (OutMI.getOpcode()) {
414 case X86::LEA64_32r:
415 case X86::LEA64r:
416 case X86::LEA16r:
417 case X86::LEA32r:
418 // LEA should have a segment register, but it must be empty.
420 "Unexpected # of LEA operands");
421 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
422 "LEA has segment specified!");
423 break;
424 case X86::MULX32Hrr:
425 case X86::MULX32Hrm:
426 case X86::MULX64Hrr:
427 case X86::MULX64Hrm: {
428 // Turn into regular MULX by duplicating the destination.
429 unsigned NewOpc;
430 switch (OutMI.getOpcode()) {
431 default: llvm_unreachable("Invalid opcode");
432 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
433 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
434 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
435 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
436 }
437 OutMI.setOpcode(NewOpc);
438 // Duplicate the destination.
439 unsigned DestReg = OutMI.getOperand(0).getReg();
440 OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
441 break;
442 }
443 // CALL64r, CALL64pcrel32 - These instructions used to have
444 // register inputs modeled as normal uses instead of implicit uses. As such,
445 // they we used to truncate off all but the first operand (the callee). This
446 // issue seems to have been fixed at some point. This assert verifies that.
447 case X86::CALL64r:
448 case X86::CALL64pcrel32:
449 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
450 break;
451 case X86::EH_RETURN:
452 case X86::EH_RETURN64: {
453 OutMI = MCInst();
454 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
455 break;
456 }
457 case X86::CLEANUPRET: {
458 // Replace CLEANUPRET with the appropriate RET.
459 OutMI = MCInst();
460 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
461 break;
462 }
463 case X86::CATCHRET: {
464 // Replace CATCHRET with the appropriate RET.
465 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
466 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
467 OutMI = MCInst();
468 OutMI.setOpcode(getRetOpcode(Subtarget));
469 OutMI.addOperand(MCOperand::createReg(ReturnReg));
470 break;
471 }
472 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
473 // instruction.
474 case X86::TAILJMPr:
475 case X86::TAILJMPr64:
476 case X86::TAILJMPr64_REX:
477 case X86::TAILJMPd:
478 case X86::TAILJMPd64:
479 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
481 break;
482 case X86::TAILJMPd_CC:
483 case X86::TAILJMPd64_CC:
484 assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");
486 break;
487 case X86::TAILJMPm:
488 case X86::TAILJMPm64:
489 case X86::TAILJMPm64_REX:
491 "Unexpected number of operands!");
493 break;
494 case X86::MASKMOVDQU:
495 case X86::VMASKMOVDQU:
496 if (In64BitMode)
498 break;
499 case X86::BSF16rm:
500 case X86::BSF16rr:
501 case X86::BSF32rm:
502 case X86::BSF32rr:
503 case X86::BSF64rm:
504 case X86::BSF64rr: {
505 // Add an REP prefix to BSF instructions so that new processors can
506 // recognize as TZCNT, which has better performance than BSF.
507 // BSF and TZCNT have different interpretations on ZF bit. So make sure
508 // it won't be used later.
509 const MachineOperand *FlagDef =
510 MI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr);
511 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->isDead())
513 break;
514 }
515 default:
516 break;
517 }
518}
519
520void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
521 const MachineInstr &MI) {
522 NoAutoPaddingScope NoPadScope(*OutStreamer);
523 bool Is64Bits = getSubtarget().is64Bit();
524 bool Is64BitsLP64 = getSubtarget().isTarget64BitLP64();
525 MCContext &Ctx = OutStreamer->getContext();
526
528 switch (MI.getOpcode()) {
529 case X86::TLS_addr32:
530 case X86::TLS_addr64:
531 case X86::TLS_addrX32:
533 break;
534 case X86::TLS_base_addr32:
536 break;
537 case X86::TLS_base_addr64:
538 case X86::TLS_base_addrX32:
540 break;
541 case X86::TLS_desc32:
542 case X86::TLS_desc64:
544 break;
545 default:
546 llvm_unreachable("unexpected opcode");
547 }
548
550 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
551
552 // Before binutils 2.41, ld has a bogus TLS relaxation error when the GD/LD
553 // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
554 // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by
555 // only using GOT when GOTPCRELX is enabled.
556 // TODO Delete the workaround when rustc no longer relies on the hack
557 bool UseGot = MMI->getModule()->getRtLibUseGOT() &&
559
560 if (SRVK == MCSymbolRefExpr::VK_TLSDESC) {
562 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)),
564 EmitAndCountInstruction(
565 MCInstBuilder(Is64BitsLP64 ? X86::LEA64r : X86::LEA32r)
566 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
567 .addReg(Is64Bits ? X86::RIP : X86::EBX)
568 .addImm(1)
569 .addReg(0)
570 .addExpr(Sym)
571 .addReg(0));
572 EmitAndCountInstruction(
573 MCInstBuilder(Is64Bits ? X86::CALL64m : X86::CALL32m)
574 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
575 .addImm(1)
576 .addReg(0)
577 .addExpr(Expr)
578 .addReg(0));
579 } else if (Is64Bits) {
580 bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD;
581 if (NeedsPadding && Is64BitsLP64)
582 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
583 EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
584 .addReg(X86::RDI)
585 .addReg(X86::RIP)
586 .addImm(1)
587 .addReg(0)
588 .addExpr(Sym)
589 .addReg(0));
590 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr");
591 if (NeedsPadding) {
592 if (!UseGot)
593 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
594 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
595 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
596 }
597 if (UseGot) {
598 const MCExpr *Expr = MCSymbolRefExpr::create(
599 TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx);
600 EmitAndCountInstruction(MCInstBuilder(X86::CALL64m)
601 .addReg(X86::RIP)
602 .addImm(1)
603 .addReg(0)
604 .addExpr(Expr)
605 .addReg(0));
606 } else {
607 EmitAndCountInstruction(
608 MCInstBuilder(X86::CALL64pcrel32)
609 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
611 }
612 } else {
613 if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) {
614 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
615 .addReg(X86::EAX)
616 .addReg(0)
617 .addImm(1)
618 .addReg(X86::EBX)
619 .addExpr(Sym)
620 .addReg(0));
621 } else {
622 EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
623 .addReg(X86::EAX)
624 .addReg(X86::EBX)
625 .addImm(1)
626 .addReg(0)
627 .addExpr(Sym)
628 .addReg(0));
629 }
630
631 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr");
632 if (UseGot) {
633 const MCExpr *Expr =
635 EmitAndCountInstruction(MCInstBuilder(X86::CALL32m)
636 .addReg(X86::EBX)
637 .addImm(1)
638 .addReg(0)
639 .addExpr(Expr)
640 .addReg(0));
641 } else {
642 EmitAndCountInstruction(
643 MCInstBuilder(X86::CALLpcrel32)
644 .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
646 }
647 }
648}
649
650/// Emit the largest nop instruction smaller than or equal to \p NumBytes
651/// bytes. Return the size of nop emitted.
652static unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
653 const X86Subtarget *Subtarget) {
654 // Determine the longest nop which can be efficiently decoded for the given
655 // target cpu. 15-bytes is the longest single NOP instruction, but some
656 // platforms can't decode the longest forms efficiently.
657 unsigned MaxNopLength = 1;
658 if (Subtarget->is64Bit()) {
659 // FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the
660 // IndexReg/BaseReg below need to be updated.
661 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
662 MaxNopLength = 7;
663 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
664 MaxNopLength = 15;
665 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
666 MaxNopLength = 11;
667 else
668 MaxNopLength = 10;
669 } if (Subtarget->is32Bit())
670 MaxNopLength = 2;
671
672 // Cap a single nop emission at the profitable value for the target
673 NumBytes = std::min(NumBytes, MaxNopLength);
674
675 unsigned NopSize;
676 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
677 IndexReg = Displacement = SegmentReg = 0;
678 BaseReg = X86::RAX;
679 ScaleVal = 1;
680 switch (NumBytes) {
681 case 0:
682 llvm_unreachable("Zero nops?");
683 break;
684 case 1:
685 NopSize = 1;
686 Opc = X86::NOOP;
687 break;
688 case 2:
689 NopSize = 2;
690 Opc = X86::XCHG16ar;
691 break;
692 case 3:
693 NopSize = 3;
694 Opc = X86::NOOPL;
695 break;
696 case 4:
697 NopSize = 4;
698 Opc = X86::NOOPL;
699 Displacement = 8;
700 break;
701 case 5:
702 NopSize = 5;
703 Opc = X86::NOOPL;
704 Displacement = 8;
705 IndexReg = X86::RAX;
706 break;
707 case 6:
708 NopSize = 6;
709 Opc = X86::NOOPW;
710 Displacement = 8;
711 IndexReg = X86::RAX;
712 break;
713 case 7:
714 NopSize = 7;
715 Opc = X86::NOOPL;
716 Displacement = 512;
717 break;
718 case 8:
719 NopSize = 8;
720 Opc = X86::NOOPL;
721 Displacement = 512;
722 IndexReg = X86::RAX;
723 break;
724 case 9:
725 NopSize = 9;
726 Opc = X86::NOOPW;
727 Displacement = 512;
728 IndexReg = X86::RAX;
729 break;
730 default:
731 NopSize = 10;
732 Opc = X86::NOOPW;
733 Displacement = 512;
734 IndexReg = X86::RAX;
735 SegmentReg = X86::CS;
736 break;
737 }
738
739 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
740 NopSize += NumPrefixes;
741 for (unsigned i = 0; i != NumPrefixes; ++i)
742 OS.emitBytes("\x66");
743
744 switch (Opc) {
745 default: llvm_unreachable("Unexpected opcode");
746 case X86::NOOP:
747 OS.emitInstruction(MCInstBuilder(Opc), *Subtarget);
748 break;
749 case X86::XCHG16ar:
750 OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX),
751 *Subtarget);
752 break;
753 case X86::NOOPL:
754 case X86::NOOPW:
755 OS.emitInstruction(MCInstBuilder(Opc)
756 .addReg(BaseReg)
757 .addImm(ScaleVal)
758 .addReg(IndexReg)
759 .addImm(Displacement)
760 .addReg(SegmentReg),
761 *Subtarget);
762 break;
763 }
764 assert(NopSize <= NumBytes && "We overemitted?");
765 return NopSize;
766}
767
768/// Emit the optimal amount of multi-byte nops on X86.
769static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
770 const X86Subtarget *Subtarget) {
771 unsigned NopsToEmit = NumBytes;
772 (void)NopsToEmit;
773 while (NumBytes) {
774 NumBytes -= emitNop(OS, NumBytes, Subtarget);
775 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
776 }
777}
778
779void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
780 X86MCInstLower &MCIL) {
781 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
782
783 NoAutoPaddingScope NoPadScope(*OutStreamer);
784
785 StatepointOpers SOpers(&MI);
786 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
787 emitX86Nops(*OutStreamer, PatchBytes, Subtarget);
788 } else {
789 // Lower call target and choose correct opcode
790 const MachineOperand &CallTarget = SOpers.getCallTarget();
791 MCOperand CallTargetMCOp;
792 unsigned CallOpcode;
793 switch (CallTarget.getType()) {
796 CallTargetMCOp = MCIL.LowerSymbolOperand(
797 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
798 CallOpcode = X86::CALL64pcrel32;
799 // Currently, we only support relative addressing with statepoints.
800 // Otherwise, we'll need a scratch register to hold the target
801 // address. You'll fail asserts during load & relocation if this
802 // symbol is to far away. (TODO: support non-relative addressing)
803 break;
805 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
806 CallOpcode = X86::CALL64pcrel32;
807 // Currently, we only support relative addressing with statepoints.
808 // Otherwise, we'll need a scratch register to hold the target
809 // immediate. You'll fail asserts during load & relocation if this
810 // address is to far away. (TODO: support non-relative addressing)
811 break;
813 // FIXME: Add retpoline support and remove this.
814 if (Subtarget->useIndirectThunkCalls())
815 report_fatal_error("Lowering register statepoints with thunks not "
816 "yet implemented.");
817 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
818 CallOpcode = X86::CALL64r;
819 break;
820 default:
821 llvm_unreachable("Unsupported operand type in statepoint call target");
822 break;
823 }
824
825 // Emit call
827 CallInst.setOpcode(CallOpcode);
828 CallInst.addOperand(CallTargetMCOp);
829 OutStreamer->emitInstruction(CallInst, getSubtargetInfo());
830 }
831
832 // Record our statepoint node in the same section used by STACKMAP
833 // and PATCHPOINT
834 auto &Ctx = OutStreamer->getContext();
835 MCSymbol *MILabel = Ctx.createTempSymbol();
836 OutStreamer->emitLabel(MILabel);
837 SM.recordStatepoint(*MILabel, MI);
838}
839
840void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
841 X86MCInstLower &MCIL) {
842 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
843 // <opcode>, <operands>
844
845 NoAutoPaddingScope NoPadScope(*OutStreamer);
846
847 Register DefRegister = FaultingMI.getOperand(0).getReg();
849 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
850 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
851 unsigned Opcode = FaultingMI.getOperand(3).getImm();
852 unsigned OperandsBeginIdx = 4;
853
854 auto &Ctx = OutStreamer->getContext();
855 MCSymbol *FaultingLabel = Ctx.createTempSymbol();
856 OutStreamer->emitLabel(FaultingLabel);
857
858 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
859 FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel);
860
861 MCInst MI;
862 MI.setOpcode(Opcode);
863
864 if (DefRegister != X86::NoRegister)
865 MI.addOperand(MCOperand::createReg(DefRegister));
866
867 for (const MachineOperand &MO :
868 llvm::drop_begin(FaultingMI.operands(), OperandsBeginIdx))
869 if (auto Op = MCIL.LowerMachineOperand(&FaultingMI, MO); Op.isValid())
870 MI.addOperand(Op);
871
872 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
873 OutStreamer->emitInstruction(MI, getSubtargetInfo());
874}
875
876void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
877 X86MCInstLower &MCIL) {
878 bool Is64Bits = Subtarget->is64Bit();
879 MCContext &Ctx = OutStreamer->getContext();
880 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
881 const MCSymbolRefExpr *Op =
883
884 EmitAndCountInstruction(
885 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
886 .addExpr(Op));
887}
888
889void X86AsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
890 assert(std::next(MI.getIterator())->isCall() &&
891 "KCFI_CHECK not followed by a call instruction");
892
893 // Adjust the offset for patchable-function-prefix. X86InstrInfo::getNop()
894 // returns a 1-byte X86::NOOP, which means the offset is the same in
895 // bytes. This assumes that patchable-function-prefix is the same for all
896 // functions.
897 const MachineFunction &MF = *MI.getMF();
898 int64_t PrefixNops = 0;
899 (void)MF.getFunction()
900 .getFnAttribute("patchable-function-prefix")
902 .getAsInteger(10, PrefixNops);
903
904 // KCFI allows indirect calls to any location that's preceded by a valid
905 // type identifier. To avoid encoding the full constant into an instruction,
906 // and thus emitting potential call target gadgets at each indirect call
907 // site, load a negated constant to a register and compare that to the
908 // expected value at the call target.
909 const Register AddrReg = MI.getOperand(0).getReg();
910 const uint32_t Type = MI.getOperand(1).getImm();
911 // The check is immediately before the call. If the call target is in R10,
912 // we can clobber R11 for the check instead.
913 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
914 EmitAndCountInstruction(
915 MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type)));
916 EmitAndCountInstruction(MCInstBuilder(X86::ADD32rm)
917 .addReg(X86::NoRegister)
918 .addReg(TempReg)
919 .addReg(AddrReg)
920 .addImm(1)
921 .addReg(X86::NoRegister)
922 .addImm(-(PrefixNops + 4))
923 .addReg(X86::NoRegister));
924
926 EmitAndCountInstruction(
927 MCInstBuilder(X86::JCC_1)
929 .addImm(X86::COND_E));
930
932 OutStreamer->emitLabel(Trap);
933 EmitAndCountInstruction(MCInstBuilder(X86::TRAP));
935 OutStreamer->emitLabel(Pass);
936}
937
938void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
939 // FIXME: Make this work on non-ELF.
941 report_fatal_error("llvm.asan.check.memaccess only supported on ELF");
942 return;
943 }
944
945 const auto &Reg = MI.getOperand(0).getReg();
946 ASanAccessInfo AccessInfo(MI.getOperand(1).getImm());
947
948 uint64_t ShadowBase;
949 int MappingScale;
950 bool OrShadowOffset;
952 AccessInfo.CompileKernel, &ShadowBase,
953 &MappingScale, &OrShadowOffset);
954
955 StringRef Name = AccessInfo.IsWrite ? "store" : "load";
956 StringRef Op = OrShadowOffset ? "or" : "add";
957 std::string SymName = ("__asan_check_" + Name + "_" + Op + "_" +
958 Twine(1ULL << AccessInfo.AccessSizeIndex) + "_" +
959 TM.getMCRegisterInfo()->getName(Reg.asMCReg()))
960 .str();
961 if (OrShadowOffset)
963 "OrShadowOffset is not supported with optimized callbacks");
964
965 EmitAndCountInstruction(
966 MCInstBuilder(X86::CALL64pcrel32)
969}
970
971void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
972 X86MCInstLower &MCIL) {
973 // PATCHABLE_OP minsize
974
975 NoAutoPaddingScope NoPadScope(*OutStreamer);
976
977 auto NextMI = std::find_if(std::next(MI.getIterator()),
978 MI.getParent()->end().getInstrIterator(),
979 [](auto &II) { return !II.isMetaInstruction(); });
980
982 unsigned MinSize = MI.getOperand(0).getImm();
983
984 if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) {
985 // Lower the next MachineInstr to find its byte size.
986 // If the next instruction is inline assembly, we skip lowering it for now,
987 // and assume we should always generate NOPs.
988 MCInst MCI;
989 MCIL.Lower(&*NextMI, MCI);
990
992 CodeEmitter->encodeInstruction(MCI, Code, Fixups, getSubtargetInfo());
993 }
994
995 if (Code.size() < MinSize) {
996 if (MinSize == 2 && Subtarget->is32Bit() &&
997 Subtarget->isTargetWindowsMSVC() &&
998 (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) {
999 // For compatibility reasons, when targetting MSVC, it is important to
1000 // generate a 'legacy' NOP in the form of a 8B FF MOV EDI, EDI. Some tools
1001 // rely specifically on this pattern to be able to patch a function.
1002 // This is only for 32-bit targets, when using /arch:IA32 or /arch:SSE.
1003 OutStreamer->emitInstruction(
1004 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1005 *Subtarget);
1006 } else {
1007 unsigned NopSize = emitNop(*OutStreamer, MinSize, Subtarget);
1008 assert(NopSize == MinSize && "Could not implement MinSize!");
1009 (void)NopSize;
1010 }
1011 }
1012}
1013
1014// Lower a stackmap of the form:
1015// <id>, <shadowBytes>, ...
1016void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1017 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1018
1019 auto &Ctx = OutStreamer->getContext();
1020 MCSymbol *MILabel = Ctx.createTempSymbol();
1021 OutStreamer->emitLabel(MILabel);
1022
1023 SM.recordStackMap(*MILabel, MI);
1024 unsigned NumShadowBytes = MI.getOperand(1).getImm();
1025 SMShadowTracker.reset(NumShadowBytes);
1026}
1027
1028// Lower a patchpoint of the form:
1029// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1030void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1031 X86MCInstLower &MCIL) {
1032 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1033
1034 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1035
1036 NoAutoPaddingScope NoPadScope(*OutStreamer);
1037
1038 auto &Ctx = OutStreamer->getContext();
1039 MCSymbol *MILabel = Ctx.createTempSymbol();
1040 OutStreamer->emitLabel(MILabel);
1041 SM.recordPatchPoint(*MILabel, MI);
1042
1043 PatchPointOpers opers(&MI);
1044 unsigned ScratchIdx = opers.getNextScratchIdx();
1045 unsigned EncodedBytes = 0;
1046 const MachineOperand &CalleeMO = opers.getCallTarget();
1047
1048 // Check for null target. If target is non-null (i.e. is non-zero or is
1049 // symbolic) then emit a call.
1050 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1051 MCOperand CalleeMCOp;
1052 switch (CalleeMO.getType()) {
1053 default:
1054 /// FIXME: Add a verifier check for bad callee types.
1055 llvm_unreachable("Unrecognized callee operand type.");
1057 if (CalleeMO.getImm())
1058 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1059 break;
1062 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1063 MCIL.GetSymbolFromOperand(CalleeMO));
1064 break;
1065 }
1066
1067 // Emit MOV to materialize the target address and the CALL to target.
1068 // This is encoded with 12-13 bytes, depending on which register is used.
1069 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1070 if (X86II::isX86_64ExtendedReg(ScratchReg))
1071 EncodedBytes = 13;
1072 else
1073 EncodedBytes = 12;
1074
1075 EmitAndCountInstruction(
1076 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1077 // FIXME: Add retpoline support and remove this.
1078 if (Subtarget->useIndirectThunkCalls())
1080 "Lowering patchpoint with thunks not yet implemented.");
1081 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1082 }
1083
1084 // Emit padding.
1085 unsigned NumBytes = opers.getNumPatchBytes();
1086 assert(NumBytes >= EncodedBytes &&
1087 "Patchpoint can't request size less than the length of a call.");
1088
1089 emitX86Nops(*OutStreamer, NumBytes - EncodedBytes, Subtarget);
1090}
1091
1092void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1093 X86MCInstLower &MCIL) {
1094 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1095
1096 NoAutoPaddingScope NoPadScope(*OutStreamer);
1097
1098 // We want to emit the following pattern, which follows the x86 calling
1099 // convention to prepare for the trampoline call to be patched in.
1100 //
1101 // .p2align 1, ...
1102 // .Lxray_event_sled_N:
1103 // jmp +N // jump across the instrumentation sled
1104 // ... // set up arguments in register
1105 // callq __xray_CustomEvent@plt // force dependency to symbol
1106 // ...
1107 // <jump here>
1108 //
1109 // After patching, it would look something like:
1110 //
1111 // nopw (2-byte nop)
1112 // ...
1113 // callq __xrayCustomEvent // already lowered
1114 // ...
1115 //
1116 // ---
1117 // First we emit the label and the jump.
1118 auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1119 OutStreamer->AddComment("# XRay Custom Event Log");
1120 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1121 OutStreamer->emitLabel(CurSled);
1122
1123 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1124 // an operand (computed as an offset from the jmp instruction).
1125 // FIXME: Find another less hacky way do force the relative jump.
1126 OutStreamer->emitBinaryData("\xeb\x0f");
1127
1128 // The default C calling convention will place two arguments into %rcx and
1129 // %rdx -- so we only work with those.
1130 const Register DestRegs[] = {X86::RDI, X86::RSI};
1131 bool UsedMask[] = {false, false};
1132 // Filled out in loop.
1133 Register SrcRegs[] = {0, 0};
1134
1135 // Then we put the operands in the %rdi and %rsi registers. We spill the
1136 // values in the register before we clobber them, and mark them as used in
1137 // UsedMask. In case the arguments are already in the correct register, we use
1138 // emit nops appropriately sized to keep the sled the same size in every
1139 // situation.
1140 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1141 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I));
1142 Op.isValid()) {
1143 assert(Op.isReg() && "Only support arguments in registers");
1144 SrcRegs[I] = getX86SubSuperRegister(Op.getReg(), 64);
1145 assert(SrcRegs[I].isValid() && "Invalid operand");
1146 if (SrcRegs[I] != DestRegs[I]) {
1147 UsedMask[I] = true;
1148 EmitAndCountInstruction(
1149 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1150 } else {
1151 emitX86Nops(*OutStreamer, 4, Subtarget);
1152 }
1153 }
1154
1155 // Now that the register values are stashed, mov arguments into place.
1156 // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1157 // earlier DestReg. We will have already overwritten over the register before
1158 // we can copy from it.
1159 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1160 if (SrcRegs[I] != DestRegs[I])
1161 EmitAndCountInstruction(
1162 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1163
1164 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1165 // name of the trampoline to be implemented by the XRay runtime.
1166 auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1170
1171 // Emit the call instruction.
1172 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1173 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1174
1175 // Restore caller-saved and used registers.
1176 for (unsigned I = sizeof UsedMask; I-- > 0;)
1177 if (UsedMask[I])
1178 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1179 else
1180 emitX86Nops(*OutStreamer, 1, Subtarget);
1181
1182 OutStreamer->AddComment("xray custom event end.");
1183
1184 // Record the sled version. Version 0 of this sled was spelled differently, so
1185 // we let the runtime handle the different offsets we're using. Version 2
1186 // changed the absolute address to a PC-relative address.
1187 recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 2);
1188}
1189
1190void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1191 X86MCInstLower &MCIL) {
1192 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1193
1194 NoAutoPaddingScope NoPadScope(*OutStreamer);
1195
1196 // We want to emit the following pattern, which follows the x86 calling
1197 // convention to prepare for the trampoline call to be patched in.
1198 //
1199 // .p2align 1, ...
1200 // .Lxray_event_sled_N:
1201 // jmp +N // jump across the instrumentation sled
1202 // ... // set up arguments in register
1203 // callq __xray_TypedEvent@plt // force dependency to symbol
1204 // ...
1205 // <jump here>
1206 //
1207 // After patching, it would look something like:
1208 //
1209 // nopw (2-byte nop)
1210 // ...
1211 // callq __xrayTypedEvent // already lowered
1212 // ...
1213 //
1214 // ---
1215 // First we emit the label and the jump.
1216 auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1217 OutStreamer->AddComment("# XRay Typed Event Log");
1218 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1219 OutStreamer->emitLabel(CurSled);
1220
1221 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1222 // an operand (computed as an offset from the jmp instruction).
1223 // FIXME: Find another less hacky way do force the relative jump.
1224 OutStreamer->emitBinaryData("\xeb\x14");
1225
1226 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1227 // so we'll work with those. Or we may be called via SystemV, in which case
1228 // we don't have to do any translation.
1229 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1230 bool UsedMask[] = {false, false, false};
1231
1232 // Will fill out src regs in the loop.
1233 Register SrcRegs[] = {0, 0, 0};
1234
1235 // Then we put the operands in the SystemV registers. We spill the values in
1236 // the registers before we clobber them, and mark them as used in UsedMask.
1237 // In case the arguments are already in the correct register, we emit nops
1238 // appropriately sized to keep the sled the same size in every situation.
1239 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1240 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I));
1241 Op.isValid()) {
1242 // TODO: Is register only support adequate?
1243 assert(Op.isReg() && "Only supports arguments in registers");
1244 SrcRegs[I] = getX86SubSuperRegister(Op.getReg(), 64);
1245 assert(SrcRegs[I].isValid() && "Invalid operand");
1246 if (SrcRegs[I] != DestRegs[I]) {
1247 UsedMask[I] = true;
1248 EmitAndCountInstruction(
1249 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1250 } else {
1251 emitX86Nops(*OutStreamer, 4, Subtarget);
1252 }
1253 }
1254
1255 // In the above loop we only stash all of the destination registers or emit
1256 // nops if the arguments are already in the right place. Doing the actually
1257 // moving is postponed until after all the registers are stashed so nothing
1258 // is clobbers. We've already added nops to account for the size of mov and
1259 // push if the register is in the right place, so we only have to worry about
1260 // emitting movs.
1261 // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1262 // earlier DestReg. We will have already overwritten over the register before
1263 // we can copy from it.
1264 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1265 if (UsedMask[I])
1266 EmitAndCountInstruction(
1267 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1268
1269 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1270 // name of the trampoline to be implemented by the XRay runtime.
1271 auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1275
1276 // Emit the call instruction.
1277 EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1278 .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1279
1280 // Restore caller-saved and used registers.
1281 for (unsigned I = sizeof UsedMask; I-- > 0;)
1282 if (UsedMask[I])
1283 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1284 else
1285 emitX86Nops(*OutStreamer, 1, Subtarget);
1286
1287 OutStreamer->AddComment("xray typed event end.");
1288
1289 // Record the sled version.
1290 recordSled(CurSled, MI, SledKind::TYPED_EVENT, 2);
1291}
1292
1293void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1294 X86MCInstLower &MCIL) {
1295
1296 NoAutoPaddingScope NoPadScope(*OutStreamer);
1297
1298 const Function &F = MF->getFunction();
1299 if (F.hasFnAttribute("patchable-function-entry")) {
1300 unsigned Num;
1301 if (F.getFnAttribute("patchable-function-entry")
1302 .getValueAsString()
1303 .getAsInteger(10, Num))
1304 return;
1305 emitX86Nops(*OutStreamer, Num, Subtarget);
1306 return;
1307 }
1308 // We want to emit the following pattern:
1309 //
1310 // .p2align 1, ...
1311 // .Lxray_sled_N:
1312 // jmp .tmpN
1313 // # 9 bytes worth of noops
1314 //
1315 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1316 // bytes with the following pattern:
1317 //
1318 // mov %r10, <function id, 32-bit> // 6 bytes
1319 // call <relative offset, 32-bits> // 5 bytes
1320 //
1321 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1322 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1323 OutStreamer->emitLabel(CurSled);
1324
1325 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1326 // an operand (computed as an offset from the jmp instruction).
1327 // FIXME: Find another less hacky way do force the relative jump.
1328 OutStreamer->emitBytes("\xeb\x09");
1329 emitX86Nops(*OutStreamer, 9, Subtarget);
1331}
1332
1333void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1334 X86MCInstLower &MCIL) {
1335 NoAutoPaddingScope NoPadScope(*OutStreamer);
1336
1337 // Since PATCHABLE_RET takes the opcode of the return statement as an
1338 // argument, we use that to emit the correct form of the RET that we want.
1339 // i.e. when we see this:
1340 //
1341 // PATCHABLE_RET X86::RET ...
1342 //
1343 // We should emit the RET followed by sleds.
1344 //
1345 // .p2align 1, ...
1346 // .Lxray_sled_N:
1347 // ret # or equivalent instruction
1348 // # 10 bytes worth of noops
1349 //
1350 // This just makes sure that the alignment for the next instruction is 2.
1351 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1352 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1353 OutStreamer->emitLabel(CurSled);
1354 unsigned OpCode = MI.getOperand(0).getImm();
1355 MCInst Ret;
1356 Ret.setOpcode(OpCode);
1357 for (auto &MO : drop_begin(MI.operands()))
1358 if (auto Op = MCIL.LowerMachineOperand(&MI, MO); Op.isValid())
1359 Ret.addOperand(Op);
1360 OutStreamer->emitInstruction(Ret, getSubtargetInfo());
1361 emitX86Nops(*OutStreamer, 10, Subtarget);
1363}
1364
1365void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1366 X86MCInstLower &MCIL) {
1367 MCInst TC;
1368 TC.setOpcode(convertTailJumpOpcode(MI.getOperand(0).getImm()));
1369 // Drop the tail jump opcode.
1370 auto TCOperands = drop_begin(MI.operands());
1371 bool IsConditional = TC.getOpcode() == X86::JCC_1;
1372 MCSymbol *FallthroughLabel;
1373 if (IsConditional) {
1374 // Rewrite:
1375 // je target
1376 //
1377 // To:
1378 // jne .fallthrough
1379 // .p2align 1, ...
1380 // .Lxray_sled_N:
1381 // SLED_CODE
1382 // jmp target
1383 // .fallthrough:
1384 FallthroughLabel = OutContext.createTempSymbol();
1386 *OutStreamer,
1387 MCInstBuilder(X86::JCC_1)
1388 .addExpr(MCSymbolRefExpr::create(FallthroughLabel, OutContext))
1390 static_cast<X86::CondCode>(MI.getOperand(2).getImm()))));
1391 TC.setOpcode(X86::JMP_1);
1392 // Drop the condition code.
1393 TCOperands = drop_end(TCOperands);
1394 }
1395
1396 NoAutoPaddingScope NoPadScope(*OutStreamer);
1397
1398 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1399 // instruction so we lower that particular instruction and its operands.
1400 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1401 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1402 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1403 // tail call much like how we have it in PATCHABLE_RET.
1404 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1405 OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1406 OutStreamer->emitLabel(CurSled);
1408
1409 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1410 // an operand (computed as an offset from the jmp instruction).
1411 // FIXME: Find another less hacky way do force the relative jump.
1412 OutStreamer->emitBytes("\xeb\x09");
1413 emitX86Nops(*OutStreamer, 9, Subtarget);
1414 OutStreamer->emitLabel(Target);
1415 recordSled(CurSled, MI, SledKind::TAIL_CALL, 2);
1416
1417 // Before emitting the instruction, add a comment to indicate that this is
1418 // indeed a tail call.
1419 OutStreamer->AddComment("TAILCALL");
1420 for (auto &MO : TCOperands)
1421 if (auto Op = MCIL.LowerMachineOperand(&MI, MO); Op.isValid())
1422 TC.addOperand(Op);
1423 OutStreamer->emitInstruction(TC, getSubtargetInfo());
1424
1425 if (IsConditional)
1426 OutStreamer->emitLabel(FallthroughLabel);
1427}
1428
1429// Returns instruction preceding MBBI in MachineFunction.
1430// If MBBI is the first instruction of the first basic block, returns null.
1433 const MachineBasicBlock *MBB = MBBI->getParent();
1434 while (MBBI == MBB->begin()) {
1435 if (MBB == &MBB->getParent()->front())
1437 MBB = MBB->getPrevNode();
1438 MBBI = MBB->end();
1439 }
1440 --MBBI;
1441 return MBBI;
1442}
1443
1444static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) {
1445 if (X86II::isKMasked(MI->getDesc().TSFlags)) {
1446 // Skip mask operand.
1447 ++SrcIdx;
1448 if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
1449 // Skip passthru operand.
1450 ++SrcIdx;
1451 }
1452 }
1453 return SrcIdx;
1454}
1455
1457 unsigned SrcOpIdx) {
1458 const MachineOperand &DstOp = MI->getOperand(0);
1460
1461 // Handle AVX512 MASK/MASXZ write mask comments.
1462 // MASK: zmmX {%kY}
1463 // MASKZ: zmmX {%kY} {z}
1464 if (X86II::isKMasked(MI->getDesc().TSFlags)) {
1465 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOpIdx - 1);
1467 CS << " {%" << Mask << "}";
1468 if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
1469 CS << " {z}";
1470 }
1471 }
1472}
1473
1474static void printShuffleMask(raw_ostream &CS, StringRef Src1Name,
1475 StringRef Src2Name, ArrayRef<int> Mask) {
1476 // One source operand, fix the mask to print all elements in one span.
1477 SmallVector<int, 8> ShuffleMask(Mask);
1478 if (Src1Name == Src2Name)
1479 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1480 if (ShuffleMask[i] >= e)
1481 ShuffleMask[i] -= e;
1482
1483 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1484 if (i != 0)
1485 CS << ",";
1486 if (ShuffleMask[i] == SM_SentinelZero) {
1487 CS << "zero";
1488 continue;
1489 }
1490
1491 // Otherwise, it must come from src1 or src2. Print the span of elements
1492 // that comes from this src.
1493 bool isSrc1 = ShuffleMask[i] < (int)e;
1494 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1495
1496 bool IsFirst = true;
1497 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1498 (ShuffleMask[i] < (int)e) == isSrc1) {
1499 if (!IsFirst)
1500 CS << ',';
1501 else
1502 IsFirst = false;
1503 if (ShuffleMask[i] == SM_SentinelUndef)
1504 CS << "u";
1505 else
1506 CS << ShuffleMask[i] % (int)e;
1507 ++i;
1508 }
1509 CS << ']';
1510 --i; // For loop increments element #.
1511 }
1512}
1513
1514static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1515 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1516 std::string Comment;
1517
1518 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1519 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1520 StringRef Src1Name = SrcOp1.isReg()
1522 : "mem";
1523 StringRef Src2Name = SrcOp2.isReg()
1525 : "mem";
1526
1527 raw_string_ostream CS(Comment);
1528 printDstRegisterName(CS, MI, SrcOp1Idx);
1529 CS << " = ";
1530 printShuffleMask(CS, Src1Name, Src2Name, Mask);
1531 CS.flush();
1532
1533 return Comment;
1534}
1535
1536static void printConstant(const APInt &Val, raw_ostream &CS,
1537 bool PrintZero = false) {
1538 if (Val.getBitWidth() <= 64) {
1539 CS << (PrintZero ? 0ULL : Val.getZExtValue());
1540 } else {
1541 // print multi-word constant as (w0,w1)
1542 CS << "(";
1543 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1544 if (i > 0)
1545 CS << ",";
1546 CS << (PrintZero ? 0ULL : Val.getRawData()[i]);
1547 }
1548 CS << ")";
1549 }
1550}
1551
1552static void printConstant(const APFloat &Flt, raw_ostream &CS,
1553 bool PrintZero = false) {
1554 SmallString<32> Str;
1555 // Force scientific notation to distinguish from integers.
1556 if (PrintZero)
1557 APFloat::getZero(Flt.getSemantics()).toString(Str, 0, 0);
1558 else
1559 Flt.toString(Str, 0, 0);
1560 CS << Str;
1561}
1562
1563static void printConstant(const Constant *COp, unsigned BitWidth,
1564 raw_ostream &CS, bool PrintZero = false) {
1565 if (isa<UndefValue>(COp)) {
1566 CS << "u";
1567 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1568 printConstant(CI->getValue(), CS, PrintZero);
1569 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1570 printConstant(CF->getValueAPF(), CS, PrintZero);
1571 } else if (auto *CDS = dyn_cast<ConstantDataSequential>(COp)) {
1572 Type *EltTy = CDS->getElementType();
1573 bool IsInteger = EltTy->isIntegerTy();
1574 bool IsFP = EltTy->isHalfTy() || EltTy->isFloatTy() || EltTy->isDoubleTy();
1575 unsigned EltBits = EltTy->getPrimitiveSizeInBits();
1576 unsigned E = std::min(BitWidth / EltBits, CDS->getNumElements());
1577 assert((BitWidth % EltBits) == 0 && "Element size mismatch");
1578 for (unsigned I = 0; I != E; ++I) {
1579 if (I != 0)
1580 CS << ",";
1581 if (IsInteger)
1582 printConstant(CDS->getElementAsAPInt(I), CS, PrintZero);
1583 else if (IsFP)
1584 printConstant(CDS->getElementAsAPFloat(I), CS, PrintZero);
1585 else
1586 CS << "?";
1587 }
1588 } else if (auto *CV = dyn_cast<ConstantVector>(COp)) {
1589 unsigned EltBits = CV->getType()->getScalarSizeInBits();
1590 unsigned E = std::min(BitWidth / EltBits, CV->getNumOperands());
1591 assert((BitWidth % EltBits) == 0 && "Element size mismatch");
1592 for (unsigned I = 0; I != E; ++I) {
1593 if (I != 0)
1594 CS << ",";
1595 printConstant(CV->getOperand(I), EltBits, CS, PrintZero);
1596 }
1597 } else {
1598 CS << "?";
1599 }
1600}
1601
1602static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer,
1603 int SclWidth, int VecWidth,
1604 const char *ShuffleComment) {
1605 unsigned SrcIdx = getSrcIdx(MI, 1);
1606
1607 std::string Comment;
1608 raw_string_ostream CS(Comment);
1609 printDstRegisterName(CS, MI, SrcIdx);
1610 CS << " = ";
1611
1612 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) {
1613 CS << "[";
1614 printConstant(C, SclWidth, CS);
1615 for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) {
1616 CS << ",";
1617 printConstant(C, SclWidth, CS, true);
1618 }
1619 CS << "]";
1620 OutStreamer.AddComment(CS.str());
1621 return; // early-out
1622 }
1623
1624 // We didn't find a constant load, fallback to a shuffle mask decode.
1625 CS << ShuffleComment;
1626 OutStreamer.AddComment(CS.str());
1627}
1628
1629static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
1630 int Repeats, int BitWidth) {
1631 unsigned SrcIdx = getSrcIdx(MI, 1);
1632 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx)) {
1633 std::string Comment;
1634 raw_string_ostream CS(Comment);
1635 printDstRegisterName(CS, MI, SrcIdx);
1636 CS << " = [";
1637 for (int l = 0; l != Repeats; ++l) {
1638 if (l != 0)
1639 CS << ",";
1640 printConstant(C, BitWidth, CS);
1641 }
1642 CS << "]";
1643 OutStreamer.AddComment(CS.str());
1644 }
1645}
1646
1647static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1648 int SrcEltBits, int DstEltBits, bool IsSext) {
1649 unsigned SrcIdx = getSrcIdx(MI, 1);
1650 auto *C = X86::getConstantFromPool(*MI, SrcIdx);
1651 if (C && C->getType()->getScalarSizeInBits() == unsigned(SrcEltBits)) {
1652 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1653 int NumElts = CDS->getNumElements();
1654 std::string Comment;
1655 raw_string_ostream CS(Comment);
1656 printDstRegisterName(CS, MI, SrcIdx);
1657 CS << " = [";
1658 for (int i = 0; i != NumElts; ++i) {
1659 if (i != 0)
1660 CS << ",";
1661 if (CDS->getElementType()->isIntegerTy()) {
1662 APInt Elt = CDS->getElementAsAPInt(i);
1663 Elt = IsSext ? Elt.sext(DstEltBits) : Elt.zext(DstEltBits);
1664 printConstant(Elt, CS);
1665 } else
1666 CS << "?";
1667 }
1668 CS << "]";
1669 OutStreamer.AddComment(CS.str());
1670 return true;
1671 }
1672 }
1673
1674 return false;
1675}
1676static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1677 int SrcEltBits, int DstEltBits) {
1678 printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, true);
1679}
1680static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1681 int SrcEltBits, int DstEltBits) {
1682 if (printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, false))
1683 return;
1684
1685 // We didn't find a constant load, fallback to a shuffle mask decode.
1686 std::string Comment;
1687 raw_string_ostream CS(Comment);
1689 CS << " = ";
1690
1691 SmallVector<int> Mask;
1692 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1693 assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
1694 "Illegal extension ratio");
1695 DecodeZeroExtendMask(SrcEltBits, DstEltBits, Width / DstEltBits, false, Mask);
1696 printShuffleMask(CS, "mem", "", Mask);
1697
1698 OutStreamer.AddComment(CS.str());
1699}
1700
1701void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1702 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1703 assert((getSubtarget().isOSWindows() || TM.getTargetTriple().isUEFI()) &&
1704 "SEH_ instruction Windows and UEFI only");
1705
1706 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1707 if (EmitFPOData) {
1708 X86TargetStreamer *XTS =
1709 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1710 switch (MI->getOpcode()) {
1711 case X86::SEH_PushReg:
1712 XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1713 break;
1714 case X86::SEH_StackAlloc:
1715 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1716 break;
1717 case X86::SEH_StackAlign:
1718 XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1719 break;
1720 case X86::SEH_SetFrame:
1721 assert(MI->getOperand(1).getImm() == 0 &&
1722 ".cv_fpo_setframe takes no offset");
1723 XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1724 break;
1725 case X86::SEH_EndPrologue:
1726 XTS->emitFPOEndPrologue();
1727 break;
1728 case X86::SEH_SaveReg:
1729 case X86::SEH_SaveXMM:
1730 case X86::SEH_PushFrame:
1731 llvm_unreachable("SEH_ directive incompatible with FPO");
1732 break;
1733 default:
1734 llvm_unreachable("expected SEH_ instruction");
1735 }
1736 return;
1737 }
1738
1739 // Otherwise, use the .seh_ directives for all other Windows platforms.
1740 switch (MI->getOpcode()) {
1741 case X86::SEH_PushReg:
1742 OutStreamer->emitWinCFIPushReg(MI->getOperand(0).getImm());
1743 break;
1744
1745 case X86::SEH_SaveReg:
1746 OutStreamer->emitWinCFISaveReg(MI->getOperand(0).getImm(),
1747 MI->getOperand(1).getImm());
1748 break;
1749
1750 case X86::SEH_SaveXMM:
1751 OutStreamer->emitWinCFISaveXMM(MI->getOperand(0).getImm(),
1752 MI->getOperand(1).getImm());
1753 break;
1754
1755 case X86::SEH_StackAlloc:
1756 OutStreamer->emitWinCFIAllocStack(MI->getOperand(0).getImm());
1757 break;
1758
1759 case X86::SEH_SetFrame:
1760 OutStreamer->emitWinCFISetFrame(MI->getOperand(0).getImm(),
1761 MI->getOperand(1).getImm());
1762 break;
1763
1764 case X86::SEH_PushFrame:
1765 OutStreamer->emitWinCFIPushFrame(MI->getOperand(0).getImm());
1766 break;
1767
1768 case X86::SEH_EndPrologue:
1769 OutStreamer->emitWinCFIEndProlog();
1770 break;
1771
1772 default:
1773 llvm_unreachable("expected SEH_ instruction");
1774 }
1775}
1776
1778 MCStreamer &OutStreamer) {
1779 switch (MI->getOpcode()) {
1780 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1781 // a constant shuffle mask. We won't be able to do this at the MC layer
1782 // because the mask isn't an immediate.
1783 case X86::PSHUFBrm:
1784 case X86::VPSHUFBrm:
1785 case X86::VPSHUFBYrm:
1786 case X86::VPSHUFBZ128rm:
1787 case X86::VPSHUFBZ128rmk:
1788 case X86::VPSHUFBZ128rmkz:
1789 case X86::VPSHUFBZ256rm:
1790 case X86::VPSHUFBZ256rmk:
1791 case X86::VPSHUFBZ256rmkz:
1792 case X86::VPSHUFBZrm:
1793 case X86::VPSHUFBZrmk:
1794 case X86::VPSHUFBZrmkz: {
1795 unsigned SrcIdx = getSrcIdx(MI, 1);
1796 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1797 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1799 DecodePSHUFBMask(C, Width, Mask);
1800 if (!Mask.empty())
1801 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1802 }
1803 break;
1804 }
1805
1806 case X86::VPERMILPSrm:
1807 case X86::VPERMILPSYrm:
1808 case X86::VPERMILPSZ128rm:
1809 case X86::VPERMILPSZ128rmk:
1810 case X86::VPERMILPSZ128rmkz:
1811 case X86::VPERMILPSZ256rm:
1812 case X86::VPERMILPSZ256rmk:
1813 case X86::VPERMILPSZ256rmkz:
1814 case X86::VPERMILPSZrm:
1815 case X86::VPERMILPSZrmk:
1816 case X86::VPERMILPSZrmkz: {
1817 unsigned SrcIdx = getSrcIdx(MI, 1);
1818 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1819 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1821 DecodeVPERMILPMask(C, 32, Width, Mask);
1822 if (!Mask.empty())
1823 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1824 }
1825 break;
1826 }
1827 case X86::VPERMILPDrm:
1828 case X86::VPERMILPDYrm:
1829 case X86::VPERMILPDZ128rm:
1830 case X86::VPERMILPDZ128rmk:
1831 case X86::VPERMILPDZ128rmkz:
1832 case X86::VPERMILPDZ256rm:
1833 case X86::VPERMILPDZ256rmk:
1834 case X86::VPERMILPDZ256rmkz:
1835 case X86::VPERMILPDZrm:
1836 case X86::VPERMILPDZrmk:
1837 case X86::VPERMILPDZrmkz: {
1838 unsigned SrcIdx = getSrcIdx(MI, 1);
1839 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1840 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1842 DecodeVPERMILPMask(C, 64, Width, Mask);
1843 if (!Mask.empty())
1844 OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
1845 }
1846 break;
1847 }
1848
1849 case X86::VPERMIL2PDrm:
1850 case X86::VPERMIL2PSrm:
1851 case X86::VPERMIL2PDYrm:
1852 case X86::VPERMIL2PSYrm: {
1853 assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands + 1) &&
1854 "Unexpected number of operands!");
1855
1856 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
1857 if (!CtrlOp.isImm())
1858 break;
1859
1860 unsigned ElSize;
1861 switch (MI->getOpcode()) {
1862 default: llvm_unreachable("Invalid opcode");
1863 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1864 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1865 }
1866
1867 if (auto *C = X86::getConstantFromPool(*MI, 3)) {
1868 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1870 DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
1871 if (!Mask.empty())
1872 OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask));
1873 }
1874 break;
1875 }
1876
1877 case X86::VPPERMrrm: {
1878 if (auto *C = X86::getConstantFromPool(*MI, 3)) {
1879 unsigned Width = X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1881 DecodeVPPERMMask(C, Width, Mask);
1882 if (!Mask.empty())
1883 OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask));
1884 }
1885 break;
1886 }
1887
1888 case X86::MMX_MOVQ64rm: {
1889 if (auto *C = X86::getConstantFromPool(*MI, 1)) {
1890 std::string Comment;
1891 raw_string_ostream CS(Comment);
1892 const MachineOperand &DstOp = MI->getOperand(0);
1894 if (auto *CF = dyn_cast<ConstantFP>(C)) {
1895 CS << "0x" << toString(CF->getValueAPF().bitcastToAPInt(), 16, false);
1896 OutStreamer.AddComment(CS.str());
1897 }
1898 }
1899 break;
1900 }
1901
1902#define INSTR_CASE(Prefix, Instr, Suffix, Postfix) \
1903 case X86::Prefix##Instr##Suffix##rm##Postfix:
1904
1905#define CASE_ARITH_RM(Instr) \
1906 INSTR_CASE(, Instr, , ) /* SSE */ \
1907 INSTR_CASE(V, Instr, , ) /* AVX-128 */ \
1908 INSTR_CASE(V, Instr, Y, ) /* AVX-256 */ \
1909 INSTR_CASE(V, Instr, Z128, ) \
1910 INSTR_CASE(V, Instr, Z128, k) \
1911 INSTR_CASE(V, Instr, Z128, kz) \
1912 INSTR_CASE(V, Instr, Z256, ) \
1913 INSTR_CASE(V, Instr, Z256, k) \
1914 INSTR_CASE(V, Instr, Z256, kz) \
1915 INSTR_CASE(V, Instr, Z, ) \
1916 INSTR_CASE(V, Instr, Z, k) \
1917 INSTR_CASE(V, Instr, Z, kz)
1918
1919 // TODO: Add additional instructions when useful.
1920 CASE_ARITH_RM(PMADDUBSW) {
1921 unsigned SrcIdx = getSrcIdx(MI, 1);
1922 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1923 if (C->getType()->getScalarSizeInBits() == 8) {
1924 std::string Comment;
1925 raw_string_ostream CS(Comment);
1926 unsigned VectorWidth =
1927 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1928 CS << "[";
1929 printConstant(C, VectorWidth, CS);
1930 CS << "]";
1931 OutStreamer.AddComment(CS.str());
1932 }
1933 }
1934 break;
1935 }
1936
1937 CASE_ARITH_RM(PMADDWD)
1938 CASE_ARITH_RM(PMULLW)
1939 CASE_ARITH_RM(PMULHW)
1940 CASE_ARITH_RM(PMULHUW)
1941 CASE_ARITH_RM(PMULHRSW) {
1942 unsigned SrcIdx = getSrcIdx(MI, 1);
1943 if (auto *C = X86::getConstantFromPool(*MI, SrcIdx + 1)) {
1944 if (C->getType()->getScalarSizeInBits() == 16) {
1945 std::string Comment;
1946 raw_string_ostream CS(Comment);
1947 unsigned VectorWidth =
1948 X86::getVectorRegisterWidth(MI->getDesc().operands()[0]);
1949 CS << "[";
1950 printConstant(C, VectorWidth, CS);
1951 CS << "]";
1952 OutStreamer.AddComment(CS.str());
1953 }
1954 }
1955 break;
1956 }
1957
1958#define MASK_AVX512_CASE(Instr) \
1959 case Instr: \
1960 case Instr##k: \
1961 case Instr##kz:
1962
1963 case X86::MOVSDrm:
1964 case X86::VMOVSDrm:
1965 MASK_AVX512_CASE(X86::VMOVSDZrm)
1966 case X86::MOVSDrm_alt:
1967 case X86::VMOVSDrm_alt:
1968 case X86::VMOVSDZrm_alt:
1969 case X86::MOVQI2PQIrm:
1970 case X86::VMOVQI2PQIrm:
1971 case X86::VMOVQI2PQIZrm:
1972 printZeroUpperMove(MI, OutStreamer, 64, 128, "mem[0],zero");
1973 break;
1974
1975 MASK_AVX512_CASE(X86::VMOVSHZrm)
1976 case X86::VMOVSHZrm_alt:
1977 printZeroUpperMove(MI, OutStreamer, 16, 128,
1978 "mem[0],zero,zero,zero,zero,zero,zero,zero");
1979 break;
1980
1981 case X86::MOVSSrm:
1982 case X86::VMOVSSrm:
1983 MASK_AVX512_CASE(X86::VMOVSSZrm)
1984 case X86::MOVSSrm_alt:
1985 case X86::VMOVSSrm_alt:
1986 case X86::VMOVSSZrm_alt:
1987 case X86::MOVDI2PDIrm:
1988 case X86::VMOVDI2PDIrm:
1989 case X86::VMOVDI2PDIZrm:
1990 printZeroUpperMove(MI, OutStreamer, 32, 128, "mem[0],zero,zero,zero");
1991 break;
1992
1993#define MOV_CASE(Prefix, Suffix) \
1994 case X86::Prefix##MOVAPD##Suffix##rm: \
1995 case X86::Prefix##MOVAPS##Suffix##rm: \
1996 case X86::Prefix##MOVUPD##Suffix##rm: \
1997 case X86::Prefix##MOVUPS##Suffix##rm: \
1998 case X86::Prefix##MOVDQA##Suffix##rm: \
1999 case X86::Prefix##MOVDQU##Suffix##rm:
2000
2001#define MOV_AVX512_CASE(Suffix, Postfix) \
2002 case X86::VMOVDQA64##Suffix##rm##Postfix: \
2003 case X86::VMOVDQA32##Suffix##rm##Postfix: \
2004 case X86::VMOVDQU64##Suffix##rm##Postfix: \
2005 case X86::VMOVDQU32##Suffix##rm##Postfix: \
2006 case X86::VMOVDQU16##Suffix##rm##Postfix: \
2007 case X86::VMOVDQU8##Suffix##rm##Postfix: \
2008 case X86::VMOVAPS##Suffix##rm##Postfix: \
2009 case X86::VMOVAPD##Suffix##rm##Postfix: \
2010 case X86::VMOVUPS##Suffix##rm##Postfix: \
2011 case X86::VMOVUPD##Suffix##rm##Postfix:
2012
2013#define CASE_128_MOV_RM() \
2014 MOV_CASE(, ) /* SSE */ \
2015 MOV_CASE(V, ) /* AVX-128 */ \
2016 MOV_AVX512_CASE(Z128, ) \
2017 MOV_AVX512_CASE(Z128, k) \
2018 MOV_AVX512_CASE(Z128, kz)
2019
2020#define CASE_256_MOV_RM() \
2021 MOV_CASE(V, Y) /* AVX-256 */ \
2022 MOV_AVX512_CASE(Z256, ) \
2023 MOV_AVX512_CASE(Z256, k) \
2024 MOV_AVX512_CASE(Z256, kz) \
2025
2026#define CASE_512_MOV_RM() \
2027 MOV_AVX512_CASE(Z, ) \
2028 MOV_AVX512_CASE(Z, k) \
2029 MOV_AVX512_CASE(Z, kz) \
2030
2031 // For loads from a constant pool to a vector register, print the constant
2032 // loaded.
2034 printBroadcast(MI, OutStreamer, 1, 128);
2035 break;
2037 printBroadcast(MI, OutStreamer, 1, 256);
2038 break;
2040 printBroadcast(MI, OutStreamer, 1, 512);
2041 break;
2042 case X86::VBROADCASTF128rm:
2043 case X86::VBROADCASTI128rm:
2044 MASK_AVX512_CASE(X86::VBROADCASTF32X4Z256rm)
2045 MASK_AVX512_CASE(X86::VBROADCASTF64X2Z128rm)
2046 MASK_AVX512_CASE(X86::VBROADCASTI32X4Z256rm)
2047 MASK_AVX512_CASE(X86::VBROADCASTI64X2Z128rm)
2048 printBroadcast(MI, OutStreamer, 2, 128);
2049 break;
2050 MASK_AVX512_CASE(X86::VBROADCASTF32X4rm)
2051 MASK_AVX512_CASE(X86::VBROADCASTF64X2rm)
2052 MASK_AVX512_CASE(X86::VBROADCASTI32X4rm)
2053 MASK_AVX512_CASE(X86::VBROADCASTI64X2rm)
2054 printBroadcast(MI, OutStreamer, 4, 128);
2055 break;
2056 MASK_AVX512_CASE(X86::VBROADCASTF32X8rm)
2057 MASK_AVX512_CASE(X86::VBROADCASTF64X4rm)
2058 MASK_AVX512_CASE(X86::VBROADCASTI32X8rm)
2059 MASK_AVX512_CASE(X86::VBROADCASTI64X4rm)
2060 printBroadcast(MI, OutStreamer, 2, 256);
2061 break;
2062
2063 // For broadcast loads from a constant pool to a vector register, repeatedly
2064 // print the constant loaded.
2065 case X86::MOVDDUPrm:
2066 case X86::VMOVDDUPrm:
2067 MASK_AVX512_CASE(X86::VMOVDDUPZ128rm)
2068 case X86::VPBROADCASTQrm:
2069 MASK_AVX512_CASE(X86::VPBROADCASTQZ128rm)
2070 printBroadcast(MI, OutStreamer, 2, 64);
2071 break;
2072 case X86::VBROADCASTSDYrm:
2073 MASK_AVX512_CASE(X86::VBROADCASTSDZ256rm)
2074 case X86::VPBROADCASTQYrm:
2075 MASK_AVX512_CASE(X86::VPBROADCASTQZ256rm)
2076 printBroadcast(MI, OutStreamer, 4, 64);
2077 break;
2078 MASK_AVX512_CASE(X86::VBROADCASTSDZrm)
2079 MASK_AVX512_CASE(X86::VPBROADCASTQZrm)
2080 printBroadcast(MI, OutStreamer, 8, 64);
2081 break;
2082 case X86::VBROADCASTSSrm:
2083 MASK_AVX512_CASE(X86::VBROADCASTSSZ128rm)
2084 case X86::VPBROADCASTDrm:
2085 MASK_AVX512_CASE(X86::VPBROADCASTDZ128rm)
2086 printBroadcast(MI, OutStreamer, 4, 32);
2087 break;
2088 case X86::VBROADCASTSSYrm:
2089 MASK_AVX512_CASE(X86::VBROADCASTSSZ256rm)
2090 case X86::VPBROADCASTDYrm:
2091 MASK_AVX512_CASE(X86::VPBROADCASTDZ256rm)
2092 printBroadcast(MI, OutStreamer, 8, 32);
2093 break;
2094 MASK_AVX512_CASE(X86::VBROADCASTSSZrm)
2095 MASK_AVX512_CASE(X86::VPBROADCASTDZrm)
2096 printBroadcast(MI, OutStreamer, 16, 32);
2097 break;
2098 case X86::VPBROADCASTWrm:
2099 MASK_AVX512_CASE(X86::VPBROADCASTWZ128rm)
2100 printBroadcast(MI, OutStreamer, 8, 16);
2101 break;
2102 case X86::VPBROADCASTWYrm:
2103 MASK_AVX512_CASE(X86::VPBROADCASTWZ256rm)
2104 printBroadcast(MI, OutStreamer, 16, 16);
2105 break;
2106 MASK_AVX512_CASE(X86::VPBROADCASTWZrm)
2107 printBroadcast(MI, OutStreamer, 32, 16);
2108 break;
2109 case X86::VPBROADCASTBrm:
2110 MASK_AVX512_CASE(X86::VPBROADCASTBZ128rm)
2111 printBroadcast(MI, OutStreamer, 16, 8);
2112 break;
2113 case X86::VPBROADCASTBYrm:
2114 MASK_AVX512_CASE(X86::VPBROADCASTBZ256rm)
2115 printBroadcast(MI, OutStreamer, 32, 8);
2116 break;
2117 MASK_AVX512_CASE(X86::VPBROADCASTBZrm)
2118 printBroadcast(MI, OutStreamer, 64, 8);
2119 break;
2120
2121#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2122 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
2123
2124#define CASE_MOVX_RM(Ext, Type) \
2125 MOVX_CASE(, Ext, Type, , ) \
2126 MOVX_CASE(V, Ext, Type, , ) \
2127 MOVX_CASE(V, Ext, Type, Y, ) \
2128 MOVX_CASE(V, Ext, Type, Z128, ) \
2129 MOVX_CASE(V, Ext, Type, Z128, k ) \
2130 MOVX_CASE(V, Ext, Type, Z128, kz ) \
2131 MOVX_CASE(V, Ext, Type, Z256, ) \
2132 MOVX_CASE(V, Ext, Type, Z256, k ) \
2133 MOVX_CASE(V, Ext, Type, Z256, kz ) \
2134 MOVX_CASE(V, Ext, Type, Z, ) \
2135 MOVX_CASE(V, Ext, Type, Z, k ) \
2136 MOVX_CASE(V, Ext, Type, Z, kz )
2137
2138 CASE_MOVX_RM(SX, BD)
2139 printSignExtend(MI, OutStreamer, 8, 32);
2140 break;
2141 CASE_MOVX_RM(SX, BQ)
2142 printSignExtend(MI, OutStreamer, 8, 64);
2143 break;
2144 CASE_MOVX_RM(SX, BW)
2145 printSignExtend(MI, OutStreamer, 8, 16);
2146 break;
2147 CASE_MOVX_RM(SX, DQ)
2148 printSignExtend(MI, OutStreamer, 32, 64);
2149 break;
2150 CASE_MOVX_RM(SX, WD)
2151 printSignExtend(MI, OutStreamer, 16, 32);
2152 break;
2153 CASE_MOVX_RM(SX, WQ)
2154 printSignExtend(MI, OutStreamer, 16, 64);
2155 break;
2156
2157 CASE_MOVX_RM(ZX, BD)
2158 printZeroExtend(MI, OutStreamer, 8, 32);
2159 break;
2160 CASE_MOVX_RM(ZX, BQ)
2161 printZeroExtend(MI, OutStreamer, 8, 64);
2162 break;
2163 CASE_MOVX_RM(ZX, BW)
2164 printZeroExtend(MI, OutStreamer, 8, 16);
2165 break;
2166 CASE_MOVX_RM(ZX, DQ)
2167 printZeroExtend(MI, OutStreamer, 32, 64);
2168 break;
2169 CASE_MOVX_RM(ZX, WD)
2170 printZeroExtend(MI, OutStreamer, 16, 32);
2171 break;
2172 CASE_MOVX_RM(ZX, WQ)
2173 printZeroExtend(MI, OutStreamer, 16, 64);
2174 break;
2175 }
2176}
2177
2179 // FIXME: Enable feature predicate checks once all the test pass.
2180 // X86_MC::verifyInstructionPredicates(MI->getOpcode(),
2181 // Subtarget->getFeatureBits());
2182
2183 X86MCInstLower MCInstLowering(*MF, *this);
2184 const X86RegisterInfo *RI =
2185 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
2186
2187 if (MI->getOpcode() == X86::OR64rm) {
2188 for (auto &Opd : MI->operands()) {
2189 if (Opd.isSymbol() && StringRef(Opd.getSymbolName()) ==
2190 "swift_async_extendedFramePointerFlags") {
2191 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags = true;
2192 }
2193 }
2194 }
2195
2196 // Add comments for values loaded from constant pool.
2197 if (OutStreamer->isVerboseAsm())
2199
2200 // Add a comment about EVEX compression
2202 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY)
2203 OutStreamer->AddComment("EVEX TO LEGACY Compression ", false);
2204 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
2205 OutStreamer->AddComment("EVEX TO VEX Compression ", false);
2206 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_EVEX)
2207 OutStreamer->AddComment("EVEX TO EVEX Compression ", false);
2208 }
2209
2210 switch (MI->getOpcode()) {
2211 case TargetOpcode::DBG_VALUE:
2212 llvm_unreachable("Should be handled target independently");
2213
2214 case X86::EH_RETURN:
2215 case X86::EH_RETURN64: {
2216 // Lower these as normal, but add some comments.
2217 Register Reg = MI->getOperand(0).getReg();
2218 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
2220 break;
2221 }
2222 case X86::CLEANUPRET: {
2223 // Lower these as normal, but add some comments.
2224 OutStreamer->AddComment("CLEANUPRET");
2225 break;
2226 }
2227
2228 case X86::CATCHRET: {
2229 // Lower these as normal, but add some comments.
2230 OutStreamer->AddComment("CATCHRET");
2231 break;
2232 }
2233
2234 case X86::ENDBR32:
2235 case X86::ENDBR64: {
2236 // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
2237 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
2238 // non-empty. If MI is the initial ENDBR, place the
2239 // __patchable_function_entries label after ENDBR.
2242 MI == &MF->front().front()) {
2243 MCInst Inst;
2244 MCInstLowering.Lower(MI, Inst);
2245 EmitAndCountInstruction(Inst);
2248 return;
2249 }
2250 break;
2251 }
2252
2253 case X86::TAILJMPd64:
2254 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11))
2255 EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX));
2256 [[fallthrough]];
2257 case X86::TAILJMPr:
2258 case X86::TAILJMPm:
2259 case X86::TAILJMPd:
2260 case X86::TAILJMPd_CC:
2261 case X86::TAILJMPr64:
2262 case X86::TAILJMPm64:
2263 case X86::TAILJMPd64_CC:
2264 case X86::TAILJMPr64_REX:
2265 case X86::TAILJMPm64_REX:
2266 // Lower these as normal, but add some comments.
2267 OutStreamer->AddComment("TAILCALL");
2268 break;
2269
2270 case X86::TLS_addr32:
2271 case X86::TLS_addr64:
2272 case X86::TLS_addrX32:
2273 case X86::TLS_base_addr32:
2274 case X86::TLS_base_addr64:
2275 case X86::TLS_base_addrX32:
2276 case X86::TLS_desc32:
2277 case X86::TLS_desc64:
2278 return LowerTlsAddr(MCInstLowering, *MI);
2279
2280 case X86::MOVPC32r: {
2281 // This is a pseudo op for a two instruction sequence with a label, which
2282 // looks like:
2283 // call "L1$pb"
2284 // "L1$pb":
2285 // popl %esi
2286
2287 // Emit the call.
2288 MCSymbol *PICBase = MF->getPICBaseSymbol();
2289 // FIXME: We would like an efficient form for this, so we don't have to do a
2290 // lot of extra uniquing.
2291 EmitAndCountInstruction(
2292 MCInstBuilder(X86::CALLpcrel32)
2293 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
2294
2295 const X86FrameLowering *FrameLowering =
2296 MF->getSubtarget<X86Subtarget>().getFrameLowering();
2297 bool hasFP = FrameLowering->hasFP(*MF);
2298
2299 // TODO: This is needed only if we require precise CFA.
2300 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
2301 !OutStreamer->getDwarfFrameInfos().back().End;
2302
2303 int stackGrowth = -RI->getSlotSize();
2304
2305 if (HasActiveDwarfFrame && !hasFP) {
2306 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2307 MF->getInfo<X86MachineFunctionInfo>()->setHasCFIAdjustCfa(true);
2308 }
2309
2310 // Emit the label.
2311 OutStreamer->emitLabel(PICBase);
2312
2313 // popl $reg
2314 EmitAndCountInstruction(
2315 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
2316
2317 if (HasActiveDwarfFrame && !hasFP) {
2318 OutStreamer->emitCFIAdjustCfaOffset(stackGrowth);
2319 }
2320 return;
2321 }
2322
2323 case X86::ADD32ri: {
2324 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
2325 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
2326 break;
2327
2328 // Okay, we have something like:
2329 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
2330
2331 // For this, we want to print something like:
2332 // MYGLOBAL + (. - PICBASE)
2333 // However, we can't generate a ".", so just emit a new label here and refer
2334 // to it.
2336 OutStreamer->emitLabel(DotSym);
2337
2338 // Now that we have emitted the label, lower the complex operand expression.
2339 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
2340
2341 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
2342 const MCExpr *PICBase =
2344 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
2345
2346 DotExpr = MCBinaryExpr::createAdd(
2348
2349 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
2350 .addReg(MI->getOperand(0).getReg())
2351 .addReg(MI->getOperand(1).getReg())
2352 .addExpr(DotExpr));
2353 return;
2354 }
2355 case TargetOpcode::STATEPOINT:
2356 return LowerSTATEPOINT(*MI, MCInstLowering);
2357
2358 case TargetOpcode::FAULTING_OP:
2359 return LowerFAULTING_OP(*MI, MCInstLowering);
2360
2361 case TargetOpcode::FENTRY_CALL:
2362 return LowerFENTRY_CALL(*MI, MCInstLowering);
2363
2364 case TargetOpcode::PATCHABLE_OP:
2365 return LowerPATCHABLE_OP(*MI, MCInstLowering);
2366
2367 case TargetOpcode::STACKMAP:
2368 return LowerSTACKMAP(*MI);
2369
2370 case TargetOpcode::PATCHPOINT:
2371 return LowerPATCHPOINT(*MI, MCInstLowering);
2372
2373 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2374 return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
2375
2376 case TargetOpcode::PATCHABLE_RET:
2377 return LowerPATCHABLE_RET(*MI, MCInstLowering);
2378
2379 case TargetOpcode::PATCHABLE_TAIL_CALL:
2380 return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
2381
2382 case TargetOpcode::PATCHABLE_EVENT_CALL:
2383 return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
2384
2385 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2386 return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
2387
2388 case X86::MORESTACK_RET:
2389 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2390 return;
2391
2392 case X86::KCFI_CHECK:
2393 return LowerKCFI_CHECK(*MI);
2394
2395 case X86::ASAN_CHECK_MEMACCESS:
2396 return LowerASAN_CHECK_MEMACCESS(*MI);
2397
2398 case X86::MORESTACK_RET_RESTORE_R10:
2399 // Return, then restore R10.
2400 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2401 EmitAndCountInstruction(
2402 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2403 return;
2404
2405 case X86::SEH_PushReg:
2406 case X86::SEH_SaveReg:
2407 case X86::SEH_SaveXMM:
2408 case X86::SEH_StackAlloc:
2409 case X86::SEH_StackAlign:
2410 case X86::SEH_SetFrame:
2411 case X86::SEH_PushFrame:
2412 case X86::SEH_EndPrologue:
2413 EmitSEHInstruction(MI);
2414 return;
2415
2416 case X86::SEH_Epilogue: {
2417 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
2419 // Check if preceded by a call and emit nop if so.
2420 for (MBBI = PrevCrossBBInst(MBBI);
2423 // Pseudo instructions that aren't a call are assumed to not emit any
2424 // code. If they do, we worst case generate unnecessary noops after a
2425 // call.
2426 if (MBBI->isCall() || !MBBI->isPseudo()) {
2427 if (MBBI->isCall())
2428 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
2429 break;
2430 }
2431 }
2432 return;
2433 }
2434 case X86::UBSAN_UD1:
2435 EmitAndCountInstruction(MCInstBuilder(X86::UD1Lm)
2436 .addReg(X86::EAX)
2437 .addReg(X86::EAX)
2438 .addImm(1)
2439 .addReg(X86::NoRegister)
2440 .addImm(MI->getOperand(0).getImm())
2441 .addReg(X86::NoRegister));
2442 return;
2443 case X86::CALL64pcrel32:
2444 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11))
2445 EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX));
2446 break;
2447 }
2448
2449 MCInst TmpInst;
2450 MCInstLowering.Lower(MI, TmpInst);
2451
2452 // Stackmap shadows cannot include branch targets, so we can count the bytes
2453 // in a call towards the shadow, but must ensure that the no thread returns
2454 // in to the stackmap shadow. The only way to achieve this is if the call
2455 // is at the end of the shadow.
2456 if (MI->isCall()) {
2457 // Count then size of the call towards the shadow
2458 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2459 // Then flush the shadow so that we fill with nops before the call, not
2460 // after it.
2461 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2462 // Then emit the call
2463 OutStreamer->emitInstruction(TmpInst, getSubtargetInfo());
2464 return;
2465 }
2466
2467 EmitAndCountInstruction(TmpInst);
2468}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
std::string Name
Symbol * Sym
Definition: ELF_riscv.cpp:479
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
uint64_t IntrinsicInst * II
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
This file contains some functions that are useful when dealing with strings.
static void printShuffleMask(raw_ostream &CS, StringRef Src1Name, StringRef Src2Name, ArrayRef< int > Mask)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static unsigned getSrcIdx(const MachineInstr *MI, unsigned SrcIdx)
static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, int Repeats, int BitWidth)
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits, bool IsSext)
static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, int SclWidth, int VecWidth, const char *ShuffleComment)
#define MASK_AVX512_CASE(Instr)
#define CASE_ARITH_RM(Instr)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
#define CASE_256_MOV_RM()
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI, unsigned SrcOpIdx)
#define CASE_MOVX_RM(Ext, Type)
static void printConstant(const APInt &Val, raw_ostream &CS, bool PrintZero=false)
static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
#define CASE_512_MOV_RM()
#define CASE_128_MOV_RM()
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
Definition: APFloat.h:1378
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Definition: APFloat.h:982
Class for arbitrary precision integers.
Definition: APInt.h:77
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:981
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1499
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1447
unsigned getNumWords() const
Get the number of words.
Definition: APInt.h:1454
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:954
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:548
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:85
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:704
MCSymbol * CurrentFnBegin
Definition: AsmPrinter.h:201
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:419
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:88
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:103
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
Definition: AsmPrinter.cpp:708
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:106
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:95
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:390
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
Definition: AsmPrinter.h:118
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:100
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:699
StackMaps SM
Definition: AsmPrinter.h:211
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:414
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:391
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Register getReg() const
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:28
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:706
bool hasInternalLinkage() const
Definition: GlobalValue.h:525
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:621
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:83
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:345
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:212
const MCTargetOptions * getTargetOptions() const
Definition: MCContext.h:417
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:61
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:224
void setFlags(unsigned F)
Definition: MCInst.h:200
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
iterator begin()
Definition: MCInst.h:219
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:361
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:120
void setAllowAutoPadding(bool v)
Definition: MCStreamer.h:310
bool getAllowAutoPadding() const
Definition: MCStreamer.h:311
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:205
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
Definition: MachineInstr.h:69
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:682
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:576
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
Definition: Mangler.cpp:120
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Definition: Module.cpp:701
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
MI-level patchpoint operands.
Definition: StackMaps.h:76
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
size_t size() const
Definition: SmallVector.h:91
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:569
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:548
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:538
MI-level Statepoint operands.
Definition: StackMaps.h:158
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:463
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
const Triple & getTargetTriple() const
TargetOptions Options
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isUEFI() const
Tests whether the OS is UEFI.
Definition: Triple.h:619
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:154
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:143
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:157
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:312
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:185
bool useIndirectThunkCalls() const
Definition: X86Subtarget.h:230
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:661
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:679
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1332
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1206
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:427
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:407
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:397
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:484
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition: X86BaseInfo.h:383
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:504
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:466
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:480
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
Definition: X86BaseInfo.h:448
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:472
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:454
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:492
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:392
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:500
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:412
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:419
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
Definition: X86BaseInfo.h:379
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:488
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:476
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:441
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: X86BaseInfo.h:496
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:460
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:387
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:435
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:403
bool isKMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1327
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrNumOperands
Definition: X86BaseInfo.h:36
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
@ AC_EVEX_2_EVEX
Definition: X86InstrInfo.h:43
@ AC_EVEX_2_LEGACY
Definition: X86InstrInfo.h:39
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
NodeAddr< CodeNode * > Code
Definition: RDFGraph.h:388
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
@ SM_SentinelUndef
@ SM_SentinelZero
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto drop_end(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the last N elements excluded.
Definition: STLExtras.h:336
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
#define N
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39