62 "branch-hint-probability-threshold",
63 cl::desc(
"The probability threshold of enabling branch hint."),
117void X86AsmPrinter::StackMapShadowTracker::count(
MCInst &Inst,
124 CurrentShadowSize +=
Code.size();
125 if (CurrentShadowSize >= RequiredShadowSize)
130void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
132 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
134 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
139void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
146 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
162 "Isn't a symbol reference");
178 Suffix =
"$non_lazy_ptr";
183 Name +=
DL.getPrivateGlobalPrefix();
190 }
else if (MO.
isMBB()) {
197 Sym = Ctx.getOrCreateSymbol(
Name);
208 if (!StubSym.getPointer()) {
218 getMachOMMI().getGVStubEntry(
Sym);
236 const MCExpr *Expr =
nullptr;
313 assert(MAI.doesSetDirectiveSuppressReloc());
335 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
375 Opcode = X86::JMP32r;
378 Opcode = X86::JMP32m;
380 case X86::TAILJMPr64:
381 Opcode = X86::JMP64r;
383 case X86::TAILJMPm64:
384 Opcode = X86::JMP64m;
386 case X86::TAILJMPr64_REX:
387 Opcode = X86::JMP64r_REX;
389 case X86::TAILJMPm64_REX:
390 Opcode = X86::JMP64m_REX;
393 case X86::TAILJMPd64:
396 case X86::TAILJMPd_CC:
397 case X86::TAILJMPd64_CC:
409 if (
auto Op = LowerMachineOperand(
MI, MO);
Op.isValid())
412 bool In64BitMode =
AsmPrinter.getSubtarget().is64Bit();
429 "Unexpected # of LEA operands");
431 "LEA has segment specified!");
436 case X86::MULX64Hrm: {
441 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
442 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
443 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
444 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
457 case X86::CALL64pcrel32:
461 case X86::EH_RETURN64: {
466 case X86::CLEANUPRET: {
472 case X86::CATCHRET: {
475 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
484 case X86::TAILJMPr64:
485 case X86::TAILJMPr64_REX:
487 case X86::TAILJMPd64:
491 case X86::TAILJMPd_CC:
492 case X86::TAILJMPd64_CC:
497 case X86::TAILJMPm64:
498 case X86::TAILJMPm64_REX:
500 "Unexpected number of operands!");
503 case X86::MASKMOVDQU:
504 case X86::VMASKMOVDQU:
519 MI->findRegisterDefOperand(X86::EFLAGS,
nullptr);
520 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->
isDead())
529void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
537 switch (
MI.getOpcode()) {
538 case X86::TLS_addr32:
539 case X86::TLS_addr64:
540 case X86::TLS_addrX32:
543 case X86::TLS_base_addr32:
546 case X86::TLS_base_addr64:
547 case X86::TLS_base_addrX32:
550 case X86::TLS_desc32:
551 case X86::TLS_desc64:
559 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
571 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)),
573 EmitAndCountInstruction(
575 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
576 .addReg(Is64Bits ? X86::RIP : X86::EBX)
581 EmitAndCountInstruction(
583 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
588 }
else if (Is64Bits) {
590 if (NeedsPadding && Is64BitsLP64)
616 EmitAndCountInstruction(
651 EmitAndCountInstruction(
666 unsigned MaxNopLength = 1;
667 if (Subtarget->is64Bit()) {
670 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
672 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
674 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
678 }
if (Subtarget->is32Bit())
682 NumBytes = std::min(NumBytes, MaxNopLength);
685 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
686 IndexReg = Displacement = SegmentReg = 0;
744 SegmentReg = X86::CS;
748 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
749 NopSize += NumPrefixes;
750 for (
unsigned i = 0; i != NumPrefixes; ++i)
751 OS.emitBytes(
"\x66");
768 .addImm(Displacement)
773 assert(NopSize <= NumBytes &&
"We overemitted?");
780 unsigned NopsToEmit = NumBytes;
783 NumBytes -=
emitNop(
OS, NumBytes, Subtarget);
784 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
789 X86MCInstLower &MCIL) {
790 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
795 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
802 switch (CallTarget.
getType()) {
805 CallTargetMCOp = MCIL.LowerSymbolOperand(
806 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
807 CallOpcode = X86::CALL64pcrel32;
815 CallOpcode = X86::CALL64pcrel32;
827 CallOpcode = X86::CALL64r;
837 CallInst.addOperand(CallTargetMCOp);
849void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
850 X86MCInstLower &MCIL) {
861 unsigned OperandsBeginIdx = 4;
871 MI.setOpcode(Opcode);
873 if (DefRegister != X86::NoRegister)
878 if (
auto Op = MCIL.LowerMachineOperand(&FaultingMI, MO);
Op.isValid())
886 X86MCInstLower &MCIL) {
887 bool Is64Bits = Subtarget->is64Bit();
893 EmitAndCountInstruction(
894 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
899 assert(std::next(
MI.getIterator())->isCall() &&
900 "KCFI_CHECK not followed by a call instruction");
907 int64_t PrefixNops = 0;
918 const Register AddrReg =
MI.getOperand(0).getReg();
922 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
923 EmitAndCountInstruction(
926 .addReg(X86::NoRegister)
930 .addReg(X86::NoRegister)
931 .addImm(-(PrefixNops + 4))
932 .addReg(X86::NoRegister));
935 EmitAndCountInstruction(
947void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
954 const auto &
Reg =
MI.getOperand(0).getReg();
961 AccessInfo.CompileKernel, &ShadowBase,
962 &MappingScale, &OrShadowOffset);
966 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
967 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
972 "OrShadowOffset is not supported with optimized callbacks");
974 EmitAndCountInstruction(
981 X86MCInstLower &MCIL) {
986 auto NextMI = std::find_if(std::next(
MI.getIterator()),
987 MI.getParent()->end().getInstrIterator(),
988 [](
auto &
II) { return !II.isMetaInstruction(); });
991 unsigned MinSize =
MI.getOperand(0).getImm();
993 if (NextMI !=
MI.getParent()->end() && !NextMI->isInlineAsm()) {
998 MCIL.Lower(&*NextMI, MCI);
1004 if (
Code.size() < MinSize) {
1005 if (MinSize == 2 && Subtarget->is32Bit() &&
1007 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
1013 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1017 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1033 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1034 SMShadowTracker.reset(NumShadowBytes);
1040 X86MCInstLower &MCIL) {
1041 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1053 unsigned ScratchIdx = opers.getNextScratchIdx();
1054 unsigned EncodedBytes = 0;
1071 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1072 MCIL.GetSymbolFromOperand(CalleeMO));
1078 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1084 EmitAndCountInstruction(
1089 "Lowering patchpoint with thunks not yet implemented.");
1090 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1094 unsigned NumBytes = opers.getNumPatchBytes();
1095 assert(NumBytes >= EncodedBytes &&
1096 "Patchpoint can't request size less than the length of a call.");
1101void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1102 X86MCInstLower &MCIL) {
1103 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1128 OutStreamer->AddComment(
"# XRay Custom Event Log");
1139 const Register DestRegs[] = {X86::RDI, X86::RSI};
1140 bool UsedMask[] = {
false,
false};
1149 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1150 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I));
1152 assert(
Op.isReg() &&
"Only support arguments in registers");
1155 if (SrcRegs[
I] != DestRegs[
I]) {
1157 EmitAndCountInstruction(
1168 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1169 if (SrcRegs[
I] != DestRegs[
I])
1170 EmitAndCountInstruction(
1182 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1185 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1187 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1191 OutStreamer->AddComment(
"xray custom event end.");
1199void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1200 X86MCInstLower &MCIL) {
1201 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1226 OutStreamer->AddComment(
"# XRay Typed Event Log");
1238 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1239 bool UsedMask[] = {
false,
false,
false};
1248 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1249 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I));
1252 assert(
Op.isReg() &&
"Only supports arguments in registers");
1255 if (SrcRegs[
I] != DestRegs[
I]) {
1257 EmitAndCountInstruction(
1273 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1275 EmitAndCountInstruction(
1287 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1290 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1292 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1302void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1303 X86MCInstLower &MCIL) {
1308 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1310 if (
F.getFnAttribute(
"patchable-function-entry")
1312 .getAsInteger(10, Num))
1343 X86MCInstLower &MCIL) {
1363 unsigned OpCode =
MI.getOperand(0).getImm();
1365 Ret.setOpcode(OpCode);
1367 if (
auto Op = MCIL.LowerMachineOperand(&
MI, MO);
Op.isValid())
1374void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1375 X86MCInstLower &MCIL) {
1380 bool IsConditional = TC.
getOpcode() == X86::JCC_1;
1382 if (IsConditional) {
1429 for (
auto &MO : TCOperands)
1430 if (
auto Op = MCIL.LowerMachineOperand(&
MI, MO);
Op.isValid())
1466 unsigned SrcOpIdx) {
1476 CS <<
" {%" << Mask <<
"}";
1487 if (Src1Name == Src2Name)
1488 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i)
1489 if (ShuffleMask[i] >= e)
1490 ShuffleMask[i] -= e;
1492 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1502 bool isSrc1 = ShuffleMask[i] < (int)e;
1503 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1505 bool IsFirst =
true;
1507 (ShuffleMask[i] < (
int)e) == isSrc1) {
1515 CS << ShuffleMask[i] % (int)e;
1525 std::string Comment;
1546 bool PrintZero =
false) {
1555 CS << (PrintZero ? 0ULL : Val.
getRawData()[i]);
1562 bool PrintZero =
false) {
1568 Flt.toString(Str, 0, 0);
1574 if (isa<UndefValue>(COp)) {
1576 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1578 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1580 }
else if (
auto *CDS = dyn_cast<ConstantDataSequential>(COp)) {
1581 Type *EltTy = CDS->getElementType();
1585 unsigned E = std::min(
BitWidth / EltBits, CDS->getNumElements());
1587 for (
unsigned I = 0;
I != E; ++
I) {
1597 }
else if (
auto *CV = dyn_cast<ConstantVector>(COp)) {
1598 unsigned EltBits = CV->getType()->getScalarSizeInBits();
1599 unsigned E = std::min(
BitWidth / EltBits, CV->getNumOperands());
1601 for (
unsigned I = 0;
I != E; ++
I) {
1612 int SclWidth,
int VecWidth,
1613 const char *ShuffleComment) {
1616 std::string Comment;
1624 for (
int I = 1, E = VecWidth / SclWidth;
I < E; ++
I) {
1634 CS << ShuffleComment;
1642 std::string Comment;
1646 for (
int l = 0; l != Repeats; ++l) {
1657 int SrcEltBits,
int DstEltBits,
bool IsSext) {
1660 if (
C &&
C->getType()->getScalarSizeInBits() ==
unsigned(SrcEltBits)) {
1661 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
1662 int NumElts = CDS->getNumElements();
1663 std::string Comment;
1667 for (
int i = 0; i != NumElts; ++i) {
1670 if (CDS->getElementType()->isIntegerTy()) {
1671 APInt Elt = CDS->getElementAsAPInt(i);
1672 Elt = IsSext ? Elt.
sext(DstEltBits) : Elt.
zext(DstEltBits);
1686 int SrcEltBits,
int DstEltBits) {
1690 int SrcEltBits,
int DstEltBits) {
1691 if (
printExtend(
MI, OutStreamer, SrcEltBits, DstEltBits,
false))
1695 std::string Comment;
1702 assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
1703 "Illegal extension ratio");
1713 "SEH_ instruction Windows and UEFI only");
1719 switch (
MI->getOpcode()) {
1720 case X86::SEH_PushReg:
1723 case X86::SEH_StackAlloc:
1726 case X86::SEH_StackAlign:
1729 case X86::SEH_SetFrame:
1730 assert(
MI->getOperand(1).getImm() == 0 &&
1731 ".cv_fpo_setframe takes no offset");
1734 case X86::SEH_EndPrologue:
1737 case X86::SEH_SaveReg:
1738 case X86::SEH_SaveXMM:
1739 case X86::SEH_PushFrame:
1749 switch (
MI->getOpcode()) {
1750 case X86::SEH_PushReg:
1754 case X86::SEH_SaveReg:
1756 MI->getOperand(1).getImm());
1759 case X86::SEH_SaveXMM:
1761 MI->getOperand(1).getImm());
1764 case X86::SEH_StackAlloc:
1765 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
1768 case X86::SEH_SetFrame:
1770 MI->getOperand(1).getImm());
1773 case X86::SEH_PushFrame:
1774 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
1777 case X86::SEH_EndPrologue:
1788 switch (
MI->getOpcode()) {
1793 case X86::VPSHUFBrm:
1794 case X86::VPSHUFBYrm:
1795 case X86::VPSHUFBZ128rm:
1796 case X86::VPSHUFBZ128rmk:
1797 case X86::VPSHUFBZ128rmkz:
1798 case X86::VPSHUFBZ256rm:
1799 case X86::VPSHUFBZ256rmk:
1800 case X86::VPSHUFBZ256rmkz:
1801 case X86::VPSHUFBZrm:
1802 case X86::VPSHUFBZrmk:
1803 case X86::VPSHUFBZrmkz: {
1815 case X86::VPERMILPSrm:
1816 case X86::VPERMILPSYrm:
1817 case X86::VPERMILPSZ128rm:
1818 case X86::VPERMILPSZ128rmk:
1819 case X86::VPERMILPSZ128rmkz:
1820 case X86::VPERMILPSZ256rm:
1821 case X86::VPERMILPSZ256rmk:
1822 case X86::VPERMILPSZ256rmkz:
1823 case X86::VPERMILPSZrm:
1824 case X86::VPERMILPSZrmk:
1825 case X86::VPERMILPSZrmkz: {
1836 case X86::VPERMILPDrm:
1837 case X86::VPERMILPDYrm:
1838 case X86::VPERMILPDZ128rm:
1839 case X86::VPERMILPDZ128rmk:
1840 case X86::VPERMILPDZ128rmkz:
1841 case X86::VPERMILPDZ256rm:
1842 case X86::VPERMILPDZ256rmk:
1843 case X86::VPERMILPDZ256rmkz:
1844 case X86::VPERMILPDZrm:
1845 case X86::VPERMILPDZrmk:
1846 case X86::VPERMILPDZrmkz: {
1858 case X86::VPERMIL2PDrm:
1859 case X86::VPERMIL2PSrm:
1860 case X86::VPERMIL2PDYrm:
1861 case X86::VPERMIL2PSYrm: {
1863 "Unexpected number of operands!");
1866 if (!CtrlOp.
isImm())
1870 switch (
MI->getOpcode()) {
1872 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
1873 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
1886 case X86::VPPERMrrm: {
1897 case X86::MMX_MOVQ64rm: {
1899 std::string Comment;
1903 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
1904 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
1911#define INSTR_CASE(Prefix, Instr, Suffix, Postfix) \
1912 case X86::Prefix##Instr##Suffix##rm##Postfix:
1914#define CASE_ARITH_RM(Instr) \
1915 INSTR_CASE(, Instr, , ) \
1916 INSTR_CASE(V, Instr, , ) \
1917 INSTR_CASE(V, Instr, Y, ) \
1918 INSTR_CASE(V, Instr, Z128, ) \
1919 INSTR_CASE(V, Instr, Z128, k) \
1920 INSTR_CASE(V, Instr, Z128, kz) \
1921 INSTR_CASE(V, Instr, Z256, ) \
1922 INSTR_CASE(V, Instr, Z256, k) \
1923 INSTR_CASE(V, Instr, Z256, kz) \
1924 INSTR_CASE(V, Instr, Z, ) \
1925 INSTR_CASE(V, Instr, Z, k) \
1926 INSTR_CASE(V, Instr, Z, kz)
1932 if (
C->getType()->getScalarSizeInBits() == 8) {
1933 std::string Comment;
1935 unsigned VectorWidth =
1953 if (
C->getType()->getScalarSizeInBits() == 16) {
1954 std::string Comment;
1956 unsigned VectorWidth =
1967#define MASK_AVX512_CASE(Instr) \
1975 case X86::MOVSDrm_alt:
1976 case X86::VMOVSDrm_alt:
1977 case X86::VMOVSDZrm_alt:
1978 case X86::MOVQI2PQIrm:
1979 case X86::VMOVQI2PQIrm:
1980 case X86::VMOVQI2PQIZrm:
1985 case X86::VMOVSHZrm_alt:
1987 "mem[0],zero,zero,zero,zero,zero,zero,zero");
1993 case X86::MOVSSrm_alt:
1994 case X86::VMOVSSrm_alt:
1995 case X86::VMOVSSZrm_alt:
1996 case X86::MOVDI2PDIrm:
1997 case X86::VMOVDI2PDIrm:
1998 case X86::VMOVDI2PDIZrm:
2002#define MOV_CASE(Prefix, Suffix) \
2003 case X86::Prefix##MOVAPD##Suffix##rm: \
2004 case X86::Prefix##MOVAPS##Suffix##rm: \
2005 case X86::Prefix##MOVUPD##Suffix##rm: \
2006 case X86::Prefix##MOVUPS##Suffix##rm: \
2007 case X86::Prefix##MOVDQA##Suffix##rm: \
2008 case X86::Prefix##MOVDQU##Suffix##rm:
2010#define MOV_AVX512_CASE(Suffix, Postfix) \
2011 case X86::VMOVDQA64##Suffix##rm##Postfix: \
2012 case X86::VMOVDQA32##Suffix##rm##Postfix: \
2013 case X86::VMOVDQU64##Suffix##rm##Postfix: \
2014 case X86::VMOVDQU32##Suffix##rm##Postfix: \
2015 case X86::VMOVDQU16##Suffix##rm##Postfix: \
2016 case X86::VMOVDQU8##Suffix##rm##Postfix: \
2017 case X86::VMOVAPS##Suffix##rm##Postfix: \
2018 case X86::VMOVAPD##Suffix##rm##Postfix: \
2019 case X86::VMOVUPS##Suffix##rm##Postfix: \
2020 case X86::VMOVUPD##Suffix##rm##Postfix:
2022#define CASE_128_MOV_RM() \
2025 MOV_AVX512_CASE(Z128, ) \
2026 MOV_AVX512_CASE(Z128, k) \
2027 MOV_AVX512_CASE(Z128, kz)
2029#define CASE_256_MOV_RM() \
2031 MOV_AVX512_CASE(Z256, ) \
2032 MOV_AVX512_CASE(Z256, k) \
2033 MOV_AVX512_CASE(Z256, kz) \
2035#define CASE_512_MOV_RM() \
2036 MOV_AVX512_CASE(Z, ) \
2037 MOV_AVX512_CASE(Z, k) \
2038 MOV_AVX512_CASE(Z, kz) \
2051 case X86::VBROADCASTF128rm:
2052 case X86::VBROADCASTI128rm:
2074 case X86::MOVDDUPrm:
2075 case X86::VMOVDDUPrm:
2077 case X86::VPBROADCASTQrm:
2081 case X86::VBROADCASTSDYrm:
2083 case X86::VPBROADCASTQYrm:
2091 case X86::VBROADCASTSSrm:
2093 case X86::VPBROADCASTDrm:
2097 case X86::VBROADCASTSSYrm:
2099 case X86::VPBROADCASTDYrm:
2107 case X86::VPBROADCASTWrm:
2111 case X86::VPBROADCASTWYrm:
2118 case X86::VPBROADCASTBrm:
2122 case X86::VPBROADCASTBYrm:
2130#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2131 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
2133#define CASE_MOVX_RM(Ext, Type) \
2134 MOVX_CASE(, Ext, Type, , ) \
2135 MOVX_CASE(V, Ext, Type, , ) \
2136 MOVX_CASE(V, Ext, Type, Y, ) \
2137 MOVX_CASE(V, Ext, Type, Z128, ) \
2138 MOVX_CASE(V, Ext, Type, Z128, k ) \
2139 MOVX_CASE(V, Ext, Type, Z128, kz ) \
2140 MOVX_CASE(V, Ext, Type, Z256, ) \
2141 MOVX_CASE(V, Ext, Type, Z256, k ) \
2142 MOVX_CASE(V, Ext, Type, Z256, kz ) \
2143 MOVX_CASE(V, Ext, Type, Z, ) \
2144 MOVX_CASE(V, Ext, Type, Z, k ) \
2145 MOVX_CASE(V, Ext, Type, Z, kz )
2192 X86MCInstLower MCInstLowering(*
MF, *
this);
2196 if (
MI->getOpcode() == X86::OR64rm) {
2197 for (
auto &Opd :
MI->operands()) {
2198 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2199 "swift_async_extendedFramePointerFlags") {
2200 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2212 OutStreamer->AddComment(
"EVEX TO LEGACY Compression ",
false);
2214 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2216 OutStreamer->AddComment(
"EVEX TO EVEX Compression ",
false);
2219 switch (
MI->getOpcode()) {
2220 case TargetOpcode::DBG_VALUE:
2223 case X86::EH_RETURN:
2224 case X86::EH_RETURN64: {
2231 case X86::CLEANUPRET: {
2237 case X86::CATCHRET: {
2244 case X86::ENDBR64: {
2253 MCInstLowering.Lower(
MI, Inst);
2254 EmitAndCountInstruction(Inst);
2262 case X86::TAILJMPd64:
2263 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2269 case X86::TAILJMPd_CC:
2270 case X86::TAILJMPr64:
2271 case X86::TAILJMPm64:
2272 case X86::TAILJMPd64_CC:
2273 case X86::TAILJMPr64_REX:
2274 case X86::TAILJMPm64_REX:
2279 case X86::TLS_addr32:
2280 case X86::TLS_addr64:
2281 case X86::TLS_addrX32:
2282 case X86::TLS_base_addr32:
2283 case X86::TLS_base_addr64:
2284 case X86::TLS_base_addrX32:
2285 case X86::TLS_desc32:
2286 case X86::TLS_desc64:
2287 return LowerTlsAddr(MCInstLowering, *
MI);
2289 case X86::MOVPC32r: {
2300 EmitAndCountInstruction(
2306 bool hasFP = FrameLowering->
hasFP(*
MF);
2309 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2314 if (HasActiveDwarfFrame && !hasFP) {
2315 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2323 EmitAndCountInstruction(
2326 if (HasActiveDwarfFrame && !hasFP) {
2332 case X86::ADD32ri: {
2348 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2359 .addReg(
MI->getOperand(0).getReg())
2360 .
addReg(
MI->getOperand(1).getReg())
2364 case TargetOpcode::STATEPOINT:
2365 return LowerSTATEPOINT(*
MI, MCInstLowering);
2367 case TargetOpcode::FAULTING_OP:
2368 return LowerFAULTING_OP(*
MI, MCInstLowering);
2370 case TargetOpcode::FENTRY_CALL:
2371 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2373 case TargetOpcode::PATCHABLE_OP:
2374 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2376 case TargetOpcode::STACKMAP:
2377 return LowerSTACKMAP(*
MI);
2379 case TargetOpcode::PATCHPOINT:
2380 return LowerPATCHPOINT(*
MI, MCInstLowering);
2382 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2383 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2385 case TargetOpcode::PATCHABLE_RET:
2386 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2388 case TargetOpcode::PATCHABLE_TAIL_CALL:
2389 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2391 case TargetOpcode::PATCHABLE_EVENT_CALL:
2392 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2394 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2395 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2397 case X86::MORESTACK_RET:
2401 case X86::KCFI_CHECK:
2402 return LowerKCFI_CHECK(*
MI);
2404 case X86::ASAN_CHECK_MEMACCESS:
2405 return LowerASAN_CHECK_MEMACCESS(*
MI);
2407 case X86::MORESTACK_RET_RESTORE_R10:
2410 EmitAndCountInstruction(
2411 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2414 case X86::SEH_PushReg:
2415 case X86::SEH_SaveReg:
2416 case X86::SEH_SaveXMM:
2417 case X86::SEH_StackAlloc:
2418 case X86::SEH_StackAlign:
2419 case X86::SEH_SetFrame:
2420 case X86::SEH_PushFrame:
2421 case X86::SEH_EndPrologue:
2422 EmitSEHInstruction(
MI);
2425 case X86::SEH_Epilogue: {
2435 if (
MBBI->isCall() || !
MBBI->isPseudo()) {
2443 case X86::UBSAN_UD1:
2448 .addReg(X86::NoRegister)
2449 .addImm(
MI->getOperand(0).getImm())
2450 .
addReg(X86::NoRegister));
2452 case X86::CALL64pcrel32:
2453 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2462 &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
2467 if (EdgeProb > Threshold)
2474 MCInstLowering.Lower(
MI, TmpInst);
2491 EmitAndCountInstruction(TmpInst);
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
uint64_t IntrinsicInst * II
static cl::opt< bool > EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
static void printShuffleMask(raw_ostream &CS, StringRef Src1Name, StringRef Src2Name, ArrayRef< int > Mask)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static unsigned getSrcIdx(const MachineInstr *MI, unsigned SrcIdx)
static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, int Repeats, int BitWidth)
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits, bool IsSext)
static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, int SclWidth, int VecWidth, const char *ShuffleComment)
#define MASK_AVX512_CASE(Instr)
#define CASE_ARITH_RM(Instr)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
#define CASE_256_MOV_RM()
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI, unsigned SrcOpIdx)
#define CASE_MOVX_RM(Ext, Type)
static cl::opt< bool > EnableBranchHint("enable-branch-hint", cl::desc("Enable branch hint."), cl::init(false), cl::Hidden)
static void printConstant(const APInt &Val, raw_ostream &CS, bool PrintZero=false)
static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
#define CASE_512_MOV_RM()
static cl::opt< unsigned > BranchHintProbabilityThreshold("branch-hint-probability-threshold", cl::desc("The probability threshold of enabling branch hint."), cl::init(50), cl::Hidden)
#define CASE_128_MOV_RM()
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumWords() const
Get the number of words.
APInt sext(unsigned width) const
Sign extend to a new width.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
MCSymbol * CurrentFnBegin
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
TargetMachine & TM
Target machine description.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
StringRef getValueAsString() const
Return the attribute's value as a string.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasInternalLinkage() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
const MCTargetOptions * getTargetOptions() const
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
iterator insert(iterator I, const MCOperand &Op)
void setFlags(unsigned F)
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Streaming machine code generation interface.
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
void setAllowAutoPadding(bool v)
bool getAllowAutoPadding() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
BranchProbability getEdgeProbability(const MachineBasicBlock *Src, const MachineBasicBlock *Dst) const
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
const MachineOperand & getOperand(unsigned i) const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
Ty & getObjFileInfo()
Keep track of various per-module pieces of information for backends that would like to do so.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
MI-level patchpoint operands.
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool useIndirectThunkCalls() const
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
bool isX86_64ExtendedReg(unsigned RegNo)
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool isKMasked(uint64_t TSFlags)
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
initializer< Ty > init(const Ty &Val)
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto drop_end(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the last N elements excluded.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
constexpr unsigned BitWidth
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.