LLVM  16.0.0git
X86MCInstLower.cpp
Go to the documentation of this file.
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains code to lower X86 MachineInstrs to their corresponding
10 // MCInst records.
11 //
12 //===----------------------------------------------------------------------===//
13 
19 #include "X86AsmPrinter.h"
20 #include "X86RegisterInfo.h"
22 #include "X86Subtarget.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/SmallString.h"
30 #include "llvm/CodeGen/StackMaps.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/GlobalValue.h"
33 #include "llvm/IR/Mangler.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCCodeEmitter.h"
36 #include "llvm/MC/MCContext.h"
37 #include "llvm/MC/MCExpr.h"
38 #include "llvm/MC/MCFixup.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
41 #include "llvm/MC/MCSection.h"
42 #include "llvm/MC/MCSectionELF.h"
43 #include "llvm/MC/MCStreamer.h"
44 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/MC/MCSymbolELF.h"
46 #include "llvm/MC/TargetRegistry.h"
51 #include <string>
52 
53 using namespace llvm;
54 
55 namespace {
56 
57 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
58 class X86MCInstLower {
59  MCContext &Ctx;
60  const MachineFunction &MF;
61  const TargetMachine &TM;
62  const MCAsmInfo &MAI;
64 
65 public:
66  X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
67 
68  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
69  const MachineOperand &MO) const;
70  void Lower(const MachineInstr *MI, MCInst &OutMI) const;
71 
73  MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
74 
75 private:
76  MachineModuleInfoMachO &getMachOMMI() const;
77 };
78 
79 } // end anonymous namespace
80 
81 /// A RAII helper which defines a region of instructions which can't have
82 /// padding added between them for correctness.
85  const bool OldAllowAutoPadding;
87  : OS(OS), OldAllowAutoPadding(OS.getAllowAutoPadding()) {
88  changeAndComment(false);
89  }
90  ~NoAutoPaddingScope() { changeAndComment(OldAllowAutoPadding); }
91  void changeAndComment(bool b) {
92  if (b == OS.getAllowAutoPadding())
93  return;
95  if (b)
96  OS.emitRawComment("autopadding");
97  else
98  OS.emitRawComment("noautopadding");
99  }
100 };
101 
102 // Emit a minimal sequence of nops spanning NumBytes bytes.
103 static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
104  const X86Subtarget *Subtarget);
105 
107  const MCSubtargetInfo &STI,
108  MCCodeEmitter *CodeEmitter) {
109  if (InShadow) {
112  raw_svector_ostream VecOS(Code);
113  CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
114  CurrentShadowSize += Code.size();
115  if (CurrentShadowSize >= RequiredShadowSize)
116  InShadow = false; // The shadow is big enough. Stop counting.
117  }
118 }
119 
120 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
121  MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
122  if (InShadow && CurrentShadowSize < RequiredShadowSize) {
123  InShadow = false;
124  emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
125  &MF->getSubtarget<X86Subtarget>());
126  }
127 }
128 
129 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
130  OutStreamer->emitInstruction(Inst, getSubtargetInfo());
131  SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get());
132 }
133 
134 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
135  X86AsmPrinter &asmprinter)
136  : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
137  AsmPrinter(asmprinter) {}
138 
139 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
140  return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
141 }
142 
143 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
144 /// operand to an MCSymbol.
146  const Triple &TT = TM.getTargetTriple();
147  if (MO.isGlobal() && TT.isOSBinFormatELF())
149 
150  const DataLayout &DL = MF.getDataLayout();
151  assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
152  "Isn't a symbol reference");
153 
154  MCSymbol *Sym = nullptr;
156  StringRef Suffix;
157 
158  switch (MO.getTargetFlags()) {
159  case X86II::MO_DLLIMPORT:
160  // Handle dllimport linkage.
161  Name += "__imp_";
162  break;
163  case X86II::MO_COFFSTUB:
164  Name += ".refptr.";
165  break;
168  Suffix = "$non_lazy_ptr";
169  break;
170  }
171 
172  if (!Suffix.empty())
173  Name += DL.getPrivateGlobalPrefix();
174 
175  if (MO.isGlobal()) {
176  const GlobalValue *GV = MO.getGlobal();
178  } else if (MO.isSymbol()) {
179  Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
180  } else if (MO.isMBB()) {
181  assert(Suffix.empty());
182  Sym = MO.getMBB()->getSymbol();
183  }
184 
185  Name += Suffix;
186  if (!Sym)
187  Sym = Ctx.getOrCreateSymbol(Name);
188 
189  // If the target flags on the operand changes the name of the symbol, do that
190  // before we return the symbol.
191  switch (MO.getTargetFlags()) {
192  default:
193  break;
194  case X86II::MO_COFFSTUB: {
195  MachineModuleInfoCOFF &MMICOFF =
196  MF.getMMI().getObjFileInfo<MachineModuleInfoCOFF>();
197  MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
198  if (!StubSym.getPointer()) {
199  assert(MO.isGlobal() && "Extern symbol not handled yet");
201  AsmPrinter.getSymbol(MO.getGlobal()), true);
202  }
203  break;
204  }
208  getMachOMMI().getGVStubEntry(Sym);
209  if (!StubSym.getPointer()) {
210  assert(MO.isGlobal() && "Extern symbol not handled yet");
213  !MO.getGlobal()->hasInternalLinkage());
214  }
215  break;
216  }
217  }
218 
219  return Sym;
220 }
221 
223  MCSymbol *Sym) const {
224  // FIXME: We would like an efficient form for this, so we don't have to do a
225  // lot of extra uniquing.
226  const MCExpr *Expr = nullptr;
227  MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
228 
229  switch (MO.getTargetFlags()) {
230  default:
231  llvm_unreachable("Unknown target flag on GV operand");
232  case X86II::MO_NO_FLAG: // No flag.
233  // These affect the name of the symbol, not any suffix.
235  case X86II::MO_DLLIMPORT:
236  case X86II::MO_COFFSTUB:
237  break;
238 
239  case X86II::MO_TLVP:
240  RefKind = MCSymbolRefExpr::VK_TLVP;
241  break;
243  Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
244  // Subtract the pic base.
245  Expr = MCBinaryExpr::createSub(
246  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
247  break;
248  case X86II::MO_SECREL:
249  RefKind = MCSymbolRefExpr::VK_SECREL;
250  break;
251  case X86II::MO_TLSGD:
252  RefKind = MCSymbolRefExpr::VK_TLSGD;
253  break;
254  case X86II::MO_TLSLD:
255  RefKind = MCSymbolRefExpr::VK_TLSLD;
256  break;
257  case X86II::MO_TLSLDM:
258  RefKind = MCSymbolRefExpr::VK_TLSLDM;
259  break;
260  case X86II::MO_GOTTPOFF:
261  RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
262  break;
263  case X86II::MO_INDNTPOFF:
264  RefKind = MCSymbolRefExpr::VK_INDNTPOFF;
265  break;
266  case X86II::MO_TPOFF:
267  RefKind = MCSymbolRefExpr::VK_TPOFF;
268  break;
269  case X86II::MO_DTPOFF:
270  RefKind = MCSymbolRefExpr::VK_DTPOFF;
271  break;
272  case X86II::MO_NTPOFF:
273  RefKind = MCSymbolRefExpr::VK_NTPOFF;
274  break;
275  case X86II::MO_GOTNTPOFF:
276  RefKind = MCSymbolRefExpr::VK_GOTNTPOFF;
277  break;
278  case X86II::MO_GOTPCREL:
279  RefKind = MCSymbolRefExpr::VK_GOTPCREL;
280  break;
282  RefKind = MCSymbolRefExpr::VK_GOTPCREL_NORELAX;
283  break;
284  case X86II::MO_GOT:
285  RefKind = MCSymbolRefExpr::VK_GOT;
286  break;
287  case X86II::MO_GOTOFF:
288  RefKind = MCSymbolRefExpr::VK_GOTOFF;
289  break;
290  case X86II::MO_PLT:
291  RefKind = MCSymbolRefExpr::VK_PLT;
292  break;
293  case X86II::MO_ABS8:
294  RefKind = MCSymbolRefExpr::VK_X86_ABS8;
295  break;
298  Expr = MCSymbolRefExpr::create(Sym, Ctx);
299  // Subtract the pic base.
300  Expr = MCBinaryExpr::createSub(
301  Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
302  if (MO.isJTI()) {
303  assert(MAI.doesSetDirectiveSuppressReloc());
304  // If .set directive is supported, use it to reduce the number of
305  // relocations the assembler will generate for differences between
306  // local labels. This is only safe when the symbols are in the same
307  // section so we are restricting it to jumptable references.
308  MCSymbol *Label = Ctx.createTempSymbol();
309  AsmPrinter.OutStreamer->emitAssignment(Label, Expr);
310  Expr = MCSymbolRefExpr::create(Label, Ctx);
311  }
312  break;
313  }
314 
315  if (!Expr)
316  Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
317 
318  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
319  Expr = MCBinaryExpr::createAdd(
320  Expr, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
321  return MCOperand::createExpr(Expr);
322 }
323 
324 /// Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
325 /// a short fixed-register form.
326 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
327  unsigned ImmOp = Inst.getNumOperands() - 1;
328  assert(Inst.getOperand(0).isReg() &&
329  (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
330  ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
331  Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
332  Inst.getNumOperands() == 2) &&
333  "Unexpected instruction!");
334 
335  // Check whether the destination register can be fixed.
336  unsigned Reg = Inst.getOperand(0).getReg();
337  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
338  return;
339 
340  // If so, rewrite the instruction.
341  MCOperand Saved = Inst.getOperand(ImmOp);
342  Inst = MCInst();
343  Inst.setOpcode(Opcode);
344  Inst.addOperand(Saved);
345 }
346 
347 /// If a movsx instruction has a shorter encoding for the used register
348 /// simplify the instruction to use it instead.
349 static void SimplifyMOVSX(MCInst &Inst) {
350  unsigned NewOpcode = 0;
351  unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
352  switch (Inst.getOpcode()) {
353  default:
354  llvm_unreachable("Unexpected instruction!");
355  case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
356  if (Op0 == X86::AX && Op1 == X86::AL)
357  NewOpcode = X86::CBW;
358  break;
359  case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
360  if (Op0 == X86::EAX && Op1 == X86::AX)
361  NewOpcode = X86::CWDE;
362  break;
363  case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
364  if (Op0 == X86::RAX && Op1 == X86::EAX)
365  NewOpcode = X86::CDQE;
366  break;
367  }
368 
369  if (NewOpcode != 0) {
370  Inst = MCInst();
371  Inst.setOpcode(NewOpcode);
372  }
373 }
374 
375 /// Simplify things like MOV32rm to MOV32o32a.
377  unsigned Opcode) {
378  // Don't make these simplifications in 64-bit mode; other assemblers don't
379  // perform them because they make the code larger.
380  if (Printer.getSubtarget().is64Bit())
381  return;
382 
383  bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
384  unsigned AddrBase = IsStore;
385  unsigned RegOp = IsStore ? 0 : 5;
386  unsigned AddrOp = AddrBase + 3;
387  assert(
388  Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
389  Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
390  Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
391  Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
392  Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
393  (Inst.getOperand(AddrOp).isExpr() || Inst.getOperand(AddrOp).isImm()) &&
394  "Unexpected instruction!");
395 
396  // Check whether the destination register can be fixed.
397  unsigned Reg = Inst.getOperand(RegOp).getReg();
398  if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
399  return;
400 
401  // Check whether this is an absolute address.
402  // FIXME: We know TLVP symbol refs aren't, but there should be a better way
403  // to do this here.
404  bool Absolute = true;
405  if (Inst.getOperand(AddrOp).isExpr()) {
406  const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
407  if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
408  if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
409  Absolute = false;
410  }
411 
412  if (Absolute &&
413  (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
414  Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
415  Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
416  return;
417 
418  // If so, rewrite the instruction.
419  MCOperand Saved = Inst.getOperand(AddrOp);
420  MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
421  Inst = MCInst();
422  Inst.setOpcode(Opcode);
423  Inst.addOperand(Saved);
424  Inst.addOperand(Seg);
425 }
426 
427 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
428  return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
429 }
430 
432 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
433  const MachineOperand &MO) const {
434  switch (MO.getType()) {
435  default:
436  MI->print(errs());
437  llvm_unreachable("unknown operand type");
438  case MachineOperand::MO_Register:
439  // Ignore all implicit register operands.
440  if (MO.isImplicit())
441  return None;
442  return MCOperand::createReg(MO.getReg());
443  case MachineOperand::MO_Immediate:
444  return MCOperand::createImm(MO.getImm());
445  case MachineOperand::MO_MachineBasicBlock:
446  case MachineOperand::MO_GlobalAddress:
447  case MachineOperand::MO_ExternalSymbol:
449  case MachineOperand::MO_MCSymbol:
450  return LowerSymbolOperand(MO, MO.getMCSymbol());
451  case MachineOperand::MO_JumpTableIndex:
453  case MachineOperand::MO_ConstantPoolIndex:
455  case MachineOperand::MO_BlockAddress:
456  return LowerSymbolOperand(
458  case MachineOperand::MO_RegisterMask:
459  // Ignore call clobbers.
460  return None;
461  }
462 }
463 
464 // Replace TAILJMP opcodes with their equivalent opcodes that have encoding
465 // information.
466 static unsigned convertTailJumpOpcode(unsigned Opcode) {
467  switch (Opcode) {
468  case X86::TAILJMPr:
469  Opcode = X86::JMP32r;
470  break;
471  case X86::TAILJMPm:
472  Opcode = X86::JMP32m;
473  break;
474  case X86::TAILJMPr64:
475  Opcode = X86::JMP64r;
476  break;
477  case X86::TAILJMPm64:
478  Opcode = X86::JMP64m;
479  break;
480  case X86::TAILJMPr64_REX:
481  Opcode = X86::JMP64r_REX;
482  break;
483  case X86::TAILJMPm64_REX:
484  Opcode = X86::JMP64m_REX;
485  break;
486  case X86::TAILJMPd:
487  case X86::TAILJMPd64:
488  Opcode = X86::JMP_1;
489  break;
490  case X86::TAILJMPd_CC:
491  case X86::TAILJMPd64_CC:
492  Opcode = X86::JCC_1;
493  break;
494  }
495 
496  return Opcode;
497 }
498 
499 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
500  OutMI.setOpcode(MI->getOpcode());
501 
502  for (const MachineOperand &MO : MI->operands())
503  if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
504  OutMI.addOperand(*MaybeMCOp);
505 
506  // Handle a few special cases to eliminate operand modifiers.
507  switch (OutMI.getOpcode()) {
508  case X86::LEA64_32r:
509  case X86::LEA64r:
510  case X86::LEA16r:
511  case X86::LEA32r:
512  // LEA should have a segment register, but it must be empty.
513  assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
514  "Unexpected # of LEA operands");
515  assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
516  "LEA has segment specified!");
517  break;
518 
519  case X86::MULX32Hrr:
520  case X86::MULX32Hrm:
521  case X86::MULX64Hrr:
522  case X86::MULX64Hrm: {
523  // Turn into regular MULX by duplicating the destination.
524  unsigned NewOpc;
525  switch (OutMI.getOpcode()) {
526  default: llvm_unreachable("Invalid opcode");
527  case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
528  case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
529  case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
530  case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
531  }
532  OutMI.setOpcode(NewOpc);
533  // Duplicate the destination.
534  unsigned DestReg = OutMI.getOperand(0).getReg();
535  OutMI.insert(OutMI.begin(), MCOperand::createReg(DestReg));
536  break;
537  }
538 
539  // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
540  // if one of the registers is extended, but other isn't.
541  case X86::VMOVZPQILo2PQIrr:
542  case X86::VMOVAPDrr:
543  case X86::VMOVAPDYrr:
544  case X86::VMOVAPSrr:
545  case X86::VMOVAPSYrr:
546  case X86::VMOVDQArr:
547  case X86::VMOVDQAYrr:
548  case X86::VMOVDQUrr:
549  case X86::VMOVDQUYrr:
550  case X86::VMOVUPDrr:
551  case X86::VMOVUPDYrr:
552  case X86::VMOVUPSrr:
553  case X86::VMOVUPSYrr: {
554  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
556  unsigned NewOpc;
557  switch (OutMI.getOpcode()) {
558  default: llvm_unreachable("Invalid opcode");
559  case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr; break;
560  case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
561  case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
562  case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
563  case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
564  case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
565  case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
566  case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
567  case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
568  case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
569  case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
570  case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
571  case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
572  }
573  OutMI.setOpcode(NewOpc);
574  }
575  break;
576  }
577  case X86::VMOVSDrr:
578  case X86::VMOVSSrr: {
579  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
581  unsigned NewOpc;
582  switch (OutMI.getOpcode()) {
583  default: llvm_unreachable("Invalid opcode");
584  case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
585  case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
586  }
587  OutMI.setOpcode(NewOpc);
588  }
589  break;
590  }
591 
592  case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rmik:
593  case X86::VPCMPBZ128rri: case X86::VPCMPBZ128rrik:
594  case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rmik:
595  case X86::VPCMPBZ256rri: case X86::VPCMPBZ256rrik:
596  case X86::VPCMPBZrmi: case X86::VPCMPBZrmik:
597  case X86::VPCMPBZrri: case X86::VPCMPBZrrik:
598  case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rmik:
599  case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
600  case X86::VPCMPDZ128rri: case X86::VPCMPDZ128rrik:
601  case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rmik:
602  case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
603  case X86::VPCMPDZ256rri: case X86::VPCMPDZ256rrik:
604  case X86::VPCMPDZrmi: case X86::VPCMPDZrmik:
605  case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
606  case X86::VPCMPDZrri: case X86::VPCMPDZrrik:
607  case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rmik:
608  case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
609  case X86::VPCMPQZ128rri: case X86::VPCMPQZ128rrik:
610  case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rmik:
611  case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
612  case X86::VPCMPQZ256rri: case X86::VPCMPQZ256rrik:
613  case X86::VPCMPQZrmi: case X86::VPCMPQZrmik:
614  case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
615  case X86::VPCMPQZrri: case X86::VPCMPQZrrik:
616  case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rmik:
617  case X86::VPCMPWZ128rri: case X86::VPCMPWZ128rrik:
618  case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rmik:
619  case X86::VPCMPWZ256rri: case X86::VPCMPWZ256rrik:
620  case X86::VPCMPWZrmi: case X86::VPCMPWZrmik:
621  case X86::VPCMPWZrri: case X86::VPCMPWZrrik: {
622  // Turn immediate 0 into the VPCMPEQ instruction.
623  if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 0) {
624  unsigned NewOpc;
625  switch (OutMI.getOpcode()) {
626  default: llvm_unreachable("Invalid opcode");
627  case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPEQBZ128rm; break;
628  case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPEQBZ128rmk; break;
629  case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPEQBZ128rr; break;
630  case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPEQBZ128rrk; break;
631  case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPEQBZ256rm; break;
632  case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPEQBZ256rmk; break;
633  case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPEQBZ256rr; break;
634  case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPEQBZ256rrk; break;
635  case X86::VPCMPBZrmi: NewOpc = X86::VPCMPEQBZrm; break;
636  case X86::VPCMPBZrmik: NewOpc = X86::VPCMPEQBZrmk; break;
637  case X86::VPCMPBZrri: NewOpc = X86::VPCMPEQBZrr; break;
638  case X86::VPCMPBZrrik: NewOpc = X86::VPCMPEQBZrrk; break;
639  case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPEQDZ128rm; break;
640  case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPEQDZ128rmb; break;
641  case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPEQDZ128rmbk; break;
642  case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPEQDZ128rmk; break;
643  case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPEQDZ128rr; break;
644  case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPEQDZ128rrk; break;
645  case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPEQDZ256rm; break;
646  case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPEQDZ256rmb; break;
647  case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPEQDZ256rmbk; break;
648  case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPEQDZ256rmk; break;
649  case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPEQDZ256rr; break;
650  case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPEQDZ256rrk; break;
651  case X86::VPCMPDZrmi: NewOpc = X86::VPCMPEQDZrm; break;
652  case X86::VPCMPDZrmib: NewOpc = X86::VPCMPEQDZrmb; break;
653  case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPEQDZrmbk; break;
654  case X86::VPCMPDZrmik: NewOpc = X86::VPCMPEQDZrmk; break;
655  case X86::VPCMPDZrri: NewOpc = X86::VPCMPEQDZrr; break;
656  case X86::VPCMPDZrrik: NewOpc = X86::VPCMPEQDZrrk; break;
657  case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPEQQZ128rm; break;
658  case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPEQQZ128rmb; break;
659  case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPEQQZ128rmbk; break;
660  case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPEQQZ128rmk; break;
661  case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPEQQZ128rr; break;
662  case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPEQQZ128rrk; break;
663  case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPEQQZ256rm; break;
664  case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPEQQZ256rmb; break;
665  case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPEQQZ256rmbk; break;
666  case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPEQQZ256rmk; break;
667  case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPEQQZ256rr; break;
668  case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPEQQZ256rrk; break;
669  case X86::VPCMPQZrmi: NewOpc = X86::VPCMPEQQZrm; break;
670  case X86::VPCMPQZrmib: NewOpc = X86::VPCMPEQQZrmb; break;
671  case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPEQQZrmbk; break;
672  case X86::VPCMPQZrmik: NewOpc = X86::VPCMPEQQZrmk; break;
673  case X86::VPCMPQZrri: NewOpc = X86::VPCMPEQQZrr; break;
674  case X86::VPCMPQZrrik: NewOpc = X86::VPCMPEQQZrrk; break;
675  case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPEQWZ128rm; break;
676  case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPEQWZ128rmk; break;
677  case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPEQWZ128rr; break;
678  case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPEQWZ128rrk; break;
679  case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPEQWZ256rm; break;
680  case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPEQWZ256rmk; break;
681  case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPEQWZ256rr; break;
682  case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPEQWZ256rrk; break;
683  case X86::VPCMPWZrmi: NewOpc = X86::VPCMPEQWZrm; break;
684  case X86::VPCMPWZrmik: NewOpc = X86::VPCMPEQWZrmk; break;
685  case X86::VPCMPWZrri: NewOpc = X86::VPCMPEQWZrr; break;
686  case X86::VPCMPWZrrik: NewOpc = X86::VPCMPEQWZrrk; break;
687  }
688 
689  OutMI.setOpcode(NewOpc);
690  OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1));
691  break;
692  }
693 
694  // Turn immediate 6 into the VPCMPGT instruction.
695  if (OutMI.getOperand(OutMI.getNumOperands() - 1).getImm() == 6) {
696  unsigned NewOpc;
697  switch (OutMI.getOpcode()) {
698  default: llvm_unreachable("Invalid opcode");
699  case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPGTBZ128rm; break;
700  case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPGTBZ128rmk; break;
701  case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPGTBZ128rr; break;
702  case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPGTBZ128rrk; break;
703  case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPGTBZ256rm; break;
704  case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPGTBZ256rmk; break;
705  case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPGTBZ256rr; break;
706  case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPGTBZ256rrk; break;
707  case X86::VPCMPBZrmi: NewOpc = X86::VPCMPGTBZrm; break;
708  case X86::VPCMPBZrmik: NewOpc = X86::VPCMPGTBZrmk; break;
709  case X86::VPCMPBZrri: NewOpc = X86::VPCMPGTBZrr; break;
710  case X86::VPCMPBZrrik: NewOpc = X86::VPCMPGTBZrrk; break;
711  case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPGTDZ128rm; break;
712  case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPGTDZ128rmb; break;
713  case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPGTDZ128rmbk; break;
714  case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPGTDZ128rmk; break;
715  case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPGTDZ128rr; break;
716  case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPGTDZ128rrk; break;
717  case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPGTDZ256rm; break;
718  case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPGTDZ256rmb; break;
719  case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPGTDZ256rmbk; break;
720  case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPGTDZ256rmk; break;
721  case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPGTDZ256rr; break;
722  case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPGTDZ256rrk; break;
723  case X86::VPCMPDZrmi: NewOpc = X86::VPCMPGTDZrm; break;
724  case X86::VPCMPDZrmib: NewOpc = X86::VPCMPGTDZrmb; break;
725  case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPGTDZrmbk; break;
726  case X86::VPCMPDZrmik: NewOpc = X86::VPCMPGTDZrmk; break;
727  case X86::VPCMPDZrri: NewOpc = X86::VPCMPGTDZrr; break;
728  case X86::VPCMPDZrrik: NewOpc = X86::VPCMPGTDZrrk; break;
729  case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPGTQZ128rm; break;
730  case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPGTQZ128rmb; break;
731  case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPGTQZ128rmbk; break;
732  case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPGTQZ128rmk; break;
733  case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPGTQZ128rr; break;
734  case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPGTQZ128rrk; break;
735  case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPGTQZ256rm; break;
736  case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPGTQZ256rmb; break;
737  case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPGTQZ256rmbk; break;
738  case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPGTQZ256rmk; break;
739  case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPGTQZ256rr; break;
740  case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPGTQZ256rrk; break;
741  case X86::VPCMPQZrmi: NewOpc = X86::VPCMPGTQZrm; break;
742  case X86::VPCMPQZrmib: NewOpc = X86::VPCMPGTQZrmb; break;
743  case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPGTQZrmbk; break;
744  case X86::VPCMPQZrmik: NewOpc = X86::VPCMPGTQZrmk; break;
745  case X86::VPCMPQZrri: NewOpc = X86::VPCMPGTQZrr; break;
746  case X86::VPCMPQZrrik: NewOpc = X86::VPCMPGTQZrrk; break;
747  case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPGTWZ128rm; break;
748  case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPGTWZ128rmk; break;
749  case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPGTWZ128rr; break;
750  case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPGTWZ128rrk; break;
751  case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPGTWZ256rm; break;
752  case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPGTWZ256rmk; break;
753  case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPGTWZ256rr; break;
754  case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPGTWZ256rrk; break;
755  case X86::VPCMPWZrmi: NewOpc = X86::VPCMPGTWZrm; break;
756  case X86::VPCMPWZrmik: NewOpc = X86::VPCMPGTWZrmk; break;
757  case X86::VPCMPWZrri: NewOpc = X86::VPCMPGTWZrr; break;
758  case X86::VPCMPWZrrik: NewOpc = X86::VPCMPGTWZrrk; break;
759  }
760 
761  OutMI.setOpcode(NewOpc);
762  OutMI.erase(&OutMI.getOperand(OutMI.getNumOperands() - 1));
763  break;
764  }
765 
766  break;
767  }
768 
769  // CALL64r, CALL64pcrel32 - These instructions used to have
770  // register inputs modeled as normal uses instead of implicit uses. As such,
771  // they we used to truncate off all but the first operand (the callee). This
772  // issue seems to have been fixed at some point. This assert verifies that.
773  case X86::CALL64r:
774  case X86::CALL64pcrel32:
775  assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
776  break;
777 
778  case X86::EH_RETURN:
779  case X86::EH_RETURN64: {
780  OutMI = MCInst();
781  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
782  break;
783  }
784 
785  case X86::CLEANUPRET: {
786  // Replace CLEANUPRET with the appropriate RET.
787  OutMI = MCInst();
788  OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
789  break;
790  }
791 
792  case X86::CATCHRET: {
793  // Replace CATCHRET with the appropriate RET.
794  const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
795  unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
796  OutMI = MCInst();
797  OutMI.setOpcode(getRetOpcode(Subtarget));
798  OutMI.addOperand(MCOperand::createReg(ReturnReg));
799  break;
800  }
801 
802  // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
803  // instruction.
804  case X86::TAILJMPr:
805  case X86::TAILJMPr64:
806  case X86::TAILJMPr64_REX:
807  case X86::TAILJMPd:
808  case X86::TAILJMPd64:
809  assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
810  OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
811  break;
812 
813  case X86::TAILJMPd_CC:
814  case X86::TAILJMPd64_CC:
815  assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");
816  OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
817  break;
818 
819  case X86::TAILJMPm:
820  case X86::TAILJMPm64:
821  case X86::TAILJMPm64_REX:
823  "Unexpected number of operands!");
824  OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
825  break;
826 
827  case X86::DEC16r:
828  case X86::DEC32r:
829  case X86::INC16r:
830  case X86::INC32r:
831  // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
832  if (!AsmPrinter.getSubtarget().is64Bit()) {
833  unsigned Opcode;
834  switch (OutMI.getOpcode()) {
835  default: llvm_unreachable("Invalid opcode");
836  case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
837  case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
838  case X86::INC16r: Opcode = X86::INC16r_alt; break;
839  case X86::INC32r: Opcode = X86::INC32r_alt; break;
840  }
841  OutMI.setOpcode(Opcode);
842  }
843  break;
844 
845  // We don't currently select the correct instruction form for instructions
846  // which have a short %eax, etc. form. Handle this by custom lowering, for
847  // now.
848  //
849  // Note, we are currently not handling the following instructions:
850  // MOV64ao8, MOV64o8a
851  // XCHG16ar, XCHG32ar, XCHG64ar
852  case X86::MOV8mr_NOREX:
853  case X86::MOV8mr:
854  case X86::MOV8rm_NOREX:
855  case X86::MOV8rm:
856  case X86::MOV16mr:
857  case X86::MOV16rm:
858  case X86::MOV32mr:
859  case X86::MOV32rm: {
860  unsigned NewOpc;
861  switch (OutMI.getOpcode()) {
862  default: llvm_unreachable("Invalid opcode");
863  case X86::MOV8mr_NOREX:
864  case X86::MOV8mr: NewOpc = X86::MOV8o32a; break;
865  case X86::MOV8rm_NOREX:
866  case X86::MOV8rm: NewOpc = X86::MOV8ao32; break;
867  case X86::MOV16mr: NewOpc = X86::MOV16o32a; break;
868  case X86::MOV16rm: NewOpc = X86::MOV16ao32; break;
869  case X86::MOV32mr: NewOpc = X86::MOV32o32a; break;
870  case X86::MOV32rm: NewOpc = X86::MOV32ao32; break;
871  }
872  SimplifyShortMoveForm(AsmPrinter, OutMI, NewOpc);
873  break;
874  }
875 
876  case X86::ADC8ri: case X86::ADC16ri: case X86::ADC32ri: case X86::ADC64ri32:
877  case X86::ADD8ri: case X86::ADD16ri: case X86::ADD32ri: case X86::ADD64ri32:
878  case X86::AND8ri: case X86::AND16ri: case X86::AND32ri: case X86::AND64ri32:
879  case X86::CMP8ri: case X86::CMP16ri: case X86::CMP32ri: case X86::CMP64ri32:
880  case X86::OR8ri: case X86::OR16ri: case X86::OR32ri: case X86::OR64ri32:
881  case X86::SBB8ri: case X86::SBB16ri: case X86::SBB32ri: case X86::SBB64ri32:
882  case X86::SUB8ri: case X86::SUB16ri: case X86::SUB32ri: case X86::SUB64ri32:
883  case X86::TEST8ri:case X86::TEST16ri:case X86::TEST32ri:case X86::TEST64ri32:
884  case X86::XOR8ri: case X86::XOR16ri: case X86::XOR32ri: case X86::XOR64ri32: {
885  unsigned NewOpc;
886  switch (OutMI.getOpcode()) {
887  default: llvm_unreachable("Invalid opcode");
888  case X86::ADC8ri: NewOpc = X86::ADC8i8; break;
889  case X86::ADC16ri: NewOpc = X86::ADC16i16; break;
890  case X86::ADC32ri: NewOpc = X86::ADC32i32; break;
891  case X86::ADC64ri32: NewOpc = X86::ADC64i32; break;
892  case X86::ADD8ri: NewOpc = X86::ADD8i8; break;
893  case X86::ADD16ri: NewOpc = X86::ADD16i16; break;
894  case X86::ADD32ri: NewOpc = X86::ADD32i32; break;
895  case X86::ADD64ri32: NewOpc = X86::ADD64i32; break;
896  case X86::AND8ri: NewOpc = X86::AND8i8; break;
897  case X86::AND16ri: NewOpc = X86::AND16i16; break;
898  case X86::AND32ri: NewOpc = X86::AND32i32; break;
899  case X86::AND64ri32: NewOpc = X86::AND64i32; break;
900  case X86::CMP8ri: NewOpc = X86::CMP8i8; break;
901  case X86::CMP16ri: NewOpc = X86::CMP16i16; break;
902  case X86::CMP32ri: NewOpc = X86::CMP32i32; break;
903  case X86::CMP64ri32: NewOpc = X86::CMP64i32; break;
904  case X86::OR8ri: NewOpc = X86::OR8i8; break;
905  case X86::OR16ri: NewOpc = X86::OR16i16; break;
906  case X86::OR32ri: NewOpc = X86::OR32i32; break;
907  case X86::OR64ri32: NewOpc = X86::OR64i32; break;
908  case X86::SBB8ri: NewOpc = X86::SBB8i8; break;
909  case X86::SBB16ri: NewOpc = X86::SBB16i16; break;
910  case X86::SBB32ri: NewOpc = X86::SBB32i32; break;
911  case X86::SBB64ri32: NewOpc = X86::SBB64i32; break;
912  case X86::SUB8ri: NewOpc = X86::SUB8i8; break;
913  case X86::SUB16ri: NewOpc = X86::SUB16i16; break;
914  case X86::SUB32ri: NewOpc = X86::SUB32i32; break;
915  case X86::SUB64ri32: NewOpc = X86::SUB64i32; break;
916  case X86::TEST8ri: NewOpc = X86::TEST8i8; break;
917  case X86::TEST16ri: NewOpc = X86::TEST16i16; break;
918  case X86::TEST32ri: NewOpc = X86::TEST32i32; break;
919  case X86::TEST64ri32: NewOpc = X86::TEST64i32; break;
920  case X86::XOR8ri: NewOpc = X86::XOR8i8; break;
921  case X86::XOR16ri: NewOpc = X86::XOR16i16; break;
922  case X86::XOR32ri: NewOpc = X86::XOR32i32; break;
923  case X86::XOR64ri32: NewOpc = X86::XOR64i32; break;
924  }
925  SimplifyShortImmForm(OutMI, NewOpc);
926  break;
927  }
928 
929  // Try to shrink some forms of movsx.
930  case X86::MOVSX16rr8:
931  case X86::MOVSX32rr16:
932  case X86::MOVSX64rr32:
933  SimplifyMOVSX(OutMI);
934  break;
935 
936  case X86::VCMPPDrri:
937  case X86::VCMPPDYrri:
938  case X86::VCMPPSrri:
939  case X86::VCMPPSYrri:
940  case X86::VCMPSDrr:
941  case X86::VCMPSSrr: {
942  // Swap the operands if it will enable a 2 byte VEX encoding.
943  // FIXME: Change the immediate to improve opportunities?
944  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&
946  unsigned Imm = MI->getOperand(3).getImm() & 0x7;
947  switch (Imm) {
948  default: break;
949  case 0x00: // EQUAL
950  case 0x03: // UNORDERED
951  case 0x04: // NOT EQUAL
952  case 0x07: // ORDERED
953  std::swap(OutMI.getOperand(1), OutMI.getOperand(2));
954  break;
955  }
956  }
957  break;
958  }
959 
960  case X86::VMOVHLPSrr:
961  case X86::VUNPCKHPDrr:
962  // These are not truly commutable so hide them from the default case.
963  break;
964 
965  case X86::MASKMOVDQU:
966  case X86::VMASKMOVDQU:
967  if (AsmPrinter.getSubtarget().is64Bit())
969  break;
970 
971  default: {
972  // If the instruction is a commutable arithmetic instruction we might be
973  // able to commute the operands to get a 2 byte VEX prefix.
974  uint64_t TSFlags = MI->getDesc().TSFlags;
975  if (MI->getDesc().isCommutable() &&
980  OutMI.getNumOperands() == 3) {
981  if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) &&
983  std::swap(OutMI.getOperand(1), OutMI.getOperand(2));
984  }
985  // Add an REP prefix to BSF instructions so that new processors can
986  // recognize as TZCNT, which has better performance than BSF.
987  if (X86::isBSF(OutMI.getOpcode()) && !MF.getFunction().hasOptSize()) {
988  // BSF and TZCNT have different interpretations on ZF bit. So make sure
989  // it won't be used later.
990  const MachineOperand *FlagDef = MI->findRegisterDefOperand(X86::EFLAGS);
991  if (FlagDef && FlagDef->isDead())
993  }
994  break;
995  }
996  }
997 }
998 
999 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
1000  const MachineInstr &MI) {
1001  NoAutoPaddingScope NoPadScope(*OutStreamer);
1002  bool Is64Bits = MI.getOpcode() != X86::TLS_addr32 &&
1003  MI.getOpcode() != X86::TLS_base_addr32;
1004  bool Is64BitsLP64 = MI.getOpcode() == X86::TLS_addr64 ||
1005  MI.getOpcode() == X86::TLS_base_addr64;
1006  MCContext &Ctx = OutStreamer->getContext();
1007 
1009  switch (MI.getOpcode()) {
1010  case X86::TLS_addr32:
1011  case X86::TLS_addr64:
1012  case X86::TLS_addrX32:
1014  break;
1015  case X86::TLS_base_addr32:
1017  break;
1018  case X86::TLS_base_addr64:
1019  case X86::TLS_base_addrX32:
1021  break;
1022  default:
1023  llvm_unreachable("unexpected opcode");
1024  }
1025 
1027  MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
1028 
1029  // As of binutils 2.32, ld has a bogus TLS relaxation error when the GD/LD
1030  // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
1031  // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by
1032  // only using GOT when GOTPCRELX is enabled.
1033  // TODO Delete the workaround when GOTPCRELX becomes commonplace.
1034  bool UseGot = MMI->getModule()->getRtLibUseGOT() &&
1036 
1037  if (Is64Bits) {
1038  bool NeedsPadding = SRVK == MCSymbolRefExpr::VK_TLSGD;
1039  if (NeedsPadding && Is64BitsLP64)
1040  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1041  EmitAndCountInstruction(MCInstBuilder(X86::LEA64r)
1042  .addReg(X86::RDI)
1043  .addReg(X86::RIP)
1044  .addImm(1)
1045  .addReg(0)
1046  .addExpr(Sym)
1047  .addReg(0));
1048  const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("__tls_get_addr");
1049  if (NeedsPadding) {
1050  if (!UseGot)
1051  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1052  EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
1053  EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
1054  }
1055  if (UseGot) {
1056  const MCExpr *Expr = MCSymbolRefExpr::create(
1057  TlsGetAddr, MCSymbolRefExpr::VK_GOTPCREL, Ctx);
1058  EmitAndCountInstruction(MCInstBuilder(X86::CALL64m)
1059  .addReg(X86::RIP)
1060  .addImm(1)
1061  .addReg(0)
1062  .addExpr(Expr)
1063  .addReg(0));
1064  } else {
1065  EmitAndCountInstruction(
1066  MCInstBuilder(X86::CALL64pcrel32)
1067  .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
1068  MCSymbolRefExpr::VK_PLT, Ctx)));
1069  }
1070  } else {
1071  if (SRVK == MCSymbolRefExpr::VK_TLSGD && !UseGot) {
1072  EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
1073  .addReg(X86::EAX)
1074  .addReg(0)
1075  .addImm(1)
1076  .addReg(X86::EBX)
1077  .addExpr(Sym)
1078  .addReg(0));
1079  } else {
1080  EmitAndCountInstruction(MCInstBuilder(X86::LEA32r)
1081  .addReg(X86::EAX)
1082  .addReg(X86::EBX)
1083  .addImm(1)
1084  .addReg(0)
1085  .addExpr(Sym)
1086  .addReg(0));
1087  }
1088 
1089  const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol("___tls_get_addr");
1090  if (UseGot) {
1091  const MCExpr *Expr =
1093  EmitAndCountInstruction(MCInstBuilder(X86::CALL32m)
1094  .addReg(X86::EBX)
1095  .addImm(1)
1096  .addReg(0)
1097  .addExpr(Expr)
1098  .addReg(0));
1099  } else {
1100  EmitAndCountInstruction(
1101  MCInstBuilder(X86::CALLpcrel32)
1102  .addExpr(MCSymbolRefExpr::create(TlsGetAddr,
1103  MCSymbolRefExpr::VK_PLT, Ctx)));
1104  }
1105  }
1106 }
1107 
1108 /// Emit the largest nop instruction smaller than or equal to \p NumBytes
1109 /// bytes. Return the size of nop emitted.
1110 static unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
1111  const X86Subtarget *Subtarget) {
1112  // Determine the longest nop which can be efficiently decoded for the given
1113  // target cpu. 15-bytes is the longest single NOP instruction, but some
1114  // platforms can't decode the longest forms efficiently.
1115  unsigned MaxNopLength = 1;
1116  if (Subtarget->is64Bit()) {
1117  // FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the
1118  // IndexReg/BaseReg below need to be updated.
1119  if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
1120  MaxNopLength = 7;
1121  else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
1122  MaxNopLength = 15;
1123  else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
1124  MaxNopLength = 11;
1125  else
1126  MaxNopLength = 10;
1127  } if (Subtarget->is32Bit())
1128  MaxNopLength = 2;
1129 
1130  // Cap a single nop emission at the profitable value for the target
1131  NumBytes = std::min(NumBytes, MaxNopLength);
1132 
1133  unsigned NopSize;
1134  unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
1135  IndexReg = Displacement = SegmentReg = 0;
1136  BaseReg = X86::RAX;
1137  ScaleVal = 1;
1138  switch (NumBytes) {
1139  case 0:
1140  llvm_unreachable("Zero nops?");
1141  break;
1142  case 1:
1143  NopSize = 1;
1144  Opc = X86::NOOP;
1145  break;
1146  case 2:
1147  NopSize = 2;
1148  Opc = X86::XCHG16ar;
1149  break;
1150  case 3:
1151  NopSize = 3;
1152  Opc = X86::NOOPL;
1153  break;
1154  case 4:
1155  NopSize = 4;
1156  Opc = X86::NOOPL;
1157  Displacement = 8;
1158  break;
1159  case 5:
1160  NopSize = 5;
1161  Opc = X86::NOOPL;
1162  Displacement = 8;
1163  IndexReg = X86::RAX;
1164  break;
1165  case 6:
1166  NopSize = 6;
1167  Opc = X86::NOOPW;
1168  Displacement = 8;
1169  IndexReg = X86::RAX;
1170  break;
1171  case 7:
1172  NopSize = 7;
1173  Opc = X86::NOOPL;
1174  Displacement = 512;
1175  break;
1176  case 8:
1177  NopSize = 8;
1178  Opc = X86::NOOPL;
1179  Displacement = 512;
1180  IndexReg = X86::RAX;
1181  break;
1182  case 9:
1183  NopSize = 9;
1184  Opc = X86::NOOPW;
1185  Displacement = 512;
1186  IndexReg = X86::RAX;
1187  break;
1188  default:
1189  NopSize = 10;
1190  Opc = X86::NOOPW;
1191  Displacement = 512;
1192  IndexReg = X86::RAX;
1193  SegmentReg = X86::CS;
1194  break;
1195  }
1196 
1197  unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
1198  NopSize += NumPrefixes;
1199  for (unsigned i = 0; i != NumPrefixes; ++i)
1200  OS.emitBytes("\x66");
1201 
1202  switch (Opc) {
1203  default: llvm_unreachable("Unexpected opcode");
1204  case X86::NOOP:
1205  OS.emitInstruction(MCInstBuilder(Opc), *Subtarget);
1206  break;
1207  case X86::XCHG16ar:
1208  OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX),
1209  *Subtarget);
1210  break;
1211  case X86::NOOPL:
1212  case X86::NOOPW:
1214  .addReg(BaseReg)
1215  .addImm(ScaleVal)
1216  .addReg(IndexReg)
1217  .addImm(Displacement)
1218  .addReg(SegmentReg),
1219  *Subtarget);
1220  break;
1221  }
1222  assert(NopSize <= NumBytes && "We overemitted?");
1223  return NopSize;
1224 }
1225 
1226 /// Emit the optimal amount of multi-byte nops on X86.
1227 static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
1228  const X86Subtarget *Subtarget) {
1229  unsigned NopsToEmit = NumBytes;
1230  (void)NopsToEmit;
1231  while (NumBytes) {
1232  NumBytes -= emitNop(OS, NumBytes, Subtarget);
1233  assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
1234  }
1235 }
1236 
1237 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
1238  X86MCInstLower &MCIL) {
1239  assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
1240 
1241  NoAutoPaddingScope NoPadScope(*OutStreamer);
1242 
1243  StatepointOpers SOpers(&MI);
1244  if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1245  emitX86Nops(*OutStreamer, PatchBytes, Subtarget);
1246  } else {
1247  // Lower call target and choose correct opcode
1248  const MachineOperand &CallTarget = SOpers.getCallTarget();
1249  MCOperand CallTargetMCOp;
1250  unsigned CallOpcode;
1251  switch (CallTarget.getType()) {
1254  CallTargetMCOp = MCIL.LowerSymbolOperand(
1255  CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
1256  CallOpcode = X86::CALL64pcrel32;
1257  // Currently, we only support relative addressing with statepoints.
1258  // Otherwise, we'll need a scratch register to hold the target
1259  // address. You'll fail asserts during load & relocation if this
1260  // symbol is to far away. (TODO: support non-relative addressing)
1261  break;
1263  CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
1264  CallOpcode = X86::CALL64pcrel32;
1265  // Currently, we only support relative addressing with statepoints.
1266  // Otherwise, we'll need a scratch register to hold the target
1267  // immediate. You'll fail asserts during load & relocation if this
1268  // address is to far away. (TODO: support non-relative addressing)
1269  break;
1271  // FIXME: Add retpoline support and remove this.
1272  if (Subtarget->useIndirectThunkCalls())
1273  report_fatal_error("Lowering register statepoints with thunks not "
1274  "yet implemented.");
1275  CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1276  CallOpcode = X86::CALL64r;
1277  break;
1278  default:
1279  llvm_unreachable("Unsupported operand type in statepoint call target");
1280  break;
1281  }
1282 
1283  // Emit call
1284  MCInst CallInst;
1285  CallInst.setOpcode(CallOpcode);
1286  CallInst.addOperand(CallTargetMCOp);
1287  OutStreamer->emitInstruction(CallInst, getSubtargetInfo());
1288  }
1289 
1290  // Record our statepoint node in the same section used by STACKMAP
1291  // and PATCHPOINT
1292  auto &Ctx = OutStreamer->getContext();
1293  MCSymbol *MILabel = Ctx.createTempSymbol();
1294  OutStreamer->emitLabel(MILabel);
1295  SM.recordStatepoint(*MILabel, MI);
1296 }
1297 
1298 void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
1299  X86MCInstLower &MCIL) {
1300  // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
1301  // <opcode>, <operands>
1302 
1303  NoAutoPaddingScope NoPadScope(*OutStreamer);
1304 
1305  Register DefRegister = FaultingMI.getOperand(0).getReg();
1307  static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1308  MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1309  unsigned Opcode = FaultingMI.getOperand(3).getImm();
1310  unsigned OperandsBeginIdx = 4;
1311 
1312  auto &Ctx = OutStreamer->getContext();
1313  MCSymbol *FaultingLabel = Ctx.createTempSymbol();
1314  OutStreamer->emitLabel(FaultingLabel);
1315 
1316  assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
1317  FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel);
1318 
1319  MCInst MI;
1320  MI.setOpcode(Opcode);
1321 
1322  if (DefRegister != X86::NoRegister)
1323  MI.addOperand(MCOperand::createReg(DefRegister));
1324 
1325  for (const MachineOperand &MO :
1326  llvm::drop_begin(FaultingMI.operands(), OperandsBeginIdx))
1327  if (auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, MO))
1328  MI.addOperand(*MaybeOperand);
1329 
1330  OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1331  OutStreamer->emitInstruction(MI, getSubtargetInfo());
1332 }
1333 
1334 void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
1335  X86MCInstLower &MCIL) {
1336  bool Is64Bits = Subtarget->is64Bit();
1337  MCContext &Ctx = OutStreamer->getContext();
1338  MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__");
1339  const MCSymbolRefExpr *Op =
1341 
1342  EmitAndCountInstruction(
1343  MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1344  .addExpr(Op));
1345 }
1346 
1347 void X86AsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
1348  assert(std::next(MI.getIterator())->isCall() &&
1349  "KCFI_CHECK not followed by a call instruction");
1350 
1351  // Adjust the offset for patchable-function-prefix. X86InstrInfo::getNop()
1352  // returns a 1-byte X86::NOOP, which means the offset is the same in
1353  // bytes. This assumes that patchable-function-prefix is the same for all
1354  // functions.
1355  const MachineFunction &MF = *MI.getMF();
1356  int64_t PrefixNops = 0;
1357  (void)MF.getFunction()
1358  .getFnAttribute("patchable-function-prefix")
1359  .getValueAsString()
1360  .getAsInteger(10, PrefixNops);
1361 
1362  // KCFI allows indirect calls to any location that's preceded by a valid
1363  // type identifier. To avoid encoding the full constant into an instruction,
1364  // and thus emitting potential call target gadgets at each indirect call
1365  // site, load a negated constant to a register and compare that to the
1366  // expected value at the call target.
1367  const Register AddrReg = MI.getOperand(0).getReg();
1368  const uint32_t Type = MI.getOperand(1).getImm();
1369  // The check is immediately before the call. If the call target is in R10,
1370  // we can clobber R11 for the check instead.
1371  unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
1372  EmitAndCountInstruction(
1373  MCInstBuilder(X86::MOV32ri).addReg(TempReg).addImm(-MaskKCFIType(Type)));
1374  EmitAndCountInstruction(MCInstBuilder(X86::ADD32rm)
1375  .addReg(X86::NoRegister)
1376  .addReg(TempReg)
1377  .addReg(AddrReg)
1378  .addImm(1)
1379  .addReg(X86::NoRegister)
1380  .addImm(-(PrefixNops + 4))
1381  .addReg(X86::NoRegister));
1382 
1384  EmitAndCountInstruction(
1385  MCInstBuilder(X86::JCC_1)
1387  .addImm(X86::COND_E));
1388 
1390  OutStreamer->emitLabel(Trap);
1391  EmitAndCountInstruction(MCInstBuilder(X86::TRAP));
1392  emitKCFITrapEntry(MF, Trap);
1393  OutStreamer->emitLabel(Pass);
1394 }
1395 
1396 void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
1397  // FIXME: Make this work on non-ELF.
1398  if (!TM.getTargetTriple().isOSBinFormatELF()) {
1399  report_fatal_error("llvm.asan.check.memaccess only supported on ELF");
1400  return;
1401  }
1402 
1403  const auto &Reg = MI.getOperand(0).getReg();
1404  ASanAccessInfo AccessInfo(MI.getOperand(1).getImm());
1405 
1406  uint64_t ShadowBase;
1407  int MappingScale;
1408  bool OrShadowOffset;
1410  AccessInfo.CompileKernel, &ShadowBase,
1411  &MappingScale, &OrShadowOffset);
1412 
1413  StringRef Name = AccessInfo.IsWrite ? "store" : "load";
1414  StringRef Op = OrShadowOffset ? "or" : "add";
1415  std::string SymName = ("__asan_check_" + Name + "_" + Op + "_" +
1416  Twine(1ULL << AccessInfo.AccessSizeIndex) + "_" +
1417  TM.getMCRegisterInfo()->getName(Reg.asMCReg()))
1418  .str();
1419  if (OrShadowOffset)
1421  "OrShadowOffset is not supported with optimized callbacks");
1422 
1423  EmitAndCountInstruction(
1424  MCInstBuilder(X86::CALL64pcrel32)
1425  .addExpr(MCSymbolRefExpr::create(
1427 }
1428 
1429 void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
1430  X86MCInstLower &MCIL) {
1431  // PATCHABLE_OP minsize, opcode, operands
1432 
1433  NoAutoPaddingScope NoPadScope(*OutStreamer);
1434 
1435  unsigned MinSize = MI.getOperand(0).getImm();
1436  unsigned Opcode = MI.getOperand(1).getImm();
1437 
1438  MCInst MCI;
1439  MCI.setOpcode(Opcode);
1440  for (auto &MO : drop_begin(MI.operands(), 2))
1441  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1442  MCI.addOperand(*MaybeOperand);
1443 
1446  raw_svector_ostream VecOS(Code);
1447  CodeEmitter->encodeInstruction(MCI, VecOS, Fixups, getSubtargetInfo());
1448 
1449  if (Code.size() < MinSize) {
1450  if (MinSize == 2 && Subtarget->is32Bit() &&
1451  Subtarget->isTargetWindowsMSVC() &&
1452  (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) {
1453  // For compatibility reasons, when targetting MSVC, is is important to
1454  // generate a 'legacy' NOP in the form of a 8B FF MOV EDI, EDI. Some tools
1455  // rely specifically on this pattern to be able to patch a function.
1456  // This is only for 32-bit targets, when using /arch:IA32 or /arch:SSE.
1457  OutStreamer->emitInstruction(
1458  MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1459  *Subtarget);
1460  } else if (MinSize == 2 && Opcode == X86::PUSH64r) {
1461  // This is an optimization that lets us get away without emitting a nop in
1462  // many cases.
1463  //
1464  // NB! In some cases the encoding for PUSH64r (e.g. PUSH64r %r9) takes two
1465  // bytes too, so the check on MinSize is important.
1466  MCI.setOpcode(X86::PUSH64rmr);
1467  } else {
1468  unsigned NopSize = emitNop(*OutStreamer, MinSize, Subtarget);
1469  assert(NopSize == MinSize && "Could not implement MinSize!");
1470  (void)NopSize;
1471  }
1472  }
1473 
1474  OutStreamer->emitInstruction(MCI, getSubtargetInfo());
1475 }
1476 
1477 // Lower a stackmap of the form:
1478 // <id>, <shadowBytes>, ...
1479 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1480  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1481 
1482  auto &Ctx = OutStreamer->getContext();
1483  MCSymbol *MILabel = Ctx.createTempSymbol();
1484  OutStreamer->emitLabel(MILabel);
1485 
1486  SM.recordStackMap(*MILabel, MI);
1487  unsigned NumShadowBytes = MI.getOperand(1).getImm();
1488  SMShadowTracker.reset(NumShadowBytes);
1489 }
1490 
1491 // Lower a patchpoint of the form:
1492 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1493 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1494  X86MCInstLower &MCIL) {
1495  assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1496 
1497  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1498 
1499  NoAutoPaddingScope NoPadScope(*OutStreamer);
1500 
1501  auto &Ctx = OutStreamer->getContext();
1502  MCSymbol *MILabel = Ctx.createTempSymbol();
1503  OutStreamer->emitLabel(MILabel);
1504  SM.recordPatchPoint(*MILabel, MI);
1505 
1506  PatchPointOpers opers(&MI);
1507  unsigned ScratchIdx = opers.getNextScratchIdx();
1508  unsigned EncodedBytes = 0;
1509  const MachineOperand &CalleeMO = opers.getCallTarget();
1510 
1511  // Check for null target. If target is non-null (i.e. is non-zero or is
1512  // symbolic) then emit a call.
1513  if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1514  MCOperand CalleeMCOp;
1515  switch (CalleeMO.getType()) {
1516  default:
1517  /// FIXME: Add a verifier check for bad callee types.
1518  llvm_unreachable("Unrecognized callee operand type.");
1520  if (CalleeMO.getImm())
1521  CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
1522  break;
1525  CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1526  MCIL.GetSymbolFromOperand(CalleeMO));
1527  break;
1528  }
1529 
1530  // Emit MOV to materialize the target address and the CALL to target.
1531  // This is encoded with 12-13 bytes, depending on which register is used.
1532  Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1533  if (X86II::isX86_64ExtendedReg(ScratchReg))
1534  EncodedBytes = 13;
1535  else
1536  EncodedBytes = 12;
1537 
1538  EmitAndCountInstruction(
1539  MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
1540  // FIXME: Add retpoline support and remove this.
1541  if (Subtarget->useIndirectThunkCalls())
1543  "Lowering patchpoint with thunks not yet implemented.");
1544  EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1545  }
1546 
1547  // Emit padding.
1548  unsigned NumBytes = opers.getNumPatchBytes();
1549  assert(NumBytes >= EncodedBytes &&
1550  "Patchpoint can't request size less than the length of a call.");
1551 
1552  emitX86Nops(*OutStreamer, NumBytes - EncodedBytes, Subtarget);
1553 }
1554 
1555 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1556  X86MCInstLower &MCIL) {
1557  assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1558 
1559  NoAutoPaddingScope NoPadScope(*OutStreamer);
1560 
1561  // We want to emit the following pattern, which follows the x86 calling
1562  // convention to prepare for the trampoline call to be patched in.
1563  //
1564  // .p2align 1, ...
1565  // .Lxray_event_sled_N:
1566  // jmp +N // jump across the instrumentation sled
1567  // ... // set up arguments in register
1568  // callq __xray_CustomEvent@plt // force dependency to symbol
1569  // ...
1570  // <jump here>
1571  //
1572  // After patching, it would look something like:
1573  //
1574  // nopw (2-byte nop)
1575  // ...
1576  // callq __xrayCustomEvent // already lowered
1577  // ...
1578  //
1579  // ---
1580  // First we emit the label and the jump.
1581  auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true);
1582  OutStreamer->AddComment("# XRay Custom Event Log");
1583  OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1584  OutStreamer->emitLabel(CurSled);
1585 
1586  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1587  // an operand (computed as an offset from the jmp instruction).
1588  // FIXME: Find another less hacky way do force the relative jump.
1589  OutStreamer->emitBinaryData("\xeb\x0f");
1590 
1591  // The default C calling convention will place two arguments into %rcx and
1592  // %rdx -- so we only work with those.
1593  const Register DestRegs[] = {X86::RDI, X86::RSI};
1594  bool UsedMask[] = {false, false};
1595  // Filled out in loop.
1596  Register SrcRegs[] = {0, 0};
1597 
1598  // Then we put the operands in the %rdi and %rsi registers. We spill the
1599  // values in the register before we clobber them, and mark them as used in
1600  // UsedMask. In case the arguments are already in the correct register, we use
1601  // emit nops appropriately sized to keep the sled the same size in every
1602  // situation.
1603  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1604  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1605  assert(Op->isReg() && "Only support arguments in registers");
1606  SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64);
1607  if (SrcRegs[I] != DestRegs[I]) {
1608  UsedMask[I] = true;
1609  EmitAndCountInstruction(
1610  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1611  } else {
1612  emitX86Nops(*OutStreamer, 4, Subtarget);
1613  }
1614  }
1615 
1616  // Now that the register values are stashed, mov arguments into place.
1617  // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1618  // earlier DestReg. We will have already overwritten over the register before
1619  // we can copy from it.
1620  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1621  if (SrcRegs[I] != DestRegs[I])
1622  EmitAndCountInstruction(
1623  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1624 
1625  // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1626  // name of the trampoline to be implemented by the XRay runtime.
1627  auto TSym = OutContext.getOrCreateSymbol("__xray_CustomEvent");
1629  if (isPositionIndependent())
1631 
1632  // Emit the call instruction.
1633  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1634  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1635 
1636  // Restore caller-saved and used registers.
1637  for (unsigned I = sizeof UsedMask; I-- > 0;)
1638  if (UsedMask[I])
1639  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1640  else
1641  emitX86Nops(*OutStreamer, 1, Subtarget);
1642 
1643  OutStreamer->AddComment("xray custom event end.");
1644 
1645  // Record the sled version. Version 0 of this sled was spelled differently, so
1646  // we let the runtime handle the different offsets we're using. Version 2
1647  // changed the absolute address to a PC-relative address.
1648  recordSled(CurSled, MI, SledKind::CUSTOM_EVENT, 2);
1649 }
1650 
1651 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1652  X86MCInstLower &MCIL) {
1653  assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1654 
1655  NoAutoPaddingScope NoPadScope(*OutStreamer);
1656 
1657  // We want to emit the following pattern, which follows the x86 calling
1658  // convention to prepare for the trampoline call to be patched in.
1659  //
1660  // .p2align 1, ...
1661  // .Lxray_event_sled_N:
1662  // jmp +N // jump across the instrumentation sled
1663  // ... // set up arguments in register
1664  // callq __xray_TypedEvent@plt // force dependency to symbol
1665  // ...
1666  // <jump here>
1667  //
1668  // After patching, it would look something like:
1669  //
1670  // nopw (2-byte nop)
1671  // ...
1672  // callq __xrayTypedEvent // already lowered
1673  // ...
1674  //
1675  // ---
1676  // First we emit the label and the jump.
1677  auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true);
1678  OutStreamer->AddComment("# XRay Typed Event Log");
1679  OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1680  OutStreamer->emitLabel(CurSled);
1681 
1682  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1683  // an operand (computed as an offset from the jmp instruction).
1684  // FIXME: Find another less hacky way do force the relative jump.
1685  OutStreamer->emitBinaryData("\xeb\x14");
1686 
1687  // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1688  // so we'll work with those. Or we may be called via SystemV, in which case
1689  // we don't have to do any translation.
1690  const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1691  bool UsedMask[] = {false, false, false};
1692 
1693  // Will fill out src regs in the loop.
1694  Register SrcRegs[] = {0, 0, 0};
1695 
1696  // Then we put the operands in the SystemV registers. We spill the values in
1697  // the registers before we clobber them, and mark them as used in UsedMask.
1698  // In case the arguments are already in the correct register, we emit nops
1699  // appropriately sized to keep the sled the same size in every situation.
1700  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1701  if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1702  // TODO: Is register only support adequate?
1703  assert(Op->isReg() && "Only supports arguments in registers");
1704  SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64);
1705  if (SrcRegs[I] != DestRegs[I]) {
1706  UsedMask[I] = true;
1707  EmitAndCountInstruction(
1708  MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I]));
1709  } else {
1710  emitX86Nops(*OutStreamer, 4, Subtarget);
1711  }
1712  }
1713 
1714  // In the above loop we only stash all of the destination registers or emit
1715  // nops if the arguments are already in the right place. Doing the actually
1716  // moving is postponed until after all the registers are stashed so nothing
1717  // is clobbers. We've already added nops to account for the size of mov and
1718  // push if the register is in the right place, so we only have to worry about
1719  // emitting movs.
1720  // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1721  // earlier DestReg. We will have already overwritten over the register before
1722  // we can copy from it.
1723  for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1724  if (UsedMask[I])
1725  EmitAndCountInstruction(
1726  MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I]));
1727 
1728  // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1729  // name of the trampoline to be implemented by the XRay runtime.
1730  auto TSym = OutContext.getOrCreateSymbol("__xray_TypedEvent");
1732  if (isPositionIndependent())
1734 
1735  // Emit the call instruction.
1736  EmitAndCountInstruction(MCInstBuilder(X86::CALL64pcrel32)
1737  .addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1738 
1739  // Restore caller-saved and used registers.
1740  for (unsigned I = sizeof UsedMask; I-- > 0;)
1741  if (UsedMask[I])
1742  EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I]));
1743  else
1744  emitX86Nops(*OutStreamer, 1, Subtarget);
1745 
1746  OutStreamer->AddComment("xray typed event end.");
1747 
1748  // Record the sled version.
1749  recordSled(CurSled, MI, SledKind::TYPED_EVENT, 2);
1750 }
1751 
1752 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1753  X86MCInstLower &MCIL) {
1754 
1755  NoAutoPaddingScope NoPadScope(*OutStreamer);
1756 
1757  const Function &F = MF->getFunction();
1758  if (F.hasFnAttribute("patchable-function-entry")) {
1759  unsigned Num;
1760  if (F.getFnAttribute("patchable-function-entry")
1761  .getValueAsString()
1762  .getAsInteger(10, Num))
1763  return;
1764  emitX86Nops(*OutStreamer, Num, Subtarget);
1765  return;
1766  }
1767  // We want to emit the following pattern:
1768  //
1769  // .p2align 1, ...
1770  // .Lxray_sled_N:
1771  // jmp .tmpN
1772  // # 9 bytes worth of noops
1773  //
1774  // We need the 9 bytes because at runtime, we'd be patching over the full 11
1775  // bytes with the following pattern:
1776  //
1777  // mov %r10, <function id, 32-bit> // 6 bytes
1778  // call <relative offset, 32-bits> // 5 bytes
1779  //
1780  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1781  OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1782  OutStreamer->emitLabel(CurSled);
1783 
1784  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1785  // an operand (computed as an offset from the jmp instruction).
1786  // FIXME: Find another less hacky way do force the relative jump.
1787  OutStreamer->emitBytes("\xeb\x09");
1788  emitX86Nops(*OutStreamer, 9, Subtarget);
1789  recordSled(CurSled, MI, SledKind::FUNCTION_ENTER, 2);
1790 }
1791 
1792 void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1793  X86MCInstLower &MCIL) {
1794  NoAutoPaddingScope NoPadScope(*OutStreamer);
1795 
1796  // Since PATCHABLE_RET takes the opcode of the return statement as an
1797  // argument, we use that to emit the correct form of the RET that we want.
1798  // i.e. when we see this:
1799  //
1800  // PATCHABLE_RET X86::RET ...
1801  //
1802  // We should emit the RET followed by sleds.
1803  //
1804  // .p2align 1, ...
1805  // .Lxray_sled_N:
1806  // ret # or equivalent instruction
1807  // # 10 bytes worth of noops
1808  //
1809  // This just makes sure that the alignment for the next instruction is 2.
1810  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1811  OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1812  OutStreamer->emitLabel(CurSled);
1813  unsigned OpCode = MI.getOperand(0).getImm();
1814  MCInst Ret;
1815  Ret.setOpcode(OpCode);
1816  for (auto &MO : drop_begin(MI.operands()))
1817  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1818  Ret.addOperand(*MaybeOperand);
1819  OutStreamer->emitInstruction(Ret, getSubtargetInfo());
1820  emitX86Nops(*OutStreamer, 10, Subtarget);
1821  recordSled(CurSled, MI, SledKind::FUNCTION_EXIT, 2);
1822 }
1823 
1824 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1825  X86MCInstLower &MCIL) {
1826  NoAutoPaddingScope NoPadScope(*OutStreamer);
1827 
1828  // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1829  // instruction so we lower that particular instruction and its operands.
1830  // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1831  // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1832  // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1833  // tail call much like how we have it in PATCHABLE_RET.
1834  auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
1835  OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo());
1836  OutStreamer->emitLabel(CurSled);
1838 
1839  // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1840  // an operand (computed as an offset from the jmp instruction).
1841  // FIXME: Find another less hacky way do force the relative jump.
1842  OutStreamer->emitBytes("\xeb\x09");
1843  emitX86Nops(*OutStreamer, 9, Subtarget);
1844  OutStreamer->emitLabel(Target);
1845  recordSled(CurSled, MI, SledKind::TAIL_CALL, 2);
1846 
1847  unsigned OpCode = MI.getOperand(0).getImm();
1848  OpCode = convertTailJumpOpcode(OpCode);
1849  MCInst TC;
1850  TC.setOpcode(OpCode);
1851 
1852  // Before emitting the instruction, add a comment to indicate that this is
1853  // indeed a tail call.
1854  OutStreamer->AddComment("TAILCALL");
1855  for (auto &MO : drop_begin(MI.operands()))
1856  if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO))
1857  TC.addOperand(*MaybeOperand);
1858  OutStreamer->emitInstruction(TC, getSubtargetInfo());
1859 }
1860 
1861 // Returns instruction preceding MBBI in MachineFunction.
1862 // If MBBI is the first instruction of the first basic block, returns null.
1865  const MachineBasicBlock *MBB = MBBI->getParent();
1866  while (MBBI == MBB->begin()) {
1867  if (MBB == &MBB->getParent()->front())
1869  MBB = MBB->getPrevNode();
1870  MBBI = MBB->end();
1871  }
1872  --MBBI;
1873  return MBBI;
1874 }
1875 
1877  const MachineOperand &Op) {
1878  if (!Op.isCPI() || Op.getOffset() != 0)
1879  return nullptr;
1880 
1882  MI.getParent()->getParent()->getConstantPool()->getConstants();
1883  const MachineConstantPoolEntry &ConstantEntry = Constants[Op.getIndex()];
1884 
1885  // Bail if this is a machine constant pool entry, we won't be able to dig out
1886  // anything useful.
1887  if (ConstantEntry.isMachineConstantPoolEntry())
1888  return nullptr;
1889 
1890  return ConstantEntry.Val.ConstVal;
1891 }
1892 
1893 static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1894  unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1895  std::string Comment;
1896 
1897  // Compute the name for a register. This is really goofy because we have
1898  // multiple instruction printers that could (in theory) use different
1899  // names. Fortunately most people use the ATT style (outside of Windows)
1900  // and they actually agree on register naming here. Ultimately, this is
1901  // a comment, and so its OK if it isn't perfect.
1902  auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1903  return X86ATTInstPrinter::getRegisterName(RegNum);
1904  };
1905 
1906  const MachineOperand &DstOp = MI->getOperand(0);
1907  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1908  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1909 
1910  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1911  StringRef Src1Name =
1912  SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1913  StringRef Src2Name =
1914  SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1915 
1916  // One source operand, fix the mask to print all elements in one span.
1917  SmallVector<int, 8> ShuffleMask(Mask);
1918  if (Src1Name == Src2Name)
1919  for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1920  if (ShuffleMask[i] >= e)
1921  ShuffleMask[i] -= e;
1922 
1923  raw_string_ostream CS(Comment);
1924  CS << DstName;
1925 
1926  // Handle AVX512 MASK/MASXZ write mask comments.
1927  // MASK: zmmX {%kY}
1928  // MASKZ: zmmX {%kY} {z}
1929  if (SrcOp1Idx > 1) {
1930  assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
1931 
1932  const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1933  if (WriteMaskOp.isReg()) {
1934  CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1935 
1936  if (SrcOp1Idx == 2) {
1937  CS << " {z}";
1938  }
1939  }
1940  }
1941 
1942  CS << " = ";
1943 
1944  for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1945  if (i != 0)
1946  CS << ",";
1947  if (ShuffleMask[i] == SM_SentinelZero) {
1948  CS << "zero";
1949  continue;
1950  }
1951 
1952  // Otherwise, it must come from src1 or src2. Print the span of elements
1953  // that comes from this src.
1954  bool isSrc1 = ShuffleMask[i] < (int)e;
1955  CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1956 
1957  bool IsFirst = true;
1958  while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1959  (ShuffleMask[i] < (int)e) == isSrc1) {
1960  if (!IsFirst)
1961  CS << ',';
1962  else
1963  IsFirst = false;
1964  if (ShuffleMask[i] == SM_SentinelUndef)
1965  CS << "u";
1966  else
1967  CS << ShuffleMask[i] % (int)e;
1968  ++i;
1969  }
1970  CS << ']';
1971  --i; // For loop increments element #.
1972  }
1973  CS.flush();
1974 
1975  return Comment;
1976 }
1977 
1978 static void printConstant(const APInt &Val, raw_ostream &CS) {
1979  if (Val.getBitWidth() <= 64) {
1980  CS << Val.getZExtValue();
1981  } else {
1982  // print multi-word constant as (w0,w1)
1983  CS << "(";
1984  for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1985  if (i > 0)
1986  CS << ",";
1987  CS << Val.getRawData()[i];
1988  }
1989  CS << ")";
1990  }
1991 }
1992 
1993 static void printConstant(const APFloat &Flt, raw_ostream &CS) {
1994  SmallString<32> Str;
1995  // Force scientific notation to distinquish from integers.
1996  Flt.toString(Str, 0, 0);
1997  CS << Str;
1998 }
1999 
2000 static void printConstant(const Constant *COp, raw_ostream &CS) {
2001  if (isa<UndefValue>(COp)) {
2002  CS << "u";
2003  } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
2004  printConstant(CI->getValue(), CS);
2005  } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
2006  printConstant(CF->getValueAPF(), CS);
2007  } else {
2008  CS << "?";
2009  }
2010 }
2011 
2012 void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
2013  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
2014  assert(getSubtarget().isOSWindows() && "SEH_ instruction Windows only");
2015 
2016  // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
2017  if (EmitFPOData) {
2018  X86TargetStreamer *XTS =
2019  static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
2020  switch (MI->getOpcode()) {
2021  case X86::SEH_PushReg:
2022  XTS->emitFPOPushReg(MI->getOperand(0).getImm());
2023  break;
2024  case X86::SEH_StackAlloc:
2025  XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
2026  break;
2027  case X86::SEH_StackAlign:
2028  XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
2029  break;
2030  case X86::SEH_SetFrame:
2031  assert(MI->getOperand(1).getImm() == 0 &&
2032  ".cv_fpo_setframe takes no offset");
2033  XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
2034  break;
2035  case X86::SEH_EndPrologue:
2036  XTS->emitFPOEndPrologue();
2037  break;
2038  case X86::SEH_SaveReg:
2039  case X86::SEH_SaveXMM:
2040  case X86::SEH_PushFrame:
2041  llvm_unreachable("SEH_ directive incompatible with FPO");
2042  break;
2043  default:
2044  llvm_unreachable("expected SEH_ instruction");
2045  }
2046  return;
2047  }
2048 
2049  // Otherwise, use the .seh_ directives for all other Windows platforms.
2050  switch (MI->getOpcode()) {
2051  case X86::SEH_PushReg:
2052  OutStreamer->emitWinCFIPushReg(MI->getOperand(0).getImm());
2053  break;
2054 
2055  case X86::SEH_SaveReg:
2056  OutStreamer->emitWinCFISaveReg(MI->getOperand(0).getImm(),
2057  MI->getOperand(1).getImm());
2058  break;
2059 
2060  case X86::SEH_SaveXMM:
2061  OutStreamer->emitWinCFISaveXMM(MI->getOperand(0).getImm(),
2062  MI->getOperand(1).getImm());
2063  break;
2064 
2065  case X86::SEH_StackAlloc:
2066  OutStreamer->emitWinCFIAllocStack(MI->getOperand(0).getImm());
2067  break;
2068 
2069  case X86::SEH_SetFrame:
2070  OutStreamer->emitWinCFISetFrame(MI->getOperand(0).getImm(),
2071  MI->getOperand(1).getImm());
2072  break;
2073 
2074  case X86::SEH_PushFrame:
2075  OutStreamer->emitWinCFIPushFrame(MI->getOperand(0).getImm());
2076  break;
2077 
2078  case X86::SEH_EndPrologue:
2079  OutStreamer->emitWinCFIEndProlog();
2080  break;
2081 
2082  default:
2083  llvm_unreachable("expected SEH_ instruction");
2084  }
2085 }
2086 
2087 static unsigned getRegisterWidth(const MCOperandInfo &Info) {
2088  if (Info.RegClass == X86::VR128RegClassID ||
2089  Info.RegClass == X86::VR128XRegClassID)
2090  return 128;
2091  if (Info.RegClass == X86::VR256RegClassID ||
2092  Info.RegClass == X86::VR256XRegClassID)
2093  return 256;
2094  if (Info.RegClass == X86::VR512RegClassID)
2095  return 512;
2096  llvm_unreachable("Unknown register class!");
2097 }
2098 
2100  MCStreamer &OutStreamer) {
2101  switch (MI->getOpcode()) {
2102  // Lower PSHUFB and VPERMILP normally but add a comment if we can find
2103  // a constant shuffle mask. We won't be able to do this at the MC layer
2104  // because the mask isn't an immediate.
2105  case X86::PSHUFBrm:
2106  case X86::VPSHUFBrm:
2107  case X86::VPSHUFBYrm:
2108  case X86::VPSHUFBZ128rm:
2109  case X86::VPSHUFBZ128rmk:
2110  case X86::VPSHUFBZ128rmkz:
2111  case X86::VPSHUFBZ256rm:
2112  case X86::VPSHUFBZ256rmk:
2113  case X86::VPSHUFBZ256rmkz:
2114  case X86::VPSHUFBZrm:
2115  case X86::VPSHUFBZrmk:
2116  case X86::VPSHUFBZrmkz: {
2117  unsigned SrcIdx = 1;
2118  if (X86II::isKMasked(MI->getDesc().TSFlags)) {
2119  // Skip mask operand.
2120  ++SrcIdx;
2121  if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
2122  // Skip passthru operand.
2123  ++SrcIdx;
2124  }
2125  }
2126  unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp;
2127 
2128  assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) &&
2129  "Unexpected number of operands!");
2130 
2131  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2132  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2133  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2136  if (!Mask.empty())
2137  OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2138  }
2139  break;
2140  }
2141 
2142  case X86::VPERMILPSrm:
2143  case X86::VPERMILPSYrm:
2144  case X86::VPERMILPSZ128rm:
2145  case X86::VPERMILPSZ128rmk:
2146  case X86::VPERMILPSZ128rmkz:
2147  case X86::VPERMILPSZ256rm:
2148  case X86::VPERMILPSZ256rmk:
2149  case X86::VPERMILPSZ256rmkz:
2150  case X86::VPERMILPSZrm:
2151  case X86::VPERMILPSZrmk:
2152  case X86::VPERMILPSZrmkz:
2153  case X86::VPERMILPDrm:
2154  case X86::VPERMILPDYrm:
2155  case X86::VPERMILPDZ128rm:
2156  case X86::VPERMILPDZ128rmk:
2157  case X86::VPERMILPDZ128rmkz:
2158  case X86::VPERMILPDZ256rm:
2159  case X86::VPERMILPDZ256rmk:
2160  case X86::VPERMILPDZ256rmkz:
2161  case X86::VPERMILPDZrm:
2162  case X86::VPERMILPDZrmk:
2163  case X86::VPERMILPDZrmkz: {
2164  unsigned ElSize;
2165  switch (MI->getOpcode()) {
2166  default: llvm_unreachable("Invalid opcode");
2167  case X86::VPERMILPSrm:
2168  case X86::VPERMILPSYrm:
2169  case X86::VPERMILPSZ128rm:
2170  case X86::VPERMILPSZ256rm:
2171  case X86::VPERMILPSZrm:
2172  case X86::VPERMILPSZ128rmkz:
2173  case X86::VPERMILPSZ256rmkz:
2174  case X86::VPERMILPSZrmkz:
2175  case X86::VPERMILPSZ128rmk:
2176  case X86::VPERMILPSZ256rmk:
2177  case X86::VPERMILPSZrmk:
2178  ElSize = 32;
2179  break;
2180  case X86::VPERMILPDrm:
2181  case X86::VPERMILPDYrm:
2182  case X86::VPERMILPDZ128rm:
2183  case X86::VPERMILPDZ256rm:
2184  case X86::VPERMILPDZrm:
2185  case X86::VPERMILPDZ128rmkz:
2186  case X86::VPERMILPDZ256rmkz:
2187  case X86::VPERMILPDZrmkz:
2188  case X86::VPERMILPDZ128rmk:
2189  case X86::VPERMILPDZ256rmk:
2190  case X86::VPERMILPDZrmk:
2191  ElSize = 64;
2192  break;
2193  }
2194 
2195  unsigned SrcIdx = 1;
2196  if (X86II::isKMasked(MI->getDesc().TSFlags)) {
2197  // Skip mask operand.
2198  ++SrcIdx;
2199  if (X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
2200  // Skip passthru operand.
2201  ++SrcIdx;
2202  }
2203  }
2204  unsigned MaskIdx = SrcIdx + 1 + X86::AddrDisp;
2205 
2206  assert(MI->getNumOperands() >= (SrcIdx + 1 + X86::AddrNumOperands) &&
2207  "Unexpected number of operands!");
2208 
2209  const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2210  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2211  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2213  DecodeVPERMILPMask(C, ElSize, Width, Mask);
2214  if (!Mask.empty())
2215  OutStreamer.AddComment(getShuffleComment(MI, SrcIdx, SrcIdx, Mask));
2216  }
2217  break;
2218  }
2219 
2220  case X86::VPERMIL2PDrm:
2221  case X86::VPERMIL2PSrm:
2222  case X86::VPERMIL2PDYrm:
2223  case X86::VPERMIL2PSYrm: {
2224  assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands + 1) &&
2225  "Unexpected number of operands!");
2226 
2227  const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2228  if (!CtrlOp.isImm())
2229  break;
2230 
2231  unsigned ElSize;
2232  switch (MI->getOpcode()) {
2233  default: llvm_unreachable("Invalid opcode");
2234  case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
2235  case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
2236  }
2237 
2238  const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp);
2239  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2240  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2242  DecodeVPERMIL2PMask(C, (unsigned)CtrlOp.getImm(), ElSize, Width, Mask);
2243  if (!Mask.empty())
2244  OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask));
2245  }
2246  break;
2247  }
2248 
2249  case X86::VPPERMrrm: {
2250  assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands) &&
2251  "Unexpected number of operands!");
2252 
2253  const MachineOperand &MaskOp = MI->getOperand(3 + X86::AddrDisp);
2254  if (auto *C = getConstantFromPool(*MI, MaskOp)) {
2255  unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
2258  if (!Mask.empty())
2259  OutStreamer.AddComment(getShuffleComment(MI, 1, 2, Mask));
2260  }
2261  break;
2262  }
2263 
2264  case X86::MMX_MOVQ64rm: {
2265  assert(MI->getNumOperands() == (1 + X86::AddrNumOperands) &&
2266  "Unexpected number of operands!");
2267  if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
2268  std::string Comment;
2269  raw_string_ostream CS(Comment);
2270  const MachineOperand &DstOp = MI->getOperand(0);
2272  if (auto *CF = dyn_cast<ConstantFP>(C)) {
2273  CS << "0x" << toString(CF->getValueAPF().bitcastToAPInt(), 16, false);
2274  OutStreamer.AddComment(CS.str());
2275  }
2276  }
2277  break;
2278  }
2279 
2280 #define MOV_CASE(Prefix, Suffix) \
2281  case X86::Prefix##MOVAPD##Suffix##rm: \
2282  case X86::Prefix##MOVAPS##Suffix##rm: \
2283  case X86::Prefix##MOVUPD##Suffix##rm: \
2284  case X86::Prefix##MOVUPS##Suffix##rm: \
2285  case X86::Prefix##MOVDQA##Suffix##rm: \
2286  case X86::Prefix##MOVDQU##Suffix##rm:
2287 
2288 #define MOV_AVX512_CASE(Suffix) \
2289  case X86::VMOVDQA64##Suffix##rm: \
2290  case X86::VMOVDQA32##Suffix##rm: \
2291  case X86::VMOVDQU64##Suffix##rm: \
2292  case X86::VMOVDQU32##Suffix##rm: \
2293  case X86::VMOVDQU16##Suffix##rm: \
2294  case X86::VMOVDQU8##Suffix##rm: \
2295  case X86::VMOVAPS##Suffix##rm: \
2296  case X86::VMOVAPD##Suffix##rm: \
2297  case X86::VMOVUPS##Suffix##rm: \
2298  case X86::VMOVUPD##Suffix##rm:
2299 
2300 #define CASE_ALL_MOV_RM() \
2301  MOV_CASE(, ) /* SSE */ \
2302  MOV_CASE(V, ) /* AVX-128 */ \
2303  MOV_CASE(V, Y) /* AVX-256 */ \
2304  MOV_AVX512_CASE(Z) \
2305  MOV_AVX512_CASE(Z256) \
2306  MOV_AVX512_CASE(Z128)
2307 
2308  // For loads from a constant pool to a vector register, print the constant
2309  // loaded.
2310  CASE_ALL_MOV_RM()
2311  case X86::VBROADCASTF128:
2312  case X86::VBROADCASTI128:
2313  case X86::VBROADCASTF32X4Z256rm:
2314  case X86::VBROADCASTF32X4rm:
2315  case X86::VBROADCASTF32X8rm:
2316  case X86::VBROADCASTF64X2Z128rm:
2317  case X86::VBROADCASTF64X2rm:
2318  case X86::VBROADCASTF64X4rm:
2319  case X86::VBROADCASTI32X4Z256rm:
2320  case X86::VBROADCASTI32X4rm:
2321  case X86::VBROADCASTI32X8rm:
2322  case X86::VBROADCASTI64X2Z128rm:
2323  case X86::VBROADCASTI64X2rm:
2324  case X86::VBROADCASTI64X4rm:
2325  assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) &&
2326  "Unexpected number of operands!");
2327  if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
2328  int NumLanes = 1;
2329  // Override NumLanes for the broadcast instructions.
2330  switch (MI->getOpcode()) {
2331  case X86::VBROADCASTF128: NumLanes = 2; break;
2332  case X86::VBROADCASTI128: NumLanes = 2; break;
2333  case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break;
2334  case X86::VBROADCASTF32X4rm: NumLanes = 4; break;
2335  case X86::VBROADCASTF32X8rm: NumLanes = 2; break;
2336  case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break;
2337  case X86::VBROADCASTF64X2rm: NumLanes = 4; break;
2338  case X86::VBROADCASTF64X4rm: NumLanes = 2; break;
2339  case X86::VBROADCASTI32X4Z256rm: NumLanes = 2; break;
2340  case X86::VBROADCASTI32X4rm: NumLanes = 4; break;
2341  case X86::VBROADCASTI32X8rm: NumLanes = 2; break;
2342  case X86::VBROADCASTI64X2Z128rm: NumLanes = 2; break;
2343  case X86::VBROADCASTI64X2rm: NumLanes = 4; break;
2344  case X86::VBROADCASTI64X4rm: NumLanes = 2; break;
2345  }
2346 
2347  std::string Comment;
2348  raw_string_ostream CS(Comment);
2349  const MachineOperand &DstOp = MI->getOperand(0);
2351  if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
2352  CS << "[";
2353  for (int l = 0; l != NumLanes; ++l) {
2354  for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2355  ++i) {
2356  if (i != 0 || l != 0)
2357  CS << ",";
2358  if (CDS->getElementType()->isIntegerTy())
2359  printConstant(CDS->getElementAsAPInt(i), CS);
2360  else if (CDS->getElementType()->isHalfTy() ||
2361  CDS->getElementType()->isFloatTy() ||
2362  CDS->getElementType()->isDoubleTy())
2363  printConstant(CDS->getElementAsAPFloat(i), CS);
2364  else
2365  CS << "?";
2366  }
2367  }
2368  CS << "]";
2369  OutStreamer.AddComment(CS.str());
2370  } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
2371  CS << "<";
2372  for (int l = 0; l != NumLanes; ++l) {
2373  for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2374  ++i) {
2375  if (i != 0 || l != 0)
2376  CS << ",";
2377  printConstant(CV->getOperand(i), CS);
2378  }
2379  }
2380  CS << ">";
2381  OutStreamer.AddComment(CS.str());
2382  }
2383  }
2384  break;
2385 
2386  case X86::MOVDDUPrm:
2387  case X86::VMOVDDUPrm:
2388  case X86::VMOVDDUPZ128rm:
2389  case X86::VBROADCASTSSrm:
2390  case X86::VBROADCASTSSYrm:
2391  case X86::VBROADCASTSSZ128rm:
2392  case X86::VBROADCASTSSZ256rm:
2393  case X86::VBROADCASTSSZrm:
2394  case X86::VBROADCASTSDYrm:
2395  case X86::VBROADCASTSDZ256rm:
2396  case X86::VBROADCASTSDZrm:
2397  case X86::VPBROADCASTBrm:
2398  case X86::VPBROADCASTBYrm:
2399  case X86::VPBROADCASTBZ128rm:
2400  case X86::VPBROADCASTBZ256rm:
2401  case X86::VPBROADCASTBZrm:
2402  case X86::VPBROADCASTDrm:
2403  case X86::VPBROADCASTDYrm:
2404  case X86::VPBROADCASTDZ128rm:
2405  case X86::VPBROADCASTDZ256rm:
2406  case X86::VPBROADCASTDZrm:
2407  case X86::VPBROADCASTQrm:
2408  case X86::VPBROADCASTQYrm:
2409  case X86::VPBROADCASTQZ128rm:
2410  case X86::VPBROADCASTQZ256rm:
2411  case X86::VPBROADCASTQZrm:
2412  case X86::VPBROADCASTWrm:
2413  case X86::VPBROADCASTWYrm:
2414  case X86::VPBROADCASTWZ128rm:
2415  case X86::VPBROADCASTWZ256rm:
2416  case X86::VPBROADCASTWZrm:
2417  assert(MI->getNumOperands() >= (1 + X86::AddrNumOperands) &&
2418  "Unexpected number of operands!");
2419  if (auto *C = getConstantFromPool(*MI, MI->getOperand(1 + X86::AddrDisp))) {
2420  int NumElts;
2421  switch (MI->getOpcode()) {
2422  default: llvm_unreachable("Invalid opcode");
2423  case X86::MOVDDUPrm: NumElts = 2; break;
2424  case X86::VMOVDDUPrm: NumElts = 2; break;
2425  case X86::VMOVDDUPZ128rm: NumElts = 2; break;
2426  case X86::VBROADCASTSSrm: NumElts = 4; break;
2427  case X86::VBROADCASTSSYrm: NumElts = 8; break;
2428  case X86::VBROADCASTSSZ128rm: NumElts = 4; break;
2429  case X86::VBROADCASTSSZ256rm: NumElts = 8; break;
2430  case X86::VBROADCASTSSZrm: NumElts = 16; break;
2431  case X86::VBROADCASTSDYrm: NumElts = 4; break;
2432  case X86::VBROADCASTSDZ256rm: NumElts = 4; break;
2433  case X86::VBROADCASTSDZrm: NumElts = 8; break;
2434  case X86::VPBROADCASTBrm: NumElts = 16; break;
2435  case X86::VPBROADCASTBYrm: NumElts = 32; break;
2436  case X86::VPBROADCASTBZ128rm: NumElts = 16; break;
2437  case X86::VPBROADCASTBZ256rm: NumElts = 32; break;
2438  case X86::VPBROADCASTBZrm: NumElts = 64; break;
2439  case X86::VPBROADCASTDrm: NumElts = 4; break;
2440  case X86::VPBROADCASTDYrm: NumElts = 8; break;
2441  case X86::VPBROADCASTDZ128rm: NumElts = 4; break;
2442  case X86::VPBROADCASTDZ256rm: NumElts = 8; break;
2443  case X86::VPBROADCASTDZrm: NumElts = 16; break;
2444  case X86::VPBROADCASTQrm: NumElts = 2; break;
2445  case X86::VPBROADCASTQYrm: NumElts = 4; break;
2446  case X86::VPBROADCASTQZ128rm: NumElts = 2; break;
2447  case X86::VPBROADCASTQZ256rm: NumElts = 4; break;
2448  case X86::VPBROADCASTQZrm: NumElts = 8; break;
2449  case X86::VPBROADCASTWrm: NumElts = 8; break;
2450  case X86::VPBROADCASTWYrm: NumElts = 16; break;
2451  case X86::VPBROADCASTWZ128rm: NumElts = 8; break;
2452  case X86::VPBROADCASTWZ256rm: NumElts = 16; break;
2453  case X86::VPBROADCASTWZrm: NumElts = 32; break;
2454  }
2455 
2456  std::string Comment;
2457  raw_string_ostream CS(Comment);
2458  const MachineOperand &DstOp = MI->getOperand(0);
2460  CS << "[";
2461  for (int i = 0; i != NumElts; ++i) {
2462  if (i != 0)
2463  CS << ",";
2464  printConstant(C, CS);
2465  }
2466  CS << "]";
2467  OutStreamer.AddComment(CS.str());
2468  }
2469  }
2470 }
2471 
2473  // FIXME: Enable feature predicate checks once all the test pass.
2474  // X86_MC::verifyInstructionPredicates(MI->getOpcode(),
2475  // Subtarget->getFeatureBits());
2476 
2477  X86MCInstLower MCInstLowering(*MF, *this);
2478  const X86RegisterInfo *RI =
2479  MF->getSubtarget<X86Subtarget>().getRegisterInfo();
2480 
2481  if (MI->getOpcode() == X86::OR64rm) {
2482  for (auto &Opd : MI->operands()) {
2483  if (Opd.isSymbol() && StringRef(Opd.getSymbolName()) ==
2484  "swift_async_extendedFramePointerFlags") {
2485  ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags = true;
2486  }
2487  }
2488  }
2489 
2490  // Add a comment about EVEX-2-VEX compression for AVX-512 instrs that
2491  // are compressed from EVEX encoding to VEX encoding.
2493  if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
2494  OutStreamer->AddComment("EVEX TO VEX Compression ", false);
2495  }
2496 
2497  // Add comments for values loaded from constant pool.
2498  if (OutStreamer->isVerboseAsm())
2500 
2501  switch (MI->getOpcode()) {
2502  case TargetOpcode::DBG_VALUE:
2503  llvm_unreachable("Should be handled target independently");
2504 
2505  // Emit nothing here but a comment if we can.
2506  case X86::Int_MemBarrier:
2507  OutStreamer->emitRawComment("MEMBARRIER");
2508  return;
2509 
2510  case X86::EH_RETURN:
2511  case X86::EH_RETURN64: {
2512  // Lower these as normal, but add some comments.
2513  Register Reg = MI->getOperand(0).getReg();
2514  OutStreamer->AddComment(StringRef("eh_return, addr: %") +
2516  break;
2517  }
2518  case X86::CLEANUPRET: {
2519  // Lower these as normal, but add some comments.
2520  OutStreamer->AddComment("CLEANUPRET");
2521  break;
2522  }
2523 
2524  case X86::CATCHRET: {
2525  // Lower these as normal, but add some comments.
2526  OutStreamer->AddComment("CATCHRET");
2527  break;
2528  }
2529 
2530  case X86::ENDBR32:
2531  case X86::ENDBR64: {
2532  // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
2533  // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
2534  // non-empty. If MI is the initial ENDBR, place the
2535  // __patchable_function_entries label after ENDBR.
2538  MI == &MF->front().front()) {
2539  MCInst Inst;
2540  MCInstLowering.Lower(MI, Inst);
2541  EmitAndCountInstruction(Inst);
2544  return;
2545  }
2546  break;
2547  }
2548 
2549  case X86::TAILJMPd64:
2550  if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11))
2551  EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX));
2552  [[fallthrough]];
2553  case X86::TAILJMPr:
2554  case X86::TAILJMPm:
2555  case X86::TAILJMPd:
2556  case X86::TAILJMPd_CC:
2557  case X86::TAILJMPr64:
2558  case X86::TAILJMPm64:
2559  case X86::TAILJMPd64_CC:
2560  case X86::TAILJMPr64_REX:
2561  case X86::TAILJMPm64_REX:
2562  // Lower these as normal, but add some comments.
2563  OutStreamer->AddComment("TAILCALL");
2564  break;
2565 
2566  case X86::TLS_addr32:
2567  case X86::TLS_addr64:
2568  case X86::TLS_addrX32:
2569  case X86::TLS_base_addr32:
2570  case X86::TLS_base_addr64:
2571  case X86::TLS_base_addrX32:
2572  return LowerTlsAddr(MCInstLowering, *MI);
2573 
2574  case X86::MOVPC32r: {
2575  // This is a pseudo op for a two instruction sequence with a label, which
2576  // looks like:
2577  // call "L1$pb"
2578  // "L1$pb":
2579  // popl %esi
2580 
2581  // Emit the call.
2582  MCSymbol *PICBase = MF->getPICBaseSymbol();
2583  // FIXME: We would like an efficient form for this, so we don't have to do a
2584  // lot of extra uniquing.
2585  EmitAndCountInstruction(
2586  MCInstBuilder(X86::CALLpcrel32)
2587  .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
2588 
2589  const X86FrameLowering *FrameLowering =
2590  MF->getSubtarget<X86Subtarget>().getFrameLowering();
2591  bool hasFP = FrameLowering->hasFP(*MF);
2592 
2593  // TODO: This is needed only if we require precise CFA.
2594  bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
2595  !OutStreamer->getDwarfFrameInfos().back().End;
2596 
2597  int stackGrowth = -RI->getSlotSize();
2598 
2599  if (HasActiveDwarfFrame && !hasFP) {
2600  OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2601  }
2602 
2603  // Emit the label.
2604  OutStreamer->emitLabel(PICBase);
2605 
2606  // popl $reg
2607  EmitAndCountInstruction(
2608  MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
2609 
2610  if (HasActiveDwarfFrame && !hasFP) {
2611  OutStreamer->emitCFIAdjustCfaOffset(stackGrowth);
2612  }
2613  return;
2614  }
2615 
2616  case X86::ADD32ri: {
2617  // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
2618  if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
2619  break;
2620 
2621  // Okay, we have something like:
2622  // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
2623 
2624  // For this, we want to print something like:
2625  // MYGLOBAL + (. - PICBASE)
2626  // However, we can't generate a ".", so just emit a new label here and refer
2627  // to it.
2628  MCSymbol *DotSym = OutContext.createTempSymbol();
2629  OutStreamer->emitLabel(DotSym);
2630 
2631  // Now that we have emitted the label, lower the complex operand expression.
2632  MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
2633 
2634  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
2635  const MCExpr *PICBase =
2637  DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
2638 
2639  DotExpr = MCBinaryExpr::createAdd(
2640  MCSymbolRefExpr::create(OpSym, OutContext), DotExpr, OutContext);
2641 
2642  EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
2643  .addReg(MI->getOperand(0).getReg())
2644  .addReg(MI->getOperand(1).getReg())
2645  .addExpr(DotExpr));
2646  return;
2647  }
2648  case TargetOpcode::STATEPOINT:
2649  return LowerSTATEPOINT(*MI, MCInstLowering);
2650 
2651  case TargetOpcode::FAULTING_OP:
2652  return LowerFAULTING_OP(*MI, MCInstLowering);
2653 
2654  case TargetOpcode::FENTRY_CALL:
2655  return LowerFENTRY_CALL(*MI, MCInstLowering);
2656 
2657  case TargetOpcode::PATCHABLE_OP:
2658  return LowerPATCHABLE_OP(*MI, MCInstLowering);
2659 
2661  return LowerSTACKMAP(*MI);
2662 
2664  return LowerPATCHPOINT(*MI, MCInstLowering);
2665 
2666  case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2667  return LowerPATCHABLE_FUNCTION_ENTER(*MI, MCInstLowering);
2668 
2669  case TargetOpcode::PATCHABLE_RET:
2670  return LowerPATCHABLE_RET(*MI, MCInstLowering);
2671 
2672  case TargetOpcode::PATCHABLE_TAIL_CALL:
2673  return LowerPATCHABLE_TAIL_CALL(*MI, MCInstLowering);
2674 
2675  case TargetOpcode::PATCHABLE_EVENT_CALL:
2676  return LowerPATCHABLE_EVENT_CALL(*MI, MCInstLowering);
2677 
2678  case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2679  return LowerPATCHABLE_TYPED_EVENT_CALL(*MI, MCInstLowering);
2680 
2681  case X86::MORESTACK_RET:
2682  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2683  return;
2684 
2685  case X86::KCFI_CHECK:
2686  return LowerKCFI_CHECK(*MI);
2687 
2688  case X86::ASAN_CHECK_MEMACCESS:
2689  return LowerASAN_CHECK_MEMACCESS(*MI);
2690 
2691  case X86::MORESTACK_RET_RESTORE_R10:
2692  // Return, then restore R10.
2693  EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
2694  EmitAndCountInstruction(
2695  MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2696  return;
2697 
2698  case X86::SEH_PushReg:
2699  case X86::SEH_SaveReg:
2700  case X86::SEH_SaveXMM:
2701  case X86::SEH_StackAlloc:
2702  case X86::SEH_StackAlign:
2703  case X86::SEH_SetFrame:
2704  case X86::SEH_PushFrame:
2705  case X86::SEH_EndPrologue:
2706  EmitSEHInstruction(MI);
2707  return;
2708 
2709  case X86::SEH_Epilogue: {
2710  assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
2712  // Check if preceded by a call and emit nop if so.
2713  for (MBBI = PrevCrossBBInst(MBBI);
2715  MBBI = PrevCrossBBInst(MBBI)) {
2716  // Conservatively assume that pseudo instructions don't emit code and keep
2717  // looking for a call. We may emit an unnecessary nop in some cases.
2718  if (!MBBI->isPseudo()) {
2719  if (MBBI->isCall())
2720  EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
2721  break;
2722  }
2723  }
2724  return;
2725  }
2726  case X86::UBSAN_UD1:
2727  EmitAndCountInstruction(MCInstBuilder(X86::UD1Lm)
2728  .addReg(X86::EAX)
2729  .addReg(X86::EAX)
2730  .addImm(1)
2731  .addReg(X86::NoRegister)
2732  .addImm(MI->getOperand(0).getImm())
2733  .addReg(X86::NoRegister));
2734  return;
2735  case X86::CALL64pcrel32:
2736  if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(X86::R11))
2737  EmitAndCountInstruction(MCInstBuilder(X86::CS_PREFIX));
2738  break;
2739  }
2740 
2741  MCInst TmpInst;
2742  MCInstLowering.Lower(MI, TmpInst);
2743 
2744  // Stackmap shadows cannot include branch targets, so we can count the bytes
2745  // in a call towards the shadow, but must ensure that the no thread returns
2746  // in to the stackmap shadow. The only way to achieve this is if the call
2747  // is at the end of the shadow.
2748  if (MI->isCall()) {
2749  // Count then size of the call towards the shadow
2750  SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2751  // Then flush the shadow so that we fill with nops before the call, not
2752  // after it.
2753  SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
2754  // Then emit the call
2755  OutStreamer->emitInstruction(TmpInst, getSubtargetInfo());
2756  return;
2757  }
2758 
2759  EmitAndCountInstruction(TmpInst);
2760 }
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:739
i
i
Definition: README.txt:29
AddressSanitizer.h
llvm::X86II::MO_TLVP
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:553
llvm::X86II::MO_DARWIN_NONLAZY
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:542
llvm::X86II::MO_GOTTPOFF
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
Definition: X86BaseInfo.h:491
llvm::AsmPrinter::isPositionIndependent
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:374
MachineModuleInfoImpls.h
llvm::X86TargetStreamer::emitFPOStackAlloc
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
Definition: X86TargetStreamer.h:31
SimplifyShortImmForm
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form.
Definition: X86MCInstLower.cpp:326
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineConstantPoolEntry::Val
union llvm::MachineConstantPoolEntry::@193 Val
The constant itself.
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::dwarf::Constants
Constants
Definition: Dwarf.h:432
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::drop_begin
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:387
llvm::StackMaps::recordStatepoint
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:555
Optional.h
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MCSymbolRefExpr::VK_GOT
@ VK_GOT
Definition: MCExpr.h:198
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::AsmPrinter::recordSled
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
Definition: AsmPrinter.cpp:3973
X86Subtarget.h
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::X86TargetStreamer::emitFPOEndPrologue
virtual bool emitFPOEndPrologue(SMLoc L={})
Definition: X86TargetStreamer.h:25
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::AsmPrinter::createTempSymbol
MCSymbol * createTempSymbol(const Twine &Name) const
Definition: AsmPrinter.cpp:3530
llvm::APInt::getNumWords
unsigned getNumWords() const
Get the number of words.
Definition: APInt.h:1438
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::Function
Definition: Function.h:60
llvm::X86TargetStreamer::emitFPOStackAlign
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
Definition: X86TargetStreamer.h:34
llvm::AsmPrinter::SledKind::CUSTOM_EVENT
@ CUSTOM_EVENT
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:95
X86ShuffleDecode.h
llvm::MCInst::insert
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:224
MCCodeEmitter.h
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:628
NoAutoPaddingScope::changeAndComment
void changeAndComment(bool b)
Definition: X86MCInstLower.cpp:91
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCSectionELF.h
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::tgtok::Code
@ Code
Definition: TGLexer.h:50
llvm::MachineOperand::getBlockAddress
const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:577
llvm::TargetMachine::getMCRegisterInfo
const MCRegisterInfo * getMCRegisterInfo() const
Definition: TargetMachine.h:207
llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
Definition: X86BaseInfo.h:415
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::Module::getRtLibUseGOT
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Definition: Module.cpp:667
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
SimplifyMOVSX
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
Definition: X86MCInstLower.cpp:349
llvm::X86AsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: X86MCInstLower.cpp:2472
llvm::AsmPrinter::getNameWithPrefix
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:650
MCInstBuilder.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::SM_SentinelZero
@ SM_SentinelZero
Definition: X86ShuffleDecode.h:28
Saved
Fixup Statepoint Caller Saved
Definition: FixupStatepointCallerSaved.cpp:89
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition: MachineOperand.h:340
llvm::MachineOperand::isJTI
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:336
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1431
addConstantComments
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
Definition: X86MCInstLower.cpp:2099
llvm::M68kII::MO_PLT
@ MO_PLT
On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol name from ...
Definition: M68kBaseInfo.h:114
llvm::X86II::MO_TPOFF
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
Definition: X86BaseInfo.h:508
GetSymbolFromOperand
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
Definition: PPCMCInstLower.cpp:32
llvm::MCStreamer::setAllowAutoPadding
void setAllowAutoPadding(bool v)
Definition: MCStreamer.h:304
llvm::Optional
Definition: APInt.h:33
llvm::X86II::OpMapMask
@ OpMapMask
Definition: X86BaseInfo.h:803
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::HexagonII::Absolute
@ Absolute
Definition: HexagonBaseInfo.h:32
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
X86AsmPrinter.h
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
llvm::MCStreamer::getAllowAutoPadding
bool getAllowAutoPadding() const
Definition: MCStreamer.h:305
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::MipsII::MO_TLSGD
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:582
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
X86ATTInstPrinter.h
llvm::StackMaps::recordStackMap
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:524
NoAutoPaddingScope::OldAllowAutoPadding
const bool OldAllowAutoPadding
Definition: X86MCInstLower.cpp:85
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::MachineBasicBlock::const_iterator
MachineInstrBundleIterator< const MachineInstr > const_iterator
Definition: MachineBasicBlock.h:270
llvm::AsmPrinter::emitKCFITrapEntry
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
Definition: AsmPrinter.cpp:1369
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
llvm::MCAsmInfo::canRelaxRelocations
bool canRelaxRelocations() const
Definition: MCAsmInfo.h:875
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:58
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
CASE_ALL_MOV_RM
#define CASE_ALL_MOV_RM()
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
llvm::X86::AC_EVEX_2_VEX
@ AC_EVEX_2_VEX
Definition: X86InstrInfo.h:33
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:673
GlobalValue.h
TargetMachine.h
llvm::MCTargetOptions::ShowMCEncoding
bool ShowMCEncoding
Definition: MCTargetOptions.h:52
convertTailJumpOpcode
static unsigned convertTailJumpOpcode(unsigned Opcode)
Definition: X86MCInstLower.cpp:466
llvm::DecodePSHUFBMask
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
Definition: X86ShuffleDecode.cpp:292
SmallString.h
llvm::X86TargetStreamer::emitFPOPushReg
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
Definition: X86TargetStreamer.h:30
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
llvm::X86II::MO_PLT
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
Definition: X86BaseInfo.h:454
llvm::X86::IP_HAS_AD_SIZE
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:59
llvm::SystemZII::MO_INDNTPOFF
@ MO_INDNTPOFF
Definition: SystemZInstrInfo.h:74
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1044
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:108
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:99
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
emitX86Nops
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
Definition: X86MCInstLower.cpp:1227
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCSymbolELF.h
MCContext.h
llvm::MipsII::MO_TLSLDM
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
llvm::X86TargetStreamer::emitFPOSetFrame
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
Definition: X86TargetStreamer.h:35
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
MCSymbol.h
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::StringRef::getAsInteger
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:474
llvm::X86II::isX86_64ExtendedReg
bool isX86_64ExtendedReg(unsigned RegNo)
Definition: X86BaseInfo.h:1191
llvm::MCSymbolRefExpr::VK_TLSLDM
@ VK_TLSLDM
Definition: MCExpr.h:211
AddressSanitizerCommon.h
l
This requires reassociating to forms of expressions that are already something that reassoc doesn t think about yet These two functions should generate the same code on big endian int * l
Definition: README.txt:100
MCInst.h
llvm::MachineOperand::isMBB
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
Definition: MachineOperand.h:328
llvm::TargetOptions::MCOptions
MCTargetOptions MCOptions
Machine level options.
Definition: TargetOptions.h:442
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::Function::getFnAttribute
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:655
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1486
llvm::MCStreamer::emitRawComment
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
Definition: MCStreamer.cpp:121
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::X86II::MO_GOTPCREL_NORELAX
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:447
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:185
llvm::MCInst::setFlags
void setFlags(unsigned F)
Definition: MCInst.h:200
llvm::DecodeVPPERMMask
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
Definition: X86ShuffleDecode.cpp:324
llvm::MCSymbolRefExpr::VK_TLSLD
@ VK_TLSLD
Definition: MCExpr.h:210
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:519
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
llvm::AsmPrinter::SM
StackMaps SM
Definition: AsmPrinter.h:210
llvm::MachineOperand::setTargetFlags
void setTargetFlags(unsigned F)
Definition: MachineOperand.h:223
llvm::X86II::MO_TLVP_PIC_BASE
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
Definition: X86BaseInfo.h:559
llvm::AsmPrinter::CurrentPatchableFunctionEntrySym
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
Definition: AsmPrinter.h:117
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
Flt
@ Flt
Definition: TargetLibraryInfo.cpp:56
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
llvm::MCInst::erase
void erase(iterator I)
Definition: MCInst.h:216
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString< 256 >
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
getConstantFromPool
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
Definition: X86MCInstLower.cpp:1876
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
SimplifyShortMoveForm
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
Definition: X86MCInstLower.cpp:376
llvm::X86AsmPrinter
Definition: X86AsmPrinter.h:27
llvm::MachineModuleInfoCOFF
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
Definition: MachineModuleInfoImpls.h:85
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::PointerIntPair::getPointer
PointerTy getPointer() const
Definition: PointerIntPair.h:60
TSFlags
uint64_t TSFlags
Definition: RISCVInsertVSETVLI.cpp:595
llvm::MCID::Trap
@ Trap
Definition: MCInstrDesc.h:186
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::LegacyLegalizeActions::Lower
@ Lower
The operation itself must be expressed in terms of simpler actions on this target.
Definition: LegacyLegalizerInfo.h:58
llvm::APFloat
Definition: APFloat.h:716
NoAutoPaddingScope::NoAutoPaddingScope
NoAutoPaddingScope(MCStreamer &OS)
Definition: X86MCInstLower.cpp:86
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:547
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::CSKYII::MO_GOTOFF
@ MO_GOTOFF
Definition: CSKYBaseInfo.h:44
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::count
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1870
llvm::AsmPrinter::GetCPISymbol
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
Definition: AsmPrinter.cpp:3544
llvm::X86::IP_HAS_REPEAT
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:61
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::AArch64II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: AArch64BaseInfo.h:786
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::X86II::MO_GOTNTPOFF
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
Definition: X86BaseInfo.h:532
llvm::APInt::getRawData
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
Definition: APInt.h:550
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:447
llvm::X86II::MO_PIC_BASE_OFFSET
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
llvm::X86FrameLowering
Definition: X86FrameLowering.h:28
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:918
X86TargetStreamer.h
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3534
llvm::MCSymbolRefExpr::VK_PLT
@ VK_PLT
Definition: MCExpr.h:208
llvm::MCInst::begin
iterator begin()
Definition: MCInst.h:219
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::AsmPrinter::getSymbolPreferLocal
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
Definition: AsmPrinter.cpp:659
llvm::MCStreamer::emitInstruction
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:1096
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1048
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:384
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
MachineConstantPool.h
llvm::X86II::MO_DTPOFF
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
Definition: X86BaseInfo.h:516
llvm::AArch64II::MO_NO_FLAG
@ MO_NO_FLAG
Definition: AArch64BaseInfo.h:727
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::X86II::MRMSrcReg
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
Definition: X86BaseInfo.h:700
llvm::ilist_node_with_parent::getPrevNode
NodeTy * getPrevNode()
Definition: ilist_node.h:275
NoAutoPaddingScope
A RAII helper which defines a region of instructions which can't have padding added between them for ...
Definition: X86MCInstLower.cpp:83
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
Definition: MachineConstantPool.h:93
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:655
llvm::X86ATTInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo)
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:59
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::ARMII::MO_SECREL
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
Definition: ARMBaseInfo.h:281
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
llvm::DecodeVPERMILPMask
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
Definition: X86ShuffleDecode.cpp:476
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:102
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:94
iterator_range.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::MachineOperand::CreateMCSymbol
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
Definition: MachineOperand.h:913
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::X86II::VEX_W
@ VEX_W
Definition: X86BaseInfo.h:930
MCSection.h
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
Mangler.h
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AsmPrinter::SledKind::TYPED_EVENT
@ TYPED_EVENT
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Printer
Memory true print Memory SSA Printer
Definition: MemorySSA.cpp:80
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::AsmPrinter::GetJTISymbol
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
Definition: AsmPrinter.cpp:3572
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::AsmPrinter::SledKind::FUNCTION_EXIT
@ FUNCTION_EXIT
llvm::SM_SentinelUndef
@ SM_SentinelUndef
Definition: X86ShuffleDecode.h:28
TargetLoweringObjectFile.h
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:315
uint32_t
MCFixup.h
llvm::MachineModuleInfoCOFF::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:95
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MCSymbolRefExpr::VK_GOTPCREL
@ VK_GOTPCREL
Definition: MCExpr.h:202
llvm::FaultMaps::FaultKindMax
@ FaultKindMax
Definition: FaultMaps.h:27
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
llvm::X86II::TB
@ TB
Definition: X86BaseInfo.h:810
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AsmPrinter::MMI
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:105
llvm::AsmPrinter::SledKind::TAIL_CALL
@ TAIL_CALL
X86ShuffleDecodeConstantPool.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
getRegisterWidth
static unsigned getRegisterWidth(const MCOperandInfo &Info)
Definition: X86MCInstLower.cpp:2087
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
emitNop
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
Definition: X86MCInstLower.cpp:1110
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::ASanAccessInfo
Definition: AddressSanitizer.h:53
llvm::pdb::PDB_SymType::Label
@ Label
llvm::MachineConstantPoolEntry
This class is a data container for one entry in a MachineConstantPool.
Definition: MachineConstantPool.h:67
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::X86Subtarget::isTargetWindowsMSVC
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:291
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::toString
const char * toString(DWARFSectionKind Kind)
Definition: DWARFUnitIndex.h:67
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AsmPrinter::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:397
llvm::MachineOperand::MO_ExternalSymbol
@ MO_ExternalSymbol
Name of external global symbol.
Definition: MachineOperand.h:60
llvm::X86II::VEX
@ VEX
Definition: X86BaseInfo.h:913
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::StackMaps::recordPatchPoint
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:534
llvm::X86II::isKMasked
bool isKMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1231
llvm::MachineBasicBlock::front
MachineInstr & front()
Definition: MachineBasicBlock.h:284
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::X86II::MO_TLSLD
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
Definition: X86BaseInfo.h:473
llvm::X86II::EncodingMask
@ EncodingMask
Definition: X86BaseInfo.h:910
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
StackMaps.h
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
NoAutoPaddingScope::OS
MCStreamer & OS
Definition: X86MCInstLower.cpp:84
llvm::MCOperand::isExpr
bool isExpr() const
Definition: MCInst.h:65
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::X86TargetStreamer
X86 target streamer implementing x86-only assembly directives.
Definition: X86TargetStreamer.h:17
llvm::DecodeVPERMIL2PMask
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
Definition: X86ShuffleDecode.cpp:498
X86RegisterInfo.h
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
getRetOpcode
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
Definition: X86MCInstLower.cpp:427
llvm::FaultMaps::FaultKind
FaultKind
Definition: FaultMaps.h:23
llvm::MachineFunction::getPICBaseSymbol
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
Definition: MachineFunction.cpp:719
PrevCrossBBInst
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
Definition: X86MCInstLower.cpp:1864
X86BaseInfo.h
llvm::X86II::isKMergeMasked
bool isKMergeMasked(uint64_t TSFlags)
Definition: X86BaseInfo.h:1236
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::X86II::VEX_4V
@ VEX_4V
Definition: X86BaseInfo.h:936
llvm::getAddressSanitizerParams
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
Definition: AddressSanitizer.cpp:596
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:46
llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:87
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition: MachineOperand.h:617
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:158
N
#define N
llvm::DstOp
Definition: MachineIRBuilder.h:67
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
printConstant
static void printConstant(const APInt &Val, raw_ostream &CS)
Definition: X86MCInstLower.cpp:1978
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
NoAutoPaddingScope::~NoAutoPaddingScope
~NoAutoPaddingScope()
Definition: X86MCInstLower.cpp:90
llvm::AsmPrinter::CurrentFnBegin
MCSymbol * CurrentFnBegin
Definition: AsmPrinter.h:200
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:658
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
llvm::AsmPrinter::SledKind::FUNCTION_ENTER
@ FUNCTION_ENTER
llvm::MCStreamer::emitBytes
virtual void emitBytes(StringRef Data)
Emit the bytes in Data into the output.
Definition: MCStreamer.cpp:1212
MachineOperand.h
llvm::M68kII::MO_GOTPCREL
@ MO_GOTPCREL
On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...
Definition: M68kBaseInfo.h:108
llvm::X86AsmPrinter::getSubtarget
const X86Subtarget & getSubtarget() const
Definition: X86AsmPrinter.h:131
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1473
llvm::AArch64II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: AArch64BaseInfo.h:765
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::X86II::MO_ABS8
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
Definition: X86BaseInfo.h:570
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::X86II::MO_NTPOFF
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
Definition: X86BaseInfo.h:524
getShuffleComment
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
Definition: X86MCInstLower.cpp:1893
MachineFunction.h
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::X86::COND_E
@ COND_E
Definition: X86BaseInfo.h:85
TargetRegistry.h
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:646
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MachineConstantPoolEntry::ConstVal
const Constant * ConstVal
Definition: MachineConstantPool.h:71
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:150
llvm::X86Subtarget::useIndirectThunkCalls
bool useIndirectThunkCalls() const
Definition: X86Subtarget.h:231
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:770
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::MCStreamer::AddComment
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
Definition: MCStreamer.h:355
X86InstComments.h
llvm::MachineModuleInfoMachO
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
Definition: MachineModuleInfoImpls.h:28
llvm::FaultMaps::recordFaultingOp
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Definition: FaultMaps.cpp:28
llvm::MCCodeEmitter::encodeInstruction
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
LowerSymbolOperand
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
Definition: SparcMCInstLower.cpp:29