LLVM  14.0.0git
Macros | Functions | Variables
DAGCombiner.cpp File Reference
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/None.h"
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/Metadata.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <iterator>
#include <string>
#include <tuple>
#include <utility>
#include "llvm/IR/VPIntrinsics.def"

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "dagcombine"
 
#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...)   case ISD::SDOPC:
 

Functions

 STATISTIC (NodesCombined, "Number of dag nodes combined")
 
 STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created")
 
 STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created")
 
 STATISTIC (OpsNarrowed, "Number of load/op/store narrowed")
 
 STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int")
 
 STATISTIC (SlicedLoads, "Number of load sliced")
 
 STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops")
 
static void zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0)
 
static bool isConstantSplatVectorMaskForType (SDNode *N, EVT ScalarTy)
 
static bool isConstantOrConstantVector (SDValue N, bool NoOpaques=false)
 
static bool isAnyConstantBuildVector (SDValue V, bool NoOpaques=false)
 
static bool canSplitIdx (LoadSDNode *LD)
 
static SDValue getInputChainForNode (SDNode *N)
 Given a node, return its input chain if it has one, otherwise return a null sd operand. More...
 
static ConstantSDNodegetAsNonOpaqueConstant (SDValue N)
 If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr. More...
 
static bool canFoldInAddressingMode (SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI)
 Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode. More...
 
static SDValue foldAddSubBoolOfMaskedVal (SDNode *N, SelectionDAG &DAG)
 
static SDValue foldAddSubOfSignBit (SDNode *N, SelectionDAG &DAG)
 Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant. More...
 
static SDValue getAsCarry (const TargetLowering &TLI, SDValue V)
 
static SDValue foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL)
 Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1. More...
 
static SDValue extractBooleanFlip (SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force)
 Flips a boolean if it is cheaper to compute. More...
 
static SDValue combineADDCARRYDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N)
 If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (addcarry X, 0, (addcarry A, B, Z):Carry) More...
 
static SDValue combineCarryDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, const TargetLowering &TLI, SDValue Carry0, SDValue Carry1, SDNode *N)
 
static SDValue getTruncatedUSUBSAT (EVT DstVT, EVT SrcVT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &DL)
 
static SDValue tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations)
 
static bool isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const TargetLowering &TLI)
 Return true if divmod libcall is available. More...
 
static SDValue simplifyDivRem (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineShiftAnd1ToBitTest (SDNode *And, SelectionDAG &DAG)
 Try to replace shift/logic that tests if a bit is clear with mask + setcc. More...
 
static SDValue foldAndToUsubsat (SDNode *N, SelectionDAG &DAG)
 For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it. More...
 
static bool isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode * > Parts)
 Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap. More...
 
static bool isBSwapHWordPair (SDValue N, MutableArrayRef< SDNode * > Parts)
 
static SDValue matchBSwapHWordOrAndAnd (const TargetLowering &TLI, SelectionDAG &DAG, SDNode *N, SDValue N0, SDValue N1, EVT VT, EVT ShiftAmountTy)
 
static SDValue visitORCommutative (SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N)
 OR combines for which the commuted variant will be tried as well. More...
 
static SDValue stripConstantMask (SelectionDAG &DAG, SDValue Op, SDValue &Mask)
 
static bool matchRotateHalf (SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask)
 Match "(X shl/srl V1) & V2" where V2 may not be present. More...
 
static SDValue extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL)
 Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv. More...
 
static bool matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG, bool IsRotate)
 
static const Optional< ByteProvider > calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, bool Root=false)
 Recursively traverses the expression calculating the origin of the requested byte of the given value. More...
 
static unsigned littleEndianByteAt (unsigned BW, unsigned i)
 
static unsigned bigEndianByteAt (unsigned BW, unsigned i)
 
static Optional< bool > isBigEndian (const ArrayRef< int64_t > ByteOffsets, int64_t FirstOffset)
 
static SDValue stripTruncAndExt (SDValue Value)
 
static SDValue combineShiftOfShiftedLogic (SDNode *Shift, SelectionDAG &DAG)
 If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op. More...
 
static SDValue combineShiftToMULH (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
 
static SDValue combineABSToABD (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
 
static bool isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI)
 
static SDValue combineMinNumMaxNum (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG)
 Generate Min/Max node. More...
 
static SDValue foldSelectOfConstantsUsingSra (SDNode *N, SelectionDAG &DAG)
 If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask. More...
 
static SDValue foldBoolSelectToLogic (SDNode *N, SelectionDAG &DAG)
 
static SDValue ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG)
 
bool refineUniformBase (SDValue &BasePtr, SDValue &Index, SelectionDAG &DAG)
 
bool refineIndexType (MaskedGatherScatterSDNode *MGS, SDValue &Index, bool Scaled, SelectionDAG &DAG)
 
static bool isCompatibleLoad (SDValue N, unsigned ExtOpcode)
 Check if N satisfies: N is used once. More...
 
static SDValue tryToFoldExtendSelectLoad (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG)
 Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). More...
 
static SDValue tryToFoldExtendOfConstant (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes)
 Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants. More...
 
static bool ExtendUsesToFormExtLoad (EVT VT, SDNode *N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode * > &ExtendNodes, const TargetLowering &TLI)
 
static SDValue tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType)
 
static SDValue tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)
 
static SDValue tryToFoldExtOfMaskedLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)
 
static SDValue foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations)
 
static bool isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known)
 
static SDValue widenCtPop (SDNode *Extend, SelectionDAG &DAG)
 Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type. More...
 
static SDNodegetBuildPairElt (SDNode *N, unsigned i)
 
static unsigned getPPCf128HiElementSelector (const SelectionDAG &DAG)
 
static SDValue foldBitcastedFPLogic (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
 
static bool isContractableFMUL (const TargetOptions &Options, SDValue N)
 
static bool hasNoInfs (const TargetOptions &Options, SDValue N)
 
static bool CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N)
 copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) More...
 
static SDValue foldFPToIntToFP (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
 
static SDValue FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG)
 
static SDValue visitFMinMax (SelectionDAG &DAG, SDNode *N, APFloat(*Op)(const APFloat &, const APFloat &))
 
static bool getCombineLoadStoreParts (SDNode *N, unsigned Inc, unsigned Dec, bool &IsLoad, bool &IsMasked, SDValue &Ptr, const TargetLowering &TLI)
 
static bool shouldCombineToPostInc (SDNode *N, SDValue Ptr, SDNode *PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)
 
static SDNodegetPostIndexedLoadStoreOp (SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)
 
static ElementCount numVectorEltsOrZero (EVT T)
 
static bool areUsedBitsDense (const APInt &UsedBits)
 Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0. More...
 
static bool areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second)
 Check whether or not First and Second are next to each other in memory. More...
 
static void adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost)
 Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices. More...
 
static bool isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize)
 Check the profitability of all involved LoadedSlice. More...
 
static std::pair< unsigned, unsigned > CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain)
 Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out. More...
 
static SDValue ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode *St, DAGCombiner *DC)
 Check to see if IVal is something that provides a value as specified by MaskInfo. More...
 
static SDValue scalarizeExtractedBinop (SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations)
 Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector. More...
 
static SDValue reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG)
 
template<typename R , typename T >
static auto getFirstIndexOf (R &&Range, const T &Val)
 
static SDValue combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineConcatVectorOfConcatVectors (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineConcatVectorOfCasts (SDNode *N, SelectionDAG &DAG)
 
static SDValue getSubVectorSrc (SDValue V, SDValue Index, EVT SubVT)
 
static SDValue narrowInsertExtractVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations)
 
static SDValue narrowExtractedVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations)
 If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction. More...
 
static SDValue narrowExtractedVectorLoad (SDNode *Extract, SelectionDAG &DAG)
 If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector) More...
 
static SDValue foldShuffleOfConcatUndefs (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
 Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation. More...
 
static SDValue partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG)
 
static SDValue combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI)
 
static SDValue combineShuffleToVectorExtend (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
 
static SDValue combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG)
 
static SDValue combineShuffleOfSplatVal (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
 
static SDValue formSplatFromShuffles (ShuffleVectorSDNode *OuterShuf, SelectionDAG &DAG)
 Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X. More...
 
static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask)
 If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand. More...
 
static SDValue replaceShuffleOfInsert (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
 If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle. More...
 
static SDValue simplifyShuffleOfShuffle (ShuffleVectorSDNode *Shuf)
 If we have a unary shuffle of a shuffle, see if it can be folded away completely. More...
 
static SDValue scalarizeBinOpOfSplats (SDNode *N, SelectionDAG &DAG)
 If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat. More...
 

Variables

static cl::opt< bool > CombinerGlobalAA ("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))
 
static cl::opt< bool > UseTBAA ("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))
 
static cl::opt< std::string > CombinerAAOnlyFunc ("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))
 
static cl::opt< bool > StressLoadSlicing ("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))
 Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards. More...
 
static cl::opt< bool > MaySplitLoadIndex ("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))
 
static cl::opt< bool > EnableStoreMerging ("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))
 
static cl::opt< unsigned > TokenFactorInlineLimit ("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))
 
static cl::opt< unsigned > StoreMergeDependenceLimit ("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))
 
static cl::opt< bool > EnableReduceLoadOpStoreWidth ("combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence"))
 
static cl::opt< bool > EnableShrinkLoadReplaceStoreWithStore ("combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store"))
 

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

#define BEGIN_REGISTER_VP_SDNODE (   SDOPC,
  ... 
)    case ISD::SDOPC:

◆ DEBUG_TYPE

#define DEBUG_TYPE   "dagcombine"

Definition at line 80 of file DAGCombiner.cpp.

Function Documentation

◆ adjustCostForPairing()

static void adjustCostForPairing ( SmallVectorImpl< LoadedSlice > &  LoadedSlices,
LoadedSlice::Cost &  GlobalLSCost 
)
static

Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.

Precondition
GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices.

Definition at line 16378 of file DAGCombiner.cpp.

References areSlicesNextToEachOther(), assert(), First, and llvm::sort().

Referenced by isSlicingProfitable().

◆ areSlicesNextToEachOther()

static bool areSlicesNextToEachOther ( const LoadedSlice &  First,
const LoadedSlice &  Second 
)
static

Check whether or not First and Second are next to each other in memory.

This means that there is no hole between the bits loaded by First and the bits loaded by Second.

Definition at line 16363 of file DAGCombiner.cpp.

References areUsedBitsDense(), assert(), and First.

Referenced by adjustCostForPairing().

◆ areUsedBitsDense()

static bool areUsedBitsDense ( const APInt UsedBits)
static

Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.

Definition at line 16346 of file DAGCombiner.cpp.

References llvm::APInt::countLeadingZeros(), llvm::APInt::countTrailingZeros(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnes(), llvm::APInt::lshr(), and llvm::APInt::trunc().

Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().

◆ bigEndianByteAt()

static unsigned bigEndianByteAt ( unsigned  BW,
unsigned  i 
)
static

Definition at line 7287 of file DAGCombiner.cpp.

References i.

Referenced by isBigEndian().

◆ calculateByteProvider()

static const Optional<ByteProvider> calculateByteProvider ( SDValue  Op,
unsigned  Index,
unsigned  Depth,
bool  Root = false 
)
static

Recursively traverses the expression calculating the origin of the requested byte of the given value.

Returns None if the provider can't be calculated.

For all the values except the root of the expression verifies that the value has exactly one use and if it's not true return None. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression.

Because the parts of the expression are not allowed to have more than one use this function iterates over trees, not DAGs. So it never visits the same node more than once.

Definition at line 7197 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::BitWidth, llvm::ISD::BSWAP, llvm::Depth, getMemory(), llvm::SDValue::getScalarValueSizeInBits(), Index, llvm::ISD::LOAD, llvm::None, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ CanCombineFCOPYSIGN_EXTEND_ROUND()

static bool CanCombineFCOPYSIGN_EXTEND_ROUND ( SDNode N)
inlinestatic

copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y)

Definition at line 14511 of file DAGCombiner.cpp.

References llvm::MVT::f128, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::isVector(), and N.

◆ canFoldInAddressingMode()

static bool canFoldInAddressingMode ( SDNode N,
SDNode Use,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.

Definition at line 2051 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::TargetLoweringBase::isLegalAddressingMode(), llvm::ARM_MB::LD, N, Offset, llvm::ARM_MB::ST, and llvm::ISD::SUB.

Referenced by shouldCombineToPostInc().

◆ canSplitIdx()

static bool canSplitIdx ( LoadSDNode LD)
static

Definition at line 995 of file DAGCombiner.cpp.

References llvm::ARM_MB::LD, MaySplitLoadIndex, and llvm::ISD::TargetConstant.

◆ CheckForMaskedLoad()

static std::pair<unsigned, unsigned> CheckForMaskedLoad ( SDValue  V,
SDValue  Ptr,
SDValue  Chain 
)
static

◆ combineABSToABD()

static SDValue combineABSToABD ( SDNode N,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ combineADDCARRYDiamond()

static SDValue combineADDCARRYDiamond ( DAGCombiner &  Combiner,
SelectionDAG DAG,
SDValue  X,
SDValue  Carry0,
SDValue  Carry1,
SDNode N 
)
static

If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (addcarry X, 0, (addcarry A, B, Z):Carry)

The end result is usually an increase in operation required, but because the carry is now linearized, other tranforms can kick in and optimize the DAG.

Patterns typically look something like (uaddo A, B) / \ Carry Sum | \ | (addcarry *, 0, Z) | / \ Carry | / (addcarry X, *, *)

But numerous variation exist. Our goal is to identify A, B, X and Z and produce a combine with a single path for carry propagation.

First look for a suitable Z. It will present itself in the form of (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true

 (uaddo A, B)
      |
     Sum
      |

(addcarry *, 0, Z)

(addcarry A, 0, Z) | Sum | (uaddo *, B)

Definition at line 2975 of file DAGCombiner.cpp.

References llvm::ISD::ADDCARRY, B, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::isNullConstant(), llvm::isOneConstant(), N, llvm::ISD::UADDO, and X.

◆ combineCarryDiamond()

static SDValue combineCarryDiamond ( DAGCombiner &  Combiner,
SelectionDAG DAG,
const TargetLowering TLI,
SDValue  Carry0,
SDValue  Carry1,
SDNode N 
)
static

◆ combineConcatVectorOfCasts()

static SDValue combineConcatVectorOfCasts ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineConcatVectorOfConcatVectors()

static SDValue combineConcatVectorOfConcatVectors ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineConcatVectorOfExtracts()

static SDValue combineConcatVectorOfExtracts ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineConcatVectorOfScalars()

static SDValue combineConcatVectorOfScalars ( SDNode N,
SelectionDAG DAG 
)
static

◆ combineMinNumMaxNum()

static SDValue combineMinNumMaxNum ( const SDLoc DL,
EVT  VT,
SDValue  LHS,
SDValue  RHS,
SDValue  True,
SDValue  False,
ISD::CondCode  CC,
const TargetLowering TLI,
SelectionDAG DAG 
)
static

◆ combineShiftAnd1ToBitTest()

static SDValue combineShiftAnd1ToBitTest ( SDNode And,
SelectionDAG DAG 
)
static

◆ combineShiftOfShiftedLogic()

static SDValue combineShiftOfShiftedLogic ( SDNode Shift,
SelectionDAG DAG 
)
static

If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.

This is a throughput improvement.

Definition at line 8035 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), C1, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::ISD::OR, Shift, X, llvm::ISD::XOR, and Y.

◆ combineShiftToMULH()

static SDValue combineShiftToMULH ( SDNode N,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ combineShuffleOfScalars()

static SDValue combineShuffleOfScalars ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ combineShuffleOfSplatVal()

static SDValue combineShuffleOfSplatVal ( ShuffleVectorSDNode Shuf,
SelectionDAG DAG 
)
static

◆ combineShuffleToVectorExtend()

static SDValue combineShuffleToVectorExtend ( ShuffleVectorSDNode SVN,
SelectionDAG DAG,
const TargetLowering TLI,
bool  LegalOperations 
)
static

◆ combineTruncationShuffle()

static SDValue combineTruncationShuffle ( ShuffleVectorSDNode SVN,
SelectionDAG DAG 
)
static

◆ ConvertSelectToConcatVector()

static SDValue ConvertSelectToConcatVector ( SDNode N,
SelectionDAG DAG 
)
static

◆ ExtendUsesToFormExtLoad()

static bool ExtendUsesToFormExtLoad ( EVT  VT,
SDNode N,
SDValue  N0,
unsigned  ExtOpc,
SmallVectorImpl< SDNode * > &  ExtendNodes,
const TargetLowering TLI 
)
static

◆ extractBooleanFlip()

static SDValue extractBooleanFlip ( SDValue  V,
SelectionDAG DAG,
const TargetLowering TLI,
bool  Force 
)
static

Flips a boolean if it is cheaper to compute.

If the Force parameters is set, then the flip also occurs if computing the inverse is the same cost. This function returns an empty SDValue in case it cannot flip the boolean without increasing the cost of the computation. If you want to flip a boolean no matter what, use DAG.getLogicalNOT.

Definition at line 2767 of file DAGCombiner.cpp.

References llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getLogicalNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::XOR, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

◆ extractShiftForRotate()

static SDValue extractShiftForRotate ( SelectionDAG DAG,
SDValue  OppShift,
SDValue  ExtractFrom,
SDValue Mask,
const SDLoc DL 
)
static

Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.

This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.

Returns
An empty SDValue if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom based on the following patterns:

(or (add v v) (shrl v bitwidth-1)): expands (add v v) -> (shl v 1)

(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)

(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)

(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)

(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)

Such that in all cases, c3+c2==bitwidth(op v c1).

Definition at line 6653 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::DELETED_NODE, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::BitmaskEnumDetail::Mask(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().

◆ foldAddSubBoolOfMaskedVal()

static SDValue foldAddSubBoolOfMaskedVal ( SDNode N,
SelectionDAG DAG 
)
static

◆ foldAddSubMasked1()

static SDValue foldAddSubMasked1 ( bool  IsAdd,
SDValue  N0,
SDValue  N1,
SelectionDAG DAG,
const SDLoc DL 
)
static

Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.

If so, invert the opcode and bypass the mask operation.

Definition at line 2636 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isOneOrOneSplat(), and llvm::ISD::SUB.

◆ foldAddSubOfSignBit()

static SDValue foldAddSubOfSignBit ( SDNode N,
SelectionDAG DAG 
)
static

◆ foldAndToUsubsat()

static SDValue foldAndToUsubsat ( SDNode N,
SelectionDAG DAG 
)
static

◆ foldBitcastedFPLogic()

static SDValue foldBitcastedFPLogic ( SDNode N,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ foldBoolSelectToLogic()

static SDValue foldBoolSelectToLogic ( SDNode N,
SelectionDAG DAG 
)
static

◆ foldExtendedSignBitTest()

static SDValue foldExtendedSignBitTest ( SDNode N,
SelectionDAG DAG,
bool  LegalOperations 
)
static

◆ foldFPToIntToFP()

static SDValue foldFPToIntToFP ( SDNode N,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ FoldIntToFPToInt()

static SDValue FoldIntToFPToInt ( SDNode N,
SelectionDAG DAG 
)
static

◆ foldSelectOfConstantsUsingSra()

static SDValue foldSelectOfConstantsUsingSra ( SDNode N,
SelectionDAG DAG 
)
static

If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.

Definition at line 9356 of file DAGCombiner.cpp.

References llvm::ISD::AND, C1, Cond, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstantOrConstantVector(), llvm::isNullOrNullSplat(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SRA, and X.

◆ foldShuffleOfConcatUndefs()

static SDValue foldShuffleOfConcatUndefs ( ShuffleVectorSDNode Shuf,
SelectionDAG DAG 
)
static

Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.

Narrow vector ops may have better performance than wide ops, and this can unlock further narrowing of other vector ops. Targets can invert this transform later if it is not profitable.

Definition at line 20743 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), i, int, llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), M, llvm::BitmaskEnumDetail::Mask(), X, and Y.

◆ formSplatFromShuffles()

static SDValue formSplatFromShuffles ( ShuffleVectorSDNode OuterShuf,
SelectionDAG DAG 
)
static

◆ getAsCarry()

static SDValue getAsCarry ( const TargetLowering TLI,
SDValue  V 
)
static

◆ getAsNonOpaqueConstant()

static ConstantSDNode* getAsNonOpaqueConstant ( SDValue  N)
static

If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.

Definition at line 2044 of file DAGCombiner.cpp.

References N.

◆ getBuildPairElt()

static SDNode* getBuildPairElt ( SDNode N,
unsigned  i 
)
static

◆ getCombineLoadStoreParts()

static bool getCombineLoadStoreParts ( SDNode N,
unsigned  Inc,
unsigned  Dec,
bool &  IsLoad,
bool &  IsMasked,
SDValue Ptr,
const TargetLowering TLI 
)
static

◆ getFirstIndexOf()

template<typename R , typename T >
static auto getFirstIndexOf ( R &&  Range,
const T Val 
)
static

Definition at line 19513 of file DAGCombiner.cpp.

References llvm::sys::path::begin(), llvm::find(), and I.

◆ getInputChainForNode()

static SDValue getInputChainForNode ( SDNode N)
static

Given a node, return its input chain if it has one, otherwise return a null sd operand.

Definition at line 1821 of file DAGCombiner.cpp.

References i, N, and llvm::MVT::Other.

◆ getPostIndexedLoadStoreOp()

static SDNode* getPostIndexedLoadStoreOp ( SDNode N,
bool &  IsLoad,
bool &  IsMasked,
SDValue Ptr,
SDValue BasePtr,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ getPPCf128HiElementSelector()

static unsigned getPPCf128HiElementSelector ( const SelectionDAG DAG)
static

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()

static int getShuffleMaskIndexOfOneElementFromOp0IntoOp1 ( ArrayRef< int Mask)
static

If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.

Otherwise, return -1.

Definition at line 21174 of file DAGCombiner.cpp.

References i, and llvm::BitmaskEnumDetail::Mask().

Referenced by replaceShuffleOfInsert().

◆ getSubVectorSrc()

static SDValue getSubVectorSrc ( SDValue  V,
SDValue  Index,
EVT  SubVT 
)
static

◆ getTruncatedUSUBSAT()

static SDValue getTruncatedUSUBSAT ( EVT  DstVT,
EVT  SrcVT,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc DL 
)
static

◆ hasNoInfs()

static bool hasNoInfs ( const TargetOptions Options,
SDValue  N 
)
static

Definition at line 13065 of file DAGCombiner.cpp.

References N, and Options.

Referenced by llvm::SDNode::print_details().

◆ isAnyConstantBuildVector()

static bool isAnyConstantBuildVector ( SDValue  V,
bool  NoOpaques = false 
)
static

◆ isBigEndian()

static Optional<bool> isBigEndian ( const ArrayRef< int64_t >  ByteOffsets,
int64_t  FirstOffset 
)
static

◆ isBSwapHWordElement()

static bool isBSwapHWordElement ( SDValue  N,
MutableArrayRef< SDNode * >  Parts 
)
static

Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.

((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)

Definition at line 6150 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by isBSwapHWordPair().

◆ isBSwapHWordPair()

static bool isBSwapHWordPair ( SDValue  N,
MutableArrayRef< SDNode * >  Parts 
)
static

◆ isCompatibleLoad()

static bool isCompatibleLoad ( SDValue  N,
unsigned  ExtOpcode 
)
static

Check if N satisfies: N is used once.

N is a Load. The load is compatible with ExtOpcode. It means If load has explicit zero/sign extension, ExpOpcode must have the same extension. Otherwise returns true.

Definition at line 10373 of file DAGCombiner.cpp.

References llvm::ISD::EXTLOAD, llvm::SPII::Load, N, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

Referenced by tryToFoldExtendSelectLoad().

◆ isConstantOrConstantVector()

static bool isConstantOrConstantVector ( SDValue  N,
bool  NoOpaques = false 
)
static

Definition at line 968 of file DAGCombiner.cpp.

References llvm::BitWidth, llvm::ISD::BUILD_VECTOR, N, and llvm::ISD::SPLAT_VECTOR.

◆ isConstantSplatVectorMaskForType()

static bool isConstantSplatVectorMaskForType ( SDNode N,
EVT  ScalarTy 
)
static

◆ isContractableFMUL()

static bool isContractableFMUL ( const TargetOptions Options,
SDValue  N 
)
static

Definition at line 13057 of file DAGCombiner.cpp.

References assert(), llvm::FPOpFusion::Fast, llvm::ISD::FMUL, N, and Options.

◆ isDivRemLibcallAvailable()

static bool isDivRemLibcallAvailable ( SDNode Node,
bool  isSigned,
const TargetLowering TLI 
)
static

Return true if divmod libcall is available.

Definition at line 4002 of file DAGCombiner.cpp.

◆ isLegalToCombineMinNumMaxNum()

static bool isLegalToCombineMinNumMaxNum ( SelectionDAG DAG,
SDValue  LHS,
SDValue  RHS,
const TargetLowering TLI 
)
static

◆ isSlicingProfitable()

static bool isSlicingProfitable ( SmallVectorImpl< LoadedSlice > &  LoadedSlices,
const APInt UsedBits,
bool  ForCodeSize 
)
static

Check the profitability of all involved LoadedSlice.

Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (

See also
LoadedSlice::Cost) is smaller than the original load (3).

Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.

FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).

Definition at line 16444 of file DAGCombiner.cpp.

References adjustCostForPairing(), areUsedBitsDense(), llvm::AArch64CC::LS, and StressLoadSlicing.

◆ isTruncateOf()

static bool isTruncateOf ( SelectionDAG DAG,
SDValue  N,
SDValue Op,
KnownBits Known 
)
static

◆ littleEndianByteAt()

static unsigned littleEndianByteAt ( unsigned  BW,
unsigned  i 
)
static

Definition at line 7283 of file DAGCombiner.cpp.

References i.

Referenced by isBigEndian().

◆ matchBSwapHWordOrAndAnd()

static SDValue matchBSwapHWordOrAndAnd ( const TargetLowering TLI,
SelectionDAG DAG,
SDNode N,
SDValue  N0,
SDValue  N1,
EVT  VT,
EVT  ShiftAmountTy 
)
static

◆ matchRotateHalf()

static bool matchRotateHalf ( SelectionDAG DAG,
SDValue  Op,
SDValue Shift,
SDValue Mask 
)
static

Match "(X shl/srl V1) & V2" where V2 may not be present.

Definition at line 6619 of file DAGCombiner.cpp.

References llvm::BitmaskEnumDetail::Mask(), Shift, llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().

◆ matchRotateSub()

static bool matchRotateSub ( SDValue  Pos,
SDValue  Neg,
unsigned  EltSize,
SelectionDAG DAG,
bool  IsRotate 
)
static

◆ narrowExtractedVectorBinOp()

static SDValue narrowExtractedVectorBinOp ( SDNode Extract,
SelectionDAG DAG,
bool  LegalOperations 
)
static

◆ narrowExtractedVectorLoad()

static SDValue narrowExtractedVectorLoad ( SDNode Extract,
SelectionDAG DAG 
)
static

◆ narrowInsertExtractVectorBinOp()

static SDValue narrowInsertExtractVectorBinOp ( SDNode Extract,
SelectionDAG DAG,
bool  LegalOperations 
)
static

◆ numVectorEltsOrZero()

static ElementCount numVectorEltsOrZero ( EVT  T)
inlinestatic

◆ partitionShuffleOfConcats()

static SDValue partitionShuffleOfConcats ( SDNode N,
SelectionDAG DAG 
)
static

◆ reduceBuildVecToShuffleWithZero()

static SDValue reduceBuildVecToShuffleWithZero ( SDNode BV,
SelectionDAG DAG 
)
static

◆ refineIndexType()

bool refineIndexType ( MaskedGatherScatterSDNode MGS,
SDValue Index,
bool  Scaled,
SelectionDAG DAG 
)

◆ refineUniformBase()

bool refineUniformBase ( SDValue BasePtr,
SDValue Index,
SelectionDAG DAG 
)

◆ replaceShuffleOfInsert()

static SDValue replaceShuffleOfInsert ( ShuffleVectorSDNode Shuf,
SelectionDAG DAG 
)
static

◆ scalarizeBinOpOfSplats()

static SDValue scalarizeBinOpOfSplats ( SDNode N,
SelectionDAG DAG 
)
static

◆ scalarizeExtractedBinop()

static SDValue scalarizeExtractedBinop ( SDNode ExtElt,
SelectionDAG DAG,
bool  LegalOperations 
)
static

◆ shouldCombineToPostInc()

static bool shouldCombineToPostInc ( SDNode N,
SDValue  Ptr,
SDNode PtrUse,
SDValue BasePtr,
SDValue Offset,
ISD::MemIndexedMode AM,
SelectionDAG DAG,
const TargetLowering TLI 
)
static

◆ ShrinkLoadReplaceStoreWithStore()

static SDValue ShrinkLoadReplaceStoreWithStore ( const std::pair< unsigned, unsigned > &  MaskInfo,
SDValue  IVal,
StoreSDNode St,
DAGCombiner *  DC 
)
static

◆ simplifyDivRem()

static SDValue simplifyDivRem ( SDNode N,
SelectionDAG DAG 
)
static

◆ simplifyShuffleOfShuffle()

static SDValue simplifyShuffleOfShuffle ( ShuffleVectorSDNode Shuf)
static

If we have a unary shuffle of a shuffle, see if it can be folded away completely.

This has the potential to lose undef knowledge because the first shuffle may not have an undef mask element where the second one does. So only call this after doing simplifications based on demanded elements.

Definition at line 21251 of file DAGCombiner.cpp.

References assert(), llvm::numbers::e, llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), i, llvm::SDValue::isUndef(), and llvm::BitmaskEnumDetail::Mask().

◆ STATISTIC() [1/7]

STATISTIC ( LdStFP2Int  ,
"Number of fp load/store pairs transformed to int  
)

◆ STATISTIC() [2/7]

STATISTIC ( NodesCombined  ,
"Number of dag nodes combined"   
)

◆ STATISTIC() [3/7]

STATISTIC ( NumFPLogicOpsConv  ,
"Number of logic ops converted to fp ops  
)

◆ STATISTIC() [4/7]

STATISTIC ( OpsNarrowed  ,
"Number of load/op/store narrowed"   
)

◆ STATISTIC() [5/7]

STATISTIC ( PostIndexedNodes  ,
"Number of post-indexed nodes created"   
)

◆ STATISTIC() [6/7]

STATISTIC ( PreIndexedNodes  ,
"Number of pre-indexed nodes created"   
)

◆ STATISTIC() [7/7]

STATISTIC ( SlicedLoads  ,
"Number of load sliced"   
)

◆ stripConstantMask()

static SDValue stripConstantMask ( SelectionDAG DAG,
SDValue  Op,
SDValue Mask 
)
static

◆ stripTruncAndExt()

static SDValue stripTruncAndExt ( SDValue  Value)
static

◆ tryFoldToZero()

static SDValue tryFoldToZero ( const SDLoc DL,
const TargetLowering TLI,
EVT  VT,
SelectionDAG DAG,
bool  LegalOperations 
)
static

◆ tryToFoldExtendOfConstant()

static SDValue tryToFoldExtendOfConstant ( SDNode N,
const TargetLowering TLI,
SelectionDAG DAG,
bool  LegalTypes 
)
static

◆ tryToFoldExtendSelectLoad()

static SDValue tryToFoldExtendSelectLoad ( SDNode N,
const TargetLowering TLI,
SelectionDAG DAG 
)
static

Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).

Definition at line 10400 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), DL, llvm::ISD::EXTLOAD, llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::hasOneUse(), isCompatibleLoad(), llvm::TargetLoweringBase::isLoadExtLegal(), N, llvm::ISD::SELECT, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::VSELECT, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfExtload()

static SDValue tryToFoldExtOfExtload ( SelectionDAG DAG,
DAGCombiner &  Combiner,
const TargetLowering TLI,
EVT  VT,
bool  LegalOperations,
SDNode N,
SDValue  N0,
ISD::LoadExtType  ExtLoadType 
)
static

◆ tryToFoldExtOfLoad()

static SDValue tryToFoldExtOfLoad ( SelectionDAG DAG,
DAGCombiner &  Combiner,
const TargetLowering TLI,
EVT  VT,
bool  LegalOperations,
SDNode N,
SDValue  N0,
ISD::LoadExtType  ExtLoadType,
ISD::NodeType  ExtOpc 
)
static

◆ tryToFoldExtOfMaskedLoad()

static SDValue tryToFoldExtOfMaskedLoad ( SelectionDAG DAG,
const TargetLowering TLI,
EVT  VT,
SDNode N,
SDValue  N0,
ISD::LoadExtType  ExtLoadType,
ISD::NodeType  ExtOpc 
)
static

◆ visitFMinMax()

static SDValue visitFMinMax ( SelectionDAG DAG,
SDNode N,
APFloat(*)(const APFloat &, const APFloat &)  Op 
)
static

◆ visitORCommutative()

static SDValue visitORCommutative ( SelectionDAG DAG,
SDValue  N0,
SDValue  N1,
SDNode N 
)
static

OR combines for which the commuted variant will be tried as well.

Definition at line 6415 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::isBitwiseNot(), N, and llvm::ISD::OR.

◆ widenCtPop()

static SDValue widenCtPop ( SDNode Extend,
SelectionDAG DAG 
)
static

◆ zeroExtendToMatch()

static void zeroExtendToMatch ( APInt LHS,
APInt RHS,
unsigned  Offset = 0 
)
static

Variable Documentation

◆ CombinerAAOnlyFunc

cl::opt<std::string> CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function"))
static

◆ CombinerGlobalAA

cl::opt<bool> CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis"))
static

◆ EnableReduceLoadOpStoreWidth

cl::opt<bool> EnableReduceLoadOpStoreWidth("combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence"))
static

◆ EnableShrinkLoadReplaceStoreWithStore

cl::opt<bool> EnableShrinkLoadReplaceStoreWithStore("combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store"))
static

◆ EnableStoreMerging

cl::opt<bool> EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store"))
static

◆ MaySplitLoadIndex

cl::opt<bool> MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads"))
static

Referenced by canSplitIdx().

◆ StoreMergeDependenceLimit

cl::opt<unsigned> StoreMergeDependenceLimit("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check"))
static

◆ StressLoadSlicing

cl::opt<bool> StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false))
static

Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.

Referenced by isSlicingProfitable().

◆ TokenFactorInlineLimit

cl::opt<unsigned> TokenFactorInlineLimit("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors"))
static

◆ UseTBAA

cl::opt<bool> UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA"))
static