#include "SelectionDAGOptions.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IntervalMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/ByteProvider.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Metadata.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/DebugCounter.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <initializer_list>
#include <iterator>
#include <optional>
#include <string>
#include <tuple>
#include <utility>
#include <variant>
#include "SDNodeDbgValue.h"
#include "llvm/IR/VPIntrinsics.def"

Macros
#define	DEBUG_TYPE "dagcombine"
#define	BEGIN_REGISTER_VP_SDNODE(SDOPC, ...)

Typedefs
using	SDByteProvider = ByteProvider<SDNode *>
	Recursively traverses the expression calculating the origin of the requested byte of the given value.

Functions
	STATISTIC (NodesCombined, "Number of dag nodes combined")
	STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created")
	STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created")
	STATISTIC (OpsNarrowed, "Number of load/op/store narrowed")
	STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int")
	STATISTIC (SlicedLoads, "Number of load sliced")
	STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops")
	DEBUG_COUNTER (DAGCombineCounter, "dagcombine", "Controls whether a DAG combine is performed for a node")
static void	zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0)
static bool	isConstantSplatVectorMaskForType (SDNode *N, EVT ScalarTy)
static bool	isConstantOrConstantVector (SDValue N, bool NoOpaques=false, bool AllowTruncation=false)
static bool	isAnyConstantBuildVector (SDValue V, bool NoOpaques=false)
static bool	canSplitIdx (LoadSDNode *LD, const SelectionDAGOptions &Opts)
static SDValue	getInputChainForNode (SDNode *N)
	Given a node, return its input chain if it has one, otherwise return a null sd operand.
static ConstantSDNode *	getAsNonOpaqueConstant (SDValue N)
	If `N` is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.
static bool	isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known)
static bool	canFoldInAddressingMode (SDNode N, SDNode Use, SelectionDAG &DAG, const TargetLowering &TLI)
	Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.
static SDValue	foldSelectWithIdentityConstant (SDNode *N, SelectionDAG &DAG, bool ShouldCommuteOperands)
	This inverts a canonicalization in IR that replaces a variable select arm with an identity constant.
static SDValue	foldAddSubBoolOfMaskedVal (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	foldAddSubOfSignBit (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.
static bool	areBitwiseNotOfEachother (SDValue Op0, SDValue Op1)
static SDValue	getAsCarry (const TargetLowering &TLI, SDValue V, bool ForceCarryReconstruction=false)
static SDValue	foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL)
	Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.
static SDValue	extractBooleanFlip (SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force)
	Flips a boolean if it is cheaper to compute.
static SDValue	combineUADDO_CARRYDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N)
	If we are facing some sort of diamond carry propagation pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)
static SDValue	combineCarryDiamond (SelectionDAG &DAG, const TargetLowering &TLI, SDValue N0, SDValue N1, SDNode *N)
static SDValue	combineOrOfSetCCToUSUBOCarry (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	getTruncatedUSUBSAT (EVT DstVT, EVT SrcVT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &DL)
static SDValue	foldSubCtlzNot (SDNode *N, SelectionDAG &DAG)
static SDValue	foldRemainderIdiom (SDNode *N, SelectionDAG &DAG, const SDLoc &DL)
static SDValue	tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations)
static bool	isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const SelectionDAG &DAG)
	Return true if divmod libcall is available.
static SDValue	simplifyDivRem (SDNode *N, SelectionDAG &DAG)
static bool	isDivisorPowerOfTwo (SDValue Divisor)
static SDValue	isSaturatingMinMax (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, unsigned &BW, bool &Unsigned, SelectionDAG &DAG)
static SDValue	PerformMinMaxFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG)
static SDValue	PerformUMinFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG)
static SDValue	performNanGuardFpToSatCombine (SDNode *N, SelectionDAG &DAG)
static bool	areBothOperandsNotSNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG)
static bool	areBothOperandsNotNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG)
static unsigned	getMinMaxOpcodeForClamp (bool IsMin, SDValue Operand1, SDValue Operand2, SelectionDAG &DAG, const TargetLowering &TLI)
	Returns an appropriate FP min/max opcode for clamping operations.
static unsigned	getMinMaxOpcodeForCompareFold (SDValue Operand1, SDValue Operand2, bool SetCCNoNaNs, ISD::CondCode CC, unsigned OrAndOpcode, SelectionDAG &DAG, bool isFMAXNUMFMINNUM_IEEE, bool isFMAXNUMFMINNUM, bool isFMAXIMUMNUMFMINIMUMNUM, bool isPSEUDOFMAXFMIN)
static SDValue	foldAndOrOfSETCC (SDNode *LogicOp, SelectionDAG &DAG)
static SDValue	combineSelectAsExtAnd (SDValue Cond, SDValue T, SDValue F, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	combineShiftAnd1ToBitTest (SDNode *And, SelectionDAG &DAG)
	Try to replace shift/logic that tests if a bit is clear with mask + setcc.
static SDValue	foldAndToUsubsat (SDNode *N, SelectionDAG &DAG, const SDLoc &DL)
	For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it.
static SDValue	foldLogicOfShifts (SDNode *N, SDValue LogicOp, SDValue ShiftOp, SelectionDAG &DAG)
	Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values.
static SDValue	foldLogicTreeOfShifts (SDNode *N, SDValue LeftHand, SDValue RightHand, SelectionDAG &DAG)
	Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount.
static SDValue	foldMaskedMerge (SDNode *Node, SelectionDAG &DAG, const TargetLowering &TLI, const SDLoc &DL)
	Fold "masked merge" expressions like (m & x) \| (~m & y) and its DeMorgan variant (~m \| x) & (m \| y) into the equivalent ((x ^ y) & m) ^ y) pattern.
static bool	isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode * > Parts)
	Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.
static bool	isBSwapHWordPair (SDValue N, MutableArrayRef< SDNode * > Parts)
static SDValue	matchBSwapHWordOrAndAnd (const TargetLowering &TLI, SelectionDAG &DAG, SDNode *N, SDValue N0, SDValue N1, EVT VT)
static SDValue	visitORCommutative (SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N)
	OR combines for which the commuted variant will be tried as well.
static SDValue	stripConstantMask (const SelectionDAG &DAG, SDValue Op, SDValue &Mask)
static bool	matchRotateHalf (const SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask)
	Match "(X shl/srl V1) & V2" where V2 may not be present.
static SDValue	extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL)
	Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.
static bool	matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG, bool IsRotate, bool FromAdd)
static std::optional< SDByteProvider >	calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, std::optional< uint64_t > VectorIndex, unsigned StartingIndex=0, MutableArrayRef< uint8_t > ByteMask={})
static unsigned	littleEndianByteAt (unsigned BW, unsigned i)
static unsigned	bigEndianByteAt (unsigned BW, unsigned i)
static std::optional< bool >	isBigEndian (ArrayRef< int64_t > ByteOffsets, int64_t FirstOffset)
static SDValue	stripTruncAndExt (SDValue Value)
static SDValue	combineShiftOfShiftedLogic (SDNode *Shift, SelectionDAG &DAG)
	If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.
static SDValue	combineShiftToMULH (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	foldBitOrderCrossLogicOp (SDNode *N, SelectionDAG &DAG)
static bool	isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const SDNodeFlags SelectFlags, const SDNodeFlags CmpFlags, const TargetLowering &TLI)
static SDValue	combineMinNumMaxNumImpl (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG)
static SDValue	foldSelectOfConstantsUsingSra (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
	If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.
static bool	shouldConvertSelectOfConstantsToMath (const SDValue &Cond, EVT VT, const TargetLowering &TLI)
static SDValue	foldBoolSelectToLogic (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	foldVSelectToSignBitSplatMask (SDNode *N, SelectionDAG &DAG)
static std::tuple< unsigned, SDValue, SDValue >	combineSelectCCToPseudoMinMax (SelectionDAG &DAG, const SDLoc &DL, ISD::CondCode CC, SDValue Op0, SDValue Op1, SDValue LHS, SDValue RHS, SDNodeFlags Flags, bool IsStrict)
static SDValue	combineSelectToPseudoMinMax (SelectionDAG &DAG, SDNode *N)
static SDValue	foldSelectOfSelectCmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue TrueV, SDValue FalseV, const SDLoc &DL, EVT VT, SelectionDAG &DAG, SDNodeFlags Flags)
	Fold: select_cc (select C, TV, FV), CmpC, TrueV, FalseV, seteq -> select C, TrueV, FalseV select_cc (select C, TV, FV), CmpC, TrueV, FalseV, setne -> select C, FalseV, TrueV and the same with CmpC on the LHS of the comparison.
static SDValue	foldSelectCCOfSelect (SDNode *N, SelectionDAG &DAG)
static SDValue	ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG)
bool	refineUniformBase (SDValue &BasePtr, SDValue &Index, bool IndexIsScaled, SelectionDAG &DAG, const SDLoc &DL)
bool	refineIndexType (SDValue &Index, ISD::MemIndexType &IndexType, EVT DataVT, SelectionDAG &DAG)
static uint64_t	calculateConstantLowMaskLanes (SDValue Mask)
	Check if Mask defines a known constant set of enabled lanes, where only the first N lanes are enabled.
static SDValue	combineVSelectWithAllOnesOrZeros (SDValue Cond, SDValue TVal, SDValue FVal, const TargetLowering &TLI, SelectionDAG &DAG, const SDLoc &DL)
static bool	isCompatibleLoad (SDValue N, unsigned ExtOpcode)
	Check if N satisfies: N is used once.
static SDValue	tryToFoldExtendSelectLoad (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, const SDLoc &DL, CombineLevel Level)
	Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
static SDValue	tryToFoldExtendOfConstant (SDNode *N, const SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes)
	Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.
static bool	ExtendUsesToFormExtLoad (EVT VT, SDNode N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode > &ExtendNodes, const TargetLowering &TLI)
static SDValue	tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType)
static SDValue	tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc, bool NonNegZExt=false)
static SDValue	tryToFoldExtOfMaskedLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc)
static SDValue	tryToFoldExtOfAtomicLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDValue N0, ISD::LoadExtType ExtLoadType)
static SDValue	foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations)
static SDValue	widenCtPop (SDNode *Extend, SelectionDAG &DAG, const SDLoc &DL)
	Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type.
static SDValue	widenAbs (SDNode *Extend, SelectionDAG &DAG)
static SDValue	propagateUnaryUndef (SelectionDAG &DAG, SDValue N0, EVT VT)
	For a unary operation, propagate poison or undef from the operand `N0` to the result type `VT`.
static SDValue	foldExtendVectorInregToExtendOfSubvector (SDNode *N, const SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalOperations)
static SDValue	detectUSatUPattern (SDValue In, EVT VT)
	Detect patterns of truncation with unsigned saturation:
static SDValue	detectSSatSPattern (SDValue In, EVT VT)
	Detect patterns of truncation with signed saturation: (truncate (smin (smax (x, signed_min_of_dest_type), signed_max_of_dest_type)) to dest_type) or: (truncate (smax (smin (x, signed_max_of_dest_type), signed_min_of_dest_type)) to dest_type).
static SDValue	detectSSatUPattern (SDValue In, EVT VT, SelectionDAG &DAG, const SDLoc &DL)
	Detect patterns of truncation with unsigned saturation:
static SDValue	foldToSaturated (SDNode *N, EVT &VT, SDValue &Src, EVT &SrcVT, SDLoc &DL, const TargetLowering &TLI, SelectionDAG &DAG)
static SDNode *	getBuildPairElt (SDNode *N, unsigned i)
static unsigned	getPPCf128HiElementSelector (const SelectionDAG &DAG)
static bool	isContractableFMUL (SDValue N)
static bool	CanCombineFCOPYSIGN_EXTEND_ROUND (EVT XTy, EVT YTy)
	copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively.
static bool	CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N)
static SDValue	foldFPToIntToFP (SDNode *N, const SDLoc &DL, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	FoldIntToFPToInt (SDNode *N, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	eliminateFPCastPair (SDNode *N)
static bool	getCombineLoadStoreParts (SDNode *N, unsigned Inc, unsigned Dec, bool &IsLoad, bool &IsMasked, SDValue &Ptr, const TargetLowering &TLI)
static bool	shouldCombineToPostInc (SDNode N, SDValue Ptr, SDNode PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)
static SDNode *	getPostIndexedLoadStoreOp (SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI)
static ElementCount	numVectorEltsOrZero (EVT T)
static bool	areUsedBitsDense (const APInt &UsedBits)
	Check that all bits set in `UsedBits` form a dense region, i.e., `UsedBits` looks like 0..0 1..1 0..0.
static bool	areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second)
	Check whether or not `First` and `Second` are next to each other in memory.
static void	adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost)
	Adjust the `GlobalLSCost` according to the target paring capabilities and the layout of the slices.
static bool	isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize, const SelectionDAGOptions &Opts)
	Check the profitability of all involved LoadedSlice.
static std::pair< unsigned, unsigned >	CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain)
	Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.
static SDValue	ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode St, DAGCombiner DC)
	Check to see if IVal is something that provides a value as specified by MaskInfo.
static SDValue	foldToMaskedStore (StoreSDNode *Store, SelectionDAG &DAG, const SDLoc &Dl)
static bool	mergeEltWithShuffle (SDValue &X, SDValue &Y, ArrayRef< int > Mask, SmallVectorImpl< int > &NewMask, SDValue Elt, unsigned InsIndex)
static SDValue	scalarizeExtractedBinOp (SDNode *ExtElt, SelectionDAG &DAG, const SDLoc &DL, bool LegalTypes)
	Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.
static SDValue	reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG)
template<typename R, typename T>
static auto	getFirstIndexOf (R &&Range, const T &Val)
static SDValue	combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG)
static SDValue	combineConcatVectorOfConcatVectors (SDNode *N, SelectionDAG &DAG)
static SDValue	combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG)
static SDValue	combineConcatVectorOfCasts (SDNode *N, SelectionDAG &DAG)
static SDValue	combineConcatVectorOfShuffleAndItsOperands (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations)
static SDValue	combineConcatVectorOfShuffles (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
static SDValue	combineConcatVectorOfSplats (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations)
static SDValue	getSubVectorSrc (SDValue V, unsigned Index, EVT SubVT)
static SDValue	narrowInsertExtractVectorBinOp (EVT SubVT, SDValue BinOp, unsigned Index, const SDLoc &DL, SelectionDAG &DAG, bool LegalOperations)
static SDValue	narrowExtractedVectorBinOp (EVT VT, SDValue Src, unsigned Index, const SDLoc &DL, SelectionDAG &DAG, bool LegalOperations)
	If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.
static SDValue	narrowExtractedVectorLoad (EVT VT, SDValue Src, unsigned Index, const SDLoc &DL, SelectionDAG &DAG)
	If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector)
static SDValue	foldExtractSubvectorFromShuffleVector (EVT NarrowVT, SDValue Src, unsigned Index, const SDLoc &DL, SelectionDAG &DAG, bool LegalOperations)
	Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?
static SDValue	foldShuffleOfConcatUndefs (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
	Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.
static SDValue	partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG)
static SDValue	combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI)
static std::optional< EVT >	canCombineShuffleToExtendVectorInreg (unsigned Opcode, EVT VT, std::function< bool(unsigned)> Match, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations)
static SDValue	combineShuffleToAnyExtendVectorInreg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
static SDValue	combineShuffleToZeroExtendVectorInReg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
static SDValue	combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG)
static SDValue	combineShuffleOfSplatVal (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG)
static SDValue	combineShuffleOfBitcast (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations)
static SDValue	formSplatFromShuffles (ShuffleVectorSDNode *OuterShuf, SelectionDAG &DAG)
	Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X.
static int	getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask)
	If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.
static SDValue	simplifyShuffleOfShuffle (ShuffleVectorSDNode *Shuf)
	If we have a unary shuffle of a shuffle, see if it can be folded away completely.
static SDValue	scalarizeBinOpOfSplats (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, bool LegalTypes)
	If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.
static SDValue	matchMergedBFX (SDValue Root, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue	takeInexpensiveLog2 (SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned Depth, bool AssumeNonZero)

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

#define BEGIN_REGISTER_VP_SDNODE	(		SDOPC,
			... )

Value:

case ISD::SDOPC:

◆ DEBUG_TYPE

#define DEBUG_TYPE "dagcombine"

Definition at line 89 of file DAGCombiner.cpp.

Typedef Documentation

◆ SDByteProvider

using SDByteProvider = ByteProvider<SDNode *>

Recursively traverses the expression calculating the origin of the requested byte of the given value.

Returns std::nullopt if the provider can't be calculated.

For all the values except the root of the expression, we verify that the value has exactly one use and if not then return std::nullopt. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression. However, there is a special case when dealing with vector loads – we allow more than one use if the load is a vector type. Since the values that contribute to the byte ultimately come from the ExtractVectorElements of the Load, we don't care if the Load has uses other than ExtractVectorElements, because those operations are independent from the pattern to be combined. For vector loads, we simply care that the ByteProviders are adjacent positions of the same vector, and their index matches the byte that is being provided. This is captured by the VectorIndex algorithm. VectorIndex is the index used in an ExtractVectorElement, and StartingIndex is the byte position we are trying to provide for the LoadCombine. If these do not match, then we can not combine the vector loads. Index uses the byte position we are trying to provide for and is matched against the shl and load size. The Index algorithm ensures the requested byte is provided for by the pattern, and the pattern does not over provide bytes.

*ExtractVectorElement

Definition at line 9804 of file DAGCombiner.cpp.

Function Documentation

◆ adjustCostForPairing()

void adjustCostForPairing	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		LoadedSlice::Cost &	GlobalLSCost )

static

Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.

Precondition: GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices.

Definition at line 22811 of file DAGCombiner.cpp.

References areSlicesNextToEachOther(), assert(), llvm::First, LHS, RHS, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::sort(), and TLI.

Referenced by isSlicingProfitable().

◆ areBitwiseNotOfEachother()

bool areBitwiseNotOfEachother	(	SDValue	Op0,
		SDValue	Op1 )

static

Definition at line 2912 of file DAGCombiner.cpp.

References llvm::SDValue::getOperand(), and llvm::isBitwiseNot().

◆ areBothOperandsNotNan()

bool areBothOperandsNotNan	(	SDValue	Operand1,
		SDValue	Operand2,
		SelectionDAG &	DAG )

static

Definition at line 6982 of file DAGCombiner.cpp.

References llvm::SelectionDAG::isKnownNeverNaN().

Referenced by getMinMaxOpcodeForClamp(), and getMinMaxOpcodeForCompareFold().

◆ areBothOperandsNotSNan()

bool areBothOperandsNotSNan	(	SDValue	Operand1,
		SDValue	Operand2,
		SelectionDAG &	DAG )

static

Definition at line 6977 of file DAGCombiner.cpp.

References llvm::SelectionDAG::isKnownNeverSNaN().

Referenced by getMinMaxOpcodeForCompareFold().

◆ areSlicesNextToEachOther()

bool areSlicesNextToEachOther	(	const LoadedSlice &	First,
		const LoadedSlice &	Second )

static

Check whether or not First and Second are next to each other in memory.

This means that there is no hole between the bits loaded by First and the bits loaded by Second.

Definition at line 22796 of file DAGCombiner.cpp.

References areUsedBitsDense(), assert(), and llvm::First.

Referenced by adjustCostForPairing().

◆ areUsedBitsDense()

bool areUsedBitsDense ( const APInt & UsedBits )

static

Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.

Definition at line 22779 of file DAGCombiner.cpp.

References llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnes(), llvm::APInt::lshr(), and llvm::APInt::trunc().

Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().

◆ bigEndianByteAt()

unsigned bigEndianByteAt	(	unsigned	BW,
		unsigned	i )

static

Definition at line 9979 of file DAGCombiner.cpp.

◆ calculateByteProvider()

std::optional< SDByteProvider > calculateByteProvider	(	SDValue	Op,
		unsigned	Index,
		unsigned	Depth,
		std::optional< uint64_t >	VectorIndex,
		unsigned	StartingIndex = 0,
		MutableArrayRef< uint8_t >	ByteMask = {} )

static

Definition at line 9807 of file DAGCombiner.cpp.

References llvm::Depth.

Referenced by calculateByteProvider(), handleMulOperand(), and matchPERM().

◆ calculateConstantLowMaskLanes()

uint64_t calculateConstantLowMaskLanes ( SDValue Mask )

static

Check if Mask defines a known constant set of enabled lanes, where only the first N lanes are enabled.

N is returned if so.

Definition at line 13992 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::GET_ACTIVE_LANE_MASK, llvm::isa(), llvm::isNullConstant(), llvm::isOneConstant(), and uint64_t.

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [1/2]

bool CanCombineFCOPYSIGN_EXTEND_ROUND	(	EVT	XTy,
		EVT	YTy )

inlinestatic

copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively.

Definition at line 20542 of file DAGCombiner.cpp.

References llvm::EVT::isVector().

Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [2/2]

bool CanCombineFCOPYSIGN_EXTEND_ROUND ( SDNode * N )

inlinestatic

Definition at line 20558 of file DAGCombiner.cpp.

References CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), and N.

◆ canCombineShuffleToExtendVectorInreg()

std::optional< EVT > canCombineShuffleToExtendVectorInreg	(	unsigned	Opcode,
		EVT	VT,
		std::function< bool(unsigned)>	Match,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalTypes,
		bool	LegalOperations )

static

Definition at line 29196 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), and TLI.

Referenced by combineShuffleToAnyExtendVectorInreg(), and combineShuffleToZeroExtendVectorInReg().

◆ canFoldInAddressingMode()

bool canFoldInAddressingMode	(	SDNode *	N,
		SDNode *	Use,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.

Definition at line 2474 of file DAGCombiner.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::dyn_cast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, N, llvm::Offset, llvm::TargetLoweringBase::AddrMode::Scale, llvm::ISD::SUB, and TLI.

◆ canSplitIdx()

bool canSplitIdx	(	LoadSDNode *	LD,
		const SelectionDAGOptions &	Opts )

static

Definition at line 1061 of file DAGCombiner.cpp.

References llvm::cast(), and llvm::ISD::TargetConstant.

◆ CheckForMaskedLoad()

std::pair< unsigned, unsigned > CheckForMaskedLoad	(	SDValue	V,
		SDValue	Ptr,
		SDValue	Chain )

static

Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.

If so, return the byte size being masked out and the shift amount.

Definition at line 23021 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::cast(), llvm::countl_zero(), llvm::countr_one(), llvm::countr_zero(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::isa(), llvm::ISD::isNormalLoad(), llvm::ISD::TokenFactor, uint64_t, and V.

◆ combineCarryDiamond()

SDValue combineCarryDiamond	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		SDValue	N0,
		SDValue	N1,
		SDNode *	N )

static

◆ combineConcatVectorOfCasts()

SDValue combineConcatVectorOfCasts	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 27745 of file DAGCombiner.cpp.

References llvm::EVT::changeVectorElementCount(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::isVector(), llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::SINT_TO_FP, TLI, and llvm::ISD::UINT_TO_FP.

◆ combineConcatVectorOfConcatVectors()

SDValue combineConcatVectorOfConcatVectors	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 27631 of file DAGCombiner.cpp.

References llvm::SmallVectorImpl< T >::append(), assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isTypeLegal(), N, and SDValue().

◆ combineConcatVectorOfExtracts()

SDValue combineConcatVectorOfExtracts	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 27671 of file DAGCombiner.cpp.

References llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), N, llvm::peekThroughBitcasts(), SDValue(), and TLI.

◆ combineConcatVectorOfScalars()

SDValue combineConcatVectorOfScalars	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 27574 of file DAGCombiner.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), N, SDValue(), and TLI.

◆ combineConcatVectorOfShuffleAndItsOperands()

SDValue combineConcatVectorOfShuffleAndItsOperands	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalTypes,
		bool	LegalOperations )

static

◆ combineConcatVectorOfShuffles()

SDValue combineConcatVectorOfShuffles	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations )

static

Definition at line 27911 of file DAGCombiner.cpp.

◆ combineConcatVectorOfSplats()

SDValue combineConcatVectorOfSplats	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalTypes,
		bool	LegalOperations )

static

Definition at line 27992 of file DAGCombiner.cpp.

References llvm::all_equal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), N, SDValue(), llvm::ISD::SPLAT_VECTOR, and TLI.

◆ combineMinNumMaxNumImpl()

SDValue combineMinNumMaxNumImpl	(	const SDLoc &	DL,
		EVT	VT,
		SDValue	LHS,
		SDValue	RHS,
		SDValue	True,
		SDValue	False,
		ISD::CondCode	CC,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG )

static

◆ combineOrOfSetCCToUSUBOCarry()

SDValue combineOrOfSetCCToUSUBOCarry	(	SDNode *	N,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

◆ combineSelectAsExtAnd()

SDValue combineSelectAsExtAnd	(	SDValue	Cond,
		SDValue	T,
		SDValue	F,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Definition at line 7277 of file DAGCombiner.cpp.

References llvm::ISD::AND, Cond, DL, F, llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isNullConstant(), llvm::isOneConstant(), SDValue(), T, TLI, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

◆ combineSelectCCToPseudoMinMax()

std::tuple< unsigned, SDValue, SDValue > combineSelectCCToPseudoMinMax	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		ISD::CondCode	CC,
		SDValue	Op0,
		SDValue	Op1,
		SDValue	LHS,
		SDValue	RHS,
		SDNodeFlags	Flags,
		bool	IsStrict )

static

◆ combineSelectToPseudoMinMax()

SDValue combineSelectToPseudoMinMax	(	SelectionDAG &	DAG,
		SDNode *	N )

static

Definition at line 13497 of file DAGCombiner.cpp.

References CC, combineSelectCCToPseudoMinMax(), Cond, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), LHS, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), RHS, SDValue(), llvm::ISD::SETCC, and llvm::ISD::STRICT_FSETCCS.

◆ combineShiftAnd1ToBitTest()

SDValue combineShiftAnd1ToBitTest	(	SDNode *	And,
		SelectionDAG &	DAG )

static

Try to replace shift/logic that tests if a bit is clear with mask + setcc.

For a target with a bit test, this is expected to become test + set and save at least 1 instruction.

Definition at line 7711 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::BitWidth, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::isBitwiseNot(), llvm::isOneConstant(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SRL, TLI, llvm::ISD::TRUNCATE, X, and Zero.

◆ combineShiftOfShiftedLogic()

SDValue combineShiftOfShiftedLogic	(	SDNode *	Shift,
		SelectionDAG &	DAG )

static

If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.

This is a throughput improvement.

Definition at line 10869 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), C1, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::ISD::OR, SDValue(), llvm::APInt::uadd_ov(), llvm::APInt::uge(), V, X, llvm::ISD::XOR, and Y.

◆ combineShiftToMULH()

SDValue combineShiftToMULH	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Definition at line 11436 of file DAGCombiner.cpp.

References llvm::any_of(), assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeMaxSignificantBits(), llvm::KnownBits::countMaxActiveBits(), DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRL, std::swap(), TLI, llvm::ISD::TRUNCATE, llvm::ISD::UMUL_LOHI, llvm::SDNode::users(), and llvm::ISD::ZERO_EXTEND.

◆ combineShuffleOfBitcast()

SDValue combineShuffleOfBitcast	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations )

static

◆ combineShuffleOfScalars()

SDValue combineShuffleOfScalars	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Definition at line 29113 of file DAGCombiner.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), llvm::SmallSet< T, N, C >::insert(), isAnyConstantBuildVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isInteger(), llvm::isIntOrFPConstant(), llvm::SDValue::isUndef(), llvm::ISD::SCALAR_TO_VECTOR, SDValue(), and TLI.

◆ combineShuffleOfSplatVal()

SDValue combineShuffleOfSplatVal	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG )

static

Definition at line 29459 of file DAGCombiner.cpp.

References assert(), llvm::dyn_cast(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::APInt::setBit(), llvm::ArrayRef< T >::size(), and llvm::Splat.

◆ combineShuffleToAnyExtendVectorInreg()

SDValue combineShuffleToAnyExtendVectorInreg	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations )

static

Definition at line 29234 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND_VECTOR_INREG, canCombineShuffleToExtendVectorInreg(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), SDValue(), and TLI.

◆ combineShuffleToZeroExtendVectorInReg()

SDValue combineShuffleToZeroExtendVectorInReg	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	LegalOperations )

static

Definition at line 29272 of file DAGCombiner.cpp.

References llvm::all_of(), assert(), canCombineShuffleToExtendVectorInreg(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::SelectionDAG::computeVectorKnownZeroElements(), llvm::ArrayRef< T >::drop_front(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::getShuffleMaskWithWidestElts(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZero(), I, llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::SDNode::ops(), SDValue(), llvm::ArrayRef< T >::size(), llvm::SmallVectorTemplateCommon< T, typename >::size(), TLI, llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::zip().

◆ combineTruncationShuffle()

SDValue combineTruncationShuffle	(	ShuffleVectorSDNode *	SVN,
		SelectionDAG &	DAG )

static

Definition at line 29398 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::ISD::isExtVecInRegOpcode(), llvm::EVT::isInteger(), llvm::peekThroughBitcasts(), and SDValue().

◆ combineUADDO_CARRYDiamond()

SDValue combineUADDO_CARRYDiamond	(	DAGCombiner &	Combiner,
		SelectionDAG &	DAG,
		SDValue	X,
		SDValue	Carry0,
		SDValue	Carry1,
		SDNode *	N )

static

If we are facing some sort of diamond carry propagation pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)

The end result is usually an increase in operation required, but because the carry is now linearized, other transforms can kick in and optimize the DAG.

Patterns typically look something like (uaddo A, B) / \ Carry Sum | \ | (uaddo_carry *, 0, Z) | / \ Carry | / (uaddo_carry X, *, *)

But numerous variation exist. Our goal is to identify A, B, X and Z and produce a combine with a single path for carry propagation.

First look for a suitable Z. It will present itself in the form of (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true

    (uaddo A, B)
         |
        Sum
         |

(uaddo_carry *, 0, Z)

(uaddo_carry A, 0, Z) | Sum | (uaddo *, B)

Definition at line 3776 of file DAGCombiner.cpp.

References A(), B(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::isNullConstant(), llvm::isOneConstant(), N, SDValue(), llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, and X.

◆ combineVSelectWithAllOnesOrZeros()

SDValue combineVSelectWithAllOnesOrZeros	(	SDValue	Cond,
		SDValue	TVal,
		SDValue	FVal,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Definition at line 14679 of file DAGCombiner.cpp.

◆ ConvertSelectToConcatVector()

SDValue ConvertSelectToConcatVector	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 13807 of file DAGCombiner.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::CONCAT_VECTORS, Cond, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::isZero(), LHS, N, RHS, and SDValue().

◆ DEBUG_COUNTER()

DEBUG_COUNTER	(	DAGCombineCounter	,
		"dagcombine"	,
		"Controls whether a DAG combine is performed for a node"	)

◆ detectSSatSPattern()

SDValue detectSSatSPattern	(	SDValue	In,
		EVT	VT )

static

Detect patterns of truncation with signed saturation: (truncate (smin (smax (x, signed_min_of_dest_type), signed_max_of_dest_type)) to dest_type) or: (truncate (smax (smin (x, signed_max_of_dest_type), signed_min_of_dest_type)) to dest_type).

Return the source value to be truncated or SDValue() if the pattern was not matched.

Definition at line 17799 of file DAGCombiner.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::PatternMatch::m_SMax(), llvm::PatternMatch::m_SMin(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::APInt::sext().

Referenced by foldToSaturated().

◆ detectSSatUPattern()

SDValue detectSSatUPattern	(	SDValue	In,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Detect patterns of truncation with unsigned saturation:

Definition at line 17821 of file DAGCombiner.cpp.

References assert(), DL, llvm::APInt::getMaxValue(), llvm::EVT::getScalarSizeInBits(), llvm::PatternMatch::m_SMax(), llvm::PatternMatch::m_SMin(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_UMin(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::APInt::zext().

Referenced by foldToSaturated().

◆ detectUSatUPattern()

SDValue detectUSatUPattern	(	SDValue	In,
		EVT	VT )

static

Detect patterns of truncation with unsigned saturation:

(truncate (umin (x, unsigned_max_of_dest_type)) to dest_type). Return the source value x to be truncated or SDValue() if the pattern was not matched.

Definition at line 17776 of file DAGCombiner.cpp.

References assert(), llvm::APInt::getMaxValue(), llvm::EVT::getScalarSizeInBits(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_UMin(), llvm::PatternMatch::m_Value(), llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::APInt::zext().

Referenced by foldToSaturated().

◆ eliminateFPCastPair()

SDValue eliminateFPCastPair ( SDNode * N )

static

Definition at line 21140 of file DAGCombiner.cpp.

References llvm::ISD::BF16_TO_FP, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_BF16, llvm::ISD::FP_TO_FP16, llvm::SDNode::getFlags(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNodeFlags::hasAllowContract(), llvm::SDNodeFlags::hasNoInfs(), llvm::SDNodeFlags::hasNoNaNs(), llvm_unreachable, N, and SDValue().

◆ ExtendUsesToFormExtLoad()

bool ExtendUsesToFormExtLoad	(	EVT	VT,
		SDNode *	N,
		SDValue	N0,
		unsigned	ExtOpc,
		SmallVectorImpl< SDNode * > &	ExtendNodes,
		const TargetLowering &	TLI )

static

◆ extractBooleanFlip()

SDValue extractBooleanFlip	(	SDValue	V,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		bool	Force )

static

Flips a boolean if it is cheaper to compute.

If the Force parameters is set, then the flip also occurs if computing the inverse is the same cost. This function returns an empty SDValue in case it cannot flip the boolean without increasing the cost of the computation. If you want to flip a boolean no matter what, use DAG.getLogicalNOT.

Definition at line 3588 of file DAGCombiner.cpp.

References llvm::Force, llvm::SelectionDAG::getLogicalNOT(), llvm::isa(), llvm::SelectionDAG::isBoolConstant(), llvm::isConstOrConstSplat(), SDValue(), TLI, V, and llvm::ISD::XOR.

◆ extractShiftForRotate()

SDValue extractShiftForRotate	(	SelectionDAG &	DAG,
		SDValue	OppShift,
		SDValue	ExtractFrom,
		SDValue &	Mask,
		const SDLoc &	DL )

static

Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.

This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.

Returns: An empty SDValue if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom based on the following patterns:

(or (add v v) (shrl v bitwidth-1)): expands (add v v) -> (shl v 1)

(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)

(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)

(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)

(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)

Such that in all cases, c3+c2==bitwidth(op v c1).

Definition at line 9202 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::DELETED_NODE, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::ISD::MUL, SDValue(), llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().

◆ foldAddSubBoolOfMaskedVal()

SDValue foldAddSubBoolOfMaskedVal	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

◆ foldAddSubMasked1()

SDValue foldAddSubMasked1	(	bool	IsAdd,
		SDValue	N0,
		SDValue	N1,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.

If so, invert the opcode and bypass the mask operation.

Definition at line 3439 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isOneOrOneSplat(), SDValue(), llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ foldAddSubOfSignBit()

SDValue foldAddSubOfSignBit	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.

Definition at line 2871 of file DAGCombiner.cpp.

References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isBitwiseNot(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isConstOrConstSplat(), N, SDValue(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

◆ foldAndOrOfSETCC()

SDValue foldAndOrOfSETCC	(	SDNode *	LogicOp,
		SelectionDAG &	DAG )

static

Definition at line 7062 of file DAGCombiner.cpp.

◆ foldAndToUsubsat()

SDValue foldAndToUsubsat	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it.

Definition at line 7785 of file DAGCombiner.cpp.

References llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::APInt::getSignMask(), llvm::PatternMatch::m_Add(), llvm::PatternMatch::m_And(), llvm::PatternMatch::m_Deferred(), llvm::SDPatternMatch::m_OneUse(), llvm::PatternMatch::m_SpecificInt(), llvm::SDPatternMatch::m_Sra(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::USUBSAT, and X.

◆ foldBitOrderCrossLogicOp()

SDValue foldBitOrderCrossLogicOp	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 11550 of file DAGCombiner.cpp.

References llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::PatternMatch::m_BitwiseLogic(), llvm::SDPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_UnaryOp(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), X, and Y.

Referenced by llvm::InstCombinerImpl::visitCallInst().

◆ foldBoolSelectToLogic()

SDValue foldBoolSelectToLogic	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Definition at line 13220 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), Cond, DL, F, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), N, llvm::ISD::OR, SDValue(), llvm::ISD::SELECT, T, llvm::ISD::VSELECT, and llvm::ISD::XOR.

◆ foldExtendedSignBitTest()

SDValue foldExtendedSignBitTest	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

◆ foldExtendVectorInregToExtendOfSubvector()

SDValue foldExtendVectorInregToExtendOfSubvector	(	SDNode *	N,
		const SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

Definition at line 17699 of file DAGCombiner.cpp.

References assert(), llvm::EVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getOpcode_EXTEND(), llvm::ISD::isExtVecInRegOpcode(), N, SDValue(), and TLI.

◆ foldExtractSubvectorFromShuffleVector()

SDValue foldExtractSubvectorFromShuffleVector	(	EVT	NarrowVT,
		SDValue	Src,
		unsigned	Index,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?

, ?), EXTRACT_SUBVECTOR(Op?, ?), Mask')) iff it is legal and profitable to do so. Notably, the trimmed mask (containing only the elements that are extracted) must reference at most two subvectors.

Definition at line 28568 of file DAGCombiner.cpp.

References llvm::any_of(), assert(), llvm::TargetLoweringBase::Cheap, DL, llvm::dyn_cast(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::ISD::EXTRACT_SUBVECTOR, getFirstIndexOf(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getPOISON(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::isFixedLengthVector(), llvm::ShuffleVectorInst::isIdentityMask(), llvm::SmallVectorImpl< T >::reserve(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), TLI, and llvm::ISD::VECTOR_SHUFFLE.

◆ foldFPToIntToFP()

SDValue foldFPToIntToFP	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Definition at line 20693 of file DAGCombiner.cpp.

References assert(), llvm::SelectionDAG::canIgnoreSignBitOfZeroResult(), llvm::APFloat::convertFromAPInt(), llvm::APFloat::convertToInteger(), llvm::ISD::DELETED_NODE, DL, llvm::dyn_cast(), llvm::ISD::FABS, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::EVT::getFltSemantics(), getMinMaxOpcodeForClamp(), llvm::SelectionDAG::getNode(), llvm::ISD::isConstantSplatVector(), N, llvm::APFloatBase::opOK, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::reverse(), RHS, llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardZero, SDValue(), llvm::ISD::SINT_TO_FP, llvm::ISD::SMAX, llvm::ISD::SMIN, TLI, llvm::ISD::UINT_TO_FP, llvm::ISD::UMAX, and llvm::ISD::UMIN.

◆ FoldIntToFPToInt()

SDValue FoldIntToFPToInt	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

Definition at line 20946 of file DAGCombiner.cpp.

References DL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getBitcast(), llvm::EVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), N, SDValue(), llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

◆ foldLogicOfShifts()

SDValue foldLogicOfShifts	(	SDNode *	N,
		SDValue	LogicOp,
		SDValue	ShiftOp,
		SelectionDAG &	DAG )

static

Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values.

For example: ((X0 << Y) | Z) | (X1 << Y) --> ((X0 | X1) << Y) | Z

Definition at line 7810 of file DAGCombiner.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and Y.

Referenced by foldLogicTreeOfShifts(), and visitORCommutative().

◆ foldLogicTreeOfShifts()

SDValue foldLogicTreeOfShifts	(	SDNode *	N,
		SDValue	LeftHand,
		SDValue	RightHand,
		SelectionDAG &	DAG )

static

Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount.

For example: LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) --> --> LOGIC (SH (LOGIC X0, X1), Y), (LOGIC Z, W)

Definition at line 7858 of file DAGCombiner.cpp.

References assert(), DL, foldLogicOfShifts(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), N, and SDValue().

◆ foldMaskedMerge()

SDValue foldMaskedMerge	(	SDNode *	Node,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		const SDLoc &	DL )

static

Fold "masked merge" expressions like (m & x) | (~m & y) and its DeMorgan variant (~m | x) & (m | y) into the equivalent ((x ^ y) & m) ^ y) pattern.

This is typically a better representation for targets without a fused "and-not" operation.

Definition at line 7893 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getNode(), llvm::PatternMatch::m_And(), llvm::PatternMatch::m_Deferred(), llvm::MIPatternMatch::m_Not(), llvm::SDPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::PatternMatch::m_Value(), llvm::ISD::OR, llvm::SDPatternMatch::sd_match(), SDValue(), TLI, X, llvm::ISD::XOR, llvm::Xor, and Y.

◆ foldRemainderIdiom()

SDValue foldRemainderIdiom	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Definition at line 4204 of file DAGCombiner.cpp.

References assert(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::isConstOrConstSplat(), llvm::APInt::isPowerOf2(), llvm::APInt::logBase2(), llvm::ISD::MUL, N, llvm::ISD::SDIVREM, SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, and llvm::ISD::UDIVREM.

◆ foldSelectCCOfSelect()

SDValue foldSelectCCOfSelect	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 13586 of file DAGCombiner.cpp.

References CC, foldSelectOfSelectCmp(), and N.

◆ foldSelectOfConstantsUsingSra()

SDValue foldSelectOfConstantsUsingSra	(	SDNode *	N,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.

Definition at line 13043 of file DAGCombiner.cpp.

References llvm::ISD::AND, C1, CC, Cond, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstantOrConstantVector(), llvm::isNullOrNullSplat(), N, llvm::ISD::OR, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SRA, and X.

◆ foldSelectOfSelectCmp()

SDValue foldSelectOfSelectCmp	(	SDValue	LHS,
		SDValue	RHS,
		ISD::CondCode	CC,
		SDValue	TrueV,
		SDValue	FalseV,
		const SDLoc &	DL,
		EVT	VT,
		SelectionDAG &	DAG,
		SDNodeFlags	Flags )

static

Fold: select_cc (select C, TV, FV), CmpC, TrueV, FalseV, seteq -> select C, TrueV, FalseV select_cc (select C, TV, FV), CmpC, TrueV, FalseV, setne -> select C, FalseV, TrueV and the same with CmpC on the LHS of the comparison.

TV and FV must be distinct integer constants. Also used for select (setcc ...).

Definition at line 13534 of file DAGCombiner.cpp.

References CC, Cond, DL, llvm::dyn_cast(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), LHS, RHS, SDValue(), llvm::ISD::SELECT, llvm::ISD::SETEQ, llvm::ISD::SETNE, and std::swap().

Referenced by foldSelectCCOfSelect().

◆ foldSelectWithIdentityConstant()

SDValue foldSelectWithIdentityConstant	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	ShouldCommuteOperands )

static

This inverts a canonicalization in IR that replaces a variable select arm with an identity constant.

Codegen improves if we re-use the variable operand rather than load a constant. This can also be converted into a masked vector operation if the target supports it.

Definition at line 2534 of file DAGCombiner.cpp.

References Cond, llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::isIdentityElement(), llvm::SelectionDAG::isSafeToSpeculativelyExecuteNode(), llvm::SDPatternMatch::m_OneUse(), llvm::PatternMatch::m_SelectLike(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), std::swap(), and TLI.

◆ foldShuffleOfConcatUndefs()

SDValue foldShuffleOfConcatUndefs	(	ShuffleVectorSDNode *	Shuf,
		SelectionDAG &	DAG )

static

Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.

Narrow vector ops may have better performance than wide ops, and this can unlock further narrowing of other vector ops. Targets can invert this transform later if it is not profitable.

Definition at line 28986 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::SDValue::isUndef(), SDValue(), TLI, X, and Y.

◆ foldSubCtlzNot()

SDValue foldSubCtlzNot	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ foldToMaskedStore()

SDValue foldToMaskedStore	(	StoreSDNode *	Store,
		SelectionDAG &	DAG,
		const SDLoc &	Dl )

static

◆ foldToSaturated()

SDValue foldToSaturated	(	SDNode *	N,
		EVT &	VT,
		SDValue &	Src,
		EVT &	SrcVT,
		SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG )

static

Definition at line 17846 of file DAGCombiner.cpp.

References detectSSatSPattern(), detectSSatUPattern(), detectUSatUPattern(), DL, llvm::SelectionDAG::getNode(), N, Opc, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, TLI, llvm::ISD::TRUNCATE_SSAT_S, llvm::ISD::TRUNCATE_SSAT_U, llvm::ISD::TRUNCATE_USAT_U, and llvm::ISD::UMIN.

◆ foldVSelectToSignBitSplatMask()

SDValue foldVSelectToSignBitSplatMask	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ formSplatFromShuffles()

SDValue formSplatFromShuffles	(	ShuffleVectorSDNode *	OuterShuf,
		SelectionDAG &	DAG )

static

Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X.

Definition at line 29607 of file DAGCombiner.cpp.

References llvm::all_of(), assert(), llvm::dyn_cast(), llvm::equal_to(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::getSplatIndex(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), SDValue(), and llvm::ArrayRef< T >::size().

◆ getAsCarry()

SDValue getAsCarry	(	const TargetLowering &	TLI,
		SDValue	V,
		bool	ForceCarryReconstruction = false )

static

Definition at line 3387 of file DAGCombiner.cpp.

References llvm::ISD::AND, llvm::isOneConstant(), llvm::Masked, SDValue(), TLI, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, V, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by combineCarryDiamond().

◆ getAsNonOpaqueConstant()

ConstantSDNode * getAsNonOpaqueConstant ( SDValue N )

static

If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.

Definition at line 2445 of file DAGCombiner.cpp.

References llvm::dyn_cast(), and N.

◆ getBuildPairElt()

SDNode * getBuildPairElt	(	SDNode *	N,
		unsigned	i )

static

Definition at line 18306 of file DAGCombiner.cpp.

References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::ISD::MERGE_VALUES, and N.

◆ getCombineLoadStoreParts()

bool getCombineLoadStoreParts	(	SDNode *	N,
		unsigned	Inc,
		unsigned	Dec,
		bool &	IsLoad,
		bool &	IsMasked,
		SDValue &	Ptr,
		const TargetLowering &	TLI )

static

Definition at line 21647 of file DAGCombiner.cpp.

References llvm::dyn_cast(), N, and TLI.

Referenced by getPostIndexedLoadStoreOp(), and shouldCombineToPostInc().

◆ getFirstIndexOf()

template<typename R, typename T>

auto getFirstIndexOf	(	R &&	Range,
		const T &	Val )

static

Definition at line 27006 of file DAGCombiner.cpp.

References llvm::find(), I, Range, and T.

Referenced by foldExtractSubvectorFromShuffleVector().

◆ getInputChainForNode()

SDValue getInputChainForNode ( SDNode * N )

static

Given a node, return its input chain if it has one, otherwise return a null sd operand.

Definition at line 2195 of file DAGCombiner.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, N, and SDValue().

◆ getMinMaxOpcodeForClamp()

unsigned getMinMaxOpcodeForClamp	(	bool	IsMin,
		SDValue	Operand1,
		SDValue	Operand2,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Returns an appropriate FP min/max opcode for clamping operations.

Definition at line 6988 of file DAGCombiner.cpp.

References areBothOperandsNotNan(), llvm::ISD::DELETED_NODE, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::SDValue::getValueType(), and TLI.

Referenced by foldFPToIntToFP().

◆ getMinMaxOpcodeForCompareFold()

unsigned getMinMaxOpcodeForCompareFold	(	SDValue	Operand1,
		SDValue	Operand2,
		bool	SetCCNoNaNs,
		ISD::CondCode	CC,
		unsigned	OrAndOpcode,
		SelectionDAG &	DAG,
		bool	isFMAXNUMFMINNUM_IEEE,
		bool	isFMAXNUMFMINNUM,
		bool	isFMAXIMUMNUMFMINIMUMNUM,
		bool	isPSEUDOFMAXFMIN )

static

◆ getPostIndexedLoadStoreOp()

SDNode * getPostIndexedLoadStoreOp	(	SDNode *	N,
		bool &	IsLoad,
		bool &	IsMasked,
		SDValue &	Ptr,
		SDValue &	BasePtr,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

Definition at line 21959 of file DAGCombiner.cpp.

References getCombineLoadStoreParts(), llvm::SelectionDAG::getHasPredecessorMaxSteps(), llvm::SDValue::getNode(), llvm::SDValue::getResNo(), llvm::SDNode::hasOneUse(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::SmallVectorTemplateBase< T, bool >::push_back(), shouldCombineToPostInc(), TLI, and llvm::SDNode::uses().

◆ getPPCf128HiElementSelector()

unsigned getPPCf128HiElementSelector ( const SelectionDAG & DAG )

static

Definition at line 18347 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getDataLayout(), and llvm::DataLayout::isBigEndian().

◆ getShuffleMaskIndexOfOneElementFromOp0IntoOp1()

int getShuffleMaskIndexOfOneElementFromOp0IntoOp1 ( ArrayRef< int > Mask )

static

If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.

Otherwise, return -1.

Definition at line 29660 of file DAGCombiner.cpp.

◆ getSubVectorSrc()

SDValue getSubVectorSrc	(	SDValue	V,
		unsigned	Index,
		EVT	SubVT )

static

Definition at line 28328 of file DAGCombiner.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::EVT::getVectorMinNumElements(), llvm::ISD::INSERT_SUBVECTOR, SDValue(), uint64_t, and V.

Referenced by narrowInsertExtractVectorBinOp().

◆ getTruncatedUSUBSAT()

SDValue getTruncatedUSUBSAT	(	EVT	DstVT,
		EVT	SrcVT,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Definition at line 4059 of file DAGCombiner.cpp.

References assert(), DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), RHS, SDValue(), llvm::ISD::TRUNCATE, llvm::ISD::UMIN, and llvm::ISD::USUBSAT.

◆ isAnyConstantBuildVector()

bool isAnyConstantBuildVector	(	SDValue	V,
		bool	NoOpaques = false )

static

Definition at line 1053 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::isConstantOrConstantVector(), and V.

Referenced by combineShuffleOfBitcast(), combineShuffleOfScalars(), and scalarizeExtractedBinOp().

◆ isBigEndian()

std::optional< bool > isBigEndian	(	ArrayRef< int64_t >	ByteOffsets,
		int64_t	FirstOffset )

static

Definition at line 9986 of file DAGCombiner.cpp.

References assert(), bigEndianByteAt(), littleEndianByteAt(), and llvm::ArrayRef< T >::size().

◆ isBSwapHWordElement()

bool isBSwapHWordElement	(	SDValue	N,
		MutableArrayRef< SDNode * >	Parts )

static

Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.

((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)

Definition at line 8534 of file DAGCombiner.cpp.

References llvm::ISD::AND, C(), llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), N, Opc, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by isBSwapHWordPair().

◆ isBSwapHWordPair()

bool isBSwapHWordPair	(	SDValue	N,
		MutableArrayRef< SDNode * >	Parts )

static

Definition at line 8619 of file DAGCombiner.cpp.

References llvm::ISD::BSWAP, C(), isBSwapHWordElement(), llvm::isConstOrConstSplat(), N, llvm::ISD::OR, and llvm::ISD::SRL.

◆ isCompatibleLoad()

bool isCompatibleLoad	(	SDValue	N,
		unsigned	ExtOpcode )

static

Check if N satisfies: N is used once.

N is a Load. The load is compatible with ExtOpcode. It means If load has explicit zero/sign extension, ExpOpcode must have the same extension. Otherwise returns true.

Definition at line 15294 of file DAGCombiner.cpp.

References llvm::cast(), llvm::ISD::EXTLOAD, llvm::isa(), llvm::Load, N, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

Referenced by tryToFoldExtendSelectLoad().

◆ isConstantOrConstantVector()

bool isConstantOrConstantVector	(	SDValue	N,
		bool	NoOpaques = false,
		bool	AllowTruncation = false )

static

Definition at line 1028 of file DAGCombiner.cpp.

References llvm::BitWidth, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), N, and llvm::ISD::SPLAT_VECTOR.

◆ isConstantSplatVectorMaskForType()

bool isConstantSplatVectorMaskForType	(	SDNode *	N,
		EVT	ScalarTy )

static

Definition at line 998 of file DAGCombiner.cpp.

References llvm::APInt::getLimitedValue(), llvm::EVT::getSimpleVT(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isSimple(), N, llvm::MVT::SimpleTy, and uint64_t.

Referenced by performSVEAndCombine().

◆ isContractableFMUL()

bool isContractableFMUL ( SDValue N )

static

Definition at line 18897 of file DAGCombiner.cpp.

References assert(), llvm::ISD::FMUL, and N.

◆ isDivisorPowerOfTwo()

bool isDivisorPowerOfTwo ( SDValue Divisor )

static

Definition at line 5362 of file DAGCombiner.cpp.

References C(), and llvm::ISD::matchUnaryPredicate().

◆ isDivRemLibcallAvailable()

bool isDivRemLibcallAvailable	(	SDNode *	Node,
		bool	isSigned,
		const SelectionDAG &	DAG )

static

Return true if divmod libcall is available.

Definition at line 5162 of file DAGCombiner.cpp.

References llvm::LibcallLoweringInfo::getLibcallImpl(), llvm::SelectionDAG::getLibcalls(), and isSigned().

◆ isLegalToCombineMinNumMaxNum()

bool isLegalToCombineMinNumMaxNum	(	SelectionDAG &	DAG,
		SDValue	LHS,
		SDValue	RHS,
		const SDNodeFlags	SelectFlags,
		const SDNodeFlags	CmpFlags,
		const TargetLowering &	TLI )

static

Definition at line 12882 of file DAGCombiner.cpp.

References llvm::SDNodeFlags::hasNoNaNs(), llvm::SDNodeFlags::hasNoSignedZeros(), llvm::EVT::isFloatingPoint(), llvm::SelectionDAG::isKnownNeverNaN(), LHS, RHS, and TLI.

◆ isSaturatingMinMax()

SDValue isSaturatingMinMax	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		unsigned &	BW,
		bool &	Unsigned,
		SelectionDAG &	DAG )

static

Definition at line 6262 of file DAGCombiner.cpp.

References C1, CC, llvm::APInt::exactLogBase2(), llvm::ISD::FP_TO_SINT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getContext(), llvm::Type::getFltSemantics(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::isNullOrNullSplat(), llvm::APInt::isPowerOf2(), llvm::EVT::isSimple(), llvm::peekThroughTruncates(), llvm::PowerOf2Ceil(), SDValue(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APFloatBase::semanticsIntSizeInBits(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::APInt::sext(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, llvm::Unsigned, and llvm::ISD::VSELECT.

Referenced by PerformMinMaxFpToSatCombine().

◆ isSlicingProfitable()

bool isSlicingProfitable	(	SmallVectorImpl< LoadedSlice > &	LoadedSlices,
		const APInt &	UsedBits,
		bool	ForCodeSize,
		const SelectionDAGOptions &	Opts )

static

Check the profitability of all involved LoadedSlice.

Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (

See also: LoadedSlice::Cost) is smaller than the original load (3).

Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.

FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).

Definition at line 22877 of file DAGCombiner.cpp.

References adjustCostForPairing(), areUsedBitsDense(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

◆ isTruncateOf()

bool isTruncateOf	(	SelectionDAG &	DAG,
		SDValue	N,
		SDValue &	Op,
		KnownBits &	Known )

static

Definition at line 2454 of file DAGCombiner.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::isAllOnes(), llvm::Known, llvm::SDPatternMatch::m_c_SpecificSetCC(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SETNE, and llvm::ISD::TRUNCATE.

◆ littleEndianByteAt()

unsigned littleEndianByteAt	(	unsigned	BW,
		unsigned	i )

static

Definition at line 9975 of file DAGCombiner.cpp.

◆ matchBSwapHWordOrAndAnd()

SDValue matchBSwapHWordOrAndAnd	(	const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		SDNode *	N,
		SDValue	N0,
		SDValue	N1,
		EVT	VT )

static

◆ matchMergedBFX()

SDValue matchMergedBFX	(	SDValue	Root,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

◆ matchRotateHalf()

bool matchRotateHalf	(	const SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Shift,
		SDValue &	Mask )

static

Match "(X shl/srl V1) & V2" where V2 may not be present.

Definition at line 9168 of file DAGCombiner.cpp.

References llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().

◆ matchRotateSub()

bool matchRotateSub	(	SDValue	Pos,
		SDValue	Neg,
		unsigned	EltSize,
		SelectionDAG &	DAG,
		bool	IsRotate,
		bool	FromAdd )

static

Definition at line 9320 of file DAGCombiner.cpp.

References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLoBits(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isConstOrConstSplat(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::ISD::SUB, TLI, and llvm::ISD::TRUNCATE.

◆ mergeEltWithShuffle()

bool mergeEltWithShuffle	(	SDValue &	X,
		SDValue &	Y,
		ArrayRef< int >	Mask,
		SmallVectorImpl< int > &	NewMask,
		SDValue	Elt,
		unsigned	InsIndex )

static

Definition at line 25391 of file DAGCombiner.cpp.

References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::SDNode::ops(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::reverse(), X, and Y.

◆ narrowExtractedVectorBinOp()

SDValue narrowExtractedVectorBinOp	(	EVT	VT,
		SDValue	Src,
		unsigned	Index,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.

Definition at line 28376 of file DAGCombiner.cpp.

References llvm::ISD::AND, assert(), C(), llvm::TargetLoweringBase::Cheap, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplatFP(), llvm::EVT::isFixedLengthVector(), narrowInsertExtractVectorBinOp(), llvm::ISD::OR, llvm::peekThroughBitcasts(), SDValue(), TLI, V, X, llvm::ISD::XOR, and Y.

◆ narrowExtractedVectorLoad()

SDValue narrowExtractedVectorLoad	(	EVT	VT,
		SDValue	Src,
		unsigned	Index,
		const SDLoc &	DL,
		SelectionDAG &	DAG )

static

If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector)

Definition at line 28503 of file DAGCombiner.cpp.

References assert(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorMinNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isByteSized(), llvm::ISD::isNormalLoad(), llvm::ISD::LOAD, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, SDValue(), and TLI.

◆ narrowInsertExtractVectorBinOp()

SDValue narrowInsertExtractVectorBinOp	(	EVT	SubVT,
		SDValue	BinOp,
		unsigned	Index,
		const SDLoc &	DL,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

Definition at line 28343 of file DAGCombiner.cpp.

References DL, llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getSubVectorSrc(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), SDValue(), and TLI.

Referenced by narrowExtractedVectorBinOp().

◆ numVectorEltsOrZero()

ElementCount numVectorEltsOrZero ( EVT T )

inlinestatic

Definition at line 22076 of file DAGCombiner.cpp.

References llvm::ElementCount::getFixed(), and T.

◆ partitionShuffleOfConcats()

SDValue partitionShuffleOfConcats	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ PerformMinMaxFpToSatCombine()

SDValue PerformMinMaxFpToSatCombine	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		SelectionDAG &	DAG )

static

◆ performNanGuardFpToSatCombine()

SDValue performNanGuardFpToSatCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ PerformUMinFpToSatCombine()

SDValue PerformUMinFpToSatCombine	(	SDValue	N0,
		SDValue	N1,
		SDValue	N2,
		SDValue	N3,
		ISD::CondCode	CC,
		SelectionDAG &	DAG )

static

◆ propagateUnaryUndef()

SDValue propagateUnaryUndef	(	SelectionDAG &	DAG,
		SDValue	N0,
		EVT	VT )

static

For a unary operation, propagate poison or undef from the operand N0 to the result type VT.

Returns an empty SDValue if N0 is neither.

Definition at line 16834 of file DAGCombiner.cpp.

References llvm::SDValue::getOpcode(), llvm::SelectionDAG::getPOISON(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::POISON, SDValue(), and llvm::ISD::UNDEF.

◆ reduceBuildVecToShuffleWithZero()

SDValue reduceBuildVecToShuffleWithZero	(	SDNode *	BV,
		SelectionDAG &	DAG )

static

◆ refineIndexType()

bool refineIndexType	(	SDValue &	Index,
		ISD::MemIndexType &	IndexType,
		EVT	DataVT,
		SelectionDAG &	DAG )

Definition at line 13899 of file DAGCombiner.cpp.

References llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isIndexTypeSigned(), llvm::ISD::SIGN_EXTEND, TLI, llvm::ISD::UNSIGNED_SCALED, and llvm::ISD::ZERO_EXTEND.

◆ refineUniformBase()

bool refineUniformBase	(	SDValue &	BasePtr,
		SDValue &	Index,
		bool	IndexIsScaled,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

Definition at line 13860 of file DAGCombiner.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatValue(), llvm::SDValue::getValueType(), and llvm::isNullConstant().

◆ scalarizeBinOpOfSplats()

SDValue scalarizeBinOpOfSplats	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		bool	LegalTypes )

static

If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.

Definition at line 31091 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatSourceVector(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::MULHS, llvm::ISD::MULHU, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::SPLAT_VECTOR, TLI, X, Y, and llvm::zip().

◆ scalarizeExtractedBinOp()

SDValue scalarizeExtractedBinOp	(	SDNode *	ExtElt,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		bool	LegalTypes )

static

Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.

Definition at line 25994 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDNode::getOperandCondCode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::SDValue::hasOneUse(), isAnyConstantBuildVector(), llvm::ISD::isConstantSplatVector(), Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND_INREG, TLI, llvm::TargetLoweringBase::UndefinedBooleanContent, and llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent.

◆ shouldCombineToPostInc()

bool shouldCombineToPostInc	(	SDNode *	N,
		SDValue	Ptr,
		SDNode *	PtrUse,
		SDValue &	BasePtr,
		SDValue &	Offset,
		ISD::MemIndexedMode &	AM,
		SelectionDAG &	DAG,
		const TargetLowering &	TLI )

static

◆ shouldConvertSelectOfConstantsToMath()

bool shouldConvertSelectOfConstantsToMath	(	const SDValue &	Cond,
		EVT	VT,
		const TargetLowering &	TLI )

static

Definition at line 13077 of file DAGCombiner.cpp.

References CC, Cond, llvm::isAllOnesOrAllOnesSplat(), llvm::isNullOrNullSplat(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, and TLI.

◆ ShrinkLoadReplaceStoreWithStore()

SDValue ShrinkLoadReplaceStoreWithStore	(	const std::pair< unsigned, unsigned > &	MaskInfo,
		SDValue	IVal,
		StoreSDNode *	St,
		DAGCombiner *	DC )

static

Check to see if IVal is something that provides a value as specified by MaskInfo.

If so, replace the specified store with a narrower store of truncated IVal.

Definition at line 23091 of file DAGCombiner.cpp.

◆ simplifyDivRem()

SDValue simplifyDivRem	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 5249 of file DAGCombiner.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::isConstOrConstSplat(), llvm::isOneOrOneSplat(), llvm::SDValue::isUndef(), llvm::SelectionDAG::isUndef(), llvm::ConstantSDNode::isZero(), N, Opc, llvm::ISD::SDIV, SDValue(), and llvm::ISD::UDIV.

◆ simplifyShuffleOfShuffle()

SDValue simplifyShuffleOfShuffle ( ShuffleVectorSDNode * Shuf )

static

If we have a unary shuffle of a shuffle, see if it can be folded away completely.

This has the potential to lose undef knowledge because the first shuffle may not have an undef mask element where the second one does. So only call this after doing simplifications based on demanded elements.

Definition at line 29747 of file DAGCombiner.cpp.

References assert(), llvm::dyn_cast(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDValue::isUndef(), and SDValue().

◆ STATISTIC() [1/7]

STATISTIC	(	LdStFP2Int	,
		"Number of fp load/store pairs transformed to int"	)

◆ STATISTIC() [2/7]

STATISTIC	(	NodesCombined	,
		"Number of dag nodes combined"	)

◆ STATISTIC() [3/7]

STATISTIC	(	NumFPLogicOpsConv	,
		"Number of logic ops converted to fp ops"	)

◆ STATISTIC() [4/7]

STATISTIC	(	OpsNarrowed	,
		"Number of load/op/store narrowed"	)

◆ STATISTIC() [5/7]

STATISTIC	(	PostIndexedNodes	,
		"Number of post-indexed nodes created"	)

◆ STATISTIC() [6/7]

STATISTIC	(	PreIndexedNodes	,
		"Number of pre-indexed nodes created"	)

◆ STATISTIC() [7/7]

STATISTIC	(	SlicedLoads	,
		"Number of load sliced"	)

◆ stripConstantMask()

SDValue stripConstantMask	(	const SelectionDAG &	DAG,
		SDValue	Op,
		SDValue &	Mask )

static

Definition at line 9157 of file DAGCombiner.cpp.

References llvm::ISD::AND, and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().

Referenced by extractShiftForRotate(), and matchRotateHalf().

◆ stripTruncAndExt()

SDValue stripTruncAndExt ( SDValue Value )

static

Definition at line 10008 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ takeInexpensiveLog2()

SDValue takeInexpensiveLog2	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		EVT	VT,
		SDValue	Op,
		unsigned	Depth,
		bool	AssumeNonZero )

static

Definition at line 32123 of file DAGCombiner.cpp.

Referenced by takeInexpensiveLog2().

◆ tryFoldToZero()

SDValue tryFoldToZero	(	const SDLoc &	DL,
		const TargetLowering &	TLI,
		EVT	VT,
		SelectionDAG &	DAG,
		bool	LegalOperations )

static

Definition at line 4257 of file DAGCombiner.cpp.

References llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getConstant(), llvm::EVT::isVector(), SDValue(), and TLI.

◆ tryToFoldExtendOfConstant()

SDValue tryToFoldExtendOfConstant	(	SDNode *	N,
		const SDLoc &	DL,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		bool	LegalTypes )

static

Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.

This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.

Definition at line 15368 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), C(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isExtOpcode(), llvm::ISD::isExtVecInRegOpcode(), llvm::EVT::isVector(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, TLI, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent.

◆ tryToFoldExtendSelectLoad()

SDValue tryToFoldExtendSelectLoad	(	SDNode *	N,
		const TargetLowering &	TLI,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		CombineLevel	Level )

static

Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).

Definition at line 15321 of file DAGCombiner.cpp.

References llvm::AfterLegalizeTypes, llvm::ISD::ANY_EXTEND, assert(), llvm::cast(), Cond, DL, llvm::ISD::EXTLOAD, llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlign(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SelectionDAG::getSelect(), isCompatibleLoad(), llvm::TargetLoweringBase::Legal, llvm::SDPatternMatch::m_OneUse(), llvm::PatternMatch::m_SelectLike(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, TLI, llvm::ISD::VSELECT, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfAtomicLoad()

SDValue tryToFoldExtOfAtomicLoad	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		EVT	VT,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType )

static

Definition at line 15999 of file DAGCombiner.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD, llvm::cast(), llvm::dyn_cast(), llvm::SelectionDAG::getAtomicLoad(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SEXTLOAD, TLI, llvm::ISD::TRUNCATE, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfExtload()

SDValue tryToFoldExtOfExtload	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType )

static

◆ tryToFoldExtOfLoad()

SDValue tryToFoldExtOfLoad	(	SelectionDAG &	DAG,
		DAGCombiner &	Combiner,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc,
		bool	NonNegZExt = false )

static

Definition at line 15805 of file DAGCombiner.cpp.

References llvm::SelectionDAG::AddDbgValue(), llvm::DIExpression::appendExt(), llvm::DIExpression::appendOpsToArg(), assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, CC, Changed, llvm::DIExpression::convertToVariadicExpression(), DL, llvm::dyn_cast(), E(), ExtendUsesToFormExtLoad(), llvm::ISD::FREEZE, llvm::SDDbgOperand::fromNode(), llvm::SelectionDAG::getDbgValueList(), llvm::SelectionDAG::GetDbgValues(), llvm::SelectionDAG::getExtLoad(), llvm::DIExpression::getExtOps(), llvm::SelectionDAG::getFreeze(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::hasOneUse(), llvm::SDValue::hasOneUse(), I, llvm::EVT::isFixedLengthVector(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isSignedIntSetCC(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::Load, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SDDbgOperand::SDNODE, SDValue(), llvm::ISD::SETCC, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorTemplateCommon< T, typename >::size(), TLI, llvm::SelectionDAG::transferDbgValues(), llvm::ISD::TRUNCATE, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.

◆ tryToFoldExtOfMaskedLoad()

SDValue tryToFoldExtOfMaskedLoad	(	SelectionDAG &	DAG,
		const TargetLowering &	TLI,
		EVT	VT,
		bool	LegalOperations,
		SDNode *	N,
		SDValue	N0,
		ISD::LoadExtType	ExtLoadType,
		ISD::NodeType	ExtOpc )

static

Definition at line 15970 of file DAGCombiner.cpp.

References llvm::cast(), llvm::dyn_cast(), llvm::SelectionDAG::getMaskedLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::hasOneUse(), N, llvm::ISD::NON_EXTLOAD, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), and TLI.

◆ visitORCommutative()

SDValue visitORCommutative	(	SelectionDAG &	DAG,
		SDValue	N0,
		SDValue	N1,
		SDNode *	N )

static

OR combines for which the commuted variant will be tried as well.

Definition at line 8797 of file DAGCombiner.cpp.

◆ widenAbs()

◆ widenCtPop()

SDValue widenCtPop	(	SDNode *	Extend,
		SelectionDAG &	DAG,
		const SDLoc &	DL )

static

Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type.

Definition at line 16435 of file DAGCombiner.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), SDValue(), TLI, and llvm::ISD::ZERO_EXTEND.

◆ zeroExtendToMatch()

void zeroExtendToMatch	(	APInt &	LHS,
		APInt &	RHS,
		unsigned	Offset = 0 )

static

Definition at line 945 of file DAGCombiner.cpp.

References LHS, llvm::Offset, and RHS.

Referenced by extractShiftForRotate().

Macros

Typedefs

Functions

Macro Definition Documentation

◆ BEGIN_REGISTER_VP_SDNODE

◆ DEBUG_TYPE

Typedef Documentation

◆ SDByteProvider

Function Documentation

◆ adjustCostForPairing()

◆ areBitwiseNotOfEachother()

◆ areBothOperandsNotNan()

◆ areBothOperandsNotSNan()

◆ areSlicesNextToEachOther()

◆ areUsedBitsDense()

◆ bigEndianByteAt()

◆ calculateByteProvider()

◆ calculateConstantLowMaskLanes()

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [1/2]

◆ CanCombineFCOPYSIGN_EXTEND_ROUND() [2/2]

◆ canCombineShuffleToExtendVectorInreg()

◆ canFoldInAddressingMode()

◆ canSplitIdx()

◆ CheckForMaskedLoad()

◆ combineCarryDiamond()

◆ combineConcatVectorOfCasts()

◆ combineConcatVectorOfConcatVectors()

◆ combineConcatVectorOfExtracts()

◆ combineConcatVectorOfScalars()

◆ combineConcatVectorOfShuffleAndItsOperands()

◆ combineConcatVectorOfShuffles()

◆ combineConcatVectorOfSplats()

◆ combineMinNumMaxNumImpl()

◆ combineOrOfSetCCToUSUBOCarry()

◆ combineSelectAsExtAnd()

◆ combineSelectCCToPseudoMinMax()

◆ combineSelectToPseudoMinMax()

◆ combineShiftAnd1ToBitTest()

◆ combineShiftOfShiftedLogic()

◆ combineShiftToMULH()

◆ combineShuffleOfBitcast()

◆ combineShuffleOfScalars()

◆ combineShuffleOfSplatVal()

◆ combineShuffleToAnyExtendVectorInreg()

◆ combineShuffleToZeroExtendVectorInReg()

◆ combineTruncationShuffle()

◆ combineUADDO_CARRYDiamond()

◆ combineVSelectWithAllOnesOrZeros()

◆ ConvertSelectToConcatVector()

◆ DEBUG_COUNTER()

◆ detectSSatSPattern()

◆ detectSSatUPattern()

◆ detectUSatUPattern()

◆ eliminateFPCastPair()

◆ ExtendUsesToFormExtLoad()

◆ extractBooleanFlip()

◆ extractShiftForRotate()

◆ foldAddSubBoolOfMaskedVal()

◆ foldAddSubMasked1()

◆ foldAddSubOfSignBit()

◆ foldAndOrOfSETCC()

◆ foldAndToUsubsat()

◆ foldBitOrderCrossLogicOp()

◆ foldBoolSelectToLogic()

◆ foldExtendedSignBitTest()

◆ foldExtendVectorInregToExtendOfSubvector()

◆ foldExtractSubvectorFromShuffleVector()

◆ foldFPToIntToFP()

◆ FoldIntToFPToInt()

◆ foldLogicOfShifts()

◆ foldLogicTreeOfShifts()

◆ foldMaskedMerge()

◆ foldRemainderIdiom()

◆ foldSelectCCOfSelect()

◆ foldSelectOfConstantsUsingSra()

◆ foldSelectOfSelectCmp()

◆ foldSelectWithIdentityConstant()

◆ foldShuffleOfConcatUndefs()

◆ foldSubCtlzNot()

◆ foldToMaskedStore()