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LLVM 18.0.0git
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#include "llvm/ADT/APFloat.h"#include "llvm/ADT/APInt.h"#include "llvm/ADT/ArrayRef.h"#include "llvm/ADT/DenseMap.h"#include "llvm/ADT/IntervalMap.h"#include "llvm/ADT/STLExtras.h"#include "llvm/ADT/SetVector.h"#include "llvm/ADT/SmallBitVector.h"#include "llvm/ADT/SmallPtrSet.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/AliasAnalysis.h"#include "llvm/Analysis/MemoryLocation.h"#include "llvm/Analysis/TargetLibraryInfo.h"#include "llvm/Analysis/ValueTracking.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/ByteProvider.h"#include "llvm/CodeGen/DAGCombine.h"#include "llvm/CodeGen/ISDOpcodes.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineMemOperand.h"#include "llvm/CodeGen/MachineValueType.h"#include "llvm/CodeGen/RuntimeLibcalls.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"#include "llvm/CodeGen/SelectionDAGNodes.h"#include "llvm/CodeGen/SelectionDAGTargetInfo.h"#include "llvm/CodeGen/TargetLowering.h"#include "llvm/CodeGen/TargetRegisterInfo.h"#include "llvm/CodeGen/TargetSubtargetInfo.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/Attributes.h"#include "llvm/IR/Constant.h"#include "llvm/IR/DataLayout.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/Metadata.h"#include "llvm/Support/Casting.h"#include "llvm/Support/CodeGen.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Compiler.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include "llvm/Support/raw_ostream.h"#include "llvm/Target/TargetMachine.h"#include "llvm/Target/TargetOptions.h"#include <algorithm>#include <cassert>#include <cstdint>#include <functional>#include <iterator>#include <optional>#include <string>#include <tuple>#include <utility>#include <variant>#include "llvm/IR/VPIntrinsics.def"Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "dagcombine" |
| #define | BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) case ISD::SDOPC: |
Typedefs | |
| using | SDByteProvider = ByteProvider< SDNode * > |
| Recursively traverses the expression calculating the origin of the requested byte of the given value. | |
Functions | |
| STATISTIC (NodesCombined, "Number of dag nodes combined") | |
| STATISTIC (PreIndexedNodes, "Number of pre-indexed nodes created") | |
| STATISTIC (PostIndexedNodes, "Number of post-indexed nodes created") | |
| STATISTIC (OpsNarrowed, "Number of load/op/store narrowed") | |
| STATISTIC (LdStFP2Int, "Number of fp load/store pairs transformed to int") | |
| STATISTIC (SlicedLoads, "Number of load sliced") | |
| STATISTIC (NumFPLogicOpsConv, "Number of logic ops converted to fp ops") | |
| static void | zeroExtendToMatch (APInt &LHS, APInt &RHS, unsigned Offset=0) |
| static bool | isConstantSplatVectorMaskForType (SDNode *N, EVT ScalarTy) |
| static bool | isConstantOrConstantVector (SDValue N, bool NoOpaques=false) |
| static bool | isAnyConstantBuildVector (SDValue V, bool NoOpaques=false) |
| static bool | canSplitIdx (LoadSDNode *LD) |
| static SDValue | getInputChainForNode (SDNode *N) |
| Given a node, return its input chain if it has one, otherwise return a null sd operand. | |
| static ConstantSDNode * | getAsNonOpaqueConstant (SDValue N) |
If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr. | |
| static bool | isTruncateOf (SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known) |
| static bool | canFoldInAddressingMode (SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) |
| Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode. | |
| static SDValue | foldSelectWithIdentityConstant (SDNode *N, SelectionDAG &DAG, bool ShouldCommuteOperands) |
| This inverts a canonicalization in IR that replaces a variable select arm with an identity constant. | |
| static SDValue | foldAddSubBoolOfMaskedVal (SDNode *N, SelectionDAG &DAG) |
| static SDValue | foldAddSubOfSignBit (SDNode *N, SelectionDAG &DAG) |
| Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant. | |
| static bool | areBitwiseNotOfEachother (SDValue Op0, SDValue Op1) |
| static SDValue | getAsCarry (const TargetLowering &TLI, SDValue V, bool ForceCarryReconstruction=false) |
| static SDValue | foldAddSubMasked1 (bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL) |
| Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1. | |
| static SDValue | extractBooleanFlip (SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force) |
| Flips a boolean if it is cheaper to compute. | |
| static SDValue | combineUADDO_CARRYDiamond (DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N) |
| If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry) | |
| static SDValue | combineCarryDiamond (SelectionDAG &DAG, const TargetLowering &TLI, SDValue N0, SDValue N1, SDNode *N) |
| static SDValue | getTruncatedUSUBSAT (EVT DstVT, EVT SrcVT, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &DL) |
| static SDValue | tryFoldToZero (const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations) |
| static bool | isDivRemLibcallAvailable (SDNode *Node, bool isSigned, const TargetLowering &TLI) |
| Return true if divmod libcall is available. | |
| static SDValue | simplifyDivRem (SDNode *N, SelectionDAG &DAG) |
| static bool | isDivisorPowerOfTwo (SDValue Divisor) |
| static SDValue | isSaturatingMinMax (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, unsigned &BW, bool &Unsigned, SelectionDAG &DAG) |
| static SDValue | PerformMinMaxFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG) |
| static SDValue | PerformUMinFpToSatCombine (SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, SelectionDAG &DAG) |
| static bool | arebothOperandsNotSNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG) |
| static bool | arebothOperandsNotNan (SDValue Operand1, SDValue Operand2, SelectionDAG &DAG) |
| static unsigned | getMinMaxOpcodeForFP (SDValue Operand1, SDValue Operand2, ISD::CondCode CC, unsigned OrAndOpcode, SelectionDAG &DAG, bool isFMAXNUMFMINNUM_IEEE, bool isFMAXNUMFMINNUM) |
| static SDValue | foldAndOrOfSETCC (SDNode *LogicOp, SelectionDAG &DAG) |
| static SDValue | combineSelectAsExtAnd (SDValue Cond, SDValue T, SDValue F, const SDLoc &DL, SelectionDAG &DAG) |
| static SDValue | combineShiftAnd1ToBitTest (SDNode *And, SelectionDAG &DAG) |
| Try to replace shift/logic that tests if a bit is clear with mask + setcc. | |
| static SDValue | foldAndToUsubsat (SDNode *N, SelectionDAG &DAG) |
| For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it. | |
| static SDValue | foldLogicOfShifts (SDNode *N, SDValue LogicOp, SDValue ShiftOp, SelectionDAG &DAG) |
| Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values. | |
| static SDValue | foldLogicTreeOfShifts (SDNode *N, SDValue LeftHand, SDValue RightHand, SelectionDAG &DAG) |
| Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount. | |
| static bool | isBSwapHWordElement (SDValue N, MutableArrayRef< SDNode * > Parts) |
| Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap. | |
| static bool | isBSwapHWordPair (SDValue N, MutableArrayRef< SDNode * > Parts) |
| static SDValue | matchBSwapHWordOrAndAnd (const TargetLowering &TLI, SelectionDAG &DAG, SDNode *N, SDValue N0, SDValue N1, EVT VT, EVT ShiftAmountTy) |
| static SDValue | visitORCommutative (SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) |
| OR combines for which the commuted variant will be tried as well. | |
| static SDValue | stripConstantMask (const SelectionDAG &DAG, SDValue Op, SDValue &Mask) |
| static bool | matchRotateHalf (const SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask) |
| Match "(X shl/srl V1) & V2" where V2 may not be present. | |
| static SDValue | extractShiftForRotate (SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL) |
| Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv. | |
| static bool | matchRotateSub (SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG, bool IsRotate) |
| static std::optional< SDByteProvider > | calculateByteProvider (SDValue Op, unsigned Index, unsigned Depth, std::optional< uint64_t > VectorIndex, unsigned StartingIndex=0) |
| static unsigned | littleEndianByteAt (unsigned BW, unsigned i) |
| static unsigned | bigEndianByteAt (unsigned BW, unsigned i) |
| static std::optional< bool > | isBigEndian (const ArrayRef< int64_t > ByteOffsets, int64_t FirstOffset) |
| static SDValue | stripTruncAndExt (SDValue Value) |
| static SDValue | combineShiftOfShiftedLogic (SDNode *Shift, SelectionDAG &DAG) |
| If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op. | |
| static SDValue | combineShiftToMULH (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) |
| static SDValue | foldBitOrderCrossLogicOp (SDNode *N, SelectionDAG &DAG) |
| static bool | isLegalToCombineMinNumMaxNum (SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI) |
| static SDValue | combineMinNumMaxNumImpl (const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) |
| static SDValue | foldSelectOfConstantsUsingSra (SDNode *N, SelectionDAG &DAG) |
| If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask. | |
| static bool | shouldConvertSelectOfConstantsToMath (const SDValue &Cond, EVT VT, const TargetLowering &TLI) |
| static SDValue | foldBoolSelectToLogic (SDNode *N, SelectionDAG &DAG) |
| static SDValue | foldVSelectToSignBitSplatMask (SDNode *N, SelectionDAG &DAG) |
| static SDValue | ConvertSelectToConcatVector (SDNode *N, SelectionDAG &DAG) |
| bool | refineUniformBase (SDValue &BasePtr, SDValue &Index, bool IndexIsScaled, SelectionDAG &DAG, const SDLoc &DL) |
| bool | refineIndexType (SDValue &Index, ISD::MemIndexType &IndexType, EVT DataVT, SelectionDAG &DAG) |
| static bool | isCompatibleLoad (SDValue N, unsigned ExtOpcode) |
| Check if N satisfies: N is used once. | |
| static SDValue | tryToFoldExtendSelectLoad (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, CombineLevel Level) |
| Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). | |
| static SDValue | tryToFoldExtendOfConstant (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes) |
| Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants. | |
| static bool | ExtendUsesToFormExtLoad (EVT VT, SDNode *N, SDValue N0, unsigned ExtOpc, SmallVectorImpl< SDNode * > &ExtendNodes, const TargetLowering &TLI) |
| static SDValue | tryToFoldExtOfExtload (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType) |
| static SDValue | tryToFoldExtOfLoad (SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) |
| static SDValue | tryToFoldExtOfMaskedLoad (SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) |
| static SDValue | foldExtendedSignBitTest (SDNode *N, SelectionDAG &DAG, bool LegalOperations) |
| static SDValue | widenCtPop (SDNode *Extend, SelectionDAG &DAG) |
| Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type. | |
| static SDValue | widenAbs (SDNode *Extend, SelectionDAG &DAG) |
| static SDValue | foldExtendVectorInregToExtendOfSubvector (SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalOperations) |
| static SDNode * | getBuildPairElt (SDNode *N, unsigned i) |
| static unsigned | getPPCf128HiElementSelector (const SelectionDAG &DAG) |
| static bool | isContractableFMUL (const TargetOptions &Options, SDValue N) |
| static bool | hasNoInfs (const TargetOptions &Options, SDValue N) |
| static bool | CanCombineFCOPYSIGN_EXTEND_ROUND (EVT XTy, EVT YTy) |
| copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively. | |
| static bool | CanCombineFCOPYSIGN_EXTEND_ROUND (SDNode *N) |
| static SDValue | foldFPToIntToFP (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) |
| static SDValue | FoldIntToFPToInt (SDNode *N, SelectionDAG &DAG) |
| static bool | getCombineLoadStoreParts (SDNode *N, unsigned Inc, unsigned Dec, bool &IsLoad, bool &IsMasked, SDValue &Ptr, const TargetLowering &TLI) |
| static bool | shouldCombineToPostInc (SDNode *N, SDValue Ptr, SDNode *PtrUse, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) |
| static SDNode * | getPostIndexedLoadStoreOp (SDNode *N, bool &IsLoad, bool &IsMasked, SDValue &Ptr, SDValue &BasePtr, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG, const TargetLowering &TLI) |
| static ElementCount | numVectorEltsOrZero (EVT T) |
| static bool | areUsedBitsDense (const APInt &UsedBits) |
Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0. | |
| static bool | areSlicesNextToEachOther (const LoadedSlice &First, const LoadedSlice &Second) |
Check whether or not First and Second are next to each other in memory. | |
| static void | adjustCostForPairing (SmallVectorImpl< LoadedSlice > &LoadedSlices, LoadedSlice::Cost &GlobalLSCost) |
Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices. | |
| static bool | isSlicingProfitable (SmallVectorImpl< LoadedSlice > &LoadedSlices, const APInt &UsedBits, bool ForCodeSize) |
| Check the profitability of all involved LoadedSlice. | |
| static std::pair< unsigned, unsigned > | CheckForMaskedLoad (SDValue V, SDValue Ptr, SDValue Chain) |
| Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out. | |
| static SDValue | ShrinkLoadReplaceStoreWithStore (const std::pair< unsigned, unsigned > &MaskInfo, SDValue IVal, StoreSDNode *St, DAGCombiner *DC) |
| Check to see if IVal is something that provides a value as specified by MaskInfo. | |
| static bool | mergeEltWithShuffle (SDValue &X, SDValue &Y, ArrayRef< int > Mask, SmallVectorImpl< int > &NewMask, SDValue Elt, unsigned InsIndex) |
| static SDValue | scalarizeExtractedBinop (SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations) |
| Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector. | |
| static SDValue | reduceBuildVecToShuffleWithZero (SDNode *BV, SelectionDAG &DAG) |
| template<typename R , typename T > | |
| static auto | getFirstIndexOf (R &&Range, const T &Val) |
| static SDValue | combineConcatVectorOfScalars (SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineConcatVectorOfConcatVectors (SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineConcatVectorOfExtracts (SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineConcatVectorOfCasts (SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineConcatVectorOfShuffleAndItsOperands (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations) |
| static SDValue | getSubVectorSrc (SDValue V, SDValue Index, EVT SubVT) |
| static SDValue | narrowInsertExtractVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations) |
| static SDValue | narrowExtractedVectorBinOp (SDNode *Extract, SelectionDAG &DAG, bool LegalOperations) |
| If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction. | |
| static SDValue | narrowExtractedVectorLoad (SDNode *Extract, SelectionDAG &DAG) |
| If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector) | |
| static SDValue | foldExtractSubvectorFromShuffleVector (SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations) |
| Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), EXTRACT_SUBVECTOR(Op?, ?), Mask')) iff it is legal and profitable to do so. | |
| static SDValue | foldShuffleOfConcatUndefs (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) |
| Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation. | |
| static SDValue | partitionShuffleOfConcats (SDNode *N, SelectionDAG &DAG) |
| static SDValue | combineShuffleOfScalars (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI) |
| static std::optional< EVT > | canCombineShuffleToExtendVectorInreg (unsigned Opcode, EVT VT, std::function< bool(unsigned)> Match, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalTypes, bool LegalOperations) |
| static SDValue | combineShuffleToAnyExtendVectorInreg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations) |
| static SDValue | combineShuffleToZeroExtendVectorInReg (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations) |
| static SDValue | combineTruncationShuffle (ShuffleVectorSDNode *SVN, SelectionDAG &DAG) |
| static SDValue | combineShuffleOfSplatVal (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) |
| static SDValue | combineShuffleOfBitcast (ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, bool LegalOperations) |
| static SDValue | formSplatFromShuffles (ShuffleVectorSDNode *OuterShuf, SelectionDAG &DAG) |
| Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X. | |
| static int | getShuffleMaskIndexOfOneElementFromOp0IntoOp1 (ArrayRef< int > Mask) |
| If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand. | |
| static SDValue | replaceShuffleOfInsert (ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) |
| If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle. | |
| static SDValue | simplifyShuffleOfShuffle (ShuffleVectorSDNode *Shuf) |
| If we have a unary shuffle of a shuffle, see if it can be folded away completely. | |
| static SDValue | scalarizeBinOpOfSplats (SDNode *N, SelectionDAG &DAG, const SDLoc &DL) |
| If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat. | |
| static SDValue | takeInexpensiveLog2 (SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned Depth, bool AssumeNonZero) |
Variables | |
| static cl::opt< bool > | CombinerGlobalAA ("combiner-global-alias-analysis", cl::Hidden, cl::desc("Enable DAG combiner's use of IR alias analysis")) |
| static cl::opt< bool > | UseTBAA ("combiner-use-tbaa", cl::Hidden, cl::init(true), cl::desc("Enable DAG combiner's use of TBAA")) |
| static cl::opt< std::string > | CombinerAAOnlyFunc ("combiner-aa-only-func", cl::Hidden, cl::desc("Only use DAG-combiner alias analysis in this" " function")) |
| static cl::opt< bool > | StressLoadSlicing ("combiner-stress-load-slicing", cl::Hidden, cl::desc("Bypass the profitability model of load slicing"), cl::init(false)) |
| Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards. | |
| static cl::opt< bool > | MaySplitLoadIndex ("combiner-split-load-index", cl::Hidden, cl::init(true), cl::desc("DAG combiner may split indexing from loads")) |
| static cl::opt< bool > | EnableStoreMerging ("combiner-store-merging", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable merging multiple stores " "into a wider store")) |
| static cl::opt< unsigned > | TokenFactorInlineLimit ("combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048), cl::desc("Limit the number of operands to inline for Token Factors")) |
| static cl::opt< unsigned > | StoreMergeDependenceLimit ("combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10), cl::desc("Limit the number of times for the same StoreNode and RootNode " "to bail out in store merging dependence check")) |
| static cl::opt< bool > | EnableReduceLoadOpStoreWidth ("combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable reducing the width of load/op/store " "sequence")) |
| static cl::opt< bool > | EnableShrinkLoadReplaceStoreWithStore ("combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true), cl::desc("DAG combiner enable load/<replace bytes>/store with " "a narrower store")) |
| static cl::opt< bool > | EnableVectorFCopySignExtendRound ("combiner-vector-fcopysign-extend-round", cl::Hidden, cl::init(false), cl::desc("Enable merging extends and rounds into FCOPYSIGN on vector types")) |
| #define BEGIN_REGISTER_VP_SDNODE | ( | SDOPC, | |
| ... | |||
| ) | case ISD::SDOPC: |
| #define DEBUG_TYPE "dagcombine" |
Definition at line 80 of file DAGCombiner.cpp.
| using SDByteProvider = ByteProvider<SDNode *> |
Recursively traverses the expression calculating the origin of the requested byte of the given value.
Returns std::nullopt if the provider can't be calculated.
For all the values except the root of the expression, we verify that the value has exactly one use and if not then return std::nullopt. This way if the origin of the byte is returned it's guaranteed that the values which contribute to the byte are not used outside of this expression. However, there is a special case when dealing with vector loads – we allow more than one use if the load is a vector type. Since the values that contribute to the byte ultimately come from the ExtractVectorElements of the Load, we don't care if the Load has uses other than ExtractVectorElements, because those operations are independent from the pattern to be combined. For vector loads, we simply care that the ByteProviders are adjacent positions of the same vector, and their index matches the byte that is being provided. This is captured by the VectorIndex algorithm. VectorIndex is the index used in an ExtractVectorElement, and StartingIndex is the byte position we are trying to provide for the LoadCombine. If these do not match, then we can not combine the vector loads. Index uses the byte position we are trying to provide for and is matched against the shl and load size. The Index algorithm ensures the requested byte is provided for by the pattern, and the pattern does not over provide bytes.
The supported LoadCombine pattern for vector loads is as follows or / \ or shl / \ | or shl zext / \ | | shl zext zext EVE* | | | | zext EVE* EVE* LOAD | | | EVE* LOAD LOAD | LOAD
*ExtractVectorElement
Definition at line 8658 of file DAGCombiner.cpp.
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Adjust the GlobalLSCost according to the target paring capabilities and the layout of the slices.
GlobalLSCost should account for at least as many loads as there is in the slices in LoadedSlices. Definition at line 19158 of file DAGCombiner.cpp.
References areSlicesNextToEachOther(), assert(), llvm::First, LHS, RHS, llvm::SmallVectorBase< Size_T >::size(), and llvm::sort().
Referenced by isSlicingProfitable().
Definition at line 2697 of file DAGCombiner.cpp.
References llvm::SDValue::getOperand(), and llvm::isBitwiseNot().
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Definition at line 6072 of file DAGCombiner.cpp.
References llvm::SelectionDAG::isKnownNeverNaN().
Referenced by getMinMaxOpcodeForFP().
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Definition at line 6067 of file DAGCombiner.cpp.
References llvm::SelectionDAG::isKnownNeverSNaN().
Referenced by getMinMaxOpcodeForFP().
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Check whether or not First and Second are next to each other in memory.
This means that there is no hole between the bits loaded by First and the bits loaded by Second.
Definition at line 19143 of file DAGCombiner.cpp.
References areUsedBitsDense(), assert(), and llvm::First.
Referenced by adjustCostForPairing().
Check that all bits set in UsedBits form a dense region, i.e., UsedBits looks like 0..0 1..1 0..0.
Definition at line 19126 of file DAGCombiner.cpp.
References llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::APInt::getActiveBits(), llvm::APInt::isAllOnes(), llvm::APInt::lshr(), and llvm::APInt::trunc().
Referenced by areSlicesNextToEachOther(), and isSlicingProfitable().
Definition at line 8801 of file DAGCombiner.cpp.
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Definition at line 8661 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::BitWidth, llvm::ISD::BSWAP, calculateByteProvider(), llvm::Depth, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ByteProvider< ISelOp >::getConstantZero(), llvm::SDValue::getScalarValueSizeInBits(), llvm::ByteProvider< ISelOp >::getSrc(), LHS, llvm::ISD::LOAD, llvm::ISD::OR, RHS, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
Referenced by calculateByteProvider(), handleMulOperand(), and matchPERM().
copysign(x, fp_extend(y)) -> copysign(x, y) copysign(x, fp_round(y)) -> copysign(x, y) Operands to the functions are the type of X and Y respectively.
Definition at line 17175 of file DAGCombiner.cpp.
References EnableVectorFCopySignExtendRound, and llvm::EVT::isVector().
Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().
Definition at line 17190 of file DAGCombiner.cpp.
References CanCombineFCOPYSIGN_EXTEND_ROUND(), llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), and N.
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Definition at line 24768 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), llvm::Match, and Opcode.
Referenced by combineShuffleToAnyExtendVectorInreg(), and combineShuffleToZeroExtendVectorInReg().
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Return true if 'Use' is a load or a store that uses N as its base pointer and that N may be folded in the load / store addressing mode.
Definition at line 2410 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::TargetLoweringBase::isLegalAddressingMode(), N, llvm::Offset, llvm::TargetLoweringBase::AddrMode::Scale, and llvm::ISD::SUB.
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Definition at line 1189 of file DAGCombiner.cpp.
References MaySplitLoadIndex, and llvm::ISD::TargetConstant.
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Check to see if V is (and load (ptr), imm), where the load is having specific bytes cleared out.
If so, return the byte size being masked out and the shift amount.
Definition at line 19367 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_one(), llvm::countr_zero(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), Ptr, and llvm::ISD::TokenFactor.
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Definition at line 3555 of file DAGCombiner.cpp.
References llvm::ISD::AND, DL, getAsCarry(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::SDNode::isOperandOf(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), N, Opcode, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), std::swap(), llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::USUBO, and llvm::ISD::USUBO_CARRY.
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Definition at line 23610 of file DAGCombiner.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.
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Definition at line 23497 of file DAGCombiner.cpp.
References llvm::SmallVectorImpl< T >::append(), assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::TargetLoweringBase::isTypeLegal(), and N.
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Definition at line 23536 of file DAGCombiner.cpp.
References llvm::TargetLowering::buildLegalVectorShuffle(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBitcast(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), llvm::SDValue::isUndef(), N, and llvm::peekThroughBitcasts().
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Definition at line 23433 of file DAGCombiner.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::UNDEF.
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Definition at line 23676 of file DAGCombiner.cpp.
References llvm::all_of(), llvm::append_range(), assert(), llvm::MutableArrayRef< T >::begin(), llvm::ISD::CONCAT_VECTORS, llvm::MutableArrayRef< T >::end(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), isUndef(), llvm_unreachable, N, llvm::SDNode::ops(), llvm::SmallVectorImpl< T >::reserve(), llvm::ArrayRef< T >::size(), llvm::MutableArrayRef< T >::take_back(), llvm::MutableArrayRef< T >::take_front(), llvm::ISD::VECTOR_SHUFFLE, and llvm::zip().
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Definition at line 11143 of file DAGCombiner.cpp.
References CC, DL, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), LHS, Opcode, RHS, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
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Definition at line 6320 of file DAGCombiner.cpp.
References llvm::ISD::AND, Cond, DL, F, llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isNullConstant(), llvm::isOneConstant(), and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
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Try to replace shift/logic that tests if a bit is clear with mask + setcc.
For a target with a bit test, this is expected to become test + set and save at least 1 instruction.
Definition at line 6743 of file DAGCombiner.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::BitWidth, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::TargetLoweringBase::hasBitTest(), llvm::SDValue::hasOneUse(), llvm::isBitwiseNot(), llvm::isOneConstant(), llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::SETEQ, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and X.
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If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.
This is a throughput improvement.
Definition at line 9590 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::ISD::OR, X, llvm::ISD::XOR, and Y.
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Definition at line 10122 of file DAGCombiner.cpp.
References llvm::any_of(), assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::UMUL_LOHI, llvm::SDNode::uses(), and llvm::ISD::ZERO_EXTEND.
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Definition at line 25131 of file DAGCombiner.cpp.
References llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getBitcast(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), isAnyConstantBuildVector(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::ISD::VECTOR_SHUFFLE, and llvm::widenShuffleMaskElts().
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Definition at line 24685 of file DAGCombiner.cpp.
References llvm::EVT::bitsLT(), llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDNode::hasOneUse(), Idx, llvm::SmallSet< T, N, C >::insert(), isAnyConstantBuildVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isInteger(), llvm::isIntOrFPConstant(), llvm::SDValue::isUndef(), llvm::TargetLoweringBase::isZExtFree(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::SCALAR_TO_VECTOR.
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Definition at line 25029 of file DAGCombiner.cpp.
References assert(), llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), Idx, llvm::ShuffleVectorSDNode::isSplat(), llvm::SelectionDAG::isSplatValue(), llvm::SDValue::isUndef(), llvm::APInt::popcount(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::APInt::setBit(), llvm::ArrayRef< T >::size(), and llvm::Splat.
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Definition at line 24806 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND_VECTOR_INREG, canCombineShuffleToExtendVectorInreg(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), and Opcode.
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Definition at line 24844 of file DAGCombiner.cpp.
References llvm::all_of(), assert(), llvm::ArrayRef< T >::begin(), canCombineShuffleToExtendVectorInreg(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::SelectionDAG::computeVectorKnownZeroElements(), llvm::ArrayRef< T >::drop_front(), llvm::ArrayRef< T >::end(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::getShuffleMaskWithWidestElts(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZero(), I, llvm::DataLayout::isBigEndian(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm::TargetLoweringBase::isTypeLegal(), Opcode, llvm::SDNode::ops(), llvm::ArrayRef< T >::size(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::ZERO_EXTEND_VECTOR_INREG, and llvm::zip().
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Definition at line 24970 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getDataLayout(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::DataLayout::isBigEndian(), llvm::ISD::isExtVecInRegOpcode(), llvm::EVT::isInteger(), Opcode, and llvm::peekThroughBitcasts().
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If we are facing some sort of diamond carry propapagtion pattern try to break it up to generate something like: (uaddo_carry X, 0, (uaddo_carry A, B, Z):Carry)
The end result is usually an increase in operation required, but because the carry is now linearized, other transforms can kick in and optimize the DAG.
Patterns typically look something like (uaddo A, B) / \ Carry Sum | \ | (uaddo_carry *, 0, Z) | / \ Carry | / (uaddo_carry X, *, *)
But numerous variation exist. Our goal is to identify A, B, X and Z and produce a combine with a single path for carry propagation.
First look for a suitable Z. It will present itself in the form of (uaddo_carry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
(uaddo A, B)
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(uaddo_carry *, 0, Z)
(uaddo_carry A, 0, Z) | Sum | (uaddo *, B)
Definition at line 3462 of file DAGCombiner.cpp.
References A, B, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getVTList(), llvm::isNullConstant(), llvm::isOneConstant(), N, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, and X.
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Definition at line 11674 of file DAGCombiner.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, Cond, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::isZero(), LHS, N, and RHS.
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Definition at line 12775 of file DAGCombiner.cpp.
References llvm::Add, llvm::ISD::ANY_EXTEND, CC, llvm::ISD::CopyToReg, llvm::SmallVectorBase< Size_T >::empty(), llvm::User::getOperand(), llvm::SDValue::getResNo(), llvm::Use::getUser(), llvm::SDValue::getValueType(), llvm::ISD::isSignedIntSetCC(), llvm::TargetLoweringBase::isTruncateFree(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETCC, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), and llvm::ISD::ZERO_EXTEND.
Referenced by tryToFoldExtOfLoad().
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Flips a boolean if it is cheaper to compute.
If the Force parameters is set, then the flip also occurs if computing the inverse is the same cost. This function returns an empty SDValue in case it cannot flip the boolean without increasing the cost of the computation. If you want to flip a boolean no matter what, use DAG.getLogicalNOT.
Definition at line 3260 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::getBooleanContents(), llvm::SelectionDAG::getLogicalNOT(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::ISD::XOR, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
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Helper function for visitOR to extract the needed side of a rotate idiom from a shl/srl/mul/udiv.
This is meant to handle cases where InstCombine merged some outside op with one of the shifts from the rotate pattern.
SDValue if the needed shift couldn't be extracted. Otherwise, returns an expansion of ExtractFrom based on the following patterns:(or (add v v) (shrl v bitwidth-1)): expands (add v v) -> (shl v 1)
(or (mul v c0) (shrl (mul v c1) c2)): expands (mul v c0) -> (shl (mul v c1) c3)
(or (udiv v c0) (shl (udiv v c1) c2)): expands (udiv v c0) -> (shrl (udiv v c1) c3)
(or (shl v c0) (shrl (shl v c1) c2)): expands (shl v c0) -> (shl (shl v c1) c3)
(or (shrl v c0) (shl (shrl v c1) c2)): expands (shrl v c0) -> (shrl (shrl v c1) c3)
Such that in all cases, c3+c2==bitwidth(op v c1).
Definition at line 8046 of file DAGCombiner.cpp.
References llvm::ISD::ADD, assert(), llvm::ISD::DELETED_NODE, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::APInt::getZExtValue(), llvm::isConstOrConstSplat(), llvm::ISD::MUL, Opcode, llvm::ISD::SHL, llvm::ISD::SRL, stripConstantMask(), llvm::ISD::UDIV, llvm::APInt::udivrem(), llvm::APInt::ugt(), zeroExtendToMatch(), and llvm::APInt::zextOrTrunc().
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Definition at line 2615 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::CallingConv::C, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), llvm::isOneConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.
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Given the operands of an add/sub operation, see if the 2nd operand is a masked 0/1 whose source operand is actually known to be 0/-1.
If so, invert the opcode and bypass the mask operation.
Definition at line 3107 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::SelectionDAG::ComputeNumSignBits(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isOneOrOneSplat(), llvm::ISD::SUB, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
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Try to fold a 'not' shifted sign-bit with add/sub with constant operand into a shift and add with a different constant.
Definition at line 2656 of file DAGCombiner.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::FoldConstantArithmetic(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isBitwiseNot(), llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt(), llvm::isConstOrConstSplat(), N, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.
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Definition at line 6133 of file DAGCombiner.cpp.
References llvm::ISD::ABS, llvm::TargetLoweringBase::ABS, llvm::ISD::ADD, llvm::TargetLoweringBase::AddAnd, llvm::ISD::AND, assert(), llvm::CallingConv::C, CC, llvm::ISD::DELETED_NODE, DL, llvm::SelectionDAG::doesNodeExist(), llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::SelectionDAG::getConstant(), getMinMaxOpcodeForFP(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::Value::hasOneUse(), llvm::APInt::isAllOnes(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstOrConstSplat(), llvm::TargetLowering::isDesirableToCombineLogicOpOfSETCC(), llvm::EVT::isFloatingPoint(), llvm::ISD::isFPEqualitySetCC(), llvm::EVT::isInteger(), llvm::ISD::isIntEqualitySetCC(), llvm::APInt::isNegative(), llvm::isNullOrNullSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::APInt::isPowerOf2(), llvm::APInt::isZero(), LHS, llvm::TargetLoweringBase::None, llvm::TargetLoweringBase::NotAnd, llvm::ISD::OR, RHS, llvm::ISD::SETCC, llvm::ISD::SETCC_INVALID, llvm::ISD::SETEQ, llvm::ISD::SETFALSE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETTRUE, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::APIntOps::smax(), llvm::ISD::SMAX, llvm::APIntOps::smin(), llvm::ISD::SMIN, llvm::ISD::UMAX, and llvm::ISD::UMIN.
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For targets that support usubsat, match a bit-hack form of that operation that ends in 'and' and convert it.
Definition at line 6817 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::BitWidth, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isConstOrConstSplat(), llvm::APInt::isSignMask(), N, llvm::ISD::SRA, std::swap(), llvm::ISD::USUBSAT, and llvm::ISD::XOR.
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Definition at line 10236 of file DAGCombiner.cpp.
References llvm::ISD::BITREVERSE, llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), N, and Opcode.
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Definition at line 11404 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), Cond, F, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getScalarSizeInBits(), llvm::isNullOrNullSplat(), llvm::isOneOrOneSplat(), N, llvm::ISD::OR, llvm::ISD::SELECT, and llvm::ISD::VSELECT.
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Definition at line 13179 of file DAGCombiner.cpp.
References assert(), CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), N, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::TargetLoweringBase::shouldAvoidTransformToShift(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::ISD::SRL, X, and llvm::ISD::ZERO_EXTEND.
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Definition at line 14580 of file DAGCombiner.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getOpcode_EXTEND(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isExtVecInRegOpcode(), llvm::TargetLoweringBase::isOperationLegal(), N, and Opcode.
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Given EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(Op0, Op1, Mask)), try to produce VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(Op?, ?), EXTRACT_SUBVECTOR(Op?, ?), Mask')) iff it is legal and profitable to do so.
Notably, the trimmed mask (containing only the elements that are extracted) must reference at most two subvectors.
Definition at line 24214 of file DAGCombiner.cpp.
References llvm::any_of(), assert(), DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::ISD::EXTRACT_SUBVECTOR, getFirstIndexOf(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::EVT::isFixedLengthVector(), llvm::ShuffleVectorInst::isIdentityMask(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isShuffleMaskLegal(), N, llvm::SmallVectorImpl< T >::reserve(), llvm::SmallVectorBase< Size_T >::size(), and llvm::ISD::VECTOR_SHUFFLE.
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Definition at line 17324 of file DAGCombiner.cpp.
References llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FTRUNC, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTarget(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isOperationLegal(), N, llvm::TargetOptions::NoSignedZerosFPMath, llvm::TargetMachine::Options, llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.
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Definition at line 17443 of file DAGCombiner.cpp.
References llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), N, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
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Given a bitwise logic operation N with a matching bitwise logic operand, fold a pattern where 2 of the source operands are identically shifted values.
For example: ((X0 << Y) | Z) | (X1 << Y) --> ((X0 | X1) << Y) | Z
Definition at line 6852 of file DAGCombiner.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and Y.
Referenced by foldLogicTreeOfShifts(), and visitORCommutative().
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Given a tree of logic operations with shape like (LOGIC (LOGIC (X, Y), LOGIC (Z, Y))) try to match and fold shift operations with the same shift amount.
For example: LOGIC (LOGIC (SH X0, Y), Z), (LOGIC (SH X1, Y), W) --> --> LOGIC (SH (LOGIC X0, X1), Y), (LOGIC Z, W)
Definition at line 6900 of file DAGCombiner.cpp.
References assert(), DL, foldLogicOfShifts(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::isBitwiseLogicOp(), and N.
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If a (v)select has a condition value that is a sign-bit test, try to smear the condition operand sign-bit across the value width and use it as a mask.
Definition at line 11231 of file DAGCombiner.cpp.
References llvm::ISD::AND, CC, Cond, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isAllOnesOrAllOnesSplat(), llvm::isConstantOrConstantVector(), llvm::isNullOrNullSplat(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SRA, and X.
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This inverts a canonicalization in IR that replaces a variable select arm with an identity constant.
Codegen improves if we re-use the variable operand rather than load a constant. This can also be converted into a masked vector operation if the target supports it.
Definition at line 2470 of file DAGCombiner.cpp.
References Cond, llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::hasOneUse(), llvm::isNeutralConstant(), llvm::SelectionDAG::isSafeToSpeculativelyExecuteNode(), N, Opcode, std::swap(), and llvm::ISD::VSELECT.
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Try to convert a wide shuffle of concatenated vectors into 2 narrow shuffles followed by concatenation.
Narrow vector ops may have better performance than wide ops, and this can unlock further narrowing of other vector ops. Targets can invert this transform later if it is not profitable.
Definition at line 24558 of file DAGCombiner.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), X, and Y.
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Definition at line 11438 of file DAGCombiner.cpp.
References llvm::ISD::AND, CC, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::hasAndNot(), llvm::SDValue::hasOneUse(), llvm::isAllOnesOrAllOnesSplat(), llvm::isNullOrNullSplat(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SRA, and std::swap().
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Combine shuffle of shuffle of the form: shuf (shuf X, undef, InnerMask), undef, OuterMask --> splat X.
Definition at line 25178 of file DAGCombiner.cpp.
References llvm::all_of(), assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::getSplatIndex(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isShuffleMaskLegal(), llvm::SDValue::isUndef(), and llvm::ArrayRef< T >::size().
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Definition at line 3055 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::TargetLoweringBase::getBooleanContents(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, llvm::ISD::USUBO, llvm::ISD::USUBO_CARRY, llvm::ISD::ZERO_EXTEND, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.
Referenced by combineCarryDiamond().
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If N is a ConstantSDNode with isOpaque() == false return it casted to a ConstantSDNode pointer else nullptr.
Definition at line 2370 of file DAGCombiner.cpp.
References N.
Definition at line 14980 of file DAGCombiner.cpp.
References llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::ISD::MERGE_VALUES, and N.
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Definition at line 18034 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::isIndexedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedLoadLegal(), llvm::TargetLoweringBase::isIndexedMaskedStoreLegal(), llvm::TargetLoweringBase::isIndexedStoreLegal(), N, and Ptr.
Referenced by getPostIndexedLoadStoreOp(), and shouldCombineToPostInc().
Definition at line 22905 of file DAGCombiner.cpp.
References llvm::find(), and I.
Referenced by foldExtractSubvectorFromShuffleVector().
Given a node, return its input chain if it has one, otherwise return a null sd operand.
Definition at line 2147 of file DAGCombiner.cpp.
References N.
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Definition at line 6077 of file DAGCombiner.cpp.
References llvm::ISD::AND, arebothOperandsNotNan(), arebothOperandsNotSNan(), CC, llvm::ISD::DELETED_NODE, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::OR, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by foldAndOrOfSETCC().
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Definition at line 18349 of file DAGCombiner.cpp.
References getCombineLoadStoreParts(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), N, llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, Ptr, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and shouldCombineToPostInc().
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Definition at line 15019 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getDataLayout(), and llvm::DataLayout::isBigEndian().
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If the shuffle mask is taking exactly one element from the first vector operand and passing through all other elements from the second vector operand, return the index of the mask element that is choosing an element from the first operand.
Otherwise, return -1.
Definition at line 25231 of file DAGCombiner.cpp.
Referenced by replaceShuffleOfInsert().
Definition at line 23969 of file DAGCombiner.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::EVT::getVectorMinNumElements(), and llvm::ISD::INSERT_SUBVECTOR.
Referenced by narrowInsertExtractVectorBinOp().
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Definition at line 3702 of file DAGCombiner.cpp.
References assert(), DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::TRUNCATE, llvm::ISD::UMIN, and llvm::ISD::USUBSAT.
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Definition at line 15527 of file DAGCombiner.cpp.
Referenced by llvm::SDNode::print_details().
Definition at line 1181 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), and llvm::isConstantOrConstantVector().
Referenced by combineShuffleOfBitcast(), combineShuffleOfScalars(), and scalarizeExtractedBinop().
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Definition at line 8808 of file DAGCombiner.cpp.
References assert(), bigEndianByteAt(), littleEndianByteAt(), and llvm::ArrayRef< T >::size().
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Return true if the specified node is an element that makes up a 32-bit packed halfword byteswap.
((x & 0x000000ff) << 8) | ((x & 0x0000ff00) >> 8) | ((x & 0x00ff0000) << 8) | ((x & 0xff000000) >> 8)
Definition at line 7473 of file DAGCombiner.cpp.
References llvm::ISD::AND, llvm::CallingConv::C, llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by isBSwapHWordPair().
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Definition at line 7558 of file DAGCombiner.cpp.
References llvm::ISD::BSWAP, llvm::CallingConv::C, isBSwapHWordElement(), llvm::isConstOrConstSplat(), N, llvm::ISD::OR, and llvm::ISD::SRL.
Check if N satisfies: N is used once.
N is a Load. The load is compatible with ExtOpcode. It means If load has explicit zero/sign extension, ExpOpcode must have the same extension. Otherwise returns true.
Definition at line 12617 of file DAGCombiner.cpp.
References llvm::ISD::EXTLOAD, N, llvm::ISD::NON_EXTLOAD, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
Referenced by tryToFoldExtendSelectLoad().
Definition at line 1162 of file DAGCombiner.cpp.
References llvm::BitWidth, llvm::ISD::BUILD_VECTOR, N, and llvm::ISD::SPLAT_VECTOR.
Definition at line 1132 of file DAGCombiner.cpp.
References llvm::APInt::getLimitedValue(), llvm::EVT::getSimpleVT(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isSimple(), N, and llvm::MVT::SimpleTy.
Referenced by performSVEAndCombine().
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Definition at line 15519 of file DAGCombiner.cpp.
References assert(), llvm::FPOpFusion::Fast, llvm::ISD::FMUL, N, and Options.
Definition at line 4785 of file DAGCombiner.cpp.
References llvm::CallingConv::C, and llvm::ISD::matchUnaryPredicate().
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Return true if divmod libcall is available.
Definition at line 4589 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::getLibcallName(), and isSigned().
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Definition at line 11132 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getTarget(), llvm::EVT::isFloatingPoint(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::TargetLoweringBase::isProfitableToCombineMinNumMaxNum(), LHS, llvm::TargetMachine::Options, Options, and RHS.
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Definition at line 5503 of file DAGCombiner.cpp.
References CC, llvm::APInt::exactLogBase2(), llvm::ISD::FP_TO_SINT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getContext(), llvm::Type::getFltSemantics(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getScalarValueSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::isConstOrConstSplat(), llvm::isNullOrNullSplat(), llvm::APInt::isPowerOf2(), llvm::EVT::isSimple(), llvm::peekThroughTruncates(), llvm::PowerOf2Ceil(), llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::APFloatBase::semanticsIntSizeInBits(), llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::APInt::sext(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::APInt::trunc(), llvm::ISD::TRUNCATE, Unsigned, and llvm::ISD::VSELECT.
Referenced by PerformMinMaxFpToSatCombine().
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Check the profitability of all involved LoadedSlice.
Currently, it is considered profitable if there is exactly two involved slices (1) which are (2) next to each other in memory, and whose cost (
Note: The order of the elements in LoadedSlices may be modified, but not the elements themselves.
FIXME: When the cost model will be mature enough, we can relax constraints (1) and (2).
Definition at line 19224 of file DAGCombiner.cpp.
References adjustCostForPairing(), areUsedBitsDense(), llvm::SmallVectorBase< Size_T >::size(), and StressLoadSlicing.
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Definition at line 2379 of file DAGCombiner.cpp.
References assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SDValue::getValueType(), llvm::KnownBits::isAllOnes(), llvm::isNullOrNullSplat(), N, llvm::ISD::SETCC, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::KnownBits::Zero.
Definition at line 8797 of file DAGCombiner.cpp.
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Definition at line 7578 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::BSWAP, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), N, llvm::ISD::OR, llvm::ISD::ROTR, llvm::ISD::SHL, and llvm::ISD::SRL.
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Match "(X shl/srl V1) & V2" where V2 may not be present.
Definition at line 8012 of file DAGCombiner.cpp.
References llvm::ISD::SHL, llvm::ISD::SRL, and stripConstantMask().
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Definition at line 8164 of file DAGCombiner.cpp.
References llvm::ISD::ADD, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isConstOrConstSplat(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::TargetLowering::SimplifyMultipleUseDemandedBits(), llvm::ISD::SUB, and llvm::ISD::TRUNCATE.
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Definition at line 21432 of file DAGCombiner.cpp.
References assert(), llvm::SmallVectorImpl< T >::assign(), llvm::ISD::CONCAT_VECTORS, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorBase< Size_T >::empty(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::ops(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::reverse(), X, and Y.
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If we are extracting a subvector produced by a wide binary operator try to use a narrow binary operator and/or avoid concatenation and extraction.
Definition at line 24021 of file DAGCombiner.cpp.
References llvm::ISD::AND, assert(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::TargetLoweringBase::isBinOp(), llvm::isConstOrConstSplatFP(), llvm::TargetLoweringBase::isExtractSubvectorCheap(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), narrowInsertExtractVectorBinOp(), llvm::ISD::OR, llvm::peekThroughBitcasts(), X, llvm::ISD::XOR, and Y.
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If we are extracting a subvector from a wide vector load, convert to a narrow load to eliminate the extraction: (extract_subvector (load wide vector)) --> (load narrow vector)
Definition at line 24153 of file DAGCombiner.cpp.
References assert(), DL, llvm::MachinePointerInfo::getAddrSpace(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::MemSDNode::getMemOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::MemoryLocation::getSizeOrUnknown(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::DataLayout::isBigEndian(), llvm::EVT::isByteSized(), llvm::MemSDNode::isSimple(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::Offset, and llvm::TargetLoweringBase::shouldReduceLoadWidth().
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Definition at line 23984 of file DAGCombiner.cpp.
References llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getSubVectorSrc(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::isBinOp(), and llvm::TargetLoweringBase::isOperationLegalOrCustom().
Referenced by narrowExtractedVectorBinOp().
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Definition at line 18462 of file DAGCombiner.cpp.
References llvm::ElementCount::getFixed().
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Definition at line 24606 of file DAGCombiner.cpp.
References llvm::all_of(), assert(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::SDValue::isUndef(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 5606 of file DAGCombiner.cpp.
References CC, DL, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT_SAT, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtOrTrunc(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), isSaturatingMinMax(), llvm::EVT::isVector(), llvm::TargetLoweringBase::shouldConvertFpToSat(), and Unsigned.
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Definition at line 5628 of file DAGCombiner.cpp.
References CC, llvm::ISD::FP_TO_UINT, llvm::ISD::FP_TO_UINT_SAT, llvm::ConstantSDNode::getAPIntValue(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isConstOrConstSplat(), llvm::EVT::isVector(), llvm::ISD::SETULT, llvm::TargetLoweringBase::shouldConvertFpToSat(), llvm::ISD::TRUNCATE, and llvm::APInt::zext().
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Definition at line 22827 of file DAGCombiner.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::buildLegalVectorShuffle(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::DataLayout::isBigEndian(), llvm::Low, and llvm::ISD::ZERO_EXTEND.
| bool refineIndexType | ( | SDValue & | Index, |
| ISD::MemIndexType & | IndexType, | ||
| EVT | DataVT, | ||
| SelectionDAG & | DAG | ||
| ) |
Definition at line 11766 of file DAGCombiner.cpp.
References llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isIndexTypeSigned(), llvm::TargetLoweringBase::shouldRemoveExtendFromGSIndex(), llvm::ISD::SIGN_EXTEND, llvm::ISD::UNSIGNED_SCALED, and llvm::ISD::ZERO_EXTEND.
| bool refineUniformBase | ( | SDValue & | BasePtr, |
| SDValue & | Index, | ||
| bool | IndexIsScaled, | ||
| SelectionDAG & | DAG, | ||
| const SDLoc & | DL | ||
| ) |
Definition at line 11727 of file DAGCombiner.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatValue(), llvm::SDValue::getValueType(), and llvm::isNullConstant().
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If a shuffle inserts exactly one element from a source vector operand into another vector operand and we can access the specified element as a scalar, then we can eliminate the shuffle.
Definition at line 25255 of file DAGCombiner.cpp.
References assert(), llvm::ShuffleVectorSDNode::commuteMask(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getShuffleMaskIndexOfOneElementFromOp0IntoOp1(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::ISD::INSERT_VECTOR_ELT, and std::swap().
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If a vector binop is performed on splat values, it may be profitable to extract, scalarize, and insert/splat.
Definition at line 26568 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::count_if(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatSourceVector(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::TargetLoweringBase::isExtractVecEltCheap(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), N, Opcode, llvm::SDNode::ops(), llvm::ISD::SPLAT_VECTOR, X, and Y.
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Transform a vector binary operation into a scalar binary operation by moving the math/logic after an extract element of a vector.
Definition at line 21963 of file DAGCombiner.cpp.
References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), isAnyConstantBuildVector(), llvm::TargetLoweringBase::isBinOp(), llvm::ISD::isConstantSplatVector(), and llvm::TargetLoweringBase::shouldScalarizeBinop().
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Definition at line 18300 of file DAGCombiner.cpp.
References llvm::ISD::ADD, canFoldInAddressingMode(), getCombineLoadStoreParts(), llvm::SDNode::getOpcode(), llvm::TargetLowering::getPostIndexedAddressParts(), llvm::SDNode::hasPredecessorHelper(), llvm::isNullConstant(), N, llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, Ptr, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SUB, and llvm::Value::uses().
Referenced by getPostIndexedLoadStoreOp().
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Definition at line 11266 of file DAGCombiner.cpp.
References CC, Cond, llvm::TargetLoweringBase::convertSelectOfConstantsToMath(), llvm::isAllOnesOrAllOnesSplat(), llvm::isNullOrNullSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, and llvm::ISD::SETLT.
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Check to see if IVal is something that provides a value as specified by MaskInfo.
If so, replace the specified store with a narrower store of truncated IVal.
Definition at line 19437 of file DAGCombiner.cpp.
References llvm::TargetLoweringBase::allowsMemoryAccess(), DL, llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::TypeSize::getFixed(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::MachinePointerInfo::getWithOffset(), llvm::LSBaseSDNode::isIndexed(), llvm::DataLayout::isLittleEndian(), llvm::TargetLoweringBase::isTruncStoreLegal(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SelectionDAG::MaskedValueIsZero(), Ptr, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
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Definition at line 4676 of file DAGCombiner.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getUNDEF(), llvm::isConstOrConstSplat(), llvm::ConstantSDNode::isOne(), llvm::SDValue::isUndef(), llvm::SelectionDAG::isUndef(), llvm::ConstantSDNode::isZero(), N, llvm::ISD::SDIV, and llvm::ISD::UDIV.
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If we have a unary shuffle of a shuffle, see if it can be folded away completely.
This has the potential to lose undef knowledge because the first shuffle may not have an undef mask element where the second one does. So only call this after doing simplifications based on demanded elements.
Definition at line 25308 of file DAGCombiner.cpp.
References assert(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), and llvm::SDValue::isUndef().
| STATISTIC | ( | LdStFP2Int | , |
| "Number of fp load/store pairs transformed to int" | |||
| ) |
| STATISTIC | ( | NodesCombined | , |
| "Number of dag nodes combined" | |||
| ) |
| STATISTIC | ( | NumFPLogicOpsConv | , |
| "Number of logic ops converted to fp ops" | |||
| ) |
| STATISTIC | ( | OpsNarrowed | , |
| "Number of load/op/store narrowed" | |||
| ) |
| STATISTIC | ( | PostIndexedNodes | , |
| "Number of post-indexed nodes created" | |||
| ) |
| STATISTIC | ( | PreIndexedNodes | , |
| "Number of pre-indexed nodes created" | |||
| ) |
| STATISTIC | ( | SlicedLoads | , |
| "Number of load sliced" | |||
| ) |
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Definition at line 8001 of file DAGCombiner.cpp.
References llvm::ISD::AND, and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().
Referenced by extractShiftForRotate(), and matchRotateHalf().
Definition at line 8829 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::SIGN_EXTEND, stripTruncAndExt(), llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by stripTruncAndExt().
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Definition at line 27479 of file DAGCombiner.cpp.
References llvm::ISD::ADD, assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::CallingConv::C, llvm::Depth, DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::EVT::isScalableVector(), llvm::EVT::isVector(), llvm::ISD::matchUnaryPredicate(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::SELECT, llvm::ISD::SHL, takeInexpensiveLog2(), llvm::ISD::TRUNCATE, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
Referenced by takeInexpensiveLog2().
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Definition at line 3778 of file DAGCombiner.cpp.
References llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getConstant(), llvm::TargetLoweringBase::isOperationLegal(), and llvm::EVT::isVector().
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Try to fold a sext/zext/aext dag node into a ConstantSDNode or a build_vector of constants.
This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND). Vector extends are not folded if operations are legal; this is to avoid introducing illegal build_vector dag nodes.
Definition at line 12692 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::ANY_EXTEND_VECTOR_INREG, assert(), llvm::CallingConv::C, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isExtOpcode(), llvm::ISD::isExtVecInRegOpcode(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isZExtFree(), N, Opcode, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SELECT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_VECTOR_INREG, and llvm::ISD::ZERO_EXTEND.
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Fold (sext (select c, load x, load y)) -> (select c, sextload x, sextload y) (zext (select c, load x, load y)) -> (select c, zextload x, zextload y) (aext (select c, load x, load y)) -> (select c, extload x, extload y) This function is called by the DAGCombiner when visiting sext/zext/aext dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
Definition at line 12644 of file DAGCombiner.cpp.
References llvm::AfterLegalizeTypes, llvm::ISD::ANY_EXTEND, assert(), DL, llvm::ISD::EXTLOAD, llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getOperationAction(), llvm::SelectionDAG::getSelect(), llvm::SDValue::hasOneUse(), isCompatibleLoad(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::TargetLoweringBase::Legal, N, Opcode, llvm::ISD::SELECT, llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::ISD::VSELECT, llvm::ISD::ZERO_EXTEND, and llvm::ISD::ZEXTLOAD.
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Definition at line 13077 of file DAGCombiner.cpp.
References llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getValue(), llvm::SDValue::hasOneUse(), llvm::ISD::isEXTLoad(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isSEXTLoad(), llvm::MemSDNode::isSimple(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::ISD::isZEXTLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, and llvm::SDNode::use_empty().
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Definition at line 13108 of file DAGCombiner.cpp.
References ExtendUsesToFormExtLoad(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isLoadExtLegal(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isUNINDEXEDLoad(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ISD::TRUNCATE.
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Definition at line 13152 of file DAGCombiner.cpp.
References llvm::MaskedLoadStoreSDNode::getAddressingMode(), llvm::MaskedLoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MaskedLoadSDNode::getExtensionType(), llvm::MaskedLoadSDNode::getMask(), llvm::SelectionDAG::getMaskedLoad(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::MaskedLoadSDNode::getOffset(), llvm::MaskedLoadSDNode::getPassThru(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::MaskedLoadSDNode::isExpandingLoad(), llvm::TargetLoweringBase::isLoadExtLegalOrCustom(), isSimple(), llvm::TargetLoweringBase::isVectorLoadExtDesirable(), N, llvm::ISD::NON_EXTLOAD, and llvm::SelectionDAG::ReplaceAllUsesOfValueWith().
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OR combines for which the commuted variant will be tried as well.
Definition at line 7739 of file DAGCombiner.cpp.
References llvm::ISD::AND, foldLogicOfShifts(), llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::getBitwiseNotOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), N, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
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Definition at line 13584 of file DAGCombiner.cpp.
References llvm::ISD::ABS, assert(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTypeAction(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), llvm::ISD::SIGN_EXTEND, llvm::TargetLoweringBase::TypePromoteInteger, and llvm::ISD::ZERO_EXTEND.
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Given an extending node with a pop-count operand, if the target does not support a pop-count in the narrow source type but does support it in the destination type, widen the pop-count to the destination type.
Definition at line 13562 of file DAGCombiner.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), and llvm::ISD::ZERO_EXTEND.
Definition at line 1079 of file DAGCombiner.cpp.
References LHS, llvm::Offset, and RHS.
Referenced by extractShiftForRotate().
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Referenced by CanCombineFCOPYSIGN_EXTEND_ROUND().
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Referenced by canSplitIdx().
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Hidden option to stress test load slicing, i.e., when this option is enabled, load slicing bypasses most of its profitability guards.
Referenced by isSlicingProfitable().
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1.9.6