LLVM  14.0.0git
StackMaps.cpp
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1 //===- StackMaps.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "llvm/ADT/DenseMapInfo.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/ADT/Twine.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Support/Debug.h"
32 #include <algorithm>
33 #include <cassert>
34 #include <cstdint>
35 #include <iterator>
36 #include <utility>
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "stackmaps"
41 
43  "stackmap-version", cl::init(3), cl::Hidden,
44  cl::desc("Specify the stackmap encoding version (default = 3)"));
45 
46 const char *StackMaps::WSMP = "Stack Maps: ";
47 
48 static uint64_t getConstMetaVal(const MachineInstr &MI, unsigned Idx) {
49  assert(MI.getOperand(Idx).isImm() &&
50  MI.getOperand(Idx).getImm() == StackMaps::ConstantOp);
51  const auto &MO = MI.getOperand(Idx + 1);
52  assert(MO.isImm());
53  return MO.getImm();
54 }
55 
57  : MI(MI) {
58  assert(getVarIdx() <= MI->getNumOperands() &&
59  "invalid stackmap definition");
60 }
61 
63  : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
64  !MI->getOperand(0).isImplicit()) {
65 #ifndef NDEBUG
66  unsigned CheckStartIdx = 0, e = MI->getNumOperands();
67  while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
68  MI->getOperand(CheckStartIdx).isDef() &&
69  !MI->getOperand(CheckStartIdx).isImplicit())
70  ++CheckStartIdx;
71 
72  assert(getMetaIdx() == CheckStartIdx &&
73  "Unexpected additional definition in Patchpoint intrinsic.");
74 #endif
75 }
76 
77 unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
78  if (!StartIdx)
79  StartIdx = getVarIdx();
80 
81  // Find the next scratch register (implicit def and early clobber)
82  unsigned ScratchIdx = StartIdx, e = MI->getNumOperands();
83  while (ScratchIdx < e &&
84  !(MI->getOperand(ScratchIdx).isReg() &&
85  MI->getOperand(ScratchIdx).isDef() &&
86  MI->getOperand(ScratchIdx).isImplicit() &&
87  MI->getOperand(ScratchIdx).isEarlyClobber()))
88  ++ScratchIdx;
89 
90  assert(ScratchIdx != e && "No scratch register available");
91  return ScratchIdx;
92 }
93 
95  // Take index of num of allocas and skip all allocas records.
96  unsigned CurIdx = getNumAllocaIdx();
97  unsigned NumAllocas = getConstMetaVal(*MI, CurIdx - 1);
98  CurIdx++;
99  while (NumAllocas--)
100  CurIdx = StackMaps::getNextMetaArgIdx(MI, CurIdx);
101  return CurIdx + 1; // skip <StackMaps::ConstantOp>
102 }
103 
105  // Take index of num of gc ptrs and skip all gc ptr records.
106  unsigned CurIdx = getNumGCPtrIdx();
107  unsigned NumGCPtrs = getConstMetaVal(*MI, CurIdx - 1);
108  CurIdx++;
109  while (NumGCPtrs--)
110  CurIdx = StackMaps::getNextMetaArgIdx(MI, CurIdx);
111  return CurIdx + 1; // skip <StackMaps::ConstantOp>
112 }
113 
115  // Take index of num of deopt args and skip all deopt records.
116  unsigned CurIdx = getNumDeoptArgsIdx();
117  unsigned NumDeoptArgs = getConstMetaVal(*MI, CurIdx - 1);
118  CurIdx++;
119  while (NumDeoptArgs--) {
120  CurIdx = StackMaps::getNextMetaArgIdx(MI, CurIdx);
121  }
122  return CurIdx + 1; // skip <StackMaps::ConstantOp>
123 }
124 
126  unsigned NumGCPtrsIdx = getNumGCPtrIdx();
127  unsigned NumGCPtrs = getConstMetaVal(*MI, NumGCPtrsIdx - 1);
128  if (NumGCPtrs == 0)
129  return -1;
130  ++NumGCPtrsIdx; // skip <num gc ptrs>
131  assert(NumGCPtrsIdx < MI->getNumOperands());
132  return (int)NumGCPtrsIdx;
133 }
134 
136  SmallVectorImpl<std::pair<unsigned, unsigned>> &GCMap) {
137  unsigned CurIdx = getNumGcMapEntriesIdx();
138  unsigned GCMapSize = getConstMetaVal(*MI, CurIdx - 1);
139  CurIdx++;
140  for (unsigned N = 0; N < GCMapSize; ++N) {
141  unsigned B = MI->getOperand(CurIdx++).getImm();
142  unsigned D = MI->getOperand(CurIdx++).getImm();
143  GCMap.push_back(std::make_pair(B, D));
144  }
145 
146  return GCMapSize;
147 }
148 
150  if (StackMapVersion != 3)
151  llvm_unreachable("Unsupported stackmap version!");
152 }
153 
154 unsigned StackMaps::getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx) {
155  assert(CurIdx < MI->getNumOperands() && "Bad meta arg index");
156  const auto &MO = MI->getOperand(CurIdx);
157  if (MO.isImm()) {
158  switch (MO.getImm()) {
159  default:
160  llvm_unreachable("Unrecognized operand type.");
161  case StackMaps::DirectMemRefOp:
162  CurIdx += 2;
163  break;
164  case StackMaps::IndirectMemRefOp:
165  CurIdx += 3;
166  break;
167  case StackMaps::ConstantOp:
168  ++CurIdx;
169  break;
170  }
171  }
172  ++CurIdx;
173  assert(CurIdx < MI->getNumOperands() && "points past operand list");
174  return CurIdx;
175 }
176 
177 /// Go up the super-register chain until we hit a valid dwarf register number.
178 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
179  int RegNum = TRI->getDwarfRegNum(Reg, false);
180  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
181  RegNum = TRI->getDwarfRegNum(*SR, false);
182 
183  assert(RegNum >= 0 && "Invalid Dwarf register number.");
184  return (unsigned)RegNum;
185 }
186 
188 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
189  MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
190  LiveOutVec &LiveOuts) const {
192  if (MOI->isImm()) {
193  switch (MOI->getImm()) {
194  default:
195  llvm_unreachable("Unrecognized operand type.");
196  case StackMaps::DirectMemRefOp: {
197  auto &DL = AP.MF->getDataLayout();
198 
199  unsigned Size = DL.getPointerSizeInBits();
200  assert((Size % 8) == 0 && "Need pointer size in bytes.");
201  Size /= 8;
202  Register Reg = (++MOI)->getReg();
203  int64_t Imm = (++MOI)->getImm();
204  Locs.emplace_back(StackMaps::Location::Direct, Size,
205  getDwarfRegNum(Reg, TRI), Imm);
206  break;
207  }
208  case StackMaps::IndirectMemRefOp: {
209  int64_t Size = (++MOI)->getImm();
210  assert(Size > 0 && "Need a valid size for indirect memory locations.");
211  Register Reg = (++MOI)->getReg();
212  int64_t Imm = (++MOI)->getImm();
213  Locs.emplace_back(StackMaps::Location::Indirect, Size,
214  getDwarfRegNum(Reg, TRI), Imm);
215  break;
216  }
217  case StackMaps::ConstantOp: {
218  ++MOI;
219  assert(MOI->isImm() && "Expected constant operand.");
220  int64_t Imm = MOI->getImm();
221  Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, Imm);
222  break;
223  }
224  }
225  return ++MOI;
226  }
227 
228  // The physical register number will ultimately be encoded as a DWARF regno.
229  // The stack map also records the size of a spill slot that can hold the
230  // register content. (The runtime can track the actual size of the data type
231  // if it needs to.)
232  if (MOI->isReg()) {
233  // Skip implicit registers (this includes our scratch registers)
234  if (MOI->isImplicit())
235  return ++MOI;
236 
237  if (MOI->isUndef()) {
238  // Record `undef` register as constant. Use same value as ISel uses.
239  Locs.emplace_back(Location::Constant, sizeof(int64_t), 0, 0xFEFEFEFE);
240  return ++MOI;
241  }
242 
244  "Virtreg operands should have been rewritten before now.");
246  assert(!MOI->getSubReg() && "Physical subreg still around.");
247 
248  unsigned Offset = 0;
249  unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI);
250  unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false);
251  unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
252  if (SubRegIdx)
253  Offset = TRI->getSubRegIdxOffset(SubRegIdx);
254 
255  Locs.emplace_back(Location::Register, TRI->getSpillSize(*RC),
256  DwarfRegNum, Offset);
257  return ++MOI;
258  }
259 
260  if (MOI->isRegLiveOut())
261  LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
262 
263  return ++MOI;
264 }
265 
266 void StackMaps::print(raw_ostream &OS) {
267  const TargetRegisterInfo *TRI =
268  AP.MF ? AP.MF->getSubtarget().getRegisterInfo() : nullptr;
269  OS << WSMP << "callsites:\n";
270  for (const auto &CSI : CSInfos) {
271  const LocationVec &CSLocs = CSI.Locations;
272  const LiveOutVec &LiveOuts = CSI.LiveOuts;
273 
274  OS << WSMP << "callsite " << CSI.ID << "\n";
275  OS << WSMP << " has " << CSLocs.size() << " locations\n";
276 
277  unsigned Idx = 0;
278  for (const auto &Loc : CSLocs) {
279  OS << WSMP << "\t\tLoc " << Idx << ": ";
280  switch (Loc.Type) {
282  OS << "<Unprocessed operand>";
283  break;
284  case Location::Register:
285  OS << "Register ";
286  if (TRI)
287  OS << printReg(Loc.Reg, TRI);
288  else
289  OS << Loc.Reg;
290  break;
291  case Location::Direct:
292  OS << "Direct ";
293  if (TRI)
294  OS << printReg(Loc.Reg, TRI);
295  else
296  OS << Loc.Reg;
297  if (Loc.Offset)
298  OS << " + " << Loc.Offset;
299  break;
300  case Location::Indirect:
301  OS << "Indirect ";
302  if (TRI)
303  OS << printReg(Loc.Reg, TRI);
304  else
305  OS << Loc.Reg;
306  OS << "+" << Loc.Offset;
307  break;
308  case Location::Constant:
309  OS << "Constant " << Loc.Offset;
310  break;
312  OS << "Constant Index " << Loc.Offset;
313  break;
314  }
315  OS << "\t[encoding: .byte " << Loc.Type << ", .byte 0"
316  << ", .short " << Loc.Size << ", .short " << Loc.Reg << ", .short 0"
317  << ", .int " << Loc.Offset << "]\n";
318  Idx++;
319  }
320 
321  OS << WSMP << "\thas " << LiveOuts.size() << " live-out registers\n";
322 
323  Idx = 0;
324  for (const auto &LO : LiveOuts) {
325  OS << WSMP << "\t\tLO " << Idx << ": ";
326  if (TRI)
327  OS << printReg(LO.Reg, TRI);
328  else
329  OS << LO.Reg;
330  OS << "\t[encoding: .short " << LO.DwarfRegNum << ", .byte 0, .byte "
331  << LO.Size << "]\n";
332  Idx++;
333  }
334  }
335 }
336 
337 /// Create a live-out register record for the given register Reg.
339 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
340  unsigned DwarfRegNum = getDwarfRegNum(Reg, TRI);
342  return LiveOutReg(Reg, DwarfRegNum, Size);
343 }
344 
345 /// Parse the register live-out mask and return a vector of live-out registers
346 /// that need to be recorded in the stackmap.
348 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
349  assert(Mask && "No register mask specified");
351  LiveOutVec LiveOuts;
352 
353  // Create a LiveOutReg for each bit that is set in the register mask.
354  for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
355  if ((Mask[Reg / 32] >> (Reg % 32)) & 1)
356  LiveOuts.push_back(createLiveOutReg(Reg, TRI));
357 
358  // We don't need to keep track of a register if its super-register is already
359  // in the list. Merge entries that refer to the same dwarf register and use
360  // the maximum size that needs to be spilled.
361 
362  llvm::sort(LiveOuts, [](const LiveOutReg &LHS, const LiveOutReg &RHS) {
363  // Only sort by the dwarf register number.
364  return LHS.DwarfRegNum < RHS.DwarfRegNum;
365  });
366 
367  for (auto I = LiveOuts.begin(), E = LiveOuts.end(); I != E; ++I) {
368  for (auto II = std::next(I); II != E; ++II) {
369  if (I->DwarfRegNum != II->DwarfRegNum) {
370  // Skip all the now invalid entries.
371  I = --II;
372  break;
373  }
374  I->Size = std::max(I->Size, II->Size);
375  if (TRI->isSuperRegister(I->Reg, II->Reg))
376  I->Reg = II->Reg;
377  II->Reg = 0; // mark for deletion.
378  }
379  }
380 
381  llvm::erase_if(LiveOuts, [](const LiveOutReg &LO) { return LO.Reg == 0; });
382 
383  return LiveOuts;
384 }
385 
386 // See statepoint MI format description in StatepointOpers' class comment
387 // in include/llvm/CodeGen/StackMaps.h
388 void StackMaps::parseStatepointOpers(const MachineInstr &MI,
391  LocationVec &Locations,
392  LiveOutVec &LiveOuts) {
393  LLVM_DEBUG(dbgs() << "record statepoint : " << MI << "\n");
394  StatepointOpers SO(&MI);
395  MOI = parseOperand(MOI, MOE, Locations, LiveOuts); // CC
396  MOI = parseOperand(MOI, MOE, Locations, LiveOuts); // Flags
397  MOI = parseOperand(MOI, MOE, Locations, LiveOuts); // Num Deopts
398 
399  // Record Deopt Args.
400  unsigned NumDeoptArgs = Locations.back().Offset;
401  assert(Locations.back().Type == Location::Constant);
402  assert(NumDeoptArgs == SO.getNumDeoptArgs());
403 
404  while (NumDeoptArgs--)
405  MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
406 
407  // Record gc base/derived pairs
408  assert(MOI->isImm() && MOI->getImm() == StackMaps::ConstantOp);
409  ++MOI;
410  assert(MOI->isImm());
411  unsigned NumGCPointers = MOI->getImm();
412  ++MOI;
413  if (NumGCPointers) {
414  // Map logical index of GC ptr to MI operand index.
415  SmallVector<unsigned, 8> GCPtrIndices;
416  unsigned GCPtrIdx = (unsigned)SO.getFirstGCPtrIdx();
417  assert((int)GCPtrIdx != -1);
418  assert(MOI - MI.operands_begin() == GCPtrIdx + 0LL);
419  while (NumGCPointers--) {
420  GCPtrIndices.push_back(GCPtrIdx);
421  GCPtrIdx = StackMaps::getNextMetaArgIdx(&MI, GCPtrIdx);
422  }
423 
425  unsigned NumGCPairs = SO.getGCPointerMap(GCPairs);
426  (void)NumGCPairs;
427  LLVM_DEBUG(dbgs() << "NumGCPairs = " << NumGCPairs << "\n");
428 
429  auto MOB = MI.operands_begin();
430  for (auto &P : GCPairs) {
431  assert(P.first < GCPtrIndices.size() && "base pointer index not found");
432  assert(P.second < GCPtrIndices.size() &&
433  "derived pointer index not found");
434  unsigned BaseIdx = GCPtrIndices[P.first];
435  unsigned DerivedIdx = GCPtrIndices[P.second];
436  LLVM_DEBUG(dbgs() << "Base : " << BaseIdx << " Derived : " << DerivedIdx
437  << "\n");
438  (void)parseOperand(MOB + BaseIdx, MOE, Locations, LiveOuts);
439  (void)parseOperand(MOB + DerivedIdx, MOE, Locations, LiveOuts);
440  }
441 
442  MOI = MOB + GCPtrIdx;
443  }
444 
445  // Record gc allocas
446  assert(MOI < MOE);
447  assert(MOI->isImm() && MOI->getImm() == StackMaps::ConstantOp);
448  ++MOI;
449  unsigned NumAllocas = MOI->getImm();
450  ++MOI;
451  while (NumAllocas--) {
452  MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
453  assert(MOI < MOE);
454  }
455 }
456 
457 void StackMaps::recordStackMapOpers(const MCSymbol &MILabel,
458  const MachineInstr &MI, uint64_t ID,
461  bool recordResult) {
462  MCContext &OutContext = AP.OutStreamer->getContext();
463 
464  LocationVec Locations;
465  LiveOutVec LiveOuts;
466 
467  if (recordResult) {
468  assert(PatchPointOpers(&MI).hasDef() && "Stackmap has no return value.");
469  parseOperand(MI.operands_begin(), std::next(MI.operands_begin()), Locations,
470  LiveOuts);
471  }
472 
473  // Parse operands.
474  if (MI.getOpcode() == TargetOpcode::STATEPOINT)
475  parseStatepointOpers(MI, MOI, MOE, Locations, LiveOuts);
476  else
477  while (MOI != MOE)
478  MOI = parseOperand(MOI, MOE, Locations, LiveOuts);
479 
480  // Move large constants into the constant pool.
481  for (auto &Loc : Locations) {
482  // Constants are encoded as sign-extended integers.
483  // -1 is directly encoded as .long 0xFFFFFFFF with no constant pool.
484  if (Loc.Type == Location::Constant && !isInt<32>(Loc.Offset)) {
485  Loc.Type = Location::ConstantIndex;
486  // ConstPool is intentionally a MapVector of 'uint64_t's (as
487  // opposed to 'int64_t's). We should never be in a situation
488  // where we have to insert either the tombstone or the empty
489  // keys into a map, and for a DenseMap<uint64_t, T> these are
490  // (uint64_t)0 and (uint64_t)-1. They can be and are
491  // represented using 32 bit integers.
493  (uint64_t)Loc.Offset !=
495  "empty and tombstone keys should fit in 32 bits!");
496  auto Result = ConstPool.insert(std::make_pair(Loc.Offset, Loc.Offset));
497  Loc.Offset = Result.first - ConstPool.begin();
498  }
499  }
500 
501  // Create an expression to calculate the offset of the callsite from function
502  // entry.
503  const MCExpr *CSOffsetExpr = MCBinaryExpr::createSub(
504  MCSymbolRefExpr::create(&MILabel, OutContext),
505  MCSymbolRefExpr::create(AP.CurrentFnSymForSize, OutContext), OutContext);
506 
507  CSInfos.emplace_back(CSOffsetExpr, ID, std::move(Locations),
508  std::move(LiveOuts));
509 
510  // Record the stack size of the current function and update callsite count.
511  const MachineFrameInfo &MFI = AP.MF->getFrameInfo();
512  const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
513  bool HasDynamicFrameSize =
514  MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(*(AP.MF));
515  uint64_t FrameSize = HasDynamicFrameSize ? UINT64_MAX : MFI.getStackSize();
516 
517  auto CurrentIt = FnInfos.find(AP.CurrentFnSym);
518  if (CurrentIt != FnInfos.end())
519  CurrentIt->second.RecordCount++;
520  else
521  FnInfos.insert(std::make_pair(AP.CurrentFnSym, FunctionInfo(FrameSize)));
522 }
523 
525  assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
526 
527  StackMapOpers opers(&MI);
528  const int64_t ID = MI.getOperand(PatchPointOpers::IDPos).getImm();
529  recordStackMapOpers(L, MI, ID, std::next(MI.operands_begin(),
530  opers.getVarIdx()),
531  MI.operands_end());
532 }
533 
535  assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
536 
537  PatchPointOpers opers(&MI);
538  const int64_t ID = opers.getID();
539  auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx());
540  recordStackMapOpers(L, MI, ID, MOI, MI.operands_end(),
541  opers.isAnyReg() && opers.hasDef());
542 
543 #ifndef NDEBUG
544  // verify anyregcc
545  auto &Locations = CSInfos.back().Locations;
546  if (opers.isAnyReg()) {
547  unsigned NArgs = opers.getNumCallArgs();
548  for (unsigned i = 0, e = (opers.hasDef() ? NArgs + 1 : NArgs); i != e; ++i)
549  assert(Locations[i].Type == Location::Register &&
550  "anyreg arg must be in reg.");
551  }
552 #endif
553 }
554 
556  assert(MI.getOpcode() == TargetOpcode::STATEPOINT && "expected statepoint");
557 
558  StatepointOpers opers(&MI);
559  const unsigned StartIdx = opers.getVarIdx();
560  recordStackMapOpers(L, MI, opers.getID(), MI.operands_begin() + StartIdx,
561  MI.operands_end(), false);
562 }
563 
564 /// Emit the stackmap header.
565 ///
566 /// Header {
567 /// uint8 : Stack Map Version (currently 3)
568 /// uint8 : Reserved (expected to be 0)
569 /// uint16 : Reserved (expected to be 0)
570 /// }
571 /// uint32 : NumFunctions
572 /// uint32 : NumConstants
573 /// uint32 : NumRecords
574 void StackMaps::emitStackmapHeader(MCStreamer &OS) {
575  // Header.
576  OS.emitIntValue(StackMapVersion, 1); // Version.
577  OS.emitIntValue(0, 1); // Reserved.
578  OS.emitInt16(0); // Reserved.
579 
580  // Num functions.
581  LLVM_DEBUG(dbgs() << WSMP << "#functions = " << FnInfos.size() << '\n');
582  OS.emitInt32(FnInfos.size());
583  // Num constants.
584  LLVM_DEBUG(dbgs() << WSMP << "#constants = " << ConstPool.size() << '\n');
585  OS.emitInt32(ConstPool.size());
586  // Num callsites.
587  LLVM_DEBUG(dbgs() << WSMP << "#callsites = " << CSInfos.size() << '\n');
588  OS.emitInt32(CSInfos.size());
589 }
590 
591 /// Emit the function frame record for each function.
592 ///
593 /// StkSizeRecord[NumFunctions] {
594 /// uint64 : Function Address
595 /// uint64 : Stack Size
596 /// uint64 : Record Count
597 /// }
598 void StackMaps::emitFunctionFrameRecords(MCStreamer &OS) {
599  // Function Frame records.
600  LLVM_DEBUG(dbgs() << WSMP << "functions:\n");
601  for (auto const &FR : FnInfos) {
602  LLVM_DEBUG(dbgs() << WSMP << "function addr: " << FR.first
603  << " frame size: " << FR.second.StackSize
604  << " callsite count: " << FR.second.RecordCount << '\n');
605  OS.emitSymbolValue(FR.first, 8);
606  OS.emitIntValue(FR.second.StackSize, 8);
607  OS.emitIntValue(FR.second.RecordCount, 8);
608  }
609 }
610 
611 /// Emit the constant pool.
612 ///
613 /// int64 : Constants[NumConstants]
614 void StackMaps::emitConstantPoolEntries(MCStreamer &OS) {
615  // Constant pool entries.
616  LLVM_DEBUG(dbgs() << WSMP << "constants:\n");
617  for (const auto &ConstEntry : ConstPool) {
618  LLVM_DEBUG(dbgs() << WSMP << ConstEntry.second << '\n');
619  OS.emitIntValue(ConstEntry.second, 8);
620  }
621 }
622 
623 /// Emit the callsite info for each callsite.
624 ///
625 /// StkMapRecord[NumRecords] {
626 /// uint64 : PatchPoint ID
627 /// uint32 : Instruction Offset
628 /// uint16 : Reserved (record flags)
629 /// uint16 : NumLocations
630 /// Location[NumLocations] {
631 /// uint8 : Register | Direct | Indirect | Constant | ConstantIndex
632 /// uint8 : Size in Bytes
633 /// uint16 : Dwarf RegNum
634 /// int32 : Offset
635 /// }
636 /// uint16 : Padding
637 /// uint16 : NumLiveOuts
638 /// LiveOuts[NumLiveOuts] {
639 /// uint16 : Dwarf RegNum
640 /// uint8 : Reserved
641 /// uint8 : Size in Bytes
642 /// }
643 /// uint32 : Padding (only if required to align to 8 byte)
644 /// }
645 ///
646 /// Location Encoding, Type, Value:
647 /// 0x1, Register, Reg (value in register)
648 /// 0x2, Direct, Reg + Offset (frame index)
649 /// 0x3, Indirect, [Reg + Offset] (spilled value)
650 /// 0x4, Constant, Offset (small constant)
651 /// 0x5, ConstIndex, Constants[Offset] (large constant)
652 void StackMaps::emitCallsiteEntries(MCStreamer &OS) {
653  LLVM_DEBUG(print(dbgs()));
654  // Callsite entries.
655  for (const auto &CSI : CSInfos) {
656  const LocationVec &CSLocs = CSI.Locations;
657  const LiveOutVec &LiveOuts = CSI.LiveOuts;
658 
659  // Verify stack map entry. It's better to communicate a problem to the
660  // runtime than crash in case of in-process compilation. Currently, we do
661  // simple overflow checks, but we may eventually communicate other
662  // compilation errors this way.
663  if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
664  OS.emitIntValue(UINT64_MAX, 8); // Invalid ID.
665  OS.emitValue(CSI.CSOffsetExpr, 4);
666  OS.emitInt16(0); // Reserved.
667  OS.emitInt16(0); // 0 locations.
668  OS.emitInt16(0); // padding.
669  OS.emitInt16(0); // 0 live-out registers.
670  OS.emitInt32(0); // padding.
671  continue;
672  }
673 
674  OS.emitIntValue(CSI.ID, 8);
675  OS.emitValue(CSI.CSOffsetExpr, 4);
676 
677  // Reserved for flags.
678  OS.emitInt16(0);
679  OS.emitInt16(CSLocs.size());
680 
681  for (const auto &Loc : CSLocs) {
682  OS.emitIntValue(Loc.Type, 1);
683  OS.emitIntValue(0, 1); // Reserved
684  OS.emitInt16(Loc.Size);
685  OS.emitInt16(Loc.Reg);
686  OS.emitInt16(0); // Reserved
687  OS.emitInt32(Loc.Offset);
688  }
689 
690  // Emit alignment to 8 byte.
691  OS.emitValueToAlignment(8);
692 
693  // Num live-out registers and padding to align to 4 byte.
694  OS.emitInt16(0);
695  OS.emitInt16(LiveOuts.size());
696 
697  for (const auto &LO : LiveOuts) {
698  OS.emitInt16(LO.DwarfRegNum);
699  OS.emitIntValue(0, 1);
700  OS.emitIntValue(LO.Size, 1);
701  }
702  // Emit alignment to 8 byte.
703  OS.emitValueToAlignment(8);
704  }
705 }
706 
707 /// Serialize the stackmap data.
709  (void)WSMP;
710  // Bail out if there's no stack map data.
711  assert((!CSInfos.empty() || ConstPool.empty()) &&
712  "Expected empty constant pool too!");
713  assert((!CSInfos.empty() || FnInfos.empty()) &&
714  "Expected empty function record too!");
715  if (CSInfos.empty())
716  return;
717 
718  MCContext &OutContext = AP.OutStreamer->getContext();
719  MCStreamer &OS = *AP.OutStreamer;
720 
721  // Create the section.
722  MCSection *StackMapSection =
723  OutContext.getObjectFileInfo()->getStackMapSection();
724  OS.SwitchSection(StackMapSection);
725 
726  // Emit a dummy symbol to force section inclusion.
727  OS.emitLabel(OutContext.getOrCreateSymbol(Twine("__LLVM_StackMaps")));
728 
729  // Serialize data.
730  LLVM_DEBUG(dbgs() << "********** Stack Map Output **********\n");
731  emitStackmapHeader(OS);
732  emitFunctionFrameRecords(OS);
733  emitConstantPoolEntries(OS);
734  emitCallsiteEntries(OS);
735  OS.AddBlankLine();
736 
737  // Clean up.
738  CSInfos.clear();
739  ConstPool.clear();
740 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StackMaps::Location::Indirect
@ Indirect
Definition: StackMaps.h:258
i
i
Definition: README.txt:29
AsmPrinter.h
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::MCContext::getObjectFileInfo
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:427
llvm::PatchPointOpers::getNumCallArgs
uint32_t getNumCallArgs() const
Return the number of call arguments.
Definition: StackMaps.h:121
llvm::AArch64CC::LO
@ LO
Definition: AArch64BaseInfo.h:258
llvm::PatchPointOpers::hasDef
bool hasDef() const
Definition: StackMaps.h:98
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::StackMapOpers
MI-level stackmap operands.
Definition: StackMaps.h:35
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::StackMaps::Location::Register
@ Register
Definition: StackMaps.h:256
StackMapVersion
static cl::opt< int > StackMapVersion("stackmap-version", cl::init(3), cl::Hidden, cl::desc("Specify the stackmap encoding version (default = 3)"))
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::StackMaps::recordStatepoint
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
Definition: StackMaps.cpp:555
llvm::AsmPrinter::CurrentFnSymForSize
MCSymbol * CurrentFnSymForSize
The symbol used to represent the start of the current function for the purpose of calculating its siz...
Definition: AsmPrinter.h:128
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SmallVector< LiveOutReg, 8 >
ErrorHandling.h
llvm::MCRegisterInfo::getDwarfRegNum
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Definition: MCRegisterInfo.cpp:68
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::erase_if
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
Definition: STLExtras.h:1732
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:177
getDwarfRegNum
static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI)
Go up the super-register chain until we hit a valid dwarf register number.
Definition: StackMaps.cpp:178
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
MCObjectFileInfo.h
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::StatepointOpers::getNumGcMapEntriesIdx
unsigned getNumGcMapEntriesIdx()
Get index of number of gc map entries.
Definition: StackMaps.cpp:94
llvm::MCStreamer::emitInt32
void emitInt32(uint64_t Value)
Definition: MCStreamer.h:707
llvm::MCStreamer::AddBlankLine
virtual void AddBlankLine()
AddBlankLine - Emit a blank line to a .s file to pretty it up.
Definition: MCStreamer.h:363
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
STLExtras.h
llvm::PatchPointOpers
MI-level patchpoint operands.
Definition: StackMaps.h:76
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::PatchPointOpers::getID
uint64_t getID() const
Return the ID for the given patchpoint.
Definition: StackMaps.h:101
llvm::StackMaps::recordStackMap
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
Definition: StackMaps.cpp:524
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::StatepointOpers::getNumDeoptArgsIdx
unsigned getNumDeoptArgsIdx() const
Get index of Number Deopt Arguments operand.
Definition: StackMaps.h:199
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::MapVector::begin
iterator begin()
Definition: MapVector.h:69
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:191
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:97
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
Twine.h
MCContext.h
llvm::StatepointOpers::getGCPointerMap
unsigned getGCPointerMap(SmallVectorImpl< std::pair< unsigned, unsigned >> &GCMap)
Get vector of base/derived pairs from statepoint.
Definition: StackMaps.cpp:135
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:415
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MCStreamer::emitSymbolValue
void emitSymbolValue(const MCSymbol *Sym, unsigned Size, bool IsSectionRelative=false)
Special case of EmitValue that avoids the client having to pass in a MCExpr for MCSymbols.
Definition: MCStreamer.cpp:181
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::MCObjectFileInfo::getStackMapSection
MCSection * getStackMapSection() const
Definition: MCObjectFileInfo.h:345
UINT64_MAX
#define UINT64_MAX
Definition: DataTypes.h:77
TargetOpcodes.h
llvm::MCRegisterInfo::getSubRegIndex
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
Definition: MCRegisterInfo.cpp:44
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::StatepointOpers::getVarIdx
unsigned getVarIdx() const
Get starting index of non call related arguments (calling convention, statepoint flags,...
Definition: StackMaps.h:188
llvm::AsmPrinter::CurrentFnSym
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:119
llvm::StackMaps::StackMaps
StackMaps(AsmPrinter &AP)
Definition: StackMaps.cpp:149
llvm::PatchPointOpers::PatchPointOpers
PatchPointOpers(const MachineInstr *MI)
Definition: StackMaps.cpp:62
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MachineOperand::isRegLiveOut
bool isRegLiveOut() const
isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
Definition: MachineOperand.h:347
llvm::PatchPointOpers::isAnyReg
bool isAnyReg() const
Definition: StackMaps.h:97
llvm::MCRegisterInfo::getLLVMRegNum
Optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
Definition: MCRegisterInfo.cpp:81
llvm::PatchPointOpers::getNextScratchIdx
unsigned getNextScratchIdx(unsigned StartIdx=0) const
Get the next scratch register operand index.
Definition: StackMaps.cpp:77
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MCStreamer::emitInt16
void emitInt16(uint64_t Value)
Definition: MCStreamer.h:706
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::StatepointOpers::getNumAllocaIdx
unsigned getNumAllocaIdx()
Get index of number of gc allocas.
Definition: StackMaps.cpp:104
llvm::StackMapOpers::getVarIdx
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
Definition: StackMaps.h:56
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::PatchPointOpers::getVarIdx
unsigned getVarIdx() const
Get the operand index of the variable list of non-argument operands.
Definition: StackMaps.h:127
llvm::MapVector::find
iterator find(const KeyT &Key)
Definition: MapVector.h:147
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::StackMaps::Location::Constant
@ Constant
Definition: StackMaps.h:259
llvm::StackMaps::serializeToStackMapSection
void serializeToStackMapSection()
If there is any stack map data, create a stack map section and serialize the map info into it.
Definition: StackMaps.cpp:708
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
MCRegisterInfo.h
llvm::StackMaps::LiveOutVec
SmallVector< LiveOutReg, 8 > LiveOutVec
Definition: StackMaps.h:301
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCStreamer::emitIntValue
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Definition: MCStreamer.cpp:133
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:609
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:100
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::StackMaps::getNextMetaArgIdx
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:154
llvm::PatchPointOpers::getStackMapStartIdx
unsigned getStackMapStartIdx() const
Get the index at which stack map locations will be recorded.
Definition: StackMaps.h:133
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MapVector::insert
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: MapVector.h:117
DataLayout.h
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MCSection
Instances of this class represent a uniqued identifier for a section in the current translation unit.
Definition: MCSection.h:39
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::StackMapOpers::StackMapOpers
StackMapOpers(const MachineInstr *MI)
Definition: StackMaps.cpp:56
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::MapVector::end
iterator end()
Definition: MapVector.h:71
llvm::StatepointOpers::getFirstGCPtrIdx
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
llvm::StackMaps::Location::Direct
@ Direct
Definition: StackMaps.h:257
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::StatepointOpers
MI-level Statepoint operands.
Definition: StackMaps.h:158
llvm::StackMaps::Location::ConstantIndex
@ ConstantIndex
Definition: StackMaps.h:260
MachineFrameInfo.h
llvm::StackMaps::recordPatchPoint
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
Definition: StackMaps.cpp:534
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1492
llvm::MapVector::size
size_type size() const
Definition: MapVector.h:60
StackMaps.h
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:385
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:936
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:656
getConstMetaVal
static uint64_t getConstMetaVal(const MachineInstr &MI, unsigned Idx)
Definition: StackMaps.cpp:48
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
MCStreamer.h
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::StackMaps::Location::Unprocessed
@ Unprocessed
Definition: StackMaps.h:255
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MCStreamer::emitValueToAlignment
virtual void emitValueToAlignment(unsigned ByteAlignment, int64_t Value=0, unsigned ValueSize=1, unsigned MaxBytesToEmit=0)
Emit some number of copies of Value until the byte alignment ByteAlignment is reached.
Definition: MCStreamer.cpp:1199
llvm::MachineOperand::getRegLiveOut
const uint32_t * getRegLiveOut() const
getRegLiveOut - Returns a bit mask of live-out registers.
Definition: MachineOperand.h:641
llvm::MCRegisterInfo::getSubRegIdxOffset
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
Definition: MCRegisterInfo.cpp:62
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
DenseMapInfo.h
llvm::StatepointOpers::getID
uint64_t getID() const
Return the ID for the given statepoint.
Definition: StackMaps.h:204
llvm::StackMaps::LocationVec
SmallVector< Location, 8 > LocationVec
Definition: StackMaps.h:300
llvm::cl::desc
Definition: CommandLine.h:412
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MCStreamer::SwitchSection
virtual void SwitchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Definition: MCStreamer.cpp:1212
MCExpr.h
llvm::PatchPointOpers::IDPos
@ IDPos
Definition: StackMaps.h:79
TargetRegisterInfo.h
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::StatepointOpers::getNumGCPtrIdx
unsigned getNumGCPtrIdx()
Get index of number of GC pointers.
Definition: StackMaps.cpp:114
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::StackMaps::LiveOutReg
Definition: StackMaps.h:272