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43 #define DEBUG_TYPE "tile-pre-config"
49 ": Failed to config tile register, please define the shape earlier";
69 Pos(
std::distance(
MBB->instr_begin(), ++
MI->getIterator())) {}
72 Pos(
std::distance(
MBB->instr_begin(), ++
MI->getIterator())) {}
75 operator bool()
const {
return MBB !=
nullptr; }
95 bool HasAMXRegLiveIn =
false;
96 bool TileCfgForbidden =
false;
97 bool NeedTileCfgLiveIn =
false;
111 if (Iter ==
MI.operands_end())
114 return !UsableRegs.
none();
119 if (
MI.isPHI() ||
MI.isDebugInstr() ||
MI.getNumOperands() < 3)
126 collectShapeInfo(
MI);
130 return MI.getOpcode() == X86::PTILESTOREDV;
138 if (ML->contains(Bottom) && ML->isLoopLatch(Bottom))
149 MIRef &FirstAMX = BBVisitedInfo[
MBB].FirstAMX;
151 auto InsertPoint = FirstAMX.MI->getIterator();
152 for (
auto I = FirstShapeBelowAMX,
E = Shapes.end();
I !=
E; ++
I) {
154 if (
I->MI->mayLoadOrStore())
156 for (
auto &MO :
I->MI->operands()) {
165 MBB->
insert(InsertPoint,
I->MI->removeFromParent());
169 Shapes.push_back(MIRef(&*--InsertPoint,
MBB));
178 return "Tile Register Pre-configure";
189 void releaseMemory()
override {
192 BBVisitedInfo.
clear();
206 "Tile Register Pre-configure",
false,
false)
215 if (
I == ShapeBBs[
MBB].
end() || *
I != MIR)
220 {
MI.getOperand(1).
getReg(),
MI.getOperand(2).getReg()});
221 while (!WorkList.empty()) {
222 Register R = WorkList.pop_back_val();
224 assert(
DefMI &&
"R must has one define instruction");
231 RecordShape(
DefMI, DefMBB);
235 RecordShape(
DefMI, DefMBB);
249 AMXRegs.set(X86::TMM0 +
I);
253 MLI = &getAnalysis<MachineLoopInfo>();
256 for (
auto &
MBB : MF) {
258 for (
auto &
MI :
MBB) {
260 if (isAMXInstruction(
MI)) {
262 if (BBVisitedInfo[&
MBB].LastCall)
263 CfgNeedInsert.
insert(BBVisitedInfo[&
MBB].LastCall);
265 BBVisitedInfo[&
MBB].NeedTileCfgLiveIn =
true;
267 if (!BBVisitedInfo[&
MBB].FirstAMX)
268 BBVisitedInfo[&
MBB].FirstAMX = MIRef(&
MI, &
MBB, Pos);
269 }
else if (
MI.isCall() && isDestructiveCall(
MI, AMXRegs)) {
271 BBVisitedInfo[&
MBB].LastCall = MIRef(&
MI, &
MBB, Pos);
274 if (BBVisitedInfo[&
MBB].NeedTileCfgLiveIn) {
278 CfgLiveInBBs.push_back(&
MBB);
280 if (BBVisitedInfo[&
MBB].FirstAMX || BBVisitedInfo[&
MBB].HasAMXRegLiveIn)
282 if (!isLoopBackEdge(Succ, &
MBB))
283 BBVisitedInfo[Succ].HasAMXRegLiveIn =
true;
287 while (!CfgLiveInBBs.empty()) {
290 if (BBVisitedInfo[Pred].LastCall) {
291 CfgNeedInsert.
insert(BBVisitedInfo[Pred].LastCall);
292 }
else if (!BBVisitedInfo[Pred].NeedTileCfgLiveIn) {
293 BBVisitedInfo[Pred].NeedTileCfgLiveIn =
true;
294 if (Pred == &MF.front())
295 CfgNeedInsert.
insert(MIRef(Pred));
297 CfgLiveInBBs.push_back(Pred);
303 if (CfgNeedInsert.
empty())
309 for (
auto &
I : ShapeBBs) {
311 if (BBVisitedInfo[
I.first].HasAMXRegLiveIn) {
318 if (BBVisitedInfo[
I.first].FirstAMX &&
319 BBVisitedInfo[
I.first].FirstAMX <
I.second.back() &&
320 !hoistShapesInBB(
I.first,
I.second)) {
324 WorkList.push_back(
I.first);
326 while (!WorkList.empty()) {
329 if (!BBVisitedInfo[Pred].TileCfgForbidden && !isLoopBackEdge(
MBB, Pred)) {
330 BBVisitedInfo[Pred].TileCfgForbidden =
true;
331 WorkList.push_back(Pred);
338 int SS = MF.getFrameInfo().CreateStackObject(
339 ST.getTileConfigSize(),
ST.getTileConfigAlignment(),
false);
342 for (
const auto &
I : CfgNeedInsert) {
345 while (!WorkList.empty()) {
347 if (!VisitedOrInserted.
count(
I)) {
348 if (!BBVisitedInfo[
I.MBB].TileCfgForbidden) {
356 for (
auto *Succ :
I.MBB->successors())
357 if (BBVisitedInfo[Succ].NeedTileCfgLiveIn)
358 WorkList.push_back(MIRef(Succ));
364 for (MIRef
I : InsertPoints) {
366 if (ShapeBBs.count(
I.MBB) &&
I < ShapeBBs[
I.MBB].back())
367 I = ShapeBBs[
I.MBB].back();
370 if (VisitedOrInserted.
insert(
I).second) {
371 auto II =
I.MI ?
I.MI->getIterator() :
I.MBB->instr_begin();
381 if (
ST.hasAVX512()) {
386 }
else if (
ST.hasAVX2()) {
394 assert(
ST.hasSSE2() &&
"AMX should assume SSE2 enabled");
395 unsigned StoreOpc =
ST.hasAVX() ? X86::VMOVUPSmr : X86::MOVUPSmr;
413 return new X86PreTileConfig();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
bool none() const
none - Returns true if none of the bits are set.
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
INITIALIZE_PASS_BEGIN(X86PreTileConfig, "tilepreconfig", "Tile Register Pre-configure", false, false) INITIALIZE_PASS_END(X86PreTileConfig
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
bool isMoveImmediate(QueryType Type=IgnoreBundle) const
Return true if this instruction is a move immediate (including conditional moves) instruction.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const_iterator end(StringRef path)
Get end iterator over path.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bool operator!=(uint64_t V1, const APInt &V2)
LLVM_NODISCARD T pop_back_val()
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineOperand & getOperand(unsigned i) const
Represent the analysis usage information of a pass.
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isLoopHeader(const MachineBasicBlock *BB) const
True if the block is a loop header node.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
MachineModuleInfo & getMMI() const
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
This is an important class for using LLVM in a threaded context.
bool operator<(int64_t V1, const APSInt &V2)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
static void emitErrorMsg(MachineFunction &MF)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool operator==(uint64_t V1, const APInt &V2)
void setHasVirtualTileReg(bool v)
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
iterator_range< pred_iterator > predecessors()
MachineBasicBlock * getMBB() const
iterator_range< succ_iterator > successors()
StringRef - Represent a constant reference to a string, i.e.
void clearBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
clearBitsInMask - Clear any bits in this vector that are set in Mask.
static const Function * getParent(const Value *V)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
const MachineBasicBlock * getParent() const
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Tile Register Pre configure
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
unsigned getNumRegs() const
Return the number of registers in this class.
void setPreservesAll()
Set by analyses that do not transform their input at all.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LLVMContext & getContext() const
Get the global data context.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBuilder MachineInstrBuilder & DefMI
unsigned getNumOperands() const
Retuns the total number of operands.
bool operator>(int64_t V1, const APSInt &V2)
LLVM_NODISCARD bool empty() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
FunctionPass class - This class is used to implement most global optimizations.
AnalysisUsage & addRequired()
const Module * getModule() const