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20 #define GET_TARGET_REGBANK_IMPL
21 #include "X86GenRegisterBank.inc"
25 #define GET_TARGET_REGBANK_INFO_IMPL
26 #include "X86GenRegisterBankInfo.def"
34 assert(&X86::GPRRegBank == &RBGPR &&
"Incorrect RegBanks inizalization.");
39 "Subclass not added?");
40 assert(RBGPR.
getSize() == 64 &&
"GPRs should hold up to 64-bit");
47 if (X86::GR8RegClass.hasSubClassEq(&RC) ||
48 X86::GR16RegClass.hasSubClassEq(&RC) ||
49 X86::GR32RegClass.hasSubClassEq(&RC) ||
50 X86::GR64RegClass.hasSubClassEq(&RC) ||
51 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) ||
52 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC))
55 if (X86::FR32XRegClass.hasSubClassEq(&RC) ||
56 X86::FR64XRegClass.hasSubClassEq(&RC) ||
57 X86::VR128XRegClass.hasSubClassEq(&RC) ||
58 X86::VR256XRegClass.hasSubClassEq(&RC) ||
59 X86::VR512RegClass.hasSubClassEq(&RC))
111 void X86RegisterBankInfo::getInstrPartialMappingIdxs(
115 unsigned NumOperands =
MI.getNumOperands();
116 for (
unsigned Idx = 0; Idx < NumOperands; ++Idx) {
117 auto &MO =
MI.getOperand(Idx);
119 OpRegBankIdx[Idx] = PMI_None;
125 bool X86RegisterBankInfo::getInstrValueMapping(
130 unsigned NumOperands =
MI.getNumOperands();
131 for (
unsigned Idx = 0; Idx < NumOperands; ++Idx) {
132 if (!
MI.getOperand(Idx).isReg())
136 if (!Mapping->isValid())
139 OpdsMapping[Idx] = Mapping;
145 X86RegisterBankInfo::getSameOperandsMapping(
const MachineInstr &
MI,
150 unsigned NumOperands =
MI.getNumOperands();
153 if (NumOperands != 3 || (Ty !=
MRI.
getType(
MI.getOperand(1).getReg())) ||
165 unsigned Opc =
MI.getOpcode();
176 case TargetOpcode::G_ADD:
177 case TargetOpcode::G_SUB:
178 case TargetOpcode::G_MUL:
179 return getSameOperandsMapping(
MI,
false);
180 case TargetOpcode::G_FADD:
181 case TargetOpcode::G_FSUB:
182 case TargetOpcode::G_FMUL:
183 case TargetOpcode::G_FDIV:
184 return getSameOperandsMapping(
MI,
true);
185 case TargetOpcode::G_SHL:
186 case TargetOpcode::G_LSHR:
187 case TargetOpcode::G_ASHR: {
188 unsigned NumOperands =
MI.getNumOperands();
199 unsigned NumOperands =
MI.getNumOperands();
203 case TargetOpcode::G_FPEXT:
204 case TargetOpcode::G_FPTRUNC:
205 case TargetOpcode::G_FCONSTANT:
207 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
209 case TargetOpcode::G_SITOFP:
210 case TargetOpcode::G_FPTOSI: {
213 auto &Op0 =
MI.getOperand(0);
214 auto &Op1 =
MI.getOperand(1);
218 bool FirstArgIsFP = Opc == TargetOpcode::G_SITOFP;
219 bool SecondArgIsFP = Opc == TargetOpcode::G_FPTOSI;
224 case TargetOpcode::G_FCMP: {
229 "Mismatched operand sizes for G_FCMP");
233 assert((
Size == 32 ||
Size == 64) &&
"Unsupported size for G_FCMP");
236 OpRegBankIdx = {PMI_GPR8,
237 PMI_None, FpRegBank, FpRegBank};
240 case TargetOpcode::G_TRUNC:
241 case TargetOpcode::G_ANYEXT: {
242 auto &Op0 =
MI.getOperand(0);
243 auto &Op1 =
MI.getOperand(1);
252 Opc == TargetOpcode::G_ANYEXT;
254 getInstrPartialMappingIdxs(
MI,
MRI, isFPTrunc || isFPAnyExt,
259 getInstrPartialMappingIdxs(
MI,
MRI,
false, OpRegBankIdx);
265 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
285 switch (
MI.getOpcode()) {
286 case TargetOpcode::G_LOAD:
287 case TargetOpcode::G_STORE:
288 case TargetOpcode::G_IMPLICIT_DEF: {
294 unsigned NumOperands =
MI.getNumOperands();
298 getInstrPartialMappingIdxs(
MI,
MRI,
true, OpRegBankIdx);
302 if (!getInstrValueMapping(
MI, OpRegBankIdx, OpdsMapping))
308 AltMappings.push_back(&Mapping);
void applyMappingImpl(const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isValid() const
Check whether this object is valid.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
unsigned const TargetRegisterInfo * TRI
static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This class implements the register bank concept.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
X86RegisterBankInfo(const TargetRegisterInfo &TRI)
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
Representation of each machine instruction.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx Idx, unsigned NumOperands)
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...