LLVM 19.0.0git
SIISelLowering.h
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1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUISelLowering.h"
20
21namespace llvm {
22
23class GCNSubtarget;
24class SIMachineFunctionInfo;
25class SIRegisterInfo;
26
27namespace AMDGPU {
28struct ImageDimIntrinsicInfo;
29}
30
32private:
33 const GCNSubtarget *Subtarget;
34
35public:
38 EVT VT) const override;
41 EVT VT) const override;
42
44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
46
47private:
48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49 SDValue Chain, uint64_t Offset) const;
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
53 const SDLoc &SL, SDValue Chain,
54 uint64_t Offset, Align Alignment,
55 bool Signed,
56 const ISD::InputArg *Arg = nullptr) const;
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
58 Align Alignment,
59 ImplicitParameter Param) const;
60
61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
62 const SDLoc &SL, SDValue Chain,
63 const ISD::InputArg &Arg) const;
64 SDValue getPreloadedValue(SelectionDAG &DAG,
65 const SIMachineFunctionInfo &MFI,
66 EVT VT,
68
69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
70 SelectionDAG &DAG) const override;
71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
72 MVT VT, unsigned Offset) const;
74 SelectionDAG &DAG, bool WithChain) const;
75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
76 SDValue CachePolicy, SelectionDAG &DAG) const;
77
78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
79 unsigned NewOpcode) const;
80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
81 unsigned NewOpcode) const;
82
83 SDValue lowerWaveID(SelectionDAG &DAG, SDValue Op) const;
84 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
85 const ArgDescriptor &ArgDesc) const;
86
87 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
90
91 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
92 // (the offset that is included in bounds checking and swizzling, to be split
93 // between the instruction's voffset and immoffset fields) and soffset (the
94 // offset that is excluded from bounds checking and swizzling, to go in the
95 // instruction's soffset field). This function takes the first kind of
96 // offset and figures out how to split it between voffset and immoffset.
97 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
98 SelectionDAG &DAG) const;
99
100 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
101 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
103 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
104 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
105 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
112 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
113 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
114 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
115 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
118 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
119 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
121 bool IsIntrinsic = false) const;
122
123 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
124 ArrayRef<SDValue> Ops) const;
125
126 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
127 // dwordx4 if on SI.
128 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
129 ArrayRef<SDValue> Ops, EVT MemVT,
130 MachineMemOperand *MMO, SelectionDAG &DAG) const;
131
132 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
133 bool ImageStore = false) const;
134
135 /// Converts \p Op, which must be of floating point type, to the
136 /// floating point type \p VT, by either extending or truncating it.
137 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
138 SDValue Op,
139 const SDLoc &DL,
140 EVT VT) const;
141
142 SDValue convertArgType(
143 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
144 bool Signed, const ISD::InputArg *Arg = nullptr) const;
145
146 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
147 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
148 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
149 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
150 SDValue lowerMUL(SDValue Op, SelectionDAG &DAG) const;
151 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
152 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
153
154 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
155 SelectionDAG &DAG) const;
156
157 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
158 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
159 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
160 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
161 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
162 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
163 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
164
165 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
166 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
167 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
168 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
169 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
170
171 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
172
173 SDValue performUCharToFloatCombine(SDNode *N,
174 DAGCombinerInfo &DCI) const;
175 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
176
177 SDValue performSHLPtrCombine(SDNode *N,
178 unsigned AS,
179 EVT MemVT,
180 DAGCombinerInfo &DCI) const;
181
182 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
183
184 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
185 unsigned Opc, SDValue LHS,
186 const ConstantSDNode *CRHS) const;
187
188 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
189 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
190 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
191 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
192 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
195 const APFloat &C) const;
196 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197
198 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
199 SDValue Op0, SDValue Op1) const;
200 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
201 SDValue Src, SDValue MinVal, SDValue MaxVal,
202 bool Signed) const;
203 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
204 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
205 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
208 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
209
210 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
211 unsigned getFusedOpcode(const SelectionDAG &DAG,
212 const SDNode *N0, const SDNode *N1) const;
213 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
214 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
215 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
217 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
218 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
219 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
220 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
221 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
222 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
223 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
224 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
225
226 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
227
228 unsigned isCFIntrinsic(const SDNode *Intr) const;
229
230public:
231 /// \returns True if fixup needs to be emitted for given global value \p GV,
232 /// false otherwise.
233 bool shouldEmitFixup(const GlobalValue *GV) const;
234
235 /// \returns True if GOT relocation needs to be emitted for given global value
236 /// \p GV, false otherwise.
237 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
238
239 /// \returns True if PC-relative relocation needs to be emitted for given
240 /// global value \p GV, false otherwise.
241 bool shouldEmitPCReloc(const GlobalValue *GV) const;
242
243 /// \returns true if this should use a literal constant for an LDS address,
244 /// and not emit a relocation for an LDS global.
245 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
246
247 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
248 /// expanded into a set of cmp/select instructions.
249 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
250 bool IsDivergentIdx,
251 const GCNSubtarget *Subtarget);
252
253 bool shouldExpandVectorDynExt(SDNode *N) const;
254
255private:
256 // Analyze a combined offset from an amdgcn_s_buffer_load intrinsic and store
257 // the three offsets (voffset, soffset and instoffset) into the SDValue[3]
258 // array pointed to by Offsets.
259 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
260 SDValue *Offsets, Align Alignment = Align(4)) const;
261
262 // Convert the i128 that an addrspace(8) pointer is natively represented as
263 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
264 // add register classes for i128 on pain of the promotion logic going haywire,
265 // so this slightly ugly hack is what we've got. If passed a non-pointer
266 // argument (as would be seen in older buffer intrinsics), does nothing.
267 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
268
269 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
270 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
271 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
272
273 // Handle 8 bit and 16 bit buffer loads
274 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
277 bool IsTFE = false) const;
278
279 // Handle 8 bit and 16 bit buffer stores
280 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
281 SDLoc DL, SDValue Ops[],
282 MemSDNode *M) const;
283
284public:
285 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
286
287 const GCNSubtarget *getSubtarget() const;
288
290
291 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
292 EVT SrcVT) const override;
293
294 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
295 LLT SrcTy) const override;
296
297 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
298
299 // While address space 7 should never make it to codegen, it still needs to
300 // have a MVT to prevent some analyses that query this function from breaking,
301 // so, to work around the lack of i160, map it to v5i32.
302 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
303 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
304
306 MachineFunction &MF,
307 unsigned IntrinsicID) const override;
308
311 SelectionDAG &DAG) const override;
312
315 Type *&/*AccessTy*/) const override;
316
317 bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const;
318 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
319 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
320 unsigned AS,
321 Instruction *I = nullptr) const override;
322
323 bool canMergeStoresTo(unsigned AS, EVT MemVT,
324 const MachineFunction &MF) const override;
325
327 unsigned Size, unsigned AddrSpace, Align Alignment,
329 unsigned *IsFast = nullptr) const;
330
332 LLT Ty, unsigned AddrSpace, Align Alignment,
334 unsigned *IsFast = nullptr) const override {
335 if (IsFast)
336 *IsFast = 0;
338 Alignment, Flags, IsFast);
339 }
340
342 EVT VT, unsigned AS, Align Alignment,
344 unsigned *IsFast = nullptr) const override;
345
347 const AttributeList &FuncAttributes) const override;
348
349 bool isMemOpUniform(const SDNode *N) const;
350 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
351
352 static bool isNonGlobalAddrSpace(unsigned AS);
353
354 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
355
357 getPreferredVectorAction(MVT VT) const override;
358
360 Type *Ty) const override;
361
362 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
363 unsigned Index) const override;
364
365 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
366
367 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
368
369 unsigned combineRepeatedFPDivisors() const override {
370 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
371 // reciprocal.
372 return 2;
373 }
374
375 bool supportSplitCSR(MachineFunction *MF) const override;
376 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
378 MachineBasicBlock *Entry,
379 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
380
382 bool isVarArg,
384 const SDLoc &DL, SelectionDAG &DAG,
385 SmallVectorImpl<SDValue> &InVals) const override;
386
387 bool CanLowerReturn(CallingConv::ID CallConv,
388 MachineFunction &MF, bool isVarArg,
390 LLVMContext &Context) const override;
391
392 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
394 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
395 SelectionDAG &DAG) const override;
396
398 CallLoweringInfo &CLI,
399 CCState &CCInfo,
401 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
402 SmallVectorImpl<SDValue> &MemOpChains,
403 SDValue Chain) const;
404
406 CallingConv::ID CallConv, bool isVarArg,
408 const SDLoc &DL, SelectionDAG &DAG,
409 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
410 SDValue ThisVal) const;
411
412 bool mayBeEmittedAsTailCall(const CallInst *) const override;
413
415 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
417 const SmallVectorImpl<SDValue> &OutVals,
418 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
419
420 SDValue LowerCall(CallLoweringInfo &CLI,
421 SmallVectorImpl<SDValue> &InVals) const override;
422
428
433
434 Register getRegisterByName(const char* RegName, LLT VT,
435 const MachineFunction &MF) const override;
436
438 MachineBasicBlock *BB) const;
439
442 MachineBasicBlock *BB) const;
443
446 MachineBasicBlock *BB) const override;
447
448 bool enableAggressiveFMAFusion(EVT VT) const override;
449 bool enableAggressiveFMAFusion(LLT Ty) const override;
451 EVT VT) const override;
452 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
453 LLT getPreferredShiftAmountTy(LLT Ty) const override;
454
456 EVT VT) const override;
458 const LLT Ty) const override;
459 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
460 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
461
465 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
466
468 SelectionDAG &DAG) const override;
469
470 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
471 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
472 void AddMemOpInit(MachineInstr &MI) const;
474 SDNode *Node) const override;
475
477
479 SDValue Ptr) const;
481 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
482 std::pair<unsigned, const TargetRegisterClass *>
484 StringRef Constraint, MVT VT) const override;
485 ConstraintType getConstraintType(StringRef Constraint) const override;
487 std::vector<SDValue> &Ops,
488 SelectionDAG &DAG) const override;
489 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
490 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
491 uint64_t Val) const;
493 uint64_t Val,
494 unsigned MaxSize = 64) const;
495 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
496 SDValue V) const;
497
498 void finalizeLowering(MachineFunction &MF) const override;
499
501 const APInt &DemandedElts,
502 const SelectionDAG &DAG,
503 unsigned Depth = 0) const override;
504 void computeKnownBitsForFrameIndex(int FrameIdx,
505 KnownBits &Known,
506 const MachineFunction &MF) const override;
508 KnownBits &Known,
509 const APInt &DemandedElts,
511 unsigned Depth = 0) const override;
512
515 unsigned Depth = 0) const override;
517 UniformityInfo *UA) const override;
518
519 bool hasMemSDNodeUser(SDNode *N) const;
520
522 SDValue N1) const override;
523
525 Register N1) const override;
526
528 unsigned MaxDepth = 5) const;
530 unsigned MaxDepth = 5) const;
531 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
532 bool denormalsEnabledForType(LLT Ty, const MachineFunction &MF) const;
533
534 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
535 const TargetRegisterInfo *TRI,
536 const TargetInstrInfo *TII, unsigned &PhysReg,
537 int &Cost) const override;
538
540 const SelectionDAG &DAG,
541 bool SNaN = false,
542 unsigned Depth = 0) const override;
548 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
549
550 LoadInst *
552
554 bool isDivergent) const override;
556 const Value *V) const override;
557 Align getPrefLoopAlignment(MachineLoop *ML) const override;
558
559 void allocateHSAUserSGPRs(CCState &CCInfo,
560 MachineFunction &MF,
561 const SIRegisterInfo &TRI,
563
567 MachineFunction &MF,
568 const SIRegisterInfo &TRI,
570
572 const SIRegisterInfo &TRI,
574
575 void allocateSystemSGPRs(CCState &CCInfo,
576 MachineFunction &MF,
578 CallingConv::ID CallConv,
579 bool IsShader) const;
580
582 MachineFunction &MF,
583 const SIRegisterInfo &TRI,
586 CCState &CCInfo,
587 MachineFunction &MF,
588 const SIRegisterInfo &TRI,
590
592 MachineFunction &MF,
593 const SIRegisterInfo &TRI,
596 MachineFunction &MF,
597 const SIRegisterInfo &TRI,
599
601 getTargetMMOFlags(const Instruction &I) const override;
602};
603
604// Returns true if argument is a boolean value which is not serialized into
605// memory or argument and does not require v_cndmask_b32 to be deserialized.
606bool isBoolSGPR(SDValue V);
607
608} // End namespace llvm
609
610#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned Intr
Interface definition of the TargetLowering class that is common to all AMD GPUs.
Function Alias Analysis Results
block Block Frequency Analysis
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Value * LHS
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:540
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:749
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:193
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const
bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const override
Allows the target to handle physreg-carried dependency in target-specific way.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MVT getPointerTy(const DataLayout &DL, unsigned AS) const override
Map address space 7 to MVT::v5i32 because that's its in-memory representation.
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const
const GCNSubtarget * getSubtarget() const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
bool shouldEmitGOTReloc(const GlobalValue *GV) const
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
ArrayRef< MCPhysReg > getRoundingControlRegisters() const override
Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
void AddMemOpInit(MachineInstr &MI) const
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isMemOpUniform(const SDNode *N) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool shouldEmitFixup(const GlobalValue *GV) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
bool hasMemSDNodeUser(SDNode *N) const
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
bool isLegalFlatAddressingMode(const AddrMode &AM, unsigned AddrSpace) const
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
static bool isNonGlobalAddrSpace(unsigned AS)
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) const
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override
Perform a atomicrmw expansion using a target-specific way.
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx, const GCNSubtarget *Subtarget)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override
LLT handling variant.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
bool shouldEmitPCReloc(const GlobalValue *GV) const
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocatePreloadKernArgSGPRs(CCState &CCInfo, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ISD::InputArg > &Ins, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override
Similarly, the in-memory representation of a p7 is {p8, i32}, aka v8i32 when padding is added.
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
An instruction for storing to memory.
Definition: Instructions.h:318
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool isBoolSGPR(SDValue V)
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...