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SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class SIMachineFunctionInfo;
25 class SIRegisterInfo;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 
31 class SITargetLowering final : public AMDGPUTargetLowering {
32 private:
33  const GCNSubtarget *Subtarget;
34 
35 public:
38  EVT VT) const override;
41  EVT VT) const override;
42 
44  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
45  unsigned &NumIntermediates, MVT &RegisterVT) const override;
46 
47 private:
48  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49  SDValue Chain, uint64_t Offset) const;
50  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51  SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
53  const SDLoc &SL, SDValue Chain,
54  uint64_t Offset, Align Alignment,
55  bool Signed,
56  const ISD::InputArg *Arg = nullptr) const;
57  SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
58  Align Alignment,
59  ImplicitParameter Param) const;
60 
61  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
62  const SDLoc &SL, SDValue Chain,
63  const ISD::InputArg &Arg) const;
64  SDValue getPreloadedValue(SelectionDAG &DAG,
65  const SIMachineFunctionInfo &MFI,
66  EVT VT,
68 
69  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
70  SelectionDAG &DAG) const override;
71  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
72  MVT VT, unsigned Offset) const;
74  SelectionDAG &DAG, bool WithChain) const;
75  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
76  SDValue CachePolicy, SelectionDAG &DAG) const;
77 
78  SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
79  unsigned NewOpcode) const;
80  SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
81  unsigned NewOpcode) const;
82 
83  SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
84  const ArgDescriptor &ArgDesc) const;
85 
86  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
89 
90  SDValue makeV_ILLEGAL(SDValue Op, SelectionDAG &DAG) const;
91 
92  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
93  // (the offset that is included in bounds checking and swizzling, to be split
94  // between the instruction's voffset and immoffset fields) and soffset (the
95  // offset that is excluded from bounds checking and swizzling, to go in the
96  // instruction's soffset field). This function takes the first kind of
97  // offset and figures out how to split it between voffset and immoffset.
98  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
99  SelectionDAG &DAG) const;
100 
101  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
102  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
104  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
105  SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
106  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
107  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
108  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
109  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
110  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
111  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
112  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
113  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
114  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
115  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
116  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
118  bool IsIntrinsic = false) const;
119 
120  SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
121  ArrayRef<SDValue> Ops) const;
122 
123  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
124  // dwordx4 if on SI.
125  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
126  ArrayRef<SDValue> Ops, EVT MemVT,
127  MachineMemOperand *MMO, SelectionDAG &DAG) const;
128 
129  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
130  bool ImageStore = false) const;
131 
132  /// Converts \p Op, which must be of floating point type, to the
133  /// floating point type \p VT, by either extending or truncating it.
134  SDValue getFPExtOrFPRound(SelectionDAG &DAG,
135  SDValue Op,
136  const SDLoc &DL,
137  EVT VT) const;
138 
139  SDValue convertArgType(
140  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
141  bool Signed, const ISD::InputArg *Arg = nullptr) const;
142 
143  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
144  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
145  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
146  SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
147  SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
148 
149  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
150  SelectionDAG &DAG) const;
151 
152  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
153  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
154  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
155  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
156  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
157  SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
158  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
159 
160  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
161  SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
162  SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
163  SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
164  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
165 
166  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
167 
168  SDValue performUCharToFloatCombine(SDNode *N,
169  DAGCombinerInfo &DCI) const;
170  SDValue performSHLPtrCombine(SDNode *N,
171  unsigned AS,
172  EVT MemVT,
173  DAGCombinerInfo &DCI) const;
174 
175  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
176 
177  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
178  unsigned Opc, SDValue LHS,
179  const ConstantSDNode *CRHS) const;
180 
181  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
182  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
183  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
184  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
185  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
186  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
188  const APFloat &C) const;
189  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
190 
191  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
192  SDValue Op0, SDValue Op1) const;
193  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
194  SDValue Op0, SDValue Op1, bool Signed) const;
195  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
197  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
198  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
199  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
200 
201  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
202  unsigned getFusedOpcode(const SelectionDAG &DAG,
203  const SDNode *N0, const SDNode *N1) const;
204  SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
205  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
208  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
209  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
210  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
211  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
212  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
213  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
214  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
215 
216  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
217  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
218 
219  unsigned isCFIntrinsic(const SDNode *Intr) const;
220 
221 public:
222  /// \returns True if fixup needs to be emitted for given global value \p GV,
223  /// false otherwise.
224  bool shouldEmitFixup(const GlobalValue *GV) const;
225 
226  /// \returns True if GOT relocation needs to be emitted for given global value
227  /// \p GV, false otherwise.
228  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
229 
230  /// \returns True if PC-relative relocation needs to be emitted for given
231  /// global value \p GV, false otherwise.
232  bool shouldEmitPCReloc(const GlobalValue *GV) const;
233 
234  /// \returns true if this should use a literal constant for an LDS address,
235  /// and not emit a relocation for an LDS global.
236  bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
237 
238  /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
239  /// expanded into a set of cmp/select instructions.
240  static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
241  bool IsDivergentIdx,
242  const GCNSubtarget *Subtarget);
243 
244  bool shouldExpandVectorDynExt(SDNode *N) const;
245 
246 private:
247  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
248  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
249  // pointed to by Offsets.
250  void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
251  SDValue *Offsets, Align Alignment = Align(4)) const;
252 
253  // Handle 8 bit and 16 bit buffer loads
254  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
255  ArrayRef<SDValue> Ops, MemSDNode *M) const;
256 
257  // Handle 8 bit and 16 bit buffer stores
258  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
259  SDLoc DL, SDValue Ops[],
260  MemSDNode *M) const;
261 
262 public:
263  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
264 
265  const GCNSubtarget *getSubtarget() const;
266 
267  bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
268  EVT SrcVT) const override;
269 
270  bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
271  LLT SrcTy) const override;
272 
273  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
274 
275  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
276  MachineFunction &MF,
277  unsigned IntrinsicID) const override;
278 
279  bool getAddrModeArguments(IntrinsicInst * /*I*/,
280  SmallVectorImpl<Value*> &/*Ops*/,
281  Type *&/*AccessTy*/) const override;
282 
283  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
284  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
285  unsigned AS,
286  Instruction *I = nullptr) const override;
287 
288  bool canMergeStoresTo(unsigned AS, EVT MemVT,
289  const MachineFunction &MF) const override;
290 
292  unsigned Size, unsigned AddrSpace, Align Alignment,
294  unsigned *IsFast = nullptr) const;
295 
297  LLT Ty, unsigned AddrSpace, Align Alignment,
299  unsigned *IsFast = nullptr) const override {
300  if (IsFast)
301  *IsFast = 0;
302  return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
303  Alignment, Flags, IsFast);
304  }
305 
307  EVT VT, unsigned AS, Align Alignment,
309  unsigned *IsFast = nullptr) const override;
310 
312  const AttributeList &FuncAttributes) const override;
313 
314  bool isMemOpUniform(const SDNode *N) const;
315  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
316 
317  static bool isNonGlobalAddrSpace(unsigned AS);
318 
319  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
320 
322  getPreferredVectorAction(MVT VT) const override;
323 
325  Type *Ty) const override;
326 
327  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
328  unsigned Index) const override;
329 
330  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
331 
332  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
333 
334  bool supportSplitCSR(MachineFunction *MF) const override;
335  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
337  MachineBasicBlock *Entry,
338  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
339 
341  bool isVarArg,
343  const SDLoc &DL, SelectionDAG &DAG,
344  SmallVectorImpl<SDValue> &InVals) const override;
345 
346  bool CanLowerReturn(CallingConv::ID CallConv,
347  MachineFunction &MF, bool isVarArg,
349  LLVMContext &Context) const override;
350 
351  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
353  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
354  SelectionDAG &DAG) const override;
355 
356  void passSpecialInputs(
357  CallLoweringInfo &CLI,
358  CCState &CCInfo,
360  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
361  SmallVectorImpl<SDValue> &MemOpChains,
362  SDValue Chain) const;
363 
364  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
365  CallingConv::ID CallConv, bool isVarArg,
367  const SDLoc &DL, SelectionDAG &DAG,
368  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
369  SDValue ThisVal) const;
370 
371  bool mayBeEmittedAsTailCall(const CallInst *) const override;
372 
374  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
376  const SmallVectorImpl<SDValue> &OutVals,
377  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
378 
379  SDValue LowerCall(CallLoweringInfo &CLI,
380  SmallVectorImpl<SDValue> &InVals) const override;
381 
384 
385  Register getRegisterByName(const char* RegName, LLT VT,
386  const MachineFunction &MF) const override;
387 
389  MachineBasicBlock *BB) const;
390 
393  MachineBasicBlock *BB) const;
394 
397  MachineBasicBlock *BB) const override;
398 
399  bool hasBitPreservingFPLogic(EVT VT) const override;
400  bool hasAtomicFaddRtnForTy(SDValue &Op) const;
401  bool enableAggressiveFMAFusion(EVT VT) const override;
402  bool enableAggressiveFMAFusion(LLT Ty) const override;
404  EVT VT) const override;
405  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
406  LLT getPreferredShiftAmountTy(LLT Ty) const override;
407 
409  EVT VT) const override;
411  const LLT Ty) const override;
412  bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
413  bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
414 
418  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
419 
421  SelectionDAG &DAG) const override;
422 
423  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
424  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
425  void AddIMGInit(MachineInstr &MI) const;
427  SDNode *Node) const override;
428 
430 
432  SDValue Ptr) const;
434  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
435  std::pair<unsigned, const TargetRegisterClass *>
437  StringRef Constraint, MVT VT) const override;
438  ConstraintType getConstraintType(StringRef Constraint) const override;
440  std::string &Constraint,
441  std::vector<SDValue> &Ops,
442  SelectionDAG &DAG) const override;
443  bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
445  const std::string &Constraint,
446  uint64_t Val) const;
448  uint64_t Val,
449  unsigned MaxSize = 64) const;
450  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
451  SDValue V) const;
452 
453  void finalizeLowering(MachineFunction &MF) const override;
454 
455  void computeKnownBitsForFrameIndex(int FrameIdx,
456  KnownBits &Known,
457  const MachineFunction &MF) const override;
459  KnownBits &Known,
460  const APInt &DemandedElts,
461  const MachineRegisterInfo &MRI,
462  unsigned Depth = 0) const override;
463 
465  const MachineRegisterInfo &MRI,
466  unsigned Depth = 0) const override;
467  bool isSDNodeSourceOfDivergence(const SDNode *N,
468  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
469 
470  bool hasMemSDNodeUser(SDNode *N) const;
471 
473  SDValue N1) const override;
474 
476  unsigned MaxDepth = 5) const;
478  unsigned MaxDepth = 5) const;
479  bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
480  bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
481 
482  bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
483  const TargetRegisterInfo *TRI,
484  const TargetInstrInfo *TII, unsigned &PhysReg,
485  int &Cost) const override;
486 
488  const SelectionDAG &DAG,
489  bool SNaN = false,
490  unsigned Depth = 0) const override;
496  void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
497 
499  bool isDivergent) const override;
501  const Value *V) const override;
502  Align getPrefLoopAlignment(MachineLoop *ML) const override;
503 
504  void allocateHSAUserSGPRs(CCState &CCInfo,
505  MachineFunction &MF,
506  const SIRegisterInfo &TRI,
507  SIMachineFunctionInfo &Info) const;
508 
509  void allocateSystemSGPRs(CCState &CCInfo,
510  MachineFunction &MF,
512  CallingConv::ID CallConv,
513  bool IsShader) const;
514 
516  MachineFunction &MF,
517  const SIRegisterInfo &TRI,
518  SIMachineFunctionInfo &Info) const;
520  CCState &CCInfo,
521  MachineFunction &MF,
522  const SIRegisterInfo &TRI,
523  SIMachineFunctionInfo &Info) const;
524 
525  void allocateSpecialInputVGPRs(CCState &CCInfo,
526  MachineFunction &MF,
527  const SIRegisterInfo &TRI,
528  SIMachineFunctionInfo &Info) const;
530  MachineFunction &MF,
531  const SIRegisterInfo &TRI,
532  SIMachineFunctionInfo &Info) const;
533 
535  getTargetMMOFlags(const Instruction &I) const override;
536 };
537 
538 } // End namespace llvm
539 
540 #endif
llvm::SITargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SIISelLowering.cpp:4434
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1582
llvm::SITargetLowering::bundleInstWithWaitcnt
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
Definition: SIISelLowering.cpp:3529
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4550
llvm::SITargetLowering::isNonGlobalAddrSpace
static bool isNonGlobalAddrSpace(unsigned AS)
Definition: SIISelLowering.cpp:1577
llvm::SITargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SIISelLowering.cpp:817
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2147
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::SITargetLowering::getAsmOperandConstVal
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
Definition: SIISelLowering.cpp:12361
llvm::SITargetLowering::emitExpandAtomicRMW
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override
Perform a atomicrmw expansion using a target-specific way.
Definition: SIISelLowering.cpp:13111
llvm::SITargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override
LLT handling variant.
Definition: SIISelLowering.h:296
llvm::SITargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SIISelLowering.cpp:1601
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2897
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SITargetLowering::checkForPhysRegDependency
bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const override
Allows the target to handle physreg-carried dependency in target-specific way.
Definition: SIISelLowering.cpp:13086
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::SITargetLowering::LowerCallResult
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Definition: SIISelLowering.cpp:2708
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2344
llvm::SITargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: SIISelLowering.cpp:12485
llvm::MemOp
Definition: TargetLowering.h:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::SITargetLowering::allocateHSAUserSGPRs
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2086
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SITargetLowering::isFMADLegal
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
Definition: SIISelLowering.cpp:4556
llvm::AttributeList
Definition: Attributes.h:430
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SITargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: SIISelLowering.cpp:6009
llvm::SITargetLowering::shouldEmitFixup
bool shouldEmitFixup(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5151
llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SIISelLowering.cpp:4498
llvm::SITargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SIISelLowering.cpp:12195
llvm::SITargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SIISelLowering.cpp:2614
llvm::MemSDNode
This is an abstract virtual class for memory operations.
Definition: SelectionDAGNodes.h:1275
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SITargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: SIISelLowering.cpp:2319
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:772
llvm::SITargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: SIISelLowering.cpp:947
llvm::SITargetLowering::getTargetMMOFlags
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
Definition: SIISelLowering.cpp:13079
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::SITargetLowering::shouldExpandAtomicLoadInIR
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Definition: SIISelLowering.cpp:12940
llvm::SITargetLowering::SITargetLowering
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
Definition: SIISelLowering.cpp:78
llvm::SITargetLowering::legalizeTargetIndependentNode
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
Definition: SIISelLowering.cpp:11848
llvm::SITargetLowering::isReassocProfitable
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
Definition: SIISelLowering.cpp:13065
llvm::SITargetLowering::PostISelFolding
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
Definition: SIISelLowering.cpp:11893
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::SITargetLowering::getSubtarget
const GCNSubtarget * getSubtarget() const
Definition: SIISelLowering.cpp:779
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::SITargetLowering::hasAtomicFaddRtnForTy
bool hasAtomicFaddRtnForTy(SDValue &Op) const
Definition: SIISelLowering.cpp:4438
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SITargetLowering::denormalsEnabledForType
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
Definition: SIISelLowering.cpp:12775
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::SITargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SIISelLowering.cpp:12345
llvm::User
Definition: User.h:44
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2491
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SITargetLowering::getRegClassFor
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
Definition: SIISelLowering.cpp:12961
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::SITargetLowering::splitUnaryVectorOp
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4578
llvm::SITargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SIISelLowering.cpp:2597
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3903
Param
Value * Param
Definition: NVPTXLowerArgs.cpp:165
llvm::SITargetLowering::emitGWSMemViolTestLoop
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3543
llvm::SITargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Definition: SIISelLowering.cpp:12058
llvm::SITargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SIISelLowering.cpp:3428
llvm::SITargetLowering::requiresUniformRegister
bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
Definition: SIISelLowering.cpp:13027
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::SITargetLowering::computeKnownBitsForFrameIndex
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Definition: SIISelLowering.cpp:12540
llvm::SITargetLowering::checkAsmConstraintVal
bool checkAsmConstraintVal(SDValue Op, const std::string &Constraint, uint64_t Val) const
Definition: SIISelLowering.cpp:12395
llvm::Instruction
Definition: Instruction.h:42
AMDGPUISelLowering.h
llvm::SITargetLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:2974
llvm::SITargetLowering::isLegalGlobalAddressingMode
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
Definition: SIISelLowering.cpp:1229
llvm::LegacyDivergenceAnalysis
Definition: LegacyDivergenceAnalysis.h:31
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::SITargetLowering::computeKnownBitsForTargetInstr
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SIISelLowering.cpp:12557
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3367
llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const
Definition: SIISelLowering.cpp:1382
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:2035
llvm::SITargetLowering::getAddrModeArguments
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
Definition: SIISelLowering.cpp:1186
llvm::SITargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SIISelLowering.cpp:3061
llvm::APFloat
Definition: APFloat.h:716
llvm::AArch64PACKey::DA
@ DA
Definition: AArch64BaseInfo.h:821
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::SITargetLowering::splitTernaryVectorOp
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4622
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::SITargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: SIISelLowering.cpp:2315
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::SITargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SIISelLowering.cpp:843
llvm::SITargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SIISelLowering.cpp:4471
llvm::SITargetLowering::isSDNodeSourceOfDivergence
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
Definition: SIISelLowering.cpp:12708
llvm::SITargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: SIISelLowering.cpp:1369
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SITargetLowering::hasMemSDNodeUser
bool hasMemSDNodeUser(SDNode *N) const
Definition: SIISelLowering.cpp:13054
llvm::SITargetLowering::isMemOpHasNoClobberedMemOperand
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
Definition: SIISelLowering.cpp:1572
llvm::SITargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: SIISelLowering.cpp:1623
llvm::SITargetLowering::splitKillBlock
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3477
llvm::SITargetLowering::shouldEmitGOTReloc
bool shouldEmitGOTReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5158
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::SITargetLowering::shouldUseLDSConstAddress
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5171
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:2014
llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: SIISelLowering.cpp:869
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::SITargetLowering::copyToM0
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
Definition: SIISelLowering.cpp:6124
llvm::SITargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SIISelLowering.cpp:4989
llvm::SITargetLowering::shouldExpandAtomicCmpXchgInIR
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: SIISelLowering.cpp:12954
llvm::SITargetLowering::computeKnownAlignForTargetInstr
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
Definition: SIISelLowering.cpp:12599
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SITargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: SIISelLowering.cpp:4463
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SITargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: SIISelLowering.cpp:12829
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SITargetLowering::getPreferredShiftAmountTy
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Definition: SIISelLowering.cpp:4477
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::SITargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: SIISelLowering.cpp:2310
Node
Definition: ItaniumDemangle.h:156
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::SITargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SIISelLowering.cpp:11547
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:714
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::SITargetLowering::isKnownNeverNaNForTargetNode
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
Definition: SIISelLowering.cpp:12801
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:1082
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1892
llvm::SITargetLowering::buildRSRC
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
Definition: SIISelLowering.cpp:12160
llvm::SITargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SIISelLowering.cpp:4653
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:1048
llvm::SITargetLowering::isMemOpUniform
bool isMemOpUniform(const SDNode *N) const
Definition: SIISelLowering.cpp:1594
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1759
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::SITargetLowering::wrapAddr64Rsrc
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
Definition: SIISelLowering.cpp:12125
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::SITargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: SIISelLowering.cpp:12620
llvm::SITargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: SIISelLowering.cpp:1608
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::SITargetLowering::isFPExtFoldable
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition: SIISelLowering.cpp:791
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3414
llvm::SITargetLowering::passSpecialInputs
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
Definition: SIISelLowering.cpp:2766
llvm::SITargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SIISelLowering.cpp:2354
llvm::SITargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SIISelLowering.cpp:3977
N
#define N
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:351
llvm::SITargetLowering::isFreeAddrSpaceCast
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: SIISelLowering.cpp:1582
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2572
llvm::SITargetLowering::checkAsmConstraintValA
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
Definition: SIISelLowering.cpp:12428
llvm::SITargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: SIISelLowering.cpp:4450
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl< Value * >
llvm::SITargetLowering::shouldEmitPCReloc
bool shouldEmitPCReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:5167
llvm::SITargetLowering::splitBinaryVectorOp
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4598
RegName
#define RegName(no)
llvm::SITargetLowering::AddIMGInit
void AddIMGInit(MachineInstr &MI) const
Definition: SIISelLowering.cpp:11971
llvm::SITargetLowering::shouldExpandAtomicStoreInIR
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
Definition: SIISelLowering.cpp:12947
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1473
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SITargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: SIISelLowering.cpp:811
llvm::SITargetLowering::shouldExpandVectorDynExt
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx, const GCNSubtarget *Subtarget)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
Definition: SIISelLowering.cpp:10693
llvm::SITargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Definition: SIISelLowering.cpp:1614
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1314
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2048
llvm::SITargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SIISelLowering.cpp:1554
MachineFunction.h
AMDGPUArgumentUsageInfo.h
llvm::AMDGPUTargetLowering::ImplicitParameter
ImplicitParameter
Definition: AMDGPUISelLowering.h:324
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:23
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:509
llvm::SITargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SIISelLowering.cpp:1287
llvm::SITargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SIISelLowering.cpp:3050
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:10038
llvm::SITargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SIISelLowering.cpp:12322
llvm::LLT
Definition: LowLevelTypeImpl.h:39