LLVM 18.0.0git
SIISelLowering.h
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1//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI DAG Lowering interface definition
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16
17#include "AMDGPUISelLowering.h"
20
21namespace llvm {
22
23class GCNSubtarget;
24class SIMachineFunctionInfo;
25class SIRegisterInfo;
26
27namespace AMDGPU {
28struct ImageDimIntrinsicInfo;
29}
30
32private:
33 const GCNSubtarget *Subtarget;
34
35public:
38 EVT VT) const override;
41 EVT VT) const override;
42
44 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
45 unsigned &NumIntermediates, MVT &RegisterVT) const override;
46
47private:
48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
49 SDValue Chain, uint64_t Offset) const;
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
53 const SDLoc &SL, SDValue Chain,
54 uint64_t Offset, Align Alignment,
55 bool Signed,
56 const ISD::InputArg *Arg = nullptr) const;
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
58 Align Alignment,
59 ImplicitParameter Param) const;
60
61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
62 const SDLoc &SL, SDValue Chain,
63 const ISD::InputArg &Arg) const;
64 SDValue getPreloadedValue(SelectionDAG &DAG,
65 const SIMachineFunctionInfo &MFI,
66 EVT VT,
68
69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
70 SelectionDAG &DAG) const override;
71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
72 MVT VT, unsigned Offset) const;
74 SelectionDAG &DAG, bool WithChain) const;
75 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
76 SDValue CachePolicy, SelectionDAG &DAG) const;
77
78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
79 unsigned NewOpcode) const;
80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
81 unsigned NewOpcode) const;
82
83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
84 const ArgDescriptor &ArgDesc) const;
85
86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
89
90 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
91 // (the offset that is included in bounds checking and swizzling, to be split
92 // between the instruction's voffset and immoffset fields) and soffset (the
93 // offset that is excluded from bounds checking and swizzling, to go in the
94 // instruction's soffset field). This function takes the first kind of
95 // offset and figures out how to split it between voffset and immoffset.
96 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
97 SelectionDAG &DAG) const;
98
99 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
100 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
102 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
103 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
104 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
108 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerFFREXP(SDValue Op, SelectionDAG &DAG) const;
110 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
112 SDValue lowerFSQRTF16(SDValue Op, SelectionDAG &DAG) const;
113 SDValue lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const;
114 SDValue lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const;
115 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
116 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
117 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
118 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
120 bool IsIntrinsic = false) const;
121
122 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
123 ArrayRef<SDValue> Ops) const;
124
125 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
126 // dwordx4 if on SI.
127 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
128 ArrayRef<SDValue> Ops, EVT MemVT,
129 MachineMemOperand *MMO, SelectionDAG &DAG) const;
130
131 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
132 bool ImageStore = false) const;
133
134 /// Converts \p Op, which must be of floating point type, to the
135 /// floating point type \p VT, by either extending or truncating it.
136 SDValue getFPExtOrFPRound(SelectionDAG &DAG,
137 SDValue Op,
138 const SDLoc &DL,
139 EVT VT) const;
140
141 SDValue convertArgType(
142 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
143 bool Signed, const ISD::InputArg *Arg = nullptr) const;
144
145 /// Custom lowering for ISD::FP_ROUND for MVT::f16.
146 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
147 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
148 SDValue lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const;
149 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
150 SDValue lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
151
152 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
153 SelectionDAG &DAG) const;
154
155 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
156 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
157 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
158 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
159 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
160 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
161 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
162
163 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
164 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
165 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
166 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
167 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
168
169 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
170
171 SDValue performUCharToFloatCombine(SDNode *N,
172 DAGCombinerInfo &DCI) const;
173 SDValue performFCopySignCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174
175 SDValue performSHLPtrCombine(SDNode *N,
176 unsigned AS,
177 EVT MemVT,
178 DAGCombinerInfo &DCI) const;
179
180 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
181
182 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
183 unsigned Opc, SDValue LHS,
184 const ConstantSDNode *CRHS) const;
185
186 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
188 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
189 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
190 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
191 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
192 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
193 const APFloat &C) const;
194 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195
196 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
197 SDValue Op0, SDValue Op1) const;
198 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
199 SDValue Src, SDValue MinVal, SDValue MaxVal,
200 bool Signed) const;
201 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
202 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
203 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
204 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
205 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
206 SDValue performFPRoundCombine(SDNode *N, DAGCombinerInfo &DCI) const;
207
208 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
209 unsigned getFusedOpcode(const SelectionDAG &DAG,
210 const SDNode *N0, const SDNode *N1) const;
211 SDValue tryFoldToMad64_32(SDNode *N, DAGCombinerInfo &DCI) const;
212 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
213 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
214 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
215 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
216 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
217 SDValue performFDivCombine(SDNode *N, DAGCombinerInfo &DCI) const;
218 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
219 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
220 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
221 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
222 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
223
224 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
225 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
226
227 unsigned isCFIntrinsic(const SDNode *Intr) const;
228
229public:
230 /// \returns True if fixup needs to be emitted for given global value \p GV,
231 /// false otherwise.
232 bool shouldEmitFixup(const GlobalValue *GV) const;
233
234 /// \returns True if GOT relocation needs to be emitted for given global value
235 /// \p GV, false otherwise.
236 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
237
238 /// \returns True if PC-relative relocation needs to be emitted for given
239 /// global value \p GV, false otherwise.
240 bool shouldEmitPCReloc(const GlobalValue *GV) const;
241
242 /// \returns true if this should use a literal constant for an LDS address,
243 /// and not emit a relocation for an LDS global.
244 bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
245
246 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
247 /// expanded into a set of cmp/select instructions.
248 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
249 bool IsDivergentIdx,
250 const GCNSubtarget *Subtarget);
251
252 bool shouldExpandVectorDynExt(SDNode *N) const;
253
254private:
255 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
256 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
257 // pointed to by Offsets.
258 void setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
259 SDValue *Offsets, Align Alignment = Align(4)) const;
260
261 // Convert the i128 that an addrspace(8) pointer is natively represented as
262 // into the v4i32 that all the buffer intrinsics expect to receive. We can't
263 // add register classes for i128 on pain of the promotion logic going haywire,
264 // so this slightly ugly hack is what we've got. If passed a non-pointer
265 // argument (as would be seen in older buffer intrinsics), does nothing.
266 SDValue bufferRsrcPtrToVector(SDValue MaybePointer, SelectionDAG &DAG) const;
267
268 // Wrap a 64-bit pointer into a v4i32 (which is how all SelectionDAG code
269 // represents ptr addrspace(8)) using the flags specified in the intrinsic.
270 SDValue lowerPointerAsRsrcIntrin(SDNode *Op, SelectionDAG &DAG) const;
271
272 // Handle 8 bit and 16 bit buffer loads
273 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
274 ArrayRef<SDValue> Ops, MemSDNode *M) const;
275
276 // Handle 8 bit and 16 bit buffer stores
277 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
278 SDLoc DL, SDValue Ops[],
279 MemSDNode *M) const;
280
281public:
282 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
283
284 const GCNSubtarget *getSubtarget() const;
285
286 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
287 EVT SrcVT) const override;
288
289 bool isFPExtFoldable(const MachineInstr &MI, unsigned Opcode, LLT DestTy,
290 LLT SrcTy) const override;
291
292 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
293
294 // While address space 7 should never make it to codegen, it still needs to
295 // have a MVT to prevent some analyses that query this function from breaking,
296 // so, to work around the lack of i160, map it to v5i32.
297 MVT getPointerTy(const DataLayout &DL, unsigned AS) const override;
298 MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override;
299
301 MachineFunction &MF,
302 unsigned IntrinsicID) const override;
303
306 Type *&/*AccessTy*/) const override;
307
308 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
309 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
310 unsigned AS,
311 Instruction *I = nullptr) const override;
312
313 bool canMergeStoresTo(unsigned AS, EVT MemVT,
314 const MachineFunction &MF) const override;
315
317 unsigned Size, unsigned AddrSpace, Align Alignment,
319 unsigned *IsFast = nullptr) const;
320
322 LLT Ty, unsigned AddrSpace, Align Alignment,
324 unsigned *IsFast = nullptr) const override {
325 if (IsFast)
326 *IsFast = 0;
328 Alignment, Flags, IsFast);
329 }
330
332 EVT VT, unsigned AS, Align Alignment,
334 unsigned *IsFast = nullptr) const override;
335
337 const AttributeList &FuncAttributes) const override;
338
339 bool isMemOpUniform(const SDNode *N) const;
340 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
341
342 static bool isNonGlobalAddrSpace(unsigned AS);
343
344 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
345
347 getPreferredVectorAction(MVT VT) const override;
348
350 Type *Ty) const override;
351
352 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
353 unsigned Index) const override;
354
355 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
356
357 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
358
359 unsigned combineRepeatedFPDivisors() const override {
360 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
361 // reciprocal.
362 return 2;
363 }
364
365 bool supportSplitCSR(MachineFunction *MF) const override;
366 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
368 MachineBasicBlock *Entry,
369 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
370
372 bool isVarArg,
374 const SDLoc &DL, SelectionDAG &DAG,
375 SmallVectorImpl<SDValue> &InVals) const override;
376
377 bool CanLowerReturn(CallingConv::ID CallConv,
378 MachineFunction &MF, bool isVarArg,
380 LLVMContext &Context) const override;
381
382 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
384 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
385 SelectionDAG &DAG) const override;
386
388 CallLoweringInfo &CLI,
389 CCState &CCInfo,
391 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
392 SmallVectorImpl<SDValue> &MemOpChains,
393 SDValue Chain) const;
394
396 CallingConv::ID CallConv, bool isVarArg,
398 const SDLoc &DL, SelectionDAG &DAG,
399 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
400 SDValue ThisVal) const;
401
402 bool mayBeEmittedAsTailCall(const CallInst *) const override;
403
405 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
407 const SmallVectorImpl<SDValue> &OutVals,
408 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
409
410 SDValue LowerCall(CallLoweringInfo &CLI,
411 SmallVectorImpl<SDValue> &InVals) const override;
412
417
418 Register getRegisterByName(const char* RegName, LLT VT,
419 const MachineFunction &MF) const override;
420
422 MachineBasicBlock *BB) const;
423
426 MachineBasicBlock *BB) const;
427
430 MachineBasicBlock *BB) const override;
431
432 bool hasAtomicFaddRtnForTy(SDValue &Op) const;
433 bool enableAggressiveFMAFusion(EVT VT) const override;
434 bool enableAggressiveFMAFusion(LLT Ty) const override;
436 EVT VT) const override;
437 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
438 LLT getPreferredShiftAmountTy(LLT Ty) const override;
439
441 EVT VT) const override;
443 const LLT Ty) const override;
444 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
445 bool isFMADLegal(const MachineInstr &MI, const LLT Ty) const override;
446
450 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
451
453 SelectionDAG &DAG) const override;
454
455 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
456 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
457 void AddIMGInit(MachineInstr &MI) const;
459 SDNode *Node) const override;
460
462
464 SDValue Ptr) const;
466 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
467 std::pair<unsigned, const TargetRegisterClass *>
469 StringRef Constraint, MVT VT) const override;
470 ConstraintType getConstraintType(StringRef Constraint) const override;
472 std::vector<SDValue> &Ops,
473 SelectionDAG &DAG) const override;
474 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
475 bool checkAsmConstraintVal(SDValue Op, StringRef Constraint,
476 uint64_t Val) const;
478 uint64_t Val,
479 unsigned MaxSize = 64) const;
480 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
481 SDValue V) const;
482
483 void finalizeLowering(MachineFunction &MF) const override;
484
486 const APInt &DemandedElts,
487 const SelectionDAG &DAG,
488 unsigned Depth = 0) const override;
489 void computeKnownBitsForFrameIndex(int FrameIdx,
490 KnownBits &Known,
491 const MachineFunction &MF) const override;
493 KnownBits &Known,
494 const APInt &DemandedElts,
496 unsigned Depth = 0) const override;
497
500 unsigned Depth = 0) const override;
502 UniformityInfo *UA) const override;
503
504 bool hasMemSDNodeUser(SDNode *N) const;
505
507 SDValue N1) const override;
508
510 Register N1) const override;
511
513 unsigned MaxDepth = 5) const;
515 unsigned MaxDepth = 5) const;
516 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
517 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
518
519 bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
520 const TargetRegisterInfo *TRI,
521 const TargetInstrInfo *TII, unsigned &PhysReg,
522 int &Cost) const override;
523
525 const SelectionDAG &DAG,
526 bool SNaN = false,
527 unsigned Depth = 0) const override;
533 void emitExpandAtomicRMW(AtomicRMWInst *AI) const override;
534
535 LoadInst *
537
539 bool isDivergent) const override;
541 const Value *V) const override;
542 Align getPrefLoopAlignment(MachineLoop *ML) const override;
543
544 void allocateHSAUserSGPRs(CCState &CCInfo,
545 MachineFunction &MF,
546 const SIRegisterInfo &TRI,
548
552 MachineFunction &MF,
553 const SIRegisterInfo &TRI,
555
557 const SIRegisterInfo &TRI,
559
560 void allocateSystemSGPRs(CCState &CCInfo,
561 MachineFunction &MF,
563 CallingConv::ID CallConv,
564 bool IsShader) const;
565
567 MachineFunction &MF,
568 const SIRegisterInfo &TRI,
571 CCState &CCInfo,
572 MachineFunction &MF,
573 const SIRegisterInfo &TRI,
575
577 MachineFunction &MF,
578 const SIRegisterInfo &TRI,
581 MachineFunction &MF,
582 const SIRegisterInfo &TRI,
584
586 getTargetMMOFlags(const Instruction &I) const override;
587};
588
589// Returns true if argument is a boolean value which is not serialized into
590// memory or argument and does not require v_cndmask_b32 to be deserialized.
591bool isBoolSGPR(SDValue V);
592
593} // End namespace llvm
594
595#endif
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
unsigned Intr
Interface definition of the TargetLowering class that is common to all AMD GPUs.
Function Alias Analysis Results
block Block Frequency Analysis
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
LLVMContext & Context
Value * LHS
static constexpr uint32_t Opcode
Definition: aarch32.h:200
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:183
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:68
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const
bool checkForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) const override
Allows the target to handle physreg-carried dependency in target-specific way.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
MVT getPointerTy(const DataLayout &DL, unsigned AS) const override
Map address space 7 to MVT::v5i32 because that's its in-memory representation.
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
const GCNSubtarget * getSubtarget() const
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
bool shouldEmitGOTReloc(const GlobalValue *GV) const
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
bool hasAtomicFaddRtnForTy(SDValue &Op) const
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
void AddIMGInit(MachineInstr &MI) const
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool isMemOpUniform(const SDNode *N) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool shouldEmitFixup(const GlobalValue *GV) const
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
bool hasMemSDNodeUser(SDNode *N) const
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const override
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
static bool isNonGlobalAddrSpace(unsigned AS)
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue > > &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) const
void emitExpandAtomicRMW(AtomicRMWInst *AI) const override
Perform a atomicrmw expansion using a target-specific way.
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx, const GCNSubtarget *Subtarget)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *IsFast=nullptr) const override
LLT handling variant.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
unsigned combineRepeatedFPDivisors() const override
Indicate whether this target prefers to combine FDIVs with the same divisor.
bool canMergeStoresTo(unsigned AS, EVT MemVT, const MachineFunction &MF) const override
Returns if it's reasonable to merge stores to MemVT size.
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
bool shouldEmitPCReloc(const GlobalValue *GV) const
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
void allocatePreloadKernArgSGPRs(CCState &CCInfo, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ISD::InputArg > &Ins, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
MVT getPointerMemTy(const DataLayout &DL, unsigned AS) const override
Similarly, the in-memory representation of a p7 is {p8, i32}, aka v8i32 when padding is added.
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
bool isBoolSGPR(SDValue V)
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...