LLVM  13.0.0git
SIISelLowering.h
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1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// SI DAG Lowering interface definition
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 
17 #include "AMDGPUISelLowering.h"
19 
20 namespace llvm {
21 
22 class GCNSubtarget;
23 class SIMachineFunctionInfo;
24 class SIRegisterInfo;
25 
26 namespace AMDGPU {
27 struct ImageDimIntrinsicInfo;
28 }
29 
30 class SITargetLowering final : public AMDGPUTargetLowering {
31 private:
32  const GCNSubtarget *Subtarget;
33 
34 public:
36  CallingConv::ID CC,
37  EVT VT) const override;
39  CallingConv::ID CC,
40  EVT VT) const override;
41 
43  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
44  unsigned &NumIntermediates, MVT &RegisterVT) const override;
45 
46 private:
47  SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
48  SDValue Chain, uint64_t Offset) const;
49  SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
50  SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
51  const SDLoc &SL, SDValue Chain,
52  uint64_t Offset, Align Alignment,
53  bool Signed,
54  const ISD::InputArg *Arg = nullptr) const;
55 
56  SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
57  const SDLoc &SL, SDValue Chain,
58  const ISD::InputArg &Arg) const;
59  SDValue getPreloadedValue(SelectionDAG &DAG,
60  const SIMachineFunctionInfo &MFI,
61  EVT VT,
63 
64  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
65  SelectionDAG &DAG) const override;
66  SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
67  MVT VT, unsigned Offset) const;
69  SelectionDAG &DAG, bool WithChain) const;
70  SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset,
71  SDValue CachePolicy, SelectionDAG &DAG) const;
72 
73  SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
74  unsigned NewOpcode) const;
75  SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
76  unsigned NewOpcode) const;
77 
78  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
79  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
80  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
81 
82  // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset
83  // (the offset that is included in bounds checking and swizzling, to be split
84  // between the instruction's voffset and immoffset fields) and soffset (the
85  // offset that is excluded from bounds checking and swizzling, to go in the
86  // instruction's soffset field). This function takes the first kind of
87  // offset and figures out how to split it between voffset and immoffset.
88  std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset,
89  SelectionDAG &DAG) const;
90 
91  SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const;
92  SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
94  SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
95  SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const;
96  SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
97  SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
98  SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
99  SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
100  SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
101  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
102  SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
103  SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
104  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
105  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
106  SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
108  bool IsIntrinsic = false) const;
109 
110  SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG,
111  ArrayRef<SDValue> Ops) const;
112 
113  // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
114  // dwordx4 if on SI.
115  SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
116  ArrayRef<SDValue> Ops, EVT MemVT,
117  MachineMemOperand *MMO, SelectionDAG &DAG) const;
118 
119  SDValue handleD16VData(SDValue VData, SelectionDAG &DAG,
120  bool ImageStore = false) const;
121 
122  /// Converts \p Op, which must be of floating point type, to the
123  /// floating point type \p VT, by either extending or truncating it.
124  SDValue getFPExtOrFPRound(SelectionDAG &DAG,
125  SDValue Op,
126  const SDLoc &DL,
127  EVT VT) const;
128 
129  SDValue convertArgType(
130  SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
131  bool Signed, const ISD::InputArg *Arg = nullptr) const;
132 
133  /// Custom lowering for ISD::FP_ROUND for MVT::f16.
134  SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
135  SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const;
136  SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const;
137 
138  SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
139  SelectionDAG &DAG) const;
140 
141  SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
142  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
143  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
144  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
145  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
146  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
147 
148  SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
149  SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
150  SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
151  SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
152  SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
153 
154  SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
155 
156  SDValue performUCharToFloatCombine(SDNode *N,
157  DAGCombinerInfo &DCI) const;
158  SDValue performSHLPtrCombine(SDNode *N,
159  unsigned AS,
160  EVT MemVT,
161  DAGCombinerInfo &DCI) const;
162 
163  SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
164 
165  SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
166  unsigned Opc, SDValue LHS,
167  const ConstantSDNode *CRHS) const;
168 
169  SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
170  SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
171  SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
172  SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
173  SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
174  SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
175  SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT,
176  const APFloat &C) const;
177  SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
178 
179  SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
180  SDValue Op0, SDValue Op1) const;
181  SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
182  SDValue Op0, SDValue Op1, bool Signed) const;
183  SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
184  SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
185  SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
186  SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
187  SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
188 
189  SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const;
190  unsigned getFusedOpcode(const SelectionDAG &DAG,
191  const SDNode *N0, const SDNode *N1) const;
192  SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
193  SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
194  SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
195  SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
196  SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
197  SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const;
198  SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
199  SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
200  SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const;
201  SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
202 
203  bool isLegalFlatAddressingMode(const AddrMode &AM) const;
204  bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
205 
206  unsigned isCFIntrinsic(const SDNode *Intr) const;
207 
208 public:
209  /// \returns True if fixup needs to be emitted for given global value \p GV,
210  /// false otherwise.
211  bool shouldEmitFixup(const GlobalValue *GV) const;
212 
213  /// \returns True if GOT relocation needs to be emitted for given global value
214  /// \p GV, false otherwise.
215  bool shouldEmitGOTReloc(const GlobalValue *GV) const;
216 
217  /// \returns True if PC-relative relocation needs to be emitted for given
218  /// global value \p GV, false otherwise.
219  bool shouldEmitPCReloc(const GlobalValue *GV) const;
220 
221  /// \returns true if this should use a literal constant for an LDS address,
222  /// and not emit a relocation for an LDS global.
223  bool shouldUseLDSConstAddress(const GlobalValue *GV) const;
224 
225  /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be
226  /// expanded into a set of cmp/select instructions.
227  static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem,
228  bool IsDivergentIdx);
229 
230 private:
231  // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the
232  // three offsets (voffset, soffset and instoffset) into the SDValue[3] array
233  // pointed to by Offsets.
234  /// \returns 0 If there is a non-constant offset or if the offset is 0.
235  /// Otherwise returns the constant offset.
236  unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG,
237  SDValue *Offsets, Align Alignment = Align(4)) const;
238 
239  // Handle 8 bit and 16 bit buffer loads
240  SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL,
241  ArrayRef<SDValue> Ops, MemSDNode *M) const;
242 
243  // Handle 8 bit and 16 bit buffer stores
244  SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType,
245  SDLoc DL, SDValue Ops[],
246  MemSDNode *M) const;
247 
248 public:
249  SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI);
250 
251  const GCNSubtarget *getSubtarget() const;
252 
253  bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
254  EVT SrcVT) const override;
255 
256  bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
257 
258  bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
259  MachineFunction &MF,
260  unsigned IntrinsicID) const override;
261 
262  bool getAddrModeArguments(IntrinsicInst * /*I*/,
263  SmallVectorImpl<Value*> &/*Ops*/,
264  Type *&/*AccessTy*/) const override;
265 
266  bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
267  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
268  unsigned AS,
269  Instruction *I = nullptr) const override;
270 
271  bool canMergeStoresTo(unsigned AS, EVT MemVT,
272  const SelectionDAG &DAG) const override;
273 
275  unsigned Size, unsigned AddrSpace, Align Alignment,
277  bool *IsFast = nullptr) const;
278 
280  LLT Ty, unsigned AddrSpace, Align Alignment,
282  bool *IsFast = nullptr) const override {
283  if (IsFast)
284  *IsFast = false;
285  return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace,
286  Alignment, Flags, IsFast);
287  }
288 
290  EVT VT, unsigned AS, Align Alignment,
292  bool *IsFast = nullptr) const override;
293 
295  const AttributeList &FuncAttributes) const override;
296 
297  bool isMemOpUniform(const SDNode *N) const;
298  bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
299 
300  static bool isNonGlobalAddrSpace(unsigned AS);
301 
302  bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
303 
305  getPreferredVectorAction(MVT VT) const override;
306 
308  Type *Ty) const override;
309 
310  bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
311 
312  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
313 
314  bool supportSplitCSR(MachineFunction *MF) const override;
315  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
317  MachineBasicBlock *Entry,
318  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
319 
321  bool isVarArg,
323  const SDLoc &DL, SelectionDAG &DAG,
324  SmallVectorImpl<SDValue> &InVals) const override;
325 
326  bool CanLowerReturn(CallingConv::ID CallConv,
327  MachineFunction &MF, bool isVarArg,
329  LLVMContext &Context) const override;
330 
331  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
333  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
334  SelectionDAG &DAG) const override;
335 
336  void passSpecialInputs(
337  CallLoweringInfo &CLI,
338  CCState &CCInfo,
340  SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
341  SmallVectorImpl<SDValue> &MemOpChains,
342  SDValue Chain) const;
343 
344  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
345  CallingConv::ID CallConv, bool isVarArg,
347  const SDLoc &DL, SelectionDAG &DAG,
348  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
349  SDValue ThisVal) const;
350 
351  bool mayBeEmittedAsTailCall(const CallInst *) const override;
352 
354  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
356  const SmallVectorImpl<SDValue> &OutVals,
357  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
358 
359  SDValue LowerCall(CallLoweringInfo &CLI,
360  SmallVectorImpl<SDValue> &InVals) const override;
361 
364 
365  Register getRegisterByName(const char* RegName, LLT VT,
366  const MachineFunction &MF) const override;
367 
369  MachineBasicBlock *BB) const;
370 
373  MachineBasicBlock *BB) const;
374 
377  MachineBasicBlock *BB) const override;
378 
379  bool hasBitPreservingFPLogic(EVT VT) const override;
380  bool enableAggressiveFMAFusion(EVT VT) const override;
382  EVT VT) const override;
383  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
384  LLT getPreferredShiftAmountTy(LLT Ty) const override;
385 
387  EVT VT) const override;
388  bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override;
389 
393  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
394 
396  SelectionDAG &DAG) const override;
397 
398  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
399  SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
400  void AddIMGInit(MachineInstr &MI) const;
402  SDNode *Node) const override;
403 
405 
407  SDValue Ptr) const;
408  MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
409  uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
410  std::pair<unsigned, const TargetRegisterClass *>
412  StringRef Constraint, MVT VT) const override;
413  ConstraintType getConstraintType(StringRef Constraint) const override;
415  std::string &Constraint,
416  std::vector<SDValue> &Ops,
417  SelectionDAG &DAG) const override;
418  bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
420  const std::string &Constraint,
421  uint64_t Val) const;
423  uint64_t Val,
424  unsigned MaxSize = 64) const;
425  SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
426  SDValue V) const;
427 
428  void finalizeLowering(MachineFunction &MF) const override;
429 
430  void computeKnownBitsForFrameIndex(int FrameIdx,
431  KnownBits &Known,
432  const MachineFunction &MF) const override;
434  KnownBits &Known,
435  const APInt &DemandedElts,
436  const MachineRegisterInfo &MRI,
437  unsigned Depth = 0) const override;
438 
440  const MachineRegisterInfo &MRI,
441  unsigned Depth = 0) const override;
442  bool isSDNodeSourceOfDivergence(const SDNode *N,
443  FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override;
444 
446  unsigned MaxDepth = 5) const;
448  unsigned MaxDepth = 5) const;
449  bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const;
450  bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const;
451 
453  const SelectionDAG &DAG,
454  bool SNaN = false,
455  unsigned Depth = 0) const override;
457 
458  virtual const TargetRegisterClass *
459  getRegClassFor(MVT VT, bool isDivergent) const override;
460  virtual bool requiresUniformRegister(MachineFunction &MF,
461  const Value *V) const override;
462  Align getPrefLoopAlignment(MachineLoop *ML) const override;
463 
464  void allocateHSAUserSGPRs(CCState &CCInfo,
465  MachineFunction &MF,
466  const SIRegisterInfo &TRI,
467  SIMachineFunctionInfo &Info) const;
468 
469  void allocateSystemSGPRs(CCState &CCInfo,
470  MachineFunction &MF,
472  CallingConv::ID CallConv,
473  bool IsShader) const;
474 
476  MachineFunction &MF,
477  const SIRegisterInfo &TRI,
478  SIMachineFunctionInfo &Info) const;
480  CCState &CCInfo,
481  MachineFunction &MF,
482  const SIRegisterInfo &TRI,
483  SIMachineFunctionInfo &Info) const;
484 
485  void allocateSpecialInputVGPRs(CCState &CCInfo,
486  MachineFunction &MF,
487  const SIRegisterInfo &TRI,
488  SIMachineFunctionInfo &Info) const;
490  MachineFunction &MF,
491  const SIRegisterInfo &TRI,
492  SIMachineFunctionInfo &Info) const;
493 
494  std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL,
495  Type *Ty) const;
496 };
497 
498 } // End namespace llvm
499 
500 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::SITargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: SIISelLowering.cpp:4306
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1532
llvm::SITargetLowering::bundleInstWithWaitcnt
void bundleInstWithWaitcnt(MachineInstr &MI) const
Insert MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
Definition: SIISelLowering.cpp:3429
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4544
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4110
llvm::SITargetLowering::isNonGlobalAddrSpace
static bool isNonGlobalAddrSpace(unsigned AS)
Definition: SIISelLowering.cpp:1546
llvm::SITargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
Definition: SIISelLowering.cpp:882
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::GISelKnownBits
Definition: GISelKnownBits.h:29
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2070
llvm::SITargetLowering::getAsmOperandConstVal
bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const
Definition: SIISelLowering.cpp:11641
llvm::SITargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: SIISelLowering.cpp:1570
llvm::MachineSDNode
An SDNode that represents everything that will be needed to construct a MachineInstr.
Definition: SelectionDAGNodes.h:2518
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:50
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::SITargetLowering::LowerCallResult
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, bool isThisReturn, SDValue ThisVal) const
Definition: SIISelLowering.cpp:2623
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2251
llvm::SITargetLowering::finalizeLowering
void finalizeLowering(MachineFunction &MF) const override
Execute target specific actions to finalize target lowering.
Definition: SIISelLowering.cpp:11763
llvm::MemOp
Definition: TargetLowering.h:111
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SITargetLowering::allocateHSAUserSGPRs
void allocateHSAUserSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2015
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::SITargetLowering::isFMADLegal
bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override
Returns true if be combined with to form an ISD::FMAD.
Definition: SIISelLowering.cpp:4386
llvm::AttributeList
Definition: Attributes.h:385
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SITargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: SIISelLowering.cpp:5617
llvm::SITargetLowering::shouldEmitFixup
bool shouldEmitFixup(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:4940
llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: SIISelLowering.cpp:4356
llvm::SITargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SIISelLowering.cpp:11501
llvm::SITargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SIISelLowering.cpp:2514
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MemSDNode
This is an abstract virtual class for memory operations.
Definition: SelectionDAGNodes.h:1246
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::SITargetLowering::insertCopiesSplitCSR
void insertCopiesSplitCSR(MachineBasicBlock *Entry, const SmallVectorImpl< MachineBasicBlock * > &Exits) const override
Insert explicit copies in entry and exit blocks.
Definition: SIISelLowering.cpp:2220
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:853
llvm::SITargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &MF, unsigned IntrinsicID) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: SIISelLowering.cpp:1016
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::SITargetLowering::SITargetLowering
SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI)
Definition: SIISelLowering.cpp:74
llvm::SITargetLowering::legalizeTargetIndependentNode
SDNode * legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const
Legalize target independent instructions (e.g.
Definition: SIISelLowering.cpp:11129
llvm::SITargetLowering::PostISelFolding
SDNode * PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override
Fold the instructions after selecting them.
Definition: SIISelLowering.cpp:11174
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::SITargetLowering::getSubtarget
const GCNSubtarget * getSubtarget() const
Definition: SIISelLowering.cpp:854
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::SITargetLowering::denormalsEnabledForType
bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const
Definition: SIISelLowering.cpp:12056
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::SITargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: SIISelLowering.cpp:11625
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:1965
llvm::LLT::getSizeInBits
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:109
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::SITargetLowering::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent) const override
Return the register class that should be used for the specified value type.
Definition: SIISelLowering.cpp:12180
llvm::SITargetLowering::splitUnaryVectorOp
SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4408
llvm::SITargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: SIISelLowering.cpp:2497
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetLowering::DAGCombinerInfo
Definition: TargetLowering.h:3498
llvm::SITargetLowering::emitGWSMemViolTestLoop
MachineBasicBlock * emitGWSMemViolTestLoop(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3443
llvm::SITargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
Assign the register class depending on the number of bits set in the writemask.
Definition: SIISelLowering.cpp:11339
llvm::SITargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SIISelLowering.cpp:3328
llvm::SITargetLowering::requiresUniformRegister
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *V) const override
Allows target to decide about the register class of the specific value that is live outside the defin...
Definition: SIISelLowering.cpp:12246
llvm::SITargetLowering::computeKnownBitsForFrameIndex
void computeKnownBitsForFrameIndex(int FrameIdx, KnownBits &Known, const MachineFunction &MF) const override
Determine which of the bits of FrameIndex FIOp are known to be 0.
Definition: SIISelLowering.cpp:11825
llvm::SITargetLowering::checkAsmConstraintVal
bool checkAsmConstraintVal(SDValue Op, const std::string &Constraint, uint64_t Val) const
Definition: SIISelLowering.cpp:11675
llvm::Instruction
Definition: Instruction.h:45
AMDGPUISelLowering.h
llvm::SITargetLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:2846
llvm::SITargetLowering::isLegalGlobalAddressingMode
bool isLegalGlobalAddressingMode(const AddrMode &AM) const
Definition: SIISelLowering.cpp:1245
llvm::LegacyDivergenceAnalysis
Definition: LegacyDivergenceAnalysis.h:31
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:29
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::SITargetLowering::computeKnownBitsForTargetInstr
void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: SIISelLowering.cpp:11842
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SITargetLowering::lowerDYNAMIC_STACKALLOCImpl
SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3265
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:1966
llvm::SITargetLowering::getAddrModeArguments
bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const override
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
Definition: SIISelLowering.cpp:1204
llvm::SITargetLowering::LowerCall
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SIISelLowering.cpp:2933
llvm::APFloat
Definition: APFloat.h:701
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::SITargetLowering::splitTernaryVectorOp
SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4450
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::SITargetLowering::initializeSplitCSR
void initializeSplitCSR(MachineBasicBlock *Entry) const override
Perform necessary initialization to handle a subset of CSRs explicitly via copies.
Definition: SIISelLowering.cpp:2216
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SITargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
Definition: SIISelLowering.cpp:908
llvm::SITargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
Definition: SIISelLowering.cpp:4329
llvm::SITargetLowering::isSDNodeSourceOfDivergence
bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override
Definition: SIISelLowering.cpp:11989
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SITargetLowering::isMemOpHasNoClobberedMemOperand
bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const
Definition: SIISelLowering.cpp:1539
llvm::SITargetLowering::isTypeDesirableForOp
bool isTypeDesirableForOp(unsigned Op, EVT VT) const override
Return true if the target has native support for the specified value type and it is 'desirable' to us...
Definition: SIISelLowering.cpp:1583
llvm::SITargetLowering::splitKillBlock
MachineBasicBlock * splitKillBlock(MachineInstr &MI, MachineBasicBlock *BB) const
Definition: SIISelLowering.cpp:3377
llvm::SITargetLowering::shouldEmitGOTReloc
bool shouldEmitGOTReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:4947
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::SITargetLowering::shouldUseLDSConstAddress
bool shouldUseLDSConstAddress(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:4960
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SITargetLowering::allocateSpecialInputVGPRs
void allocateSpecialInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments at the end of allocated user arguments.
Definition: SIISelLowering.cpp:1945
llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
Definition: SIISelLowering.cpp:934
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::SITargetLowering::copyToM0
SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const
Definition: SIISelLowering.cpp:5732
llvm::M68kBeads::DA
@ DA
Definition: M68kBaseInfo.h:59
llvm::SITargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SIISelLowering.cpp:4778
llvm::SITargetLowering::computeKnownAlignForTargetInstr
Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const override
Determine the known alignment for the pointer value R.
Definition: SIISelLowering.cpp:11884
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::SITargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: SIISelLowering.cpp:4321
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl
bool allowsMisalignedMemoryAccessesImpl(unsigned Size, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const
Definition: SIISelLowering.cpp:1398
llvm::SITargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: SIISelLowering.cpp:12110
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
uint32_t
llvm::SITargetLowering::shouldExpandVectorDynExt
static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, bool IsDivergentIdx)
Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be expanded into a set of cmp...
Definition: SIISelLowering.cpp:10088
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SITargetLowering::getPreferredShiftAmountTy
LLT getPreferredShiftAmountTy(LLT Ty) const override
Return the preferred type to use for a shift opcode, given the shifted amount type is ShiftValueTy.
Definition: SIISelLowering.cpp:4335
llvm::SITargetLowering::supportSplitCSR
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Definition: SIISelLowering.cpp:2211
Node
Definition: ItaniumDemangle.h:114
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::SITargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SIISelLowering.cpp:10830
llvm::SITargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLT Ty, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *IsFast=nullptr) const override
LLT handling variant.
Definition: SIISelLowering.h:279
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::SITargetLowering::isKnownNeverNaNForTargetNode
bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const override
If SNaN is false,.
Definition: SIISelLowering.cpp:12082
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MaxDepth
static const unsigned MaxDepth
Definition: InstCombineMulDivRem.cpp:853
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1823
llvm::SITargetLowering::buildRSRC
MachineSDNode * buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const
Return a resource descriptor with the 'Add TID' bit enabled The TID (Thread ID) is multiplied by the ...
Definition: SIISelLowering.cpp:11466
llvm::SITargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SIISelLowering.cpp:4475
llvm::TargetLoweringBase::IntrinsicInfo
Definition: TargetLowering.h:982
llvm::SITargetLowering::isMemOpUniform
bool isMemOpUniform(const SDNode *N) const
Definition: SIISelLowering.cpp:1563
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1688
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SITargetLowering::getTypeLegalizationCost
std::pair< InstructionCost, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Definition: SIISelLowering.cpp:12281
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::SITargetLowering::wrapAddr64Rsrc
MachineSDNode * wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const
Definition: SIISelLowering.cpp:11431
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::SITargetLowering::getPrefLoopAlignment
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
Definition: SIISelLowering.cpp:11905
llvm::SITargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: SIISelLowering.cpp:1577
llvm::SITargetLowering
Definition: SIISelLowering.h:30
llvm::SITargetLowering::isFPExtFoldable
bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation input to an Opcode operation is free (for instance,...
Definition: SIISelLowering.cpp:866
llvm::TargetLoweringBase::LegalizeTypeAction
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Definition: TargetLowering.h:205
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::SITargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:3314
llvm::SITargetLowering::passSpecialInputs
void passSpecialInputs(CallLoweringInfo &CLI, CCState &CCInfo, const SIMachineFunctionInfo &Info, SmallVectorImpl< std::pair< unsigned, SDValue >> &RegsToPass, SmallVectorImpl< SDValue > &MemOpChains, SDValue Chain) const
Definition: SIISelLowering.cpp:2681
llvm::SITargetLowering::canMergeStoresTo
bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it's reasonable to merge stores to MemVT size.
Definition: SIISelLowering.cpp:1385
llvm::SITargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SIISelLowering.cpp:2255
llvm::SITargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SIISelLowering.cpp:3877
N
#define N
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::SITargetLowering::isFreeAddrSpaceCast
bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Definition: SIISelLowering.cpp:1551
llvm::TargetLoweringBase::AddrMode
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Definition: TargetLowering.h:2329
llvm::SITargetLowering::checkAsmConstraintValA
bool checkAsmConstraintValA(SDValue Op, uint64_t Val, unsigned MaxSize=64) const
Definition: SIISelLowering.cpp:11708
llvm::SITargetLowering::enableAggressiveFMAFusion
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always benefits from combining into FMA for a given value type.
Definition: SIISelLowering.cpp:4310
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl< Value * >
llvm::SITargetLowering::shouldEmitPCReloc
bool shouldEmitPCReloc(const GlobalValue *GV) const
Definition: SIISelLowering.cpp:4956
llvm::SITargetLowering::splitBinaryVectorOp
SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const
Definition: SIISelLowering.cpp:4428
RegName
#define RegName(no)
llvm::SITargetLowering::AddIMGInit
void AddIMGInit(MachineInstr &MI) const
Definition: SIISelLowering.cpp:11252
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SITargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int >, EVT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
Definition: SIISelLowering.cpp:876
llvm::SI::KernelInputOffsets::Offsets
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1246
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1979
llvm::SITargetLowering::getOptimalMemOpType
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
Definition: SIISelLowering.cpp:1521
AMDGPUArgumentUsageInfo.h
llvm::AMDGPUMachineFunction
Definition: AMDGPUMachineFunction.h:20
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::SITargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: SIISelLowering.cpp:1303
llvm::SITargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: SIISelLowering.cpp:2922
llvm::SITargetLowering::isCanonicalized
bool isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth=5) const
Definition: SIISelLowering.cpp:9504
llvm::SITargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
Definition: SIISelLowering.cpp:11602
llvm::LLT
Definition: LowLevelTypeImpl.h:40