LLVM  14.0.0git
Public Member Functions | List of all members
llvm::GCNTTIImpl Class Referencefinal

#include "Target/AMDGPU/AMDGPUTargetTransformInfo.h"

Inheritance diagram for llvm::GCNTTIImpl:
Inheritance graph
[legend]
Collaboration diagram for llvm::GCNTTIImpl:
Collaboration graph
[legend]

Public Member Functions

 GCNTTIImpl (const AMDGPUTargetMachine *TM, const Function &F)
 
bool hasBranchDivergence ()
 
bool useGPUDivergenceAnalysis () const
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
TTI::PopcntSupportKind getPopcntSupport (unsigned TyWidth)
 
unsigned getHardwareNumberOfRegisters (bool Vector) const
 
unsigned getNumberOfRegisters (bool Vector) const
 
unsigned getNumberOfRegisters (unsigned RCID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind Vector) const
 
unsigned getMinVectorRegisterBitWidth () const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeMemChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
TypegetMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
 
unsigned getMaxInterleaveFactor (unsigned VF)
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
bool isInlineAsmSourceOfDivergence (const CallInst *CI, ArrayRef< unsigned > Indices={}) const
 Analyze if the results of inline asm are divergent. More...
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *ValTy, unsigned Index)
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
ValuerewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool canSimplifyLegacyMulToMul (const Value *Op0, const Value *Op1, InstCombiner &IC) const
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
InstructionCost getVectorSplitCost ()
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
unsigned getInliningThresholdMultiplier ()
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
int getInlinerVectorBonusPercent ()
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
 
- Public Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
 
bool hasBranchDivergence ()
 
bool useGPUDivergenceAnalysis ()
 
bool isSourceOfDivergence (const Value *V)
 
bool isAlwaysUniform (const Value *V)
 
unsigned getFlatAddressSpace ()
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
ValuerewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLegalAddImmediate (int64_t imm)
 
bool isLegalICmpImmediate (int64_t imm)
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)
 
bool isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isLSRCostLess (TTI::LSRCost C1, TTI::LSRCost C2)
 
bool isNumRegsMajorCostOfLSR ()
 
bool isProfitableLSRChainElement (Instruction *I)
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)
 
bool isTruncateFree (Type *Ty1, Type *Ty2)
 
bool isProfitableToHoist (Instruction *I)
 
bool useAA () const
 
bool isTypeLegal (Type *Ty)
 
InstructionCost getRegUsageForType (Type *Ty)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 
bool shouldBuildLookupTables ()
 
bool shouldBuildRelLookupTables () const
 
bool haveFastSqrt (Type *Ty)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty)
 
InstructionCost getFPOpCost (Type *Ty)
 
unsigned getInliningThresholdMultiplier ()
 
unsigned adjustInliningThreshold (const CallBase *CB)
 
int getInlinerVectorBonusPercent ()
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
 
bool preferPredicateOverEpilogue (Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI)
 
bool emitGetActiveLaneMask ()
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II)
 
Optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
 
InstructionCost getInstructionLatency (const Instruction *I)
 
virtual Optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
virtual Optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
virtual unsigned getCacheLineSize () const
 
virtual unsigned getPrefetchDistance () const
 
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
virtual unsigned getMaxPrefetchIterationsAhead () const
 
virtual bool enableWritePrefetching () const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
Optional< unsigned > getMaxVScale () const
 
InstructionCost getScalarizationOverhead (VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract)
 Estimate the overhead of scalarizing an instruction. More...
 
InstructionCost getScalarizationOverhead (VectorType *InTy, bool Insert, bool Extract)
 Helper wrapper for the DemandedElts variant of getScalarizationOverhead. More...
 
InstructionCost getScalarizationOverhead (VectorType *RetTy, ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
 Estimate the overhead of scalarizing the inputs and outputs of an instruction, with return type RetTy and arguments Args of type Tys. More...
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)
 Estimate the overhead of scalarizing an instructions unique non-constant operands. More...
 
unsigned getMaxInterleaveFactor (unsigned VF)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
TTI::ShuffleKind improveShuffleKindFromMask (TTI::ShuffleKind Kind, ArrayRef< int > Mask) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on arguments. More...
 
InstructionCost getTypeBasedIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on argument types. More...
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Compute a cost of the given call instruction. More...
 
unsigned getNumberOfParts (Type *Tp)
 
InstructionCost getAddressComputationCost (Type *Ty, ScalarEvolution *, const SCEV *)
 
InstructionCost getTreeReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate arithmetic and shuffle op costs for reduction intrinsics. More...
 
InstructionCost getOrderedReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate the cost of performing strict (in-order) reductions, which involves doing a sequence of floating point additions in lane order, starting with an initial value. More...
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
 Try to calculate op costs for min/max reduction operations. More...
 
InstructionCost getExtendedAddReductionCost (bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind)
 
InstructionCost getVectorSplitCost ()
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< GCNTTIImpl >
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
InstructionCost getUserCost (const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
InstructionCost getInstructionLatency (const Instruction *I)
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)
 
 TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)
 
const DataLayoutgetDataLayout () const
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
int getInlinerVectorBonusPercent () const
 
InstructionCost getMemcpyCost (const Instruction *I) const
 
BranchProbability getPredictableBranchThreshold () const
 
bool hasBranchDivergence () const
 
bool useGPUDivergenceAnalysis () const
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned, unsigned) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
ValuerewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLoweredToCall (const Function *F) const
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
 
bool preferPredicateOverEpilogue (Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, const LoopAccessInfo *LAI) const
 
bool emitGetActiveLaneMask () const
 
Optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
Optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
 
Optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
void getUnrollingPreferences (Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
 
void getPeelingPreferences (Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
 
bool isLegalAddImmediate (int64_t Imm) const
 
bool isLegalICmpImmediate (int64_t Imm) const
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
 
bool isLSRCostLess (TTI::LSRCost &C1, TTI::LSRCost &C2) const
 
bool isNumRegsMajorCostOfLSR () const
 
bool isProfitableLSRChainElement (Instruction *I) const
 
bool canMacroFuseCmp () const
 
bool canSaveCmp (Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
 
TTI::AddressingModeKind getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
 
bool isLegalMaskedStore (Type *DataType, Align Alignment) const
 
bool isLegalMaskedLoad (Type *DataType, Align Alignment) const
 
bool isLegalNTStore (Type *DataType, Align Alignment) const
 
bool isLegalNTLoad (Type *DataType, Align Alignment) const
 
bool isLegalMaskedScatter (Type *DataType, Align Alignment) const
 
bool isLegalMaskedGather (Type *DataType, Align Alignment) const
 
bool isLegalMaskedCompressStore (Type *DataType) const
 
bool isLegalMaskedExpandLoad (Type *DataType) const
 
bool enableOrderedReductions () const
 
bool hasDivRemOp (Type *DataType, bool IsSigned) const
 
bool hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
 
bool prefersVectorizedAddressing () const
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
 
bool LSRWithInstrQueries () const
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const
 
bool isProfitableToHoist (Instruction *I) const
 
bool useAA () const
 
bool isTypeLegal (Type *Ty) const
 
InstructionCost getRegUsageForType (Type *Ty) const
 
bool shouldBuildLookupTables () const
 
bool shouldBuildLookupTablesForConstant (Constant *C) const
 
bool shouldBuildRelLookupTables () const
 
bool useColdCCForColdCall (Function &F) const
 
InstructionCost getScalarizationOverhead (VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
 
bool supportsEfficientVectorElementLoadStore () const
 
bool enableAggressiveInterleaving (bool LoopHasReductions) const
 
TTI::MemCmpExpansionOptions enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
 
bool enableInterleavedAccessVectorization () const
 
bool enableMaskedInterleavedAccessVectorization () const
 
bool isFPVectorizationPotentiallyUnsafe () const
 
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, bool *Fast) const
 
TTI::PopcntSupportKind getPopcntSupport (unsigned IntTyWidthInBit) const
 
bool haveFastSqrt (Type *Ty) const
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty) const
 
InstructionCost getFPOpCost (Type *Ty) const
 
InstructionCost getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
 
InstructionCost getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfRegisters (unsigned ClassID) const
 
unsigned getRegisterClassForType (bool Vector, Type *Ty=nullptr) const
 
const char * getRegisterClassName (unsigned ClassID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMinVectorRegisterBitWidth () const
 
Optional< unsigned > getMaxVScale () const
 
bool shouldMaximizeVectorBandwidth () const
 
ElementCount getMinimumVF (unsigned ElemWidth, bool IsScalable) const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
bool shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
 
unsigned getCacheLineSize () const
 
llvm::Optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
llvm::Optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
unsigned getPrefetchDistance () const
 
unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
unsigned getMaxPrefetchIterationsAhead () const
 
bool enableWritePrefetching () const
 
unsigned getMaxInterleaveFactor (unsigned VF) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, int Index, VectorType *SubTp) const
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index) const
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
unsigned getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfParts (Type *Tp) const
 
InstructionCost getAddressComputationCost (Type *Tp, ScalarEvolution *, const SCEV *) const
 
InstructionCost getArithmeticReductionCost (unsigned, VectorType *, Optional< FastMathFlags > FMF, TTI::TargetCostKind) const
 
InstructionCost getMinMaxReductionCost (VectorType *, VectorType *, bool, TTI::TargetCostKind) const
 
InstructionCost getExtendedAddReductionCost (bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
unsigned getAtomicMemIntrinsicMaxElementSize () const
 
ValuegetOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType) const
 
TypegetMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
bool areFunctionArgsABICompatible (const Function *Caller, const Function *Callee, SmallPtrSetImpl< Argument * > &Args) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeLoad (LoadInst *LI) const
 
bool isLegalToVectorizeStore (StoreInst *SI) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
 
bool isElementTypeLegalForScalableVector (Type *Ty) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
bool preferInLoopReduction (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
unsigned getGISelRematGlobalCost () const
 
bool supportsScalableVectors () const
 
bool hasActiveVectorLength () const
 
TargetTransformInfo::VPLegalization getVPLegalizationStrategy (const VPIntrinsic &PI) const
 

Additional Inherited Members

- Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo TTI
 
- Protected Member Functions inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
 BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)
 
virtual ~BasicTTIImplBase ()=default
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< GCNTTIImpl >
 TargetTransformInfoImplCRTPBase (const DataLayout &DL)
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const DataLayout &DL)
 
unsigned minRequiredElementSize (const Value *Val, bool &isSigned) const
 
bool isStridedAccess (const SCEV *Ptr) const
 
const SCEVConstantgetConstantStrideStep (ScalarEvolution *SE, const SCEV *Ptr) const
 
bool isConstantStridedAccessLessThan (ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
 
- Protected Attributes inherited from llvm::BasicTTIImplBase< GCNTTIImpl >
const DataLayoutDL
 
- Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayoutDL
 

Detailed Description

Definition at line 59 of file AMDGPUTargetTransformInfo.h.

Constructor & Destructor Documentation

◆ GCNTTIImpl()

GCNTTIImpl::GCNTTIImpl ( const AMDGPUTargetMachine TM,
const Function F 
)
explicit

Definition at line 287 of file AMDGPUTargetTransformInfo.cpp.

References F, and Mode.

Member Function Documentation

◆ adjustInliningThreshold()

unsigned GCNTTIImpl::adjustInliningThreshold ( const CallBase CB) const

◆ areInlineCompatible()

bool GCNTTIImpl::areInlineCompatible ( const Function Caller,
const Function Callee 
) const

◆ canHaveNonUndefGlobalInitializerInAddressSpace()

bool llvm::GCNTTIImpl::canHaveNonUndefGlobalInitializerInAddressSpace ( unsigned  AS) const
inline

◆ canSimplifyLegacyMulToMul()

bool GCNTTIImpl::canSimplifyLegacyMulToMul ( const Value Op0,
const Value Op1,
InstCombiner IC 
) const

◆ collectFlatAddressOperands()

bool GCNTTIImpl::collectFlatAddressOperands ( SmallVectorImpl< int > &  OpIndexes,
Intrinsic::ID  IID 
) const

Definition at line 1046 of file AMDGPUTargetTransformInfo.cpp.

◆ getArithmeticInstrCost()

InstructionCost GCNTTIImpl::getArithmeticInstrCost ( unsigned  Opcode,
Type Ty,
TTI::TargetCostKind  CostKind,
TTI::OperandValueKind  Opd1Info = TTI::OK_AnyValue,
TTI::OperandValueKind  Opd2Info = TTI::OK_AnyValue,
TTI::OperandValueProperties  Opd1PropInfo = TTI::OP_None,
TTI::OperandValueProperties  Opd2PropInfo = TTI::OP_None,
ArrayRef< const Value * >  Args = ArrayRef<const Value *>(),
const Instruction CxtI = nullptr 
)

Definition at line 516 of file AMDGPUTargetTransformInfo.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), CostKind, llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::FAdd, llvm::ISD::FADD, llvm::FPOpFusion::Fast, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FREM, llvm::ISD::FSUB, llvm::BasicTTIImplBase< GCNTTIImpl >::getArithmeticInstrCost(), llvm::BasicTTIImplBase< GCNTTIImpl >::getScalarizationOverhead(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SITargetLowering::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::Instruction::hasAllowContract(), llvm::AMDGPUSubtarget::hasMadMacF32Insts(), llvm::Value::hasOneUse(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::GCNSubtarget::hasUsableDivScaleConditionOutput(), llvm::MVT::i16, llvm::MVT::i64, llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::AMDGPUTargetLowering::isFNegFree(), llvm::Type::isFPOrFPVectorTy(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isOperationLegalOrPromote(), llvm::EVT::isSimple(), LLVM_FALLTHROUGH, llvm::AArch64CC::LT, llvm::PatternMatch::m_FPOne(), llvm::PatternMatch::match(), llvm::ISD::MUL, Options, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::TargetTransformInfo::TCC_Free, llvm::TargetTransformInfo::TCK_CodeSize, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::Value::user_begin(), and llvm::ISD::XOR.

◆ getArithmeticReductionCost()

InstructionCost GCNTTIImpl::getArithmeticReductionCost ( unsigned  Opcode,
VectorType Ty,
Optional< FastMathFlags FMF,
TTI::TargetCostKind  CostKind 
)

◆ getCFInstrCost()

InstructionCost GCNTTIImpl::getCFInstrCost ( unsigned  Opcode,
TTI::TargetCostKind  CostKind,
const Instruction I = nullptr 
)

◆ getFlatAddressSpace()

unsigned llvm::GCNTTIImpl::getFlatAddressSpace ( ) const
inline

Definition at line 171 of file AMDGPUTargetTransformInfo.h.

References llvm::AMDGPUAS::FLAT_ADDRESS.

◆ getHardwareNumberOfRegisters()

unsigned GCNTTIImpl::getHardwareNumberOfRegisters ( bool  Vector) const

Definition at line 301 of file AMDGPUTargetTransformInfo.cpp.

Referenced by getNumberOfRegisters().

◆ getInlinerVectorBonusPercent()

int llvm::GCNTTIImpl::getInlinerVectorBonusPercent ( )
inline

Definition at line 212 of file AMDGPUTargetTransformInfo.h.

◆ getInliningThresholdMultiplier()

unsigned llvm::GCNTTIImpl::getInliningThresholdMultiplier ( )
inline

Definition at line 209 of file AMDGPUTargetTransformInfo.h.

◆ getIntrinsicInstrCost()

InstructionCost GCNTTIImpl::getIntrinsicInstrCost ( const IntrinsicCostAttributes ICA,
TTI::TargetCostKind  CostKind 
)

◆ getLoadStoreVecRegBitWidth()

unsigned GCNTTIImpl::getLoadStoreVecRegBitWidth ( unsigned  AddrSpace) const

◆ getLoadVectorFactor()

unsigned GCNTTIImpl::getLoadVectorFactor ( unsigned  VF,
unsigned  LoadSize,
unsigned  ChainSizeInBytes,
VectorType VecTy 
) const

Definition at line 345 of file AMDGPUTargetTransformInfo.cpp.

References llvm::Type::getScalarSizeInBits().

◆ getMaximumVF()

unsigned GCNTTIImpl::getMaximumVF ( unsigned  ElemWidth,
unsigned  Opcode 
) const

◆ getMaxInterleaveFactor()

unsigned GCNTTIImpl::getMaxInterleaveFactor ( unsigned  VF)

Definition at line 476 of file AMDGPUTargetTransformInfo.cpp.

◆ getMemcpyLoopLoweringType()

Type * GCNTTIImpl::getMemcpyLoopLoweringType ( LLVMContext Context,
Value Length,
unsigned  SrcAddrSpace,
unsigned  DestAddrSpace,
unsigned  SrcAlign,
unsigned  DestAlign 
) const

◆ getMemcpyLoopResidualLoweringType()

void GCNTTIImpl::getMemcpyLoopResidualLoweringType ( SmallVectorImpl< Type * > &  OpsOut,
LLVMContext Context,
unsigned  RemainingBytes,
unsigned  SrcAddrSpace,
unsigned  DestAddrSpace,
unsigned  SrcAlign,
unsigned  DestAlign 
) const

◆ getMinMaxReductionCost()

InstructionCost GCNTTIImpl::getMinMaxReductionCost ( VectorType Ty,
VectorType CondTy,
bool  IsUnsigned,
TTI::TargetCostKind  CostKind 
)

◆ getMinVectorRegisterBitWidth()

unsigned GCNTTIImpl::getMinVectorRegisterBitWidth ( ) const

Definition at line 333 of file AMDGPUTargetTransformInfo.cpp.

◆ getNumberOfRegisters() [1/2]

unsigned GCNTTIImpl::getNumberOfRegisters ( bool  Vector) const

Definition at line 307 of file AMDGPUTargetTransformInfo.cpp.

References getHardwareNumberOfRegisters().

◆ getNumberOfRegisters() [2/2]

unsigned GCNTTIImpl::getNumberOfRegisters ( unsigned  RCID) const

◆ getPeelingPreferences()

void GCNTTIImpl::getPeelingPreferences ( Loop L,
ScalarEvolution SE,
TTI::PeelingPreferences PP 
)

◆ getPopcntSupport()

TTI::PopcntSupportKind llvm::GCNTTIImpl::getPopcntSupport ( unsigned  TyWidth)
inline

◆ getRegisterBitWidth()

TypeSize GCNTTIImpl::getRegisterBitWidth ( TargetTransformInfo::RegisterKind  Vector) const

◆ getShuffleCost()

InstructionCost GCNTTIImpl::getShuffleCost ( TTI::ShuffleKind  Kind,
VectorType Tp,
ArrayRef< int Mask,
int  Index,
VectorType SubTp 
)

◆ getStoreVectorFactor()

unsigned GCNTTIImpl::getStoreVectorFactor ( unsigned  VF,
unsigned  StoreSize,
unsigned  ChainSizeInBytes,
VectorType VecTy 
) const

Definition at line 356 of file AMDGPUTargetTransformInfo.cpp.

◆ getTgtMemIntrinsic()

bool GCNTTIImpl::getTgtMemIntrinsic ( IntrinsicInst Inst,
MemIntrinsicInfo Info 
) const

◆ getUnrollingPreferences()

void GCNTTIImpl::getUnrollingPreferences ( Loop L,
ScalarEvolution SE,
TTI::UnrollingPreferences UP,
OptimizationRemarkEmitter ORE 
)

◆ getVectorInstrCost()

InstructionCost GCNTTIImpl::getVectorInstrCost ( unsigned  Opcode,
Type ValTy,
unsigned  Index 
)

◆ getVectorSplitCost()

InstructionCost llvm::GCNTTIImpl::getVectorSplitCost ( )
inline

Definition at line 200 of file AMDGPUTargetTransformInfo.h.

◆ hasBranchDivergence()

bool llvm::GCNTTIImpl::hasBranchDivergence ( )
inline

Definition at line 101 of file AMDGPUTargetTransformInfo.h.

◆ instCombineIntrinsic()

Optional< Instruction * > GCNTTIImpl::instCombineIntrinsic ( InstCombiner IC,
IntrinsicInst II 
) const

Definition at line 191 of file AMDGPUInstCombineIntrinsic.cpp.

References llvm::CallBase::addFnAttr(), llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::InstCombiner::Builder, C1, canSimplifyLegacyMulToMul(), llvm::MCID::Convergent, llvm::APFloat::convert(), llvm::Instruction::copyFastMathFlags(), llvm::IRBuilderBase::CreateAShr(), llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateFAddFMF(), llvm::IRBuilderBase::CreateFCmpOEQ(), llvm::IRBuilderBase::CreateFCmpUNO(), llvm::IRBuilderBase::CreateFMulFMF(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreateMaxNum(), llvm::IRBuilderBase::CreateMinNum(), llvm::IRBuilderBase::CreateSExt(), llvm::IRBuilderBase::CreateShl(), llvm::IRBuilderBase::CreateZExt(), llvm::APFloat::divide(), llvm::InstCombiner::eraseInstFromFunction(), llvm::FAdd, llvm::CmpInst::FIRST_FCMP_PREDICATE, llvm::CmpInst::FIRST_ICMP_PREDICATE, fmed3AMDGCN(), llvm::FMul, llvm::frexp(), llvm::ConstantInt::get(), llvm::MetadataAsValue::get(), llvm::ConstantFP::get(), llvm::ConstantVector::get(), llvm::MDString::get(), llvm::MDNode::get(), llvm::UndefValue::get(), llvm::CallBase::getArgOperand(), llvm::CallBase::getCalledFunction(), llvm::ConstantExpr::getCompare(), llvm::IRBuilderBase::getContext(), llvm::Value::getContext(), llvm::Intrinsic::getDeclaration(), llvm::Type::getFltSemantics(), llvm::AMDGPU::getImageDimIntrinsicInfo(), llvm::Type::getIntegerBitWidth(), llvm::IRBuilderBase::getIntNTy(), llvm::IntrinsicInst::getIntrinsicID(), llvm::CmpInst::getInversePredicate(), llvm::Instruction::getModule(), llvm::Constant::getNullValue(), llvm::Instruction::getParent(), llvm::APFloat::getQNaN(), llvm::Type::getScalarType(), llvm::APFloat::getSemantics(), llvm::ConstantExpr::getSExt(), llvm::CmpInst::getSwappedPredicate(), llvm::InstCombiner::getTargetLibraryInfo(), llvm::ConstantInt::getType(), llvm::Value::getType(), llvm::ConstantFP::getValueAPF(), llvm::ConstantInt::getZExtValue(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::APFloatBase::IEK_Inf, llvm::APFloatBase::IEK_NaN, llvm::APFloat::isDenormal(), llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), llvm::CmpInst::isFPPredicate(), llvm::Type::isHalfTy(), llvm::APFloat::isInfinity(), llvm::Type::isIntegerTy(), llvm::isKnownNeverNaN(), llvm::APFloat::isNaN(), llvm::APFloat::isNegative(), llvm::APFloat::isNormal(), llvm::Constant::isNullValue(), llvm::APFloat::isSignaling(), llvm::CmpInst::isSigned(), llvm::CallBase::isStrictFP(), llvm::APFloat::isZero(), llvm::CmpInst::LAST_FCMP_PREDICATE, llvm::CmpInst::LAST_ICMP_PREDICATE, llvm::PatternMatch::m_AllOnes(), llvm::PatternMatch::m_AnyZeroFP(), llvm::PatternMatch::m_APFloat(), llvm::PatternMatch::m_Cmp(), llvm::PatternMatch::m_NaN(), llvm::PatternMatch::m_One(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::PatternMatch::m_ZeroInt(), llvm::PatternMatch::m_ZExt(), llvm::PatternMatch::m_ZExtOrSExt(), llvm::BitmaskEnumDetail::Mask(), llvm::PatternMatch::match(), llvm::SIInstrFlags::N_INFINITY, llvm::SIInstrFlags::N_NORMAL, llvm::SIInstrFlags::N_SUBNORMAL, llvm::SIInstrFlags::N_ZERO, llvm::None, Offset, llvm::SIInstrFlags::P_INFINITY, llvm::SIInstrFlags::P_NORMAL, llvm::SIInstrFlags::P_SUBNORMAL, llvm::SIInstrFlags::P_ZERO, llvm::SIInstrFlags::Q_NAN, RegName, llvm::InstCombiner::replaceInstUsesWith(), llvm::InstCombiner::replaceOperand(), llvm::AArch64::RM, llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::rmTowardZero, llvm::SIInstrFlags::S_NAN, llvm::scalbn(), llvm::CallBase::setArgOperand(), llvm::CallBase::setCalledOperand(), Signed, simplifyAMDGCNImageIntrinsic(), std::swap(), and llvm::Value::takeName().

◆ isAlwaysUniform()

bool GCNTTIImpl::isAlwaysUniform ( const Value V) const

◆ isInlineAsmSourceOfDivergence()

bool GCNTTIImpl::isInlineAsmSourceOfDivergence ( const CallInst CI,
ArrayRef< unsigned >  Indices = {} 
) const

Analyze if the results of inline asm are divergent.

If Indices is empty, this is analyzing the collective result of all output registers. Otherwise, this is only querying a specific result index if this returns multiple registers in a struct.

Definition at line 908 of file AMDGPUTargetTransformInfo.cpp.

References llvm::TargetLowering::ComputeConstraintToUse(), llvm::BasicTTIImplBase< GCNTTIImpl >::DL, llvm::ArrayRef< T >::empty(), llvm::Module::getDataLayout(), llvm::Instruction::getModule(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::GCNSubtarget::getRegisterInfo(), llvm::InlineAsm::isOutput, llvm::TargetLowering::ParseConstraints(), llvm::ArrayRef< T >::size(), and TRI.

Referenced by isAlwaysUniform(), and isSourceOfDivergence().

◆ isLegalToVectorizeLoadChain()

bool GCNTTIImpl::isLegalToVectorizeLoadChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

Definition at line 394 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

◆ isLegalToVectorizeMemChain()

bool GCNTTIImpl::isLegalToVectorizeMemChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

◆ isLegalToVectorizeStoreChain()

bool GCNTTIImpl::isLegalToVectorizeStoreChain ( unsigned  ChainSizeInBytes,
Align  Alignment,
unsigned  AddrSpace 
) const

Definition at line 400 of file AMDGPUTargetTransformInfo.cpp.

References isLegalToVectorizeMemChain().

◆ isSourceOfDivergence()

bool GCNTTIImpl::isSourceOfDivergence ( const Value V) const
Returns
true if the result of the value could potentially be different across workitems in a wavefront.

Definition at line 958 of file AMDGPUTargetTransformInfo.cpp.

References llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPU::isArgPassedInSGPR(), isInlineAsmSourceOfDivergence(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), llvm::SPII::Load, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

◆ rewriteIntrinsicWithAddressSpace()

Value * GCNTTIImpl::rewriteIntrinsicWithAddressSpace ( IntrinsicInst II,
Value OldV,
Value NewV 
) const

◆ simplifyDemandedVectorEltsIntrinsic()

Optional< Value * > GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic ( InstCombiner IC,
IntrinsicInst II,
APInt  DemandedElts,
APInt UndefElts,
APInt UndefElts2,
APInt UndefElts3,
std::function< void(Instruction *, unsigned, APInt, APInt &)>  SimplifyAndSetOp 
) const

◆ useGPUDivergenceAnalysis()

bool GCNTTIImpl::useGPUDivergenceAnalysis ( ) const
Returns
true if the new GPU divergence analysis is enabled.

Definition at line 952 of file AMDGPUTargetTransformInfo.cpp.

References UseLegacyDA.


The documentation for this class was generated from the following files: