LLVM 17.0.0git
Macros | Functions | Variables
LoongArchISelLowering.cpp File Reference
#include "LoongArchISelLowering.h"
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSubtarget.h"
#include "LoongArchTargetMachine.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsLoongArch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "LoongArchGenAsmMatcher.inc"
Include dependency graph for LoongArchISelLowering.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "loongarch-isel-lowering"
 
#define IOCSRRD_CASE(NAME, NODE)
 
#define IOCSRWR_CASE(NAME, NODE)
 
#define ASRT_LE_GT_CASE(NAME)
 
#define CRC_CASE_EXT_BINARYOP(NAME, NODE)
 
#define CRC_CASE_EXT_UNARYOP(NAME, NODE)
 
#define CSR_CASE(ID)
 
#define IOCSRRD_CASE(NAME, NODE)
 
#define NODE_NAME_CASE(node)
 
#define GET_REGISTER_MATCHER
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
static SDValue getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
 
static SDValue emitIntrinsicWithChainErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
 
static SDValue emitIntrinsicErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
 
static LoongArchISD::NodeType getLoongArchWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performBITREV_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static MachineBasicBlockinsertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock *MBB)
 
static bool CC_LoongArchAssign2GRLen (unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static bool CC_LoongArch (const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static bool CC_LoongArch_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 
static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp (unsigned GRLen, AtomicRMWInst::BinOp BinOp)
 

Variables

static cl::opt< boolZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
 
const MCPhysReg ArgGPRs []
 
const MCPhysReg ArgFPR32s []
 
const MCPhysReg ArgFPR64s []
 

Macro Definition Documentation

◆ ASRT_LE_GT_CASE

#define ASRT_LE_GT_CASE (   NAME)
Value:
case Intrinsic::loongarch_##NAME: { \
if (!Subtarget.is64Bit()) { \
DAG.getContext()->emitError(Op->getOperationName(0) + \
" requires target: loongarch64"); \
return Op.getOperand(0); \
} \
return Op; \
}

◆ CRC_CASE_EXT_BINARYOP

#define CRC_CASE_EXT_BINARYOP (   NAME,
  NODE 
)
Value:
case Intrinsic::loongarch_##NAME: { \
Results.push_back(DAG.getNode( \
ISD::TRUNCATE, DL, VT, \
DAG.getNode( \
LoongArchISD::NODE, DL, MVT::i64, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))))); \
Results.push_back(N->getOperand(0)); \
break; \
}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:779
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:782
#define N

◆ CRC_CASE_EXT_UNARYOP

#define CRC_CASE_EXT_UNARYOP (   NAME,
  NODE 
)
Value:
case Intrinsic::loongarch_##NAME: { \
Results.push_back( \
DAG.getNode(ISD::TRUNCATE, DL, VT, \
DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Op2, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, \
N->getOperand(3))))); \
Results.push_back(N->getOperand(0)); \
break; \
}

◆ CSR_CASE

#define CSR_CASE (   ID)
Value:
case Intrinsic::loongarch_##ID: { \
if (!Subtarget.is64Bit()) { \
DAG.getContext()->emitError(Name + " requires target: loongarch64"); \
Results.push_back(DAG.getUNDEF(VT)); \
Results.push_back(N->getOperand(0)); \
} \
break; \
}
std::string Name
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24

◆ DEBUG_TYPE

#define DEBUG_TYPE   "loongarch-isel-lowering"

Definition at line 33 of file LoongArchISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 3103 of file LoongArchISelLowering.cpp.

◆ IOCSRRD_CASE [1/2]

#define IOCSRRD_CASE (   NAME,
  NODE 
)
Value:
case Intrinsic::loongarch_##NAME: { \
return DAG.getMergeValues( \
{DAG.getNode(LoongArchISD::NODE, DL, GRLenVT, Op0, Op.getOperand(2)), \
Op0}, \
DL); \
}

◆ IOCSRRD_CASE [2/2]

#define IOCSRRD_CASE (   NAME,
  NODE 
)
Value:
case Intrinsic::loongarch_##NAME: { \
Results.push_back(DAG.getNode( \
ISD::TRUNCATE, DL, N->getValueType(0), \
DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Op0, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)))); \
Results.push_back(N->getOperand(0)); \
break; \
}

◆ IOCSRWR_CASE

#define IOCSRWR_CASE (   NAME,
  NODE 
)
Value:
case Intrinsic::loongarch_##NAME: { \
SDValue Op3 = Op.getOperand(3); \
if (Subtarget.is64Bit()) \
return DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Op0, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)); \
else \
return DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Op0, Op2, Op3); \
}
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   node)
Value:
case LoongArchISD::node: \
return "LoongArchISD::" #node;

Function Documentation

◆ CC_LoongArch()

static bool CC_LoongArch ( const DataLayout DL,
LoongArchABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy 
)
static

◆ CC_LoongArch_GHC()

static bool CC_LoongArch_GHC ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State 
)
static

◆ CC_LoongArchAssign2GRLen()

static bool CC_LoongArchAssign2GRLen ( unsigned  GRLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG,
int  NumOp,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

◆ emitIntrinsicErrorMessage()

static SDValue emitIntrinsicErrorMessage ( SDValue  Op,
StringRef  ErrorMsg,
SelectionDAG DAG 
)
static

◆ emitIntrinsicWithChainErrorMessage()

static SDValue emitIntrinsicWithChainErrorMessage ( SDValue  Op,
StringRef  ErrorMsg,
SelectionDAG DAG 
)
static

◆ getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  GRLen,
AtomicRMWInst::BinOp  BinOp 
)
static

◆ getLoongArchWOpcode()

static LoongArchISD::NodeType getLoongArchWOpcode ( unsigned  Opcode)
static

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG DAG 
)
static

◆ getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 448 of file LoongArchISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetBlockAddress(), and N.

◆ getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 454 of file LoongArchISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetConstantPool(), and N.

◆ getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 443 of file LoongArchISelLowering.cpp.

References DL, Flags, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

◆ getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode N,
SDLoc  DL,
EVT  Ty,
SelectionDAG DAG,
unsigned  Flags 
)
static

Definition at line 460 of file LoongArchISelLowering.cpp.

References Flags, llvm::SelectionDAG::getTargetJumpTable(), and N.

◆ insertDivByZeroTrap()

static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr MI,
MachineBasicBlock MBB 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performBITREV_WCombine()

static SDValue performBITREV_WCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performSRLCombine()

static SDValue performSRLCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ STATISTIC()

STATISTIC ( NumTailCalls  ,
"Number of tail calls"   
)

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL,
const LoongArchTargetLowering TLI 
)
static

Variable Documentation

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
Initial value:
= {LoongArch::F0, LoongArch::F1, LoongArch::F2,
LoongArch::F3, LoongArch::F4, LoongArch::F5,
LoongArch::F6, LoongArch::F7}

Definition at line 1841 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and CC_RISCV().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
Initial value:
= {
LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64}

Definition at line 1845 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and CC_RISCV().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
Initial value:
= {LoongArch::R4, LoongArch::R5, LoongArch::R6,
LoongArch::R7, LoongArch::R8, LoongArch::R9,
LoongArch::R10, LoongArch::R11}

Definition at line 1836 of file LoongArchISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), CC_RISCV(), CC_RISCVAssign2XLen(), llvm::RISCVTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

◆ ZeroDivCheck

cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false)) ( "loongarch-check-zero-division"  ,
cl::Hidden  ,
cl::desc("Trap on integer division by zero.")  ,
cl::init(false)   
)
static

Referenced by insertDivByZeroTrap().