LoongArchISelLowering.cpp File Reference

#include "LoongArchISelLowering.h"
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSubtarget.h"
#include "LoongArchTargetMachine.h"
#include "MCTargetDesc/LoongArchBaseInfo.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsLoongArch.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "LoongArchGenAsmMatcher.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "loongarch-isel-lowering"
#define	IOCSRRD_CASE(NAME, NODE)
#define	IOCSRWR_CASE(NAME, NODE)
#define	ASRT_LE_GT_CASE(NAME)
#define	CRC_CASE_EXT_BINARYOP(NAME, NODE)
#define	CRC_CASE_EXT_UNARYOP(NAME, NODE)
#define	CSR_CASE(ID)
#define	IOCSRRD_CASE(NAME, NODE)
#define	NODE_NAME_CASE(node)
#define	GET_REGISTER_MATCHER

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
static SDValue	getTargetNode (GlobalAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (BlockAddressSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (ConstantPoolSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
static SDValue	getTargetNode (JumpTableSDNode *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, unsigned Flags)
template<unsigned N>
static SDValue	checkIntrinsicImmArg (SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	emitIntrinsicWithChainErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static SDValue	emitIntrinsicErrorMessage (SDValue Op, StringRef ErrorMsg, SelectionDAG &DAG)
static LoongArchISD::NodeType	getLoongArchWOpcode (unsigned Opcode)
static SDValue	customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
static void	emitErrorAndReplaceIntrinsicResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, StringRef ErrorMsg, bool WithChain=true)
template<unsigned N>
static void	replaceVPICKVE2GRResults (SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceVecCondBranchResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, unsigned ResOp)
static void	replaceINTRINSIC_WO_CHAINResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget)
static SDValue	performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static SDValue	performBITREV_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
template<unsigned N>
static SDValue	legalizeIntrinsicImmArg (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget, bool IsSigned=false)
template<unsigned N>
static SDValue	lowerVectorSplatImm (SDNode *Node, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned=false)
static SDValue	truncateVecElts (SDNode *Node, SelectionDAG &DAG)
static SDValue	lowerVectorBitClear (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitClearImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitSetImm (SDNode *Node, SelectionDAG &DAG)
template<unsigned N>
static SDValue	lowerVectorBitRevImm (SDNode *Node, SelectionDAG &DAG)
static SDValue	performINTRINSIC_WO_CHAINCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
static MachineBasicBlock *	insertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock *MBB)
static MachineBasicBlock *	emitVecCondBranchPseudo (MachineInstr &MI, MachineBasicBlock *BB, const LoongArchSubtarget &Subtarget)
static bool	CC_LoongArchAssign2GRLen (unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
static bool	CC_LoongArch (const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
static SDValue	convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue	unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
static SDValue	unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
static SDValue	convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static bool	CC_LoongArch_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static Align	getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
static Intrinsic::ID	getIntrinsicForMaskedAtomicRMWBinOp (unsigned GRLen, AtomicRMWInst::BinOp BinOp)

Variables
static cl::opt< bool >	ZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
const MCPhysReg	ArgGPRs []
const MCPhysReg	ArgFPR32s []
const MCPhysReg	ArgFPR64s []
const MCPhysReg	ArgVRs []
const MCPhysReg	ArgXRs []

Macro Definition Documentation

ASRT_LE_GT_CASE

#define ASRT_LE_GT_CASE

(

NAME

)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return !Subtarget.is64Bit()                                                \
               ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)           \
               : Op;                                                           \
  }

CRC_CASE_EXT_BINARYOP

#define CRC_CASE_EXT_BINARYOP	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),               \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

CRC_CASE_EXT_UNARYOP

#define CRC_CASE_EXT_UNARYOP	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue NODE = DAG.getNode(                                                \
        LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},                        \
        {Chain, Op2,                                                           \
         DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))});       \
    Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, NODE.getValue(0)));   \
    Results.push_back(NODE.getValue(1));                                       \
    break;                                                                     \
  }

CSR_CASE

#define CSR_CASE

(

ID

)

Value:

  case Intrinsic::loongarch_##ID: {                                            \
    if (!Subtarget.is64Bit())                                                  \
      emitErrorAndReplaceIntrinsicResults(N, Results, DAG, ErrorMsgReqLA64);   \
    break;                                                                     \
  }

DEBUG_TYPE

#define DEBUG_TYPE   "loongarch-isel-lowering"

Definition at line 37 of file LoongArchISelLowering.cpp.

GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 4524 of file LoongArchISelLowering.cpp.

IOCSRRD_CASE [1/2]

#define IOCSRRD_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    return DAG.getNode(LoongArchISD::NODE, DL, {GRLenVT, MVT::Other},          \
                       {Chain, Op.getOperand(2)});                             \
  }

IOCSRRD_CASE [2/2]

#define IOCSRRD_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue IOCSRRDResults =                                                   \
        DAG.getNode(LoongArchISD::NODE, DL, {MVT::i64, MVT::Other},            \
                    {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)}); \
    Results.push_back(                                                         \
        DAG.getNode(ISD::TRUNCATE, DL, VT, IOCSRRDResults.getValue(0)));       \
    Results.push_back(IOCSRRDResults.getValue(1));                             \
    break;                                                                     \
  }

IOCSRWR_CASE

#define IOCSRWR_CASE	(		NAME,
			NODE
	)

Value:

  case Intrinsic::loongarch_##NAME: {                                          \
    SDValue Op3 = Op.getOperand(3);                                            \
    return Subtarget.is64Bit()                                                 \
               ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain,        \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),  \
                             DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3))  \
               : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2,   \
                             Op3);                                             \
  }

NODE_NAME_CASE

#define NODE_NAME_CASE

(

node

)

Value:

  case LoongArchISD::node:                                                     \
    return "LoongArchISD::" #node;

Function Documentation

CC_LoongArch()

static bool CC_LoongArch ( const DataLayout &  DL, LoongArchABI::ABI  ABI, unsigned  ValNo, MVT  ValVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State, bool  IsFixed, bool  IsRet, Type *  OrigTy  )

static

Definition at line 3276 of file LoongArchISelLowering.cpp.

References llvm::LoongArchABI::ABI_ILP32D, llvm::LoongArchABI::ABI_ILP32F, llvm::LoongArchABI::ABI_ILP32S, llvm::LoongArchABI::ABI_LP64D, llvm::LoongArchABI::ABI_LP64F, llvm::LoongArchABI::ABI_LP64S, llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgFPR32s, ArgFPR64s, ArgGPRs, ArgVRs, ArgXRs, assert(), llvm::CCValAssign::BCvt, CC_LoongArchAssign2GRLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::CCValAssign::Full, llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::CCValAssign::Indirect, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::MVT::isFloatingPoint(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::report_fatal_error(), and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::LoongArchTargetLowering::CanLowerReturn(), llvm::LoongArchTargetLowering::LowerCall(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::LoongArchTargetLowering::LowerReturn().

CC_LoongArch_GHC()

static bool CC_LoongArch_GHC ( unsigned  ValNo, MVT  ValVT, MVT  LocVT, CCValAssign::LocInfo  LocInfo, ISD::ArgFlagsTy  ArgFlags, CCState &  State  )

static

Definition at line 3550 of file LoongArchISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCValAssign::getReg(), and llvm::report_fatal_error().

Referenced by llvm::LoongArchTargetLowering::LowerCall(), and llvm::LoongArchTargetLowering::LowerFormalArguments().

CC_LoongArchAssign2GRLen()

static bool CC_LoongArchAssign2GRLen ( unsigned  GRLen, CCState &  State, CCValAssign  VA1, ISD::ArgFlagsTy  ArgFlags1, unsigned  ValNo2, MVT  ValVT2, MVT  LocVT2, ISD::ArgFlagsTy  ArgFlags2  )

static

Definition at line 3240 of file LoongArchISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgGPRs, llvm::CCValAssign::Full, llvm::CCValAssign::getLocVT(), llvm::CCValAssign::getMem(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getReg(), llvm::CCValAssign::getValNo(), and llvm::CCValAssign::getValVT().

Referenced by CC_LoongArch().

checkIntrinsicImmArg()

template<unsigned N>

static SDValue checkIntrinsicImmArg ( SDValue  Op, unsigned  ImmOp, SelectionDAG &  DAG, bool  IsSigned = false  )

static

Definition at line 783 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), and llvm::ISD::UNDEF.

convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 3471 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::LoongArchISD::MOVGR2FR_W_LA64.

convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG &  DAG, SDValue  Val, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 3531 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm_unreachable, and llvm::LoongArchISD::MOVFR2GR_S_LA64.

customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode *  N, SelectionDAG &  DAG, int  NumOp, unsigned  ExtOpc = ISD::ANY_EXTEND  )

static

Definition at line 1493 of file LoongArchISelLowering.cpp.

References DL, getLoongArchWOpcode(), llvm::SelectionDAG::getNode(), llvm_unreachable, N, and llvm::ISD::TRUNCATE.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and llvm::RISCVTargetLowering::ReplaceNodeResults().

emitErrorAndReplaceIntrinsicResults()

static void emitErrorAndReplaceIntrinsicResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, StringRef  ErrorMsg, bool  WithChain = true  )

static

Definition at line 1523 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getUNDEF(), N, and Results.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults(), and replaceVPICKVE2GRResults().

emitIntrinsicErrorMessage()

static SDValue emitIntrinsicErrorMessage ( SDValue  Op, StringRef  ErrorMsg, SelectionDAG &  DAG  )

static

Definition at line 1200 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), and llvm::SelectionDAG::getContext().

emitIntrinsicWithChainErrorMessage()

static SDValue emitIntrinsicWithChainErrorMessage ( SDValue  Op, StringRef  ErrorMsg, SelectionDAG &  DAG  )

static

Definition at line 1077 of file LoongArchISelLowering.cpp.

References llvm::LLVMContext::emitError(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), and llvm::SelectionDAG::getUNDEF().

emitVecCondBranchPseudo()

static MachineBasicBlock * emitVecCondBranchPseudo ( MachineInstr &  MI, MachineBasicBlock *  BB, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2946 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::LoongArchSubtarget::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MI, MRI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

getIntrinsicForMaskedAtomicRMWBinOp()

static Intrinsic::ID getIntrinsicForMaskedAtomicRMWBinOp ( unsigned  GRLen, AtomicRMWInst::BinOp  BinOp  )

static

Definition at line 4197 of file LoongArchISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.

Referenced by llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic(), and llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic().

getLoongArchWOpcode()

static LoongArchISD::NodeType getLoongArchWOpcode ( unsigned  Opcode )

static

Definition at line 1467 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::CLZ_W, llvm::ISD::CTLZ, llvm::ISD::CTTZ, llvm::LoongArchISD::CTZ_W, llvm_unreachable, Opcode, llvm::ISD::ROTL, llvm::LoongArchISD::ROTL_W, llvm::ISD::ROTR, llvm::LoongArchISD::ROTR_W, llvm::ISD::SHL, llvm::LoongArchISD::SLL_W, llvm::ISD::SRA, llvm::LoongArchISD::SRA_W, llvm::ISD::SRL, and llvm::LoongArchISD::SRL_W.

Referenced by customLegalizeToWOp().

getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT, SelectionDAG &  DAG  )

static

Definition at line 3802 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().

Referenced by llvm::SelectionDAG::CreateStackTemporary(), llvm::LoongArchTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerCall().

getTargetNode() [1/4]

static SDValue getTargetNode ( BlockAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 590 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetBlockAddress(), and N.

getTargetNode() [2/4]

static SDValue getTargetNode ( ConstantPoolSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 596 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetConstantPool(), and N.

getTargetNode() [3/4]

static SDValue getTargetNode ( GlobalAddressSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 585 of file LoongArchISelLowering.cpp.

References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.

getTargetNode() [4/4]

static SDValue getTargetNode ( JumpTableSDNode *  N, SDLoc  DL, EVT  Ty, SelectionDAG &  DAG, unsigned  Flags  )

static

Definition at line 602 of file LoongArchISelLowering.cpp.

References llvm::SelectionDAG::getTargetJumpTable(), and N.

insertDivByZeroTrap()

static MachineBasicBlock * insertDivByZeroTrap ( MachineInstr &  MI, MachineBasicBlock *  MBB  )

static

Definition at line 2896 of file LoongArchISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), llvm::MachineOperand::isKill(), MBB, MI, llvm::MachineOperand::setIsKill(), TII, and ZeroDivCheck.

Referenced by llvm::MipsTargetLowering::EmitInstrWithCustomInserter().

legalizeIntrinsicImmArg()

template<unsigned N>

static SDValue legalizeIntrinsicImmArg ( SDNode *  Node, unsigned  ImmOp, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, bool  IsSigned = false  )

static

Definition at line 2284 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), and llvm::ISD::UNDEF.

lowerVectorBitClear()

static SDValue lowerVectorBitClear ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 2328 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::ISD::SHL, and truncateVecElts().

Referenced by performINTRINSIC_WO_CHAINCombine().

lowerVectorBitClearImm()

template<unsigned N>

static SDValue lowerVectorBitClearImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 2340 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), and llvm::ISD::UNDEF.

lowerVectorBitRevImm()

template<unsigned N>

static SDValue lowerVectorBitRevImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 2375 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::UNDEF, and llvm::ISD::XOR.

lowerVectorBitSetImm()

template<unsigned N>

static SDValue lowerVectorBitSetImm ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 2358 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::OR, and llvm::ISD::UNDEF.

lowerVectorSplatImm()

template<unsigned N>

static SDValue lowerVectorSplatImm ( SDNode *  Node, unsigned  ImmOp, SelectionDAG &  DAG, bool  IsSigned = false  )

static

Definition at line 2301 of file LoongArchISelLowering.cpp.

References DL, llvm::LLVMContext::emitError(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), and llvm::ISD::UNDEF.

performANDCombine()

static SDValue performANDCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 1923 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::BSTRPICK, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::SDNode::use_size().

performBITREV_WCombine()

static SDValue performBITREV_WCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2269 of file LoongArchISelLowering.cpp.

References llvm::LoongArchISD::BITREV_4B, llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), N, and llvm::LoongArchISD::REVB_2W.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performINTRINSIC_WO_CHAINCombine()

static SDValue performINTRINSIC_WO_CHAINCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2392 of file LoongArchISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTPOP, DL, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, lowerVectorBitClear(), llvm::ISD::MUL, N, llvm::ISD::OR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SREM, llvm::ISD::SRL, llvm::ISD::SUB, truncateVecElts(), llvm::ISD::UDIV, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::UREM, llvm::LoongArchISD::VREPLVE, and llvm::ISD::XOR.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine().

performORCombine()

static SDValue performORCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2050 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::LoongArchISD::BSTRINS, llvm::SelectionDAG::computeKnownBits(), llvm::dbgs(), DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), llvm::APInt::isSubsetOf(), LLVM_DEBUG, N, llvm::ISD::SHL, llvm::ISD::SRL, std::swap(), and llvm::KnownBits::Zero.

performSRLCombine()

static SDValue performSRLCombine ( SDNode *  N, SelectionDAG &  DAG, TargetLowering::DAGCombinerInfo &  DCI, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 2009 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, llvm::LoongArchISD::BSTRPICK, DL, llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps(), llvm::isShiftedMask_64(), and N.

Referenced by llvm::LoongArchTargetLowering::PerformDAGCombine(), and llvm::MipsSETargetLowering::PerformDAGCombine().

replaceINTRINSIC_WO_CHAINResults()

static void replaceINTRINSIC_WO_CHAINResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget  )

static

Definition at line 1570 of file LoongArchISelLowering.cpp.

References llvm_unreachable, N, replaceVecCondBranchResults(), Results, llvm::LoongArchISD::VALL_NONZERO, llvm::LoongArchISD::VALL_ZERO, llvm::LoongArchISD::VANY_NONZERO, llvm::LoongArchISD::VANY_ZERO, llvm::LoongArchISD::VPICK_SEXT_ELT, and llvm::LoongArchISD::VPICK_ZEXT_ELT.

Referenced by llvm::LoongArchTargetLowering::ReplaceNodeResults().

replaceVecCondBranchResults()

static void replaceVecCondBranchResults ( SDNode *  N, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, unsigned  ResOp  )

static

Definition at line 1556 of file LoongArchISelLowering.cpp.

References DL, llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), N, Results, and llvm::ISD::TRUNCATE.

Referenced by replaceINTRINSIC_WO_CHAINResults().

replaceVPICKVE2GRResults()

template<unsigned N>

static void replaceVPICKVE2GRResults ( SDNode *  Node, SmallVectorImpl< SDValue > &  Results, SelectionDAG &  DAG, const LoongArchSubtarget &  Subtarget, unsigned  ResOp  )

static

Definition at line 1535 of file LoongArchISelLowering.cpp.

References DL, emitErrorAndReplaceIntrinsicResults(), llvm::SelectionDAG::getConstant(), llvm::LoongArchSubtarget::getGRLenVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorElementType(), Results, and llvm::ISD::TRUNCATE.

STATISTIC()

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"
	)

truncateVecElts()

static SDValue truncateVecElts ( SDNode *  Node, SelectionDAG &  DAG  )

static

Definition at line 2320 of file LoongArchISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getScalarValueSizeInBits().

Referenced by lowerMSABitClear(), lowerVectorBitClear(), and performINTRINSIC_WO_CHAINCombine().

unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL  )

static

Definition at line 3506 of file LoongArchISelLowering.cpp.

References llvm::CCValAssign::BCvt, llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::CCValAssign::Full, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::getValVT(), llvm::CCValAssign::Indirect, llvm_unreachable, and llvm::ISD::NON_EXTLOAD.

unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG &  DAG, SDValue  Chain, const CCValAssign &  VA, const SDLoc &  DL, const LoongArchTargetLowering &  TLI  )

static

Definition at line 3489 of file LoongArchISelLowering.cpp.

References convertLocVTToValVT(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getRegClassFor(), llvm::MachineFunction::getRegInfo(), and llvm::EVT::getSimpleVT().

Variable Documentation

ArgFPR32s

const MCPhysReg ArgFPR32s[]

Initial value:

= {LoongArch::F0, LoongArch::F1, LoongArch::F2,
                               LoongArch::F3, LoongArch::F4, LoongArch::F5,
                               LoongArch::F6, LoongArch::F7}

Definition at line 3222 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::RISCV::CC_RISCV().

ArgFPR64s

const MCPhysReg ArgFPR64s[]

Initial value:

= {
    LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
    LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64}

Definition at line 3226 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch(), and llvm::RISCV::CC_RISCV().

ArgGPRs

const MCPhysReg ArgGPRs[]

Initial value:

= {LoongArch::R4,  LoongArch::R5, LoongArch::R6,
                             LoongArch::R7,  LoongArch::R8, LoongArch::R9,
                             LoongArch::R10, LoongArch::R11}

Definition at line 3217 of file LoongArchISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), llvm::RISCV::CC_RISCV(), CC_RISCVAssign2XLen(), llvm::LoongArchTargetLowering::LowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

ArgVRs

const MCPhysReg ArgVRs[]

Initial value:

= {LoongArch::VR0, LoongArch::VR1, LoongArch::VR2,
                            LoongArch::VR3, LoongArch::VR4, LoongArch::VR5,
                            LoongArch::VR6, LoongArch::VR7}

Definition at line 3230 of file LoongArchISelLowering.cpp.

Referenced by allocateRVVReg(), and CC_LoongArch().

ArgXRs

const MCPhysReg ArgXRs[]

Initial value:

= {LoongArch::XR0, LoongArch::XR1, LoongArch::XR2,
                            LoongArch::XR3, LoongArch::XR4, LoongArch::XR5,
                            LoongArch::XR6, LoongArch::XR7}

Definition at line 3234 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

ZeroDivCheck

cl::opt< bool > ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false)) ( "loongarch-check-zero-division"  , cl::Hidden  , cl::desc("Trap on integer division by zero.")  , cl::init(false)    )

static

Referenced by insertDivByZeroTrap().