LLVM  16.0.0git
Macros | Functions | Variables
LoongArchISelLowering.cpp File Reference
#include "LoongArchISelLowering.h"
#include "LoongArch.h"
#include "LoongArchMachineFunctionInfo.h"
#include "LoongArchRegisterInfo.h"
#include "LoongArchSubtarget.h"
#include "LoongArchTargetMachine.h"
#include "MCTargetDesc/LoongArchMCTargetDesc.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/KnownBits.h"
Include dependency graph for LoongArchISelLowering.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "loongarch-isel-lowering"
 
#define NODE_NAME_CASE(node)
 

Functions

static LoongArchISD::NodeType getLoongArchWOpcode (unsigned Opcode)
 
static SDValue customLegalizeToWOp (SDNode *N, SelectionDAG &DAG, int NumOp, unsigned ExtOpc=ISD::ANY_EXTEND)
 
static SDValue performANDCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performSRLCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performORCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static SDValue performBITREV_WCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const LoongArchSubtarget &Subtarget)
 
static MachineBasicBlockinsertDivByZeroTrap (MachineInstr &MI, MachineBasicBlock *MBB)
 
static bool CC_LoongArchAssign2GRLen (unsigned GRLen, CCState &State, CCValAssign VA1, ISD::ArgFlagsTy ArgFlags1, unsigned ValNo2, MVT ValVT2, MVT LocVT2, ISD::ArgFlagsTy ArgFlags2)
 
static bool CC_LoongArch (const DataLayout &DL, LoongArchABI::ABI ABI, unsigned ValNo, MVT ValVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy)
 
static SDValue convertLocVTToValVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue unpackFromRegLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL, const LoongArchTargetLowering &TLI)
 
static SDValue unpackFromMemLoc (SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
 
static SDValue convertValVTToLocVT (SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
 
static Align getPrefTypeAlign (EVT VT, SelectionDAG &DAG)
 

Variables

static cl::opt< bool > ZeroDivCheck ("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
 
const MCPhysReg ArgGPRs []
 
const MCPhysReg ArgFPR32s []
 
const MCPhysReg ArgFPR64s []
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "loongarch-isel-lowering"

Definition at line 28 of file LoongArchISelLowering.cpp.

◆ NODE_NAME_CASE

#define NODE_NAME_CASE (   node)
Value:
return "LoongArchISD::" #node;

Function Documentation

◆ CC_LoongArch()

static bool CC_LoongArch ( const DataLayout DL,
LoongArchABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState State,
bool  IsFixed,
bool  IsRet,
Type OrigTy 
)
static

◆ CC_LoongArchAssign2GRLen()

static bool CC_LoongArchAssign2GRLen ( unsigned  GRLen,
CCState State,
CCValAssign  VA1,
ISD::ArgFlagsTy  ArgFlags1,
unsigned  ValNo2,
MVT  ValVT2,
MVT  LocVT2,
ISD::ArgFlagsTy  ArgFlags2 
)
static

◆ convertLocVTToValVT()

static SDValue convertLocVTToValVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ convertValVTToLocVT()

static SDValue convertValVTToLocVT ( SelectionDAG DAG,
SDValue  Val,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ customLegalizeToWOp()

static SDValue customLegalizeToWOp ( SDNode N,
SelectionDAG DAG,
int  NumOp,
unsigned  ExtOpc = ISD::ANY_EXTEND 
)
static

◆ getLoongArchWOpcode()

static LoongArchISD::NodeType getLoongArchWOpcode ( unsigned  Opcode)
static

◆ getPrefTypeAlign()

static Align getPrefTypeAlign ( EVT  VT,
SelectionDAG DAG 
)
static

◆ insertDivByZeroTrap()

static MachineBasicBlock* insertDivByZeroTrap ( MachineInstr MI,
MachineBasicBlock MBB 
)
static

◆ performANDCombine()

static SDValue performANDCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performBITREV_WCombine()

static SDValue performBITREV_WCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ performSRLCombine()

static SDValue performSRLCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const LoongArchSubtarget Subtarget 
)
static

◆ unpackFromMemLoc()

static SDValue unpackFromMemLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL 
)
static

◆ unpackFromRegLoc()

static SDValue unpackFromRegLoc ( SelectionDAG DAG,
SDValue  Chain,
const CCValAssign VA,
const SDLoc DL,
const LoongArchTargetLowering TLI 
)
static

Variable Documentation

◆ ArgFPR32s

const MCPhysReg ArgFPR32s[]
Initial value:
= {LoongArch::F0, LoongArch::F1, LoongArch::F2,
LoongArch::F3, LoongArch::F4, LoongArch::F5,
LoongArch::F6, LoongArch::F7}

Definition at line 1000 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

◆ ArgFPR64s

const MCPhysReg ArgFPR64s[]
Initial value:
= {
LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64,
LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64}

Definition at line 1004 of file LoongArchISelLowering.cpp.

Referenced by CC_LoongArch().

◆ ArgGPRs

const MCPhysReg ArgGPRs[]
Initial value:
= {LoongArch::R4, LoongArch::R5, LoongArch::R6,
LoongArch::R7, LoongArch::R8, LoongArch::R9,
LoongArch::R10, LoongArch::R11}

Definition at line 995 of file LoongArchISelLowering.cpp.

Referenced by llvm::CC_CSKY_ABIV2_SOFT_64(), CC_LoongArch(), CC_LoongArchAssign2GRLen(), llvm::LoongArchTargetLowering::LowerFormalArguments(), and llvm::Ret_CSKY_ABIV2_SOFT_64().

◆ ZeroDivCheck

cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden, cl::desc("Trap on integer division by zero."), cl::init(false))
static

Referenced by insertDivByZeroTrap().

R4
#define R4(n)
node
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper node
Definition: README-SSE.txt:406
R6
#define R6(n)