LLVM  15.0.0git
CSKYISelLowering.cpp
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1 //===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that CSKY uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "CSKYISelLowering.h"
15 #include "CSKYCallingConv.h"
16 #include "CSKYConstantPoolValue.h"
18 #include "CSKYRegisterInfo.h"
19 #include "CSKYSubtarget.h"
20 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "csky-isel-lowering"
29 
30 STATISTIC(NumTailCalls, "Number of tail calls");
31 
32 #include "CSKYGenCallingConv.inc"
33 
34 static const MCPhysReg GPRArgRegs[] = {CSKY::R0, CSKY::R1, CSKY::R2, CSKY::R3};
35 
37  const CSKYSubtarget &STI)
38  : TargetLowering(TM), Subtarget(STI) {
39  // Register Class
40  addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
41 
42  if (STI.useHardFloat()) {
43  if (STI.hasFPUv2SingleFloat())
44  addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
45  else if (STI.hasFPUv3SingleFloat())
46  addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
47 
48  if (STI.hasFPUv2DoubleFloat())
49  addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
50  else if (STI.hasFPUv3DoubleFloat())
51  addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
52  }
53 
57 
81 
85 
92 
93  if (!Subtarget.hasE2()) {
98  }
99 
100  if (!Subtarget.has2E3()) {
105  }
106 
108 
109  // Float
110 
111  ISD::CondCode FPCCToExtend[] = {
114  };
115 
116  ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
118 
119  if (STI.useHardFloat()) {
120 
121  MVT AllVTy[] = {MVT::f32, MVT::f64};
122 
123  for (auto VT : AllVTy) {
127 
128  for (auto CC : FPCCToExtend)
129  setCondCodeAction(CC, VT, Expand);
130  for (auto Op : FPOpToExpand)
132  }
133 
134  if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
136  }
137  if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
140  }
141  }
142 
143  // Compute derived properties from the register classes.
145 
148 
149  // TODO: Add atomic support fully.
151 
153  const Align FunctionAlignment(2);
154  setMinFunctionAlignment(FunctionAlignment);
156 }
157 
159  SelectionDAG &DAG) const {
160  switch (Op.getOpcode()) {
161  default:
162  llvm_unreachable("unimplemented op");
163  case ISD::GlobalAddress:
164  return LowerGlobalAddress(Op, DAG);
165  case ISD::ExternalSymbol:
166  return LowerExternalSymbol(Op, DAG);
168  return LowerGlobalTLSAddress(Op, DAG);
169  case ISD::JumpTable:
170  return LowerJumpTable(Op, DAG);
171  case ISD::BlockAddress:
172  return LowerBlockAddress(Op, DAG);
173  case ISD::VASTART:
174  return LowerVASTART(Op, DAG);
175  case ISD::FRAMEADDR:
176  return LowerFRAMEADDR(Op, DAG);
177  case ISD::RETURNADDR:
178  return LowerRETURNADDR(Op, DAG);
179  }
180 }
181 
183  LLVMContext &Context, EVT VT) const {
184  if (!VT.isVector())
185  return MVT::i32;
186 
188 }
189 
191  const CCValAssign &VA, const SDLoc &DL) {
192  EVT LocVT = VA.getLocVT();
193 
194  switch (VA.getLocInfo()) {
195  default:
196  llvm_unreachable("Unexpected CCValAssign::LocInfo");
197  case CCValAssign::Full:
198  break;
199  case CCValAssign::BCvt:
200  Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
201  break;
202  }
203  return Val;
204 }
205 
207  const CCValAssign &VA, const SDLoc &DL) {
208  switch (VA.getLocInfo()) {
209  default:
210  llvm_unreachable("Unexpected CCValAssign::LocInfo");
211  case CCValAssign::Full:
212  break;
213  case CCValAssign::BCvt:
214  Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
215  break;
216  }
217  return Val;
218 }
219 
220 static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget,
221  SelectionDAG &DAG, SDValue Chain,
222  const CCValAssign &VA, const SDLoc &DL) {
224  MachineRegisterInfo &RegInfo = MF.getRegInfo();
225  EVT LocVT = VA.getLocVT();
226  SDValue Val;
227  const TargetRegisterClass *RC;
228 
229  switch (LocVT.getSimpleVT().SimpleTy) {
230  default:
231  llvm_unreachable("Unexpected register type");
232  case MVT::i32:
233  RC = &CSKY::GPRRegClass;
234  break;
235  case MVT::f32:
236  RC = Subtarget.hasFPUv2SingleFloat() ? &CSKY::sFPR32RegClass
237  : &CSKY::FPR32RegClass;
238  break;
239  case MVT::f64:
240  RC = Subtarget.hasFPUv2DoubleFloat() ? &CSKY::sFPR64RegClass
241  : &CSKY::FPR64RegClass;
242  break;
243  }
244 
245  Register VReg = RegInfo.createVirtualRegister(RC);
246  RegInfo.addLiveIn(VA.getLocReg(), VReg);
247  Val = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
248 
249  return convertLocVTToValVT(DAG, Val, VA, DL);
250 }
251 
253  const CCValAssign &VA, const SDLoc &DL) {
255  MachineFrameInfo &MFI = MF.getFrameInfo();
256  EVT LocVT = VA.getLocVT();
257  EVT ValVT = VA.getValVT();
259  int FI = MFI.CreateFixedObject(ValVT.getSizeInBits() / 8,
260  VA.getLocMemOffset(), /*Immutable=*/true);
261  SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
262  SDValue Val;
263 
264  ISD::LoadExtType ExtType;
265  switch (VA.getLocInfo()) {
266  default:
267  llvm_unreachable("Unexpected CCValAssign::LocInfo");
268  case CCValAssign::Full:
269  case CCValAssign::BCvt:
270  ExtType = ISD::NON_EXTLOAD;
271  break;
272  }
273  Val = DAG.getExtLoad(
274  ExtType, DL, LocVT, Chain, FIN,
276  return Val;
277 }
278 
279 static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA,
280  const SDLoc &DL) {
281  assert(VA.getLocVT() == MVT::i32 &&
282  (VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::i64) &&
283  "Unexpected VA");
285  MachineFrameInfo &MFI = MF.getFrameInfo();
286  MachineRegisterInfo &RegInfo = MF.getRegInfo();
287 
288  if (VA.isMemLoc()) {
289  // f64/i64 is passed on the stack.
290  int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), /*Immutable=*/true);
291  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
292  return DAG.getLoad(VA.getValVT(), DL, Chain, FIN,
294  }
295 
296  assert(VA.isRegLoc() && "Expected register VA assignment");
297 
298  Register LoVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
299  RegInfo.addLiveIn(VA.getLocReg(), LoVReg);
300  SDValue Lo = DAG.getCopyFromReg(Chain, DL, LoVReg, MVT::i32);
301  SDValue Hi;
302  if (VA.getLocReg() == CSKY::R3) {
303  // Second half of f64/i64 is passed on the stack.
304  int FI = MFI.CreateFixedObject(4, 0, /*Immutable=*/true);
305  SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
306  Hi = DAG.getLoad(MVT::i32, DL, Chain, FIN,
308  } else {
309  // Second half of f64/i64 is passed in another GPR.
310  Register HiVReg = RegInfo.createVirtualRegister(&CSKY::GPRRegClass);
311  RegInfo.addLiveIn(VA.getLocReg() + 1, HiVReg);
312  Hi = DAG.getCopyFromReg(Chain, DL, HiVReg, MVT::i32);
313  }
314  return DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(), Lo, Hi);
315 }
316 
317 // Transform physical registers into virtual registers.
318 SDValue CSKYTargetLowering::LowerFormalArguments(
319  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
321  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
322 
323  switch (CallConv) {
324  default:
325  report_fatal_error("Unsupported calling convention");
326  case CallingConv::C:
327  case CallingConv::Fast:
328  break;
329  }
330 
332 
333  // Used with vargs to acumulate store chains.
334  std::vector<SDValue> OutChains;
335 
336  // Assign locations to all of the incoming arguments.
338  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
339 
340  CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg));
341 
342  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
343  CCValAssign &VA = ArgLocs[i];
344  SDValue ArgValue;
345 
346  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
347 
348  if (IsF64OnCSKY)
349  ArgValue = unpack64(DAG, Chain, VA, DL);
350  else if (VA.isRegLoc())
351  ArgValue = unpackFromRegLoc(Subtarget, DAG, Chain, VA, DL);
352  else
353  ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
354 
355  InVals.push_back(ArgValue);
356  }
357 
358  if (IsVarArg) {
359  const unsigned XLenInBytes = 4;
360  const MVT XLenVT = MVT::i32;
361 
363  unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
364  const TargetRegisterClass *RC = &CSKY::GPRRegClass;
365  MachineFrameInfo &MFI = MF.getFrameInfo();
366  MachineRegisterInfo &RegInfo = MF.getRegInfo();
368 
369  // Offset of the first variable argument from stack pointer, and size of
370  // the vararg save area. For now, the varargs save area is either zero or
371  // large enough to hold a0-a4.
372  int VaArgOffset, VarArgsSaveSize;
373 
374  // If all registers are allocated, then all varargs must be passed on the
375  // stack and we don't need to save any argregs.
376  if (ArgRegs.size() == Idx) {
377  VaArgOffset = CCInfo.getNextStackOffset();
378  VarArgsSaveSize = 0;
379  } else {
380  VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);
381  VaArgOffset = -VarArgsSaveSize;
382  }
383 
384  // Record the frame index of the first variable argument
385  // which is a value necessary to VASTART.
386  int FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
387  CSKYFI->setVarArgsFrameIndex(FI);
388 
389  // Copy the integer registers that may have been used for passing varargs
390  // to the vararg save area.
391  for (unsigned I = Idx; I < ArgRegs.size();
392  ++I, VaArgOffset += XLenInBytes) {
393  const Register Reg = RegInfo.createVirtualRegister(RC);
394  RegInfo.addLiveIn(ArgRegs[I], Reg);
395  SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, XLenVT);
396  FI = MFI.CreateFixedObject(XLenInBytes, VaArgOffset, true);
397  SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
398  SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
400  cast<StoreSDNode>(Store.getNode())
401  ->getMemOperand()
402  ->setValue((Value *)nullptr);
403  OutChains.push_back(Store);
404  }
405  CSKYFI->setVarArgsSaveSize(VarArgsSaveSize);
406  }
407 
408  // All stores are grouped in one node to allow the matching between
409  // the size of Ins and InVals. This only happens for vararg functions.
410  if (!OutChains.empty()) {
411  OutChains.push_back(Chain);
412  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
413  }
414 
415  return Chain;
416 }
417 
418 bool CSKYTargetLowering::CanLowerReturn(
419  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
422  CCState CCInfo(CallConv, IsVarArg, MF, CSKYLocs, Context);
423  return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
424 }
425 
426 SDValue
427 CSKYTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
428  bool IsVarArg,
430  const SmallVectorImpl<SDValue> &OutVals,
431  const SDLoc &DL, SelectionDAG &DAG) const {
432  // Stores the assignment of the return value to a location.
434 
435  // Info about the registers and stack slot.
436  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CSKYLocs,
437  *DAG.getContext());
438  CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
439 
440  SDValue Glue;
441  SmallVector<SDValue, 4> RetOps(1, Chain);
442 
443  // Copy the result values into the output registers.
444  for (unsigned i = 0, e = CSKYLocs.size(); i < e; ++i) {
445  SDValue Val = OutVals[i];
446  CCValAssign &VA = CSKYLocs[i];
447  assert(VA.isRegLoc() && "Can only return in registers!");
448 
449  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
450 
451  if (IsF64OnCSKY) {
452 
453  assert(VA.isRegLoc() && "Expected return via registers");
455  DAG.getVTList(MVT::i32, MVT::i32), Val);
456  SDValue Lo = Split64.getValue(0);
457  SDValue Hi = Split64.getValue(1);
458 
459  Register RegLo = VA.getLocReg();
460  assert(RegLo < CSKY::R31 && "Invalid register pair");
461  Register RegHi = RegLo + 1;
462 
463  Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
464  Glue = Chain.getValue(1);
465  RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
466  Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
467  Glue = Chain.getValue(1);
468  RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
469  } else {
470  // Handle a 'normal' return.
471  Val = convertValVTToLocVT(DAG, Val, VA, DL);
472  Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
473 
474  // Guarantee that all emitted copies are stuck together.
475  Glue = Chain.getValue(1);
476  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
477  }
478  }
479 
480  RetOps[0] = Chain; // Update chain.
481 
482  // Add the glue node if we have it.
483  if (Glue.getNode()) {
484  RetOps.push_back(Glue);
485  }
486 
487  // Interrupt service routines use different return instructions.
488  if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
489  return DAG.getNode(CSKYISD::NIR, DL, MVT::Other, RetOps);
490 
491  return DAG.getNode(CSKYISD::RET, DL, MVT::Other, RetOps);
492 }
493 
494 // Lower a call to a callseq_start + CALL + callseq_end chain, and add input
495 // and output parameter nodes.
496 SDValue CSKYTargetLowering::LowerCall(CallLoweringInfo &CLI,
497  SmallVectorImpl<SDValue> &InVals) const {
498  SelectionDAG &DAG = CLI.DAG;
499  SDLoc &DL = CLI.DL;
500  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
501  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
503  SDValue Chain = CLI.Chain;
504  SDValue Callee = CLI.Callee;
505  bool &IsTailCall = CLI.IsTailCall;
506  CallingConv::ID CallConv = CLI.CallConv;
507  bool IsVarArg = CLI.IsVarArg;
508  EVT PtrVT = getPointerTy(DAG.getDataLayout());
509  MVT XLenVT = MVT::i32;
510 
512 
513  // Analyze the operands of the call, assigning locations to each operand.
515  CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
516 
517  ArgCCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, IsVarArg));
518 
519  // Check if it's really possible to do a tail call.
520  if (IsTailCall)
521  IsTailCall = false; // TODO: TailCallOptimization;
522 
523  if (IsTailCall)
524  ++NumTailCalls;
525  else if (CLI.CB && CLI.CB->isMustTailCall())
526  report_fatal_error("failed to perform tail call elimination on a call "
527  "site marked musttail");
528 
529  // Get a count of how many bytes are to be pushed on the stack.
530  unsigned NumBytes = ArgCCInfo.getNextStackOffset();
531 
532  // Create local copies for byval args
533  SmallVector<SDValue, 8> ByValArgs;
534  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
535  ISD::ArgFlagsTy Flags = Outs[i].Flags;
536  if (!Flags.isByVal())
537  continue;
538 
539  SDValue Arg = OutVals[i];
540  unsigned Size = Flags.getByValSize();
542 
543  int FI =
544  MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false);
545  SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
546  SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT);
547 
548  Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,
549  /*IsVolatile=*/false,
550  /*AlwaysInline=*/false, IsTailCall,
552  ByValArgs.push_back(FIPtr);
553  }
554 
555  if (!IsTailCall)
556  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
557 
558  // Copy argument values to their designated locations.
560  SmallVector<SDValue, 8> MemOpChains;
562  for (unsigned i = 0, j = 0, e = ArgLocs.size(); i != e; ++i) {
563  CCValAssign &VA = ArgLocs[i];
564  SDValue ArgValue = OutVals[i];
565  ISD::ArgFlagsTy Flags = Outs[i].Flags;
566 
567  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
568 
569  if (IsF64OnCSKY && VA.isRegLoc()) {
570  SDValue Split64 =
572  DAG.getVTList(MVT::i32, MVT::i32), ArgValue);
573  SDValue Lo = Split64.getValue(0);
574  SDValue Hi = Split64.getValue(1);
575 
576  Register RegLo = VA.getLocReg();
577  RegsToPass.push_back(std::make_pair(RegLo, Lo));
578 
579  if (RegLo == CSKY::R3) {
580  // Second half of f64/i64 is passed on the stack.
581  // Work out the address of the stack slot.
582  if (!StackPtr.getNode())
583  StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
584  // Emit the store.
585  MemOpChains.push_back(
586  DAG.getStore(Chain, DL, Hi, StackPtr, MachinePointerInfo()));
587  } else {
588  // Second half of f64/i64 is passed in another GPR.
589  assert(RegLo < CSKY::R31 && "Invalid register pair");
590  Register RegHigh = RegLo + 1;
591  RegsToPass.push_back(std::make_pair(RegHigh, Hi));
592  }
593  continue;
594  }
595 
596  ArgValue = convertValVTToLocVT(DAG, ArgValue, VA, DL);
597 
598  // Use local copy if it is a byval arg.
599  if (Flags.isByVal())
600  ArgValue = ByValArgs[j++];
601 
602  if (VA.isRegLoc()) {
603  // Queue up the argument copies and emit them at the end.
604  RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
605  } else {
606  assert(VA.isMemLoc() && "Argument not register or memory");
607  assert(!IsTailCall && "Tail call not allowed if stack is used "
608  "for passing parameters");
609 
610  // Work out the address of the stack slot.
611  if (!StackPtr.getNode())
612  StackPtr = DAG.getCopyFromReg(Chain, DL, CSKY::R14, PtrVT);
613  SDValue Address =
614  DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
616 
617  // Emit the store.
618  MemOpChains.push_back(
619  DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo()));
620  }
621  }
622 
623  // Join the stores, which are independent of one another.
624  if (!MemOpChains.empty())
625  Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
626 
627  SDValue Glue;
628 
629  // Build a sequence of copy-to-reg nodes, chained and glued together.
630  for (auto &Reg : RegsToPass) {
631  Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
632  Glue = Chain.getValue(1);
633  }
634 
636  EVT Ty = getPointerTy(DAG.getDataLayout());
637  bool IsRegCall = false;
638 
639  Ops.push_back(Chain);
640 
641  if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
642  const GlobalValue *GV = S->getGlobal();
643  bool IsLocal =
645 
646  if (isPositionIndependent() || !Subtarget.has2E3()) {
647  IsRegCall = true;
648  Ops.push_back(getAddr<GlobalAddressSDNode, true>(S, DAG, IsLocal));
649  } else {
650  Ops.push_back(getTargetNode(cast<GlobalAddressSDNode>(Callee), DL, Ty,
651  DAG, CSKYII::MO_None));
652  Ops.push_back(getTargetConstantPoolValue(
653  cast<GlobalAddressSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
654  }
655  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
656  bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(
657  *MF.getFunction().getParent(), nullptr);
658 
659  if (isPositionIndependent() || !Subtarget.has2E3()) {
660  IsRegCall = true;
661  Ops.push_back(getAddr<ExternalSymbolSDNode, true>(S, DAG, IsLocal));
662  } else {
663  Ops.push_back(getTargetNode(cast<ExternalSymbolSDNode>(Callee), DL, Ty,
664  DAG, CSKYII::MO_None));
665  Ops.push_back(getTargetConstantPoolValue(
666  cast<ExternalSymbolSDNode>(Callee), Ty, DAG, CSKYII::MO_None));
667  }
668  } else {
669  IsRegCall = true;
670  Ops.push_back(Callee);
671  }
672 
673  // Add argument registers to the end of the list so that they are
674  // known live into the call.
675  for (auto &Reg : RegsToPass)
676  Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
677 
678  if (!IsTailCall) {
679  // Add a register mask operand representing the call-preserved registers.
680  const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
681  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
682  assert(Mask && "Missing call preserved mask for calling convention");
683  Ops.push_back(DAG.getRegisterMask(Mask));
684  }
685 
686  // Glue the call to the argument copies, if any.
687  if (Glue.getNode())
688  Ops.push_back(Glue);
689 
690  // Emit the call.
691  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
692 
693  if (IsTailCall) {
695  return DAG.getNode(IsRegCall ? CSKYISD::TAILReg : CSKYISD::TAIL, DL,
696  NodeTys, Ops);
697  }
698 
699  Chain = DAG.getNode(IsRegCall ? CSKYISD::CALLReg : CSKYISD::CALL, DL, NodeTys,
700  Ops);
701  DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
702  Glue = Chain.getValue(1);
703 
704  // Mark the end of the call, which is glued to the call itself.
705  Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true),
706  DAG.getConstant(0, DL, PtrVT, true), Glue, DL);
707  Glue = Chain.getValue(1);
708 
709  // Assign locations to each value returned by this call.
711  CCState RetCCInfo(CallConv, IsVarArg, MF, CSKYLocs, *DAG.getContext());
712  RetCCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, IsVarArg));
713 
714  // Copy all of the result registers out of their specified physreg.
715  for (auto &VA : CSKYLocs) {
716  // Copy the value out
717  SDValue RetValue =
718  DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue);
719  // Glue the RetValue to the end of the call sequence
720  Chain = RetValue.getValue(1);
721  Glue = RetValue.getValue(2);
722 
723  bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64;
724 
725  if (IsF64OnCSKY) {
726  assert(VA.getLocReg() == GPRArgRegs[0] && "Unexpected reg assignment");
727  SDValue RetValue2 =
728  DAG.getCopyFromReg(Chain, DL, GPRArgRegs[1], MVT::i32, Glue);
729  Chain = RetValue2.getValue(1);
730  Glue = RetValue2.getValue(2);
731  RetValue = DAG.getNode(CSKYISD::BITCAST_FROM_LOHI, DL, VA.getValVT(),
732  RetValue, RetValue2);
733  }
734 
735  RetValue = convertLocVTToValVT(DAG, RetValue, VA, DL);
736 
737  InVals.push_back(RetValue);
738  }
739 
740  return Chain;
741 }
742 
743 CCAssignFn *CSKYTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
744  bool IsVarArg) const {
745  if (IsVarArg || !Subtarget.useHardFloatABI())
746  return RetCC_CSKY_ABIV2_SOFT;
747  else
748  return RetCC_CSKY_ABIV2_FP;
749 }
750 
751 CCAssignFn *CSKYTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
752  bool IsVarArg) const {
753  if (IsVarArg || !Subtarget.useHardFloatABI())
754  return CC_CSKY_ABIV2_SOFT;
755  else
756  return CC_CSKY_ABIV2_FP;
757 }
758 
759 static CSKYCP::CSKYCPModifier getModifier(unsigned Flags) {
760 
761  if (Flags == CSKYII::MO_ADDR32)
762  return CSKYCP::ADDR;
763  else if (Flags == CSKYII::MO_GOT32)
764  return CSKYCP::GOT;
765  else if (Flags == CSKYII::MO_GOTOFF)
766  return CSKYCP::GOTOFF;
767  else if (Flags == CSKYII::MO_PLT32)
768  return CSKYCP::PLT;
769  else if (Flags == CSKYII::MO_None)
770  return CSKYCP::NO_MOD;
771  else
772  assert(0 && "unknown CSKYII Modifier");
773  return CSKYCP::NO_MOD;
774 }
775 
776 SDValue CSKYTargetLowering::getTargetConstantPoolValue(GlobalAddressSDNode *N,
777  EVT Ty,
778  SelectionDAG &DAG,
779  unsigned Flags) const {
781  N->getGlobal(), CSKYCP::CPValue, 0, getModifier(Flags), false);
782 
783  return DAG.getTargetConstantPool(CPV, Ty);
784 }
785 
787 CSKYTargetLowering::getConstraintType(StringRef Constraint) const {
788  if (Constraint.size() == 1) {
789  switch (Constraint[0]) {
790  default:
791  break;
792  case 'a':
793  case 'b':
794  case 'v':
795  case 'w':
796  case 'y':
797  return C_RegisterClass;
798  case 'c':
799  case 'l':
800  case 'h':
801  case 'z':
802  return C_Register;
803  }
804  }
805  return TargetLowering::getConstraintType(Constraint);
806 }
807 
808 std::pair<unsigned, const TargetRegisterClass *>
809 CSKYTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
810  StringRef Constraint,
811  MVT VT) const {
812  if (Constraint.size() == 1) {
813  switch (Constraint[0]) {
814  case 'r':
815  return std::make_pair(0U, &CSKY::GPRRegClass);
816  case 'a':
817  return std::make_pair(0U, &CSKY::mGPRRegClass);
818  case 'b':
819  return std::make_pair(0U, &CSKY::sGPRRegClass);
820  case 'z':
821  return std::make_pair(CSKY::R14, &CSKY::GPRRegClass);
822  case 'c':
823  return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
824  case 'w':
825  if ((Subtarget.hasFPUv2SingleFloat() ||
826  Subtarget.hasFPUv3SingleFloat()) &&
827  VT == MVT::f32)
828  return std::make_pair(0U, &CSKY::sFPR32RegClass);
829  if ((Subtarget.hasFPUv2DoubleFloat() ||
830  Subtarget.hasFPUv3DoubleFloat()) &&
831  VT == MVT::f64)
832  return std::make_pair(0U, &CSKY::sFPR64RegClass);
833  break;
834  case 'v':
835  if (Subtarget.hasFPUv2SingleFloat() && VT == MVT::f32)
836  return std::make_pair(0U, &CSKY::sFPR32RegClass);
837  if (Subtarget.hasFPUv3SingleFloat() && VT == MVT::f32)
838  return std::make_pair(0U, &CSKY::FPR32RegClass);
839  if (Subtarget.hasFPUv2DoubleFloat() && VT == MVT::f64)
840  return std::make_pair(0U, &CSKY::sFPR64RegClass);
841  if (Subtarget.hasFPUv3DoubleFloat() && VT == MVT::f64)
842  return std::make_pair(0U, &CSKY::FPR64RegClass);
843  break;
844  default:
845  break;
846  }
847  }
848 
849  if (Constraint == "{c}")
850  return std::make_pair(CSKY::C, &CSKY::CARRYRegClass);
851 
852  // Clang will correctly decode the usage of register name aliases into their
853  // official names. However, other frontends like `rustc` do not. This allows
854  // users of these frontends to use the ABI names for registers in LLVM-style
855  // register constraints.
856  unsigned XRegFromAlias = StringSwitch<unsigned>(Constraint.lower())
857  .Case("{a0}", CSKY::R0)
858  .Case("{a1}", CSKY::R1)
859  .Case("{a2}", CSKY::R2)
860  .Case("{a3}", CSKY::R3)
861  .Case("{l0}", CSKY::R4)
862  .Case("{l1}", CSKY::R5)
863  .Case("{l2}", CSKY::R6)
864  .Case("{l3}", CSKY::R7)
865  .Case("{l4}", CSKY::R8)
866  .Case("{l5}", CSKY::R9)
867  .Case("{l6}", CSKY::R10)
868  .Case("{l7}", CSKY::R11)
869  .Case("{t0}", CSKY::R12)
870  .Case("{t1}", CSKY::R13)
871  .Case("{sp}", CSKY::R14)
872  .Case("{lr}", CSKY::R15)
873  .Case("{l8}", CSKY::R16)
874  .Case("{l9}", CSKY::R17)
875  .Case("{t2}", CSKY::R18)
876  .Case("{t3}", CSKY::R19)
877  .Case("{t4}", CSKY::R20)
878  .Case("{t5}", CSKY::R21)
879  .Case("{t6}", CSKY::R22)
880  .Cases("{t7}", "{fp}", CSKY::R23)
881  .Cases("{t8}", "{top}", CSKY::R24)
882  .Cases("{t9}", "{bsp}", CSKY::R25)
883  .Case("{r26}", CSKY::R26)
884  .Case("{r27}", CSKY::R27)
885  .Cases("{gb}", "{rgb}", "{rdb}", CSKY::R28)
886  .Cases("{tb}", "{rtb}", CSKY::R29)
887  .Case("{svbr}", CSKY::R30)
888  .Case("{tls}", CSKY::R31)
889  .Default(CSKY::NoRegister);
890 
891  if (XRegFromAlias != CSKY::NoRegister)
892  return std::make_pair(XRegFromAlias, &CSKY::GPRRegClass);
893 
894  // Since TargetLowering::getRegForInlineAsmConstraint uses the name of the
895  // TableGen record rather than the AsmName to choose registers for InlineAsm
896  // constraints, plus we want to match those names to the widest floating point
897  // register type available, manually select floating point registers here.
898  //
899  // The second case is the ABI name of the register, so that frontends can also
900  // use the ABI names in register constraint lists.
901  if (Subtarget.useHardFloat()) {
902  unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
903  .Cases("{fr0}", "{vr0}", CSKY::F0_32)
904  .Cases("{fr1}", "{vr1}", CSKY::F1_32)
905  .Cases("{fr2}", "{vr2}", CSKY::F2_32)
906  .Cases("{fr3}", "{vr3}", CSKY::F3_32)
907  .Cases("{fr4}", "{vr4}", CSKY::F4_32)
908  .Cases("{fr5}", "{vr5}", CSKY::F5_32)
909  .Cases("{fr6}", "{vr6}", CSKY::F6_32)
910  .Cases("{fr7}", "{vr7}", CSKY::F7_32)
911  .Cases("{fr8}", "{vr8}", CSKY::F8_32)
912  .Cases("{fr9}", "{vr9}", CSKY::F9_32)
913  .Cases("{fr10}", "{vr10}", CSKY::F10_32)
914  .Cases("{fr11}", "{vr11}", CSKY::F11_32)
915  .Cases("{fr12}", "{vr12}", CSKY::F12_32)
916  .Cases("{fr13}", "{vr13}", CSKY::F13_32)
917  .Cases("{fr14}", "{vr14}", CSKY::F14_32)
918  .Cases("{fr15}", "{vr15}", CSKY::F15_32)
919  .Cases("{fr16}", "{vr16}", CSKY::F16_32)
920  .Cases("{fr17}", "{vr17}", CSKY::F17_32)
921  .Cases("{fr18}", "{vr18}", CSKY::F18_32)
922  .Cases("{fr19}", "{vr19}", CSKY::F19_32)
923  .Cases("{fr20}", "{vr20}", CSKY::F20_32)
924  .Cases("{fr21}", "{vr21}", CSKY::F21_32)
925  .Cases("{fr22}", "{vr22}", CSKY::F22_32)
926  .Cases("{fr23}", "{vr23}", CSKY::F23_32)
927  .Cases("{fr24}", "{vr24}", CSKY::F24_32)
928  .Cases("{fr25}", "{vr25}", CSKY::F25_32)
929  .Cases("{fr26}", "{vr26}", CSKY::F26_32)
930  .Cases("{fr27}", "{vr27}", CSKY::F27_32)
931  .Cases("{fr28}", "{vr28}", CSKY::F28_32)
932  .Cases("{fr29}", "{vr29}", CSKY::F29_32)
933  .Cases("{fr30}", "{vr30}", CSKY::F30_32)
934  .Cases("{fr31}", "{vr31}", CSKY::F31_32)
935  .Default(CSKY::NoRegister);
936  if (FReg != CSKY::NoRegister) {
937  assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg");
938  unsigned RegNo = FReg - CSKY::F0_32;
939  unsigned DReg = CSKY::F0_64 + RegNo;
940 
941  if (Subtarget.hasFPUv2DoubleFloat())
942  return std::make_pair(DReg, &CSKY::sFPR64RegClass);
943  else if (Subtarget.hasFPUv3DoubleFloat())
944  return std::make_pair(DReg, &CSKY::FPR64RegClass);
945  else if (Subtarget.hasFPUv2SingleFloat())
946  return std::make_pair(FReg, &CSKY::sFPR32RegClass);
947  else if (Subtarget.hasFPUv3SingleFloat())
948  return std::make_pair(FReg, &CSKY::FPR32RegClass);
949  }
950  }
951 
952  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
953 }
954 
955 static MachineBasicBlock *
957 
958  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
959  DebugLoc DL = MI.getDebugLoc();
960 
961  // To "insert" a SELECT instruction, we actually have to insert the
962  // diamond control-flow pattern. The incoming instruction knows the
963  // destination vreg to set, the condition code register to branch on, the
964  // true/false values to select between, and a branch opcode to use.
965  const BasicBlock *LLVM_BB = BB->getBasicBlock();
966  MachineFunction::iterator It = ++BB->getIterator();
967 
968  // thisMBB:
969  // ...
970  // TrueVal = ...
971  // bt32 c, sinkMBB
972  // fallthrough --> copyMBB
973  MachineBasicBlock *thisMBB = BB;
974  MachineFunction *F = BB->getParent();
975  MachineBasicBlock *copyMBB = F->CreateMachineBasicBlock(LLVM_BB);
976  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
977  F->insert(It, copyMBB);
978  F->insert(It, sinkMBB);
979 
980  // Transfer the remainder of BB and its successor edges to sinkMBB.
981  sinkMBB->splice(sinkMBB->begin(), BB,
982  std::next(MachineBasicBlock::iterator(MI)), BB->end());
984 
985  // Next, add the true and fallthrough blocks as its successors.
986  BB->addSuccessor(copyMBB);
987  BB->addSuccessor(sinkMBB);
988 
989  // bt32 condition, sinkMBB
990  BuildMI(BB, DL, TII.get(Opcode))
991  .addReg(MI.getOperand(1).getReg())
992  .addMBB(sinkMBB);
993 
994  // copyMBB:
995  // %FalseValue = ...
996  // # fallthrough to sinkMBB
997  BB = copyMBB;
998 
999  // Update machine-CFG edges
1000  BB->addSuccessor(sinkMBB);
1001 
1002  // sinkMBB:
1003  // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copyMBB ]
1004  // ...
1005  BB = sinkMBB;
1006 
1007  BuildMI(*BB, BB->begin(), DL, TII.get(CSKY::PHI), MI.getOperand(0).getReg())
1008  .addReg(MI.getOperand(2).getReg())
1009  .addMBB(thisMBB)
1010  .addReg(MI.getOperand(3).getReg())
1011  .addMBB(copyMBB);
1012 
1013  MI.eraseFromParent(); // The pseudo instruction is gone now.
1014 
1015  return BB;
1016 }
1017 
1019 CSKYTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1020  MachineBasicBlock *BB) const {
1021  switch (MI.getOpcode()) {
1022  default:
1023  llvm_unreachable("Unexpected instr type to insert");
1024  case CSKY::FSELS:
1025  case CSKY::FSELD:
1026  if (Subtarget.hasE2())
1027  return emitSelectPseudo(MI, BB, CSKY::BT32);
1028  else
1029  return emitSelectPseudo(MI, BB, CSKY::BT16);
1030  case CSKY::ISEL32:
1031  return emitSelectPseudo(MI, BB, CSKY::BT32);
1032  case CSKY::ISEL16:
1033  return emitSelectPseudo(MI, BB, CSKY::BT16);
1034  }
1035 }
1036 
1037 SDValue CSKYTargetLowering::getTargetConstantPoolValue(ExternalSymbolSDNode *N,
1038  EVT Ty,
1039  SelectionDAG &DAG,
1040  unsigned Flags) const {
1041  CSKYConstantPoolValue *CPV =
1043  N->getSymbol(), 0, getModifier(Flags));
1044 
1045  return DAG.getTargetConstantPool(CPV, Ty);
1046 }
1047 
1048 SDValue CSKYTargetLowering::getTargetConstantPoolValue(JumpTableSDNode *N,
1049  EVT Ty,
1050  SelectionDAG &DAG,
1051  unsigned Flags) const {
1052  CSKYConstantPoolValue *CPV =
1054  N->getIndex(), 0, getModifier(Flags));
1055  return DAG.getTargetConstantPool(CPV, Ty);
1056 }
1057 
1058 SDValue CSKYTargetLowering::getTargetConstantPoolValue(BlockAddressSDNode *N,
1059  EVT Ty,
1060  SelectionDAG &DAG,
1061  unsigned Flags) const {
1063  N->getBlockAddress(), CSKYCP::CPBlockAddress, 0, getModifier(Flags),
1064  false);
1065  return DAG.getTargetConstantPool(CPV, Ty);
1066 }
1067 
1068 SDValue CSKYTargetLowering::getTargetNode(GlobalAddressSDNode *N, SDLoc DL,
1069  EVT Ty, SelectionDAG &DAG,
1070  unsigned Flags) const {
1071  return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
1072 }
1073 
1074 SDValue CSKYTargetLowering::getTargetNode(ExternalSymbolSDNode *N, SDLoc DL,
1075  EVT Ty, SelectionDAG &DAG,
1076  unsigned Flags) const {
1077  return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flags);
1078 }
1079 
1080 SDValue CSKYTargetLowering::getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
1081  SelectionDAG &DAG,
1082  unsigned Flags) const {
1083  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
1084 }
1085 
1086 SDValue CSKYTargetLowering::getTargetNode(BlockAddressSDNode *N, SDLoc DL,
1087  EVT Ty, SelectionDAG &DAG,
1088  unsigned Flags) const {
1089  return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, N->getOffset(),
1090  Flags);
1091 }
1092 
1093 const char *CSKYTargetLowering::getTargetNodeName(unsigned Opcode) const {
1094  switch (Opcode) {
1095  default:
1096  llvm_unreachable("unknown CSKYISD node");
1097  case CSKYISD::NIE:
1098  return "CSKYISD::NIE";
1099  case CSKYISD::NIR:
1100  return "CSKYISD::NIR";
1101  case CSKYISD::RET:
1102  return "CSKYISD::RET";
1103  case CSKYISD::CALL:
1104  return "CSKYISD::CALL";
1105  case CSKYISD::CALLReg:
1106  return "CSKYISD::CALLReg";
1107  case CSKYISD::TAIL:
1108  return "CSKYISD::TAIL";
1109  case CSKYISD::TAILReg:
1110  return "CSKYISD::TAILReg";
1111  case CSKYISD::LOAD_ADDR:
1112  return "CSKYISD::LOAD_ADDR";
1114  return "CSKYISD::BITCAST_TO_LOHI";
1116  return "CSKYISD::BITCAST_FROM_LOHI";
1117  }
1118 }
1119 
1120 SDValue CSKYTargetLowering::LowerGlobalAddress(SDValue Op,
1121  SelectionDAG &DAG) const {
1122  SDLoc DL(Op);
1123  EVT Ty = Op.getValueType();
1124  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1125  int64_t Offset = N->getOffset();
1126 
1127  const GlobalValue *GV = N->getGlobal();
1128  bool IsLocal = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1129  SDValue Addr = getAddr<GlobalAddressSDNode, false>(N, DAG, IsLocal);
1130 
1131  // In order to maximise the opportunity for common subexpression elimination,
1132  // emit a separate ADD node for the global address offset instead of folding
1133  // it in the global address node. Later peephole optimisations may choose to
1134  // fold it back in when profitable.
1135  if (Offset != 0)
1136  return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1137  DAG.getConstant(Offset, DL, MVT::i32));
1138  return Addr;
1139 }
1140 
1141 SDValue CSKYTargetLowering::LowerExternalSymbol(SDValue Op,
1142  SelectionDAG &DAG) const {
1143  ExternalSymbolSDNode *N = cast<ExternalSymbolSDNode>(Op);
1144 
1145  return getAddr(N, DAG, false);
1146 }
1147 
1148 SDValue CSKYTargetLowering::LowerJumpTable(SDValue Op,
1149  SelectionDAG &DAG) const {
1150  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1151 
1152  return getAddr<JumpTableSDNode, false>(N, DAG);
1153 }
1154 
1155 SDValue CSKYTargetLowering::LowerBlockAddress(SDValue Op,
1156  SelectionDAG &DAG) const {
1157  BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1158 
1159  return getAddr(N, DAG);
1160 }
1161 
1162 SDValue CSKYTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1163  MachineFunction &MF = DAG.getMachineFunction();
1165 
1166  SDLoc DL(Op);
1167  SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1168  getPointerTy(MF.getDataLayout()));
1169 
1170  // vastart just stores the address of the VarArgsFrameIndex slot into the
1171  // memory location argument.
1172  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1173  return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1174  MachinePointerInfo(SV));
1175 }
1176 
1177 SDValue CSKYTargetLowering::LowerFRAMEADDR(SDValue Op,
1178  SelectionDAG &DAG) const {
1179  const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1180  MachineFunction &MF = DAG.getMachineFunction();
1181  MachineFrameInfo &MFI = MF.getFrameInfo();
1182  MFI.setFrameAddressIsTaken(true);
1183 
1184  EVT VT = Op.getValueType();
1185  SDLoc dl(Op);
1186  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1187  Register FrameReg = RI.getFrameRegister(MF);
1188  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1189  while (Depth--)
1190  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1191  MachinePointerInfo());
1192  return FrameAddr;
1193 }
1194 
1195 SDValue CSKYTargetLowering::LowerRETURNADDR(SDValue Op,
1196  SelectionDAG &DAG) const {
1197  const CSKYRegisterInfo &RI = *Subtarget.getRegisterInfo();
1198  MachineFunction &MF = DAG.getMachineFunction();
1199  MachineFrameInfo &MFI = MF.getFrameInfo();
1200  MFI.setReturnAddressIsTaken(true);
1201 
1203  return SDValue();
1204 
1205  EVT VT = Op.getValueType();
1206  SDLoc dl(Op);
1207  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1208  if (Depth) {
1209  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1210  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1211  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1212  DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1213  MachinePointerInfo());
1214  }
1215  // Return the value of the return address register, marking it an implicit
1216  // live-in.
1217  unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(MVT::i32));
1218  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1219 }
1220 
1221 Register CSKYTargetLowering::getExceptionPointerRegister(
1222  const Constant *PersonalityFn) const {
1223  return CSKY::R0;
1224 }
1225 
1226 Register CSKYTargetLowering::getExceptionSelectorRegister(
1227  const Constant *PersonalityFn) const {
1228  return CSKY::R1;
1229 }
1230 
1231 SDValue CSKYTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1232  SelectionDAG &DAG) const {
1233  SDLoc DL(Op);
1234  EVT Ty = Op.getValueType();
1235  GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1236  int64_t Offset = N->getOffset();
1237  MVT XLenVT = MVT::i32;
1238 
1240  SDValue Addr;
1241  switch (Model) {
1242  case TLSModel::LocalExec:
1243  Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
1244  break;
1245  case TLSModel::InitialExec:
1246  Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
1247  break;
1250  Addr = getDynamicTLSAddr(N, DAG);
1251  break;
1252  }
1253 
1254  // In order to maximise the opportunity for common subexpression elimination,
1255  // emit a separate ADD node for the global address offset instead of folding
1256  // it in the global address node. Later peephole optimisations may choose to
1257  // fold it back in when profitable.
1258  if (Offset != 0)
1259  return DAG.getNode(ISD::ADD, DL, Ty, Addr,
1260  DAG.getConstant(Offset, DL, XLenVT));
1261  return Addr;
1262 }
1263 
1264 SDValue CSKYTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
1265  SelectionDAG &DAG,
1266  bool UseGOT) const {
1267  MachineFunction &MF = DAG.getMachineFunction();
1269 
1270  unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1271 
1272  SDLoc DL(N);
1273  EVT Ty = getPointerTy(DAG.getDataLayout());
1274 
1276  bool AddCurrentAddr = UseGOT ? true : false;
1277  unsigned char PCAjust = UseGOT ? 4 : 0;
1278 
1279  CSKYConstantPoolValue *CPV =
1280  CSKYConstantPoolConstant::Create(N->getGlobal(), CSKYCP::CPValue, PCAjust,
1281  Flag, AddCurrentAddr, CSKYPCLabelIndex);
1282  SDValue CAddr = DAG.getTargetConstantPool(CPV, Ty);
1283 
1284  SDValue Load;
1285  if (UseGOT) {
1286  SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1287  auto *LRWGRS = DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty},
1288  {CAddr, PICLabel});
1289  auto LRWADDGRS =
1290  DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1291  Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), LRWADDGRS,
1292  MachinePointerInfo(N->getGlobal()));
1293  } else {
1294  Load = SDValue(DAG.getMachineNode(CSKY::LRW32, DL, Ty, CAddr), 0);
1295  }
1296 
1297  // Add the thread pointer.
1298  SDValue TPReg = DAG.getRegister(CSKY::R31, MVT::i32);
1299  return DAG.getNode(ISD::ADD, DL, Ty, Load, TPReg);
1300 }
1301 
1302 SDValue CSKYTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
1303  SelectionDAG &DAG) const {
1304  MachineFunction &MF = DAG.getMachineFunction();
1306 
1307  unsigned CSKYPCLabelIndex = CFI->createPICLabelUId();
1308 
1309  SDLoc DL(N);
1310  EVT Ty = getPointerTy(DAG.getDataLayout());
1311  IntegerType *CallTy = Type::getIntNTy(*DAG.getContext(), Ty.getSizeInBits());
1312 
1313  CSKYConstantPoolValue *CPV =
1315  CSKYCP::TLSGD, true, CSKYPCLabelIndex);
1316  SDValue Addr = DAG.getTargetConstantPool(CPV, Ty);
1317  SDValue PICLabel = DAG.getTargetConstant(CSKYPCLabelIndex, DL, MVT::i32);
1318 
1319  auto *LRWGRS =
1320  DAG.getMachineNode(CSKY::PseudoTLSLA32, DL, {Ty, Ty}, {Addr, PICLabel});
1321 
1322  auto Load =
1323  DAG.getNode(ISD::ADD, DL, Ty, SDValue(LRWGRS, 0), SDValue(LRWGRS, 1));
1324 
1325  // Prepare argument list to generate call.
1326  ArgListTy Args;
1327  ArgListEntry Entry;
1328  Entry.Node = Load;
1329  Entry.Ty = CallTy;
1330  Args.push_back(Entry);
1331 
1332  // Setup call to __tls_get_addr.
1334  CLI.setDebugLoc(DL)
1335  .setChain(DAG.getEntryNode())
1336  .setLibCallee(CallingConv::C, CallTy,
1337  DAG.getExternalSymbol("__tls_get_addr", Ty),
1338  std::move(Args));
1339  SDValue V = LowerCallTo(CLI).first;
1340 
1341  return V;
1342 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:151
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
i
i
Definition: README.txt:29
llvm::ISD::ExternalSymbol
@ ExternalSymbol
Definition: ISDOpcodes.h:83
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1417
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:2224
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
Definition: SelectionDAG.h:940
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::CSKYCP::PLT
@ PLT
Definition: CSKYConstantPoolValue.h:39
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ISD::JumpTable
@ JumpTable
Definition: ISDOpcodes.h:81
llvm::CSKYCP::TLSGD
@ TLSGD
Definition: CSKYConstantPoolValue.h:39
CSKYConstantPoolValue.h
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::CCValAssign::Full
@ Full
Definition: CallingConvLower.h:34
llvm::TargetLoweringBase::Legal
@ Legal
Definition: TargetLowering.h:196
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
CSKYCallingConv.h
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:377
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4394
llvm::CSKYConstantPoolJT::Create
static CSKYConstantPoolJT * Create(Type *Ty, int JTI, unsigned PCAdj, CSKYCP::CSKYCPModifier Modifier)
Definition: CSKYConstantPoolValue.cpp:198
llvm::ISD::BR_JT
@ BR_JT
BR_JT - Jumptable branch.
Definition: ISDOpcodes.h:984
llvm::SelectionDAG::addNoMergeSiteInfo
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
Definition: SelectionDAG.h:2175
llvm::CSKYCP::CPBlockAddress
@ CPBlockAddress
Definition: CSKYConstantPoolValue.h:34
llvm::ISD::NON_EXTLOAD
@ NON_EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:747
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:151
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
CSKYRegisterInfo.h
llvm::ISD::BSWAP
@ BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:700
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:183
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
convertValVTToLocVT
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:190
llvm::ISD::DYNAMIC_STACKALLOC
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
Definition: ISDOpcodes.h:969
llvm::TLSModel::GeneralDynamic
@ GeneralDynamic
Definition: CodeGen.h:43
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1679
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
Statistic.h
llvm::ISD::STACKRESTORE
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
Definition: ISDOpcodes.h:1050
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:9055
llvm::CSKYISD::NIR
@ NIR
Definition: CSKYISelLowering.h:28
llvm::MipsISD::Lo
@ Lo
Definition: MipsISelLowering.h:79
llvm::CSKYConstantPoolConstant::Create
static CSKYConstantPoolConstant * Create(const Constant *C, CSKYCP::CSKYCPKind Kind, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier, bool AddCurrentAddress, unsigned ID=0)
Definition: CSKYConstantPoolValue.cpp:86
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::CSKYMachineFunctionInfo::setVarArgsSaveSize
void setVarArgsSaveSize(int Size)
Definition: CSKYMachineFunctionInfo.h:46
llvm::CSKYMachineFunctionInfo
Definition: CSKYMachineFunctionInfo.h:20
getModifier
static CSKYCP::CSKYCPModifier getModifier(unsigned Flags)
Definition: CSKYISelLowering.cpp:759
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::TargetLowering::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetLowering.cpp:45
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1909
llvm::ISD::SETULE
@ SETULE
Definition: ISDOpcodes.h:1419
MachineJumpTableInfo.h
llvm::CSKYISD::CALL
@ CALL
Definition: CSKYISelLowering.h:30
llvm::CSKYRegisterInfo
Definition: CSKYRegisterInfo.h:24
llvm::ISD::SHL_PARTS
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition: ISDOpcodes.h:749
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
Definition: SelectionDAG.cpp:7756
llvm::CSKYCP::GOT
@ GOT
Definition: CSKYConstantPoolValue.h:39
llvm::SPII::Load
@ Load
Definition: SparcInstrInfo.h:32
llvm::CCValAssign::BCvt
@ BCvt
Definition: CallingConvLower.h:44
llvm::TargetLoweringBase::setMinFunctionAlignment
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
Definition: TargetLowering.h:2432
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9686
llvm::CSKYMachineFunctionInfo::setVarArgsFrameIndex
void setVarArgsFrameIndex(int v)
Definition: CSKYMachineFunctionInfo.h:42
llvm::codeview::EncodedFramePtrReg::StackPtr
@ StackPtr
llvm::ISD::VAEND
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
Definition: ISDOpcodes.h:1079
llvm::ISD::EXTLOAD
@ EXTLOAD
Definition: ISDOpcodes.h:1384
llvm::BlockAddressSDNode
Definition: SelectionDAGNodes.h:2165
llvm::CSKYISD::RET
@ RET
Definition: CSKYISelLowering.h:29
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:239
llvm::ISD::SETUEQ
@ SETUEQ
Definition: ISDOpcodes.h:1415
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:459
llvm::ISD::ADDCARRY
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:2061
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MipsISD::Hi
@ Hi
Definition: MipsISelLowering.h:75
llvm::CSKYTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: CSKYISelLowering.cpp:182
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::ISD::LoadExtType
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1384
llvm::ISD::BR_CC
@ BR_CC
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:1001
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
Definition: SelectionDAG.cpp:7706
R2
#define R2(n)
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::ISD::GlobalAddress
@ GlobalAddress
Definition: ISDOpcodes.h:78
llvm::CSKYII::MO_GOT32
@ MO_GOT32
Definition: CSKYBaseInfo.h:43
llvm::ISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:728
llvm::ExternalSymbolSDNode
Definition: SelectionDAGNodes.h:2207
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:702
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::CSKYSubtarget::hasFPUv2SingleFloat
bool hasFPUv2SingleFloat() const
Definition: CSKYSubtarget.h:139
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
Definition: TargetLowering.h:2288
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:742
llvm::ISD::ABS
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:674
CSKYSubtarget.h
llvm::CSKYCP::NO_MOD
@ NO_MOD
Definition: CSKYConstantPoolValue.h:39
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:148
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:56
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1449
llvm::JumpTableSDNode
Definition: SelectionDAGNodes.h:1837
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3394
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
unpackFromMemLoc
static SDValue unpackFromMemLoc(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:252
llvm::CSKYMachineFunctionInfo::getVarArgsFrameIndex
int getVarArgsFrameIndex()
Definition: CSKYMachineFunctionInfo.h:43
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:321
llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
Definition: TargetLowering.h:233
llvm::ISD::UDIVREM
@ UDIVREM
Definition: ISDOpcodes.h:256
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
Definition: TargetLowering.h:2271
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::SPII::Store
@ Store
Definition: SparcInstrInfo.h:33
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::TargetLowering::C_Register
@ C_Register
Definition: TargetLowering.h:4395
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:153
llvm::ISD::FSINCOS
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:953
llvm::CSKYSubtarget::getRegisterInfo
const CSKYRegisterInfo * getRegisterInfo() const override
Definition: CSKYSubtarget.h:119
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:149
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
Definition: TargetLowering.h:2219
llvm::EVT::changeVectorElementTypeToInteger
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
Definition: ValueTypes.h:93
llvm::CSKYSubtarget
Definition: CSKYSubtarget.h:30
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:143
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ISD::SETUGT
@ SETUGT
Definition: ISDOpcodes.h:1416
GPRArgRegs
static const MCPhysReg GPRArgRegs[]
Definition: CSKYISelLowering.cpp:34
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:695
llvm::CSKYISD::LOAD_ADDR
@ LOAD_ADDR
Definition: CSKYISelLowering.h:34
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::ISD::FPOW
@ FPOW
Definition: ISDOpcodes.h:911
llvm::CSKYConstantPoolSymbol::Create
static CSKYConstantPoolSymbol * Create(Type *Ty, const char *S, unsigned PCAdjust, CSKYCP::CSKYCPModifier Modifier)
Definition: CSKYConstantPoolValue.cpp:132
llvm::ISD::BlockAddress
@ BlockAddress
Definition: ISDOpcodes.h:84
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::SPIRV::Decoration::Alignment
@ Alignment
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::pdb::PDB_ColorItem::Address
@ Address
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::CSKYII::MO_GOTOFF
@ MO_GOTOFF
Definition: CSKYBaseInfo.h:44
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
llvm::CSKYTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: CSKYISelLowering.cpp:158
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ISD::ATOMIC_FENCE
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:1148
llvm::TLSModel::LocalDynamic
@ LocalDynamic
Definition: CodeGen.h:44
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:577
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:6447
llvm::CSKYII::MO_None
@ MO_None
Definition: CSKYBaseInfo.h:41
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1572
llvm::TargetLoweringBase::Promote
@ Promote
Definition: TargetLowering.h:197
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:773
llvm::CSKYConstantPoolValue
CSKYConstantPoolValue - CSKY specific constantpool value.
Definition: CSKYConstantPoolValue.h:45
llvm::CSKYCP::GOTOFF
@ GOTOFF
Definition: CSKYConstantPoolValue.h:39
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
Definition: TargetLowering.h:2237
llvm::CSKYSubtarget::useHardFloat
bool useHardFloat() const
Definition: CSKYSubtarget.h:138
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8790
llvm::CSKYCP::ADDR
@ ADDR
Definition: CSKYConstantPoolValue.h:39
llvm::CSKYMachineFunctionInfo::createPICLabelUId
unsigned createPICLabelUId()
Definition: CSKYMachineFunctionInfo.h:54
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
llvm::ISD::FCOPYSIGN
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:492
llvm::TargetMachine::getTLSModel
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
Definition: TargetMachine.cpp:158
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:631
llvm::ISD::ZEXTLOAD
@ ZEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:171
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3984
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::ISD::MULHS
@ MULHS
Definition: ISDOpcodes.h:638
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1418
llvm::CSKYCP::CPValue
@ CPValue
Definition: CSKYConstantPoolValue.h:32
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1404
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
Definition: SelectionDAG.cpp:9493
llvm::ISD::RETURNADDR
@ RETURNADDR
Definition: ISDOpcodes.h:95
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::ISD::SUBCARRY
@ SUBCARRY
Definition: ISDOpcodes.h:304
llvm::CSKYISD::BITCAST_FROM_LOHI
@ BITCAST_FROM_LOHI
Definition: CSKYISelLowering.h:38
R6
#define R6(n)
llvm::ISD::SRA_PARTS
@ SRA_PARTS
Definition: ISDOpcodes.h:750
unpack64
static SDValue unpack64(SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:279
llvm::ISD::VASTART
@ VASTART
Definition: ISDOpcodes.h:1080
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
Definition: SelectionDAG.h:952
llvm::CSKYSubtarget::useHardFloatABI
bool useHardFloatABI() const
Definition: CSKYSubtarget.cpp:96
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:679
llvm::ISD::GlobalTLSAddress
@ GlobalTLSAddress
Definition: ISDOpcodes.h:79
llvm::CSKYCP::TLSLE
@ TLSLE
Definition: CSKYConstantPoolValue.h:39
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Definition: SelectionDAG.h:711
unpackFromRegLoc
static SDValue unpackFromRegLoc(const CSKYSubtarget &Subtarget, SelectionDAG &DAG, SDValue Chain, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:220
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:99
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:154
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:972
llvm::CSKYCP::CSKYCPModifier
CSKYCPModifier
Definition: CSKYConstantPoolValue.h:39
llvm::CSKYRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: CSKYRegisterInfo.cpp:40
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::ISD::UMUL_LOHI
@ UMUL_LOHI
Definition: ISDOpcodes.h:251
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
uint32_t
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::CSKYISD::TAILReg
@ TAILReg
Definition: CSKYISelLowering.h:33
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::ISD::SMUL_LOHI
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition: ISDOpcodes.h:250
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
Definition: TargetLowering.cpp:5049
llvm::TargetMachine::shouldAssumeDSOLocal
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
Definition: TargetMachine.cpp:92
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
Definition: TargetLowering.h:2325
CSKYISelLowering.h
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:78
llvm::StringSwitch::Cases
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:90
llvm::ISD::SEXTLOAD
@ SEXTLOAD
Definition: ISDOpcodes.h:1384
llvm::TargetLowering::C_RegisterClass
@ C_RegisterClass
Definition: TargetLowering.h:4396
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:312
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.h:705
llvm::ISD::FRAMEADDR
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition: ISDOpcodes.h:94
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:186
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::StringRef::size
constexpr LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:157
j
return j(j<< 16)
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:144
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:169
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::Type::getIntNTy
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:243
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
CallingConvLower.h
llvm::CSKYISD::CALLReg
@ CALLReg
Definition: CSKYISelLowering.h:31
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:341
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::ISD::FCOS
@ FCOS
Definition: ISDOpcodes.h:909
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
Definition: SelectionDAG.h:528
llvm::ISD::FSIN
@ FSIN
Definition: ISDOpcodes.h:908
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:452
llvm::CSKYSubtarget::hasFPUv3SingleFloat
bool hasFPUv3SingleFloat() const
Definition: CSKYSubtarget.h:144
llvm::TargetLoweringBase::Custom
@ Custom
Definition: TargetLowering.h:200
llvm::CSKYSubtarget::hasFPUv2DoubleFloat
bool hasFPUv2DoubleFloat() const
Definition: CSKYSubtarget.h:140
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
Definition: SelectionDAG.cpp:1829
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::CSKYSubtarget::hasFPUv3DoubleFloat
bool hasFPUv3DoubleFloat() const
Definition: CSKYSubtarget.h:145
convertLocVTToValVT
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
Definition: CSKYISelLowering.cpp:206
CSKYMachineFunctionInfo.h
llvm::TLSModel::Model
Model
Definition: CodeGen.h:42
llvm::CSKYISD::TAIL
@ TAIL
Definition: CSKYISelLowering.h:32
llvm::ISD::VACOPY
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
Definition: ISDOpcodes.h:1075
llvm::ISD::SRL_PARTS
@ SRL_PARTS
Definition: ISDOpcodes.h:751
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::TLSModel::InitialExec
@ InitialExec
Definition: CodeGen.h:45
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
Definition: TargetLowering.h:2205
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
llvm::ISD::ArgFlagsTy::getNonZeroByValAlign
Align getNonZeroByValAlign() const
Definition: TargetCallingConv.h:153
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::TargetLoweringBase::Expand
@ Expand
Definition: TargetLowering.h:198
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:141
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::TargetLoweringBase::computeRegisterProperties
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
Definition: TargetLoweringBase.cpp:1248
llvm::ISD::BITREVERSE
@ BITREVERSE
Definition: ISDOpcodes.h:704
llvm::TargetLoweringBase::setMaxAtomicSizeInBitsSupported
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Definition: TargetLowering.h:2459
llvm::CSKYII::MO_ADDR32
@ MO_ADDR32
Definition: CSKYBaseInfo.h:42
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:2076
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::TargetLoweringBase::setCondCodeAction
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
Definition: TargetLowering.h:2386
llvm::ISD::CTTZ
@ CTTZ
Definition: ISDOpcodes.h:701
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:891
llvm::CSKYTargetLowering::CSKYTargetLowering
CSKYTargetLowering(const TargetMachine &TM, const CSKYSubtarget &STI)
Definition: CSKYISelLowering.cpp:36
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:287
llvm::CSKYCP::TLSIE
@ TLSIE
Definition: CSKYConstantPoolValue.h:39
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::ISD::MULHU
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition: ISDOpcodes.h:637
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
Definition: MachineBasicBlock.cpp:886
llvm::CSKYSubtarget::hasE2
bool hasE2() const
Definition: CSKYSubtarget.h:187
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:649
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
Definition: TargetLowering.h:2303
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ISD::SETONE
@ SETONE
Definition: ISDOpcodes.h:1412
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:449
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::ISD::VAARG
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
Definition: ISDOpcodes.h:1070
llvm::ISD::SDIVREM
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:255
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1812
llvm::CSKYISD::NIE
@ NIE
Definition: CSKYISelLowering.h:27
llvm::CSKYII::MO_PLT32
@ MO_PLT32
Definition: CSKYBaseInfo.h:45
llvm::CSKYISD::BITCAST_TO_LOHI
@ BITCAST_TO_LOHI
Definition: CSKYISelLowering.h:36
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::CSKYSubtarget::has2E3
bool has2E3() const
Definition: CSKYSubtarget.h:188
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:371
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7078
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::ISD::STACKSAVE
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:1046
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7723
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::ISD::ROTR
@ ROTR
Definition: ISDOpcodes.h:695
Debug.h
emitSelectPseudo
static MachineBasicBlock * emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode)
Definition: CSKYISelLowering.cpp:956
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:4910
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:354
llvm::ISD::CTPOP
@ CTPOP
Definition: ISDOpcodes.h:703
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::TLSModel::LocalExec
@ LocalExec
Definition: CodeGen.h:46
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:1168
llvm::TargetLoweringBase::UndefinedBooleanContent
@ UndefinedBooleanContent
Definition: TargetLowering.h:231