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27 #include "llvm/IR/IntrinsicsAMDGPU.h"
28 #include "llvm/IR/IntrinsicsR600.h"
35 #define DEBUG_TYPE "amdgpu-subtarget"
37 #define GET_SUBTARGETINFO_TARGET_DESC
38 #define GET_SUBTARGETINFO_CTOR
39 #define AMDGPUSubtarget GCNSubtarget
40 #include "AMDGPUGenSubtargetInfo.inc"
41 #define GET_SUBTARGETINFO_TARGET_DESC
42 #define GET_SUBTARGETINFO_CTOR
43 #undef AMDGPUSubtarget
44 #include "R600GenSubtargetInfo.inc"
47 "amdgpu-disable-power-sched",
48 cl::desc(
"Disable scheduling to minimize mAI power bursts"),
52 "amdgpu-vgpr-index-mode",
53 cl::desc(
"Use GPR indexing mode instead of movrel for vector indexing"),
57 "amdgpu-enable-flat-scratch",
58 cl::desc(
"Use flat scratch instructions"),
62 cl::desc(
"Enable the use of AA during codegen."),
96 FullFS +=
"+flat-for-global,+unaligned-access-mode,+trap-handler,";
98 FullFS +=
"+enable-prt-strict-null,";
103 FullFS +=
"-wavefrontsize16,";
105 FullFS +=
"-wavefrontsize32,";
107 FullFS +=
"-wavefrontsize64,";
135 ToggleFeature(AMDGPU::FeatureFlatForGlobal);
141 ToggleFeature(AMDGPU::FeatureFlatForGlobal);
180 Has16BitInsts(
false),
181 HasMadMixInsts(
false),
182 HasMadMacF32Insts(
false),
183 HasDsSrc2Insts(
false),
185 HasVOP3PInsts(
false),
188 HasInv2PiInlineImm(
false),
189 HasFminFmaxLegacy(
true),
190 EnablePromoteAlloca(
false),
191 HasTrigReducedRange(
false),
204 InstrItins(getInstrItineraryForCPU(GPU)),
206 MaxPrivateElementSize(0),
209 FastDenormalF32(
false),
210 HalfRate64Ops(
false),
211 FullRate64Ops(
false),
213 FlatForGlobal(
false),
214 AutoWaitcntBeforeBarrier(
false),
215 UnalignedScratchAccess(
false),
216 UnalignedAccessMode(
false),
218 HasApertureRegs(
false),
219 SupportsXNACK(
false),
221 EnableTgSplit(
false),
226 EnableUnsafeDSOffsetFolding(
false),
227 EnableSIScheduler(
false),
229 EnablePRTStrictNull(
false),
239 GFX7GFX8GFX9Insts(
false),
241 HasSMemRealTime(
false),
243 HasFmaMixInsts(
false),
245 HasVGPRIndexMode(
false),
246 HasScalarStores(
false),
247 HasScalarAtomics(
false),
249 HasSDWAScalar(
false),
252 HasSDWAOutModsVOPC(
false),
256 HasPackedFP32Ops(
false),
257 HasExtendedImageInsts(
false),
261 HasNSAEncoding(
false),
262 GFX10_BEncoding(
false),
272 HasPkFmacF16Inst(
false),
273 HasAtomicFaddInsts(
false),
274 SupportsSRAMECC(
false),
275 EnableSRAMECC(
false),
276 HasNoSdstCMPX(
false),
278 HasGetWaveIdInst(
false),
279 HasSMemTimeInst(
false),
280 HasShaderCyclesRegister(
false),
281 HasRegisterBanking(
false),
282 HasVOP3Literal(
false),
283 HasNoDataDepHazard(
false),
284 FlatAddressSpace(
false),
285 FlatInstOffsets(
false),
286 FlatGlobalInsts(
false),
287 FlatScratchInsts(
false),
288 ScalarFlatScratchInsts(
false),
289 AddNoCarryInsts(
false),
290 HasUnpackedD16VMem(
false),
291 LDSMisalignedBug(
false),
292 HasMFMAInlineLiteralBug(
false),
293 UnalignedBufferAccess(
false),
294 UnalignedDSAccess(
false),
299 HasVcmpxPermlaneHazard(
false),
300 HasVMEMtoScalarWriteHazard(
false),
301 HasSMEMtoVectorWriteHazard(
false),
302 HasInstFwdPrefetchBug(
false),
303 HasVcmpxExecWARHazard(
false),
304 HasLdsBranchVmemWARHazard(
false),
305 HasNSAtoVMEMBug(
false),
306 HasOffset3fBug(
false),
307 HasFlatSegmentOffsetBug(
false),
308 HasImageStoreD16Bug(
false),
309 HasImageGather4D16Bug(
false),
311 FeatureDisable(
false),
312 InstrInfo(initializeSubtargetDependencies(TT, GPU,
FS)),
333 case AMDGPU::V_LSHLREV_B64_e64:
334 case AMDGPU::V_LSHLREV_B64_gfx10:
335 case AMDGPU::V_LSHL_B64_e64:
336 case AMDGPU::V_LSHRREV_B64_e64:
337 case AMDGPU::V_LSHRREV_B64_gfx10:
338 case AMDGPU::V_LSHR_B64_e64:
339 case AMDGPU::V_ASHRREV_I64_e64:
340 case AMDGPU::V_ASHRREV_I64_gfx10:
341 case AMDGPU::V_ASHR_I64_e64:
354 if (!WorkGroupsPerCu)
365 if (!MaxWorkGroupsPerCu)
380 NumGroups =
std::min(MaxWorkGroupsPerCu, NumGroups);
383 const unsigned MaxGroupNumWaves = (MaxWorkGroupSize + WaveSize - 1) / WaveSize;
384 unsigned MaxWaves = NumGroups * MaxGroupNumWaves;
393 "computed invalid occupancy");
403 std::pair<unsigned, unsigned>
421 std::pair<unsigned, unsigned> Default =
426 F,
"amdgpu-flat-work-group-size", Default);
429 if (Requested.first > Requested.second)
453 unsigned MinImpliedByFlatWorkGroupSize =
455 Default.first = MinImpliedByFlatWorkGroupSize;
456 bool RequestedFlatWorkGroupSize =
457 F.hasFnAttribute(
"amdgpu-flat-work-group-size");
461 F,
"amdgpu-waves-per-eu", Default,
true);
464 if (Requested.second && Requested.first > Requested.second)
474 if (RequestedFlatWorkGroupSize &&
475 Requested.first < MinImpliedByFlatWorkGroupSize)
483 if (Node && Node->getNumOperands() == 3)
484 return mdconst::extract<ConstantInt>(Node->getOperand(Dim))->getZExtValue();
493 unsigned Dimension)
const {
502 unsigned MinSize = 0;
504 bool IdQuery =
false;
507 if (
auto *CI = dyn_cast<CallInst>(
I)) {
508 const Function *
F = CI->getCalledFunction();
510 unsigned Dim = UINT_MAX;
511 switch (
F->getIntrinsicID()) {
512 case Intrinsic::amdgcn_workitem_id_x:
513 case Intrinsic::r600_read_tidig_x:
516 case Intrinsic::r600_read_local_size_x:
519 case Intrinsic::amdgcn_workitem_id_y:
520 case Intrinsic::r600_read_tidig_y:
523 case Intrinsic::r600_read_local_size_y:
526 case Intrinsic::amdgcn_workitem_id_z:
527 case Intrinsic::r600_read_tidig_z:
530 case Intrinsic::r600_read_local_size_z:
540 MinSize = MaxSize = ReqdSize;
558 I->setMetadata(LLVMContext::MD_range, MaxWorkGroupSizeRange);
569 Align &MaxAlign)
const {
574 uint64_t ExplicitArgBytes = 0;
578 const bool IsByRef =
Arg.hasByRefAttr();
579 Type *ArgTy = IsByRef ?
Arg.getParamByRefType() :
Arg.getType();
582 Alignment =
DL.getABITypeAlign(ArgTy);
584 uint64_t AllocSize =
DL.getTypeAllocSize(ArgTy);
585 ExplicitArgBytes =
alignTo(ExplicitArgBytes, Alignment) + AllocSize;
586 MaxAlign =
max(MaxAlign, Alignment);
589 return ExplicitArgBytes;
593 Align &MaxAlign)
const {
598 uint64_t TotalSize = ExplicitOffset + ExplicitArgBytes;
600 if (ImplicitBytes != 0) {
602 TotalSize =
alignTo(ExplicitArgBytes, Alignment) + ImplicitBytes;
623 HasVertexCache(
false),
628 TLInfo(
TM, initializeSubtargetDependencies(TT, GPU,
FS)),
629 InstrItins(getInstrItineraryForCPU(GPU)) { }
632 unsigned NumRegionInstrs)
const {
689 unsigned RoundedRegs = ((VGPRs + Granule - 1) / Granule) * Granule;
729 std::pair<unsigned, unsigned> WavesPerEU = MFI.
getWavesPerEU();
731 unsigned MaxAddressableNumSGPRs =
getMaxNumSGPRs(WavesPerEU.first,
true);
735 if (
F.hasFnAttribute(
"amdgpu-num-sgpr")) {
737 F,
"amdgpu-num-sgpr", MaxNumSGPRs);
751 if (Requested && Requested < InputNumSGPRs)
752 Requested = InputNumSGPRs;
756 if (Requested && Requested >
getMaxNumSGPRs(WavesPerEU.first,
false))
758 if (WavesPerEU.second &&
763 MaxNumSGPRs = Requested;
770 MaxAddressableNumSGPRs);
779 std::pair<unsigned, unsigned> WavesPerEU = MFI.
getWavesPerEU();
784 if (
F.hasFnAttribute(
"amdgpu-num-vgpr")) {
786 F,
"amdgpu-num-vgpr", MaxNumVGPRs);
795 if (WavesPerEU.second &&
800 MaxNumVGPRs = Requested;
807 int UseOpIdx,
SDep &Dep)
const {
809 !
Def->isInstr() || !
Use->isInstr())
821 for (++
I;
I !=
E &&
I->isBundledWithPred(); ++
I) {
822 if (
I->modifiesRegister(
Reg,
TRI))
834 for (++
I;
I !=
E &&
I->isBundledWithPred() && Lat; ++
I) {
835 if (
I->readsRegister(
Reg,
TRI))
851 bool isSALU(
const SUnit *SU)
const {
853 return MI &&
TII->isSALU(*
MI) && !
MI->isTerminator();
856 bool isVALU(
const SUnit *SU)
const {
861 bool canAddEdge(
const SUnit *Succ,
const SUnit *Pred)
const {
867 for (
unsigned I = 0;
I < Succs.size(); ++
I) {
868 for (
const SDep &
SI : Succs[
I]->Succs) {
869 const SUnit *SU =
SI.getSUnit();
876 while (!Preds.empty()) {
877 const SUnit *SU = Preds.pop_back_val();
882 if (
SI.getSUnit() != SU && !Visited.
count(
SI.getSUnit()))
883 Preds.push_back(
SI.getSUnit());
896 while (!Worklist.empty() && MaxChain-- > 0) {
897 SUnit *SU = Worklist.pop_back_val();
898 if (!Visited.
insert(SU).second)
909 if (SUv !=
From && isVALU(SUv) && canAddEdge(SUv, SU))
915 if (Succ != SU && isSALU(Succ) && canAddEdge(
From, Succ))
916 Worklist.push_back(Succ);
929 if (!TSchedModel || DAG->
SUnits.empty())
936 auto LastSALU = DAG->
SUnits.begin();
941 if (!
TII->isMAI(MAI) ||
942 MAI.
getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
943 MAI.
getOpcode() == AMDGPU::V_ACCVGPR_READ_B32_e64)
946 unsigned Lat = TSchedModel->computeInstrLatency(&MAI) - 1;
949 dbgs() <<
"Need " << Lat
950 <<
" instructions to cover latency.\n");
954 for ( ; Lat && LastSALU !=
E; ++LastSALU) {
955 if (Visited.
count(&*LastSALU))
958 if (!isSALU(&*LastSALU) || !canAddEdge(&*LastSALU, &SU))
961 Lat -= linkSALUChain(&SU, &*LastSALU, Lat, Visited);
969 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
const {
970 Mutations.push_back(std::make_unique<FillMFMAShadowMutation>(&InstrInfo));
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Align getAlignmentForImplicitArgPtr() const
This class represents an incoming formal argument to a Function.
@ AMDGPU_HS
Calling convention used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
A parsed version of the target data layout string in and methods for querying it.
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Information about stack frame layout on the target.
bool hasVGPRIndexMode() const
@ Artificial
Arbitrary strong DAG edge (no real dependence).
R600Subtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
GCNSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
static constexpr size_t npos
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
virtual unsigned getMinWavesPerEU() const =0
bool hasFlatScratchInsts() const
MDNode * getMetadata(unsigned KindID) const
Get the current metadata attachments for the given kind, if any.
Triple - Helper class for working with autoconf configuration names.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
The instances of the Type class are immutable: once they are created, they are never changed.
static cl::opt< bool > EnableVGPRIndexMode("amdgpu-vgpr-index-mode", cl::desc("Use GPR indexing mode instead of movrel for vector indexing"), cl::init(false))
unsigned getMaxWavesPerEU() const
SmallVector< SDep, 4 > Succs
All sunit successors.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
AMDGPU::IsaInfo::AMDGPUTargetID TargetID
virtual unsigned getMaxFlatWorkGroupSize() const =0
unsigned const TargetRegisterInfo * TRI
unsigned getNumPreloadedSGPRs() const
unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const
const SIRegisterInfo * getRegisterInfo() const override
This class provides the information for the target register banks.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
bool hasCaymanISA() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
void apply(Opt *O, const Mod &M, const Mods &... Ms)
static const AMDGPUSubtarget & get(const MachineFunction &MF)
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
bool isShader(CallingConv::ID cc)
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
bool useVGPRIndexMode() const
static cl::opt< bool > ScalarizeGlobal("amdgpu-scalarize-global-loads", cl::desc("Enable global load scalarization"), cl::init(true), cl::Hidden)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned getReqdWorkGroupSize(const Function &Kernel, unsigned Dim)
const SITargetLowering * getTargetLowering() const override
unsigned NodeNum
Entry # of node in the node vector.
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
unsigned getImplicitArgNumBytes(const Function &F) const
virtual unsigned getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const =0
static cl::opt< bool > EnableFlatScratch("amdgpu-enable-flat-scratch", cl::desc("Use flat scratch instructions"), cl::init(false))
const HexagonInstrInfo * TII
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
bool isMesaKernel(const Function &F) const
bool hasSGPRInitBug() const
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
TargetIDSetting getSramEccSetting() const
unsigned getMaxWorkitemID(const Function &Kernel, unsigned Dimension) const
Return the maximum workitem ID value in the function, for the given (0, 1, 2) dimension.
This struct is a compact representation of a valid (non-zero power of two) alignment.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
unsigned getLocalMemorySize() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AMDGPUSubtarget(const Triple &TT)
unsigned getWavefrontSize() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
@ AMDGPU_GS
Calling convention used for Mesa/AMDPAL geometry shaders.
bool makeLIDRangeMetadata(Instruction *I) const
Creates value range metadata on an workitemid.* intrinsic call or load.
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
std::pair< unsigned, unsigned > getWavesPerEU(const Function &F) const
Provide an instruction scheduling machine model to CodeGen passes.
Representation of each machine instruction.
Function * Kernel
Summary of a kernel (=entry point for target offloading).
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
unsigned getTotalNumVGPRs() const
GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM)
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
unsigned getReg() const
Returns the register associated with this edge.
initializer< Ty > init(const Ty &Val)
Generation getGeneration() const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount, const Function &) const
Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount.
TargetIDSetting getXnackSetting() const
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool hasGFX90AInsts() const
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
static cl::opt< bool > UseAA("amdgpu-use-aa-in-codegen", cl::desc("Enable the use of AA during codegen."), cl::init(true))
unsigned MaxPrivateElementSize
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
unsigned getExplicitKernelArgOffset(const Function &F) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument.
instr_iterator instr_end()
Class for arbitrary precision integers.
virtual unsigned getMinFlatWorkGroupSize() const =0
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
StringRef - Represent a constant reference to a string, i.e.
Analysis the ScalarEvolution expression for r is this
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const
MachineFunction & MF
Machine function.
if(llvm_vc STREQUAL "") set(fake_version_inc "$
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const MachineBasicBlock * getParent() const
virtual unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const =0
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
bool enableFlatScratch() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
@ AMDGPU_LS
Calling convention used for AMDPAL vertex shader if tessellation is in use.
unsigned getReservedNumSGPRs(const MachineFunction &MF) const
unsigned getVGPRAllocGranule() const
uint64_t getExplicitKernArgSize(const Function &F, Align &MaxAlign) const
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
std::vector< SUnit > SUnits
The scheduling units.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Iterator for intrusive lists based on ilist_node.
void setLatency(unsigned Lat)
Sets the latency for this edge.
bool useAA() const override
std::pair< unsigned, unsigned > getWavesPerEU() const
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Generation getGeneration() const
bool isXNACKEnabled() const
static cl::opt< bool > DisablePowerSched("amdgpu-disable-power-sched", cl::desc("Disable scheduling to minimize mAI power bursts"), cl::init(false))
void dumpNode(const SUnit &SU) const override
unsigned getConstantBusLimit(unsigned Opcode) const
MDNode * createRange(const APInt &Lo, const APInt &Hi)
Return metadata describing the range [Lo, Hi).
std::pair< unsigned, unsigned > getDefaultFlatWorkGroupSize(CallingConv::ID CC) const
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
const Triple & getTargetTriple() const
bool ShouldTrackLaneMasks
Track LaneMasks to allow reordering of independent subregister writes of the same vreg.
Align max(MaybeAlign Lhs, Align Rhs)
bool enableSIScheduler() const
const InstrItineraryData * getInstrItineraryData() const override
const TargetSchedModel * getSchedModel() const
Gets the machine model for instruction scheduling.
Mutate the DAG as a postpass after normal DAG building.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
@ AMDGPU_ES
Calling convention used for AMDPAL shader stage before geometry shader if geometry is in use.
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
void setTargetIDFromFeaturesString(StringRef FS)
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Scheduling unit. This is a node in the scheduling DAG.
BlockVerifier::State From
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
std::pair< unsigned, unsigned > getFlatWorkGroupSizes(const Function &F) const
A ScheduleDAG for scheduling lists of MachineInstr.
@ AMDGPU_VS
Calling convention used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (ve...
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
unsigned computeOccupancy(const Function &F, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const
Return occupancy for the given function.
bool hasFlatScratchInit() const
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
A Use represents the edge between a Value definition and its users.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.