LLVM  14.0.0git
FastISel.cpp
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1 //===- FastISel.cpp - Implementation of the FastISel class ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of the FastISel class.
10 //
11 // "Fast" instruction selection is designed to emit very poor code quickly.
12 // Also, it is not designed to be able to do much lowering, so most illegal
13 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
14 // also not intended to be able to do much optimization, except in a few cases
15 // where doing optimizations reduces overall compile time. For example, folding
16 // constants into immediate fields is often done, because it's cheap and it
17 // reduces the number of instructions later phases have to examine.
18 //
19 // "Fast" instruction selection is able to fail gracefully and transfer
20 // control to the SelectionDAG selector for operations that it doesn't
21 // support. In many cases, this allows us to avoid duplicating a lot of
22 // the complicated lowering logic that SelectionDAG currently has.
23 //
24 // The intended use for "fast" instruction selection is "-O0" mode
25 // compilation, where the quality of the generated code is irrelevant when
26 // weighed against the speed at which the code can be generated. Also,
27 // at -O0, the LLVM optimizers are not running, and this makes the
28 // compile time of codegen a much higher portion of the overall compile
29 // time. Despite its limitations, "fast" instruction selection is able to
30 // handle enough code on its own to provide noticeable overall speedups
31 // in -O0 compiles.
32 //
33 // Basic operations are supported in a target-independent way, by reading
34 // the same instruction descriptions that the SelectionDAG selector reads,
35 // and identifying simple arithmetic operations that can be directly selected
36 // from simple operators. More complicated operations currently require
37 // target-specific code.
38 //
39 //===----------------------------------------------------------------------===//
40 
41 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/ADT/APFloat.h"
43 #include "llvm/ADT/APSInt.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/Optional.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/SmallVector.h"
49 #include "llvm/ADT/Statistic.h"
52 #include "llvm/CodeGen/Analysis.h"
63 #include "llvm/CodeGen/StackMaps.h"
68 #include "llvm/IR/Argument.h"
69 #include "llvm/IR/Attributes.h"
70 #include "llvm/IR/BasicBlock.h"
71 #include "llvm/IR/CallingConv.h"
72 #include "llvm/IR/Constant.h"
73 #include "llvm/IR/Constants.h"
74 #include "llvm/IR/DataLayout.h"
75 #include "llvm/IR/DebugInfo.h"
76 #include "llvm/IR/DebugLoc.h"
77 #include "llvm/IR/DerivedTypes.h"
78 #include "llvm/IR/DiagnosticInfo.h"
79 #include "llvm/IR/Function.h"
81 #include "llvm/IR/GlobalValue.h"
82 #include "llvm/IR/InlineAsm.h"
83 #include "llvm/IR/InstrTypes.h"
84 #include "llvm/IR/Instruction.h"
85 #include "llvm/IR/Instructions.h"
86 #include "llvm/IR/IntrinsicInst.h"
87 #include "llvm/IR/LLVMContext.h"
88 #include "llvm/IR/Mangler.h"
89 #include "llvm/IR/Metadata.h"
90 #include "llvm/IR/Operator.h"
91 #include "llvm/IR/PatternMatch.h"
92 #include "llvm/IR/Type.h"
93 #include "llvm/IR/User.h"
94 #include "llvm/IR/Value.h"
95 #include "llvm/MC/MCContext.h"
96 #include "llvm/MC/MCInstrDesc.h"
97 #include "llvm/MC/MCRegisterInfo.h"
98 #include "llvm/Support/Casting.h"
99 #include "llvm/Support/Debug.h"
102 #include "llvm/Support/MathExtras.h"
106 #include <algorithm>
107 #include <cassert>
108 #include <cstdint>
109 #include <iterator>
110 #include <utility>
111 
112 using namespace llvm;
113 using namespace PatternMatch;
114 
115 #define DEBUG_TYPE "isel"
116 
117 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
118  "target-independent selector");
119 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
120  "target-specific selector");
121 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
122 
123 /// Set the current block to which generated machine instructions will be
124 /// appended.
126  assert(LocalValueMap.empty() &&
127  "local values should be cleared after finishing a BB");
128 
129  // Instructions are appended to FuncInfo.MBB. If the basic block already
130  // contains labels or copies, use the last instruction as the last local
131  // value.
132  EmitStartPt = nullptr;
133  if (!FuncInfo.MBB->empty())
134  EmitStartPt = &FuncInfo.MBB->back();
135  LastLocalValue = EmitStartPt;
136 }
137 
138 void FastISel::finishBasicBlock() { flushLocalValueMap(); }
139 
141  if (!FuncInfo.CanLowerReturn)
142  // Fallback to SDISel argument lowering code to deal with sret pointer
143  // parameter.
144  return false;
145 
146  if (!fastLowerArguments())
147  return false;
148 
149  // Enter arguments into ValueMap for uses in non-entry BBs.
150  for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
151  E = FuncInfo.Fn->arg_end();
152  I != E; ++I) {
153  DenseMap<const Value *, Register>::iterator VI = LocalValueMap.find(&*I);
154  assert(VI != LocalValueMap.end() && "Missed an argument?");
155  FuncInfo.ValueMap[&*I] = VI->second;
156  }
157  return true;
158 }
159 
160 /// Return the defined register if this instruction defines exactly one
161 /// virtual register and uses no other virtual registers. Otherwise return 0.
163  Register RegDef;
164  for (const MachineOperand &MO : MI.operands()) {
165  if (!MO.isReg())
166  continue;
167  if (MO.isDef()) {
168  if (RegDef)
169  return Register();
170  RegDef = MO.getReg();
171  } else if (MO.getReg().isVirtual()) {
172  // This is another use of a vreg. Don't delete it.
173  return Register();
174  }
175  }
176  return RegDef;
177 }
178 
179 static bool isRegUsedByPhiNodes(Register DefReg,
180  FunctionLoweringInfo &FuncInfo) {
181  for (auto &P : FuncInfo.PHINodesToUpdate)
182  if (P.second == DefReg)
183  return true;
184  return false;
185 }
186 
187 void FastISel::flushLocalValueMap() {
188  // If FastISel bails out, it could leave local value instructions behind
189  // that aren't used for anything. Detect and erase those.
190  if (LastLocalValue != EmitStartPt) {
191  // Save the first instruction after local values, for later.
192  MachineBasicBlock::iterator FirstNonValue(LastLocalValue);
193  ++FirstNonValue;
194 
196  EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
197  : FuncInfo.MBB->rend();
198  MachineBasicBlock::reverse_iterator RI(LastLocalValue);
199  for (; RI != RE;) {
200  MachineInstr &LocalMI = *RI;
201  // Increment before erasing what it points to.
202  ++RI;
203  Register DefReg = findLocalRegDef(LocalMI);
204  if (!DefReg)
205  continue;
206  if (FuncInfo.RegsWithFixups.count(DefReg))
207  continue;
208  bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
209  if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
210  if (EmitStartPt == &LocalMI)
211  EmitStartPt = EmitStartPt->getPrevNode();
212  LLVM_DEBUG(dbgs() << "removing dead local value materialization"
213  << LocalMI);
214  LocalMI.eraseFromParent();
215  }
216  }
217 
218  if (FirstNonValue != FuncInfo.MBB->end()) {
219  // See if there are any local value instructions left. If so, we want to
220  // make sure the first one has a debug location; if it doesn't, use the
221  // first non-value instruction's debug location.
222 
223  // If EmitStartPt is non-null, this block had copies at the top before
224  // FastISel started doing anything; it points to the last one, so the
225  // first local value instruction is the one after EmitStartPt.
226  // If EmitStartPt is null, the first local value instruction is at the
227  // top of the block.
228  MachineBasicBlock::iterator FirstLocalValue =
229  EmitStartPt ? ++MachineBasicBlock::iterator(EmitStartPt)
230  : FuncInfo.MBB->begin();
231  if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
232  FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
233  }
234  }
235 
236  LocalValueMap.clear();
237  LastLocalValue = EmitStartPt;
238  recomputeInsertPt();
239  SavedInsertPt = FuncInfo.InsertPt;
240 }
241 
243  EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
244  // Don't handle non-simple values in FastISel.
245  if (!RealVT.isSimple())
246  return Register();
247 
248  // Ignore illegal types. We must do this before looking up the value
249  // in ValueMap because Arguments are given virtual registers regardless
250  // of whether FastISel can handle them.
251  MVT VT = RealVT.getSimpleVT();
252  if (!TLI.isTypeLegal(VT)) {
253  // Handle integer promotions, though, because they're common and easy.
254  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
255  VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
256  else
257  return Register();
258  }
259 
260  // Look up the value to see if we already have a register for it.
261  Register Reg = lookUpRegForValue(V);
262  if (Reg)
263  return Reg;
264 
265  // In bottom-up mode, just create the virtual register which will be used
266  // to hold the value. It will be materialized later.
267  if (isa<Instruction>(V) &&
268  (!isa<AllocaInst>(V) ||
269  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
270  return FuncInfo.InitializeRegForValue(V);
271 
272  SavePoint SaveInsertPt = enterLocalValueArea();
273 
274  // Materialize the value in a register. Emit any instructions in the
275  // local value area.
276  Reg = materializeRegForValue(V, VT);
277 
278  leaveLocalValueArea(SaveInsertPt);
279 
280  return Reg;
281 }
282 
283 Register FastISel::materializeConstant(const Value *V, MVT VT) {
284  Register Reg;
285  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
286  if (CI->getValue().getActiveBits() <= 64)
287  Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
288  } else if (isa<AllocaInst>(V))
289  Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
290  else if (isa<ConstantPointerNull>(V))
291  // Translate this as an integer zero so that it can be
292  // local-CSE'd with actual integer zeros.
293  Reg =
294  getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getType())));
295  else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
296  if (CF->isNullValue())
297  Reg = fastMaterializeFloatZero(CF);
298  else
299  // Try to emit the constant directly.
300  Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
301 
302  if (!Reg) {
303  // Try to emit the constant by using an integer constant with a cast.
304  const APFloat &Flt = CF->getValueAPF();
305  EVT IntVT = TLI.getPointerTy(DL);
306  uint32_t IntBitWidth = IntVT.getSizeInBits();
307  APSInt SIntVal(IntBitWidth, /*isUnsigned=*/false);
308  bool isExact;
309  (void)Flt.convertToInteger(SIntVal, APFloat::rmTowardZero, &isExact);
310  if (isExact) {
311  Register IntegerReg =
312  getRegForValue(ConstantInt::get(V->getContext(), SIntVal));
313  if (IntegerReg)
314  Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
315  IntegerReg);
316  }
317  }
318  } else if (const auto *Op = dyn_cast<Operator>(V)) {
319  if (!selectOperator(Op, Op->getOpcode()))
320  if (!isa<Instruction>(Op) ||
321  !fastSelectInstruction(cast<Instruction>(Op)))
322  return 0;
323  Reg = lookUpRegForValue(Op);
324  } else if (isa<UndefValue>(V)) {
325  Reg = createResultReg(TLI.getRegClassFor(VT));
326  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
327  TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
328  }
329  return Reg;
330 }
331 
332 /// Helper for getRegForValue. This function is called when the value isn't
333 /// already available in a register and must be materialized with new
334 /// instructions.
335 Register FastISel::materializeRegForValue(const Value *V, MVT VT) {
336  Register Reg;
337  // Give the target-specific code a try first.
338  if (isa<Constant>(V))
339  Reg = fastMaterializeConstant(cast<Constant>(V));
340 
341  // If target-specific code couldn't or didn't want to handle the value, then
342  // give target-independent code a try.
343  if (!Reg)
344  Reg = materializeConstant(V, VT);
345 
346  // Don't cache constant materializations in the general ValueMap.
347  // To do so would require tracking what uses they dominate.
348  if (Reg) {
349  LocalValueMap[V] = Reg;
350  LastLocalValue = MRI.getVRegDef(Reg);
351  }
352  return Reg;
353 }
354 
356  // Look up the value to see if we already have a register for it. We
357  // cache values defined by Instructions across blocks, and other values
358  // only locally. This is because Instructions already have the SSA
359  // def-dominates-use requirement enforced.
360  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(V);
361  if (I != FuncInfo.ValueMap.end())
362  return I->second;
363  return LocalValueMap[V];
364 }
365 
366 void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
367  if (!isa<Instruction>(I)) {
368  LocalValueMap[I] = Reg;
369  return;
370  }
371 
372  Register &AssignedReg = FuncInfo.ValueMap[I];
373  if (!AssignedReg)
374  // Use the new register.
375  AssignedReg = Reg;
376  else if (Reg != AssignedReg) {
377  // Arrange for uses of AssignedReg to be replaced by uses of Reg.
378  for (unsigned i = 0; i < NumRegs; i++) {
379  FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
380  FuncInfo.RegsWithFixups.insert(Reg + i);
381  }
382 
383  AssignedReg = Reg;
384  }
385 }
386 
388  Register IdxN = getRegForValue(Idx);
389  if (!IdxN)
390  // Unhandled operand. Halt "fast" selection and bail.
391  return Register();
392 
393  // If the index is smaller or larger than intptr_t, truncate or extend it.
394  MVT PtrVT = TLI.getPointerTy(DL);
395  EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
396  if (IdxVT.bitsLT(PtrVT)) {
397  IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
398  } else if (IdxVT.bitsGT(PtrVT)) {
399  IdxN =
400  fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
401  }
402  return IdxN;
403 }
404 
406  if (getLastLocalValue()) {
407  FuncInfo.InsertPt = getLastLocalValue();
408  FuncInfo.MBB = FuncInfo.InsertPt->getParent();
409  ++FuncInfo.InsertPt;
410  } else
411  FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
412 
413  // Now skip past any EH_LABELs, which must remain at the beginning.
414  while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
415  FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
416  ++FuncInfo.InsertPt;
417 }
418 
421  assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
422  "Invalid iterator!");
423  while (I != E) {
424  if (SavedInsertPt == I)
425  SavedInsertPt = E;
426  if (EmitStartPt == I)
427  EmitStartPt = E.isValid() ? &*E : nullptr;
428  if (LastLocalValue == I)
429  LastLocalValue = E.isValid() ? &*E : nullptr;
430 
431  MachineInstr *Dead = &*I;
432  ++I;
433  Dead->eraseFromParent();
434  ++NumFastIselDead;
435  }
436  recomputeInsertPt();
437 }
438 
440  SavePoint OldInsertPt = FuncInfo.InsertPt;
441  recomputeInsertPt();
442  return OldInsertPt;
443 }
444 
446  if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
447  LastLocalValue = &*std::prev(FuncInfo.InsertPt);
448 
449  // Restore the previous insert position.
450  FuncInfo.InsertPt = OldInsertPt;
451 }
452 
453 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
454  EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
455  if (VT == MVT::Other || !VT.isSimple())
456  // Unhandled type. Halt "fast" selection and bail.
457  return false;
458 
459  // We only handle legal types. For example, on x86-32 the instruction
460  // selector contains all of the 64-bit instructions from x86-64,
461  // under the assumption that i64 won't be used if the target doesn't
462  // support it.
463  if (!TLI.isTypeLegal(VT)) {
464  // MVT::i1 is special. Allow AND, OR, or XOR because they
465  // don't require additional zeroing, which makes them easy.
466  if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
467  ISDOpcode == ISD::XOR))
468  VT = TLI.getTypeToTransformTo(I->getContext(), VT);
469  else
470  return false;
471  }
472 
473  // Check if the first operand is a constant, and handle it as "ri". At -O0,
474  // we don't have anything that canonicalizes operand order.
475  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
476  if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
477  Register Op1 = getRegForValue(I->getOperand(1));
478  if (!Op1)
479  return false;
480 
481  Register ResultReg =
482  fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(),
483  VT.getSimpleVT());
484  if (!ResultReg)
485  return false;
486 
487  // We successfully emitted code for the given LLVM Instruction.
488  updateValueMap(I, ResultReg);
489  return true;
490  }
491 
492  Register Op0 = getRegForValue(I->getOperand(0));
493  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
494  return false;
495 
496  // Check if the second operand is a constant and handle it appropriately.
497  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
498  uint64_t Imm = CI->getSExtValue();
499 
500  // Transform "sdiv exact X, 8" -> "sra X, 3".
501  if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
502  cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
503  Imm = Log2_64(Imm);
504  ISDOpcode = ISD::SRA;
505  }
506 
507  // Transform "urem x, pow2" -> "and x, pow2-1".
508  if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
509  isPowerOf2_64(Imm)) {
510  --Imm;
511  ISDOpcode = ISD::AND;
512  }
513 
514  Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
515  VT.getSimpleVT());
516  if (!ResultReg)
517  return false;
518 
519  // We successfully emitted code for the given LLVM Instruction.
520  updateValueMap(I, ResultReg);
521  return true;
522  }
523 
524  Register Op1 = getRegForValue(I->getOperand(1));
525  if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
526  return false;
527 
528  // Now we have both operands in registers. Emit the instruction.
529  Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
530  ISDOpcode, Op0, Op1);
531  if (!ResultReg)
532  // Target-specific code wasn't able to find a machine opcode for
533  // the given ISD opcode and type. Halt "fast" selection and bail.
534  return false;
535 
536  // We successfully emitted code for the given LLVM Instruction.
537  updateValueMap(I, ResultReg);
538  return true;
539 }
540 
542  Register N = getRegForValue(I->getOperand(0));
543  if (!N) // Unhandled operand. Halt "fast" selection and bail.
544  return false;
545 
546  // FIXME: The code below does not handle vector GEPs. Halt "fast" selection
547  // and bail.
548  if (isa<VectorType>(I->getType()))
549  return false;
550 
551  // Keep a running tab of the total offset to coalesce multiple N = N + Offset
552  // into a single N = N + TotalOffset.
553  uint64_t TotalOffs = 0;
554  // FIXME: What's a good SWAG number for MaxOffs?
555  uint64_t MaxOffs = 2048;
556  MVT VT = TLI.getPointerTy(DL);
558  GTI != E; ++GTI) {
559  const Value *Idx = GTI.getOperand();
560  if (StructType *StTy = GTI.getStructTypeOrNull()) {
561  uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
562  if (Field) {
563  // N = N + Offset
564  TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
565  if (TotalOffs >= MaxOffs) {
566  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
567  if (!N) // Unhandled operand. Halt "fast" selection and bail.
568  return false;
569  TotalOffs = 0;
570  }
571  }
572  } else {
573  Type *Ty = GTI.getIndexedType();
574 
575  // If this is a constant subscript, handle it quickly.
576  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
577  if (CI->isZero())
578  continue;
579  // N = N + Offset
580  uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
581  TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
582  if (TotalOffs >= MaxOffs) {
583  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
584  if (!N) // Unhandled operand. Halt "fast" selection and bail.
585  return false;
586  TotalOffs = 0;
587  }
588  continue;
589  }
590  if (TotalOffs) {
591  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
592  if (!N) // Unhandled operand. Halt "fast" selection and bail.
593  return false;
594  TotalOffs = 0;
595  }
596 
597  // N = N + Idx * ElementSize;
598  uint64_t ElementSize = DL.getTypeAllocSize(Ty);
599  Register IdxN = getRegForGEPIndex(Idx);
600  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
601  return false;
602 
603  if (ElementSize != 1) {
604  IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
605  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
606  return false;
607  }
608  N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
609  if (!N) // Unhandled operand. Halt "fast" selection and bail.
610  return false;
611  }
612  }
613  if (TotalOffs) {
614  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
615  if (!N) // Unhandled operand. Halt "fast" selection and bail.
616  return false;
617  }
618 
619  // We successfully emitted code for the given LLVM Instruction.
620  updateValueMap(I, N);
621  return true;
622 }
623 
624 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
625  const CallInst *CI, unsigned StartIdx) {
626  for (unsigned i = StartIdx, e = CI->arg_size(); i != e; ++i) {
627  Value *Val = CI->getArgOperand(i);
628  // Check for constants and encode them with a StackMaps::ConstantOp prefix.
629  if (const auto *C = dyn_cast<ConstantInt>(Val)) {
630  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
631  Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
632  } else if (isa<ConstantPointerNull>(Val)) {
633  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
634  Ops.push_back(MachineOperand::CreateImm(0));
635  } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
636  // Values coming from a stack location also require a special encoding,
637  // but that is added later on by the target specific frame index
638  // elimination implementation.
639  auto SI = FuncInfo.StaticAllocaMap.find(AI);
640  if (SI != FuncInfo.StaticAllocaMap.end())
641  Ops.push_back(MachineOperand::CreateFI(SI->second));
642  else
643  return false;
644  } else {
645  Register Reg = getRegForValue(Val);
646  if (!Reg)
647  return false;
648  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
649  }
650  }
651  return true;
652 }
653 
655  // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
656  // [live variables...])
657  assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
658  "Stackmap cannot return a value.");
659 
660  // The stackmap intrinsic only records the live variables (the arguments
661  // passed to it) and emits NOPS (if requested). Unlike the patchpoint
662  // intrinsic, this won't be lowered to a function call. This means we don't
663  // have to worry about calling conventions and target-specific lowering code.
664  // Instead we perform the call lowering right here.
665  //
666  // CALLSEQ_START(0, 0...)
667  // STACKMAP(id, nbytes, ...)
668  // CALLSEQ_END(0, 0)
669  //
671 
672  // Add the <id> and <numBytes> constants.
673  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
674  "Expected a constant integer.");
675  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
676  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
677 
678  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
679  "Expected a constant integer.");
680  const auto *NumBytes =
681  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
682  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
683 
684  // Push live variables for the stack map (skipping the first two arguments
685  // <id> and <numBytes>).
686  if (!addStackMapLiveVars(Ops, I, 2))
687  return false;
688 
689  // We are not adding any register mask info here, because the stackmap doesn't
690  // clobber anything.
691 
692  // Add scratch registers as implicit def and early clobber.
693  CallingConv::ID CC = I->getCallingConv();
694  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
695  for (unsigned i = 0; ScratchRegs[i]; ++i)
696  Ops.push_back(MachineOperand::CreateReg(
697  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
698  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
699 
700  // Issue CALLSEQ_START
701  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
702  auto Builder =
703  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
704  const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
705  for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
706  Builder.addImm(0);
707 
708  // Issue STACKMAP.
709  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
710  TII.get(TargetOpcode::STACKMAP));
711  for (auto const &MO : Ops)
712  MIB.add(MO);
713 
714  // Issue CALLSEQ_END
715  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
716  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
717  .addImm(0)
718  .addImm(0);
719 
720  // Inform the Frame Information that we have a stackmap in this function.
721  FuncInfo.MF->getFrameInfo().setHasStackMap();
722 
723  return true;
724 }
725 
726 /// Lower an argument list according to the target calling convention.
727 ///
728 /// This is a helper for lowering intrinsics that follow a target calling
729 /// convention or require stack pointer adjustment. Only a subset of the
730 /// intrinsic's operands need to participate in the calling convention.
731 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
732  unsigned NumArgs, const Value *Callee,
733  bool ForceRetVoidTy, CallLoweringInfo &CLI) {
734  ArgListTy Args;
735  Args.reserve(NumArgs);
736 
737  // Populate the argument list.
738  for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {
739  Value *V = CI->getOperand(ArgI);
740 
741  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
742 
743  ArgListEntry Entry;
744  Entry.Val = V;
745  Entry.Ty = V->getType();
746  Entry.setAttributes(CI, ArgI);
747  Args.push_back(Entry);
748  }
749 
750  Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
751  : CI->getType();
752  CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
753 
754  return lowerCallTo(CLI);
755 }
756 
758  const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
759  StringRef Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
760  SmallString<32> MangledName;
761  Mangler::getNameWithPrefix(MangledName, Target, DL);
762  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
763  return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
764 }
765 
767  // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
768  // i32 <numBytes>,
769  // i8* <target>,
770  // i32 <numArgs>,
771  // [Args...],
772  // [live variables...])
773  CallingConv::ID CC = I->getCallingConv();
774  bool IsAnyRegCC = CC == CallingConv::AnyReg;
775  bool HasDef = !I->getType()->isVoidTy();
776  Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
777 
778  // Get the real number of arguments participating in the call <numArgs>
779  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
780  "Expected a constant integer.");
781  const auto *NumArgsVal =
782  cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
783  unsigned NumArgs = NumArgsVal->getZExtValue();
784 
785  // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
786  // This includes all meta-operands up to but not including CC.
787  unsigned NumMetaOpers = PatchPointOpers::CCPos;
788  assert(I->arg_size() >= NumMetaOpers + NumArgs &&
789  "Not enough arguments provided to the patchpoint intrinsic");
790 
791  // For AnyRegCC the arguments are lowered later on manually.
792  unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
793  CallLoweringInfo CLI;
794  CLI.setIsPatchPoint();
795  if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
796  return false;
797 
798  assert(CLI.Call && "No call instruction specified.");
799 
801 
802  // Add an explicit result reg if we use the anyreg calling convention.
803  if (IsAnyRegCC && HasDef) {
804  assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
805  CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
806  CLI.NumResultRegs = 1;
807  Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
808  }
809 
810  // Add the <id> and <numBytes> constants.
811  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
812  "Expected a constant integer.");
813  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
814  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
815 
816  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
817  "Expected a constant integer.");
818  const auto *NumBytes =
819  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
820  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
821 
822  // Add the call target.
823  if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
824  uint64_t CalleeConstAddr =
825  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
826  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
827  } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
828  if (C->getOpcode() == Instruction::IntToPtr) {
829  uint64_t CalleeConstAddr =
830  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
831  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
832  } else
833  llvm_unreachable("Unsupported ConstantExpr.");
834  } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
835  Ops.push_back(MachineOperand::CreateGA(GV, 0));
836  } else if (isa<ConstantPointerNull>(Callee))
837  Ops.push_back(MachineOperand::CreateImm(0));
838  else
839  llvm_unreachable("Unsupported callee address.");
840 
841  // Adjust <numArgs> to account for any arguments that have been passed on
842  // the stack instead.
843  unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
844  Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
845 
846  // Add the calling convention
847  Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
848 
849  // Add the arguments we omitted previously. The register allocator should
850  // place these in any free register.
851  if (IsAnyRegCC) {
852  for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
853  Register Reg = getRegForValue(I->getArgOperand(i));
854  if (!Reg)
855  return false;
856  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
857  }
858  }
859 
860  // Push the arguments from the call instruction.
861  for (auto Reg : CLI.OutRegs)
862  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
863 
864  // Push live variables for the stack map.
865  if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
866  return false;
867 
868  // Push the register mask info.
869  Ops.push_back(MachineOperand::CreateRegMask(
870  TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
871 
872  // Add scratch registers as implicit def and early clobber.
873  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
874  for (unsigned i = 0; ScratchRegs[i]; ++i)
875  Ops.push_back(MachineOperand::CreateReg(
876  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
877  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
878 
879  // Add implicit defs (return values).
880  for (auto Reg : CLI.InRegs)
881  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
882  /*isImp=*/true));
883 
884  // Insert the patchpoint instruction before the call generated by the target.
885  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
886  TII.get(TargetOpcode::PATCHPOINT));
887 
888  for (auto &MO : Ops)
889  MIB.add(MO);
890 
891  MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
892 
893  // Delete the original call instruction.
894  CLI.Call->eraseFromParent();
895 
896  // Inform the Frame Information that we have a patchpoint in this function.
897  FuncInfo.MF->getFrameInfo().setHasPatchPoint();
898 
899  if (CLI.NumResultRegs)
900  updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
901  return true;
902 }
903 
905  const auto &Triple = TM.getTargetTriple();
907  return true; // don't do anything to this instruction.
909  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
910  /*isDef=*/false));
911  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
912  /*isDef=*/false));
913  MachineInstrBuilder MIB =
914  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
915  TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));
916  for (auto &MO : Ops)
917  MIB.add(MO);
918 
919  // Insert the Patchable Event Call instruction, that gets lowered properly.
920  return true;
921 }
922 
924  const auto &Triple = TM.getTargetTriple();
926  return true; // don't do anything to this instruction.
928  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
929  /*isDef=*/false));
930  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
931  /*isDef=*/false));
932  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(2)),
933  /*isDef=*/false));
934  MachineInstrBuilder MIB =
935  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
936  TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
937  for (auto &MO : Ops)
938  MIB.add(MO);
939 
940  // Insert the Patchable Typed Event Call instruction, that gets lowered properly.
941  return true;
942 }
943 
944 /// Returns an AttributeList representing the attributes applied to the return
945 /// value of the given call.
948  if (CLI.RetSExt)
949  Attrs.push_back(Attribute::SExt);
950  if (CLI.RetZExt)
951  Attrs.push_back(Attribute::ZExt);
952  if (CLI.IsInReg)
953  Attrs.push_back(Attribute::InReg);
954 
956  Attrs);
957 }
958 
959 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
960  unsigned NumArgs) {
961  MCContext &Ctx = MF->getContext();
962  SmallString<32> MangledName;
963  Mangler::getNameWithPrefix(MangledName, SymName, DL);
964  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
965  return lowerCallTo(CI, Sym, NumArgs);
966 }
967 
969  unsigned NumArgs) {
970  FunctionType *FTy = CI->getFunctionType();
971  Type *RetTy = CI->getType();
972 
973  ArgListTy Args;
974  Args.reserve(NumArgs);
975 
976  // Populate the argument list.
977  // Attributes for args start at offset 1, after the return attribute.
978  for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
979  Value *V = CI->getOperand(ArgI);
980 
981  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
982 
983  ArgListEntry Entry;
984  Entry.Val = V;
985  Entry.Ty = V->getType();
986  Entry.setAttributes(CI, ArgI);
987  Args.push_back(Entry);
988  }
989  TLI.markLibCallAttributes(MF, CI->getCallingConv(), Args);
990 
991  CallLoweringInfo CLI;
992  CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), *CI, NumArgs);
993 
994  return lowerCallTo(CLI);
995 }
996 
998  // Handle the incoming return values from the call.
999  CLI.clearIns();
1000  SmallVector<EVT, 4> RetTys;
1001  ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
1002 
1004  GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
1005 
1006  bool CanLowerReturn = TLI.CanLowerReturn(
1007  CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
1008 
1009  // FIXME: sret demotion isn't supported yet - bail out.
1010  if (!CanLowerReturn)
1011  return false;
1012 
1013  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
1014  EVT VT = RetTys[I];
1015  MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
1016  unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
1017  for (unsigned i = 0; i != NumRegs; ++i) {
1018  ISD::InputArg MyFlags;
1019  MyFlags.VT = RegisterVT;
1020  MyFlags.ArgVT = VT;
1021  MyFlags.Used = CLI.IsReturnValueUsed;
1022  if (CLI.RetSExt)
1023  MyFlags.Flags.setSExt();
1024  if (CLI.RetZExt)
1025  MyFlags.Flags.setZExt();
1026  if (CLI.IsInReg)
1027  MyFlags.Flags.setInReg();
1028  CLI.Ins.push_back(MyFlags);
1029  }
1030  }
1031 
1032  // Handle all of the outgoing arguments.
1033  CLI.clearOuts();
1034  for (auto &Arg : CLI.getArgs()) {
1035  Type *FinalType = Arg.Ty;
1036  if (Arg.IsByVal)
1037  FinalType = Arg.IndirectType;
1038  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1039  FinalType, CLI.CallConv, CLI.IsVarArg, DL);
1040 
1041  ISD::ArgFlagsTy Flags;
1042  if (Arg.IsZExt)
1043  Flags.setZExt();
1044  if (Arg.IsSExt)
1045  Flags.setSExt();
1046  if (Arg.IsInReg)
1047  Flags.setInReg();
1048  if (Arg.IsSRet)
1049  Flags.setSRet();
1050  if (Arg.IsSwiftSelf)
1051  Flags.setSwiftSelf();
1052  if (Arg.IsSwiftAsync)
1053  Flags.setSwiftAsync();
1054  if (Arg.IsSwiftError)
1055  Flags.setSwiftError();
1056  if (Arg.IsCFGuardTarget)
1057  Flags.setCFGuardTarget();
1058  if (Arg.IsByVal)
1059  Flags.setByVal();
1060  if (Arg.IsInAlloca) {
1061  Flags.setInAlloca();
1062  // Set the byval flag for CCAssignFn callbacks that don't know about
1063  // inalloca. This way we can know how many bytes we should've allocated
1064  // and how many bytes a callee cleanup function will pop. If we port
1065  // inalloca to more targets, we'll have to add custom inalloca handling in
1066  // the various CC lowering callbacks.
1067  Flags.setByVal();
1068  }
1069  if (Arg.IsPreallocated) {
1070  Flags.setPreallocated();
1071  // Set the byval flag for CCAssignFn callbacks that don't know about
1072  // preallocated. This way we can know how many bytes we should've
1073  // allocated and how many bytes a callee cleanup function will pop. If we
1074  // port preallocated to more targets, we'll have to add custom
1075  // preallocated handling in the various CC lowering callbacks.
1076  Flags.setByVal();
1077  }
1078  MaybeAlign MemAlign = Arg.Alignment;
1079  if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {
1080  unsigned FrameSize = DL.getTypeAllocSize(Arg.IndirectType);
1081 
1082  // For ByVal, alignment should come from FE. BE will guess if this info
1083  // is not there, but there are cases it cannot get right.
1084  if (!MemAlign)
1085  MemAlign = Align(TLI.getByValTypeAlignment(Arg.IndirectType, DL));
1086  Flags.setByValSize(FrameSize);
1087  } else if (!MemAlign) {
1088  MemAlign = DL.getABITypeAlign(Arg.Ty);
1089  }
1090  Flags.setMemAlign(*MemAlign);
1091  if (Arg.IsNest)
1092  Flags.setNest();
1093  if (NeedsRegBlock)
1094  Flags.setInConsecutiveRegs();
1095  Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
1096  CLI.OutVals.push_back(Arg.Val);
1097  CLI.OutFlags.push_back(Flags);
1098  }
1099 
1100  if (!fastLowerCall(CLI))
1101  return false;
1102 
1103  // Set all unused physreg defs as dead.
1104  assert(CLI.Call && "No call instruction specified.");
1105  CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
1106 
1107  if (CLI.NumResultRegs && CLI.CB)
1108  updateValueMap(CLI.CB, CLI.ResultReg, CLI.NumResultRegs);
1109 
1110  // Set labels for heapallocsite call.
1111  if (CLI.CB)
1112  if (MDNode *MD = CLI.CB->getMetadata("heapallocsite"))
1113  CLI.Call->setHeapAllocMarker(*MF, MD);
1114 
1115  return true;
1116 }
1117 
1119  FunctionType *FuncTy = CI->getFunctionType();
1120  Type *RetTy = CI->getType();
1121 
1122  ArgListTy Args;
1123  ArgListEntry Entry;
1124  Args.reserve(CI->arg_size());
1125 
1126  for (auto i = CI->arg_begin(), e = CI->arg_end(); i != e; ++i) {
1127  Value *V = *i;
1128 
1129  // Skip empty types
1130  if (V->getType()->isEmptyTy())
1131  continue;
1132 
1133  Entry.Val = V;
1134  Entry.Ty = V->getType();
1135 
1136  // Skip the first return-type Attribute to get to params.
1137  Entry.setAttributes(CI, i - CI->arg_begin());
1138  Args.push_back(Entry);
1139  }
1140 
1141  // Check if target-independent constraints permit a tail call here.
1142  // Target-dependent constraints are checked within fastLowerCall.
1143  bool IsTailCall = CI->isTailCall();
1144  if (IsTailCall && !isInTailCallPosition(*CI, TM))
1145  IsTailCall = false;
1146  if (IsTailCall && MF->getFunction()
1147  .getFnAttribute("disable-tail-calls")
1148  .getValueAsBool())
1149  IsTailCall = false;
1150 
1151  CallLoweringInfo CLI;
1152  CLI.setCallee(RetTy, FuncTy, CI->getCalledOperand(), std::move(Args), *CI)
1153  .setTailCall(IsTailCall);
1154 
1155  diagnoseDontCall(*CI);
1156 
1157  return lowerCallTo(CLI);
1158 }
1159 
1161  const CallInst *Call = cast<CallInst>(I);
1162 
1163  // Handle simple inline asms.
1164  if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledOperand())) {
1165  // Don't attempt to handle constraints.
1166  if (!IA->getConstraintString().empty())
1167  return false;
1168 
1169  unsigned ExtraInfo = 0;
1170  if (IA->hasSideEffects())
1171  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1172  if (IA->isAlignStack())
1173  ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1174  if (Call->isConvergent())
1175  ExtraInfo |= InlineAsm::Extra_IsConvergent;
1176  ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
1177 
1178  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1180  MIB.addExternalSymbol(IA->getAsmString().c_str());
1181  MIB.addImm(ExtraInfo);
1182 
1183  const MDNode *SrcLoc = Call->getMetadata("srcloc");
1184  if (SrcLoc)
1185  MIB.addMetadata(SrcLoc);
1186 
1187  return true;
1188  }
1189 
1190  // Handle intrinsic function calls.
1191  if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1192  return selectIntrinsicCall(II);
1193 
1194  return lowerCall(Call);
1195 }
1196 
1198  switch (II->getIntrinsicID()) {
1199  default:
1200  break;
1201  // At -O0 we don't care about the lifetime intrinsics.
1202  case Intrinsic::lifetime_start:
1203  case Intrinsic::lifetime_end:
1204  // The donothing intrinsic does, well, nothing.
1205  case Intrinsic::donothing:
1206  // Neither does the sideeffect intrinsic.
1207  case Intrinsic::sideeffect:
1208  // Neither does the assume intrinsic; it's also OK not to codegen its operand.
1209  case Intrinsic::assume:
1210  // Neither does the llvm.experimental.noalias.scope.decl intrinsic
1211  case Intrinsic::experimental_noalias_scope_decl:
1212  return true;
1213  case Intrinsic::dbg_declare: {
1214  const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1215  assert(DI->getVariable() && "Missing variable");
1216  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1217  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1218  << " (!hasDebugInfo)\n");
1219  return true;
1220  }
1221 
1222  const Value *Address = DI->getAddress();
1223  if (!Address || isa<UndefValue>(Address)) {
1224  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1225  << " (bad/undef address)\n");
1226  return true;
1227  }
1228 
1229  // Byval arguments with frame indices were already handled after argument
1230  // lowering and before isel.
1231  const auto *Arg =
1232  dyn_cast<Argument>(Address->stripInBoundsConstantOffsets());
1233  if (Arg && FuncInfo.getArgumentFrameIndex(Arg) != INT_MAX)
1234  return true;
1235 
1237  if (Register Reg = lookUpRegForValue(Address))
1238  Op = MachineOperand::CreateReg(Reg, false);
1239 
1240  // If we have a VLA that has a "use" in a metadata node that's then used
1241  // here but it has no other uses, then we have a problem. E.g.,
1242  //
1243  // int foo (const int *x) {
1244  // char a[*x];
1245  // return 0;
1246  // }
1247  //
1248  // If we assign 'a' a vreg and fast isel later on has to use the selection
1249  // DAG isel, it will want to copy the value to the vreg. However, there are
1250  // no uses, which goes counter to what selection DAG isel expects.
1251  if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1252  (!isa<AllocaInst>(Address) ||
1253  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1254  Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1255  false);
1256 
1257  if (Op) {
1259  "Expected inlined-at fields to agree");
1260  // A dbg.declare describes the address of a source variable, so lower it
1261  // into an indirect DBG_VALUE.
1262  auto Builder =
1263  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1264  TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true, *Op,
1265  DI->getVariable(), DI->getExpression());
1266 
1267  // If using instruction referencing, mutate this into a DBG_INSTR_REF,
1268  // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
1269  // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
1270  if (FuncInfo.MF->useDebugInstrRef() && Op->isReg()) {
1271  Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
1272  Builder->getOperand(1).ChangeToImmediate(0);
1273  auto *NewExpr =
1275  Builder->getOperand(3).setMetadata(NewExpr);
1276  }
1277  } else {
1278  // We can't yet handle anything else here because it would require
1279  // generating code, thus altering codegen because of debug info.
1280  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1281  << " (no materialized reg for address)\n");
1282  }
1283  return true;
1284  }
1285  case Intrinsic::dbg_value: {
1286  // This form of DBG_VALUE is target-independent.
1287  const DbgValueInst *DI = cast<DbgValueInst>(II);
1288  const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1289  const Value *V = DI->getValue();
1291  "Expected inlined-at fields to agree");
1292  if (!V || isa<UndefValue>(V) || DI->hasArgList()) {
1293  // DI is either undef or cannot produce a valid DBG_VALUE, so produce an
1294  // undef DBG_VALUE to terminate any prior location.
1295  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, false, 0U,
1296  DI->getVariable(), DI->getExpression());
1297  } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1298  // See if there's an expression to constant-fold.
1299  DIExpression *Expr = DI->getExpression();
1300  if (Expr)
1301  std::tie(Expr, CI) = Expr->constantFold(CI);
1302  if (CI->getBitWidth() > 64)
1303  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1304  .addCImm(CI)
1305  .addImm(0U)
1306  .addMetadata(DI->getVariable())
1307  .addMetadata(Expr);
1308  else
1309  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1310  .addImm(CI->getZExtValue())
1311  .addImm(0U)
1312  .addMetadata(DI->getVariable())
1313  .addMetadata(Expr);
1314  } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1315  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1316  .addFPImm(CF)
1317  .addImm(0U)
1318  .addMetadata(DI->getVariable())
1319  .addMetadata(DI->getExpression());
1320  } else if (Register Reg = lookUpRegForValue(V)) {
1321  // FIXME: This does not handle register-indirect values at offset 0.
1322  bool IsIndirect = false;
1323  auto Builder =
1324  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1325  DI->getVariable(), DI->getExpression());
1326 
1327  // If using instruction referencing, mutate this into a DBG_INSTR_REF,
1328  // to be later patched up by finalizeDebugInstrRefs.
1329  if (FuncInfo.MF->useDebugInstrRef()) {
1330  Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
1331  Builder->getOperand(1).ChangeToImmediate(0);
1332  }
1333  } else {
1334  // We don't know how to handle other cases, so we drop.
1335  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1336  }
1337  return true;
1338  }
1339  case Intrinsic::dbg_label: {
1340  const DbgLabelInst *DI = cast<DbgLabelInst>(II);
1341  assert(DI->getLabel() && "Missing label");
1342  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1343  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1344  return true;
1345  }
1346 
1347  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1348  TII.get(TargetOpcode::DBG_LABEL)).addMetadata(DI->getLabel());
1349  return true;
1350  }
1351  case Intrinsic::objectsize:
1352  llvm_unreachable("llvm.objectsize.* should have been lowered already");
1353 
1354  case Intrinsic::is_constant:
1355  llvm_unreachable("llvm.is.constant.* should have been lowered already");
1356 
1357  case Intrinsic::launder_invariant_group:
1358  case Intrinsic::strip_invariant_group:
1359  case Intrinsic::expect: {
1360  Register ResultReg = getRegForValue(II->getArgOperand(0));
1361  if (!ResultReg)
1362  return false;
1363  updateValueMap(II, ResultReg);
1364  return true;
1365  }
1366  case Intrinsic::experimental_stackmap:
1367  return selectStackmap(II);
1368  case Intrinsic::experimental_patchpoint_void:
1369  case Intrinsic::experimental_patchpoint_i64:
1370  return selectPatchpoint(II);
1371 
1372  case Intrinsic::xray_customevent:
1373  return selectXRayCustomEvent(II);
1374  case Intrinsic::xray_typedevent:
1375  return selectXRayTypedEvent(II);
1376  }
1377 
1378  return fastLowerIntrinsicCall(II);
1379 }
1380 
1381 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1382  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1383  EVT DstVT = TLI.getValueType(DL, I->getType());
1384 
1385  if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1386  !DstVT.isSimple())
1387  // Unhandled type. Halt "fast" selection and bail.
1388  return false;
1389 
1390  // Check if the destination type is legal.
1391  if (!TLI.isTypeLegal(DstVT))
1392  return false;
1393 
1394  // Check if the source operand is legal.
1395  if (!TLI.isTypeLegal(SrcVT))
1396  return false;
1397 
1398  Register InputReg = getRegForValue(I->getOperand(0));
1399  if (!InputReg)
1400  // Unhandled operand. Halt "fast" selection and bail.
1401  return false;
1402 
1403  Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1404  Opcode, InputReg);
1405  if (!ResultReg)
1406  return false;
1407 
1408  updateValueMap(I, ResultReg);
1409  return true;
1410 }
1411 
1413  // If the bitcast doesn't change the type, just use the operand value.
1414  if (I->getType() == I->getOperand(0)->getType()) {
1415  Register Reg = getRegForValue(I->getOperand(0));
1416  if (!Reg)
1417  return false;
1418  updateValueMap(I, Reg);
1419  return true;
1420  }
1421 
1422  // Bitcasts of other values become reg-reg copies or BITCAST operators.
1423  EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1424  EVT DstEVT = TLI.getValueType(DL, I->getType());
1425  if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1426  !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1427  // Unhandled type. Halt "fast" selection and bail.
1428  return false;
1429 
1430  MVT SrcVT = SrcEVT.getSimpleVT();
1431  MVT DstVT = DstEVT.getSimpleVT();
1432  Register Op0 = getRegForValue(I->getOperand(0));
1433  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1434  return false;
1435 
1436  // First, try to perform the bitcast by inserting a reg-reg copy.
1437  Register ResultReg;
1438  if (SrcVT == DstVT) {
1439  const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1440  const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1441  // Don't attempt a cross-class copy. It will likely fail.
1442  if (SrcClass == DstClass) {
1443  ResultReg = createResultReg(DstClass);
1444  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1445  TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1446  }
1447  }
1448 
1449  // If the reg-reg copy failed, select a BITCAST opcode.
1450  if (!ResultReg)
1451  ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1452 
1453  if (!ResultReg)
1454  return false;
1455 
1456  updateValueMap(I, ResultReg);
1457  return true;
1458 }
1459 
1461  Register Reg = getRegForValue(I->getOperand(0));
1462  if (!Reg)
1463  // Unhandled operand.
1464  return false;
1465 
1466  EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());
1467  if (ETy == MVT::Other || !TLI.isTypeLegal(ETy))
1468  // Unhandled type, bail out.
1469  return false;
1470 
1471  MVT Ty = ETy.getSimpleVT();
1472  const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
1473  Register ResultReg = createResultReg(TyRegClass);
1474  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1475  TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
1476 
1477  updateValueMap(I, ResultReg);
1478  return true;
1479 }
1480 
1481 // Remove local value instructions starting from the instruction after
1482 // SavedLastLocalValue to the current function insert point.
1483 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
1484 {
1485  MachineInstr *CurLastLocalValue = getLastLocalValue();
1486  if (CurLastLocalValue != SavedLastLocalValue) {
1487  // Find the first local value instruction to be deleted.
1488  // This is the instruction after SavedLastLocalValue if it is non-NULL.
1489  // Otherwise it's the first instruction in the block.
1490  MachineBasicBlock::iterator FirstDeadInst(SavedLastLocalValue);
1491  if (SavedLastLocalValue)
1492  ++FirstDeadInst;
1493  else
1494  FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
1495  setLastLocalValue(SavedLastLocalValue);
1496  removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
1497  }
1498 }
1499 
1501  // Flush the local value map before starting each instruction.
1502  // This improves locality and debugging, and can reduce spills.
1503  // Reuse of values across IR instructions is relatively uncommon.
1504  flushLocalValueMap();
1505 
1506  MachineInstr *SavedLastLocalValue = getLastLocalValue();
1507  // Just before the terminator instruction, insert instructions to
1508  // feed PHI nodes in successor blocks.
1509  if (I->isTerminator()) {
1510  if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
1511  // PHI node handling may have generated local value instructions,
1512  // even though it failed to handle all PHI nodes.
1513  // We remove these instructions because SelectionDAGISel will generate
1514  // them again.
1515  removeDeadLocalValueCode(SavedLastLocalValue);
1516  return false;
1517  }
1518  }
1519 
1520  // FastISel does not handle any operand bundles except OB_funclet.
1521  if (auto *Call = dyn_cast<CallBase>(I))
1522  for (unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)
1523  if (Call->getOperandBundleAt(i).getTagID() != LLVMContext::OB_funclet)
1524  return false;
1525 
1526  DbgLoc = I->getDebugLoc();
1527 
1528  SavedInsertPt = FuncInfo.InsertPt;
1529 
1530  if (const auto *Call = dyn_cast<CallInst>(I)) {
1531  const Function *F = Call->getCalledFunction();
1532  LibFunc Func;
1533 
1534  // As a special case, don't handle calls to builtin library functions that
1535  // may be translated directly to target instructions.
1536  if (F && !F->hasLocalLinkage() && F->hasName() &&
1537  LibInfo->getLibFunc(F->getName(), Func) &&
1538  LibInfo->hasOptimizedCodeGen(Func))
1539  return false;
1540 
1541  // Don't handle Intrinsic::trap if a trap function is specified.
1542  if (F && F->getIntrinsicID() == Intrinsic::trap &&
1543  Call->hasFnAttr("trap-func-name"))
1544  return false;
1545  }
1546 
1547  // First, try doing target-independent selection.
1548  if (!SkipTargetIndependentISel) {
1549  if (selectOperator(I, I->getOpcode())) {
1550  ++NumFastIselSuccessIndependent;
1551  DbgLoc = DebugLoc();
1552  return true;
1553  }
1554  // Remove dead code.
1555  recomputeInsertPt();
1556  if (SavedInsertPt != FuncInfo.InsertPt)
1557  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1558  SavedInsertPt = FuncInfo.InsertPt;
1559  }
1560  // Next, try calling the target to attempt to handle the instruction.
1561  if (fastSelectInstruction(I)) {
1562  ++NumFastIselSuccessTarget;
1563  DbgLoc = DebugLoc();
1564  return true;
1565  }
1566  // Remove dead code.
1567  recomputeInsertPt();
1568  if (SavedInsertPt != FuncInfo.InsertPt)
1569  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1570 
1571  DbgLoc = DebugLoc();
1572  // Undo phi node updates, because they will be added again by SelectionDAG.
1573  if (I->isTerminator()) {
1574  // PHI node handling may have generated local value instructions.
1575  // We remove them because SelectionDAGISel will generate them again.
1576  removeDeadLocalValueCode(SavedLastLocalValue);
1577  FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1578  }
1579  return false;
1580 }
1581 
1582 /// Emit an unconditional branch to the given block, unless it is the immediate
1583 /// (fall-through) successor, and update the CFG.
1585  const DebugLoc &DbgLoc) {
1586  if (FuncInfo.MBB->getBasicBlock()->sizeWithoutDebug() > 1 &&
1587  FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1588  // For more accurate line information if this is the only non-debug
1589  // instruction in the block then emit it, otherwise we have the
1590  // unconditional fall-through case, which needs no instructions.
1591  } else {
1592  // The unconditional branch case.
1593  TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,
1594  SmallVector<MachineOperand, 0>(), DbgLoc);
1595  }
1596  if (FuncInfo.BPI) {
1597  auto BranchProbability = FuncInfo.BPI->getEdgeProbability(
1598  FuncInfo.MBB->getBasicBlock(), MSucc->getBasicBlock());
1599  FuncInfo.MBB->addSuccessor(MSucc, BranchProbability);
1600  } else
1601  FuncInfo.MBB->addSuccessorWithoutProb(MSucc);
1602 }
1603 
1605  MachineBasicBlock *TrueMBB,
1606  MachineBasicBlock *FalseMBB) {
1607  // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
1608  // happen in degenerate IR and MachineIR forbids to have a block twice in the
1609  // successor/predecessor lists.
1610  if (TrueMBB != FalseMBB) {
1611  if (FuncInfo.BPI) {
1612  auto BranchProbability =
1613  FuncInfo.BPI->getEdgeProbability(BranchBB, TrueMBB->getBasicBlock());
1614  FuncInfo.MBB->addSuccessor(TrueMBB, BranchProbability);
1615  } else
1616  FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);
1617  }
1618 
1619  fastEmitBranch(FalseMBB, DbgLoc);
1620 }
1621 
1622 /// Emit an FNeg operation.
1623 bool FastISel::selectFNeg(const User *I, const Value *In) {
1624  Register OpReg = getRegForValue(In);
1625  if (!OpReg)
1626  return false;
1627 
1628  // If the target has ISD::FNEG, use it.
1629  EVT VT = TLI.getValueType(DL, I->getType());
1630  Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1631  OpReg);
1632  if (ResultReg) {
1633  updateValueMap(I, ResultReg);
1634  return true;
1635  }
1636 
1637  // Bitcast the value to integer, twiddle the sign bit with xor,
1638  // and then bitcast it back to floating-point.
1639  if (VT.getSizeInBits() > 64)
1640  return false;
1641  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1642  if (!TLI.isTypeLegal(IntVT))
1643  return false;
1644 
1645  Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1646  ISD::BITCAST, OpReg);
1647  if (!IntReg)
1648  return false;
1649 
1650  Register IntResultReg = fastEmit_ri_(
1651  IntVT.getSimpleVT(), ISD::XOR, IntReg,
1652  UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1653  if (!IntResultReg)
1654  return false;
1655 
1656  ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1657  IntResultReg);
1658  if (!ResultReg)
1659  return false;
1660 
1661  updateValueMap(I, ResultReg);
1662  return true;
1663 }
1664 
1666  const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1667  if (!EVI)
1668  return false;
1669 
1670  // Make sure we only try to handle extracts with a legal result. But also
1671  // allow i1 because it's easy.
1672  EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1673  if (!RealVT.isSimple())
1674  return false;
1675  MVT VT = RealVT.getSimpleVT();
1676  if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1677  return false;
1678 
1679  const Value *Op0 = EVI->getOperand(0);
1680  Type *AggTy = Op0->getType();
1681 
1682  // Get the base result register.
1683  unsigned ResultReg;
1684  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1685  if (I != FuncInfo.ValueMap.end())
1686  ResultReg = I->second;
1687  else if (isa<Instruction>(Op0))
1688  ResultReg = FuncInfo.InitializeRegForValue(Op0);
1689  else
1690  return false; // fast-isel can't handle aggregate constants at the moment
1691 
1692  // Get the actual result register, which is an offset from the base register.
1693  unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1694 
1695  SmallVector<EVT, 4> AggValueVTs;
1696  ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1697 
1698  for (unsigned i = 0; i < VTIndex; i++)
1699  ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1700 
1701  updateValueMap(EVI, ResultReg);
1702  return true;
1703 }
1704 
1705 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1706  switch (Opcode) {
1707  case Instruction::Add:
1708  return selectBinaryOp(I, ISD::ADD);
1709  case Instruction::FAdd:
1710  return selectBinaryOp(I, ISD::FADD);
1711  case Instruction::Sub:
1712  return selectBinaryOp(I, ISD::SUB);
1713  case Instruction::FSub:
1714  return selectBinaryOp(I, ISD::FSUB);
1715  case Instruction::Mul:
1716  return selectBinaryOp(I, ISD::MUL);
1717  case Instruction::FMul:
1718  return selectBinaryOp(I, ISD::FMUL);
1719  case Instruction::SDiv:
1720  return selectBinaryOp(I, ISD::SDIV);
1721  case Instruction::UDiv:
1722  return selectBinaryOp(I, ISD::UDIV);
1723  case Instruction::FDiv:
1724  return selectBinaryOp(I, ISD::FDIV);
1725  case Instruction::SRem:
1726  return selectBinaryOp(I, ISD::SREM);
1727  case Instruction::URem:
1728  return selectBinaryOp(I, ISD::UREM);
1729  case Instruction::FRem:
1730  return selectBinaryOp(I, ISD::FREM);
1731  case Instruction::Shl:
1732  return selectBinaryOp(I, ISD::SHL);
1733  case Instruction::LShr:
1734  return selectBinaryOp(I, ISD::SRL);
1735  case Instruction::AShr:
1736  return selectBinaryOp(I, ISD::SRA);
1737  case Instruction::And:
1738  return selectBinaryOp(I, ISD::AND);
1739  case Instruction::Or:
1740  return selectBinaryOp(I, ISD::OR);
1741  case Instruction::Xor:
1742  return selectBinaryOp(I, ISD::XOR);
1743 
1744  case Instruction::FNeg:
1745  return selectFNeg(I, I->getOperand(0));
1746 
1747  case Instruction::GetElementPtr:
1748  return selectGetElementPtr(I);
1749 
1750  case Instruction::Br: {
1751  const BranchInst *BI = cast<BranchInst>(I);
1752 
1753  if (BI->isUnconditional()) {
1754  const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1755  MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1756  fastEmitBranch(MSucc, BI->getDebugLoc());
1757  return true;
1758  }
1759 
1760  // Conditional branches are not handed yet.
1761  // Halt "fast" selection and bail.
1762  return false;
1763  }
1764 
1765  case Instruction::Unreachable:
1766  if (TM.Options.TrapUnreachable)
1767  return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1768  else
1769  return true;
1770 
1771  case Instruction::Alloca:
1772  // FunctionLowering has the static-sized case covered.
1773  if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1774  return true;
1775 
1776  // Dynamic-sized alloca is not handled yet.
1777  return false;
1778 
1779  case Instruction::Call:
1780  // On AIX, call lowering uses the DAG-ISEL path currently so that the
1781  // callee of the direct function call instruction will be mapped to the
1782  // symbol for the function's entry point, which is distinct from the
1783  // function descriptor symbol. The latter is the symbol whose XCOFF symbol
1784  // name is the C-linkage name of the source level function.
1785  if (TM.getTargetTriple().isOSAIX())
1786  return false;
1787  return selectCall(I);
1788 
1789  case Instruction::BitCast:
1790  return selectBitCast(I);
1791 
1792  case Instruction::FPToSI:
1793  return selectCast(I, ISD::FP_TO_SINT);
1794  case Instruction::ZExt:
1795  return selectCast(I, ISD::ZERO_EXTEND);
1796  case Instruction::SExt:
1797  return selectCast(I, ISD::SIGN_EXTEND);
1798  case Instruction::Trunc:
1799  return selectCast(I, ISD::TRUNCATE);
1800  case Instruction::SIToFP:
1801  return selectCast(I, ISD::SINT_TO_FP);
1802 
1803  case Instruction::IntToPtr: // Deliberate fall-through.
1804  case Instruction::PtrToInt: {
1805  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1806  EVT DstVT = TLI.getValueType(DL, I->getType());
1807  if (DstVT.bitsGT(SrcVT))
1808  return selectCast(I, ISD::ZERO_EXTEND);
1809  if (DstVT.bitsLT(SrcVT))
1810  return selectCast(I, ISD::TRUNCATE);
1811  Register Reg = getRegForValue(I->getOperand(0));
1812  if (!Reg)
1813  return false;
1814  updateValueMap(I, Reg);
1815  return true;
1816  }
1817 
1818  case Instruction::ExtractValue:
1819  return selectExtractValue(I);
1820 
1821  case Instruction::Freeze:
1822  return selectFreeze(I);
1823 
1824  case Instruction::PHI:
1825  llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1826 
1827  default:
1828  // Unhandled instruction. Halt "fast" selection and bail.
1829  return false;
1830  }
1831 }
1832 
1834  const TargetLibraryInfo *LibInfo,
1835  bool SkipTargetIndependentISel)
1836  : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1837  MFI(FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1838  TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1839  TII(*MF->getSubtarget().getInstrInfo()),
1840  TLI(*MF->getSubtarget().getTargetLowering()),
1841  TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1842  SkipTargetIndependentISel(SkipTargetIndependentISel),
1843  LastLocalValue(nullptr), EmitStartPt(nullptr) {}
1844 
1845 FastISel::~FastISel() = default;
1846 
1847 bool FastISel::fastLowerArguments() { return false; }
1848 
1849 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1850 
1852  return false;
1853 }
1854 
1855 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1856 
1857 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1858  return 0;
1859 }
1860 
1861 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1862  unsigned /*Op1*/) {
1863  return 0;
1864 }
1865 
1866 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1867  return 0;
1868 }
1869 
1870 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1871  const ConstantFP * /*FPImm*/) {
1872  return 0;
1873 }
1874 
1875 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1876  uint64_t /*Imm*/) {
1877  return 0;
1878 }
1879 
1880 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1881 /// instruction with an immediate operand using fastEmit_ri.
1882 /// If that fails, it materializes the immediate into a register and try
1883 /// fastEmit_rr instead.
1884 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1885  uint64_t Imm, MVT ImmType) {
1886  // If this is a multiply by a power of two, emit this as a shift left.
1887  if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1888  Opcode = ISD::SHL;
1889  Imm = Log2_64(Imm);
1890  } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1891  // div x, 8 -> srl x, 3
1892  Opcode = ISD::SRL;
1893  Imm = Log2_64(Imm);
1894  }
1895 
1896  // Horrible hack (to be removed), check to make sure shift amounts are
1897  // in-range.
1898  if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1899  Imm >= VT.getSizeInBits())
1900  return 0;
1901 
1902  // First check if immediate type is legal. If not, we can't use the ri form.
1903  Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
1904  if (ResultReg)
1905  return ResultReg;
1906  Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1907  if (!MaterialReg) {
1908  // This is a bit ugly/slow, but failing here means falling out of
1909  // fast-isel, which would be very slow.
1910  IntegerType *ITy =
1912  MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1913  if (!MaterialReg)
1914  return 0;
1915  }
1916  return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
1917 }
1918 
1920  return MRI.createVirtualRegister(RC);
1921 }
1922 
1924  unsigned OpNum) {
1925  if (Op.isVirtual()) {
1926  const TargetRegisterClass *RegClass =
1927  TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1928  if (!MRI.constrainRegClass(Op, RegClass)) {
1929  // If it's not legal to COPY between the register classes, something
1930  // has gone very wrong before we got here.
1931  Register NewOp = createResultReg(RegClass);
1933  TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1934  return NewOp;
1935  }
1936  }
1937  return Op;
1938 }
1939 
1940 Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1941  const TargetRegisterClass *RC) {
1942  Register ResultReg = createResultReg(RC);
1943  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1944 
1945  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1946  return ResultReg;
1947 }
1948 
1949 Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1950  const TargetRegisterClass *RC, unsigned Op0) {
1951  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1952 
1953  Register ResultReg = createResultReg(RC);
1954  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1955 
1956  if (II.getNumDefs() >= 1)
1957  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1958  .addReg(Op0);
1959  else {
1961  .addReg(Op0);
1963  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1964  }
1965 
1966  return ResultReg;
1967 }
1968 
1969 Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1970  const TargetRegisterClass *RC, unsigned Op0,
1971  unsigned Op1) {
1972  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1973 
1974  Register ResultReg = createResultReg(RC);
1975  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1976  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1977 
1978  if (II.getNumDefs() >= 1)
1979  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1980  .addReg(Op0)
1981  .addReg(Op1);
1982  else {
1984  .addReg(Op0)
1985  .addReg(Op1);
1987  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1988  }
1989  return ResultReg;
1990 }
1991 
1992 Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1993  const TargetRegisterClass *RC, unsigned Op0,
1994  unsigned Op1, unsigned Op2) {
1995  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1996 
1997  Register ResultReg = createResultReg(RC);
1998  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1999  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2000  Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
2001 
2002  if (II.getNumDefs() >= 1)
2003  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2004  .addReg(Op0)
2005  .addReg(Op1)
2006  .addReg(Op2);
2007  else {
2009  .addReg(Op0)
2010  .addReg(Op1)
2011  .addReg(Op2);
2013  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2014  }
2015  return ResultReg;
2016 }
2017 
2018 Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2019  const TargetRegisterClass *RC, unsigned Op0,
2020  uint64_t Imm) {
2021  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2022 
2023  Register ResultReg = createResultReg(RC);
2024  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2025 
2026  if (II.getNumDefs() >= 1)
2027  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2028  .addReg(Op0)
2029  .addImm(Imm);
2030  else {
2032  .addReg(Op0)
2033  .addImm(Imm);
2035  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2036  }
2037  return ResultReg;
2038 }
2039 
2040 Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
2041  const TargetRegisterClass *RC, unsigned Op0,
2042  uint64_t Imm1, uint64_t Imm2) {
2043  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2044 
2045  Register ResultReg = createResultReg(RC);
2046  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2047 
2048  if (II.getNumDefs() >= 1)
2049  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2050  .addReg(Op0)
2051  .addImm(Imm1)
2052  .addImm(Imm2);
2053  else {
2055  .addReg(Op0)
2056  .addImm(Imm1)
2057  .addImm(Imm2);
2059  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2060  }
2061  return ResultReg;
2062 }
2063 
2064 Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
2065  const TargetRegisterClass *RC,
2066  const ConstantFP *FPImm) {
2067  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2068 
2069  Register ResultReg = createResultReg(RC);
2070 
2071  if (II.getNumDefs() >= 1)
2072  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2073  .addFPImm(FPImm);
2074  else {
2076  .addFPImm(FPImm);
2078  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2079  }
2080  return ResultReg;
2081 }
2082 
2083 Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
2084  const TargetRegisterClass *RC, unsigned Op0,
2085  unsigned Op1, uint64_t Imm) {
2086  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2087 
2088  Register ResultReg = createResultReg(RC);
2089  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2090  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2091 
2092  if (II.getNumDefs() >= 1)
2093  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2094  .addReg(Op0)
2095  .addReg(Op1)
2096  .addImm(Imm);
2097  else {
2099  .addReg(Op0)
2100  .addReg(Op1)
2101  .addImm(Imm);
2103  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2104  }
2105  return ResultReg;
2106 }
2107 
2108 Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
2109  const TargetRegisterClass *RC, uint64_t Imm) {
2110  Register ResultReg = createResultReg(RC);
2111  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2112 
2113  if (II.getNumDefs() >= 1)
2114  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2115  .addImm(Imm);
2116  else {
2119  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2120  }
2121  return ResultReg;
2122 }
2123 
2125  uint32_t Idx) {
2126  Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2128  "Cannot yet extract from physregs");
2129  const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2131  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
2132  ResultReg).addReg(Op0, 0, Idx);
2133  return ResultReg;
2134 }
2135 
2136 /// Emit MachineInstrs to compute the value of Op with all but the least
2137 /// significant bit set to zero.
2139  return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
2140 }
2141 
2142 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
2143 /// Emit code to ensure constants are copied into registers when needed.
2144 /// Remember the virtual registers that need to be added to the Machine PHI
2145 /// nodes as input. We cannot just directly add them, because expansion
2146 /// might result in multiple MBB's for one BB. As such, the start of the
2147 /// BB might correspond to a different MBB than the end.
2148 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
2149  const Instruction *TI = LLVMBB->getTerminator();
2150 
2153 
2154  // Check successor nodes' PHI nodes that expect a constant to be available
2155  // from this block.
2156  for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2157  const BasicBlock *SuccBB = TI->getSuccessor(succ);
2158  if (!isa<PHINode>(SuccBB->begin()))
2159  continue;
2160  MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2161 
2162  // If this terminator has multiple identical successors (common for
2163  // switches), only handle each succ once.
2164  if (!SuccsHandled.insert(SuccMBB).second)
2165  continue;
2166 
2167  MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2168 
2169  // At this point we know that there is a 1-1 correspondence between LLVM PHI
2170  // nodes and Machine PHI nodes, but the incoming operands have not been
2171  // emitted yet.
2172  for (const PHINode &PN : SuccBB->phis()) {
2173  // Ignore dead phi's.
2174  if (PN.use_empty())
2175  continue;
2176 
2177  // Only handle legal types. Two interesting things to note here. First,
2178  // by bailing out early, we may leave behind some dead instructions,
2179  // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2180  // own moves. Second, this check is necessary because FastISel doesn't
2181  // use CreateRegs to create registers, so it always creates
2182  // exactly one register for each non-void instruction.
2183  EVT VT = TLI.getValueType(DL, PN.getType(), /*AllowUnknown=*/true);
2184  if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2185  // Handle integer promotions, though, because they're common and easy.
2186  if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2188  return false;
2189  }
2190  }
2191 
2192  const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
2193 
2194  // Set the DebugLoc for the copy. Use the location of the operand if
2195  // there is one; otherwise no location, flushLocalValueMap will fix it.
2196  DbgLoc = DebugLoc();
2197  if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2198  DbgLoc = Inst->getDebugLoc();
2199 
2200  Register Reg = getRegForValue(PHIOp);
2201  if (!Reg) {
2203  return false;
2204  }
2205  FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
2206  DbgLoc = DebugLoc();
2207  }
2208  }
2209 
2210  return true;
2211 }
2212 
2213 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2214  assert(LI->hasOneUse() &&
2215  "tryToFoldLoad expected a LoadInst with a single use");
2216  // We know that the load has a single use, but don't know what it is. If it
2217  // isn't one of the folded instructions, then we can't succeed here. Handle
2218  // this by scanning the single-use users of the load until we get to FoldInst.
2219  unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2220 
2221  const Instruction *TheUser = LI->user_back();
2222  while (TheUser != FoldInst && // Scan up until we find FoldInst.
2223  // Stay in the right block.
2224  TheUser->getParent() == FoldInst->getParent() &&
2225  --MaxUsers) { // Don't scan too far.
2226  // If there are multiple or no uses of this instruction, then bail out.
2227  if (!TheUser->hasOneUse())
2228  return false;
2229 
2230  TheUser = TheUser->user_back();
2231  }
2232 
2233  // If we didn't find the fold instruction, then we failed to collapse the
2234  // sequence.
2235  if (TheUser != FoldInst)
2236  return false;
2237 
2238  // Don't try to fold volatile loads. Target has to deal with alignment
2239  // constraints.
2240  if (LI->isVolatile())
2241  return false;
2242 
2243  // Figure out which vreg this is going into. If there is no assigned vreg yet
2244  // then there actually was no reference to it. Perhaps the load is referenced
2245  // by a dead instruction.
2246  Register LoadReg = getRegForValue(LI);
2247  if (!LoadReg)
2248  return false;
2249 
2250  // We can't fold if this vreg has no uses or more than one use. Multiple uses
2251  // may mean that the instruction got lowered to multiple MIs, or the use of
2252  // the loaded value ended up being multiple operands of the result.
2253  if (!MRI.hasOneUse(LoadReg))
2254  return false;
2255 
2257  MachineInstr *User = RI->getParent();
2258 
2259  // Set the insertion point properly. Folding the load can cause generation of
2260  // other random instructions (like sign extends) for addressing modes; make
2261  // sure they get inserted in a logical place before the new instruction.
2263  FuncInfo.MBB = User->getParent();
2264 
2265  // Ask the target to try folding the load.
2266  return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2267 }
2268 
2269 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2270  // Must be an add.
2271  if (!isa<AddOperator>(Add))
2272  return false;
2273  // Type size needs to match.
2274  if (DL.getTypeSizeInBits(GEP->getType()) !=
2275  DL.getTypeSizeInBits(Add->getType()))
2276  return false;
2277  // Must be in the same basic block.
2278  if (isa<Instruction>(Add) &&
2279  FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2280  return false;
2281  // Must have a constant operand.
2282  return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2283 }
2284 
2287  const Value *Ptr;
2288  Type *ValTy;
2289  MaybeAlign Alignment;
2291  bool IsVolatile;
2292 
2293  if (const auto *LI = dyn_cast<LoadInst>(I)) {
2294  Alignment = LI->getAlign();
2295  IsVolatile = LI->isVolatile();
2296  Flags = MachineMemOperand::MOLoad;
2297  Ptr = LI->getPointerOperand();
2298  ValTy = LI->getType();
2299  } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2300  Alignment = SI->getAlign();
2301  IsVolatile = SI->isVolatile();
2303  Ptr = SI->getPointerOperand();
2304  ValTy = SI->getValueOperand()->getType();
2305  } else
2306  return nullptr;
2307 
2308  bool IsNonTemporal = I->hasMetadata(LLVMContext::MD_nontemporal);
2309  bool IsInvariant = I->hasMetadata(LLVMContext::MD_invariant_load);
2310  bool IsDereferenceable = I->hasMetadata(LLVMContext::MD_dereferenceable);
2311  const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2312 
2313  AAMDNodes AAInfo = I->getAAMetadata();
2314 
2315  if (!Alignment) // Ensure that codegen never sees alignment 0.
2316  Alignment = DL.getABITypeAlign(ValTy);
2317 
2318  unsigned Size = DL.getTypeStoreSize(ValTy);
2319 
2320  if (IsVolatile)
2322  if (IsNonTemporal)
2324  if (IsDereferenceable)
2326  if (IsInvariant)
2328 
2330  *Alignment, AAInfo, Ranges);
2331 }
2332 
2334  // If both operands are the same, then try to optimize or fold the cmp.
2336  if (CI->getOperand(0) != CI->getOperand(1))
2337  return Predicate;
2338 
2339  switch (Predicate) {
2340  default: llvm_unreachable("Invalid predicate!");
2357 
2368  }
2369 
2370  return Predicate;
2371 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1303
llvm::FunctionLoweringInfo::Fn
const Function * Fn
Definition: FunctionLoweringInfo.h:54
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:243
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:735
ValueTypes.h
llvm::DbgVariableIntrinsic::getExpression
DIExpression * getExpression() const
Definition: IntrinsicInst.h:257
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2047
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::FastISel::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: FastISel.h:84
llvm::DbgDeclareInst::getAddress
Value * getAddress() const
Definition: IntrinsicInst.h:310
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::FastISel::lowerCallTo
bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)
Definition: FastISel.cpp:968
llvm::FastISel::selectPatchpoint
bool selectPatchpoint(const CallInst *I)
Definition: FastISel.cpp:766
llvm::FastISel::CallLoweringInfo::OutFlags
SmallVector< ISD::ArgFlagsTy, 16 > OutFlags
Definition: FastISel.h:94
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:741
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
Optional.h
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:633
llvm::FastISel::getRegForValue
Register getRegForValue(const Value *V)
Create a virtual register and arrange for it to be assigned the value for the given LLVM value.
Definition: FastISel.cpp:242
llvm::ISD::ArgFlagsTy::setSwiftSelf
void setSwiftSelf()
Definition: TargetCallingConv.h:98
llvm::FastISel::~FastISel
virtual ~FastISel()
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::generic_gep_type_iterator
Definition: GetElementPtrTypeIterator.h:31
llvm::FastISel::fastEmit_f
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1870
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:848
Metadata.h
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ISD::ArgFlagsTy::setNest
void setNest()
Definition: TargetCallingConv.h:119
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
IntrinsicInst.h
llvm::FastISel::selectCast
bool selectCast(const User *I, unsigned Opcode)
Definition: FastISel.cpp:1381
MCInstrDesc.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:62
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:664
llvm::FastISel::updateValueMap
void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)
Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...
Definition: FastISel.cpp:366
llvm::FunctionLoweringInfo::InsertPt
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
Definition: FunctionLoweringInfo.h:152
llvm::ISD::ArgFlagsTy::setMemAlign
void setMemAlign(Align A)
Definition: TargetCallingConv.h:148
GetElementPtrTypeIterator.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FastISel::fastEmit_ri_
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, MVT ImmType)
This method is a wrapper of fastEmit_ri.
Definition: FastISel.cpp:1884
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::FastISel::fastEmitInst_f
Register fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm)
Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...
Definition: FastISel.cpp:2064
Statistic.h
InlineAsm.h
llvm::FastISel::CallLoweringInfo::setIsPatchPoint
CallLoweringInfo & setIsPatchPoint(bool Value=true)
Definition: FastISel.h:181
llvm::FastISel::FastISel
FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)
Definition: FastISel.cpp:1833
llvm::FastISel::CallLoweringInfo::ResultReg
Register ResultReg
Definition: FastISel.h:90
llvm::FastISel::CallLoweringInfo::InRegs
SmallVector< Register, 4 > InRegs
Definition: FastISel.h:97
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:431
llvm::FastISel::finishBasicBlock
void finishBasicBlock()
Flush the local value map.
Definition: FastISel.cpp:138
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:728
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:471
ErrorHandling.h
llvm::FastISel::lowerArguments
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
Definition: FastISel.cpp:140
llvm::FastISel::fastEmitZExtFromI1
Register fastEmitZExtFromI1(MVT VT, unsigned Op0)
Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.
Definition: FastISel.cpp:2138
llvm::ISD::InputArg::Used
bool Used
Definition: TargetCallingConv.h:199
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:988
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition: InstrTypes.h:742
llvm::FastISel::selectFreeze
bool selectFreeze(const User *I)
Definition: FastISel.cpp:1460
llvm::AttributeList::get
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute >> Attrs)
Create an AttributeList with the specified parameters in it.
Definition: Attributes.cpp:1011
llvm::FastISel::enterLocalValueArea
SavePoint enterLocalValueArea()
Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...
Definition: FastISel.cpp:439
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:785
NewExpr
Definition: ItaniumDemangle.h:1916
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:747
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::FastISel::CallLoweringInfo::OutVals
SmallVector< Value *, 16 > OutVals
Definition: FastISel.h:93
llvm::DenseMapIterator
Definition: DenseMap.h:56
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
DenseMap.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::FunctionLoweringInfo::MBB
MachineBasicBlock * MBB
MBB - The current block.
Definition: FunctionLoweringInfo.h:149
llvm::diagnoseDontCall
void diagnoseDontCall(const CallInst &CI)
Definition: DiagnosticInfo.cpp:403
llvm::AttributeList
Definition: Attributes.h:399
llvm::FastISel::fastEmitInst_rii
Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2)
Emit a MachineInstr with one register operand and two immediate operands.
Definition: FastISel.cpp:2040
TargetInstrInfo.h
llvm::FastISel::fastEmit_rr
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1861
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1241
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::FastISel::CallLoweringInfo::RetSExt
bool RetSExt
Definition: FastISel.h:71
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::ComputeLinearIndex
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
Definition: Analysis.cpp:36
llvm::DbgVariableIntrinsic::getVariable
DILocalVariable * getVariable() const
Definition: IntrinsicInst.h:253
llvm::Optional
Definition: APInt.h:33
llvm::FastISel::TLI
const TargetLowering & TLI
Definition: FastISel.h:211
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:596
Operator.h
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:750
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1303
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2586
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::PatchPointOpers::NArgPos
@ NArgPos
Definition: StackMaps.h:79
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:724
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:225
llvm::FastISel::getRegForGEPIndex
Register getRegForGEPIndex(const Value *Idx)
This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...
Definition: FastISel.cpp:387
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1084
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::FastISel::CallLoweringInfo::RetZExt
bool RetZExt
Definition: FastISel.h:72
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:980
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:146
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:130
MachineValueType.h
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:734
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFrameInfo::setHasStackMap
void setHasStackMap(bool s=true)
Definition: MachineFrameInfo.h:381
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
Instruction.h
llvm::MachineBasicBlock::reverse_iterator
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
Definition: MachineBasicBlock.h:235
llvm::ISD::InputArg::ArgVT
EVT ArgVT
Definition: TargetCallingConv.h:198
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::Instruction::getNumSuccessors
unsigned getNumSuccessors() const
Return the number of successors that this instruction has.
Definition: Instruction.cpp:765
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1335
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:191
llvm::APFloat::convertToInteger
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
Definition: APFloat.h:1105
llvm::Log2_64
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:602
GlobalValue.h
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:508
llvm::FastISel::FuncInfo
FunctionLoweringInfo & FuncInfo
Definition: FastISel.h:202
Constants.h
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::FunctionLoweringInfo::MBBMap
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
Definition: FunctionLoweringInfo.h:72
llvm::DbgValueInst
This represents the llvm.dbg.value instruction.
Definition: IntrinsicInst.h:347
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
SmallString.h
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::FastISel::createResultReg
Register createResultReg(const TargetRegisterClass *RC)
Definition: FastISel.cpp:1919
llvm::User
Definition: User.h:44
llvm::LibFunc
LibFunc
Definition: TargetLibraryInfo.h:34
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FastISel::CallLoweringInfo::clearIns
void clearIns()
Definition: FastISel.h:194
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:746
InstrTypes.h
llvm::BasicBlock::begin
iterator begin()
Instruction iterator methods.
Definition: BasicBlock.h:296
MCContext.h
llvm::FastISel::CallLoweringInfo::CB
const CallBase * CB
Definition: FastISel.h:88
llvm::FastISel::leaveLocalValueArea
void leaveLocalValueArea(SavePoint Old)
Reset InsertPt to the given old insert position.
Definition: FastISel.cpp:445
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:733
llvm::FastISel::selectXRayTypedEvent
bool selectXRayTypedEvent(const CallInst *II)
Definition: FastISel.cpp:923
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:224
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:735
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:658
TargetLibraryInfo.h
llvm::LLVMContext::OB_funclet
@ OB_funclet
Definition: LLVMContext.h:91
addStackMapLiveVars
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
Definition: SelectionDAGBuilder.cpp:9215
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::Mangler::getNameWithPrefix
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
Definition: Mangler.cpp:119
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::FastISel::fastEmit_
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)
This method is called by target-independent code to request that an instruction with the given type a...
Definition: FastISel.cpp:1855
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:730
llvm::Instruction
Definition: Instruction.h:45
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:826
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:739
llvm::APSInt
An arbitrary precision integer that knows its signedness.
Definition: APSInt.h:22
llvm::BasicBlock::phis
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
Definition: BasicBlock.h:354
llvm::FastISel::selectStackmap
bool selectStackmap(const CallInst *I)
Definition: FastISel.cpp:654
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
isCommutative
static bool isCommutative(Instruction *I)
Definition: SLPVectorizer.cpp:266
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:584
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::FastISel::fastEmit_ri
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1875
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:823
llvm::FastISel::CallLoweringInfo::IsInReg
bool IsInReg
Definition: FastISel.h:74
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:925
llvm::DILocalVariable::isValidLocationForIntrinsic
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Definition: DebugInfoMetadata.h:3174
llvm::FastISel::CallLoweringInfo::clearOuts
void clearOuts()
Definition: FastISel.h:188
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:723
DebugLoc.h
SmallPtrSet.h
llvm::Instruction::getSuccessor
BasicBlock * getSuccessor(unsigned Idx) const
Return the specified successor. This instruction must be a terminator.
Definition: Instruction.cpp:777
llvm::DbgVariableIntrinsic::hasArgList
bool hasArgList() const
Definition: IntrinsicInst.h:227
llvm::FastISel::MRI
MachineRegisterInfo & MRI
Definition: FastISel.h:204
llvm::FastISel::CallLoweringInfo::Call
MachineInstr * Call
Definition: FastISel.h:89
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:726
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:632
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
PatternMatch.h
llvm::CallInst::isTailCall
bool isTailCall() const
Definition: Instructions.h:1669
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:310
llvm::CallBase::getCallingConv
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1439
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:273
llvm::FastISel::createMachineMemOperandFor
MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const
Create a machine mem operand from the given instruction.
Definition: FastISel.cpp:2286
llvm::FunctionLoweringInfo::OrigNumPHINodesToUpdate
unsigned OrigNumPHINodesToUpdate
Definition: FunctionLoweringInfo.h:175
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:282
llvm::SmallString< 32 >
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:722
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:710
llvm::FastISel::fastLowerIntrinsicCall
virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)
This method is called by target-independent code to do target- specific intrinsic lowering.
Definition: FastISel.cpp:1851
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:377
llvm::InlineAsm
Definition: InlineAsm.h:31
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
BasicBlock.h
llvm::APFloat
Definition: APFloat.h:701
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:402
llvm::FastISel::CallLoweringInfo::NumResultRegs
unsigned NumResultRegs
Definition: FastISel.h:91
llvm::FastISel::selectInstruction
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
Definition: FastISel.cpp:1500
llvm::FastISel::DbgLoc
DebugLoc DbgLoc
Definition: FastISel.h:207
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
VI
@ VI
Definition: SIInstrInfo.cpp:7689
BranchProbabilityInfo.h
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::FastISel::tryToFoldLoadIntoMI
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Definition: FastISel.h:299
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:903
llvm::DbgDeclareInst
This represents the llvm.dbg.declare instruction.
Definition: IntrinsicInst.h:308
llvm::DbgLabelInst
This represents the llvm.dbg.label instruction.
Definition: IntrinsicInst.h:370
llvm::Instruction::user_back
Instruction * user_back()
Specialize the methods defined in Value, as we know that an instruction can only be used by other ins...
Definition: Instruction.h:91
llvm::FastISel::fastLowerCall
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
Definition: FastISel.cpp:1849
llvm::FastISel::fastEmit_i
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1866
llvm::FastISel::fastEmitBranch
void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)
Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...
Definition: FastISel.cpp:1584
llvm::DbgLabelInst::getLabel
DILabel * getLabel() const
Definition: IntrinsicInst.h:372
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1088
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::FastISel::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: FastISel.h:186
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::FastISel::selectIntrinsicCall
bool selectIntrinsicCall(const IntrinsicInst *II)
Definition: FastISel.cpp:1197
findLocalRegDef
static Register findLocalRegDef(MachineInstr &MI)
Return the defined register if this instruction defines exactly one virtual register and uses no othe...
Definition: FastISel.cpp:162
llvm::FastISel::fastEmitInst_rri
Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm)
Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...
Definition: FastISel.cpp:2083
DebugInfo.h
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:558
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
MCRegisterInfo.h
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(Align A)
Definition: TargetCallingConv.h:164
llvm::FastISel::CallLoweringInfo::IsReturnValueUsed
bool IsReturnValueUsed
Definition: FastISel.h:76
llvm::FastISel::CallLoweringInfo
Definition: FastISel.h:69
llvm::HighlightColor::Address
@ Address
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::FastISel::fastEmit_r
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1857
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2794
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:274
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:650
llvm::ISD::ArgFlagsTy::setInConsecutiveRegs
void setInConsecutiveRegs(bool Flag=true)
Definition: TargetCallingConv.h:125
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:725
llvm::ISD::ArgFlagsTy::setSwiftError
void setSwiftError()
Definition: TargetCallingConv.h:104
llvm::FastISel::fastEmitInst_
Register fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC)
Emit a MachineInstr with no operands and a result register in the given register class.
Definition: FastISel.cpp:1940
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition: InstrTypes.h:744
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:141
llvm::FastISel::fastLowerArguments
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
Definition: FastISel.cpp:1847
APSInt.h
llvm::FastISel::ArgListTy
TargetLoweringBase::ArgListTy ArgListTy
Definition: FastISel.h:68
MachineModuleInfo.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::ISD::ArgFlagsTy::setByVal
void setByVal()
Definition: TargetCallingConv.h:86
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1309
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::BranchInst::isUnconditional
bool isUnconditional() const
Definition: Instructions.h:3146
llvm::ISD::ArgFlagsTy::setByValSize
void setByValSize(unsigned S)
Definition: TargetCallingConv.h:173
Mangler.h
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:749
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::FastISel::selectOperator
bool selectOperator(const User *I, unsigned Opcode)
Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...
Definition: FastISel.cpp:1705
llvm::FastISel::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: FastISel.h:73
TargetOptions.h
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:850
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::ISD::ArgFlagsTy::setInAlloca
void setInAlloca()
Definition: TargetCallingConv.h:92
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition: InstrTypes.h:745
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::FastISel::canFoldAddIntoGEP
bool canFoldAddIntoGEP(const User *GEP, const Value *Add)
Check if Add is an add that can be safely folded into GEP.
Definition: FastISel.cpp:2269
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::Value::getContext
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:993
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::IsVolatile
constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
Definition: AMDGPUMetadata.h:194
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:127
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:228
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:175
isRegUsedByPhiNodes
static bool isRegUsedByPhiNodes(Register DefReg, FunctionLoweringInfo &FuncInfo)
Definition: FastISel.cpp:179
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:379
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:139
llvm::BasicBlock::getTerminator
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:152
llvm::ISD::InputArg::Flags
ArgFlagsTy Flags
Definition: TargetCallingConv.h:196
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::FastISel::fastEmitInst_ri
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:2018
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:634
Argument.h
llvm::ISD::ArgFlagsTy::setCFGuardTarget
void setCFGuardTarget()
Definition: TargetCallingConv.h:107
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:206
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:732
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:281
Constant.h
llvm::FastISel::tryToFoldLoad
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
Definition: FastISel.cpp:2213
llvm::APFloatBase::rmTowardZero
static constexpr roundingMode rmTowardZero
Definition: APFloat.h:194
llvm::PatchPointOpers::NBytesPos
@ NBytesPos
Definition: StackMaps.h:79
llvm::Constant::getNullValue
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:348
llvm::FastISel::lowerCall
bool lowerCall(const CallInst *I)
Definition: FastISel.cpp:1118
llvm::FastISel::selectExtractValue
bool selectExtractValue(const User *U)
Definition: FastISel.cpp:1665
getReturnAttrs
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
Definition: FastISel.cpp:946
llvm::FastISel::CallLoweringInfo::OutRegs
SmallVector< Register, 16 > OutRegs
Definition: FastISel.h:95
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
MachineFrameInfo.h
llvm::FastISel::selectFNeg
bool selectFNeg(const User *I, const Value *In)
Emit an FNeg operation.
Definition: FastISel.cpp:1623
llvm::Type::isEmptyTy
bool isEmptyTy() const
Return true if this type is empty, that is, it has no elements or all of its elements are empty.
Definition: Type.cpp:149
llvm::CallBase::arg_size
unsigned arg_size() const
Definition: InstrTypes.h:1326
llvm::ExtractValueInst
This instruction extracts a struct member or array element value from an aggregate value.
Definition: Instructions.h:2380
ISDOpcodes.h
Casting.h
DiagnosticInfo.h
Function.h
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1498
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:221
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::FastISel::CallLoweringInfo::RetTy
Type * RetTy
Definition: FastISel.h:70
StackMaps.h
llvm::FastISel::selectXRayCustomEvent
bool selectXRayCustomEvent(const CallInst *II)
Definition: FastISel.cpp:904
llvm::ISD::InputArg::VT
MVT VT
Definition: TargetCallingConv.h:197
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:748
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1376
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:224
FastISel.h
llvm::FastISel::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 4 > Ins
Definition: FastISel.h:96
llvm::FastISel::selectGetElementPtr
bool selectGetElementPtr(const User *I)
Definition: FastISel.cpp:541
Instructions.h
llvm::FunctionLoweringInfo::MF
MachineFunction * MF
Definition: FunctionLoweringInfo.h:55
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:378
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1653
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:657
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:212
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:510
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:381
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:886
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::Instruction::getDebugLoc
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:370
User.h
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:743
llvm::ISD::ArgFlagsTy::setSRet
void setSRet()
Definition: TargetCallingConv.h:83
llvm::DbgValueInst::getValue
Value * getValue(unsigned OpIdx=0) const
Definition: IntrinsicInst.h:351
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:736
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::CallBase::getArgOperand
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1328
N
#define N
llvm::FastISel::fastEmitInst_rrr
Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2)
Emit a MachineInstr with three register operands and a result register in the given register class.
Definition: FastISel.cpp:1992
llvm::Instruction::getParent
const BasicBlock * getParent() const
Definition: Instruction.h:94
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:659
llvm::PatchPointOpers::TargetPos
@ TargetPos
Definition: StackMaps.h:79
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:223
llvm::FastISel::removeDeadCode
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
Definition: FastISel.cpp:419
llvm::CmpInst::getPredicate
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:796
llvm::FastISel::CallLoweringInfo::setTailCall
CallLoweringInfo & setTailCall(bool Value=true)
Definition: FastISel.h:176
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:860
llvm::isInTailCallPosition
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:501
llvm::PHINode
Definition: Instructions.h:2633
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
MachineMemOperand.h
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:727
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::sys::path::rend
reverse_iterator rend(StringRef path)
Get reverse end iterator over path.
Definition: Path.cpp:304
MachineOperand.h
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:257
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:313
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1475
llvm::FastISel::TRI
const TargetRegisterInfo & TRI
Definition: FastISel.h:212
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:866
llvm::FastISel::selectCall
bool selectCall(const User *I)
Definition: FastISel.cpp:1160
llvm::ISD::ArgFlagsTy::setPreallocated
void setPreallocated()
Definition: TargetCallingConv.h:95
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::FunctionLoweringInfo::PHINodesToUpdate
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
Definition: FunctionLoweringInfo.h:174
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
LLVMContext.h
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
selectBinaryOp
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV),...
Definition: AArch64InstructionSelector.cpp:726
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::FastISel::optimizeCmpPredicate
CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const
Definition: FastISel.cpp:2333
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)
Definition: FastISel.h:103
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1417
llvm::FastISel::selectBitCast
bool selectBitCast(const User *I)
Definition: FastISel.cpp:1412
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3068
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
raw_ostream.h
llvm::FastISel::TII
const TargetInstrInfo & TII
Definition: FastISel.h:210
llvm::FastISel::fastEmitInst_extractsubreg
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx)
Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...
Definition: FastISel.cpp:2124
llvm::FastISel::lookUpRegForValue
Register lookUpRegForValue(const Value *V)
Look up the value to see if its value is already cached in a register.
Definition: FastISel.cpp:355
llvm::FastISel::finishCondBranch
void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)
Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...
Definition: FastISel.cpp:1604
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:737
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
Value.h
llvm::PatchPointOpers::IDPos
@ IDPos
Definition: StackMaps.h:79
llvm::FastISel::fastEmitInst_rr
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:1969
llvm::ISD::ArgFlagsTy::setSwiftAsync
void setSwiftAsync()
Definition: TargetCallingConv.h:101
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::ExtractValueInst::getIndices
ArrayRef< unsigned > getIndices() const
Definition: Instructions.h:2445
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::FastISel::DL
const DataLayout & DL
Definition: FastISel.h:209
llvm::FastISel::selectBinaryOp
bool selectBinaryOp(const User *I, unsigned ISDOpcode)
Select and emit code for a binary operator instruction, which has an opcode which directly correspond...
Definition: FastISel.cpp:453
Debug.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::FastISel::recomputeInsertPt
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
Definition: FastISel.cpp:405
llvm::FastISel::startNewBlock
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
Definition: FastISel.cpp:125
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:729
llvm::BranchInst::getSuccessor
BasicBlock * getSuccessor(unsigned i) const
Definition: Instructions.h:3161
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::FastISel::constrainOperandRegClass
Register constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum)
Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.
Definition: FastISel.cpp:1923
llvm::FastISel::fastEmitInst_r
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:1949
llvm::FastISel::fastEmitInst_i
Register fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm)
Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...
Definition: FastISel.cpp:2108
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:731
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:205
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:380