LLVM  16.0.0git
FastISel.cpp
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1 //===- FastISel.cpp - Implementation of the FastISel class ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of the FastISel class.
10 //
11 // "Fast" instruction selection is designed to emit very poor code quickly.
12 // Also, it is not designed to be able to do much lowering, so most illegal
13 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
14 // also not intended to be able to do much optimization, except in a few cases
15 // where doing optimizations reduces overall compile time. For example, folding
16 // constants into immediate fields is often done, because it's cheap and it
17 // reduces the number of instructions later phases have to examine.
18 //
19 // "Fast" instruction selection is able to fail gracefully and transfer
20 // control to the SelectionDAG selector for operations that it doesn't
21 // support. In many cases, this allows us to avoid duplicating a lot of
22 // the complicated lowering logic that SelectionDAG currently has.
23 //
24 // The intended use for "fast" instruction selection is "-O0" mode
25 // compilation, where the quality of the generated code is irrelevant when
26 // weighed against the speed at which the code can be generated. Also,
27 // at -O0, the LLVM optimizers are not running, and this makes the
28 // compile time of codegen a much higher portion of the overall compile
29 // time. Despite its limitations, "fast" instruction selection is able to
30 // handle enough code on its own to provide noticeable overall speedups
31 // in -O0 compiles.
32 //
33 // Basic operations are supported in a target-independent way, by reading
34 // the same instruction descriptions that the SelectionDAG selector reads,
35 // and identifying simple arithmetic operations that can be directly selected
36 // from simple operators. More complicated operations currently require
37 // target-specific code.
38 //
39 //===----------------------------------------------------------------------===//
40 
41 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/ADT/APFloat.h"
43 #include "llvm/ADT/APSInt.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/Optional.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/SmallVector.h"
49 #include "llvm/ADT/Statistic.h"
52 #include "llvm/CodeGen/Analysis.h"
63 #include "llvm/CodeGen/StackMaps.h"
68 #include "llvm/IR/Argument.h"
69 #include "llvm/IR/Attributes.h"
70 #include "llvm/IR/BasicBlock.h"
71 #include "llvm/IR/CallingConv.h"
72 #include "llvm/IR/Constant.h"
73 #include "llvm/IR/Constants.h"
74 #include "llvm/IR/DataLayout.h"
75 #include "llvm/IR/DebugLoc.h"
76 #include "llvm/IR/DerivedTypes.h"
77 #include "llvm/IR/DiagnosticInfo.h"
78 #include "llvm/IR/Function.h"
80 #include "llvm/IR/GlobalValue.h"
81 #include "llvm/IR/InlineAsm.h"
82 #include "llvm/IR/InstrTypes.h"
83 #include "llvm/IR/Instruction.h"
84 #include "llvm/IR/Instructions.h"
85 #include "llvm/IR/IntrinsicInst.h"
86 #include "llvm/IR/LLVMContext.h"
87 #include "llvm/IR/Mangler.h"
88 #include "llvm/IR/Metadata.h"
89 #include "llvm/IR/Operator.h"
90 #include "llvm/IR/PatternMatch.h"
91 #include "llvm/IR/Type.h"
92 #include "llvm/IR/User.h"
93 #include "llvm/IR/Value.h"
94 #include "llvm/MC/MCContext.h"
95 #include "llvm/MC/MCInstrDesc.h"
96 #include "llvm/Support/Casting.h"
97 #include "llvm/Support/Debug.h"
100 #include "llvm/Support/MathExtras.h"
104 #include <algorithm>
105 #include <cassert>
106 #include <cstdint>
107 #include <iterator>
108 #include <utility>
109 
110 using namespace llvm;
111 using namespace PatternMatch;
112 
113 #define DEBUG_TYPE "isel"
114 
115 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
116  "target-independent selector");
117 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
118  "target-specific selector");
119 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
120 
121 /// Set the current block to which generated machine instructions will be
122 /// appended.
124  assert(LocalValueMap.empty() &&
125  "local values should be cleared after finishing a BB");
126 
127  // Instructions are appended to FuncInfo.MBB. If the basic block already
128  // contains labels or copies, use the last instruction as the last local
129  // value.
130  EmitStartPt = nullptr;
131  if (!FuncInfo.MBB->empty())
132  EmitStartPt = &FuncInfo.MBB->back();
133  LastLocalValue = EmitStartPt;
134 }
135 
136 void FastISel::finishBasicBlock() { flushLocalValueMap(); }
137 
139  if (!FuncInfo.CanLowerReturn)
140  // Fallback to SDISel argument lowering code to deal with sret pointer
141  // parameter.
142  return false;
143 
144  if (!fastLowerArguments())
145  return false;
146 
147  // Enter arguments into ValueMap for uses in non-entry BBs.
148  for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
149  E = FuncInfo.Fn->arg_end();
150  I != E; ++I) {
151  DenseMap<const Value *, Register>::iterator VI = LocalValueMap.find(&*I);
152  assert(VI != LocalValueMap.end() && "Missed an argument?");
153  FuncInfo.ValueMap[&*I] = VI->second;
154  }
155  return true;
156 }
157 
158 /// Return the defined register if this instruction defines exactly one
159 /// virtual register and uses no other virtual registers. Otherwise return 0.
161  Register RegDef;
162  for (const MachineOperand &MO : MI.operands()) {
163  if (!MO.isReg())
164  continue;
165  if (MO.isDef()) {
166  if (RegDef)
167  return Register();
168  RegDef = MO.getReg();
169  } else if (MO.getReg().isVirtual()) {
170  // This is another use of a vreg. Don't delete it.
171  return Register();
172  }
173  }
174  return RegDef;
175 }
176 
177 static bool isRegUsedByPhiNodes(Register DefReg,
178  FunctionLoweringInfo &FuncInfo) {
179  for (auto &P : FuncInfo.PHINodesToUpdate)
180  if (P.second == DefReg)
181  return true;
182  return false;
183 }
184 
185 void FastISel::flushLocalValueMap() {
186  // If FastISel bails out, it could leave local value instructions behind
187  // that aren't used for anything. Detect and erase those.
188  if (LastLocalValue != EmitStartPt) {
189  // Save the first instruction after local values, for later.
190  MachineBasicBlock::iterator FirstNonValue(LastLocalValue);
191  ++FirstNonValue;
192 
194  EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
195  : FuncInfo.MBB->rend();
196  MachineBasicBlock::reverse_iterator RI(LastLocalValue);
197  for (MachineInstr &LocalMI :
199  Register DefReg = findLocalRegDef(LocalMI);
200  if (!DefReg)
201  continue;
202  if (FuncInfo.RegsWithFixups.count(DefReg))
203  continue;
204  bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
205  if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
206  if (EmitStartPt == &LocalMI)
207  EmitStartPt = EmitStartPt->getPrevNode();
208  LLVM_DEBUG(dbgs() << "removing dead local value materialization"
209  << LocalMI);
210  LocalMI.eraseFromParent();
211  }
212  }
213 
214  if (FirstNonValue != FuncInfo.MBB->end()) {
215  // See if there are any local value instructions left. If so, we want to
216  // make sure the first one has a debug location; if it doesn't, use the
217  // first non-value instruction's debug location.
218 
219  // If EmitStartPt is non-null, this block had copies at the top before
220  // FastISel started doing anything; it points to the last one, so the
221  // first local value instruction is the one after EmitStartPt.
222  // If EmitStartPt is null, the first local value instruction is at the
223  // top of the block.
224  MachineBasicBlock::iterator FirstLocalValue =
225  EmitStartPt ? ++MachineBasicBlock::iterator(EmitStartPt)
226  : FuncInfo.MBB->begin();
227  if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
228  FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
229  }
230  }
231 
232  LocalValueMap.clear();
233  LastLocalValue = EmitStartPt;
234  recomputeInsertPt();
235  SavedInsertPt = FuncInfo.InsertPt;
236 }
237 
239  EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
240  // Don't handle non-simple values in FastISel.
241  if (!RealVT.isSimple())
242  return Register();
243 
244  // Ignore illegal types. We must do this before looking up the value
245  // in ValueMap because Arguments are given virtual registers regardless
246  // of whether FastISel can handle them.
247  MVT VT = RealVT.getSimpleVT();
248  if (!TLI.isTypeLegal(VT)) {
249  // Handle integer promotions, though, because they're common and easy.
250  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
251  VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
252  else
253  return Register();
254  }
255 
256  // Look up the value to see if we already have a register for it.
257  Register Reg = lookUpRegForValue(V);
258  if (Reg)
259  return Reg;
260 
261  // In bottom-up mode, just create the virtual register which will be used
262  // to hold the value. It will be materialized later.
263  if (isa<Instruction>(V) &&
264  (!isa<AllocaInst>(V) ||
265  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
266  return FuncInfo.InitializeRegForValue(V);
267 
268  SavePoint SaveInsertPt = enterLocalValueArea();
269 
270  // Materialize the value in a register. Emit any instructions in the
271  // local value area.
272  Reg = materializeRegForValue(V, VT);
273 
274  leaveLocalValueArea(SaveInsertPt);
275 
276  return Reg;
277 }
278 
279 Register FastISel::materializeConstant(const Value *V, MVT VT) {
280  Register Reg;
281  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
282  if (CI->getValue().getActiveBits() <= 64)
283  Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
284  } else if (isa<AllocaInst>(V))
285  Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
286  else if (isa<ConstantPointerNull>(V))
287  // Translate this as an integer zero so that it can be
288  // local-CSE'd with actual integer zeros.
289  Reg =
290  getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getType())));
291  else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
292  if (CF->isNullValue())
293  Reg = fastMaterializeFloatZero(CF);
294  else
295  // Try to emit the constant directly.
296  Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
297 
298  if (!Reg) {
299  // Try to emit the constant by using an integer constant with a cast.
300  const APFloat &Flt = CF->getValueAPF();
301  EVT IntVT = TLI.getPointerTy(DL);
302  uint32_t IntBitWidth = IntVT.getSizeInBits();
303  APSInt SIntVal(IntBitWidth, /*isUnsigned=*/false);
304  bool isExact;
305  (void)Flt.convertToInteger(SIntVal, APFloat::rmTowardZero, &isExact);
306  if (isExact) {
307  Register IntegerReg =
308  getRegForValue(ConstantInt::get(V->getContext(), SIntVal));
309  if (IntegerReg)
310  Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
311  IntegerReg);
312  }
313  }
314  } else if (const auto *Op = dyn_cast<Operator>(V)) {
315  if (!selectOperator(Op, Op->getOpcode()))
316  if (!isa<Instruction>(Op) ||
317  !fastSelectInstruction(cast<Instruction>(Op)))
318  return 0;
319  Reg = lookUpRegForValue(Op);
320  } else if (isa<UndefValue>(V)) {
321  Reg = createResultReg(TLI.getRegClassFor(VT));
322  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
323  TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
324  }
325  return Reg;
326 }
327 
328 /// Helper for getRegForValue. This function is called when the value isn't
329 /// already available in a register and must be materialized with new
330 /// instructions.
331 Register FastISel::materializeRegForValue(const Value *V, MVT VT) {
332  Register Reg;
333  // Give the target-specific code a try first.
334  if (isa<Constant>(V))
335  Reg = fastMaterializeConstant(cast<Constant>(V));
336 
337  // If target-specific code couldn't or didn't want to handle the value, then
338  // give target-independent code a try.
339  if (!Reg)
340  Reg = materializeConstant(V, VT);
341 
342  // Don't cache constant materializations in the general ValueMap.
343  // To do so would require tracking what uses they dominate.
344  if (Reg) {
345  LocalValueMap[V] = Reg;
346  LastLocalValue = MRI.getVRegDef(Reg);
347  }
348  return Reg;
349 }
350 
352  // Look up the value to see if we already have a register for it. We
353  // cache values defined by Instructions across blocks, and other values
354  // only locally. This is because Instructions already have the SSA
355  // def-dominates-use requirement enforced.
356  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(V);
357  if (I != FuncInfo.ValueMap.end())
358  return I->second;
359  return LocalValueMap[V];
360 }
361 
362 void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
363  if (!isa<Instruction>(I)) {
364  LocalValueMap[I] = Reg;
365  return;
366  }
367 
368  Register &AssignedReg = FuncInfo.ValueMap[I];
369  if (!AssignedReg)
370  // Use the new register.
371  AssignedReg = Reg;
372  else if (Reg != AssignedReg) {
373  // Arrange for uses of AssignedReg to be replaced by uses of Reg.
374  for (unsigned i = 0; i < NumRegs; i++) {
375  FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
376  FuncInfo.RegsWithFixups.insert(Reg + i);
377  }
378 
379  AssignedReg = Reg;
380  }
381 }
382 
384  Register IdxN = getRegForValue(Idx);
385  if (!IdxN)
386  // Unhandled operand. Halt "fast" selection and bail.
387  return Register();
388 
389  // If the index is smaller or larger than intptr_t, truncate or extend it.
390  MVT PtrVT = TLI.getPointerTy(DL);
391  EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
392  if (IdxVT.bitsLT(PtrVT)) {
393  IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
394  } else if (IdxVT.bitsGT(PtrVT)) {
395  IdxN =
396  fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
397  }
398  return IdxN;
399 }
400 
402  if (getLastLocalValue()) {
403  FuncInfo.InsertPt = getLastLocalValue();
404  FuncInfo.MBB = FuncInfo.InsertPt->getParent();
405  ++FuncInfo.InsertPt;
406  } else
407  FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
408 
409  // Now skip past any EH_LABELs, which must remain at the beginning.
410  while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
411  FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
412  ++FuncInfo.InsertPt;
413 }
414 
417  assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
418  "Invalid iterator!");
419  while (I != E) {
420  if (SavedInsertPt == I)
421  SavedInsertPt = E;
422  if (EmitStartPt == I)
423  EmitStartPt = E.isValid() ? &*E : nullptr;
424  if (LastLocalValue == I)
425  LastLocalValue = E.isValid() ? &*E : nullptr;
426 
427  MachineInstr *Dead = &*I;
428  ++I;
429  Dead->eraseFromParent();
430  ++NumFastIselDead;
431  }
432  recomputeInsertPt();
433 }
434 
436  SavePoint OldInsertPt = FuncInfo.InsertPt;
437  recomputeInsertPt();
438  return OldInsertPt;
439 }
440 
442  if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
443  LastLocalValue = &*std::prev(FuncInfo.InsertPt);
444 
445  // Restore the previous insert position.
446  FuncInfo.InsertPt = OldInsertPt;
447 }
448 
449 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
450  EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
451  if (VT == MVT::Other || !VT.isSimple())
452  // Unhandled type. Halt "fast" selection and bail.
453  return false;
454 
455  // We only handle legal types. For example, on x86-32 the instruction
456  // selector contains all of the 64-bit instructions from x86-64,
457  // under the assumption that i64 won't be used if the target doesn't
458  // support it.
459  if (!TLI.isTypeLegal(VT)) {
460  // MVT::i1 is special. Allow AND, OR, or XOR because they
461  // don't require additional zeroing, which makes them easy.
462  if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
463  ISDOpcode == ISD::XOR))
464  VT = TLI.getTypeToTransformTo(I->getContext(), VT);
465  else
466  return false;
467  }
468 
469  // Check if the first operand is a constant, and handle it as "ri". At -O0,
470  // we don't have anything that canonicalizes operand order.
471  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
472  if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
473  Register Op1 = getRegForValue(I->getOperand(1));
474  if (!Op1)
475  return false;
476 
477  Register ResultReg =
478  fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(),
479  VT.getSimpleVT());
480  if (!ResultReg)
481  return false;
482 
483  // We successfully emitted code for the given LLVM Instruction.
484  updateValueMap(I, ResultReg);
485  return true;
486  }
487 
488  Register Op0 = getRegForValue(I->getOperand(0));
489  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
490  return false;
491 
492  // Check if the second operand is a constant and handle it appropriately.
493  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
494  uint64_t Imm = CI->getSExtValue();
495 
496  // Transform "sdiv exact X, 8" -> "sra X, 3".
497  if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
498  cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
499  Imm = Log2_64(Imm);
500  ISDOpcode = ISD::SRA;
501  }
502 
503  // Transform "urem x, pow2" -> "and x, pow2-1".
504  if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
505  isPowerOf2_64(Imm)) {
506  --Imm;
507  ISDOpcode = ISD::AND;
508  }
509 
510  Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
511  VT.getSimpleVT());
512  if (!ResultReg)
513  return false;
514 
515  // We successfully emitted code for the given LLVM Instruction.
516  updateValueMap(I, ResultReg);
517  return true;
518  }
519 
520  Register Op1 = getRegForValue(I->getOperand(1));
521  if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
522  return false;
523 
524  // Now we have both operands in registers. Emit the instruction.
525  Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
526  ISDOpcode, Op0, Op1);
527  if (!ResultReg)
528  // Target-specific code wasn't able to find a machine opcode for
529  // the given ISD opcode and type. Halt "fast" selection and bail.
530  return false;
531 
532  // We successfully emitted code for the given LLVM Instruction.
533  updateValueMap(I, ResultReg);
534  return true;
535 }
536 
538  Register N = getRegForValue(I->getOperand(0));
539  if (!N) // Unhandled operand. Halt "fast" selection and bail.
540  return false;
541 
542  // FIXME: The code below does not handle vector GEPs. Halt "fast" selection
543  // and bail.
544  if (isa<VectorType>(I->getType()))
545  return false;
546 
547  // Keep a running tab of the total offset to coalesce multiple N = N + Offset
548  // into a single N = N + TotalOffset.
549  uint64_t TotalOffs = 0;
550  // FIXME: What's a good SWAG number for MaxOffs?
551  uint64_t MaxOffs = 2048;
552  MVT VT = TLI.getPointerTy(DL);
554  GTI != E; ++GTI) {
555  const Value *Idx = GTI.getOperand();
556  if (StructType *StTy = GTI.getStructTypeOrNull()) {
557  uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
558  if (Field) {
559  // N = N + Offset
560  TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
561  if (TotalOffs >= MaxOffs) {
562  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
563  if (!N) // Unhandled operand. Halt "fast" selection and bail.
564  return false;
565  TotalOffs = 0;
566  }
567  }
568  } else {
569  Type *Ty = GTI.getIndexedType();
570 
571  // If this is a constant subscript, handle it quickly.
572  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
573  if (CI->isZero())
574  continue;
575  // N = N + Offset
576  uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
577  TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
578  if (TotalOffs >= MaxOffs) {
579  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
580  if (!N) // Unhandled operand. Halt "fast" selection and bail.
581  return false;
582  TotalOffs = 0;
583  }
584  continue;
585  }
586  if (TotalOffs) {
587  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
588  if (!N) // Unhandled operand. Halt "fast" selection and bail.
589  return false;
590  TotalOffs = 0;
591  }
592 
593  // N = N + Idx * ElementSize;
594  uint64_t ElementSize = DL.getTypeAllocSize(Ty);
595  Register IdxN = getRegForGEPIndex(Idx);
596  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
597  return false;
598 
599  if (ElementSize != 1) {
600  IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
601  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
602  return false;
603  }
604  N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
605  if (!N) // Unhandled operand. Halt "fast" selection and bail.
606  return false;
607  }
608  }
609  if (TotalOffs) {
610  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
611  if (!N) // Unhandled operand. Halt "fast" selection and bail.
612  return false;
613  }
614 
615  // We successfully emitted code for the given LLVM Instruction.
616  updateValueMap(I, N);
617  return true;
618 }
619 
620 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
621  const CallInst *CI, unsigned StartIdx) {
622  for (unsigned i = StartIdx, e = CI->arg_size(); i != e; ++i) {
623  Value *Val = CI->getArgOperand(i);
624  // Check for constants and encode them with a StackMaps::ConstantOp prefix.
625  if (const auto *C = dyn_cast<ConstantInt>(Val)) {
626  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
627  Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
628  } else if (isa<ConstantPointerNull>(Val)) {
629  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
630  Ops.push_back(MachineOperand::CreateImm(0));
631  } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
632  // Values coming from a stack location also require a special encoding,
633  // but that is added later on by the target specific frame index
634  // elimination implementation.
635  auto SI = FuncInfo.StaticAllocaMap.find(AI);
636  if (SI != FuncInfo.StaticAllocaMap.end())
637  Ops.push_back(MachineOperand::CreateFI(SI->second));
638  else
639  return false;
640  } else {
641  Register Reg = getRegForValue(Val);
642  if (!Reg)
643  return false;
644  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
645  }
646  }
647  return true;
648 }
649 
651  // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
652  // [live variables...])
653  assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
654  "Stackmap cannot return a value.");
655 
656  // The stackmap intrinsic only records the live variables (the arguments
657  // passed to it) and emits NOPS (if requested). Unlike the patchpoint
658  // intrinsic, this won't be lowered to a function call. This means we don't
659  // have to worry about calling conventions and target-specific lowering code.
660  // Instead we perform the call lowering right here.
661  //
662  // CALLSEQ_START(0, 0...)
663  // STACKMAP(id, nbytes, ...)
664  // CALLSEQ_END(0, 0)
665  //
667 
668  // Add the <id> and <numBytes> constants.
669  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
670  "Expected a constant integer.");
671  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
672  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
673 
674  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
675  "Expected a constant integer.");
676  const auto *NumBytes =
677  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
678  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
679 
680  // Push live variables for the stack map (skipping the first two arguments
681  // <id> and <numBytes>).
682  if (!addStackMapLiveVars(Ops, I, 2))
683  return false;
684 
685  // We are not adding any register mask info here, because the stackmap doesn't
686  // clobber anything.
687 
688  // Add scratch registers as implicit def and early clobber.
689  CallingConv::ID CC = I->getCallingConv();
690  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
691  for (unsigned i = 0; ScratchRegs[i]; ++i)
692  Ops.push_back(MachineOperand::CreateReg(
693  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
694  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
695 
696  // Issue CALLSEQ_START
697  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
698  auto Builder =
699  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AdjStackDown));
700  const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
701  for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
702  Builder.addImm(0);
703 
704  // Issue STACKMAP.
705  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
707  for (auto const &MO : Ops)
708  MIB.add(MO);
709 
710  // Issue CALLSEQ_END
711  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
712  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(AdjStackUp))
713  .addImm(0)
714  .addImm(0);
715 
716  // Inform the Frame Information that we have a stackmap in this function.
717  FuncInfo.MF->getFrameInfo().setHasStackMap();
718 
719  return true;
720 }
721 
722 /// Lower an argument list according to the target calling convention.
723 ///
724 /// This is a helper for lowering intrinsics that follow a target calling
725 /// convention or require stack pointer adjustment. Only a subset of the
726 /// intrinsic's operands need to participate in the calling convention.
727 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
728  unsigned NumArgs, const Value *Callee,
729  bool ForceRetVoidTy, CallLoweringInfo &CLI) {
730  ArgListTy Args;
731  Args.reserve(NumArgs);
732 
733  // Populate the argument list.
734  for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {
735  Value *V = CI->getOperand(ArgI);
736 
737  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
738 
739  ArgListEntry Entry;
740  Entry.Val = V;
741  Entry.Ty = V->getType();
742  Entry.setAttributes(CI, ArgI);
743  Args.push_back(Entry);
744  }
745 
746  Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
747  : CI->getType();
748  CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
749 
750  return lowerCallTo(CLI);
751 }
752 
754  const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
755  StringRef Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
756  SmallString<32> MangledName;
757  Mangler::getNameWithPrefix(MangledName, Target, DL);
758  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
759  return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
760 }
761 
763  // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
764  // i32 <numBytes>,
765  // i8* <target>,
766  // i32 <numArgs>,
767  // [Args...],
768  // [live variables...])
769  CallingConv::ID CC = I->getCallingConv();
770  bool IsAnyRegCC = CC == CallingConv::AnyReg;
771  bool HasDef = !I->getType()->isVoidTy();
772  Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
773 
774  // Get the real number of arguments participating in the call <numArgs>
775  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
776  "Expected a constant integer.");
777  const auto *NumArgsVal =
778  cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
779  unsigned NumArgs = NumArgsVal->getZExtValue();
780 
781  // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
782  // This includes all meta-operands up to but not including CC.
783  unsigned NumMetaOpers = PatchPointOpers::CCPos;
784  assert(I->arg_size() >= NumMetaOpers + NumArgs &&
785  "Not enough arguments provided to the patchpoint intrinsic");
786 
787  // For AnyRegCC the arguments are lowered later on manually.
788  unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
789  CallLoweringInfo CLI;
790  CLI.setIsPatchPoint();
791  if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
792  return false;
793 
794  assert(CLI.Call && "No call instruction specified.");
795 
797 
798  // Add an explicit result reg if we use the anyreg calling convention.
799  if (IsAnyRegCC && HasDef) {
800  assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
801  CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
802  CLI.NumResultRegs = 1;
803  Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
804  }
805 
806  // Add the <id> and <numBytes> constants.
807  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
808  "Expected a constant integer.");
809  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
810  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
811 
812  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
813  "Expected a constant integer.");
814  const auto *NumBytes =
815  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
816  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
817 
818  // Add the call target.
819  if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
820  uint64_t CalleeConstAddr =
821  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
822  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
823  } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
824  if (C->getOpcode() == Instruction::IntToPtr) {
825  uint64_t CalleeConstAddr =
826  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
827  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
828  } else
829  llvm_unreachable("Unsupported ConstantExpr.");
830  } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
831  Ops.push_back(MachineOperand::CreateGA(GV, 0));
832  } else if (isa<ConstantPointerNull>(Callee))
833  Ops.push_back(MachineOperand::CreateImm(0));
834  else
835  llvm_unreachable("Unsupported callee address.");
836 
837  // Adjust <numArgs> to account for any arguments that have been passed on
838  // the stack instead.
839  unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
840  Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
841 
842  // Add the calling convention
843  Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
844 
845  // Add the arguments we omitted previously. The register allocator should
846  // place these in any free register.
847  if (IsAnyRegCC) {
848  for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
849  Register Reg = getRegForValue(I->getArgOperand(i));
850  if (!Reg)
851  return false;
852  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
853  }
854  }
855 
856  // Push the arguments from the call instruction.
857  for (auto Reg : CLI.OutRegs)
858  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
859 
860  // Push live variables for the stack map.
861  if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
862  return false;
863 
864  // Push the register mask info.
865  Ops.push_back(MachineOperand::CreateRegMask(
866  TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
867 
868  // Add scratch registers as implicit def and early clobber.
869  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
870  for (unsigned i = 0; ScratchRegs[i]; ++i)
871  Ops.push_back(MachineOperand::CreateReg(
872  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
873  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
874 
875  // Add implicit defs (return values).
876  for (auto Reg : CLI.InRegs)
877  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
878  /*isImp=*/true));
879 
880  // Insert the patchpoint instruction before the call generated by the target.
881  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, MIMD,
883 
884  for (auto &MO : Ops)
885  MIB.add(MO);
886 
887  MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
888 
889  // Delete the original call instruction.
890  CLI.Call->eraseFromParent();
891 
892  // Inform the Frame Information that we have a patchpoint in this function.
893  FuncInfo.MF->getFrameInfo().setHasPatchPoint();
894 
895  if (CLI.NumResultRegs)
896  updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
897  return true;
898 }
899 
901  const auto &Triple = TM.getTargetTriple();
903  return true; // don't do anything to this instruction.
905  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
906  /*isDef=*/false));
907  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
908  /*isDef=*/false));
909  MachineInstrBuilder MIB =
910  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
911  TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));
912  for (auto &MO : Ops)
913  MIB.add(MO);
914 
915  // Insert the Patchable Event Call instruction, that gets lowered properly.
916  return true;
917 }
918 
920  const auto &Triple = TM.getTargetTriple();
922  return true; // don't do anything to this instruction.
924  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
925  /*isDef=*/false));
926  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
927  /*isDef=*/false));
928  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(2)),
929  /*isDef=*/false));
930  MachineInstrBuilder MIB =
931  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
932  TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
933  for (auto &MO : Ops)
934  MIB.add(MO);
935 
936  // Insert the Patchable Typed Event Call instruction, that gets lowered properly.
937  return true;
938 }
939 
940 /// Returns an AttributeList representing the attributes applied to the return
941 /// value of the given call.
944  if (CLI.RetSExt)
945  Attrs.push_back(Attribute::SExt);
946  if (CLI.RetZExt)
947  Attrs.push_back(Attribute::ZExt);
948  if (CLI.IsInReg)
949  Attrs.push_back(Attribute::InReg);
950 
952  Attrs);
953 }
954 
955 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
956  unsigned NumArgs) {
957  MCContext &Ctx = MF->getContext();
958  SmallString<32> MangledName;
959  Mangler::getNameWithPrefix(MangledName, SymName, DL);
960  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
961  return lowerCallTo(CI, Sym, NumArgs);
962 }
963 
964 bool FastISel::lowerCallTo(const CallInst *CI, MCSymbol *Symbol,
965  unsigned NumArgs) {
966  FunctionType *FTy = CI->getFunctionType();
967  Type *RetTy = CI->getType();
968 
969  ArgListTy Args;
970  Args.reserve(NumArgs);
971 
972  // Populate the argument list.
973  // Attributes for args start at offset 1, after the return attribute.
974  for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
975  Value *V = CI->getOperand(ArgI);
976 
977  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
978 
979  ArgListEntry Entry;
980  Entry.Val = V;
981  Entry.Ty = V->getType();
982  Entry.setAttributes(CI, ArgI);
983  Args.push_back(Entry);
984  }
985  TLI.markLibCallAttributes(MF, CI->getCallingConv(), Args);
986 
987  CallLoweringInfo CLI;
988  CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), *CI, NumArgs);
989 
990  return lowerCallTo(CLI);
991 }
992 
994  // Handle the incoming return values from the call.
995  CLI.clearIns();
996  SmallVector<EVT, 4> RetTys;
997  ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
998 
1000  GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
1001 
1002  bool CanLowerReturn = TLI.CanLowerReturn(
1003  CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
1004 
1005  // FIXME: sret demotion isn't supported yet - bail out.
1006  if (!CanLowerReturn)
1007  return false;
1008 
1009  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
1010  EVT VT = RetTys[I];
1011  MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
1012  unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
1013  for (unsigned i = 0; i != NumRegs; ++i) {
1014  ISD::InputArg MyFlags;
1015  MyFlags.VT = RegisterVT;
1016  MyFlags.ArgVT = VT;
1017  MyFlags.Used = CLI.IsReturnValueUsed;
1018  if (CLI.RetSExt)
1019  MyFlags.Flags.setSExt();
1020  if (CLI.RetZExt)
1021  MyFlags.Flags.setZExt();
1022  if (CLI.IsInReg)
1023  MyFlags.Flags.setInReg();
1024  CLI.Ins.push_back(MyFlags);
1025  }
1026  }
1027 
1028  // Handle all of the outgoing arguments.
1029  CLI.clearOuts();
1030  for (auto &Arg : CLI.getArgs()) {
1031  Type *FinalType = Arg.Ty;
1032  if (Arg.IsByVal)
1033  FinalType = Arg.IndirectType;
1034  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1035  FinalType, CLI.CallConv, CLI.IsVarArg, DL);
1036 
1037  ISD::ArgFlagsTy Flags;
1038  if (Arg.IsZExt)
1039  Flags.setZExt();
1040  if (Arg.IsSExt)
1041  Flags.setSExt();
1042  if (Arg.IsInReg)
1043  Flags.setInReg();
1044  if (Arg.IsSRet)
1045  Flags.setSRet();
1046  if (Arg.IsSwiftSelf)
1047  Flags.setSwiftSelf();
1048  if (Arg.IsSwiftAsync)
1049  Flags.setSwiftAsync();
1050  if (Arg.IsSwiftError)
1051  Flags.setSwiftError();
1052  if (Arg.IsCFGuardTarget)
1053  Flags.setCFGuardTarget();
1054  if (Arg.IsByVal)
1055  Flags.setByVal();
1056  if (Arg.IsInAlloca) {
1057  Flags.setInAlloca();
1058  // Set the byval flag for CCAssignFn callbacks that don't know about
1059  // inalloca. This way we can know how many bytes we should've allocated
1060  // and how many bytes a callee cleanup function will pop. If we port
1061  // inalloca to more targets, we'll have to add custom inalloca handling in
1062  // the various CC lowering callbacks.
1063  Flags.setByVal();
1064  }
1065  if (Arg.IsPreallocated) {
1066  Flags.setPreallocated();
1067  // Set the byval flag for CCAssignFn callbacks that don't know about
1068  // preallocated. This way we can know how many bytes we should've
1069  // allocated and how many bytes a callee cleanup function will pop. If we
1070  // port preallocated to more targets, we'll have to add custom
1071  // preallocated handling in the various CC lowering callbacks.
1072  Flags.setByVal();
1073  }
1074  MaybeAlign MemAlign = Arg.Alignment;
1075  if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {
1076  unsigned FrameSize = DL.getTypeAllocSize(Arg.IndirectType);
1077 
1078  // For ByVal, alignment should come from FE. BE will guess if this info
1079  // is not there, but there are cases it cannot get right.
1080  if (!MemAlign)
1081  MemAlign = Align(TLI.getByValTypeAlignment(Arg.IndirectType, DL));
1082  Flags.setByValSize(FrameSize);
1083  } else if (!MemAlign) {
1084  MemAlign = DL.getABITypeAlign(Arg.Ty);
1085  }
1086  Flags.setMemAlign(*MemAlign);
1087  if (Arg.IsNest)
1088  Flags.setNest();
1089  if (NeedsRegBlock)
1090  Flags.setInConsecutiveRegs();
1091  Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
1092  CLI.OutVals.push_back(Arg.Val);
1093  CLI.OutFlags.push_back(Flags);
1094  }
1095 
1096  if (!fastLowerCall(CLI))
1097  return false;
1098 
1099  // Set all unused physreg defs as dead.
1100  assert(CLI.Call && "No call instruction specified.");
1101  CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
1102 
1103  if (CLI.NumResultRegs && CLI.CB)
1104  updateValueMap(CLI.CB, CLI.ResultReg, CLI.NumResultRegs);
1105 
1106  // Set labels for heapallocsite call.
1107  if (CLI.CB)
1108  if (MDNode *MD = CLI.CB->getMetadata("heapallocsite"))
1109  CLI.Call->setHeapAllocMarker(*MF, MD);
1110 
1111  return true;
1112 }
1113 
1115  FunctionType *FuncTy = CI->getFunctionType();
1116  Type *RetTy = CI->getType();
1117 
1118  ArgListTy Args;
1119  ArgListEntry Entry;
1120  Args.reserve(CI->arg_size());
1121 
1122  for (auto i = CI->arg_begin(), e = CI->arg_end(); i != e; ++i) {
1123  Value *V = *i;
1124 
1125  // Skip empty types
1126  if (V->getType()->isEmptyTy())
1127  continue;
1128 
1129  Entry.Val = V;
1130  Entry.Ty = V->getType();
1131 
1132  // Skip the first return-type Attribute to get to params.
1133  Entry.setAttributes(CI, i - CI->arg_begin());
1134  Args.push_back(Entry);
1135  }
1136 
1137  // Check if target-independent constraints permit a tail call here.
1138  // Target-dependent constraints are checked within fastLowerCall.
1139  bool IsTailCall = CI->isTailCall();
1140  if (IsTailCall && !isInTailCallPosition(*CI, TM))
1141  IsTailCall = false;
1142  if (IsTailCall && !CI->isMustTailCall() &&
1143  MF->getFunction().getFnAttribute("disable-tail-calls").getValueAsBool())
1144  IsTailCall = false;
1145 
1146  CallLoweringInfo CLI;
1147  CLI.setCallee(RetTy, FuncTy, CI->getCalledOperand(), std::move(Args), *CI)
1148  .setTailCall(IsTailCall);
1149 
1150  diagnoseDontCall(*CI);
1151 
1152  return lowerCallTo(CLI);
1153 }
1154 
1156  const CallInst *Call = cast<CallInst>(I);
1157 
1158  // Handle simple inline asms.
1159  if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledOperand())) {
1160  // Don't attempt to handle constraints.
1161  if (!IA->getConstraintString().empty())
1162  return false;
1163 
1164  unsigned ExtraInfo = 0;
1165  if (IA->hasSideEffects())
1166  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1167  if (IA->isAlignStack())
1168  ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1169  if (Call->isConvergent())
1170  ExtraInfo |= InlineAsm::Extra_IsConvergent;
1171  ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
1172 
1173  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1175  MIB.addExternalSymbol(IA->getAsmString().c_str());
1176  MIB.addImm(ExtraInfo);
1177 
1178  const MDNode *SrcLoc = Call->getMetadata("srcloc");
1179  if (SrcLoc)
1180  MIB.addMetadata(SrcLoc);
1181 
1182  return true;
1183  }
1184 
1185  // Handle intrinsic function calls.
1186  if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1187  return selectIntrinsicCall(II);
1188 
1189  return lowerCall(Call);
1190 }
1191 
1193  switch (II->getIntrinsicID()) {
1194  default:
1195  break;
1196  // At -O0 we don't care about the lifetime intrinsics.
1197  case Intrinsic::lifetime_start:
1198  case Intrinsic::lifetime_end:
1199  // The donothing intrinsic does, well, nothing.
1200  case Intrinsic::donothing:
1201  // Neither does the sideeffect intrinsic.
1202  case Intrinsic::sideeffect:
1203  // Neither does the assume intrinsic; it's also OK not to codegen its operand.
1204  case Intrinsic::assume:
1205  // Neither does the llvm.experimental.noalias.scope.decl intrinsic
1206  case Intrinsic::experimental_noalias_scope_decl:
1207  return true;
1208  case Intrinsic::dbg_declare: {
1209  const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1210  assert(DI->getVariable() && "Missing variable");
1211  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1212  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1213  << " (!hasDebugInfo)\n");
1214  return true;
1215  }
1216 
1217  const Value *Address = DI->getAddress();
1218  if (!Address || isa<UndefValue>(Address)) {
1219  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1220  << " (bad/undef address)\n");
1221  return true;
1222  }
1223 
1224  // Byval arguments with frame indices were already handled after argument
1225  // lowering and before isel.
1226  const auto *Arg =
1227  dyn_cast<Argument>(Address->stripInBoundsConstantOffsets());
1228  if (Arg && FuncInfo.getArgumentFrameIndex(Arg) != INT_MAX)
1229  return true;
1230 
1232  if (Register Reg = lookUpRegForValue(Address))
1233  Op = MachineOperand::CreateReg(Reg, false);
1234 
1235  // If we have a VLA that has a "use" in a metadata node that's then used
1236  // here but it has no other uses, then we have a problem. E.g.,
1237  //
1238  // int foo (const int *x) {
1239  // char a[*x];
1240  // return 0;
1241  // }
1242  //
1243  // If we assign 'a' a vreg and fast isel later on has to use the selection
1244  // DAG isel, it will want to copy the value to the vreg. However, there are
1245  // no uses, which goes counter to what selection DAG isel expects.
1246  if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1247  (!isa<AllocaInst>(Address) ||
1248  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1249  Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1250  false);
1251 
1252  if (Op) {
1253  assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
1254  "Expected inlined-at fields to agree");
1255  // A dbg.declare describes the address of a source variable, so lower it
1256  // into an indirect DBG_VALUE.
1257  auto Builder =
1258  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
1259  TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true, *Op,
1260  DI->getVariable(), DI->getExpression());
1261 
1262  // If using instruction referencing, mutate this into a DBG_INSTR_REF,
1263  // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
1264  // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
1265  if (UseInstrRefDebugInfo && Op->isReg()) {
1266  Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
1267  Builder->getOperand(1).ChangeToImmediate(0);
1268  auto *NewExpr =
1270  Builder->getOperand(3).setMetadata(NewExpr);
1271  }
1272  } else {
1273  // We can't yet handle anything else here because it would require
1274  // generating code, thus altering codegen because of debug info.
1275  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1276  << " (no materialized reg for address)\n");
1277  }
1278  return true;
1279  }
1280  case Intrinsic::dbg_value: {
1281  // This form of DBG_VALUE is target-independent.
1282  const DbgValueInst *DI = cast<DbgValueInst>(II);
1283  const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1284  const Value *V = DI->getValue();
1285  assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
1286  "Expected inlined-at fields to agree");
1287  if (!V || isa<UndefValue>(V) || DI->hasArgList()) {
1288  // DI is either undef or cannot produce a valid DBG_VALUE, so produce an
1289  // undef DBG_VALUE to terminate any prior location.
1290  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, false, 0U,
1291  DI->getVariable(), DI->getExpression());
1292  } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1293  // See if there's an expression to constant-fold.
1294  DIExpression *Expr = DI->getExpression();
1295  if (Expr)
1296  std::tie(Expr, CI) = Expr->constantFold(CI);
1297  if (CI->getBitWidth() > 64)
1298  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
1299  .addCImm(CI)
1300  .addImm(0U)
1301  .addMetadata(DI->getVariable())
1302  .addMetadata(Expr);
1303  else
1304  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
1305  .addImm(CI->getZExtValue())
1306  .addImm(0U)
1307  .addMetadata(DI->getVariable())
1308  .addMetadata(Expr);
1309  } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1310  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
1311  .addFPImm(CF)
1312  .addImm(0U)
1313  .addMetadata(DI->getVariable())
1314  .addMetadata(DI->getExpression());
1315  } else if (Register Reg = lookUpRegForValue(V)) {
1316  // FIXME: This does not handle register-indirect values at offset 0.
1317  bool IsIndirect = false;
1318  auto Builder =
1319  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II,
1320  IsIndirect, Reg, DI->getVariable(), DI->getExpression());
1321 
1322  // If using instruction referencing, mutate this into a DBG_INSTR_REF,
1323  // to be later patched up by finalizeDebugInstrRefs.
1324  if (UseInstrRefDebugInfo) {
1325  Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
1326  Builder->getOperand(1).ChangeToImmediate(0);
1327  }
1328  } else {
1329  // We don't know how to handle other cases, so we drop.
1330  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1331  }
1332  return true;
1333  }
1334  case Intrinsic::dbg_label: {
1335  const DbgLabelInst *DI = cast<DbgLabelInst>(II);
1336  assert(DI->getLabel() && "Missing label");
1337  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1338  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1339  return true;
1340  }
1341 
1342  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1343  TII.get(TargetOpcode::DBG_LABEL)).addMetadata(DI->getLabel());
1344  return true;
1345  }
1346  case Intrinsic::objectsize:
1347  llvm_unreachable("llvm.objectsize.* should have been lowered already");
1348 
1349  case Intrinsic::is_constant:
1350  llvm_unreachable("llvm.is.constant.* should have been lowered already");
1351 
1352  case Intrinsic::launder_invariant_group:
1353  case Intrinsic::strip_invariant_group:
1354  case Intrinsic::expect: {
1355  Register ResultReg = getRegForValue(II->getArgOperand(0));
1356  if (!ResultReg)
1357  return false;
1358  updateValueMap(II, ResultReg);
1359  return true;
1360  }
1361  case Intrinsic::experimental_stackmap:
1362  return selectStackmap(II);
1363  case Intrinsic::experimental_patchpoint_void:
1364  case Intrinsic::experimental_patchpoint_i64:
1365  return selectPatchpoint(II);
1366 
1367  case Intrinsic::xray_customevent:
1368  return selectXRayCustomEvent(II);
1369  case Intrinsic::xray_typedevent:
1370  return selectXRayTypedEvent(II);
1371  }
1372 
1373  return fastLowerIntrinsicCall(II);
1374 }
1375 
1376 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1377  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1378  EVT DstVT = TLI.getValueType(DL, I->getType());
1379 
1380  if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1381  !DstVT.isSimple())
1382  // Unhandled type. Halt "fast" selection and bail.
1383  return false;
1384 
1385  // Check if the destination type is legal.
1386  if (!TLI.isTypeLegal(DstVT))
1387  return false;
1388 
1389  // Check if the source operand is legal.
1390  if (!TLI.isTypeLegal(SrcVT))
1391  return false;
1392 
1393  Register InputReg = getRegForValue(I->getOperand(0));
1394  if (!InputReg)
1395  // Unhandled operand. Halt "fast" selection and bail.
1396  return false;
1397 
1398  Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1399  Opcode, InputReg);
1400  if (!ResultReg)
1401  return false;
1402 
1403  updateValueMap(I, ResultReg);
1404  return true;
1405 }
1406 
1408  EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1409  EVT DstEVT = TLI.getValueType(DL, I->getType());
1410  if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1411  !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1412  // Unhandled type. Halt "fast" selection and bail.
1413  return false;
1414 
1415  MVT SrcVT = SrcEVT.getSimpleVT();
1416  MVT DstVT = DstEVT.getSimpleVT();
1417  Register Op0 = getRegForValue(I->getOperand(0));
1418  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1419  return false;
1420 
1421  // If the bitcast doesn't change the type, just use the operand value.
1422  if (SrcVT == DstVT) {
1423  updateValueMap(I, Op0);
1424  return true;
1425  }
1426 
1427  // Otherwise, select a BITCAST opcode.
1428  Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1429  if (!ResultReg)
1430  return false;
1431 
1432  updateValueMap(I, ResultReg);
1433  return true;
1434 }
1435 
1437  Register Reg = getRegForValue(I->getOperand(0));
1438  if (!Reg)
1439  // Unhandled operand.
1440  return false;
1441 
1442  EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());
1443  if (ETy == MVT::Other || !TLI.isTypeLegal(ETy))
1444  // Unhandled type, bail out.
1445  return false;
1446 
1447  MVT Ty = ETy.getSimpleVT();
1448  const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
1449  Register ResultReg = createResultReg(TyRegClass);
1450  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
1451  TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
1452 
1453  updateValueMap(I, ResultReg);
1454  return true;
1455 }
1456 
1457 // Remove local value instructions starting from the instruction after
1458 // SavedLastLocalValue to the current function insert point.
1459 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
1460 {
1461  MachineInstr *CurLastLocalValue = getLastLocalValue();
1462  if (CurLastLocalValue != SavedLastLocalValue) {
1463  // Find the first local value instruction to be deleted.
1464  // This is the instruction after SavedLastLocalValue if it is non-NULL.
1465  // Otherwise it's the first instruction in the block.
1466  MachineBasicBlock::iterator FirstDeadInst(SavedLastLocalValue);
1467  if (SavedLastLocalValue)
1468  ++FirstDeadInst;
1469  else
1470  FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
1471  setLastLocalValue(SavedLastLocalValue);
1472  removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
1473  }
1474 }
1475 
1477  // Flush the local value map before starting each instruction.
1478  // This improves locality and debugging, and can reduce spills.
1479  // Reuse of values across IR instructions is relatively uncommon.
1480  flushLocalValueMap();
1481 
1482  MachineInstr *SavedLastLocalValue = getLastLocalValue();
1483  // Just before the terminator instruction, insert instructions to
1484  // feed PHI nodes in successor blocks.
1485  if (I->isTerminator()) {
1486  if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
1487  // PHI node handling may have generated local value instructions,
1488  // even though it failed to handle all PHI nodes.
1489  // We remove these instructions because SelectionDAGISel will generate
1490  // them again.
1491  removeDeadLocalValueCode(SavedLastLocalValue);
1492  return false;
1493  }
1494  }
1495 
1496  // FastISel does not handle any operand bundles except OB_funclet.
1497  if (auto *Call = dyn_cast<CallBase>(I))
1498  for (unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)
1499  if (Call->getOperandBundleAt(i).getTagID() != LLVMContext::OB_funclet)
1500  return false;
1501 
1502  MIMD = MIMetadata(*I);
1503 
1504  SavedInsertPt = FuncInfo.InsertPt;
1505 
1506  if (const auto *Call = dyn_cast<CallInst>(I)) {
1507  const Function *F = Call->getCalledFunction();
1508  LibFunc Func;
1509 
1510  // As a special case, don't handle calls to builtin library functions that
1511  // may be translated directly to target instructions.
1512  if (F && !F->hasLocalLinkage() && F->hasName() &&
1513  LibInfo->getLibFunc(F->getName(), Func) &&
1514  LibInfo->hasOptimizedCodeGen(Func))
1515  return false;
1516 
1517  // Don't handle Intrinsic::trap if a trap function is specified.
1518  if (F && F->getIntrinsicID() == Intrinsic::trap &&
1519  Call->hasFnAttr("trap-func-name"))
1520  return false;
1521  }
1522 
1523  // First, try doing target-independent selection.
1524  if (!SkipTargetIndependentISel) {
1525  if (selectOperator(I, I->getOpcode())) {
1526  ++NumFastIselSuccessIndependent;
1527  MIMD = {};
1528  return true;
1529  }
1530  // Remove dead code.
1531  recomputeInsertPt();
1532  if (SavedInsertPt != FuncInfo.InsertPt)
1533  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1534  SavedInsertPt = FuncInfo.InsertPt;
1535  }
1536  // Next, try calling the target to attempt to handle the instruction.
1537  if (fastSelectInstruction(I)) {
1538  ++NumFastIselSuccessTarget;
1539  MIMD = {};
1540  return true;
1541  }
1542  // Remove dead code.
1543  recomputeInsertPt();
1544  if (SavedInsertPt != FuncInfo.InsertPt)
1545  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1546 
1547  MIMD = {};
1548  // Undo phi node updates, because they will be added again by SelectionDAG.
1549  if (I->isTerminator()) {
1550  // PHI node handling may have generated local value instructions.
1551  // We remove them because SelectionDAGISel will generate them again.
1552  removeDeadLocalValueCode(SavedLastLocalValue);
1553  FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1554  }
1555  return false;
1556 }
1557 
1558 /// Emit an unconditional branch to the given block, unless it is the immediate
1559 /// (fall-through) successor, and update the CFG.
1561  const DebugLoc &DbgLoc) {
1562  if (FuncInfo.MBB->getBasicBlock()->sizeWithoutDebug() > 1 &&
1563  FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1564  // For more accurate line information if this is the only non-debug
1565  // instruction in the block then emit it, otherwise we have the
1566  // unconditional fall-through case, which needs no instructions.
1567  } else {
1568  // The unconditional branch case.
1569  TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,
1570  SmallVector<MachineOperand, 0>(), DbgLoc);
1571  }
1572  if (FuncInfo.BPI) {
1573  auto BranchProbability = FuncInfo.BPI->getEdgeProbability(
1574  FuncInfo.MBB->getBasicBlock(), MSucc->getBasicBlock());
1575  FuncInfo.MBB->addSuccessor(MSucc, BranchProbability);
1576  } else
1577  FuncInfo.MBB->addSuccessorWithoutProb(MSucc);
1578 }
1579 
1581  MachineBasicBlock *TrueMBB,
1582  MachineBasicBlock *FalseMBB) {
1583  // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
1584  // happen in degenerate IR and MachineIR forbids to have a block twice in the
1585  // successor/predecessor lists.
1586  if (TrueMBB != FalseMBB) {
1587  if (FuncInfo.BPI) {
1588  auto BranchProbability =
1589  FuncInfo.BPI->getEdgeProbability(BranchBB, TrueMBB->getBasicBlock());
1590  FuncInfo.MBB->addSuccessor(TrueMBB, BranchProbability);
1591  } else
1592  FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);
1593  }
1594 
1595  fastEmitBranch(FalseMBB, MIMD.getDL());
1596 }
1597 
1598 /// Emit an FNeg operation.
1599 bool FastISel::selectFNeg(const User *I, const Value *In) {
1600  Register OpReg = getRegForValue(In);
1601  if (!OpReg)
1602  return false;
1603 
1604  // If the target has ISD::FNEG, use it.
1605  EVT VT = TLI.getValueType(DL, I->getType());
1606  Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1607  OpReg);
1608  if (ResultReg) {
1609  updateValueMap(I, ResultReg);
1610  return true;
1611  }
1612 
1613  // Bitcast the value to integer, twiddle the sign bit with xor,
1614  // and then bitcast it back to floating-point.
1615  if (VT.getSizeInBits() > 64)
1616  return false;
1617  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1618  if (!TLI.isTypeLegal(IntVT))
1619  return false;
1620 
1621  Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1622  ISD::BITCAST, OpReg);
1623  if (!IntReg)
1624  return false;
1625 
1626  Register IntResultReg = fastEmit_ri_(
1627  IntVT.getSimpleVT(), ISD::XOR, IntReg,
1628  UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1629  if (!IntResultReg)
1630  return false;
1631 
1632  ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1633  IntResultReg);
1634  if (!ResultReg)
1635  return false;
1636 
1637  updateValueMap(I, ResultReg);
1638  return true;
1639 }
1640 
1642  const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1643  if (!EVI)
1644  return false;
1645 
1646  // Make sure we only try to handle extracts with a legal result. But also
1647  // allow i1 because it's easy.
1648  EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1649  if (!RealVT.isSimple())
1650  return false;
1651  MVT VT = RealVT.getSimpleVT();
1652  if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1653  return false;
1654 
1655  const Value *Op0 = EVI->getOperand(0);
1656  Type *AggTy = Op0->getType();
1657 
1658  // Get the base result register.
1659  unsigned ResultReg;
1660  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1661  if (I != FuncInfo.ValueMap.end())
1662  ResultReg = I->second;
1663  else if (isa<Instruction>(Op0))
1664  ResultReg = FuncInfo.InitializeRegForValue(Op0);
1665  else
1666  return false; // fast-isel can't handle aggregate constants at the moment
1667 
1668  // Get the actual result register, which is an offset from the base register.
1669  unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1670 
1671  SmallVector<EVT, 4> AggValueVTs;
1672  ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1673 
1674  for (unsigned i = 0; i < VTIndex; i++)
1675  ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1676 
1677  updateValueMap(EVI, ResultReg);
1678  return true;
1679 }
1680 
1681 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1682  switch (Opcode) {
1683  case Instruction::Add:
1684  return selectBinaryOp(I, ISD::ADD);
1685  case Instruction::FAdd:
1686  return selectBinaryOp(I, ISD::FADD);
1687  case Instruction::Sub:
1688  return selectBinaryOp(I, ISD::SUB);
1689  case Instruction::FSub:
1690  return selectBinaryOp(I, ISD::FSUB);
1691  case Instruction::Mul:
1692  return selectBinaryOp(I, ISD::MUL);
1693  case Instruction::FMul:
1694  return selectBinaryOp(I, ISD::FMUL);
1695  case Instruction::SDiv:
1696  return selectBinaryOp(I, ISD::SDIV);
1697  case Instruction::UDiv:
1698  return selectBinaryOp(I, ISD::UDIV);
1699  case Instruction::FDiv:
1700  return selectBinaryOp(I, ISD::FDIV);
1701  case Instruction::SRem:
1702  return selectBinaryOp(I, ISD::SREM);
1703  case Instruction::URem:
1704  return selectBinaryOp(I, ISD::UREM);
1705  case Instruction::FRem:
1706  return selectBinaryOp(I, ISD::FREM);
1707  case Instruction::Shl:
1708  return selectBinaryOp(I, ISD::SHL);
1709  case Instruction::LShr:
1710  return selectBinaryOp(I, ISD::SRL);
1711  case Instruction::AShr:
1712  return selectBinaryOp(I, ISD::SRA);
1713  case Instruction::And:
1714  return selectBinaryOp(I, ISD::AND);
1715  case Instruction::Or:
1716  return selectBinaryOp(I, ISD::OR);
1717  case Instruction::Xor:
1718  return selectBinaryOp(I, ISD::XOR);
1719 
1720  case Instruction::FNeg:
1721  return selectFNeg(I, I->getOperand(0));
1722 
1723  case Instruction::GetElementPtr:
1724  return selectGetElementPtr(I);
1725 
1726  case Instruction::Br: {
1727  const BranchInst *BI = cast<BranchInst>(I);
1728 
1729  if (BI->isUnconditional()) {
1730  const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1731  MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1732  fastEmitBranch(MSucc, BI->getDebugLoc());
1733  return true;
1734  }
1735 
1736  // Conditional branches are not handed yet.
1737  // Halt "fast" selection and bail.
1738  return false;
1739  }
1740 
1741  case Instruction::Unreachable:
1742  if (TM.Options.TrapUnreachable)
1743  return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1744  else
1745  return true;
1746 
1747  case Instruction::Alloca:
1748  // FunctionLowering has the static-sized case covered.
1749  if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1750  return true;
1751 
1752  // Dynamic-sized alloca is not handled yet.
1753  return false;
1754 
1755  case Instruction::Call:
1756  // On AIX, normal call lowering uses the DAG-ISEL path currently so that the
1757  // callee of the direct function call instruction will be mapped to the
1758  // symbol for the function's entry point, which is distinct from the
1759  // function descriptor symbol. The latter is the symbol whose XCOFF symbol
1760  // name is the C-linkage name of the source level function.
1761  // But fast isel still has the ability to do selection for intrinsics.
1762  if (TM.getTargetTriple().isOSAIX() && !isa<IntrinsicInst>(I))
1763  return false;
1764  return selectCall(I);
1765 
1766  case Instruction::BitCast:
1767  return selectBitCast(I);
1768 
1769  case Instruction::FPToSI:
1770  return selectCast(I, ISD::FP_TO_SINT);
1771  case Instruction::ZExt:
1772  return selectCast(I, ISD::ZERO_EXTEND);
1773  case Instruction::SExt:
1774  return selectCast(I, ISD::SIGN_EXTEND);
1775  case Instruction::Trunc:
1776  return selectCast(I, ISD::TRUNCATE);
1777  case Instruction::SIToFP:
1778  return selectCast(I, ISD::SINT_TO_FP);
1779 
1780  case Instruction::IntToPtr: // Deliberate fall-through.
1781  case Instruction::PtrToInt: {
1782  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1783  EVT DstVT = TLI.getValueType(DL, I->getType());
1784  if (DstVT.bitsGT(SrcVT))
1785  return selectCast(I, ISD::ZERO_EXTEND);
1786  if (DstVT.bitsLT(SrcVT))
1787  return selectCast(I, ISD::TRUNCATE);
1788  Register Reg = getRegForValue(I->getOperand(0));
1789  if (!Reg)
1790  return false;
1791  updateValueMap(I, Reg);
1792  return true;
1793  }
1794 
1795  case Instruction::ExtractValue:
1796  return selectExtractValue(I);
1797 
1798  case Instruction::Freeze:
1799  return selectFreeze(I);
1800 
1801  case Instruction::PHI:
1802  llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1803 
1804  default:
1805  // Unhandled instruction. Halt "fast" selection and bail.
1806  return false;
1807  }
1808 }
1809 
1811  const TargetLibraryInfo *LibInfo,
1812  bool SkipTargetIndependentISel)
1813  : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1814  MFI(FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1815  TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1816  TII(*MF->getSubtarget().getInstrInfo()),
1817  TLI(*MF->getSubtarget().getTargetLowering()),
1818  TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1819  SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1820 
1821 FastISel::~FastISel() = default;
1822 
1823 bool FastISel::fastLowerArguments() { return false; }
1824 
1825 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1826 
1828  return false;
1829 }
1830 
1831 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1832 
1833 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1834  return 0;
1835 }
1836 
1837 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1838  unsigned /*Op1*/) {
1839  return 0;
1840 }
1841 
1842 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1843  return 0;
1844 }
1845 
1846 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1847  const ConstantFP * /*FPImm*/) {
1848  return 0;
1849 }
1850 
1851 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1852  uint64_t /*Imm*/) {
1853  return 0;
1854 }
1855 
1856 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1857 /// instruction with an immediate operand using fastEmit_ri.
1858 /// If that fails, it materializes the immediate into a register and try
1859 /// fastEmit_rr instead.
1860 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1861  uint64_t Imm, MVT ImmType) {
1862  // If this is a multiply by a power of two, emit this as a shift left.
1863  if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1864  Opcode = ISD::SHL;
1865  Imm = Log2_64(Imm);
1866  } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1867  // div x, 8 -> srl x, 3
1868  Opcode = ISD::SRL;
1869  Imm = Log2_64(Imm);
1870  }
1871 
1872  // Horrible hack (to be removed), check to make sure shift amounts are
1873  // in-range.
1874  if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1875  Imm >= VT.getSizeInBits())
1876  return 0;
1877 
1878  // First check if immediate type is legal. If not, we can't use the ri form.
1879  Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
1880  if (ResultReg)
1881  return ResultReg;
1882  Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1883  if (!MaterialReg) {
1884  // This is a bit ugly/slow, but failing here means falling out of
1885  // fast-isel, which would be very slow.
1886  IntegerType *ITy =
1888  MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1889  if (!MaterialReg)
1890  return 0;
1891  }
1892  return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
1893 }
1894 
1896  return MRI.createVirtualRegister(RC);
1897 }
1898 
1900  unsigned OpNum) {
1901  if (Op.isVirtual()) {
1902  const TargetRegisterClass *RegClass =
1903  TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1904  if (!MRI.constrainRegClass(Op, RegClass)) {
1905  // If it's not legal to COPY between the register classes, something
1906  // has gone very wrong before we got here.
1907  Register NewOp = createResultReg(RegClass);
1909  TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1910  return NewOp;
1911  }
1912  }
1913  return Op;
1914 }
1915 
1916 Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1917  const TargetRegisterClass *RC) {
1918  Register ResultReg = createResultReg(RC);
1919  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1920 
1921  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg);
1922  return ResultReg;
1923 }
1924 
1925 Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1926  const TargetRegisterClass *RC, unsigned Op0) {
1927  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1928 
1929  Register ResultReg = createResultReg(RC);
1930  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1931 
1932  if (II.getNumDefs() >= 1)
1933  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1934  .addReg(Op0);
1935  else {
1937  .addReg(Op0);
1939  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1940  }
1941 
1942  return ResultReg;
1943 }
1944 
1945 Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1946  const TargetRegisterClass *RC, unsigned Op0,
1947  unsigned Op1) {
1948  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1949 
1950  Register ResultReg = createResultReg(RC);
1951  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1952  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1953 
1954  if (II.getNumDefs() >= 1)
1955  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1956  .addReg(Op0)
1957  .addReg(Op1);
1958  else {
1960  .addReg(Op0)
1961  .addReg(Op1);
1963  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1964  }
1965  return ResultReg;
1966 }
1967 
1968 Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1969  const TargetRegisterClass *RC, unsigned Op0,
1970  unsigned Op1, unsigned Op2) {
1971  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1972 
1973  Register ResultReg = createResultReg(RC);
1974  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1975  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1976  Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1977 
1978  if (II.getNumDefs() >= 1)
1979  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1980  .addReg(Op0)
1981  .addReg(Op1)
1982  .addReg(Op2);
1983  else {
1985  .addReg(Op0)
1986  .addReg(Op1)
1987  .addReg(Op2);
1989  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1990  }
1991  return ResultReg;
1992 }
1993 
1994 Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1995  const TargetRegisterClass *RC, unsigned Op0,
1996  uint64_t Imm) {
1997  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1998 
1999  Register ResultReg = createResultReg(RC);
2000  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2001 
2002  if (II.getNumDefs() >= 1)
2003  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
2004  .addReg(Op0)
2005  .addImm(Imm);
2006  else {
2008  .addReg(Op0)
2009  .addImm(Imm);
2011  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2012  }
2013  return ResultReg;
2014 }
2015 
2016 Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
2017  const TargetRegisterClass *RC, unsigned Op0,
2018  uint64_t Imm1, uint64_t Imm2) {
2019  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2020 
2021  Register ResultReg = createResultReg(RC);
2022  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2023 
2024  if (II.getNumDefs() >= 1)
2025  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
2026  .addReg(Op0)
2027  .addImm(Imm1)
2028  .addImm(Imm2);
2029  else {
2031  .addReg(Op0)
2032  .addImm(Imm1)
2033  .addImm(Imm2);
2035  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2036  }
2037  return ResultReg;
2038 }
2039 
2040 Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
2041  const TargetRegisterClass *RC,
2042  const ConstantFP *FPImm) {
2043  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2044 
2045  Register ResultReg = createResultReg(RC);
2046 
2047  if (II.getNumDefs() >= 1)
2048  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
2049  .addFPImm(FPImm);
2050  else {
2052  .addFPImm(FPImm);
2054  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2055  }
2056  return ResultReg;
2057 }
2058 
2059 Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
2060  const TargetRegisterClass *RC, unsigned Op0,
2061  unsigned Op1, uint64_t Imm) {
2062  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2063 
2064  Register ResultReg = createResultReg(RC);
2065  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2066  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2067 
2068  if (II.getNumDefs() >= 1)
2069  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
2070  .addReg(Op0)
2071  .addReg(Op1)
2072  .addImm(Imm);
2073  else {
2075  .addReg(Op0)
2076  .addReg(Op1)
2077  .addImm(Imm);
2079  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2080  }
2081  return ResultReg;
2082 }
2083 
2084 Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
2085  const TargetRegisterClass *RC, uint64_t Imm) {
2086  Register ResultReg = createResultReg(RC);
2087  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2088 
2089  if (II.getNumDefs() >= 1)
2090  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
2091  .addImm(Imm);
2092  else {
2095  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2096  }
2097  return ResultReg;
2098 }
2099 
2101  uint32_t Idx) {
2102  Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2104  "Cannot yet extract from physregs");
2105  const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2107  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
2108  ResultReg).addReg(Op0, 0, Idx);
2109  return ResultReg;
2110 }
2111 
2112 /// Emit MachineInstrs to compute the value of Op with all but the least
2113 /// significant bit set to zero.
2115  return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
2116 }
2117 
2118 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
2119 /// Emit code to ensure constants are copied into registers when needed.
2120 /// Remember the virtual registers that need to be added to the Machine PHI
2121 /// nodes as input. We cannot just directly add them, because expansion
2122 /// might result in multiple MBB's for one BB. As such, the start of the
2123 /// BB might correspond to a different MBB than the end.
2124 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
2125  const Instruction *TI = LLVMBB->getTerminator();
2126 
2129 
2130  // Check successor nodes' PHI nodes that expect a constant to be available
2131  // from this block.
2132  for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2133  const BasicBlock *SuccBB = TI->getSuccessor(succ);
2134  if (!isa<PHINode>(SuccBB->begin()))
2135  continue;
2136  MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2137 
2138  // If this terminator has multiple identical successors (common for
2139  // switches), only handle each succ once.
2140  if (!SuccsHandled.insert(SuccMBB).second)
2141  continue;
2142 
2143  MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2144 
2145  // At this point we know that there is a 1-1 correspondence between LLVM PHI
2146  // nodes and Machine PHI nodes, but the incoming operands have not been
2147  // emitted yet.
2148  for (const PHINode &PN : SuccBB->phis()) {
2149  // Ignore dead phi's.
2150  if (PN.use_empty())
2151  continue;
2152 
2153  // Only handle legal types. Two interesting things to note here. First,
2154  // by bailing out early, we may leave behind some dead instructions,
2155  // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2156  // own moves. Second, this check is necessary because FastISel doesn't
2157  // use CreateRegs to create registers, so it always creates
2158  // exactly one register for each non-void instruction.
2159  EVT VT = TLI.getValueType(DL, PN.getType(), /*AllowUnknown=*/true);
2160  if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2161  // Handle integer promotions, though, because they're common and easy.
2162  if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2164  return false;
2165  }
2166  }
2167 
2168  const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
2169 
2170  // Set the DebugLoc for the copy. Use the location of the operand if
2171  // there is one; otherwise no location, flushLocalValueMap will fix it.
2172  MIMD = {};
2173  if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2174  MIMD = MIMetadata(*Inst);
2175 
2176  Register Reg = getRegForValue(PHIOp);
2177  if (!Reg) {
2179  return false;
2180  }
2181  FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
2182  MIMD = {};
2183  }
2184  }
2185 
2186  return true;
2187 }
2188 
2189 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2190  assert(LI->hasOneUse() &&
2191  "tryToFoldLoad expected a LoadInst with a single use");
2192  // We know that the load has a single use, but don't know what it is. If it
2193  // isn't one of the folded instructions, then we can't succeed here. Handle
2194  // this by scanning the single-use users of the load until we get to FoldInst.
2195  unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2196 
2197  const Instruction *TheUser = LI->user_back();
2198  while (TheUser != FoldInst && // Scan up until we find FoldInst.
2199  // Stay in the right block.
2200  TheUser->getParent() == FoldInst->getParent() &&
2201  --MaxUsers) { // Don't scan too far.
2202  // If there are multiple or no uses of this instruction, then bail out.
2203  if (!TheUser->hasOneUse())
2204  return false;
2205 
2206  TheUser = TheUser->user_back();
2207  }
2208 
2209  // If we didn't find the fold instruction, then we failed to collapse the
2210  // sequence.
2211  if (TheUser != FoldInst)
2212  return false;
2213 
2214  // Don't try to fold volatile loads. Target has to deal with alignment
2215  // constraints.
2216  if (LI->isVolatile())
2217  return false;
2218 
2219  // Figure out which vreg this is going into. If there is no assigned vreg yet
2220  // then there actually was no reference to it. Perhaps the load is referenced
2221  // by a dead instruction.
2222  Register LoadReg = getRegForValue(LI);
2223  if (!LoadReg)
2224  return false;
2225 
2226  // We can't fold if this vreg has no uses or more than one use. Multiple uses
2227  // may mean that the instruction got lowered to multiple MIs, or the use of
2228  // the loaded value ended up being multiple operands of the result.
2229  if (!MRI.hasOneUse(LoadReg))
2230  return false;
2231 
2232  // If the register has fixups, there may be additional uses through a
2233  // different alias of the register.
2234  if (FuncInfo.RegsWithFixups.contains(LoadReg))
2235  return false;
2236 
2238  MachineInstr *User = RI->getParent();
2239 
2240  // Set the insertion point properly. Folding the load can cause generation of
2241  // other random instructions (like sign extends) for addressing modes; make
2242  // sure they get inserted in a logical place before the new instruction.
2244  FuncInfo.MBB = User->getParent();
2245 
2246  // Ask the target to try folding the load.
2247  return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2248 }
2249 
2250 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2251  // Must be an add.
2252  if (!isa<AddOperator>(Add))
2253  return false;
2254  // Type size needs to match.
2255  if (DL.getTypeSizeInBits(GEP->getType()) !=
2256  DL.getTypeSizeInBits(Add->getType()))
2257  return false;
2258  // Must be in the same basic block.
2259  if (isa<Instruction>(Add) &&
2260  FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2261  return false;
2262  // Must have a constant operand.
2263  return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2264 }
2265 
2268  const Value *Ptr;
2269  Type *ValTy;
2270  MaybeAlign Alignment;
2272  bool IsVolatile;
2273 
2274  if (const auto *LI = dyn_cast<LoadInst>(I)) {
2275  Alignment = LI->getAlign();
2276  IsVolatile = LI->isVolatile();
2277  Flags = MachineMemOperand::MOLoad;
2278  Ptr = LI->getPointerOperand();
2279  ValTy = LI->getType();
2280  } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2281  Alignment = SI->getAlign();
2282  IsVolatile = SI->isVolatile();
2284  Ptr = SI->getPointerOperand();
2285  ValTy = SI->getValueOperand()->getType();
2286  } else
2287  return nullptr;
2288 
2289  bool IsNonTemporal = I->hasMetadata(LLVMContext::MD_nontemporal);
2290  bool IsInvariant = I->hasMetadata(LLVMContext::MD_invariant_load);
2291  bool IsDereferenceable = I->hasMetadata(LLVMContext::MD_dereferenceable);
2292  const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2293 
2294  AAMDNodes AAInfo = I->getAAMetadata();
2295 
2296  if (!Alignment) // Ensure that codegen never sees alignment 0.
2297  Alignment = DL.getABITypeAlign(ValTy);
2298 
2299  unsigned Size = DL.getTypeStoreSize(ValTy);
2300 
2301  if (IsVolatile)
2303  if (IsNonTemporal)
2305  if (IsDereferenceable)
2307  if (IsInvariant)
2309 
2310  return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2311  *Alignment, AAInfo, Ranges);
2312 }
2313 
2315  // If both operands are the same, then try to optimize or fold the cmp.
2317  if (CI->getOperand(0) != CI->getOperand(1))
2318  return Predicate;
2319 
2320  switch (Predicate) {
2321  default: llvm_unreachable("Invalid predicate!");
2338 
2349  }
2350 
2351  return Predicate;
2352 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1492
llvm::FunctionLoweringInfo::Fn
const Function * Fn
Definition: FunctionLoweringInfo.h:54
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:637
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:245
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:734
ValueTypes.h
llvm::DbgVariableIntrinsic::getExpression
DIExpression * getExpression() const
Definition: IntrinsicInst.h:291
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:136
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2043
llvm::Instruction::getNumSuccessors
unsigned getNumSuccessors() const LLVM_READONLY
Return the number of successors that this instruction has.
Definition: Instruction.cpp:807
llvm::CallingConv::AnyReg
@ AnyReg
Used for dynamic register based calls (e.g.
Definition: CallingConv.h:60
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::FastISel::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: FastISel.h:85
llvm::DbgDeclareInst::getAddress
Value * getAddress() const
Definition: IntrinsicInst.h:350
llvm::FastISel::lowerCallTo
bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)
Definition: FastISel.cpp:964
llvm::FastISel::selectPatchpoint
bool selectPatchpoint(const CallInst *I)
Definition: FastISel.cpp:762
llvm::FastISel::CallLoweringInfo::OutFlags
SmallVector< ISD::ArgFlagsTy, 16 > OutFlags
Definition: FastISel.h:95
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::ISD::PATCHPOINT
@ PATCHPOINT
Definition: ISDOpcodes.h:1299
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:740
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:141
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
Optional.h
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:667
llvm::FastISel::getRegForValue
Register getRegForValue(const Value *V)
Create a virtual register and arrange for it to be assigned the value for the given LLVM value.
Definition: FastISel.cpp:238
llvm::FastISel::~FastISel
virtual ~FastISel()
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::generic_gep_type_iterator
Definition: GetElementPtrTypeIterator.h:31
llvm::FastISel::fastEmit_f
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1846
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:886
Metadata.h
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
IntrinsicInst.h
llvm::FastISel::selectCast
bool selectCast(const User *I, unsigned Opcode)
Definition: FastISel.cpp:1376
MCInstrDesc.h
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:243
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:53
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:673
llvm::FastISel::updateValueMap
void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)
Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...
Definition: FastISel.cpp:362
llvm::FunctionLoweringInfo::InsertPt
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
Definition: FunctionLoweringInfo.h:156
GetElementPtrTypeIterator.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::FastISel::fastEmit_ri_
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, MVT ImmType)
This method is a wrapper of fastEmit_ri.
Definition: FastISel.cpp:1860
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::FastISel::fastEmitInst_f
Register fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm)
Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...
Definition: FastISel.cpp:2040
Statistic.h
InlineAsm.h
llvm::FastISel::CallLoweringInfo::setIsPatchPoint
CallLoweringInfo & setIsPatchPoint(bool Value=true)
Definition: FastISel.h:182
llvm::FastISel::FastISel
FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)
Definition: FastISel.cpp:1810
llvm::FastISel::CallLoweringInfo::ResultReg
Register ResultReg
Definition: FastISel.h:91
llvm::FastISel::CallLoweringInfo::InRegs
SmallVector< Register, 4 > InRegs
Definition: FastISel.h:98
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::FastISel::finishBasicBlock
void finishBasicBlock()
Flush the local value map.
Definition: FastISel.cpp:136
llvm::FunctionLoweringInfo::RegsWithFixups
DenseSet< Register > RegsWithFixups
Definition: FunctionLoweringInfo.h:144
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:727
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:474
ErrorHandling.h
llvm::FastISel::lowerArguments
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
Definition: FastISel.cpp:138
llvm::FastISel::fastEmitZExtFromI1
Register fastEmitZExtFromI1(MVT VT, unsigned Op0)
Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.
Definition: FastISel.cpp:2114
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ISD::InputArg::Used
bool Used
Definition: TargetCallingConv.h:199
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:1033
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition: InstrTypes.h:741
llvm::FastISel::selectFreeze
bool selectFreeze(const User *I)
Definition: FastISel.cpp:1436
llvm::AttributeList::get
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute >> Attrs)
Create an AttributeList with the specified parameters in it.
Definition: Attributes.cpp:1132
llvm::FastISel::enterLocalValueArea
SavePoint enterLocalValueArea()
Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...
Definition: FastISel.cpp:435
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:819
NewExpr
Definition: ItaniumDemangle.h:1935
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:746
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::FastISel::CallLoweringInfo::OutVals
SmallVector< Value *, 16 > OutVals
Definition: FastISel.h:94
llvm::DenseMapIterator
Definition: DenseMap.h:57
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
DenseMap.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::FunctionLoweringInfo::MBB
MachineBasicBlock * MBB
MBB - The current block.
Definition: FunctionLoweringInfo.h:153
llvm::diagnoseDontCall
void diagnoseDontCall(const CallInst &CI)
Definition: DiagnosticInfo.cpp:418
llvm::AttributeList
Definition: Attributes.h:430
llvm::FastISel::fastEmitInst_rii
Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2)
Emit a MachineInstr with one register operand and two immediate operands.
Definition: FastISel.cpp:2016
TargetInstrInfo.h
llvm::FastISel::fastEmit_rr
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1837
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1254
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::FastISel::CallLoweringInfo::RetSExt
bool RetSExt
Definition: FastISel.h:72
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ComputeLinearIndex
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
Definition: Analysis.cpp:33
llvm::DbgVariableIntrinsic::getVariable
DILocalVariable * getVariable() const
Definition: IntrinsicInst.h:287
llvm::Optional
Definition: APInt.h:33
llvm::FastISel::TLI
const TargetLowering & TLI
Definition: FastISel.h:212
llvm::LLVMContext::OB_funclet
@ OB_funclet
Definition: LLVMContext.h:90
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:636
Operator.h
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:749
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1316
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:723
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::FastISel::getRegForGEPIndex
Register getRegForGEPIndex(const Value *Idx)
This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...
Definition: FastISel.cpp:383
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1086
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::FastISel::CallLoweringInfo::RetZExt
bool RetZExt
Definition: FastISel.h:73
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:121
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:130
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
MachineValueType.h
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:733
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFrameInfo::setHasStackMap
void setHasStackMap(bool s=true)
Definition: MachineFrameInfo.h:384
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
Instruction.h
llvm::MachineBasicBlock::reverse_iterator
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
Definition: MachineBasicBlock.h:271
llvm::ISD::InputArg::ArgVT
EVT ArgVT
Definition: TargetCallingConv.h:198
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:46
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
llvm::Log2_64
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:553
GlobalValue.h
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:492
llvm::FastISel::FuncInfo
FunctionLoweringInfo & FuncInfo
Definition: FastISel.h:203
Constants.h
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:76
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:763
llvm::FunctionLoweringInfo::MBBMap
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
Definition: FunctionLoweringInfo.h:72
llvm::DbgValueInst
This represents the llvm.dbg.value instruction.
Definition: IntrinsicInst.h:387
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
SmallString.h
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::FastISel::createResultReg
Register createResultReg(const TargetRegisterClass *RC)
Definition: FastISel.cpp:1895
llvm::User
Definition: User.h:44
llvm::LibFunc
LibFunc
Definition: TargetLibraryInfo.h:35
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FastISel::CallLoweringInfo::clearIns
void clearIns()
Definition: FastISel.h:195
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:745
InstrTypes.h
llvm::BasicBlock::begin
iterator begin()
Instruction iterator methods.
Definition: BasicBlock.h:306
MCContext.h
llvm::FastISel::CallLoweringInfo::CB
const CallBase * CB
Definition: FastISel.h:89
llvm::PatchPointOpers::TargetPos
@ TargetPos
Definition: StackMaps.h:79
llvm::FastISel::leaveLocalValueArea
void leaveLocalValueArea(SavePoint Old)
Reset InsertPt to the given old insert position.
Definition: FastISel.cpp:441
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:732
llvm::FastISel::selectXRayTypedEvent
bool selectXRayTypedEvent(const CallInst *II)
Definition: FastISel.cpp:919
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:769
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:692
TargetLibraryInfo.h
addStackMapLiveVars
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
Definition: SelectionDAGBuilder.cpp:9486
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::Mangler::getNameWithPrefix
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
Definition: Mangler.cpp:119
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::FastISel::fastEmit_
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)
This method is called by target-independent code to request that an instruction with the given type a...
Definition: FastISel.cpp:1831
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:729
llvm::Instruction
Definition: Instruction.h:42
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:829
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:773
llvm::APSInt
An arbitrary precision integer that knows its signedness.
Definition: APSInt.h:23
llvm::BasicBlock::phis
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
Definition: BasicBlock.h:364
llvm::FastISel::selectStackmap
bool selectStackmap(const CallInst *I)
Definition: FastISel.cpp:650
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
isCommutative
static bool isCommutative(Instruction *I)
Definition: SLPVectorizer.cpp:276
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:626
APFloat.h
llvm::FastISel::fastEmit_ri
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1851
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:832
llvm::FastISel::CallLoweringInfo::IsInReg
bool IsInReg
Definition: FastISel.h:75
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:879
llvm::DILocalVariable::isValidLocationForIntrinsic
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Definition: DebugInfoMetadata.h:3175
llvm::FastISel::CallLoweringInfo::clearOuts
void clearOuts()
Definition: FastISel.h:189
llvm::AArch64PACKey::IA
@ IA
Definition: AArch64BaseInfo.h:819
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:722
DebugLoc.h
SmallPtrSet.h
llvm::DbgVariableIntrinsic::hasArgList
bool hasArgList() const
Definition: IntrinsicInst.h:259
llvm::FastISel::MRI
MachineRegisterInfo & MRI
Definition: FastISel.h:205
llvm::FastISel::CallLoweringInfo::Call
MachineInstr * Call
Definition: FastISel.h:90
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:725
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:666
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:80
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
PatternMatch.h
llvm::CallInst::isTailCall
bool isTailCall() const
Definition: Instructions.h:1667
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:155
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:354
Flt
@ Flt
Definition: TargetLibraryInfo.cpp:56
llvm::CallBase::getCallingConv
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1455
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:237
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:272
llvm::FastISel::createMachineMemOperandFor
MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const
Create a machine mem operand from the given instruction.
Definition: FastISel.cpp:2267
llvm::FunctionLoweringInfo::OrigNumPHINodesToUpdate
unsigned OrigNumPHINodesToUpdate
Definition: FunctionLoweringInfo.h:179
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:271
llvm::SmallString< 32 >
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:77
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:721
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:647
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:709
llvm::FastISel::fastLowerIntrinsicCall
virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)
This method is called by target-independent code to do target- specific intrinsic lowering.
Definition: FastISel.cpp:1827
llvm::MIMetadata
Set of metadata that should be preserved when using BuildMI().
Definition: MachineInstrBuilder.h:335
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
llvm::InlineAsm
Definition: InlineAsm.h:33
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
BasicBlock.h
llvm::APFloat
Definition: APFloat.h:716
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:433
llvm::FastISel::CallLoweringInfo::NumResultRegs
unsigned NumResultRegs
Definition: FastISel.h:92
llvm::FastISel::selectInstruction
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
Definition: FastISel.cpp:1476
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
VI
@ VI
Definition: SIInstrInfo.cpp:7883
llvm::Instruction::getSuccessor
BasicBlock * getSuccessor(unsigned Idx) const LLVM_READONLY
Return the specified successor. This instruction must be a terminator.
Definition: Instruction.cpp:819
BranchProbabilityInfo.h
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::FastISel::tryToFoldLoadIntoMI
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Definition: FastISel.h:301
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:939
llvm::DbgDeclareInst
This represents the llvm.dbg.declare instruction.
Definition: IntrinsicInst.h:348
llvm::DbgLabelInst
This represents the llvm.dbg.label instruction.
Definition: IntrinsicInst.h:455
llvm::Instruction::user_back
Instruction * user_back()
Specialize the methods defined in Value, as we know that an instruction can only be used by other ins...
Definition: Instruction.h:88
llvm::FastISel::fastLowerCall
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
Definition: FastISel.cpp:1825
llvm::FastISel::fastEmit_i
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1842
llvm::FastISel::fastEmitBranch
void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)
Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...
Definition: FastISel.cpp:1560
llvm::DbgLabelInst::getLabel
DILabel * getLabel() const
Definition: IntrinsicInst.h:457
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::FastISel::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: FastISel.h:187
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::FastISel::selectIntrinsicCall
bool selectIntrinsicCall(const IntrinsicInst *II)
Definition: FastISel.cpp:1192
findLocalRegDef
static Register findLocalRegDef(MachineInstr &MI)
Return the defined register if this instruction defines exactly one virtual register and uses no othe...
Definition: FastISel.cpp:160
llvm::FastISel::fastEmitInst_rri
Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm)
Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...
Definition: FastISel.cpp:2059
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:579
I
#define I(x, y, z)
Definition: MD5.cpp:58
Analysis.h
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:716
llvm::FastISel::CallLoweringInfo::IsReturnValueUsed
bool IsReturnValueUsed
Definition: FastISel.h:77
llvm::FastISel::CallLoweringInfo
Definition: FastISel.h:70
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:195
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:46
llvm::FastISel::fastEmit_r
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1833
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2802
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:894
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:284
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:724
llvm::ISD::STACKMAP
@ STACKMAP
Definition: ISDOpcodes.h:1293
llvm::FastISel::fastEmitInst_
Register fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC)
Emit a MachineInstr with no operands and a result register in the given register class.
Definition: FastISel.cpp:1916
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition: InstrTypes.h:743
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::FastISel::fastLowerArguments
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
Definition: FastISel.cpp:1823
APSInt.h
llvm::FastISel::ArgListTy
TargetLoweringBase::ArgListTy ArgListTy
Definition: FastISel.h:69
MachineModuleInfo.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1322
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::BranchInst::isUnconditional
bool isUnconditional() const
Definition: Instructions.h:3211
getType
static M68kRelType getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel)
Definition: M68kELFObjectWriter.cpp:48
Mangler.h
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:748
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:574
llvm::FastISel::selectOperator
bool selectOperator(const User *I, unsigned Opcode)
Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...
Definition: FastISel.cpp:1681
llvm::FastISel::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: FastISel.h:74
TargetOptions.h
llvm::PatchPointOpers::NBytesPos
@ NBytesPos
Definition: StackMaps.h:79
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:269
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:70
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:859
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:49
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:213
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition: InstrTypes.h:744
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::FastISel::canFoldAddIntoGEP
bool canFoldAddIntoGEP(const User *GEP, const Value *Add)
Check if Add is an add that can be safely folded into GEP.
Definition: FastISel.cpp:2250
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:244
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::Value::getContext
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:994
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:230
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::CallInst::isMustTailCall
bool isMustTailCall() const
Definition: Instructions.h:1672
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:235
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
isRegUsedByPhiNodes
static bool isRegUsedByPhiNodes(Register DefReg, FunctionLoweringInfo &FuncInfo)
Definition: FastISel.cpp:177
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:392
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::ISD::InputArg::Flags
ArgFlagsTy Flags
Definition: TargetCallingConv.h:196
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::FastISel::fastEmitInst_ri
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:1994
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:668
Argument.h
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:731
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:289
Constant.h
llvm::FastISel::tryToFoldLoad
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
Definition: FastISel.cpp:2189
llvm::APFloatBase::rmTowardZero
static constexpr roundingMode rmTowardZero
Definition: APFloat.h:204
llvm::Constant::getNullValue
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:350
llvm::FastISel::lowerCall
bool lowerCall(const CallInst *I)
Definition: FastISel.cpp:1114
llvm::FastISel::selectExtractValue
bool selectExtractValue(const User *U)
Definition: FastISel.cpp:1641
getReturnAttrs
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
Definition: FastISel.cpp:942
llvm::FastISel::CallLoweringInfo::OutRegs
SmallVector< Register, 16 > OutRegs
Definition: FastISel.h:96
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
MachineFrameInfo.h
llvm::FastISel::selectFNeg
bool selectFNeg(const User *I, const Value *In)
Emit an FNeg operation.
Definition: FastISel.cpp:1599
llvm::Type::isEmptyTy
bool isEmptyTy() const
Return true if this type is empty, that is, it has no elements or all of its elements are empty.
Definition: Type.cpp:147
llvm::CallBase::arg_size
unsigned arg_size() const
Definition: InstrTypes.h:1339
llvm::ExtractValueInst
This instruction extracts a struct member or array element value from an aggregate value.
Definition: Instructions.h:2445
ISDOpcodes.h
Casting.h
DiagnosticInfo.h
Function.h
llvm::DIExpression::constantFold
std::pair< DIExpression *, const ConstantInt * > constantFold(const ConstantInt *CI)
Try to shorten an expression with an initial constant operand.
Definition: DebugInfoMetadata.cpp:1707
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:225
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:242
llvm::FastISel::CallLoweringInfo::RetTy
Type * RetTy
Definition: FastISel.h:71
StackMaps.h
llvm::FastISel::selectXRayCustomEvent
bool selectXRayCustomEvent(const CallInst *II)
Definition: FastISel.cpp:900
llvm::ISD::InputArg::VT
MVT VT
Definition: TargetCallingConv.h:197
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:747
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:185
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1389
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:222
FastISel.h
llvm::FastISel::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 4 > Ins
Definition: FastISel.h:97
llvm::FastISel::selectGetElementPtr
bool selectGetElementPtr(const User *I)
Definition: FastISel.cpp:537
Instructions.h
llvm::FunctionLoweringInfo::MF
MachineFunction * MF
Definition: FunctionLoweringInfo.h:55
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:391
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1669
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:691
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:210
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:518
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:394
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:895
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
llvm::Instruction::getDebugLoc
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:354
User.h
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:241
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:245
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:742
llvm::DbgValueInst::getValue
Value * getValue(unsigned OpIdx=0) const
Definition: IntrinsicInst.h:391
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:735
llvm::CallBase::getArgOperand
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1341
N
#define N
llvm::FastISel::fastEmitInst_rrr
Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2)
Emit a MachineInstr with three register operands and a result register in the given register class.
Definition: FastISel.cpp:1968
llvm::Instruction::getParent
const BasicBlock * getParent() const
Definition: Instruction.h:91
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:693
llvm::PatchPointOpers::NArgPos
@ NArgPos
Definition: StackMaps.h:79
llvm::FastISel::removeDeadCode
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
Definition: FastISel.cpp:415
llvm::CmpInst::getPredicate
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:809
llvm::FastISel::CallLoweringInfo::setTailCall
CallLoweringInfo & setTailCall(bool Value=true)
Definition: FastISel.h:177
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:896
llvm::isInTailCallPosition
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:522
llvm::PHINode
Definition: Instructions.h:2698
llvm::BasicBlock::getTerminator
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.h:119
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:82
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:274
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:236
MachineMemOperand.h
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:726
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::sys::path::rend
reverse_iterator rend(StringRef path)
Get reverse end iterator over path.
Definition: Path.cpp:306
llvm::PatchPointOpers::IDPos
@ IDPos
Definition: StackMaps.h:79
MachineOperand.h
DerivedTypes.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:256
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:47
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:311
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1473
llvm::FastISel::TRI
const TargetRegisterInfo & TRI
Definition: FastISel.h:213
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:911
llvm::FastISel::selectCall
bool selectCall(const User *I)
Definition: FastISel.cpp:1155
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::FunctionLoweringInfo::PHINodesToUpdate
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
Definition: FunctionLoweringInfo.h:178
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
LLVMContext.h
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:231
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
selectBinaryOp
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV),...
Definition: AArch64InstructionSelector.cpp:750
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::FastISel::optimizeCmpPredicate
CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const
Definition: FastISel.cpp:2314
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)
Definition: FastISel.h:104
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1493
llvm::FastISel::selectBitCast
bool selectBitCast(const User *I)
Definition: FastISel.cpp:1407
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3133
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
raw_ostream.h
llvm::FastISel::TII
const TargetInstrInfo & TII
Definition: FastISel.h:211
llvm::FastISel::fastEmitInst_extractsubreg
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx)
Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...
Definition: FastISel.cpp:2100
llvm::FastISel::lookUpRegForValue
Register lookUpRegForValue(const Value *V)
Look up the value to see if its value is already cached in a register.
Definition: FastISel.cpp:351
llvm::FastISel::finishCondBranch
void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)
Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...
Definition: FastISel.cpp:1580
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:736
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:692
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:463
Value.h
llvm::FastISel::fastEmitInst_rr
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:1945
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::ExtractValueInst::getIndices
ArrayRef< unsigned > getIndices() const
Definition: Instructions.h:2510
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::FastISel::DL
const DataLayout & DL
Definition: FastISel.h:210
llvm::FastISel::selectBinaryOp
bool selectBinaryOp(const User *I, unsigned ISDOpcode)
Select and emit code for a binary operator instruction, which has an opcode which directly correspond...
Definition: FastISel.cpp:449
Debug.h
llvm::FastISel::MIMD
MIMetadata MIMD
Definition: FastISel.h:208
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:483
llvm::FastISel::recomputeInsertPt
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
Definition: FastISel.cpp:401
llvm::FastISel::startNewBlock
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
Definition: FastISel.cpp:123
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:728
llvm::BranchInst::getSuccessor
BasicBlock * getSuccessor(unsigned i) const
Definition: Instructions.h:3226
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:74
llvm::FastISel::constrainOperandRegClass
Register constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum)
Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.
Definition: FastISel.cpp:1899
llvm::FastISel::fastEmitInst_r
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:1925
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:232
llvm::FastISel::fastEmitInst_i
Register fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm)
Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...
Definition: FastISel.cpp:2084
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:730
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:103
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:207
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:393