LLVM  13.0.0git
FastISel.cpp
Go to the documentation of this file.
1 //===- FastISel.cpp - Implementation of the FastISel class ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the implementation of the FastISel class.
10 //
11 // "Fast" instruction selection is designed to emit very poor code quickly.
12 // Also, it is not designed to be able to do much lowering, so most illegal
13 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
14 // also not intended to be able to do much optimization, except in a few cases
15 // where doing optimizations reduces overall compile time. For example, folding
16 // constants into immediate fields is often done, because it's cheap and it
17 // reduces the number of instructions later phases have to examine.
18 //
19 // "Fast" instruction selection is able to fail gracefully and transfer
20 // control to the SelectionDAG selector for operations that it doesn't
21 // support. In many cases, this allows us to avoid duplicating a lot of
22 // the complicated lowering logic that SelectionDAG currently has.
23 //
24 // The intended use for "fast" instruction selection is "-O0" mode
25 // compilation, where the quality of the generated code is irrelevant when
26 // weighed against the speed at which the code can be generated. Also,
27 // at -O0, the LLVM optimizers are not running, and this makes the
28 // compile time of codegen a much higher portion of the overall compile
29 // time. Despite its limitations, "fast" instruction selection is able to
30 // handle enough code on its own to provide noticeable overall speedups
31 // in -O0 compiles.
32 //
33 // Basic operations are supported in a target-independent way, by reading
34 // the same instruction descriptions that the SelectionDAG selector reads,
35 // and identifying simple arithmetic operations that can be directly selected
36 // from simple operators. More complicated operations currently require
37 // target-specific code.
38 //
39 //===----------------------------------------------------------------------===//
40 
41 #include "llvm/CodeGen/FastISel.h"
42 #include "llvm/ADT/APFloat.h"
43 #include "llvm/ADT/APSInt.h"
44 #include "llvm/ADT/DenseMap.h"
45 #include "llvm/ADT/Optional.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/SmallVector.h"
49 #include "llvm/ADT/Statistic.h"
52 #include "llvm/CodeGen/Analysis.h"
63 #include "llvm/CodeGen/StackMaps.h"
68 #include "llvm/IR/Argument.h"
69 #include "llvm/IR/Attributes.h"
70 #include "llvm/IR/BasicBlock.h"
71 #include "llvm/IR/CallingConv.h"
72 #include "llvm/IR/Constant.h"
73 #include "llvm/IR/Constants.h"
74 #include "llvm/IR/DataLayout.h"
75 #include "llvm/IR/DebugInfo.h"
76 #include "llvm/IR/DebugLoc.h"
77 #include "llvm/IR/DerivedTypes.h"
78 #include "llvm/IR/Function.h"
80 #include "llvm/IR/GlobalValue.h"
81 #include "llvm/IR/InlineAsm.h"
82 #include "llvm/IR/InstrTypes.h"
83 #include "llvm/IR/Instruction.h"
84 #include "llvm/IR/Instructions.h"
85 #include "llvm/IR/IntrinsicInst.h"
86 #include "llvm/IR/LLVMContext.h"
87 #include "llvm/IR/Mangler.h"
88 #include "llvm/IR/Metadata.h"
89 #include "llvm/IR/Operator.h"
90 #include "llvm/IR/PatternMatch.h"
91 #include "llvm/IR/Type.h"
92 #include "llvm/IR/User.h"
93 #include "llvm/IR/Value.h"
94 #include "llvm/MC/MCContext.h"
95 #include "llvm/MC/MCInstrDesc.h"
96 #include "llvm/MC/MCRegisterInfo.h"
97 #include "llvm/Support/Casting.h"
98 #include "llvm/Support/Debug.h"
101 #include "llvm/Support/MathExtras.h"
105 #include <algorithm>
106 #include <cassert>
107 #include <cstdint>
108 #include <iterator>
109 #include <utility>
110 
111 using namespace llvm;
112 using namespace PatternMatch;
113 
114 #define DEBUG_TYPE "isel"
115 
116 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
117  "target-independent selector");
118 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
119  "target-specific selector");
120 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
121 
122 /// Set the current block to which generated machine instructions will be
123 /// appended.
125  assert(LocalValueMap.empty() &&
126  "local values should be cleared after finishing a BB");
127 
128  // Instructions are appended to FuncInfo.MBB. If the basic block already
129  // contains labels or copies, use the last instruction as the last local
130  // value.
131  EmitStartPt = nullptr;
132  if (!FuncInfo.MBB->empty())
133  EmitStartPt = &FuncInfo.MBB->back();
134  LastLocalValue = EmitStartPt;
135 }
136 
137 void FastISel::finishBasicBlock() { flushLocalValueMap(); }
138 
140  if (!FuncInfo.CanLowerReturn)
141  // Fallback to SDISel argument lowering code to deal with sret pointer
142  // parameter.
143  return false;
144 
145  if (!fastLowerArguments())
146  return false;
147 
148  // Enter arguments into ValueMap for uses in non-entry BBs.
149  for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
150  E = FuncInfo.Fn->arg_end();
151  I != E; ++I) {
152  DenseMap<const Value *, Register>::iterator VI = LocalValueMap.find(&*I);
153  assert(VI != LocalValueMap.end() && "Missed an argument?");
154  FuncInfo.ValueMap[&*I] = VI->second;
155  }
156  return true;
157 }
158 
159 /// Return the defined register if this instruction defines exactly one
160 /// virtual register and uses no other virtual registers. Otherwise return 0.
162  Register RegDef;
163  for (const MachineOperand &MO : MI.operands()) {
164  if (!MO.isReg())
165  continue;
166  if (MO.isDef()) {
167  if (RegDef)
168  return Register();
169  RegDef = MO.getReg();
170  } else if (MO.getReg().isVirtual()) {
171  // This is another use of a vreg. Don't delete it.
172  return Register();
173  }
174  }
175  return RegDef;
176 }
177 
178 static bool isRegUsedByPhiNodes(Register DefReg,
179  FunctionLoweringInfo &FuncInfo) {
180  for (auto &P : FuncInfo.PHINodesToUpdate)
181  if (P.second == DefReg)
182  return true;
183  return false;
184 }
185 
186 void FastISel::flushLocalValueMap() {
187  // If FastISel bails out, it could leave local value instructions behind
188  // that aren't used for anything. Detect and erase those.
189  if (LastLocalValue != EmitStartPt) {
190  // Save the first instruction after local values, for later.
191  MachineBasicBlock::iterator FirstNonValue(LastLocalValue);
192  ++FirstNonValue;
193 
195  EmitStartPt ? MachineBasicBlock::reverse_iterator(EmitStartPt)
196  : FuncInfo.MBB->rend();
197  MachineBasicBlock::reverse_iterator RI(LastLocalValue);
198  for (; RI != RE;) {
199  MachineInstr &LocalMI = *RI;
200  // Increment before erasing what it points to.
201  ++RI;
202  Register DefReg = findLocalRegDef(LocalMI);
203  if (!DefReg)
204  continue;
205  if (FuncInfo.RegsWithFixups.count(DefReg))
206  continue;
207  bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo);
208  if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) {
209  if (EmitStartPt == &LocalMI)
210  EmitStartPt = EmitStartPt->getPrevNode();
211  LLVM_DEBUG(dbgs() << "removing dead local value materialization"
212  << LocalMI);
213  LocalMI.eraseFromParent();
214  }
215  }
216 
217  if (FirstNonValue != FuncInfo.MBB->end()) {
218  // See if there are any local value instructions left. If so, we want to
219  // make sure the first one has a debug location; if it doesn't, use the
220  // first non-value instruction's debug location.
221 
222  // If EmitStartPt is non-null, this block had copies at the top before
223  // FastISel started doing anything; it points to the last one, so the
224  // first local value instruction is the one after EmitStartPt.
225  // If EmitStartPt is null, the first local value instruction is at the
226  // top of the block.
227  MachineBasicBlock::iterator FirstLocalValue =
228  EmitStartPt ? ++MachineBasicBlock::iterator(EmitStartPt)
229  : FuncInfo.MBB->begin();
230  if (FirstLocalValue != FirstNonValue && !FirstLocalValue->getDebugLoc())
231  FirstLocalValue->setDebugLoc(FirstNonValue->getDebugLoc());
232  }
233  }
234 
235  LocalValueMap.clear();
236  LastLocalValue = EmitStartPt;
237  recomputeInsertPt();
238  SavedInsertPt = FuncInfo.InsertPt;
239 }
240 
242  EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
243  // Don't handle non-simple values in FastISel.
244  if (!RealVT.isSimple())
245  return Register();
246 
247  // Ignore illegal types. We must do this before looking up the value
248  // in ValueMap because Arguments are given virtual registers regardless
249  // of whether FastISel can handle them.
250  MVT VT = RealVT.getSimpleVT();
251  if (!TLI.isTypeLegal(VT)) {
252  // Handle integer promotions, though, because they're common and easy.
253  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
254  VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
255  else
256  return Register();
257  }
258 
259  // Look up the value to see if we already have a register for it.
260  Register Reg = lookUpRegForValue(V);
261  if (Reg)
262  return Reg;
263 
264  // In bottom-up mode, just create the virtual register which will be used
265  // to hold the value. It will be materialized later.
266  if (isa<Instruction>(V) &&
267  (!isa<AllocaInst>(V) ||
268  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
269  return FuncInfo.InitializeRegForValue(V);
270 
271  SavePoint SaveInsertPt = enterLocalValueArea();
272 
273  // Materialize the value in a register. Emit any instructions in the
274  // local value area.
275  Reg = materializeRegForValue(V, VT);
276 
277  leaveLocalValueArea(SaveInsertPt);
278 
279  return Reg;
280 }
281 
282 Register FastISel::materializeConstant(const Value *V, MVT VT) {
283  Register Reg;
284  if (const auto *CI = dyn_cast<ConstantInt>(V)) {
285  if (CI->getValue().getActiveBits() <= 64)
286  Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
287  } else if (isa<AllocaInst>(V))
288  Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
289  else if (isa<ConstantPointerNull>(V))
290  // Translate this as an integer zero so that it can be
291  // local-CSE'd with actual integer zeros.
292  Reg =
293  getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getType())));
294  else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
295  if (CF->isNullValue())
296  Reg = fastMaterializeFloatZero(CF);
297  else
298  // Try to emit the constant directly.
299  Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
300 
301  if (!Reg) {
302  // Try to emit the constant by using an integer constant with a cast.
303  const APFloat &Flt = CF->getValueAPF();
304  EVT IntVT = TLI.getPointerTy(DL);
305  uint32_t IntBitWidth = IntVT.getSizeInBits();
306  APSInt SIntVal(IntBitWidth, /*isUnsigned=*/false);
307  bool isExact;
308  (void)Flt.convertToInteger(SIntVal, APFloat::rmTowardZero, &isExact);
309  if (isExact) {
310  Register IntegerReg =
311  getRegForValue(ConstantInt::get(V->getContext(), SIntVal));
312  if (IntegerReg)
313  Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
314  IntegerReg);
315  }
316  }
317  } else if (const auto *Op = dyn_cast<Operator>(V)) {
318  if (!selectOperator(Op, Op->getOpcode()))
319  if (!isa<Instruction>(Op) ||
320  !fastSelectInstruction(cast<Instruction>(Op)))
321  return 0;
322  Reg = lookUpRegForValue(Op);
323  } else if (isa<UndefValue>(V)) {
324  Reg = createResultReg(TLI.getRegClassFor(VT));
325  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
326  TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
327  }
328  return Reg;
329 }
330 
331 /// Helper for getRegForValue. This function is called when the value isn't
332 /// already available in a register and must be materialized with new
333 /// instructions.
334 Register FastISel::materializeRegForValue(const Value *V, MVT VT) {
335  Register Reg;
336  // Give the target-specific code a try first.
337  if (isa<Constant>(V))
338  Reg = fastMaterializeConstant(cast<Constant>(V));
339 
340  // If target-specific code couldn't or didn't want to handle the value, then
341  // give target-independent code a try.
342  if (!Reg)
343  Reg = materializeConstant(V, VT);
344 
345  // Don't cache constant materializations in the general ValueMap.
346  // To do so would require tracking what uses they dominate.
347  if (Reg) {
348  LocalValueMap[V] = Reg;
349  LastLocalValue = MRI.getVRegDef(Reg);
350  }
351  return Reg;
352 }
353 
355  // Look up the value to see if we already have a register for it. We
356  // cache values defined by Instructions across blocks, and other values
357  // only locally. This is because Instructions already have the SSA
358  // def-dominates-use requirement enforced.
359  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(V);
360  if (I != FuncInfo.ValueMap.end())
361  return I->second;
362  return LocalValueMap[V];
363 }
364 
365 void FastISel::updateValueMap(const Value *I, Register Reg, unsigned NumRegs) {
366  if (!isa<Instruction>(I)) {
367  LocalValueMap[I] = Reg;
368  return;
369  }
370 
371  Register &AssignedReg = FuncInfo.ValueMap[I];
372  if (!AssignedReg)
373  // Use the new register.
374  AssignedReg = Reg;
375  else if (Reg != AssignedReg) {
376  // Arrange for uses of AssignedReg to be replaced by uses of Reg.
377  for (unsigned i = 0; i < NumRegs; i++) {
378  FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
379  FuncInfo.RegsWithFixups.insert(Reg + i);
380  }
381 
382  AssignedReg = Reg;
383  }
384 }
385 
387  Register IdxN = getRegForValue(Idx);
388  if (!IdxN)
389  // Unhandled operand. Halt "fast" selection and bail.
390  return Register();
391 
392  // If the index is smaller or larger than intptr_t, truncate or extend it.
393  MVT PtrVT = TLI.getPointerTy(DL);
394  EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
395  if (IdxVT.bitsLT(PtrVT)) {
396  IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
397  } else if (IdxVT.bitsGT(PtrVT)) {
398  IdxN =
399  fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
400  }
401  return IdxN;
402 }
403 
405  if (getLastLocalValue()) {
406  FuncInfo.InsertPt = getLastLocalValue();
407  FuncInfo.MBB = FuncInfo.InsertPt->getParent();
408  ++FuncInfo.InsertPt;
409  } else
410  FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
411 
412  // Now skip past any EH_LABELs, which must remain at the beginning.
413  while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
414  FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
415  ++FuncInfo.InsertPt;
416 }
417 
420  assert(I.isValid() && E.isValid() && std::distance(I, E) > 0 &&
421  "Invalid iterator!");
422  while (I != E) {
423  if (SavedInsertPt == I)
424  SavedInsertPt = E;
425  if (EmitStartPt == I)
426  EmitStartPt = E.isValid() ? &*E : nullptr;
427  if (LastLocalValue == I)
428  LastLocalValue = E.isValid() ? &*E : nullptr;
429 
430  MachineInstr *Dead = &*I;
431  ++I;
432  Dead->eraseFromParent();
433  ++NumFastIselDead;
434  }
435  recomputeInsertPt();
436 }
437 
439  SavePoint OldInsertPt = FuncInfo.InsertPt;
440  recomputeInsertPt();
441  return OldInsertPt;
442 }
443 
445  if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
446  LastLocalValue = &*std::prev(FuncInfo.InsertPt);
447 
448  // Restore the previous insert position.
449  FuncInfo.InsertPt = OldInsertPt;
450 }
451 
452 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
453  EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
454  if (VT == MVT::Other || !VT.isSimple())
455  // Unhandled type. Halt "fast" selection and bail.
456  return false;
457 
458  // We only handle legal types. For example, on x86-32 the instruction
459  // selector contains all of the 64-bit instructions from x86-64,
460  // under the assumption that i64 won't be used if the target doesn't
461  // support it.
462  if (!TLI.isTypeLegal(VT)) {
463  // MVT::i1 is special. Allow AND, OR, or XOR because they
464  // don't require additional zeroing, which makes them easy.
465  if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
466  ISDOpcode == ISD::XOR))
467  VT = TLI.getTypeToTransformTo(I->getContext(), VT);
468  else
469  return false;
470  }
471 
472  // Check if the first operand is a constant, and handle it as "ri". At -O0,
473  // we don't have anything that canonicalizes operand order.
474  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
475  if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
476  Register Op1 = getRegForValue(I->getOperand(1));
477  if (!Op1)
478  return false;
479 
480  Register ResultReg =
481  fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(),
482  VT.getSimpleVT());
483  if (!ResultReg)
484  return false;
485 
486  // We successfully emitted code for the given LLVM Instruction.
487  updateValueMap(I, ResultReg);
488  return true;
489  }
490 
491  Register Op0 = getRegForValue(I->getOperand(0));
492  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
493  return false;
494 
495  // Check if the second operand is a constant and handle it appropriately.
496  if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
497  uint64_t Imm = CI->getSExtValue();
498 
499  // Transform "sdiv exact X, 8" -> "sra X, 3".
500  if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
501  cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
502  Imm = Log2_64(Imm);
503  ISDOpcode = ISD::SRA;
504  }
505 
506  // Transform "urem x, pow2" -> "and x, pow2-1".
507  if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
508  isPowerOf2_64(Imm)) {
509  --Imm;
510  ISDOpcode = ISD::AND;
511  }
512 
513  Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
514  VT.getSimpleVT());
515  if (!ResultReg)
516  return false;
517 
518  // We successfully emitted code for the given LLVM Instruction.
519  updateValueMap(I, ResultReg);
520  return true;
521  }
522 
523  Register Op1 = getRegForValue(I->getOperand(1));
524  if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
525  return false;
526 
527  // Now we have both operands in registers. Emit the instruction.
528  Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
529  ISDOpcode, Op0, Op1);
530  if (!ResultReg)
531  // Target-specific code wasn't able to find a machine opcode for
532  // the given ISD opcode and type. Halt "fast" selection and bail.
533  return false;
534 
535  // We successfully emitted code for the given LLVM Instruction.
536  updateValueMap(I, ResultReg);
537  return true;
538 }
539 
541  Register N = getRegForValue(I->getOperand(0));
542  if (!N) // Unhandled operand. Halt "fast" selection and bail.
543  return false;
544 
545  // FIXME: The code below does not handle vector GEPs. Halt "fast" selection
546  // and bail.
547  if (isa<VectorType>(I->getType()))
548  return false;
549 
550  // Keep a running tab of the total offset to coalesce multiple N = N + Offset
551  // into a single N = N + TotalOffset.
552  uint64_t TotalOffs = 0;
553  // FIXME: What's a good SWAG number for MaxOffs?
554  uint64_t MaxOffs = 2048;
555  MVT VT = TLI.getPointerTy(DL);
557  GTI != E; ++GTI) {
558  const Value *Idx = GTI.getOperand();
559  if (StructType *StTy = GTI.getStructTypeOrNull()) {
560  uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
561  if (Field) {
562  // N = N + Offset
563  TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
564  if (TotalOffs >= MaxOffs) {
565  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
566  if (!N) // Unhandled operand. Halt "fast" selection and bail.
567  return false;
568  TotalOffs = 0;
569  }
570  }
571  } else {
572  Type *Ty = GTI.getIndexedType();
573 
574  // If this is a constant subscript, handle it quickly.
575  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
576  if (CI->isZero())
577  continue;
578  // N = N + Offset
579  uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
580  TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
581  if (TotalOffs >= MaxOffs) {
582  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
583  if (!N) // Unhandled operand. Halt "fast" selection and bail.
584  return false;
585  TotalOffs = 0;
586  }
587  continue;
588  }
589  if (TotalOffs) {
590  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
591  if (!N) // Unhandled operand. Halt "fast" selection and bail.
592  return false;
593  TotalOffs = 0;
594  }
595 
596  // N = N + Idx * ElementSize;
597  uint64_t ElementSize = DL.getTypeAllocSize(Ty);
598  Register IdxN = getRegForGEPIndex(Idx);
599  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
600  return false;
601 
602  if (ElementSize != 1) {
603  IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
604  if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
605  return false;
606  }
607  N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
608  if (!N) // Unhandled operand. Halt "fast" selection and bail.
609  return false;
610  }
611  }
612  if (TotalOffs) {
613  N = fastEmit_ri_(VT, ISD::ADD, N, TotalOffs, VT);
614  if (!N) // Unhandled operand. Halt "fast" selection and bail.
615  return false;
616  }
617 
618  // We successfully emitted code for the given LLVM Instruction.
619  updateValueMap(I, N);
620  return true;
621 }
622 
623 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
624  const CallInst *CI, unsigned StartIdx) {
625  for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
626  Value *Val = CI->getArgOperand(i);
627  // Check for constants and encode them with a StackMaps::ConstantOp prefix.
628  if (const auto *C = dyn_cast<ConstantInt>(Val)) {
629  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
630  Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
631  } else if (isa<ConstantPointerNull>(Val)) {
632  Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
633  Ops.push_back(MachineOperand::CreateImm(0));
634  } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
635  // Values coming from a stack location also require a special encoding,
636  // but that is added later on by the target specific frame index
637  // elimination implementation.
638  auto SI = FuncInfo.StaticAllocaMap.find(AI);
639  if (SI != FuncInfo.StaticAllocaMap.end())
640  Ops.push_back(MachineOperand::CreateFI(SI->second));
641  else
642  return false;
643  } else {
644  Register Reg = getRegForValue(Val);
645  if (!Reg)
646  return false;
647  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
648  }
649  }
650  return true;
651 }
652 
654  // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
655  // [live variables...])
656  assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
657  "Stackmap cannot return a value.");
658 
659  // The stackmap intrinsic only records the live variables (the arguments
660  // passed to it) and emits NOPS (if requested). Unlike the patchpoint
661  // intrinsic, this won't be lowered to a function call. This means we don't
662  // have to worry about calling conventions and target-specific lowering code.
663  // Instead we perform the call lowering right here.
664  //
665  // CALLSEQ_START(0, 0...)
666  // STACKMAP(id, nbytes, ...)
667  // CALLSEQ_END(0, 0)
668  //
670 
671  // Add the <id> and <numBytes> constants.
672  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
673  "Expected a constant integer.");
674  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
675  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
676 
677  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
678  "Expected a constant integer.");
679  const auto *NumBytes =
680  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
681  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
682 
683  // Push live variables for the stack map (skipping the first two arguments
684  // <id> and <numBytes>).
685  if (!addStackMapLiveVars(Ops, I, 2))
686  return false;
687 
688  // We are not adding any register mask info here, because the stackmap doesn't
689  // clobber anything.
690 
691  // Add scratch registers as implicit def and early clobber.
692  CallingConv::ID CC = I->getCallingConv();
693  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
694  for (unsigned i = 0; ScratchRegs[i]; ++i)
695  Ops.push_back(MachineOperand::CreateReg(
696  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
697  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
698 
699  // Issue CALLSEQ_START
700  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
701  auto Builder =
702  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
703  const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
704  for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
705  Builder.addImm(0);
706 
707  // Issue STACKMAP.
708  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
709  TII.get(TargetOpcode::STACKMAP));
710  for (auto const &MO : Ops)
711  MIB.add(MO);
712 
713  // Issue CALLSEQ_END
714  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
715  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
716  .addImm(0)
717  .addImm(0);
718 
719  // Inform the Frame Information that we have a stackmap in this function.
720  FuncInfo.MF->getFrameInfo().setHasStackMap();
721 
722  return true;
723 }
724 
725 /// Lower an argument list according to the target calling convention.
726 ///
727 /// This is a helper for lowering intrinsics that follow a target calling
728 /// convention or require stack pointer adjustment. Only a subset of the
729 /// intrinsic's operands need to participate in the calling convention.
730 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
731  unsigned NumArgs, const Value *Callee,
732  bool ForceRetVoidTy, CallLoweringInfo &CLI) {
733  ArgListTy Args;
734  Args.reserve(NumArgs);
735 
736  // Populate the argument list.
737  for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs; ArgI != ArgE; ++ArgI) {
738  Value *V = CI->getOperand(ArgI);
739 
740  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
741 
742  ArgListEntry Entry;
743  Entry.Val = V;
744  Entry.Ty = V->getType();
745  Entry.setAttributes(CI, ArgI);
746  Args.push_back(Entry);
747  }
748 
749  Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
750  : CI->getType();
751  CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
752 
753  return lowerCallTo(CLI);
754 }
755 
757  const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
758  StringRef Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
759  SmallString<32> MangledName;
760  Mangler::getNameWithPrefix(MangledName, Target, DL);
761  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
762  return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
763 }
764 
766  // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
767  // i32 <numBytes>,
768  // i8* <target>,
769  // i32 <numArgs>,
770  // [Args...],
771  // [live variables...])
772  CallingConv::ID CC = I->getCallingConv();
773  bool IsAnyRegCC = CC == CallingConv::AnyReg;
774  bool HasDef = !I->getType()->isVoidTy();
775  Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
776 
777  // Get the real number of arguments participating in the call <numArgs>
778  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
779  "Expected a constant integer.");
780  const auto *NumArgsVal =
781  cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
782  unsigned NumArgs = NumArgsVal->getZExtValue();
783 
784  // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
785  // This includes all meta-operands up to but not including CC.
786  unsigned NumMetaOpers = PatchPointOpers::CCPos;
787  assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
788  "Not enough arguments provided to the patchpoint intrinsic");
789 
790  // For AnyRegCC the arguments are lowered later on manually.
791  unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
792  CallLoweringInfo CLI;
793  CLI.setIsPatchPoint();
794  if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
795  return false;
796 
797  assert(CLI.Call && "No call instruction specified.");
798 
800 
801  // Add an explicit result reg if we use the anyreg calling convention.
802  if (IsAnyRegCC && HasDef) {
803  assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
804  CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
805  CLI.NumResultRegs = 1;
806  Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
807  }
808 
809  // Add the <id> and <numBytes> constants.
810  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
811  "Expected a constant integer.");
812  const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
813  Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
814 
815  assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
816  "Expected a constant integer.");
817  const auto *NumBytes =
818  cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
819  Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
820 
821  // Add the call target.
822  if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
823  uint64_t CalleeConstAddr =
824  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
825  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
826  } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
827  if (C->getOpcode() == Instruction::IntToPtr) {
828  uint64_t CalleeConstAddr =
829  cast<ConstantInt>(C->getOperand(0))->getZExtValue();
830  Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
831  } else
832  llvm_unreachable("Unsupported ConstantExpr.");
833  } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
834  Ops.push_back(MachineOperand::CreateGA(GV, 0));
835  } else if (isa<ConstantPointerNull>(Callee))
836  Ops.push_back(MachineOperand::CreateImm(0));
837  else
838  llvm_unreachable("Unsupported callee address.");
839 
840  // Adjust <numArgs> to account for any arguments that have been passed on
841  // the stack instead.
842  unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
843  Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
844 
845  // Add the calling convention
846  Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
847 
848  // Add the arguments we omitted previously. The register allocator should
849  // place these in any free register.
850  if (IsAnyRegCC) {
851  for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
852  Register Reg = getRegForValue(I->getArgOperand(i));
853  if (!Reg)
854  return false;
855  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
856  }
857  }
858 
859  // Push the arguments from the call instruction.
860  for (auto Reg : CLI.OutRegs)
861  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
862 
863  // Push live variables for the stack map.
864  if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
865  return false;
866 
867  // Push the register mask info.
868  Ops.push_back(MachineOperand::CreateRegMask(
869  TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
870 
871  // Add scratch registers as implicit def and early clobber.
872  const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
873  for (unsigned i = 0; ScratchRegs[i]; ++i)
874  Ops.push_back(MachineOperand::CreateReg(
875  ScratchRegs[i], /*isDef=*/true, /*isImp=*/true, /*isKill=*/false,
876  /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/true));
877 
878  // Add implicit defs (return values).
879  for (auto Reg : CLI.InRegs)
880  Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
881  /*isImp=*/true));
882 
883  // Insert the patchpoint instruction before the call generated by the target.
884  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
885  TII.get(TargetOpcode::PATCHPOINT));
886 
887  for (auto &MO : Ops)
888  MIB.add(MO);
889 
890  MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
891 
892  // Delete the original call instruction.
893  CLI.Call->eraseFromParent();
894 
895  // Inform the Frame Information that we have a patchpoint in this function.
896  FuncInfo.MF->getFrameInfo().setHasPatchPoint();
897 
898  if (CLI.NumResultRegs)
899  updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
900  return true;
901 }
902 
904  const auto &Triple = TM.getTargetTriple();
906  return true; // don't do anything to this instruction.
908  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
909  /*isDef=*/false));
910  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
911  /*isDef=*/false));
912  MachineInstrBuilder MIB =
913  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
914  TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));
915  for (auto &MO : Ops)
916  MIB.add(MO);
917 
918  // Insert the Patchable Event Call instruction, that gets lowered properly.
919  return true;
920 }
921 
923  const auto &Triple = TM.getTargetTriple();
925  return true; // don't do anything to this instruction.
927  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
928  /*isDef=*/false));
929  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
930  /*isDef=*/false));
931  Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(2)),
932  /*isDef=*/false));
933  MachineInstrBuilder MIB =
934  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
935  TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
936  for (auto &MO : Ops)
937  MIB.add(MO);
938 
939  // Insert the Patchable Typed Event Call instruction, that gets lowered properly.
940  return true;
941 }
942 
943 /// Returns an AttributeList representing the attributes applied to the return
944 /// value of the given call.
947  if (CLI.RetSExt)
948  Attrs.push_back(Attribute::SExt);
949  if (CLI.RetZExt)
950  Attrs.push_back(Attribute::ZExt);
951  if (CLI.IsInReg)
952  Attrs.push_back(Attribute::InReg);
953 
955  Attrs);
956 }
957 
958 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
959  unsigned NumArgs) {
960  MCContext &Ctx = MF->getContext();
961  SmallString<32> MangledName;
962  Mangler::getNameWithPrefix(MangledName, SymName, DL);
963  MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
964  return lowerCallTo(CI, Sym, NumArgs);
965 }
966 
968  unsigned NumArgs) {
969  FunctionType *FTy = CI->getFunctionType();
970  Type *RetTy = CI->getType();
971 
972  ArgListTy Args;
973  Args.reserve(NumArgs);
974 
975  // Populate the argument list.
976  // Attributes for args start at offset 1, after the return attribute.
977  for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
978  Value *V = CI->getOperand(ArgI);
979 
980  assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
981 
982  ArgListEntry Entry;
983  Entry.Val = V;
984  Entry.Ty = V->getType();
985  Entry.setAttributes(CI, ArgI);
986  Args.push_back(Entry);
987  }
988  TLI.markLibCallAttributes(MF, CI->getCallingConv(), Args);
989 
990  CallLoweringInfo CLI;
991  CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), *CI, NumArgs);
992 
993  return lowerCallTo(CLI);
994 }
995 
997  // Handle the incoming return values from the call.
998  CLI.clearIns();
999  SmallVector<EVT, 4> RetTys;
1000  ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
1001 
1003  GetReturnInfo(CLI.CallConv, CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
1004 
1005  bool CanLowerReturn = TLI.CanLowerReturn(
1006  CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
1007 
1008  // FIXME: sret demotion isn't supported yet - bail out.
1009  if (!CanLowerReturn)
1010  return false;
1011 
1012  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
1013  EVT VT = RetTys[I];
1014  MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
1015  unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
1016  for (unsigned i = 0; i != NumRegs; ++i) {
1017  ISD::InputArg MyFlags;
1018  MyFlags.VT = RegisterVT;
1019  MyFlags.ArgVT = VT;
1020  MyFlags.Used = CLI.IsReturnValueUsed;
1021  if (CLI.RetSExt)
1022  MyFlags.Flags.setSExt();
1023  if (CLI.RetZExt)
1024  MyFlags.Flags.setZExt();
1025  if (CLI.IsInReg)
1026  MyFlags.Flags.setInReg();
1027  CLI.Ins.push_back(MyFlags);
1028  }
1029  }
1030 
1031  // Handle all of the outgoing arguments.
1032  CLI.clearOuts();
1033  for (auto &Arg : CLI.getArgs()) {
1034  Type *FinalType = Arg.Ty;
1035  if (Arg.IsByVal)
1036  FinalType = cast<PointerType>(Arg.Ty)->getElementType();
1037  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
1038  FinalType, CLI.CallConv, CLI.IsVarArg);
1039 
1040  ISD::ArgFlagsTy Flags;
1041  if (Arg.IsZExt)
1042  Flags.setZExt();
1043  if (Arg.IsSExt)
1044  Flags.setSExt();
1045  if (Arg.IsInReg)
1046  Flags.setInReg();
1047  if (Arg.IsSRet)
1048  Flags.setSRet();
1049  if (Arg.IsSwiftSelf)
1050  Flags.setSwiftSelf();
1051  if (Arg.IsSwiftError)
1052  Flags.setSwiftError();
1053  if (Arg.IsCFGuardTarget)
1054  Flags.setCFGuardTarget();
1055  if (Arg.IsByVal)
1056  Flags.setByVal();
1057  if (Arg.IsInAlloca) {
1058  Flags.setInAlloca();
1059  // Set the byval flag for CCAssignFn callbacks that don't know about
1060  // inalloca. This way we can know how many bytes we should've allocated
1061  // and how many bytes a callee cleanup function will pop. If we port
1062  // inalloca to more targets, we'll have to add custom inalloca handling in
1063  // the various CC lowering callbacks.
1064  Flags.setByVal();
1065  }
1066  if (Arg.IsPreallocated) {
1067  Flags.setPreallocated();
1068  // Set the byval flag for CCAssignFn callbacks that don't know about
1069  // preallocated. This way we can know how many bytes we should've
1070  // allocated and how many bytes a callee cleanup function will pop. If we
1071  // port preallocated to more targets, we'll have to add custom
1072  // preallocated handling in the various CC lowering callbacks.
1073  Flags.setByVal();
1074  }
1075  if (Arg.IsByVal || Arg.IsInAlloca || Arg.IsPreallocated) {
1076  PointerType *Ty = cast<PointerType>(Arg.Ty);
1077  Type *ElementTy = Ty->getElementType();
1078  unsigned FrameSize =
1079  DL.getTypeAllocSize(Arg.ByValType ? Arg.ByValType : ElementTy);
1080 
1081  // For ByVal, alignment should come from FE. BE will guess if this info
1082  // is not there, but there are cases it cannot get right.
1083  MaybeAlign FrameAlign = Arg.Alignment;
1084  if (!FrameAlign)
1085  FrameAlign = Align(TLI.getByValTypeAlignment(ElementTy, DL));
1086  Flags.setByValSize(FrameSize);
1087  Flags.setByValAlign(*FrameAlign);
1088  }
1089  if (Arg.IsNest)
1090  Flags.setNest();
1091  if (NeedsRegBlock)
1092  Flags.setInConsecutiveRegs();
1093  Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
1094 
1095  CLI.OutVals.push_back(Arg.Val);
1096  CLI.OutFlags.push_back(Flags);
1097  }
1098 
1099  if (!fastLowerCall(CLI))
1100  return false;
1101 
1102  // Set all unused physreg defs as dead.
1103  assert(CLI.Call && "No call instruction specified.");
1104  CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
1105 
1106  if (CLI.NumResultRegs && CLI.CB)
1107  updateValueMap(CLI.CB, CLI.ResultReg, CLI.NumResultRegs);
1108 
1109  // Set labels for heapallocsite call.
1110  if (CLI.CB)
1111  if (MDNode *MD = CLI.CB->getMetadata("heapallocsite"))
1112  CLI.Call->setHeapAllocMarker(*MF, MD);
1113 
1114  return true;
1115 }
1116 
1118  FunctionType *FuncTy = CI->getFunctionType();
1119  Type *RetTy = CI->getType();
1120 
1121  ArgListTy Args;
1122  ArgListEntry Entry;
1123  Args.reserve(CI->arg_size());
1124 
1125  for (auto i = CI->arg_begin(), e = CI->arg_end(); i != e; ++i) {
1126  Value *V = *i;
1127 
1128  // Skip empty types
1129  if (V->getType()->isEmptyTy())
1130  continue;
1131 
1132  Entry.Val = V;
1133  Entry.Ty = V->getType();
1134 
1135  // Skip the first return-type Attribute to get to params.
1136  Entry.setAttributes(CI, i - CI->arg_begin());
1137  Args.push_back(Entry);
1138  }
1139 
1140  // Check if target-independent constraints permit a tail call here.
1141  // Target-dependent constraints are checked within fastLowerCall.
1142  bool IsTailCall = CI->isTailCall();
1143  if (IsTailCall && !isInTailCallPosition(*CI, TM))
1144  IsTailCall = false;
1145  if (IsTailCall && MF->getFunction()
1146  .getFnAttribute("disable-tail-calls")
1147  .getValueAsString() == "true")
1148  IsTailCall = false;
1149 
1150  CallLoweringInfo CLI;
1151  CLI.setCallee(RetTy, FuncTy, CI->getCalledOperand(), std::move(Args), *CI)
1152  .setTailCall(IsTailCall);
1153 
1154  return lowerCallTo(CLI);
1155 }
1156 
1158  const CallInst *Call = cast<CallInst>(I);
1159 
1160  // Handle simple inline asms.
1161  if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledOperand())) {
1162  // Don't attempt to handle constraints.
1163  if (!IA->getConstraintString().empty())
1164  return false;
1165 
1166  unsigned ExtraInfo = 0;
1167  if (IA->hasSideEffects())
1168  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1169  if (IA->isAlignStack())
1170  ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1171  if (Call->isConvergent())
1172  ExtraInfo |= InlineAsm::Extra_IsConvergent;
1173  ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
1174 
1175  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1177  MIB.addExternalSymbol(IA->getAsmString().c_str());
1178  MIB.addImm(ExtraInfo);
1179 
1180  const MDNode *SrcLoc = Call->getMetadata("srcloc");
1181  if (SrcLoc)
1182  MIB.addMetadata(SrcLoc);
1183 
1184  return true;
1185  }
1186 
1187  // Handle intrinsic function calls.
1188  if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1189  return selectIntrinsicCall(II);
1190 
1191  return lowerCall(Call);
1192 }
1193 
1195  switch (II->getIntrinsicID()) {
1196  default:
1197  break;
1198  // At -O0 we don't care about the lifetime intrinsics.
1199  case Intrinsic::lifetime_start:
1200  case Intrinsic::lifetime_end:
1201  // The donothing intrinsic does, well, nothing.
1202  case Intrinsic::donothing:
1203  // Neither does the sideeffect intrinsic.
1204  case Intrinsic::sideeffect:
1205  // Neither does the assume intrinsic; it's also OK not to codegen its operand.
1206  case Intrinsic::assume:
1207  // Neither does the llvm.experimental.noalias.scope.decl intrinsic
1208  case Intrinsic::experimental_noalias_scope_decl:
1209  return true;
1210  case Intrinsic::dbg_declare: {
1211  const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1212  assert(DI->getVariable() && "Missing variable");
1213  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1214  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1215  << " (!hasDebugInfo)\n");
1216  return true;
1217  }
1218 
1219  const Value *Address = DI->getAddress();
1220  if (!Address || isa<UndefValue>(Address)) {
1221  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1222  << " (bad/undef address)\n");
1223  return true;
1224  }
1225 
1226  // Byval arguments with frame indices were already handled after argument
1227  // lowering and before isel.
1228  const auto *Arg =
1229  dyn_cast<Argument>(Address->stripInBoundsConstantOffsets());
1230  if (Arg && FuncInfo.getArgumentFrameIndex(Arg) != INT_MAX)
1231  return true;
1232 
1234  if (Register Reg = lookUpRegForValue(Address))
1235  Op = MachineOperand::CreateReg(Reg, false);
1236 
1237  // If we have a VLA that has a "use" in a metadata node that's then used
1238  // here but it has no other uses, then we have a problem. E.g.,
1239  //
1240  // int foo (const int *x) {
1241  // char a[*x];
1242  // return 0;
1243  // }
1244  //
1245  // If we assign 'a' a vreg and fast isel later on has to use the selection
1246  // DAG isel, it will want to copy the value to the vreg. However, there are
1247  // no uses, which goes counter to what selection DAG isel expects.
1248  if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1249  (!isa<AllocaInst>(Address) ||
1250  !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1251  Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1252  false);
1253 
1254  if (Op) {
1256  "Expected inlined-at fields to agree");
1257  // A dbg.declare describes the address of a source variable, so lower it
1258  // into an indirect DBG_VALUE.
1259  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1260  TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true,
1261  *Op, DI->getVariable(), DI->getExpression());
1262  } else {
1263  // We can't yet handle anything else here because it would require
1264  // generating code, thus altering codegen because of debug info.
1265  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI
1266  << " (no materialized reg for address)\n");
1267  }
1268  return true;
1269  }
1270  case Intrinsic::dbg_value: {
1271  // This form of DBG_VALUE is target-independent.
1272  const DbgValueInst *DI = cast<DbgValueInst>(II);
1273  const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1274  const Value *V = DI->getValue();
1276  "Expected inlined-at fields to agree");
1277  if (!V || isa<UndefValue>(V)) {
1278  // Currently the optimizer can produce this; insert an undef to
1279  // help debugging.
1280  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, false, 0U,
1281  DI->getVariable(), DI->getExpression());
1282  } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1283  if (CI->getBitWidth() > 64)
1284  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1285  .addCImm(CI)
1286  .addImm(0U)
1287  .addMetadata(DI->getVariable())
1288  .addMetadata(DI->getExpression());
1289  else
1290  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1291  .addImm(CI->getZExtValue())
1292  .addImm(0U)
1293  .addMetadata(DI->getVariable())
1294  .addMetadata(DI->getExpression());
1295  } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1296  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1297  .addFPImm(CF)
1298  .addImm(0U)
1299  .addMetadata(DI->getVariable())
1300  .addMetadata(DI->getExpression());
1301  } else if (Register Reg = lookUpRegForValue(V)) {
1302  // FIXME: This does not handle register-indirect values at offset 0.
1303  bool IsIndirect = false;
1304  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1305  DI->getVariable(), DI->getExpression());
1306  } else {
1307  // We don't know how to handle other cases, so we drop.
1308  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1309  }
1310  return true;
1311  }
1312  case Intrinsic::dbg_label: {
1313  const DbgLabelInst *DI = cast<DbgLabelInst>(II);
1314  assert(DI->getLabel() && "Missing label");
1315  if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1316  LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1317  return true;
1318  }
1319 
1320  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1321  TII.get(TargetOpcode::DBG_LABEL)).addMetadata(DI->getLabel());
1322  return true;
1323  }
1324  case Intrinsic::objectsize:
1325  llvm_unreachable("llvm.objectsize.* should have been lowered already");
1326 
1327  case Intrinsic::is_constant:
1328  llvm_unreachable("llvm.is.constant.* should have been lowered already");
1329 
1330  case Intrinsic::launder_invariant_group:
1331  case Intrinsic::strip_invariant_group:
1332  case Intrinsic::expect: {
1333  Register ResultReg = getRegForValue(II->getArgOperand(0));
1334  if (!ResultReg)
1335  return false;
1336  updateValueMap(II, ResultReg);
1337  return true;
1338  }
1339  case Intrinsic::experimental_stackmap:
1340  return selectStackmap(II);
1341  case Intrinsic::experimental_patchpoint_void:
1342  case Intrinsic::experimental_patchpoint_i64:
1343  return selectPatchpoint(II);
1344 
1345  case Intrinsic::xray_customevent:
1346  return selectXRayCustomEvent(II);
1347  case Intrinsic::xray_typedevent:
1348  return selectXRayTypedEvent(II);
1349  }
1350 
1351  return fastLowerIntrinsicCall(II);
1352 }
1353 
1354 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1355  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1356  EVT DstVT = TLI.getValueType(DL, I->getType());
1357 
1358  if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1359  !DstVT.isSimple())
1360  // Unhandled type. Halt "fast" selection and bail.
1361  return false;
1362 
1363  // Check if the destination type is legal.
1364  if (!TLI.isTypeLegal(DstVT))
1365  return false;
1366 
1367  // Check if the source operand is legal.
1368  if (!TLI.isTypeLegal(SrcVT))
1369  return false;
1370 
1371  Register InputReg = getRegForValue(I->getOperand(0));
1372  if (!InputReg)
1373  // Unhandled operand. Halt "fast" selection and bail.
1374  return false;
1375 
1376  Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1377  Opcode, InputReg);
1378  if (!ResultReg)
1379  return false;
1380 
1381  updateValueMap(I, ResultReg);
1382  return true;
1383 }
1384 
1386  // If the bitcast doesn't change the type, just use the operand value.
1387  if (I->getType() == I->getOperand(0)->getType()) {
1388  Register Reg = getRegForValue(I->getOperand(0));
1389  if (!Reg)
1390  return false;
1391  updateValueMap(I, Reg);
1392  return true;
1393  }
1394 
1395  // Bitcasts of other values become reg-reg copies or BITCAST operators.
1396  EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1397  EVT DstEVT = TLI.getValueType(DL, I->getType());
1398  if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1399  !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1400  // Unhandled type. Halt "fast" selection and bail.
1401  return false;
1402 
1403  MVT SrcVT = SrcEVT.getSimpleVT();
1404  MVT DstVT = DstEVT.getSimpleVT();
1405  Register Op0 = getRegForValue(I->getOperand(0));
1406  if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1407  return false;
1408 
1409  // First, try to perform the bitcast by inserting a reg-reg copy.
1410  Register ResultReg;
1411  if (SrcVT == DstVT) {
1412  const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1413  const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1414  // Don't attempt a cross-class copy. It will likely fail.
1415  if (SrcClass == DstClass) {
1416  ResultReg = createResultReg(DstClass);
1417  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1418  TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1419  }
1420  }
1421 
1422  // If the reg-reg copy failed, select a BITCAST opcode.
1423  if (!ResultReg)
1424  ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1425 
1426  if (!ResultReg)
1427  return false;
1428 
1429  updateValueMap(I, ResultReg);
1430  return true;
1431 }
1432 
1434  Register Reg = getRegForValue(I->getOperand(0));
1435  if (!Reg)
1436  // Unhandled operand.
1437  return false;
1438 
1439  EVT ETy = TLI.getValueType(DL, I->getOperand(0)->getType());
1440  if (ETy == MVT::Other || !TLI.isTypeLegal(ETy))
1441  // Unhandled type, bail out.
1442  return false;
1443 
1444  MVT Ty = ETy.getSimpleVT();
1445  const TargetRegisterClass *TyRegClass = TLI.getRegClassFor(Ty);
1446  Register ResultReg = createResultReg(TyRegClass);
1447  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1448  TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg);
1449 
1450  updateValueMap(I, ResultReg);
1451  return true;
1452 }
1453 
1454 // Remove local value instructions starting from the instruction after
1455 // SavedLastLocalValue to the current function insert point.
1456 void FastISel::removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue)
1457 {
1458  MachineInstr *CurLastLocalValue = getLastLocalValue();
1459  if (CurLastLocalValue != SavedLastLocalValue) {
1460  // Find the first local value instruction to be deleted.
1461  // This is the instruction after SavedLastLocalValue if it is non-NULL.
1462  // Otherwise it's the first instruction in the block.
1463  MachineBasicBlock::iterator FirstDeadInst(SavedLastLocalValue);
1464  if (SavedLastLocalValue)
1465  ++FirstDeadInst;
1466  else
1467  FirstDeadInst = FuncInfo.MBB->getFirstNonPHI();
1468  setLastLocalValue(SavedLastLocalValue);
1469  removeDeadCode(FirstDeadInst, FuncInfo.InsertPt);
1470  }
1471 }
1472 
1474  // Flush the local value map before starting each instruction.
1475  // This improves locality and debugging, and can reduce spills.
1476  // Reuse of values across IR instructions is relatively uncommon.
1477  flushLocalValueMap();
1478 
1479  MachineInstr *SavedLastLocalValue = getLastLocalValue();
1480  // Just before the terminator instruction, insert instructions to
1481  // feed PHI nodes in successor blocks.
1482  if (I->isTerminator()) {
1483  if (!handlePHINodesInSuccessorBlocks(I->getParent())) {
1484  // PHI node handling may have generated local value instructions,
1485  // even though it failed to handle all PHI nodes.
1486  // We remove these instructions because SelectionDAGISel will generate
1487  // them again.
1488  removeDeadLocalValueCode(SavedLastLocalValue);
1489  return false;
1490  }
1491  }
1492 
1493  // FastISel does not handle any operand bundles except OB_funclet.
1494  if (auto *Call = dyn_cast<CallBase>(I))
1495  for (unsigned i = 0, e = Call->getNumOperandBundles(); i != e; ++i)
1496  if (Call->getOperandBundleAt(i).getTagID() != LLVMContext::OB_funclet)
1497  return false;
1498 
1499  DbgLoc = I->getDebugLoc();
1500 
1501  SavedInsertPt = FuncInfo.InsertPt;
1502 
1503  if (const auto *Call = dyn_cast<CallInst>(I)) {
1504  const Function *F = Call->getCalledFunction();
1505  LibFunc Func;
1506 
1507  // As a special case, don't handle calls to builtin library functions that
1508  // may be translated directly to target instructions.
1509  if (F && !F->hasLocalLinkage() && F->hasName() &&
1510  LibInfo->getLibFunc(F->getName(), Func) &&
1511  LibInfo->hasOptimizedCodeGen(Func))
1512  return false;
1513 
1514  // Don't handle Intrinsic::trap if a trap function is specified.
1515  if (F && F->getIntrinsicID() == Intrinsic::trap &&
1516  Call->hasFnAttr("trap-func-name"))
1517  return false;
1518  }
1519 
1520  // First, try doing target-independent selection.
1521  if (!SkipTargetIndependentISel) {
1522  if (selectOperator(I, I->getOpcode())) {
1523  ++NumFastIselSuccessIndependent;
1524  DbgLoc = DebugLoc();
1525  return true;
1526  }
1527  // Remove dead code.
1528  recomputeInsertPt();
1529  if (SavedInsertPt != FuncInfo.InsertPt)
1530  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1531  SavedInsertPt = FuncInfo.InsertPt;
1532  }
1533  // Next, try calling the target to attempt to handle the instruction.
1534  if (fastSelectInstruction(I)) {
1535  ++NumFastIselSuccessTarget;
1536  DbgLoc = DebugLoc();
1537  return true;
1538  }
1539  // Remove dead code.
1540  recomputeInsertPt();
1541  if (SavedInsertPt != FuncInfo.InsertPt)
1542  removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1543 
1544  DbgLoc = DebugLoc();
1545  // Undo phi node updates, because they will be added again by SelectionDAG.
1546  if (I->isTerminator()) {
1547  // PHI node handling may have generated local value instructions.
1548  // We remove them because SelectionDAGISel will generate them again.
1549  removeDeadLocalValueCode(SavedLastLocalValue);
1550  FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1551  }
1552  return false;
1553 }
1554 
1555 /// Emit an unconditional branch to the given block, unless it is the immediate
1556 /// (fall-through) successor, and update the CFG.
1558  const DebugLoc &DbgLoc) {
1559  if (FuncInfo.MBB->getBasicBlock()->sizeWithoutDebug() > 1 &&
1560  FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1561  // For more accurate line information if this is the only non-debug
1562  // instruction in the block then emit it, otherwise we have the
1563  // unconditional fall-through case, which needs no instructions.
1564  } else {
1565  // The unconditional branch case.
1566  TII.insertBranch(*FuncInfo.MBB, MSucc, nullptr,
1567  SmallVector<MachineOperand, 0>(), DbgLoc);
1568  }
1569  if (FuncInfo.BPI) {
1570  auto BranchProbability = FuncInfo.BPI->getEdgeProbability(
1571  FuncInfo.MBB->getBasicBlock(), MSucc->getBasicBlock());
1572  FuncInfo.MBB->addSuccessor(MSucc, BranchProbability);
1573  } else
1574  FuncInfo.MBB->addSuccessorWithoutProb(MSucc);
1575 }
1576 
1578  MachineBasicBlock *TrueMBB,
1579  MachineBasicBlock *FalseMBB) {
1580  // Add TrueMBB as successor unless it is equal to the FalseMBB: This can
1581  // happen in degenerate IR and MachineIR forbids to have a block twice in the
1582  // successor/predecessor lists.
1583  if (TrueMBB != FalseMBB) {
1584  if (FuncInfo.BPI) {
1585  auto BranchProbability =
1586  FuncInfo.BPI->getEdgeProbability(BranchBB, TrueMBB->getBasicBlock());
1587  FuncInfo.MBB->addSuccessor(TrueMBB, BranchProbability);
1588  } else
1589  FuncInfo.MBB->addSuccessorWithoutProb(TrueMBB);
1590  }
1591 
1592  fastEmitBranch(FalseMBB, DbgLoc);
1593 }
1594 
1595 /// Emit an FNeg operation.
1596 bool FastISel::selectFNeg(const User *I, const Value *In) {
1597  Register OpReg = getRegForValue(In);
1598  if (!OpReg)
1599  return false;
1600 
1601  // If the target has ISD::FNEG, use it.
1602  EVT VT = TLI.getValueType(DL, I->getType());
1603  Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1604  OpReg);
1605  if (ResultReg) {
1606  updateValueMap(I, ResultReg);
1607  return true;
1608  }
1609 
1610  // Bitcast the value to integer, twiddle the sign bit with xor,
1611  // and then bitcast it back to floating-point.
1612  if (VT.getSizeInBits() > 64)
1613  return false;
1614  EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1615  if (!TLI.isTypeLegal(IntVT))
1616  return false;
1617 
1618  Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1619  ISD::BITCAST, OpReg);
1620  if (!IntReg)
1621  return false;
1622 
1623  Register IntResultReg = fastEmit_ri_(
1624  IntVT.getSimpleVT(), ISD::XOR, IntReg,
1625  UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1626  if (!IntResultReg)
1627  return false;
1628 
1629  ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1630  IntResultReg);
1631  if (!ResultReg)
1632  return false;
1633 
1634  updateValueMap(I, ResultReg);
1635  return true;
1636 }
1637 
1639  const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1640  if (!EVI)
1641  return false;
1642 
1643  // Make sure we only try to handle extracts with a legal result. But also
1644  // allow i1 because it's easy.
1645  EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1646  if (!RealVT.isSimple())
1647  return false;
1648  MVT VT = RealVT.getSimpleVT();
1649  if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1650  return false;
1651 
1652  const Value *Op0 = EVI->getOperand(0);
1653  Type *AggTy = Op0->getType();
1654 
1655  // Get the base result register.
1656  unsigned ResultReg;
1657  DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1658  if (I != FuncInfo.ValueMap.end())
1659  ResultReg = I->second;
1660  else if (isa<Instruction>(Op0))
1661  ResultReg = FuncInfo.InitializeRegForValue(Op0);
1662  else
1663  return false; // fast-isel can't handle aggregate constants at the moment
1664 
1665  // Get the actual result register, which is an offset from the base register.
1666  unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1667 
1668  SmallVector<EVT, 4> AggValueVTs;
1669  ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1670 
1671  for (unsigned i = 0; i < VTIndex; i++)
1672  ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1673 
1674  updateValueMap(EVI, ResultReg);
1675  return true;
1676 }
1677 
1678 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1679  switch (Opcode) {
1680  case Instruction::Add:
1681  return selectBinaryOp(I, ISD::ADD);
1682  case Instruction::FAdd:
1683  return selectBinaryOp(I, ISD::FADD);
1684  case Instruction::Sub:
1685  return selectBinaryOp(I, ISD::SUB);
1686  case Instruction::FSub:
1687  return selectBinaryOp(I, ISD::FSUB);
1688  case Instruction::Mul:
1689  return selectBinaryOp(I, ISD::MUL);
1690  case Instruction::FMul:
1691  return selectBinaryOp(I, ISD::FMUL);
1692  case Instruction::SDiv:
1693  return selectBinaryOp(I, ISD::SDIV);
1694  case Instruction::UDiv:
1695  return selectBinaryOp(I, ISD::UDIV);
1696  case Instruction::FDiv:
1697  return selectBinaryOp(I, ISD::FDIV);
1698  case Instruction::SRem:
1699  return selectBinaryOp(I, ISD::SREM);
1700  case Instruction::URem:
1701  return selectBinaryOp(I, ISD::UREM);
1702  case Instruction::FRem:
1703  return selectBinaryOp(I, ISD::FREM);
1704  case Instruction::Shl:
1705  return selectBinaryOp(I, ISD::SHL);
1706  case Instruction::LShr:
1707  return selectBinaryOp(I, ISD::SRL);
1708  case Instruction::AShr:
1709  return selectBinaryOp(I, ISD::SRA);
1710  case Instruction::And:
1711  return selectBinaryOp(I, ISD::AND);
1712  case Instruction::Or:
1713  return selectBinaryOp(I, ISD::OR);
1714  case Instruction::Xor:
1715  return selectBinaryOp(I, ISD::XOR);
1716 
1717  case Instruction::FNeg:
1718  return selectFNeg(I, I->getOperand(0));
1719 
1720  case Instruction::GetElementPtr:
1721  return selectGetElementPtr(I);
1722 
1723  case Instruction::Br: {
1724  const BranchInst *BI = cast<BranchInst>(I);
1725 
1726  if (BI->isUnconditional()) {
1727  const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1728  MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1729  fastEmitBranch(MSucc, BI->getDebugLoc());
1730  return true;
1731  }
1732 
1733  // Conditional branches are not handed yet.
1734  // Halt "fast" selection and bail.
1735  return false;
1736  }
1737 
1738  case Instruction::Unreachable:
1739  if (TM.Options.TrapUnreachable)
1740  return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1741  else
1742  return true;
1743 
1744  case Instruction::Alloca:
1745  // FunctionLowering has the static-sized case covered.
1746  if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1747  return true;
1748 
1749  // Dynamic-sized alloca is not handled yet.
1750  return false;
1751 
1752  case Instruction::Call:
1753  // On AIX, call lowering uses the DAG-ISEL path currently so that the
1754  // callee of the direct function call instruction will be mapped to the
1755  // symbol for the function's entry point, which is distinct from the
1756  // function descriptor symbol. The latter is the symbol whose XCOFF symbol
1757  // name is the C-linkage name of the source level function.
1758  if (TM.getTargetTriple().isOSAIX())
1759  return false;
1760  return selectCall(I);
1761 
1762  case Instruction::BitCast:
1763  return selectBitCast(I);
1764 
1765  case Instruction::FPToSI:
1766  return selectCast(I, ISD::FP_TO_SINT);
1767  case Instruction::ZExt:
1768  return selectCast(I, ISD::ZERO_EXTEND);
1769  case Instruction::SExt:
1770  return selectCast(I, ISD::SIGN_EXTEND);
1771  case Instruction::Trunc:
1772  return selectCast(I, ISD::TRUNCATE);
1773  case Instruction::SIToFP:
1774  return selectCast(I, ISD::SINT_TO_FP);
1775 
1776  case Instruction::IntToPtr: // Deliberate fall-through.
1777  case Instruction::PtrToInt: {
1778  EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1779  EVT DstVT = TLI.getValueType(DL, I->getType());
1780  if (DstVT.bitsGT(SrcVT))
1781  return selectCast(I, ISD::ZERO_EXTEND);
1782  if (DstVT.bitsLT(SrcVT))
1783  return selectCast(I, ISD::TRUNCATE);
1784  Register Reg = getRegForValue(I->getOperand(0));
1785  if (!Reg)
1786  return false;
1787  updateValueMap(I, Reg);
1788  return true;
1789  }
1790 
1791  case Instruction::ExtractValue:
1792  return selectExtractValue(I);
1793 
1794  case Instruction::Freeze:
1795  return selectFreeze(I);
1796 
1797  case Instruction::PHI:
1798  llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1799 
1800  default:
1801  // Unhandled instruction. Halt "fast" selection and bail.
1802  return false;
1803  }
1804 }
1805 
1807  const TargetLibraryInfo *LibInfo,
1808  bool SkipTargetIndependentISel)
1809  : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1810  MFI(FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1811  TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1812  TII(*MF->getSubtarget().getInstrInfo()),
1813  TLI(*MF->getSubtarget().getTargetLowering()),
1814  TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1815  SkipTargetIndependentISel(SkipTargetIndependentISel),
1816  LastLocalValue(nullptr), EmitStartPt(nullptr) {}
1817 
1818 FastISel::~FastISel() = default;
1819 
1820 bool FastISel::fastLowerArguments() { return false; }
1821 
1822 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1823 
1825  return false;
1826 }
1827 
1828 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1829 
1830 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1831  return 0;
1832 }
1833 
1834 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1835  unsigned /*Op1*/) {
1836  return 0;
1837 }
1838 
1839 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1840  return 0;
1841 }
1842 
1843 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1844  const ConstantFP * /*FPImm*/) {
1845  return 0;
1846 }
1847 
1848 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1849  uint64_t /*Imm*/) {
1850  return 0;
1851 }
1852 
1853 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1854 /// instruction with an immediate operand using fastEmit_ri.
1855 /// If that fails, it materializes the immediate into a register and try
1856 /// fastEmit_rr instead.
1857 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1858  uint64_t Imm, MVT ImmType) {
1859  // If this is a multiply by a power of two, emit this as a shift left.
1860  if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1861  Opcode = ISD::SHL;
1862  Imm = Log2_64(Imm);
1863  } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1864  // div x, 8 -> srl x, 3
1865  Opcode = ISD::SRL;
1866  Imm = Log2_64(Imm);
1867  }
1868 
1869  // Horrible hack (to be removed), check to make sure shift amounts are
1870  // in-range.
1871  if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1872  Imm >= VT.getSizeInBits())
1873  return 0;
1874 
1875  // First check if immediate type is legal. If not, we can't use the ri form.
1876  Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
1877  if (ResultReg)
1878  return ResultReg;
1879  Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1880  if (!MaterialReg) {
1881  // This is a bit ugly/slow, but failing here means falling out of
1882  // fast-isel, which would be very slow.
1883  IntegerType *ITy =
1885  MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1886  if (!MaterialReg)
1887  return 0;
1888  }
1889  return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
1890 }
1891 
1893  return MRI.createVirtualRegister(RC);
1894 }
1895 
1897  unsigned OpNum) {
1898  if (Op.isVirtual()) {
1899  const TargetRegisterClass *RegClass =
1900  TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1901  if (!MRI.constrainRegClass(Op, RegClass)) {
1902  // If it's not legal to COPY between the register classes, something
1903  // has gone very wrong before we got here.
1904  Register NewOp = createResultReg(RegClass);
1906  TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1907  return NewOp;
1908  }
1909  }
1910  return Op;
1911 }
1912 
1913 Register FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1914  const TargetRegisterClass *RC) {
1915  Register ResultReg = createResultReg(RC);
1916  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1917 
1918  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1919  return ResultReg;
1920 }
1921 
1922 Register FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1923  const TargetRegisterClass *RC, unsigned Op0) {
1924  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1925 
1926  Register ResultReg = createResultReg(RC);
1927  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1928 
1929  if (II.getNumDefs() >= 1)
1930  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1931  .addReg(Op0);
1932  else {
1934  .addReg(Op0);
1936  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1937  }
1938 
1939  return ResultReg;
1940 }
1941 
1942 Register FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1943  const TargetRegisterClass *RC, unsigned Op0,
1944  unsigned Op1) {
1945  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1946 
1947  Register ResultReg = createResultReg(RC);
1948  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1949  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1950 
1951  if (II.getNumDefs() >= 1)
1952  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1953  .addReg(Op0)
1954  .addReg(Op1);
1955  else {
1957  .addReg(Op0)
1958  .addReg(Op1);
1960  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1961  }
1962  return ResultReg;
1963 }
1964 
1965 Register FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1966  const TargetRegisterClass *RC, unsigned Op0,
1967  unsigned Op1, unsigned Op2) {
1968  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1969 
1970  Register ResultReg = createResultReg(RC);
1971  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1972  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1973  Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1974 
1975  if (II.getNumDefs() >= 1)
1976  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1977  .addReg(Op0)
1978  .addReg(Op1)
1979  .addReg(Op2);
1980  else {
1982  .addReg(Op0)
1983  .addReg(Op1)
1984  .addReg(Op2);
1986  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1987  }
1988  return ResultReg;
1989 }
1990 
1991 Register FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1992  const TargetRegisterClass *RC, unsigned Op0,
1993  uint64_t Imm) {
1994  const MCInstrDesc &II = TII.get(MachineInstOpcode);
1995 
1996  Register ResultReg = createResultReg(RC);
1997  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1998 
1999  if (II.getNumDefs() >= 1)
2000  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2001  .addReg(Op0)
2002  .addImm(Imm);
2003  else {
2005  .addReg(Op0)
2006  .addImm(Imm);
2008  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2009  }
2010  return ResultReg;
2011 }
2012 
2013 Register FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
2014  const TargetRegisterClass *RC, unsigned Op0,
2015  uint64_t Imm1, uint64_t Imm2) {
2016  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2017 
2018  Register ResultReg = createResultReg(RC);
2019  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2020 
2021  if (II.getNumDefs() >= 1)
2022  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2023  .addReg(Op0)
2024  .addImm(Imm1)
2025  .addImm(Imm2);
2026  else {
2028  .addReg(Op0)
2029  .addImm(Imm1)
2030  .addImm(Imm2);
2032  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2033  }
2034  return ResultReg;
2035 }
2036 
2037 Register FastISel::fastEmitInst_f(unsigned MachineInstOpcode,
2038  const TargetRegisterClass *RC,
2039  const ConstantFP *FPImm) {
2040  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2041 
2042  Register ResultReg = createResultReg(RC);
2043 
2044  if (II.getNumDefs() >= 1)
2045  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2046  .addFPImm(FPImm);
2047  else {
2049  .addFPImm(FPImm);
2051  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2052  }
2053  return ResultReg;
2054 }
2055 
2056 Register FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
2057  const TargetRegisterClass *RC, unsigned Op0,
2058  unsigned Op1, uint64_t Imm) {
2059  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2060 
2061  Register ResultReg = createResultReg(RC);
2062  Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2063  Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
2064 
2065  if (II.getNumDefs() >= 1)
2066  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2067  .addReg(Op0)
2068  .addReg(Op1)
2069  .addImm(Imm);
2070  else {
2072  .addReg(Op0)
2073  .addReg(Op1)
2074  .addImm(Imm);
2076  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2077  }
2078  return ResultReg;
2079 }
2080 
2081 Register FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
2082  const TargetRegisterClass *RC, uint64_t Imm) {
2083  Register ResultReg = createResultReg(RC);
2084  const MCInstrDesc &II = TII.get(MachineInstOpcode);
2085 
2086  if (II.getNumDefs() >= 1)
2087  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2088  .addImm(Imm);
2089  else {
2092  TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2093  }
2094  return ResultReg;
2095 }
2096 
2098  uint32_t Idx) {
2099  Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2101  "Cannot yet extract from physregs");
2102  const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2104  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
2105  ResultReg).addReg(Op0, 0, Idx);
2106  return ResultReg;
2107 }
2108 
2109 /// Emit MachineInstrs to compute the value of Op with all but the least
2110 /// significant bit set to zero.
2112  return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);
2113 }
2114 
2115 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
2116 /// Emit code to ensure constants are copied into registers when needed.
2117 /// Remember the virtual registers that need to be added to the Machine PHI
2118 /// nodes as input. We cannot just directly add them, because expansion
2119 /// might result in multiple MBB's for one BB. As such, the start of the
2120 /// BB might correspond to a different MBB than the end.
2121 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
2122  const Instruction *TI = LLVMBB->getTerminator();
2123 
2126 
2127  // Check successor nodes' PHI nodes that expect a constant to be available
2128  // from this block.
2129  for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2130  const BasicBlock *SuccBB = TI->getSuccessor(succ);
2131  if (!isa<PHINode>(SuccBB->begin()))
2132  continue;
2133  MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2134 
2135  // If this terminator has multiple identical successors (common for
2136  // switches), only handle each succ once.
2137  if (!SuccsHandled.insert(SuccMBB).second)
2138  continue;
2139 
2140  MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2141 
2142  // At this point we know that there is a 1-1 correspondence between LLVM PHI
2143  // nodes and Machine PHI nodes, but the incoming operands have not been
2144  // emitted yet.
2145  for (const PHINode &PN : SuccBB->phis()) {
2146  // Ignore dead phi's.
2147  if (PN.use_empty())
2148  continue;
2149 
2150  // Only handle legal types. Two interesting things to note here. First,
2151  // by bailing out early, we may leave behind some dead instructions,
2152  // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2153  // own moves. Second, this check is necessary because FastISel doesn't
2154  // use CreateRegs to create registers, so it always creates
2155  // exactly one register for each non-void instruction.
2156  EVT VT = TLI.getValueType(DL, PN.getType(), /*AllowUnknown=*/true);
2157  if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2158  // Handle integer promotions, though, because they're common and easy.
2159  if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2161  return false;
2162  }
2163  }
2164 
2165  const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
2166 
2167  // Set the DebugLoc for the copy. Use the location of the operand if
2168  // there is one; otherwise no location, flushLocalValueMap will fix it.
2169  DbgLoc = DebugLoc();
2170  if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2171  DbgLoc = Inst->getDebugLoc();
2172 
2173  Register Reg = getRegForValue(PHIOp);
2174  if (!Reg) {
2176  return false;
2177  }
2178  FuncInfo.PHINodesToUpdate.push_back(std::make_pair(&*MBBI++, Reg));
2179  DbgLoc = DebugLoc();
2180  }
2181  }
2182 
2183  return true;
2184 }
2185 
2186 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2187  assert(LI->hasOneUse() &&
2188  "tryToFoldLoad expected a LoadInst with a single use");
2189  // We know that the load has a single use, but don't know what it is. If it
2190  // isn't one of the folded instructions, then we can't succeed here. Handle
2191  // this by scanning the single-use users of the load until we get to FoldInst.
2192  unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2193 
2194  const Instruction *TheUser = LI->user_back();
2195  while (TheUser != FoldInst && // Scan up until we find FoldInst.
2196  // Stay in the right block.
2197  TheUser->getParent() == FoldInst->getParent() &&
2198  --MaxUsers) { // Don't scan too far.
2199  // If there are multiple or no uses of this instruction, then bail out.
2200  if (!TheUser->hasOneUse())
2201  return false;
2202 
2203  TheUser = TheUser->user_back();
2204  }
2205 
2206  // If we didn't find the fold instruction, then we failed to collapse the
2207  // sequence.
2208  if (TheUser != FoldInst)
2209  return false;
2210 
2211  // Don't try to fold volatile loads. Target has to deal with alignment
2212  // constraints.
2213  if (LI->isVolatile())
2214  return false;
2215 
2216  // Figure out which vreg this is going into. If there is no assigned vreg yet
2217  // then there actually was no reference to it. Perhaps the load is referenced
2218  // by a dead instruction.
2219  Register LoadReg = getRegForValue(LI);
2220  if (!LoadReg)
2221  return false;
2222 
2223  // We can't fold if this vreg has no uses or more than one use. Multiple uses
2224  // may mean that the instruction got lowered to multiple MIs, or the use of
2225  // the loaded value ended up being multiple operands of the result.
2226  if (!MRI.hasOneUse(LoadReg))
2227  return false;
2228 
2230  MachineInstr *User = RI->getParent();
2231 
2232  // Set the insertion point properly. Folding the load can cause generation of
2233  // other random instructions (like sign extends) for addressing modes; make
2234  // sure they get inserted in a logical place before the new instruction.
2236  FuncInfo.MBB = User->getParent();
2237 
2238  // Ask the target to try folding the load.
2239  return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2240 }
2241 
2242 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2243  // Must be an add.
2244  if (!isa<AddOperator>(Add))
2245  return false;
2246  // Type size needs to match.
2247  if (DL.getTypeSizeInBits(GEP->getType()) !=
2248  DL.getTypeSizeInBits(Add->getType()))
2249  return false;
2250  // Must be in the same basic block.
2251  if (isa<Instruction>(Add) &&
2252  FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2253  return false;
2254  // Must have a constant operand.
2255  return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2256 }
2257 
2260  const Value *Ptr;
2261  Type *ValTy;
2262  MaybeAlign Alignment;
2264  bool IsVolatile;
2265 
2266  if (const auto *LI = dyn_cast<LoadInst>(I)) {
2267  Alignment = LI->getAlign();
2268  IsVolatile = LI->isVolatile();
2269  Flags = MachineMemOperand::MOLoad;
2270  Ptr = LI->getPointerOperand();
2271  ValTy = LI->getType();
2272  } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2273  Alignment = SI->getAlign();
2274  IsVolatile = SI->isVolatile();
2276  Ptr = SI->getPointerOperand();
2277  ValTy = SI->getValueOperand()->getType();
2278  } else
2279  return nullptr;
2280 
2281  bool IsNonTemporal = I->hasMetadata(LLVMContext::MD_nontemporal);
2282  bool IsInvariant = I->hasMetadata(LLVMContext::MD_invariant_load);
2283  bool IsDereferenceable = I->hasMetadata(LLVMContext::MD_dereferenceable);
2284  const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2285 
2286  AAMDNodes AAInfo;
2287  I->getAAMetadata(AAInfo);
2288 
2289  if (!Alignment) // Ensure that codegen never sees alignment 0.
2290  Alignment = DL.getABITypeAlign(ValTy);
2291 
2292  unsigned Size = DL.getTypeStoreSize(ValTy);
2293 
2294  if (IsVolatile)
2296  if (IsNonTemporal)
2298  if (IsDereferenceable)
2300  if (IsInvariant)
2302 
2304  *Alignment, AAInfo, Ranges);
2305 }
2306 
2308  // If both operands are the same, then try to optimize or fold the cmp.
2310  if (CI->getOperand(0) != CI->getOperand(1))
2311  return Predicate;
2312 
2313  switch (Predicate) {
2314  default: llvm_unreachable("Invalid predicate!");
2331 
2342  }
2343 
2344  return Predicate;
2345 }
llvm::FunctionLoweringInfo::Fn
const Function * Fn
Definition: FunctionLoweringInfo.h:55
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:233
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::InlineAsm::Extra_AsmDialect
@ Extra_AsmDialect
Definition: InlineAsm.h:223
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:597
llvm::MCInstrDesc::getNumDefs
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:244
llvm::CmpInst::FCMP_ULE
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
Definition: InstrTypes.h:737
ValueTypes.h
llvm::DbgVariableIntrinsic::getExpression
DIExpression * getExpression() const
Definition: IntrinsicInst.h:252
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::MachineInstrBuilder::addCImm
const MachineInstrBuilder & addCImm(const ConstantInt *Val) const
Definition: MachineInstrBuilder.h:137
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::MachineInstr::setPhysRegsDeadExcept
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
Definition: MachineInstr.cpp:2044
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::FastISel::CallLoweringInfo::CallConv
CallingConv::ID CallConv
Definition: FastISel.h:84
llvm::DbgDeclareInst::getAddress
Value * getAddress() const
Definition: IntrinsicInst.h:305
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::FastISel::lowerCallTo
bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs)
Definition: FastISel.cpp:967
llvm::FastISel::selectPatchpoint
bool selectPatchpoint(const CallInst *I)
Definition: FastISel.cpp:765
llvm::FastISel::CallLoweringInfo::OutFlags
SmallVector< ISD::ArgFlagsTy, 16 > OutFlags
Definition: FastISel.h:94
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::CmpInst::ICMP_EQ
@ ICMP_EQ
equal
Definition: InstrTypes.h:743
llvm::MachineInstrBuilder::addFPImm
const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const
Definition: MachineInstrBuilder.h:142
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
Optional.h
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:788
llvm::ISD::OR
@ OR
Definition: ISDOpcodes.h:618
llvm::FastISel::getRegForValue
Register getRegForValue(const Value *V)
Create a virtual register and arrange for it to be assigned the value for the given LLVM value.
Definition: FastISel.cpp:241
llvm::ISD::ArgFlagsTy::setSwiftSelf
void setSwiftSelf()
Definition: TargetCallingConv.h:101
llvm::FastISel::~FastISel
virtual ~FastISel()
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:447
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::generic_gep_type_iterator
Definition: GetElementPtrTypeIterator.h:31
llvm::FastISel::fastEmit_f
virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode, const ConstantFP *FPImm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1843
llvm::ISD::BITCAST
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:833
Metadata.h
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::ISD::ArgFlagsTy::setNest
void setNest()
Definition: TargetCallingConv.h:119
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
IntrinsicInst.h
llvm::FastISel::selectCast
bool selectCast(const User *I, unsigned Opcode)
Definition: FastISel.cpp:1354
MCInstrDesc.h
llvm::PointerType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:653
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:70
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::ISD::UDIV
@ UDIV
Definition: ISDOpcodes.h:236
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::DataLayout::getTypeSizeInBits
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:674
llvm::FastISel::updateValueMap
void updateValueMap(const Value *I, Register Reg, unsigned NumRegs=1)
Update the value map to include the new mapping for this instruction, or insert an extra copy to get ...
Definition: FastISel.cpp:365
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:51
llvm::FunctionLoweringInfo::InsertPt
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
Definition: FunctionLoweringInfo.h:153
GetElementPtrTypeIterator.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:124
llvm::FastISel::fastEmit_ri_
Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, uint64_t Imm, MVT ImmType)
This method is a wrapper of fastEmit_ri.
Definition: FastISel.cpp:1857
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::FastISel::fastEmitInst_f
Register fastEmitInst_f(unsigned MachineInstOpcode, const TargetRegisterClass *RC, const ConstantFP *FPImm)
Emit a MachineInstr with a floating point immediate, and a result register in the given register clas...
Definition: FastISel.cpp:2037
Statistic.h
InlineAsm.h
llvm::FastISel::CallLoweringInfo::setIsPatchPoint
CallLoweringInfo & setIsPatchPoint(bool Value=true)
Definition: FastISel.h:181
llvm::FastISel::FastISel
FastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo, bool SkipTargetIndependentISel=false)
Definition: FastISel.cpp:1806
llvm::FastISel::CallLoweringInfo::ResultReg
Register ResultReg
Definition: FastISel.h:90
llvm::FastISel::CallLoweringInfo::InRegs
SmallVector< Register, 4 > InRegs
Definition: FastISel.h:97
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::FastISel::finishBasicBlock
void finishBasicBlock()
Flush the local value map.
Definition: FastISel.cpp:137
llvm::CmpInst::FCMP_ONE
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
Definition: InstrTypes.h:730
llvm::DataLayout::getTypeStoreSize
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:466
ErrorHandling.h
llvm::FastISel::lowerArguments
bool lowerArguments()
Do "fast" instruction selection for function arguments and append the machine instructions to the cur...
Definition: FastISel.cpp:139
llvm::FastISel::fastEmitZExtFromI1
Register fastEmitZExtFromI1(MVT VT, unsigned Op0)
Emit MachineInstrs to compute the value of Op with all but the least significant bit set to zero.
Definition: FastISel.cpp:2111
llvm::ISD::InputArg::Used
bool Used
Definition: TargetCallingConv.h:207
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::ISD::EH_LABEL
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:973
llvm::CmpInst::ICMP_NE
@ ICMP_NE
not equal
Definition: InstrTypes.h:744
llvm::FastISel::selectFreeze
bool selectFreeze(const User *I)
Definition: FastISel.cpp:1433
llvm::AttributeList::get
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute >> Attrs)
Create an AttributeList with the specified parameters in it.
Definition: Attributes.cpp:1175
llvm::FastISel::enterLocalValueArea
SavePoint enterLocalValueArea()
Prepare InsertPt to begin inserting instructions into the local value area and return the old insert ...
Definition: FastISel.cpp:438
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MachineBasicBlock.h
llvm::ISD::FP_TO_SINT
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:770
llvm::CmpInst::ICMP_SGT
@ ICMP_SGT
signed greater than
Definition: InstrTypes.h:749
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:312
llvm::FastISel::CallLoweringInfo::OutVals
SmallVector< Value *, 16 > OutVals
Definition: FastISel.h:93
llvm::DenseMapIterator
Definition: DenseMap.h:56
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
DenseMap.h
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:84
llvm::FunctionLoweringInfo::MBB
MachineBasicBlock * MBB
MBB - The current block.
Definition: FunctionLoweringInfo.h:150
llvm::AttributeList
Definition: Attributes.h:375
llvm::FastISel::fastEmitInst_rii
Register fastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm1, uint64_t Imm2)
Emit a MachineInstr with one register operand and two immediate operands.
Definition: FastISel.cpp:2013
TargetInstrInfo.h
llvm::PatchPointOpers::CCPos
@ CCPos
Definition: StackMaps.h:79
llvm::FastISel::fastEmit_rr
virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1834
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::CallBase::getFunctionType
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1244
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::FastISel::CallLoweringInfo::RetSExt
bool RetSExt
Definition: FastISel.h:71
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
llvm::ComputeLinearIndex
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
Definition: Analysis.cpp:36
llvm::DbgVariableIntrinsic::getVariable
DILocalVariable * getVariable() const
Definition: IntrinsicInst.h:248
llvm::Optional
Definition: APInt.h:33
llvm::FastISel::TLI
const TargetLowering & TLI
Definition: FastISel.h:211
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
llvm::Triple::isOSLinux
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:595
Operator.h
llvm::CmpInst::ICMP_SLE
@ ICMP_SLE
signed less or equal
Definition: InstrTypes.h:752
llvm::CallBase::getNumArgOperands
unsigned getNumArgOperands() const
Definition: InstrTypes.h:1339
llvm::CallBase::arg_begin
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
Definition: InstrTypes.h:1306
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::CmpInst::FCMP_OGT
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
Definition: InstrTypes.h:726
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::FastISel::getRegForGEPIndex
Register getRegForGEPIndex(const Value *Idx)
This is a wrapper around getRegForValue that also takes care of truncating or sign-extending the give...
Definition: FastISel.cpp:386
llvm::MachineRegisterInfo::defusechain_iterator::getOperandNo
unsigned getOperandNo() const
getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.
Definition: MachineRegisterInfo.h:1056
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::FastISel::CallLoweringInfo::RetZExt
bool RetZExt
Definition: FastISel.h:72
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:965
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:146
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
MachineValueType.h
llvm::CmpInst::FCMP_ULT
@ FCMP_ULT
1 1 0 0 True if unordered or less than
Definition: InstrTypes.h:736
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::MachineFrameInfo::setHasStackMap
void setHasStackMap(bool s=true)
Definition: MachineFrameInfo.h:379
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
Instruction.h
llvm::MachineBasicBlock::reverse_iterator
MachineInstrBundleIterator< MachineInstr, true > reverse_iterator
Definition: MachineBasicBlock.h:235
llvm::ISD::InputArg::ArgVT
EVT ArgVT
Definition: TargetCallingConv.h:206
TargetLowering.h
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::Instruction::getNumSuccessors
unsigned getNumSuccessors() const
Return the number of successors that this instruction has.
Definition: Instruction.cpp:736
llvm::Intrinsic::getType
FunctionType * getType(LLVMContext &Context, ID id, ArrayRef< Type * > Tys=None)
Return the function type for an intrinsic.
Definition: Function.cpp:1247
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:40
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:157
llvm::APFloat::convertToInteger
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
Definition: APFloat.h:1107
llvm::Log2_64
unsigned Log2_64(uint64_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:603
GlobalValue.h
TargetMachine.h
llvm::MachineInstr::setHeapAllocMarker
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
Definition: MachineInstr.cpp:505
llvm::FastISel::FuncInfo
FunctionLoweringInfo & FuncInfo
Definition: FastISel.h:202
Constants.h
llvm::ISD::Constant
@ Constant
Definition: ISDOpcodes.h:69
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:714
llvm::FunctionLoweringInfo::MBBMap
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
Definition: FunctionLoweringInfo.h:73
llvm::DbgValueInst
This represents the llvm.dbg.value instruction.
Definition: IntrinsicInst.h:342
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:770
SmallString.h
FunctionLoweringInfo.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::InlineAsm::Extra_HasSideEffects
@ Extra_HasSideEffects
Definition: InlineAsm.h:221
llvm::FastISel::createResultReg
Register createResultReg(const TargetRegisterClass *RC)
Definition: FastISel.cpp:1892
llvm::User
Definition: User.h:44
llvm::LibFunc
LibFunc
Definition: TargetLibraryInfo.h:34
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::FastISel::CallLoweringInfo::clearIns
void clearIns()
Definition: FastISel.h:194
llvm::CmpInst::ICMP_ULE
@ ICMP_ULE
unsigned less or equal
Definition: InstrTypes.h:748
InstrTypes.h
llvm::BasicBlock::begin
iterator begin()
Instruction iterator methods.
Definition: BasicBlock.h:296
MCContext.h
llvm::FastISel::CallLoweringInfo::CB
const CallBase * CB
Definition: FastISel.h:88
llvm::FastISel::leaveLocalValueArea
void leaveLocalValueArea(SavePoint Old)
Reset InsertPt to the given old insert position.
Definition: FastISel.cpp:444
SI
@ SI
Definition: SIInstrInfo.cpp:7342
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::CmpInst::FCMP_UGE
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
Definition: InstrTypes.h:735
llvm::FastISel::selectXRayTypedEvent
bool selectXRayTypedEvent(const CallInst *II)
Definition: FastISel.cpp:922
llvm::ISD::TRUNCATE
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:720
llvm::ISD::SRA
@ SRA
Definition: ISDOpcodes.h:643
TargetLibraryInfo.h
addStackMapLiveVars
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
Definition: SelectionDAGBuilder.cpp:8958
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::Mangler::getNameWithPrefix
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
Definition: Mangler.cpp:114
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::FastISel::fastEmit_
virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode)
This method is called by target-independent code to request that an instruction with the given type a...
Definition: FastISel.cpp:1828
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::CmpInst::FCMP_UNO
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
Definition: InstrTypes.h:732
llvm::Instruction
Definition: Instruction.h:45
llvm::DataLayout::getABITypeAlign
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:825
llvm::ISD::SINT_TO_FP
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:724
llvm::APSInt
An arbitrary precision integer that knows its signedness.
Definition: APSInt.h:22
llvm::BasicBlock::phis
iterator_range< const_phi_iterator > phis() const
Returns a range that iterates over the phis in the basic block.
Definition: BasicBlock.h:354
llvm::FastISel::selectStackmap
bool selectStackmap(const CallInst *I)
Definition: FastISel.cpp:653
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:255
isCommutative
static bool isCommutative(Instruction *I)
Definition: SLPVectorizer.cpp:240
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:584
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::FastISel::fastEmit_ri
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1848
llvm::MachineOperand::CreateFI
static MachineOperand CreateFI(int Idx)
Definition: MachineOperand.h:820
llvm::FastISel::CallLoweringInfo::IsInReg
bool IsInReg
Definition: FastISel.h:74
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:885
llvm::DILocalVariable::isValidLocationForIntrinsic
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Definition: DebugInfoMetadata.h:3110
llvm::FastISel::CallLoweringInfo::clearOuts
void clearOuts()
Definition: FastISel.h:188
llvm::CmpInst::FCMP_OEQ
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
Definition: InstrTypes.h:725
DebugLoc.h
SmallPtrSet.h
llvm::Instruction::getSuccessor
BasicBlock * getSuccessor(unsigned Idx) const
Return the specified successor. This instruction must be a terminator.
Definition: Instruction.cpp:748
llvm::FastISel::MRI
MachineRegisterInfo & MRI
Definition: FastISel.h:204
llvm::FastISel::CallLoweringInfo::Call
MachineInstr * Call
Definition: FastISel.h:89
llvm::CmpInst::FCMP_OLT
@ FCMP_OLT
0 1 0 0 True if ordered and less than
Definition: InstrTypes.h:728
llvm::ISD::AND
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:617
llvm::ISD::ArgFlagsTy::setInReg
void setInReg()
Definition: TargetCallingConv.h:83
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
PatternMatch.h
llvm::CallInst::isTailCall
bool isTailCall() const
Definition: Instructions.h:1644
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:154
llvm::PatchPointOpers::TargetPos
@ TargetPos
Definition: StackMaps.h:79
llvm::Triple::getArch
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:307
llvm::CallBase::getCallingConv
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1453
llvm::PatchPointOpers::NBytesPos
@ NBytesPos
Definition: StackMaps.h:79
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:235
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:185
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:265
llvm::FastISel::createMachineMemOperandFor
MachineMemOperand * createMachineMemOperandFor(const Instruction *I) const
Create a machine mem operand from the given instruction.
Definition: FastISel.cpp:2259
llvm::FunctionLoweringInfo::OrigNumPHINodesToUpdate
unsigned OrigNumPHINodesToUpdate
Definition: FunctionLoweringInfo.h:176
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::Instruction::getMetadata
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:277
llvm::SmallString< 32 >
llvm::ISD::ArgFlagsTy::setSExt
void setSExt()
Definition: TargetCallingConv.h:80
llvm::CmpInst::FCMP_FALSE
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:724
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:712
llvm::FastISel::fastLowerIntrinsicCall
virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II)
This method is called by target-independent code to do target- specific intrinsic lowering.
Definition: FastISel.cpp:1824
llvm::ISD::FADD
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:371
llvm::InlineAsm
Definition: InlineAsm.h:31
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
BasicBlock.h
llvm::APFloat
Definition: APFloat.h:701
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:378
llvm::FastISel::CallLoweringInfo::NumResultRegs
unsigned NumResultRegs
Definition: FastISel.h:91
llvm::FastISel::selectInstruction
bool selectInstruction(const Instruction *I)
Do "fast" instruction selection for the given LLVM IR instruction and append the generated machine in...
Definition: FastISel.cpp:1473
llvm::FastISel::DbgLoc
DebugLoc DbgLoc
Definition: FastISel.h:207
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
VI
@ VI
Definition: SIInstrInfo.cpp:7343
BranchProbabilityInfo.h
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:333
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::FastISel::tryToFoldLoadIntoMI
virtual bool tryToFoldLoadIntoMI(MachineInstr *, unsigned, const LoadInst *)
The specified machine instr operand is a vreg, and that vreg is being provided by the specified load ...
Definition: FastISel.h:299
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
Definition: TargetLowering.h:881
llvm::DbgDeclareInst
This represents the llvm.dbg.declare instruction.
Definition: IntrinsicInst.h:303
llvm::DbgLabelInst
This represents the llvm.dbg.label instruction.
Definition: IntrinsicInst.h:365
llvm::Instruction::user_back
Instruction * user_back()
Specialize the methods defined in Value, as we know that an instruction can only be used by other ins...
Definition: Instruction.h:91
llvm::FastISel::fastLowerCall
virtual bool fastLowerCall(CallLoweringInfo &CLI)
This method is called by target-independent code to do target- specific call lowering.
Definition: FastISel.cpp:1822
llvm::FastISel::fastEmit_i
virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1839
llvm::FastISel::fastEmitBranch
void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc)
Emit an unconditional branch to the given block, unless it is the immediate (fall-through) successor,...
Definition: FastISel.cpp:1557
llvm::PatchPointOpers::NArgPos
@ NArgPos
Definition: StackMaps.h:79
llvm::DbgLabelInst::getLabel
DILabel * getLabel() const
Definition: IntrinsicInst.h:367
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1073
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::FastISel::CallLoweringInfo::getArgs
ArgListTy & getArgs()
Definition: FastISel.h:186
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:58
llvm::FastISel::selectIntrinsicCall
bool selectIntrinsicCall(const IntrinsicInst *II)
Definition: FastISel.cpp:1194
llvm::InlineAsm::Extra_IsConvergent
@ Extra_IsConvergent
Definition: InlineAsm.h:226
llvm::PatchPointOpers::IDPos
@ IDPos
Definition: StackMaps.h:79
findLocalRegDef
static Register findLocalRegDef(MachineInstr &MI)
Return the defined register if this instruction defines exactly one virtual register and uses no othe...
Definition: FastISel.cpp:161
llvm::FastISel::fastEmitInst_rri
Register fastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, uint64_t Imm)
Emit a MachineInstr with two register operands, an immediate, and a result register in the given regi...
Definition: FastISel.cpp:2056
DebugInfo.h
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:529
I
#define I(x, y, z)
Definition: MD5.cpp:59
Analysis.h
MCRegisterInfo.h
llvm::PointerType
Class to represent pointers.
Definition: DerivedTypes.h:634
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(Align A)
Definition: TargetCallingConv.h:172
llvm::FastISel::CallLoweringInfo::IsReturnValueUsed
bool IsReturnValueUsed
Definition: FastISel.h:76
llvm::FastISel::CallLoweringInfo
Definition: FastISel.h:69
llvm::HighlightColor::Address
@ Address
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::ISD::InputArg
InputArg - This struct carries flags and type information about a single incoming (formal) argument o...
Definition: TargetCallingConv.h:203
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
llvm::FastISel::fastEmit_r
virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0)
This method is called by target-independent code to request that an instruction with the given type,...
Definition: FastISel.cpp:1830
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:65
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:39
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:815
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:270
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::ISD::ArgFlagsTy::setInConsecutiveRegs
void setInConsecutiveRegs(bool Flag=true)
Definition: TargetCallingConv.h:125
llvm::CmpInst::FCMP_OGE
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
Definition: InstrTypes.h:727
llvm::ISD::ArgFlagsTy::setSwiftError
void setSwiftError()
Definition: TargetCallingConv.h:104
llvm::FastISel::fastEmitInst_
Register fastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass *RC)
Emit a MachineInstr with no operands and a result register in the given register class.
Definition: FastISel.cpp:1913
llvm::CmpInst::ICMP_UGE
@ ICMP_UGE
unsigned greater or equal
Definition: InstrTypes.h:746
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
llvm::FastISel::fastLowerArguments
virtual bool fastLowerArguments()
This method is called by target-independent code to do target- specific argument lowering.
Definition: FastISel.cpp:1820
APSInt.h
llvm::FastISel::ArgListTy
TargetLoweringBase::ArgListTy ArgListTy
Definition: FastISel.h:68
MachineModuleInfo.h
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MDNode
Metadata node.
Definition: Metadata.h:897
llvm::ISD::ArgFlagsTy::setByVal
void setByVal()
Definition: TargetCallingConv.h:89
llvm::CallBase::arg_end
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
Definition: InstrTypes.h:1312
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:649
llvm::BranchInst::isUnconditional
bool isUnconditional() const
Definition: Instructions.h:3083
llvm::ISD::ArgFlagsTy::setByValSize
void setByValSize(unsigned S)
Definition: TargetCallingConv.h:181
Mangler.h
llvm::CmpInst::ICMP_SLT
@ ICMP_SLT
signed less than
Definition: InstrTypes.h:751
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::FastISel::selectOperator
bool selectOperator(const User *I, unsigned Opcode)
Do "fast" instruction selection for the given LLVM IR operator (Instruction or ConstantExpr),...
Definition: FastISel.cpp:1678
llvm::FastISel::CallLoweringInfo::IsVarArg
bool IsVarArg
Definition: FastISel.h:73
TargetOptions.h
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::CreateGA
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:847
DataLayout.h
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:44
llvm::StructType
Class to represent struct types.
Definition: DerivedTypes.h:212
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::ISD::ArgFlagsTy::setInAlloca
void setInAlloca()
Definition: TargetCallingConv.h:95
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::CmpInst::ICMP_ULT
@ ICMP_ULT
unsigned less than
Definition: InstrTypes.h:747
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::FastISel::canFoldAddIntoGEP
bool canFoldAddIntoGEP(const User *GEP, const Value *Add)
Check if Add is an add that can be safely folded into GEP.
Definition: FastISel.cpp:2242
llvm::ISD::SREM
@ SREM
Definition: ISDOpcodes.h:237
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
uint32_t
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::Value::getContext
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:937
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::ArgFlagsTy::setByValAlign
void setByValAlign(Align A)
Definition: TargetCallingConv.h:154
llvm::AMDGPU::HSAMD::Kernel::Arg::Key::IsVolatile
constexpr char IsVolatile[]
Key for Kernel::Arg::Metadata::mIsVolatile.
Definition: AMDGPUMetadata.h:194
llvm::Type::getContext
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:128
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:174
isRegUsedByPhiNodes
static bool isRegUsedByPhiNodes(Register DefReg, FunctionLoweringInfo &FuncInfo)
Definition: FastISel.cpp:178
llvm::ISD::FMUL
@ FMUL
Definition: ISDOpcodes.h:373
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::BasicBlock::getTerminator
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
Definition: BasicBlock.cpp:148
llvm::ISD::InputArg::Flags
ArgFlagsTy Flags
Definition: TargetCallingConv.h:204
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::FastISel::fastEmitInst_ri
Register fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, uint64_t Imm)
Emit a MachineInstr with a register operand, an immediate, and a result register in the given registe...
Definition: FastISel.cpp:1991
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::XOR
@ XOR
Definition: ISDOpcodes.h:619
Argument.h
llvm::ISD::ArgFlagsTy::setCFGuardTarget
void setCFGuardTarget()
Definition: TargetCallingConv.h:107
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:205
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::CmpInst::FCMP_UGT
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
Definition: InstrTypes.h:734
llvm::MachineRegisterInfo::reg_begin
reg_iterator reg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:281
Constant.h
llvm::FastISel::tryToFoldLoad
bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst)
We're checking to see if we can fold LI into FoldInst.
Definition: FastISel.cpp:2186
llvm::APFloatBase::rmTowardZero
static constexpr roundingMode rmTowardZero
Definition: APFloat.h:194
llvm::Constant::getNullValue
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:347
llvm::FastISel::lowerCall
bool lowerCall(const CallInst *I)
Definition: FastISel.cpp:1117
llvm::FastISel::selectExtractValue
bool selectExtractValue(const User *U)
Definition: FastISel.cpp:1638
getReturnAttrs
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
Definition: FastISel.cpp:945
llvm::FastISel::CallLoweringInfo::OutRegs
SmallVector< Register, 16 > OutRegs
Definition: FastISel.h:95
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
MachineFrameInfo.h
llvm::FastISel::selectFNeg
bool selectFNeg(const User *I, const Value *In)
Emit an FNeg operation.
Definition: FastISel.cpp:1596
llvm::Type::isEmptyTy
bool isEmptyTy() const
Return true if this type is empty, that is, it has no elements or all of its elements are empty.
Definition: Type.cpp:112
llvm::CallBase::arg_size
unsigned arg_size() const
Definition: InstrTypes.h:1329
llvm::ExtractValueInst
This instruction extracts a struct member or array element value from an aggregate value.
Definition: Instructions.h:2318
ISDOpcodes.h
Casting.h
Function.h
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:207
llvm::ISD::SDIV
@ SDIV
Definition: ISDOpcodes.h:235
llvm::FastISel::CallLoweringInfo::RetTy
Type * RetTy
Definition: FastISel.h:70
StackMaps.h
llvm::FastISel::selectXRayCustomEvent
bool selectXRayCustomEvent(const CallInst *II)
Definition: FastISel.cpp:903
llvm::ISD::InputArg::VT
MVT VT
Definition: TargetCallingConv.h:205
llvm::CmpInst::ICMP_SGE
@ ICMP_SGE
signed greater or equal
Definition: InstrTypes.h:750
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::CallBase::getCalledOperand
Value * getCalledOperand() const
Definition: InstrTypes.h:1389
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:232
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
Predicate
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:187
FastISel.h
llvm::FastISel::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 4 > Ins
Definition: FastISel.h:96
llvm::FastISel::selectGetElementPtr
bool selectGetElementPtr(const User *I)
Definition: FastISel.cpp:540
Instructions.h
llvm::FunctionLoweringInfo::MF
MachineFunction * MF
Definition: FunctionLoweringInfo.h:56
llvm::ISD::FSUB
@ FSUB
Definition: ISDOpcodes.h:372
llvm::GetReturnInfo
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
Definition: TargetLoweringBase.cpp:1618
llvm::ISD::SHL
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:642
llvm::LoadInst::isVolatile
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:211
llvm::MachineRegisterInfo::hasOneUse
bool hasOneUse(Register RegNo) const
hasOneUse - Return true if there is exactly one instruction using the specified register.
Definition: MachineRegisterInfo.h:510
SmallVector.h
llvm::ISD::FREM
@ FREM
Definition: ISDOpcodes.h:375
llvm::MachineOperand::CreateRegMask
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
Definition: MachineOperand.h:883
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::Instruction::getDebugLoc
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:365
User.h
MachineInstrBuilder.h
llvm::ISD::MUL
@ MUL
Definition: ISDOpcodes.h:234
llvm::ISD::UREM
@ UREM
Definition: ISDOpcodes.h:238
llvm::CmpInst::ICMP_UGT
@ ICMP_UGT
unsigned greater than
Definition: InstrTypes.h:745
llvm::ISD::ArgFlagsTy::setSRet
void setSRet()
Definition: TargetCallingConv.h:86
llvm::DbgValueInst::getValue
Value * getValue(unsigned OpIdx=0) const
Definition: IntrinsicInst.h:346
llvm::InlineAsm::Extra_IsAlignStack
@ Extra_IsAlignStack
Definition: InlineAsm.h:222
llvm::CmpInst::FCMP_UNE
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
Definition: InstrTypes.h:738
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::CallBase::getArgOperand
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1341
N
#define N
llvm::FastISel::fastEmitInst_rrr
Register fastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1, unsigned Op2)
Emit a MachineInstr with three register operands and a result register in the given register class.
Definition: FastISel.cpp:1965
llvm::Instruction::getParent
const BasicBlock * getParent() const
Definition: Instruction.h:94
llvm::ISD::SRL
@ SRL
Definition: ISDOpcodes.h:644
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::FastISel::removeDeadCode
void removeDeadCode(MachineBasicBlock::iterator I, MachineBasicBlock::iterator E)
Remove all dead instructions between the I and E.
Definition: FastISel.cpp:418
llvm::CmpInst::getPredicate
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:799
llvm::FastISel::CallLoweringInfo::setTailCall
CallLoweringInfo & setTailCall(bool Value=true)
Definition: FastISel.h:176
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
Definition: TargetLowering.h:838
llvm::isInTailCallPosition
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:501
llvm::PHINode
Definition: Instructions.h:2572
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
llvm::MachineInstrBuilder::addMetadata
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
Definition: MachineInstrBuilder.h:237
MachineMemOperand.h
llvm::CmpInst::FCMP_OLE
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
Definition: InstrTypes.h:729
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::sys::path::rend
reverse_iterator rend(StringRef path)
Get reverse end iterator over path.
Definition: Path.cpp:304
MachineOperand.h
DerivedTypes.h
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:249
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:276
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::FastISel::TRI
const TargetRegisterInfo & TRI
Definition: FastISel.h:212
llvm::ISD::FNEG
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:851
llvm::FastISel::selectCall
bool selectCall(const User *I)
Definition: FastISel.cpp:1157
llvm::ISD::ArgFlagsTy::setPreallocated
void setPreallocated()
Definition: TargetCallingConv.h:98
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::FunctionLoweringInfo::PHINodesToUpdate
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
Definition: FunctionLoweringInfo.h:175
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
LLVMContext.h
llvm::OptimizedStructLayoutField
A field in a structure.
Definition: OptimizedStructLayout.h:45
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
selectBinaryOp
static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV),...
Definition: AArch64InstructionSelector.cpp:658
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::FastISel::optimizeCmpPredicate
CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const
Definition: FastISel.cpp:2307
llvm::FastISel::CallLoweringInfo::setCallee
CallLoweringInfo & setCallee(Type *ResultTy, FunctionType *FuncTy, const Value *Target, ArgListTy &&ArgsList, const CallBase &Call)
Definition: FastISel.h:103
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1382
llvm::FastISel::selectBitCast
bool selectBitCast(const User *I)
Definition: FastISel.cpp:1385
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3005
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:711
raw_ostream.h
llvm::FastISel::TII
const TargetInstrInfo & TII
Definition: FastISel.h:210
llvm::FastISel::fastEmitInst_extractsubreg
Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, uint32_t Idx)
Emit a MachineInstr for an extract_subreg from a specified index of a superregister to a specified ty...
Definition: FastISel.cpp:2097
llvm::LLVMContext::OB_funclet
@ OB_funclet
Definition: LLVMContext.h:91
llvm::FastISel::lookUpRegForValue
Register lookUpRegForValue(const Value *V)
Look up the value to see if its value is already cached in a register.
Definition: FastISel.cpp:354
llvm::FastISel::finishCondBranch
void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB)
Emit an unconditional branch to FalseMBB, obtains the branch weight and adds TrueMBB and FalseMBB to ...
Definition: FastISel.cpp:1577
llvm::CmpInst::FCMP_TRUE
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:739
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:497
Value.h
llvm::FastISel::fastEmitInst_rr
Register fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, unsigned Op1)
Emit a MachineInstr with two register operands and a result register in the given register class.
Definition: FastISel.cpp:1942
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:229
llvm::ExtractValueInst::getIndices
ArrayRef< unsigned > getIndices() const
Definition: Instructions.h:2383
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::FastISel::DL
const DataLayout & DL
Definition: FastISel.h:209
llvm::FastISel::selectBinaryOp
bool selectBinaryOp(const User *I, unsigned ISDOpcode)
Select and emit code for a binary operator instruction, which has an opcode which directly correspond...
Definition: FastISel.cpp:452
Debug.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::FastISel::recomputeInsertPt
void recomputeInsertPt()
Reset InsertPt to prepare for inserting instructions into the current block.
Definition: FastISel.cpp:404
llvm::FastISel::startNewBlock
void startNewBlock()
Set the current block to which generated machine instructions will be appended.
Definition: FastISel.cpp:124
llvm::CmpInst::FCMP_ORD
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
Definition: InstrTypes.h:731
llvm::BranchInst::getSuccessor
BasicBlock * getSuccessor(unsigned i) const
Definition: Instructions.h:3098
llvm::ISD::ArgFlagsTy::setZExt
void setZExt()
Definition: TargetCallingConv.h:77
llvm::FastISel::constrainOperandRegClass
Register constrainOperandRegClass(const MCInstrDesc &II, Register Op, unsigned OpNum)
Try to constrain Op so that it is usable by argument OpNum of the provided MCInstrDesc.
Definition: FastISel.cpp:1896
llvm::FastISel::fastEmitInst_r
Register fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0)
Emit a MachineInstr with one register operand and a result register in the given register class.
Definition: FastISel.cpp:1922
llvm::FastISel::fastEmitInst_i
Register fastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm)
Emit a MachineInstr with a single immediate operand, and a result register in the given register clas...
Definition: FastISel.cpp:2081
llvm::CmpInst::FCMP_UEQ
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
Definition: InstrTypes.h:733
llvm::FunctionType
Class to represent function types.
Definition: DerivedTypes.h:102
llvm::MCInstrDesc::ImplicitDefs
const MCPhysReg * ImplicitDefs
Definition: MCInstrDesc.h:206
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::ISD::FDIV
@ FDIV
Definition: ISDOpcodes.h:374