LLVM 17.0.0git
HexagonAsmPrinter.cpp
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1//===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to Hexagon assembly language. This printer is
11// the output mechanism used by `llc'.
12//
13//===----------------------------------------------------------------------===//
14
15#include "HexagonAsmPrinter.h"
16#include "Hexagon.h"
17#include "HexagonInstrInfo.h"
18#include "HexagonRegisterInfo.h"
19#include "HexagonSubtarget.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/Twine.h"
36#include "llvm/MC/MCContext.h"
38#include "llvm/MC/MCExpr.h"
39#include "llvm/MC/MCInst.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSymbol.h"
49#include <algorithm>
50#include <cassert>
51#include <cstdint>
52#include <string>
53
54using namespace llvm;
55
56namespace llvm {
57
58void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
59 MCInst &MCB, HexagonAsmPrinter &AP);
60
61} // end namespace llvm
62
63#define DEBUG_TYPE "asm-printer"
64
65// Given a scalar register return its pair.
66inline static unsigned getHexagonRegisterPair(unsigned Reg,
67 const MCRegisterInfo *RI) {
68 assert(Hexagon::IntRegsRegClass.contains(Reg));
69 MCSuperRegIterator SR(Reg, RI, false);
70 unsigned Pair = *SR;
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
72 return Pair;
73}
74
76 raw_ostream &O) {
77 const MachineOperand &MO = MI->getOperand(OpNo);
78
79 switch (MO.getType()) {
80 default:
81 llvm_unreachable ("<unknown operand type>");
84 return;
86 O << MO.getImm();
87 return;
89 MO.getMBB()->getSymbol()->print(O, MAI);
90 return;
92 GetCPISymbol(MO.getIndex())->print(O, MAI);
93 return;
95 PrintSymbolOperand(MO, O);
96 return;
97 }
98}
99
100// isBlockOnlyReachableByFallthrough - We need to override this since the
101// default AsmPrinter does not print labels for any basic block that
102// is only reachable by a fall through. That works for all cases except
103// for the case in which the basic block is reachable by a fall through but
104// through an indirect from a jump table. In this case, the jump table
105// will contain a label not defined by AsmPrinter.
107 const MachineBasicBlock *MBB) const {
108 if (MBB->hasAddressTaken())
109 return false;
111}
112
113/// PrintAsmOperand - Print out an operand for an inline asm expression.
115 const char *ExtraCode,
116 raw_ostream &OS) {
117 // Does this asm operand have a single letter operand modifier?
118 if (ExtraCode && ExtraCode[0]) {
119 if (ExtraCode[1] != 0)
120 return true; // Unknown modifier.
121
122 switch (ExtraCode[0]) {
123 default:
124 // See if this is a generic print operand
125 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
126 case 'L':
127 case 'H': { // The highest-numbered register of a pair.
128 const MachineOperand &MO = MI->getOperand(OpNo);
129 const MachineFunction &MF = *MI->getParent()->getParent();
131 if (!MO.isReg())
132 return true;
133 Register RegNumber = MO.getReg();
134 // This should be an assert in the frontend.
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
137 Hexagon::isub_lo :
138 Hexagon::isub_hi);
140 return false;
141 }
142 case 'I':
143 // Write 'i' if an integer constant, otherwise nothing. Used to print
144 // addi vs add, etc.
145 if (MI->getOperand(OpNo).isImm())
146 OS << "i";
147 return false;
148 }
149 }
150
151 printOperand(MI, OpNo, OS);
152 return false;
153}
154
156 unsigned OpNo,
157 const char *ExtraCode,
158 raw_ostream &O) {
159 if (ExtraCode && ExtraCode[0])
160 return true; // Unknown modifier.
161
162 const MachineOperand &Base = MI->getOperand(OpNo);
163 const MachineOperand &Offset = MI->getOperand(OpNo+1);
164
165 if (Base.isReg())
166 printOperand(MI, OpNo, O);
167 else
168 llvm_unreachable("Unimplemented");
169
170 if (Offset.isImm()) {
171 if (Offset.getImm())
172 O << "+#" << Offset.getImm();
173 } else {
174 llvm_unreachable("Unimplemented");
175 }
176
177 return false;
178}
179
181 MCStreamer &OutStreamer, const MCOperand &Imm,
182 int AlignSize, const MCSubtargetInfo& STI) {
183 MCSymbol *Sym;
184 int64_t Value;
185 if (Imm.getExpr()->evaluateAsAbsolute(Value)) {
186 StringRef sectionPrefix;
187 std::string ImmString;
189 if (AlignSize == 8) {
190 Name = ".CONST_0000000000000000";
191 sectionPrefix = ".gnu.linkonce.l8";
192 ImmString = utohexstr(Value);
193 } else {
194 Name = ".CONST_00000000";
195 sectionPrefix = ".gnu.linkonce.l4";
196 ImmString = utohexstr(static_cast<uint32_t>(Value));
197 }
198
199 std::string symbolName = // Yes, leading zeros are kept.
200 Name.drop_back(ImmString.size()).str() + ImmString;
201 std::string sectionName = sectionPrefix.str() + symbolName;
202
203 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
205 OutStreamer.switchSection(Section);
206
207 Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName));
208 if (Sym->isUndefined()) {
209 OutStreamer.emitLabel(Sym);
210 OutStreamer.emitSymbolAttribute(Sym, MCSA_Global);
211 OutStreamer.emitIntValue(Value, AlignSize);
212 OutStreamer.emitCodeAlignment(Align(AlignSize), &STI);
213 }
214 } else {
215 assert(Imm.isExpr() && "Expected expression and found none");
216 const MachineOperand &MO = MI.getOperand(1);
217 assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
218 MCSymbol *MOSymbol = nullptr;
219 if (MO.isGlobal())
220 MOSymbol = AP.getSymbol(MO.getGlobal());
221 else if (MO.isCPI())
222 MOSymbol = AP.GetCPISymbol(MO.getIndex());
223 else if (MO.isJTI())
224 MOSymbol = AP.GetJTISymbol(MO.getIndex());
225 else
226 llvm_unreachable("Unknown operand type!");
227
228 StringRef SymbolName = MOSymbol->getName();
229 std::string LitaName = ".CONST_" + SymbolName.str();
230
231 MCSectionELF *Section = OutStreamer.getContext().getELFSection(
233
234 OutStreamer.switchSection(Section);
235 Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName));
236 if (Sym->isUndefined()) {
237 OutStreamer.emitLabel(Sym);
238 OutStreamer.emitSymbolAttribute(Sym, MCSA_Local);
239 OutStreamer.emitValue(Imm.getExpr(), AlignSize);
240 OutStreamer.emitCodeAlignment(Align(AlignSize), &STI);
241 }
242 }
243 return Sym;
244}
245
246static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
247 unsigned VectorSize, MCContext &Ctx) {
248 MCInst T;
249 T.setOpcode(Inst.getOpcode());
250 for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) {
251 if (i != OpNo) {
252 T.addOperand(Inst.getOperand(i));
253 continue;
254 }
255 MCOperand &ImmOp = Inst.getOperand(i);
256 const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr());
257 int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
258 auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx);
259 auto *NewHE = HexagonMCExpr::create(NewCE, Ctx);
260 T.addOperand(MCOperand::createExpr(NewHE));
261 }
262 return T;
263}
264
266 const MachineInstr &MI) {
267 MCInst &MappedInst = static_cast <MCInst &>(Inst);
268 const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
269 const MachineFunction &MF = *MI.getParent()->getParent();
270 auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
272
273 switch (Inst.getOpcode()) {
274 default:
275 return;
276
277 case Hexagon::A2_iconst: {
278 Inst.setOpcode(Hexagon::A2_addi);
279 MCOperand Reg = Inst.getOperand(0);
280 MCOperand S16 = Inst.getOperand(1);
283 Inst.clear();
284 Inst.addOperand(Reg);
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0));
286 Inst.addOperand(S16);
287 break;
288 }
289
290 case Hexagon::A2_tfrf: {
292 Inst.setOpcode(Hexagon::A2_paddif);
294 break;
295 }
296
297 case Hexagon::A2_tfrt: {
299 Inst.setOpcode(Hexagon::A2_paddit);
301 break;
302 }
303
304 case Hexagon::A2_tfrfnew: {
306 Inst.setOpcode(Hexagon::A2_paddifnew);
308 break;
309 }
310
311 case Hexagon::A2_tfrtnew: {
313 Inst.setOpcode(Hexagon::A2_padditnew);
315 break;
316 }
317
318 case Hexagon::A2_zxtb: {
320 Inst.setOpcode(Hexagon::A2_andir);
322 break;
323 }
324
325 // "$dst = CONST64(#$src1)",
326 case Hexagon::CONST64:
327 if (!OutStreamer->hasRawTextSupport()) {
328 const MCOperand &Imm = MappedInst.getOperand(1);
329 MCSectionSubPair Current = OutStreamer->getCurrentSection();
330
331 MCSymbol *Sym =
332 smallData(*this, MI, *OutStreamer, Imm, 8, getSubtargetInfo());
333
334 OutStreamer->switchSection(Current.first, Current.second);
335 MCInst TmpInst;
336 MCOperand &Reg = MappedInst.getOperand(0);
337 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
338 TmpInst.addOperand(Reg);
341 MappedInst = TmpInst;
342
343 }
344 break;
345 case Hexagon::CONST32:
346 if (!OutStreamer->hasRawTextSupport()) {
347 MCOperand &Imm = MappedInst.getOperand(1);
348 MCSectionSubPair Current = OutStreamer->getCurrentSection();
349 MCSymbol *Sym =
350 smallData(*this, MI, *OutStreamer, Imm, 4, getSubtargetInfo());
351 OutStreamer->switchSection(Current.first, Current.second);
352 MCInst TmpInst;
353 MCOperand &Reg = MappedInst.getOperand(0);
354 TmpInst.setOpcode(Hexagon::L2_loadrigp);
355 TmpInst.addOperand(Reg);
358 MappedInst = TmpInst;
359 }
360 break;
361
362 // C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
363 // C2_or during instruction selection itself but it results
364 // into suboptimal code.
365 case Hexagon::C2_pxfer_map: {
366 MCOperand &Ps = Inst.getOperand(1);
367 MappedInst.setOpcode(Hexagon::C2_or);
368 MappedInst.addOperand(Ps);
369 return;
370 }
371
372 // Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
373 // The insn is mapped from the 4 operand to the 3 operand raw form taking
374 // 3 register pairs.
375 case Hexagon::M2_vrcmpys_acc_s1: {
376 MCOperand &Rt = Inst.getOperand(3);
377 assert(Rt.isReg() && "Expected register and none was found");
378 unsigned Reg = RI->getEncodingValue(Rt.getReg());
379 if (Reg & 1)
380 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
381 else
382 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
384 return;
385 }
386 case Hexagon::M2_vrcmpys_s1: {
387 MCOperand &Rt = Inst.getOperand(2);
388 assert(Rt.isReg() && "Expected register and none was found");
389 unsigned Reg = RI->getEncodingValue(Rt.getReg());
390 if (Reg & 1)
391 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
392 else
393 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
395 return;
396 }
397
398 case Hexagon::M2_vrcmpys_s1rp: {
399 MCOperand &Rt = Inst.getOperand(2);
400 assert(Rt.isReg() && "Expected register and none was found");
401 unsigned Reg = RI->getEncodingValue(Rt.getReg());
402 if (Reg & 1)
403 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
404 else
405 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
407 return;
408 }
409
410 case Hexagon::A4_boundscheck: {
411 MCOperand &Rs = Inst.getOperand(1);
412 assert(Rs.isReg() && "Expected register and none was found");
413 unsigned Reg = RI->getEncodingValue(Rs.getReg());
414 if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
415 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
416 else // raw:lo
417 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
419 return;
420 }
421
422 case Hexagon::PS_call_nr:
423 Inst.setOpcode(Hexagon::J2_call);
424 break;
425
426 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
427 MCOperand &MO = MappedInst.getOperand(2);
428 int64_t Imm;
429 MCExpr const *Expr = MO.getExpr();
430 bool Success = Expr->evaluateAsAbsolute(Imm);
431 assert(Success && "Expected immediate and none was found");
432 (void)Success;
433 MCInst TmpInst;
434 if (Imm == 0) {
435 TmpInst.setOpcode(Hexagon::S2_vsathub);
436 TmpInst.addOperand(MappedInst.getOperand(0));
437 TmpInst.addOperand(MappedInst.getOperand(1));
438 MappedInst = TmpInst;
439 return;
440 }
441 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
442 TmpInst.addOperand(MappedInst.getOperand(0));
443 TmpInst.addOperand(MappedInst.getOperand(1));
445 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
446 TmpInst.addOperand(
448 MappedInst = TmpInst;
449 return;
450 }
451
452 case Hexagon::S5_vasrhrnd_goodsyntax:
453 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
454 MCOperand &MO2 = MappedInst.getOperand(2);
455 MCExpr const *Expr = MO2.getExpr();
456 int64_t Imm;
457 bool Success = Expr->evaluateAsAbsolute(Imm);
458 assert(Success && "Expected immediate and none was found");
459 (void)Success;
460 MCInst TmpInst;
461 if (Imm == 0) {
462 TmpInst.setOpcode(Hexagon::A2_combinew);
463 TmpInst.addOperand(MappedInst.getOperand(0));
464 MCOperand &MO1 = MappedInst.getOperand(1);
465 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
466 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
467 // Add a new operand for the second register in the pair.
470 MappedInst = TmpInst;
471 return;
472 }
473
474 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
475 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
476 else
477 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
478 TmpInst.addOperand(MappedInst.getOperand(0));
479 TmpInst.addOperand(MappedInst.getOperand(1));
481 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
482 TmpInst.addOperand(
484 MappedInst = TmpInst;
485 return;
486 }
487
488 // if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
489 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
490 MCOperand &MO = Inst.getOperand(2);
491 MCExpr const *Expr = MO.getExpr();
492 int64_t Imm;
493 bool Success = Expr->evaluateAsAbsolute(Imm);
494 assert(Success && "Expected immediate and none was found");
495 (void)Success;
496 MCInst TmpInst;
497 if (Imm == 0) {
498 TmpInst.setOpcode(Hexagon::A2_tfr);
499 TmpInst.addOperand(MappedInst.getOperand(0));
500 TmpInst.addOperand(MappedInst.getOperand(1));
501 MappedInst = TmpInst;
502 return;
503 }
504 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
505 TmpInst.addOperand(MappedInst.getOperand(0));
506 TmpInst.addOperand(MappedInst.getOperand(1));
508 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
509 TmpInst.addOperand(
511 MappedInst = TmpInst;
512 return;
513 }
514
515 // Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
516 case Hexagon::A2_tfrpi: {
517 MCInst TmpInst;
518 MCOperand &Rdd = MappedInst.getOperand(0);
519 MCOperand &MO = MappedInst.getOperand(1);
520
521 TmpInst.setOpcode(Hexagon::A2_combineii);
522 TmpInst.addOperand(Rdd);
523 int64_t Imm;
524 bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
525 if (Success && Imm < 0) {
526 const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
529 } else {
530 const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
533 }
534 TmpInst.addOperand(MO);
535 MappedInst = TmpInst;
536 return;
537 }
538
539 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
540 case Hexagon::A2_tfrp: {
541 MCOperand &MO = MappedInst.getOperand(1);
542 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
543 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
544 MO.setReg(High);
545 // Add a new operand for the second register in the pair.
547 MappedInst.setOpcode(Hexagon::A2_combinew);
548 return;
549 }
550
551 case Hexagon::A2_tfrpt:
552 case Hexagon::A2_tfrpf: {
553 MCOperand &MO = MappedInst.getOperand(2);
554 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
555 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
556 MO.setReg(High);
557 // Add a new operand for the second register in the pair.
559 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
560 ? Hexagon::C2_ccombinewt
561 : Hexagon::C2_ccombinewf);
562 return;
563 }
564
565 case Hexagon::A2_tfrptnew:
566 case Hexagon::A2_tfrpfnew: {
567 MCOperand &MO = MappedInst.getOperand(2);
568 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
569 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
570 MO.setReg(High);
571 // Add a new operand for the second register in the pair.
573 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
574 ? Hexagon::C2_ccombinewnewt
575 : Hexagon::C2_ccombinewnewf);
576 return;
577 }
578
579 case Hexagon::M2_mpysmi: {
580 MCOperand &Imm = MappedInst.getOperand(2);
581 MCExpr const *Expr = Imm.getExpr();
582 int64_t Value;
583 bool Success = Expr->evaluateAsAbsolute(Value);
585 (void)Success;
586 if (Value < 0 && Value > -256) {
587 MappedInst.setOpcode(Hexagon::M2_mpysin);
588 Imm.setExpr(HexagonMCExpr::create(
590 } else
591 MappedInst.setOpcode(Hexagon::M2_mpysip);
592 return;
593 }
594
595 case Hexagon::A2_addsp: {
596 MCOperand &Rt = Inst.getOperand(1);
597 assert(Rt.isReg() && "Expected register and none was found");
598 unsigned Reg = RI->getEncodingValue(Rt.getReg());
599 if (Reg & 1)
600 MappedInst.setOpcode(Hexagon::A2_addsph);
601 else
602 MappedInst.setOpcode(Hexagon::A2_addspl);
604 return;
605 }
606
607 case Hexagon::V6_vd0: {
608 MCInst TmpInst;
609 assert(Inst.getOperand(0).isReg() &&
610 "Expected register and none was found");
611
612 TmpInst.setOpcode(Hexagon::V6_vxor);
613 TmpInst.addOperand(Inst.getOperand(0));
614 TmpInst.addOperand(Inst.getOperand(0));
615 TmpInst.addOperand(Inst.getOperand(0));
616 MappedInst = TmpInst;
617 return;
618 }
619
620 case Hexagon::V6_vdd0: {
621 MCInst TmpInst;
622 assert (Inst.getOperand(0).isReg() &&
623 "Expected register and none was found");
624
625 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
626 TmpInst.addOperand(Inst.getOperand(0));
627 TmpInst.addOperand(Inst.getOperand(0));
628 TmpInst.addOperand(Inst.getOperand(0));
629 MappedInst = TmpInst;
630 return;
631 }
632
633 case Hexagon::V6_vL32Ub_pi:
634 case Hexagon::V6_vL32b_cur_pi:
635 case Hexagon::V6_vL32b_nt_cur_pi:
636 case Hexagon::V6_vL32b_pi:
637 case Hexagon::V6_vL32b_nt_pi:
638 case Hexagon::V6_vL32b_nt_tmp_pi:
639 case Hexagon::V6_vL32b_tmp_pi:
640 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
641 return;
642
643 case Hexagon::V6_vL32Ub_ai:
644 case Hexagon::V6_vL32b_ai:
645 case Hexagon::V6_vL32b_cur_ai:
646 case Hexagon::V6_vL32b_nt_ai:
647 case Hexagon::V6_vL32b_nt_cur_ai:
648 case Hexagon::V6_vL32b_nt_tmp_ai:
649 case Hexagon::V6_vL32b_tmp_ai:
650 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
651 return;
652
653 case Hexagon::V6_vS32Ub_pi:
654 case Hexagon::V6_vS32b_new_pi:
655 case Hexagon::V6_vS32b_nt_new_pi:
656 case Hexagon::V6_vS32b_nt_pi:
657 case Hexagon::V6_vS32b_pi:
658 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
659 return;
660
661 case Hexagon::V6_vS32Ub_ai:
662 case Hexagon::V6_vS32b_ai:
663 case Hexagon::V6_vS32b_new_ai:
664 case Hexagon::V6_vS32b_nt_ai:
665 case Hexagon::V6_vS32b_nt_new_ai:
666 MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
667 return;
668
669 case Hexagon::V6_vL32b_cur_npred_pi:
670 case Hexagon::V6_vL32b_cur_pred_pi:
671 case Hexagon::V6_vL32b_npred_pi:
672 case Hexagon::V6_vL32b_nt_cur_npred_pi:
673 case Hexagon::V6_vL32b_nt_cur_pred_pi:
674 case Hexagon::V6_vL32b_nt_npred_pi:
675 case Hexagon::V6_vL32b_nt_pred_pi:
676 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
677 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
678 case Hexagon::V6_vL32b_pred_pi:
679 case Hexagon::V6_vL32b_tmp_npred_pi:
680 case Hexagon::V6_vL32b_tmp_pred_pi:
681 MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext);
682 return;
683
684 case Hexagon::V6_vL32b_cur_npred_ai:
685 case Hexagon::V6_vL32b_cur_pred_ai:
686 case Hexagon::V6_vL32b_npred_ai:
687 case Hexagon::V6_vL32b_nt_cur_npred_ai:
688 case Hexagon::V6_vL32b_nt_cur_pred_ai:
689 case Hexagon::V6_vL32b_nt_npred_ai:
690 case Hexagon::V6_vL32b_nt_pred_ai:
691 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
692 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
693 case Hexagon::V6_vL32b_pred_ai:
694 case Hexagon::V6_vL32b_tmp_npred_ai:
695 case Hexagon::V6_vL32b_tmp_pred_ai:
696 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
697 return;
698
699 case Hexagon::V6_vS32Ub_npred_pi:
700 case Hexagon::V6_vS32Ub_pred_pi:
701 case Hexagon::V6_vS32b_new_npred_pi:
702 case Hexagon::V6_vS32b_new_pred_pi:
703 case Hexagon::V6_vS32b_npred_pi:
704 case Hexagon::V6_vS32b_nqpred_pi:
705 case Hexagon::V6_vS32b_nt_new_npred_pi:
706 case Hexagon::V6_vS32b_nt_new_pred_pi:
707 case Hexagon::V6_vS32b_nt_npred_pi:
708 case Hexagon::V6_vS32b_nt_nqpred_pi:
709 case Hexagon::V6_vS32b_nt_pred_pi:
710 case Hexagon::V6_vS32b_nt_qpred_pi:
711 case Hexagon::V6_vS32b_pred_pi:
712 case Hexagon::V6_vS32b_qpred_pi:
713 MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext);
714 return;
715
716 case Hexagon::V6_vS32Ub_npred_ai:
717 case Hexagon::V6_vS32Ub_pred_ai:
718 case Hexagon::V6_vS32b_new_npred_ai:
719 case Hexagon::V6_vS32b_new_pred_ai:
720 case Hexagon::V6_vS32b_npred_ai:
721 case Hexagon::V6_vS32b_nqpred_ai:
722 case Hexagon::V6_vS32b_nt_new_npred_ai:
723 case Hexagon::V6_vS32b_nt_new_pred_ai:
724 case Hexagon::V6_vS32b_nt_npred_ai:
725 case Hexagon::V6_vS32b_nt_nqpred_ai:
726 case Hexagon::V6_vS32b_nt_pred_ai:
727 case Hexagon::V6_vS32b_nt_qpred_ai:
728 case Hexagon::V6_vS32b_pred_ai:
729 case Hexagon::V6_vS32b_qpred_ai:
730 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
731 return;
732
733 // V65+
734 case Hexagon::V6_vS32b_srls_ai:
735 MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext);
736 return;
737
738 case Hexagon::V6_vS32b_srls_pi:
739 MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext);
740 return;
741 }
742}
743
744/// Print out a single Hexagon MI to the current output stream.
746 Hexagon_MC::verifyInstructionPredicates(MI->getOpcode(),
747 getSubtargetInfo().getFeatureBits());
748
749 MCInst MCB;
750 MCB.setOpcode(Hexagon::BUNDLE);
752 const MCInstrInfo &MCII = *Subtarget->getInstrInfo();
753
754 if (MI->isBundle()) {
755 const MachineBasicBlock* MBB = MI->getParent();
756 MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
757
758 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
759 if (!MII->isDebugInstr() && !MII->isImplicitDef())
760 HexagonLowerToMC(MCII, &*MII, MCB, *this);
761 } else {
762 HexagonLowerToMC(MCII, MI, MCB, *this);
763 }
764
765 const MachineFunction &MF = *MI->getParent()->getParent();
766 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
767 if (MI->isBundle() && HII.getBundleNoShuf(*MI))
769
770 MCContext &Ctx = OutStreamer->getContext();
771 bool Ok = HexagonMCInstrInfo::canonicalizePacket(MCII, *Subtarget, Ctx,
772 MCB, nullptr);
773 assert(Ok); (void)Ok;
774 if (HexagonMCInstrInfo::bundleSize(MCB) == 0)
775 return;
776 OutStreamer->emitInstruction(MCB, getSubtargetInfo());
777}
778
780 static const int8_t NoopsInSledCount = 4;
781 // We want to emit the following pattern:
782 //
783 // .L_xray_sled_N:
784 // <xray_sled_base>:
785 // { jump .Ltmp0 }
786 // { nop
787 // nop
788 // nop
789 // nop }
790 // .Ltmp0:
791 //
792 // We need the 4 nop words because at runtime, we'd be patching over the
793 // full 5 words with the following pattern:
794 //
795 // <xray_sled_n>:
796 // { immext(#...) // upper 26-bits of trampoline
797 // r6 = ##... // lower 6-bits of trampoline
798 // immext(#...) // upper 26-bits of func id
799 // r7 = ##... } // lower 6 bits of func id
800 // { callr r6 }
801 //
802 //
803 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
804 OutStreamer->emitLabel(CurSled);
805
806 MCInst *SledJump = new (OutContext) MCInst();
807 SledJump->setOpcode(Hexagon::J2_jump);
808 auto PostSled = OutContext.createTempSymbol();
811
812 // Emit "jump PostSled" instruction, which jumps over the nop series.
813 MCInst SledJumpPacket;
814 SledJumpPacket.setOpcode(Hexagon::BUNDLE);
815 SledJumpPacket.addOperand(MCOperand::createImm(0));
816 SledJumpPacket.addOperand(MCOperand::createInst(SledJump));
817
818 EmitToStreamer(*OutStreamer, SledJumpPacket);
819
820 // FIXME: this will emit individual packets, we should
821 // special-case this and combine them into a single packet.
822 emitNops(NoopsInSledCount);
823
824 OutStreamer->emitLabel(PostSled);
825 recordSled(CurSled, MI, Kind, 2);
826}
827
830}
831
834}
835
838}
839
842}
#define Success
MachineBasicBlock & MBB
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
std::string Name
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmPrinter()
static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize, const MCSubtargetInfo &STI)
static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)
static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
uint64_t High
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:467
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:84
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:662
void emitNops(unsigned N)
Emit N NOP instructions.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:398
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS)
Print the MachineOperand as a symbol.
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:90
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:102
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:94
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:99
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:393
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
void EmitSled(const MachineInstr &MI, SledKind Kind)
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
PrintAsmOperand - Print out an operand for an inline asm expression.
void emitInstruction(const MachineInstr *MI) override
Print out a single Hexagon MI to the current output stream.
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)
static char const * getRegisterName(MCRegister Reg)
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
const HexagonInstrInfo * getInstrInfo() const override
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:318
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
Definition: MCContext.h:563
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
void clear()
Definition: MCInst.h:215
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
void setReg(unsigned Reg)
Set the register number.
Definition: MCInst.h:75
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
This represents a section on linux, lots of unix variants and some bare metal systems.
Definition: MCSectionELF.h:26
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:423
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Definition: MCStreamer.cpp:134
virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
virtual void switchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Generic base class for all target subtargets.
MCSuperRegIterator enumerates all super-registers of Reg.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:257
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.h:451
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
bool hasAddressTaken() const
Test whether this block is used as as something other than the target of a terminator,...
instr_iterator instr_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
int64_t getImm() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
Iterator for intrusive lists based on ilist_node.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SHF_ALLOC
Definition: ELF.h:1083
@ SHF_WRITE
Definition: ELF.h:1080
@ SHT_PROGBITS
Definition: ELF.h:995
size_t bundleSize(MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
void setMemReorderDisabled(MCInst &MCI)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
@ Offset
Definition: DWP.cpp:406
Target & getTheHexagonTarget()
void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)
std::pair< MCSection *, const MCExpr * > MCSectionSubPair
Definition: MCStreamer.h:66
@ MCSA_Local
.local (ELF)
Definition: MCDirectives.h:38
@ MCSA_Global
.type _foo, @gnu_unique_object
Definition: MCDirectives.h:30
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...