63#define DEBUG_TYPE "asm-printer"
115 const char *ExtraCode,
118 if (ExtraCode && ExtraCode[0]) {
119 if (ExtraCode[1] != 0)
122 switch (ExtraCode[0]) {
135 if (Hexagon::DoubleRegsRegClass.
contains(RegNumber))
136 RegNumber =
TRI->getSubReg(RegNumber, ExtraCode[0] ==
'L' ?
145 if (
MI->getOperand(OpNo).isImm())
157 const char *ExtraCode,
159 if (ExtraCode && ExtraCode[0])
172 O <<
"+#" <<
Offset.getImm();
185 if (Imm.getExpr()->evaluateAsAbsolute(
Value)) {
187 std::string ImmString;
189 if (AlignSize == 8) {
190 Name =
".CONST_0000000000000000";
191 sectionPrefix =
".gnu.linkonce.l8";
192 ImmString = utohexstr(
Value);
194 Name =
".CONST_00000000";
195 sectionPrefix =
".gnu.linkonce.l4";
199 std::string symbolName =
200 Name.drop_back(ImmString.size()).str() + ImmString;
201 std::string sectionName = sectionPrefix.
str() + symbolName;
215 assert(Imm.isExpr() &&
"Expected expression and found none");
229 std::string LitaName =
".CONST_" + SymbolName.str();
239 OutStreamer.
emitValue(Imm.getExpr(), AlignSize);
257 int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue();
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
277 case Hexagon::A2_iconst: {
290 case Hexagon::A2_tfrf: {
297 case Hexagon::A2_tfrt: {
304 case Hexagon::A2_tfrfnew: {
311 case Hexagon::A2_tfrtnew: {
318 case Hexagon::A2_zxtb: {
326 case Hexagon::CONST64:
334 OutStreamer->switchSection(Current.first, Current.second);
341 MappedInst = TmpInst;
345 case Hexagon::CONST32:
351 OutStreamer->switchSection(Current.first, Current.second);
358 MappedInst = TmpInst;
365 case Hexagon::C2_pxfer_map: {
375 case Hexagon::M2_vrcmpys_acc_s1: {
377 assert(Rt.
isReg() &&
"Expected register and none was found");
380 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
382 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
386 case Hexagon::M2_vrcmpys_s1: {
388 assert(Rt.
isReg() &&
"Expected register and none was found");
391 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_s1_h);
393 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_s1_l);
398 case Hexagon::M2_vrcmpys_s1rp: {
400 assert(Rt.
isReg() &&
"Expected register and none was found");
403 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
405 MappedInst.
setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
410 case Hexagon::A4_boundscheck: {
412 assert(Rs.
isReg() &&
"Expected register and none was found");
415 MappedInst.
setOpcode(Hexagon::A4_boundscheck_hi);
417 MappedInst.
setOpcode(Hexagon::A4_boundscheck_lo);
422 case Hexagon::PS_call_nr:
426 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
430 bool Success = Expr->evaluateAsAbsolute(Imm);
438 MappedInst = TmpInst;
441 TmpInst.
setOpcode(Hexagon::S5_asrhub_rnd_sat);
448 MappedInst = TmpInst;
452 case Hexagon::S5_vasrhrnd_goodsyntax:
453 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
457 bool Success = Expr->evaluateAsAbsolute(Imm);
470 MappedInst = TmpInst;
474 if (Inst.
getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
475 TmpInst.
setOpcode(Hexagon::S2_asr_i_p_rnd);
484 MappedInst = TmpInst;
489 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
493 bool Success = Expr->evaluateAsAbsolute(Imm);
501 MappedInst = TmpInst;
504 TmpInst.
setOpcode(Hexagon::S2_asr_i_r_rnd);
511 MappedInst = TmpInst;
516 case Hexagon::A2_tfrpi: {
521 TmpInst.
setOpcode(Hexagon::A2_combineii);
535 MappedInst = TmpInst;
540 case Hexagon::A2_tfrp: {
547 MappedInst.
setOpcode(Hexagon::A2_combinew);
551 case Hexagon::A2_tfrpt:
552 case Hexagon::A2_tfrpf: {
560 ? Hexagon::C2_ccombinewt
561 : Hexagon::C2_ccombinewf);
565 case Hexagon::A2_tfrptnew:
566 case Hexagon::A2_tfrpfnew: {
574 ? Hexagon::C2_ccombinewnewt
575 : Hexagon::C2_ccombinewnewf);
579 case Hexagon::M2_mpysmi: {
581 MCExpr const *Expr = Imm.getExpr();
586 if (Value < 0 && Value > -256) {
587 MappedInst.
setOpcode(Hexagon::M2_mpysin);
591 MappedInst.
setOpcode(Hexagon::M2_mpysip);
595 case Hexagon::A2_addsp: {
597 assert(Rt.
isReg() &&
"Expected register and none was found");
600 MappedInst.
setOpcode(Hexagon::A2_addsph);
602 MappedInst.
setOpcode(Hexagon::A2_addspl);
607 case Hexagon::V6_vd0: {
610 "Expected register and none was found");
616 MappedInst = TmpInst;
620 case Hexagon::V6_vdd0: {
623 "Expected register and none was found");
629 MappedInst = TmpInst;
633 case Hexagon::V6_vL32Ub_pi:
634 case Hexagon::V6_vL32b_cur_pi:
635 case Hexagon::V6_vL32b_nt_cur_pi:
636 case Hexagon::V6_vL32b_pi:
637 case Hexagon::V6_vL32b_nt_pi:
638 case Hexagon::V6_vL32b_nt_tmp_pi:
639 case Hexagon::V6_vL32b_tmp_pi:
643 case Hexagon::V6_vL32Ub_ai:
644 case Hexagon::V6_vL32b_ai:
645 case Hexagon::V6_vL32b_cur_ai:
646 case Hexagon::V6_vL32b_nt_ai:
647 case Hexagon::V6_vL32b_nt_cur_ai:
648 case Hexagon::V6_vL32b_nt_tmp_ai:
649 case Hexagon::V6_vL32b_tmp_ai:
653 case Hexagon::V6_vS32Ub_pi:
654 case Hexagon::V6_vS32b_new_pi:
655 case Hexagon::V6_vS32b_nt_new_pi:
656 case Hexagon::V6_vS32b_nt_pi:
657 case Hexagon::V6_vS32b_pi:
661 case Hexagon::V6_vS32Ub_ai:
662 case Hexagon::V6_vS32b_ai:
663 case Hexagon::V6_vS32b_new_ai:
664 case Hexagon::V6_vS32b_nt_ai:
665 case Hexagon::V6_vS32b_nt_new_ai:
669 case Hexagon::V6_vL32b_cur_npred_pi:
670 case Hexagon::V6_vL32b_cur_pred_pi:
671 case Hexagon::V6_vL32b_npred_pi:
672 case Hexagon::V6_vL32b_nt_cur_npred_pi:
673 case Hexagon::V6_vL32b_nt_cur_pred_pi:
674 case Hexagon::V6_vL32b_nt_npred_pi:
675 case Hexagon::V6_vL32b_nt_pred_pi:
676 case Hexagon::V6_vL32b_nt_tmp_npred_pi:
677 case Hexagon::V6_vL32b_nt_tmp_pred_pi:
678 case Hexagon::V6_vL32b_pred_pi:
679 case Hexagon::V6_vL32b_tmp_npred_pi:
680 case Hexagon::V6_vL32b_tmp_pred_pi:
684 case Hexagon::V6_vL32b_cur_npred_ai:
685 case Hexagon::V6_vL32b_cur_pred_ai:
686 case Hexagon::V6_vL32b_npred_ai:
687 case Hexagon::V6_vL32b_nt_cur_npred_ai:
688 case Hexagon::V6_vL32b_nt_cur_pred_ai:
689 case Hexagon::V6_vL32b_nt_npred_ai:
690 case Hexagon::V6_vL32b_nt_pred_ai:
691 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
692 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
693 case Hexagon::V6_vL32b_pred_ai:
694 case Hexagon::V6_vL32b_tmp_npred_ai:
695 case Hexagon::V6_vL32b_tmp_pred_ai:
699 case Hexagon::V6_vS32Ub_npred_pi:
700 case Hexagon::V6_vS32Ub_pred_pi:
701 case Hexagon::V6_vS32b_new_npred_pi:
702 case Hexagon::V6_vS32b_new_pred_pi:
703 case Hexagon::V6_vS32b_npred_pi:
704 case Hexagon::V6_vS32b_nqpred_pi:
705 case Hexagon::V6_vS32b_nt_new_npred_pi:
706 case Hexagon::V6_vS32b_nt_new_pred_pi:
707 case Hexagon::V6_vS32b_nt_npred_pi:
708 case Hexagon::V6_vS32b_nt_nqpred_pi:
709 case Hexagon::V6_vS32b_nt_pred_pi:
710 case Hexagon::V6_vS32b_nt_qpred_pi:
711 case Hexagon::V6_vS32b_pred_pi:
712 case Hexagon::V6_vS32b_qpred_pi:
716 case Hexagon::V6_vS32Ub_npred_ai:
717 case Hexagon::V6_vS32Ub_pred_ai:
718 case Hexagon::V6_vS32b_new_npred_ai:
719 case Hexagon::V6_vS32b_new_pred_ai:
720 case Hexagon::V6_vS32b_npred_ai:
721 case Hexagon::V6_vS32b_nqpred_ai:
722 case Hexagon::V6_vS32b_nt_new_npred_ai:
723 case Hexagon::V6_vS32b_nt_new_pred_ai:
724 case Hexagon::V6_vS32b_nt_npred_ai:
725 case Hexagon::V6_vS32b_nt_nqpred_ai:
726 case Hexagon::V6_vS32b_nt_pred_ai:
727 case Hexagon::V6_vS32b_nt_qpred_ai:
728 case Hexagon::V6_vS32b_pred_ai:
729 case Hexagon::V6_vS32b_qpred_ai:
734 case Hexagon::V6_vS32b_srls_ai:
738 case Hexagon::V6_vS32b_srls_pi:
746 Hexagon_MC::verifyInstructionPredicates(
MI->getOpcode(),
754 if (
MI->isBundle()) {
758 for (++MII; MII !=
MBB->
instr_end() && MII->isInsideBundle(); ++MII)
759 if (!MII->isDebugInstr() && !MII->isImplicitDef())
767 if (
MI->isBundle() && HII.getBundleNoShuf(*
MI))
780 static const int8_t NoopsInSledCount = 4;
814 SledJumpPacket.
setOpcode(Hexagon::BUNDLE);
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmPrinter()
static MCSymbol * smallData(AsmPrinter &AP, const MachineInstr &MI, MCStreamer &OutStreamer, const MCOperand &Imm, int AlignSize, const MCSubtargetInfo &STI)
static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, unsigned VectorSize, MCContext &Ctx)
static unsigned getHexagonRegisterPair(unsigned Reg, const MCRegisterInfo *RI)
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
void emitNops(unsigned N)
Emit N NOP instructions.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS)
Print the MachineOperand as a symbol.
const MCAsmInfo * MAI
Target Asm Printer information.
MachineFunction * MF
The current machine function.
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCContext & OutContext
This is the context for the output file that we are streaming.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
void EmitSled(const MachineInstr &MI, SledKind Kind)
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override
PrintAsmOperand - Print out an operand for an inline asm expression.
void emitInstruction(const MachineInstr *MI) override
Print out a single Hexagon MI to the current output stream.
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB)
static char const * getRegisterName(MCRegister Reg)
static HexagonMCExpr * create(MCExpr const *Expr, MCContext &Ctx)
const HexagonInstrInfo * getInstrInfo() const override
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSectionELF * getELFSection(const Twine &Section, unsigned Type, unsigned Flags)
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
void setReg(unsigned Reg)
Set the register number.
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
static MCOperand createInst(const MCInst *Val)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
This represents a section on linux, lots of unix variants and some bare metal systems.
Streaming machine code generation interface.
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit=0)
Emit nops until the byte alignment ByteAlignment is reached.
virtual void switchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Generic base class for all target subtargets.
MCSuperRegIterator enumerates all super-registers of Reg.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
StringRef getName() const
getName - Get the symbol name.
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
static const MCUnaryExpr * createMinus(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
bool hasAddressTaken() const
Test whether this block is used as as something other than the target of a terminator,...
instr_iterator instr_end()
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
Wrapper class representing virtual and physical registers.
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
Iterator for intrusive lists based on ilist_node.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
size_t bundleSize(MCInst const &MCI)
void setS27_2_reloc(MCExpr const &Expr, bool Val=true)
void setMemReorderDisabled(MCInst &MCI)
bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
void setMustNotExtend(MCExpr const &Expr, bool Val=true)
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
Target & getTheHexagonTarget()
void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP)
std::pair< MCSection *, const MCExpr * > MCSectionSubPair
@ MCSA_Global
.type _foo, @gnu_unique_object
This struct is a compact representation of a valid (non-zero power of two) alignment.
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...