LLVM 17.0.0git
LiveRangeEdit.cpp
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1//===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// The LiveRangeEdit class represents changes done to a virtual register when it
10// is spilled or split.
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/Statistic.h"
20#include "llvm/Support/Debug.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "regalloc"
26
27STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
28STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
29STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
30STATISTIC(NumReMaterialization, "Number of instructions rematerialized");
31
32void LiveRangeEdit::Delegate::anchor() { }
33
34LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(Register OldReg,
35 bool createSubRanges) {
36 Register VReg = MRI.cloneVirtualRegister(OldReg);
37 if (VRM)
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39
40 LiveInterval &LI = LIS.createEmptyInterval(VReg);
41 if (Parent && !Parent->isSpillable())
43 if (createSubRanges) {
44 // Create empty subranges if the OldReg's interval has them. Do not create
45 // the main range here---it will be constructed later after the subranges
46 // have been finalized.
47 LiveInterval &OldLI = LIS.getInterval(OldReg);
49 for (LiveInterval::SubRange &S : OldLI.subranges())
50 LI.createSubRange(Alloc, S.LaneMask);
51 }
52 return LI;
53}
54
56 Register VReg = MRI.cloneVirtualRegister(OldReg);
57 if (VRM) {
58 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
59 }
60 // FIXME: Getting the interval here actually computes it.
61 // In theory, this may not be what we want, but in practice
62 // the createEmptyIntervalFrom API is used when this is not
63 // the case. Generally speaking we just want to annotate the
64 // LiveInterval when it gets created but we cannot do that at
65 // the moment.
66 if (Parent && !Parent->isSpillable())
67 LIS.getInterval(VReg).markNotSpillable();
68 return VReg;
69}
70
72 const MachineInstr *DefMI) {
73 assert(DefMI && "Missing instruction");
74 ScannedRemattable = true;
76 return false;
77 Remattable.insert(VNI);
78 return true;
79}
80
81void LiveRangeEdit::scanRemattable() {
82 for (VNInfo *VNI : getParent().valnos) {
83 if (VNI->isUnused())
84 continue;
85 unsigned Original = VRM->getOriginal(getReg());
86 LiveInterval &OrigLI = LIS.getInterval(Original);
87 VNInfo *OrigVNI = OrigLI.getVNInfoAt(VNI->def);
88 if (!OrigVNI)
89 continue;
91 if (!DefMI)
92 continue;
94 }
95 ScannedRemattable = true;
96}
97
99 if (!ScannedRemattable)
100 scanRemattable();
101 return !Remattable.empty();
102}
103
104/// allUsesAvailableAt - Return true if all registers used by OrigMI at
105/// OrigIdx are also available with the same value at UseIdx.
107 SlotIndex OrigIdx,
108 SlotIndex UseIdx) const {
109 OrigIdx = OrigIdx.getRegSlot(true);
110 UseIdx = std::max(UseIdx, UseIdx.getRegSlot(true));
111 for (const MachineOperand &MO : OrigMI->operands()) {
112 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
113 continue;
114
115 // We can't remat physreg uses, unless it is a constant or target wants
116 // to ignore this use.
117 if (MO.getReg().isPhysical()) {
118 if (MRI.isConstantPhysReg(MO.getReg()) || TII.isIgnorableUse(MO))
119 continue;
120 return false;
121 }
122
123 LiveInterval &li = LIS.getInterval(MO.getReg());
124 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
125 if (!OVNI)
126 continue;
127
128 // Don't allow rematerialization immediately after the original def.
129 // It would be incorrect if OrigMI redefines the register.
130 // See PR14098.
131 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
132 return false;
133
134 if (OVNI != li.getVNInfoAt(UseIdx))
135 return false;
136
137 // Check that subrange is live at UseIdx.
138 if (li.hasSubRanges()) {
140 unsigned SubReg = MO.getSubReg();
141 LaneBitmask LM = SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
142 : MRI.getMaxLaneMaskForVReg(MO.getReg());
143 for (LiveInterval::SubRange &SR : li.subranges()) {
144 if ((SR.LaneMask & LM).none())
145 continue;
146 if (!SR.liveAt(UseIdx))
147 return false;
148 // Early exit if all used lanes are checked. No need to continue.
149 LM &= ~SR.LaneMask;
150 if (LM.none())
151 break;
152 }
153 }
154 }
155 return true;
156}
157
159 SlotIndex UseIdx, bool cheapAsAMove) {
160 assert(ScannedRemattable && "Call anyRematerializable first");
161
162 // Use scanRemattable info.
163 if (!Remattable.count(OrigVNI))
164 return false;
165
166 // No defining instruction provided.
167 SlotIndex DefIdx;
168 assert(RM.OrigMI && "No defining instruction for remattable value");
169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI);
170
171 // If only cheap remats were requested, bail out early.
172 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI))
173 return false;
174
175 // Verify that all used registers are available with the same values.
176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
177 return false;
178
179 return true;
180}
181
184 unsigned DestReg,
185 const Remat &RM,
186 const TargetRegisterInfo &tri,
187 bool Late,
188 unsigned SubIdx,
189 MachineInstr *ReplaceIndexMI) {
190 assert(RM.OrigMI && "Invalid remat");
191 TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tri);
192 // DestReg of the cloned instruction cannot be Dead. Set isDead of DestReg
193 // to false anyway in case the isDead flag of RM.OrigMI's dest register
194 // is true.
195 (*--MI).getOperand(0).setIsDead(false);
196 Rematted.insert(RM.ParentVNI);
197 ++NumReMaterialization;
198
199 if (ReplaceIndexMI)
200 return LIS.ReplaceMachineInstrInMaps(*ReplaceIndexMI, *MI).getRegSlot();
202}
203
205 if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
206 LIS.removeInterval(Reg);
207}
208
209bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
211 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
212
213 // Check that there is a single def and a single use.
214 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg())) {
215 MachineInstr *MI = MO.getParent();
216 if (MO.isDef()) {
217 if (DefMI && DefMI != MI)
218 return false;
219 if (!MI->canFoldAsLoad())
220 return false;
221 DefMI = MI;
222 } else if (!MO.isUndef()) {
223 if (UseMI && UseMI != MI)
224 return false;
225 // FIXME: Targets don't know how to fold subreg uses.
226 if (MO.getSubReg())
227 return false;
228 UseMI = MI;
229 }
230 }
231 if (!DefMI || !UseMI)
232 return false;
233
234 // Since we're moving the DefMI load, make sure we're not extending any live
235 // ranges.
238 return false;
239
240 // We also need to make sure it is safe to move the load.
241 // Assume there are stores between DefMI and UseMI.
242 bool SawStore = true;
243 if (!DefMI->isSafeToMove(nullptr, SawStore))
244 return false;
245
246 LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
247 << " into single use: " << *UseMI);
248
250 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
251 return false;
252
253 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
254 if (!FoldMI)
255 return false;
256 LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
257 LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
258 // Update the call site info.
260 UseMI->getMF()->moveCallSiteInfo(UseMI, FoldMI);
262 DefMI->addRegisterDead(LI->reg(), nullptr);
263 Dead.push_back(DefMI);
264 ++NumDCEFoldedLoads;
265 return true;
266}
267
268bool LiveRangeEdit::useIsKill(const LiveInterval &LI,
269 const MachineOperand &MO) const {
270 const MachineInstr &MI = *MO.getParent();
272 if (LI.Query(Idx).isKill())
273 return true;
275 unsigned SubReg = MO.getSubReg();
276 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
277 for (const LiveInterval::SubRange &S : LI.subranges()) {
278 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
279 return true;
280 }
281 return false;
282}
283
284/// Find all live intervals that need to shrink, then remove the instruction.
285void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
286 assert(MI->allDefsAreDead() && "Def isn't really dead");
288
289 // Never delete a bundled instruction.
290 if (MI->isBundled()) {
291 return;
292 }
293 // Never delete inline asm.
294 if (MI->isInlineAsm()) {
295 LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
296 return;
297 }
298
299 // Use the same criteria as DeadMachineInstructionElim.
300 bool SawStore = false;
301 if (!MI->isSafeToMove(nullptr, SawStore)) {
302 LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
303 return;
304 }
305
306 LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
307
308 // Collect virtual registers to be erased after MI is gone.
309 SmallVector<unsigned, 8> RegsToErase;
310 bool ReadsPhysRegs = false;
311 bool isOrigDef = false;
312 Register Dest;
313 unsigned DestSubReg;
314 // Only optimize rematerialize case when the instruction has one def, since
315 // otherwise we could leave some dead defs in the code. This case is
316 // extremely rare.
317 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
318 MI->getDesc().getNumDefs() == 1) {
319 Dest = MI->getOperand(0).getReg();
320 DestSubReg = MI->getOperand(0).getSubReg();
321 Register Original = VRM->getOriginal(Dest);
322 LiveInterval &OrigLI = LIS.getInterval(Original);
323 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
324 // The original live-range may have been shrunk to
325 // an empty live-range. It happens when it is dead, but
326 // we still keep it around to be able to rematerialize
327 // other values that depend on it.
328 if (OrigVNI)
329 isOrigDef = SlotIndex::isSameInstr(OrigVNI->def, Idx);
330 }
331
332 bool HasLiveVRegUses = false;
333
334 // Check for live intervals that may shrink
335 for (const MachineOperand &MO : MI->operands()) {
336 if (!MO.isReg())
337 continue;
338 Register Reg = MO.getReg();
339 if (!Reg.isVirtual()) {
340 // Check if MI reads any unreserved physregs.
341 if (Reg && MO.readsReg() && !MRI.isReserved(Reg))
342 ReadsPhysRegs = true;
343 else if (MO.isDef())
344 LIS.removePhysRegDefAt(Reg.asMCReg(), Idx);
345 continue;
346 }
347 LiveInterval &LI = LIS.getInterval(Reg);
348
349 // Shrink read registers, unless it is likely to be expensive and
350 // unlikely to change anything. We typically don't want to shrink the
351 // PIC base register that has lots of uses everywhere.
352 // Always shrink COPY uses that probably come from live range splitting.
353 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MO.isDef())) ||
354 (MO.readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, MO))))
355 ToShrink.insert(&LI);
356 else if (MO.readsReg())
357 HasLiveVRegUses = true;
358
359 // Remove defined value.
360 if (MO.isDef()) {
361 if (TheDelegate && LI.getVNInfoAt(Idx) != nullptr)
362 TheDelegate->LRE_WillShrinkVirtReg(LI.reg());
363 LIS.removeVRegDefAt(LI, Idx);
364 if (LI.empty())
365 RegsToErase.push_back(Reg);
366 }
367 }
368
369 // Currently, we don't support DCE of physreg live ranges. If MI reads
370 // any unreserved physregs, don't erase the instruction, but turn it into
371 // a KILL instead. This way, the physreg live ranges don't end up
372 // dangling.
373 // FIXME: It would be better to have something like shrinkToUses() for
374 // physregs. That could potentially enable more DCE and it would free up
375 // the physreg. It would not happen often, though.
376 if (ReadsPhysRegs) {
377 MI->setDesc(TII.get(TargetOpcode::KILL));
378 // Remove all operands that aren't physregs.
379 for (unsigned i = MI->getNumOperands(); i; --i) {
380 const MachineOperand &MO = MI->getOperand(i-1);
381 if (MO.isReg() && MO.getReg().isPhysical())
382 continue;
383 MI->removeOperand(i-1);
384 }
385 LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
386 } else {
387 // If the dest of MI is an original reg and MI is reMaterializable,
388 // don't delete the inst. Replace the dest with a new reg, and keep
389 // the inst for remat of other siblings. The inst is saved in
390 // LiveRangeEdit::DeadRemats and will be deleted after all the
391 // allocations of the func are done.
392 // However, immediately delete instructions which have unshrunk virtual
393 // register uses. That may provoke RA to split an interval at the KILL
394 // and later result in an invalid live segment end.
395 if (isOrigDef && DeadRemats && !HasLiveVRegUses &&
397 LiveInterval &NewLI = createEmptyIntervalFrom(Dest, false);
399 VNInfo *VNI = NewLI.getNextValue(Idx, Alloc);
400 NewLI.addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(), VNI));
401
402 if (DestSubReg) {
404 auto *SR = NewLI.createSubRange(
405 Alloc, TRI->getSubRegIndexLaneMask(DestSubReg));
406 SR->addSegment(LiveInterval::Segment(Idx, Idx.getDeadSlot(),
407 SR->getNextValue(Idx, Alloc)));
408 }
409
410 pop_back();
411 DeadRemats->insert(MI);
413 MI->substituteRegister(Dest, NewLI.reg(), 0, TRI);
414 MI->getOperand(0).setIsDead(true);
415 } else {
416 if (TheDelegate)
417 TheDelegate->LRE_WillEraseInstruction(MI);
419 MI->eraseFromParent();
420 ++NumDCEDeleted;
421 }
422 }
423
424 // Erase any virtregs that are now empty and unused. There may be <undef>
425 // uses around. Keep the empty live range in that case.
426 for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
427 Register Reg = RegsToErase[i];
428 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
429 ToShrink.remove(&LIS.getInterval(Reg));
430 eraseVirtReg(Reg);
431 }
432 }
433}
434
436 ArrayRef<Register> RegsBeingSpilled) {
437 ToShrinkSet ToShrink;
438
439 for (;;) {
440 // Erase all dead defs.
441 while (!Dead.empty())
442 eliminateDeadDef(Dead.pop_back_val(), ToShrink);
443
444 if (ToShrink.empty())
445 break;
446
447 // Shrink just one live interval. Then delete new dead defs.
448 LiveInterval *LI = ToShrink.pop_back_val();
449 if (foldAsLoad(LI, Dead))
450 continue;
451 Register VReg = LI->reg();
452 if (TheDelegate)
453 TheDelegate->LRE_WillShrinkVirtReg(VReg);
454 if (!LIS.shrinkToUses(LI, &Dead))
455 continue;
456
457 // Don't create new intervals for a register being spilled.
458 // The new intervals would have to be spilled anyway so its not worth it.
459 // Also they currently aren't spilled so creating them and not spilling
460 // them results in incorrect code.
461 if (llvm::is_contained(RegsBeingSpilled, VReg))
462 continue;
463
464 // LI may have been separated, create new intervals.
465 LI->RenumberValues();
467 LIS.splitSeparateComponents(*LI, SplitLIs);
468 if (!SplitLIs.empty())
469 ++NumFracRanges;
470
471 Register Original = VRM ? VRM->getOriginal(VReg) : Register();
472 for (const LiveInterval *SplitLI : SplitLIs) {
473 // If LI is an original interval that hasn't been split yet, make the new
474 // intervals their own originals instead of referring to LI. The original
475 // interval must contain all the split products, and LI doesn't.
476 if (Original != VReg && Original != 0)
477 VRM->setIsSplitFromReg(SplitLI->reg(), Original);
478 if (TheDelegate)
479 TheDelegate->LRE_DidCloneVirtReg(SplitLI->reg(), VReg);
480 }
481 }
482}
483
484// Keep track of new virtual registers created via
485// MachineRegisterInfo::createVirtualRegister.
486void
487LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
488 if (VRM)
489 VRM->grow();
490
491 NewRegs.push_back(VReg);
492}
493
495 VirtRegAuxInfo &VRAI) {
496 for (unsigned I = 0, Size = size(); I < Size; ++I) {
497 LiveInterval &LI = LIS.getInterval(get(I));
498 if (MRI.recomputeRegClass(LI.reg()))
499 LLVM_DEBUG({
500 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
501 dbgs() << "Inflated " << printReg(LI.reg()) << " to "
502 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n';
503 });
505 }
506}
unsigned SubReg
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
A live range for subregisters.
Definition: LiveInterval.h:693
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
void markNotSpillable()
markNotSpillable - Mark interval as not spillable
Definition: LiveInterval.h:822
Register reg() const
Definition: LiveInterval.h:717
bool isSpillable() const
isSpillable - Can this interval be spilled?
Definition: LiveInterval.h:819
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:803
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:775
SubRange * createSubRange(BumpPtrAllocator &Allocator, LaneBitmask LaneMask)
Creates a new empty subregister live range.
Definition: LiveInterval.h:785
bool hasInterval(Register Reg) const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndexes * getSlotIndexes() const
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
void RemoveMachineInstrFromMaps(MachineInstr &MI)
VNInfo::Allocator & getVNInfoAllocator()
LiveInterval & getInterval(Register Reg)
void removeInterval(Register Reg)
Interval removal.
void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos)
Remove value number and related live segments of LI and its subranges that start at position Pos.
bool shrinkToUses(LiveInterval *li, SmallVectorImpl< MachineInstr * > *dead=nullptr)
After removing some uses of a register, shrink its live range to just the remaining uses.
LiveInterval & createEmptyInterval(Register Reg)
Interval creation.
void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos)
Remove value numbers and related live segments starting at position Pos that are part of any liverang...
void splitSeparateComponents(LiveInterval &LI, SmallVectorImpl< LiveInterval * > &SplitLIs)
Split separate components in LiveInterval LI into separate intervals.
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
bool isKill() const
Return true if the live-in value is killed by this instruction.
Definition: LiveInterval.h:112
virtual bool LRE_CanEraseVirtReg(Register)
Called when a virtual register is no longer used.
Definition: LiveRangeEdit.h:56
virtual void LRE_WillEraseInstruction(MachineInstr *MI)
Called immediately before erasing a dead machine instruction.
Definition: LiveRangeEdit.h:52
virtual void LRE_WillShrinkVirtReg(Register)
Called before shrinking the live range of a virtual register.
Definition: LiveRangeEdit.h:59
virtual void LRE_DidCloneVirtReg(Register New, Register Old)
Called after cloning a virtual register.
Definition: LiveRangeEdit.h:63
void eraseVirtReg(Register Reg)
eraseVirtReg - Notify the delegate that Reg is no longer in use, and try to erase it from LIS.
unsigned size() const
Register get(unsigned idx) const
void eliminateDeadDefs(SmallVectorImpl< MachineInstr * > &Dead, ArrayRef< Register > RegsBeingSpilled=std::nullopt)
eliminateDeadDefs - Try to delete machine instructions that are now dead (allDefsAreDead returns true...
SlotIndex rematerializeAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const Remat &RM, const TargetRegisterInfo &, bool Late=false, unsigned SubIdx=0, MachineInstr *ReplaceIndexMI=nullptr)
rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an instruction into MBB before...
Register createFrom(Register OldReg)
createFrom - Create a new virtual register based on OldReg.
void calculateRegClassAndHint(MachineFunction &, VirtRegAuxInfo &)
calculateRegClassAndHint - Recompute register class and hint for each new register.
const LiveInterval & getParent() const
Register getReg() const
bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) const
allUsesAvailableAt - Return true if all registers used by OrigMI at OrigIdx are also available with t...
void pop_back()
pop_back - It allows LiveRangeEdit users to drop new registers.
bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI)
checkRematerializable - Manually add VNI to the list of rematerializable values if DefMI may be remat...
bool canRematerializeAt(Remat &RM, VNInfo *OrigVNI, SlotIndex UseIdx, bool cheapAsAMove)
canRematerializeAt - Determine if ParentVNI can be rematerialized at UseIdx.
bool anyRematerializable()
anyRematerializable - Return true if any parent values may be rematerializable.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool empty() const
Definition: LiveInterval.h:382
void RenumberValues()
RenumberValues - Renumber all values in order of appearance and remove unused values.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
Definition: LiveInterval.h:541
VNInfo * getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Definition: LiveInterval.h:331
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
Definition: LiveInterval.h:421
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:641
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
bool recomputeRegClass(Register Reg)
recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
const TargetRegisterInfo * getTargetRegisterInfo() const
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const
Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const
Register cloneVirtualRegister(Register VReg, StringRef Name="")
Create and return a new virtual register in the function with the same attributes as the given regist...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
A vector that has set insertion semantics.
Definition: SetVector.h:40
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
Definition: SlotIndexes.h:198
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:259
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:540
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
bool isTriviallyReMaterializable(const MachineInstr &MI) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
Calculate auxiliary information for a virtual register such as its spill weight and allocation hint.
void calculateSpillWeightAndHint(LiveInterval &LI)
(re)compute li's spill weight and allocation hint.
void setIsSplitFromReg(Register virtReg, Register SReg)
records virtReg is a split live interval from SReg.
Definition: VirtRegMap.h:153
Register getOriginal(Register VirtReg) const
getOriginal - Return the original virtual register that VirtReg descends from through splitting.
Definition: VirtRegMap.h:169
@ Dead
Unused definition.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1869
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
constexpr bool none() const
Definition: LaneBitmask.h:52
Remat - Information needed to rematerialize at a specific location.
This represents a simple continuous liveness interval for a value.
Definition: LiveInterval.h:162