LLVM  14.0.0git
PPCMIPeephole.cpp
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1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===---------------------------------------------------------------------===//
8 //
9 // This pass performs peephole optimizations to clean up ugly code
10 // sequences at the MachineInstruction layer. It runs at the end of
11 // the SSA phases, following VSX swap removal. A pass of dead code
12 // elimination follows this one for quick clean-up of any dead
13 // instructions introduced here. Although we could do this as callbacks
14 // from the generic peephole pass, this would have a couple of bad
15 // effects: it might remove optimization opportunities for VSX swap
16 // removal, and it would miss cleanups made possible following VSX
17 // swap removal.
18 //
19 //===---------------------------------------------------------------------===//
20 
23 #include "PPC.h"
24 #include "PPCInstrBuilder.h"
25 #include "PPCInstrInfo.h"
26 #include "PPCMachineFunctionInfo.h"
27 #include "PPCTargetMachine.h"
28 #include "llvm/ADT/Statistic.h"
35 #include "llvm/InitializePasses.h"
36 #include "llvm/Support/Debug.h"
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "ppc-mi-peepholes"
41 
42 STATISTIC(RemoveTOCSave, "Number of TOC saves removed");
43 STATISTIC(MultiTOCSaves,
44  "Number of functions with multiple TOC saves that must be kept");
45 STATISTIC(NumTOCSavesInPrologue, "Number of TOC saves placed in the prologue");
46 STATISTIC(NumEliminatedSExt, "Number of eliminated sign-extensions");
47 STATISTIC(NumEliminatedZExt, "Number of eliminated zero-extensions");
48 STATISTIC(NumOptADDLIs, "Number of optimized ADD instruction fed by LI");
49 STATISTIC(NumConvertedToImmediateForm,
50  "Number of instructions converted to their immediate form");
51 STATISTIC(NumFunctionsEnteredInMIPeephole,
52  "Number of functions entered in PPC MI Peepholes");
53 STATISTIC(NumFixedPointIterations,
54  "Number of fixed-point iterations converting reg-reg instructions "
55  "to reg-imm ones");
56 STATISTIC(NumRotatesCollapsed,
57  "Number of pairs of rotate left, clear left/right collapsed");
58 STATISTIC(NumEXTSWAndSLDICombined,
59  "Number of pairs of EXTSW and SLDI combined as EXTSWSLI");
60 STATISTIC(NumLoadImmZeroFoldedAndRemoved,
61  "Number of LI(8) reg, 0 that are folded to r0 and removed");
62 
63 static cl::opt<bool>
64 FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true),
65  cl::desc("Iterate to a fixed point when attempting to "
66  "convert reg-reg instructions to reg-imm"));
67 
68 static cl::opt<bool>
69 ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true),
70  cl::desc("Convert eligible reg+reg instructions to reg+imm"));
71 
72 static cl::opt<bool>
73  EnableSExtElimination("ppc-eliminate-signext",
74  cl::desc("enable elimination of sign-extensions"),
75  cl::init(false), cl::Hidden);
76 
77 static cl::opt<bool>
78  EnableZExtElimination("ppc-eliminate-zeroext",
79  cl::desc("enable elimination of zero-extensions"),
80  cl::init(false), cl::Hidden);
81 
82 namespace {
83 
84 struct PPCMIPeephole : public MachineFunctionPass {
85 
86  static char ID;
87  const PPCInstrInfo *TII;
88  MachineFunction *MF;
90 
91  PPCMIPeephole() : MachineFunctionPass(ID) {
93  }
94 
95 private:
99  uint64_t EntryFreq;
100 
101  // Initialize class variables.
102  void initialize(MachineFunction &MFParm);
103 
104  // Perform peepholes.
105  bool simplifyCode(void);
106 
107  // Perform peepholes.
108  bool eliminateRedundantCompare(void);
109  bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
110  bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
111  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
112  void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
113  MachineInstr *MI);
114 
115 public:
116 
117  void getAnalysisUsage(AnalysisUsage &AU) const override {
125  }
126 
127  // Main entry point for this pass.
128  bool runOnMachineFunction(MachineFunction &MF) override {
129  initialize(MF);
130  // At this point, TOC pointer should not be used in a function that uses
131  // PC-Relative addressing.
132  assert((MF.getRegInfo().use_empty(PPC::X2) ||
134  "TOC pointer used in a function using PC-Relative addressing!");
135  if (skipFunction(MF.getFunction()))
136  return false;
137  return simplifyCode();
138  }
139 };
140 
141 // Initialize class variables.
143  MF = &MFParm;
144  MRI = &MF->getRegInfo();
145  MDT = &getAnalysis<MachineDominatorTree>();
146  MPDT = &getAnalysis<MachinePostDominatorTree>();
147  MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
148  EntryFreq = MBFI->getEntryFreq();
149  TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
150  LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
151  LLVM_DEBUG(MF->dump());
152 }
153 
154 static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
156  assert(Op && "Invalid Operand!");
157  if (!Op->isReg())
158  return nullptr;
159 
160  Register Reg = Op->getReg();
162  return nullptr;
163 
164  return MRI->getVRegDef(Reg);
165 }
166 
167 // This function returns number of known zero bits in output of MI
168 // starting from the most significant bit.
169 static unsigned
170 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
171  unsigned Opcode = MI->getOpcode();
172  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec ||
173  Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec)
174  return MI->getOperand(3).getImm();
175 
176  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) &&
177  MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
178  return MI->getOperand(3).getImm();
179 
180  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec ||
181  Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec ||
182  Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
183  MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
184  return 32 + MI->getOperand(3).getImm();
185 
186  if (Opcode == PPC::ANDI_rec) {
187  uint16_t Imm = MI->getOperand(2).getImm();
188  return 48 + countLeadingZeros(Imm);
189  }
190 
191  if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec ||
192  Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec ||
193  Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
194  // The result ranges from 0 to 32.
195  return 58;
196 
197  if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec ||
198  Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec)
199  // The result ranges from 0 to 64.
200  return 57;
201 
202  if (Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
203  Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
204  Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
205  Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8)
206  return 48;
207 
208  if (Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
209  Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
210  Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
211  Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
212  return 56;
213 
214  if (TII->isZeroExtended(*MI))
215  return 32;
216 
217  return 0;
218 }
219 
220 // This function maintains a map for the pairs <TOC Save Instr, Keep>
221 // Each time a new TOC save is encountered, it checks if any of the existing
222 // ones are dominated by the new one. If so, it marks the existing one as
223 // redundant by setting it's entry in the map as false. It then adds the new
224 // instruction to the map with either true or false depending on if any
225 // existing instructions dominated the new one.
226 void PPCMIPeephole::UpdateTOCSaves(
227  std::map<MachineInstr *, bool> &TOCSaves, MachineInstr *MI) {
228  assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
229  // FIXME: Saving TOC in prologue hasn't been implemented well in AIX ABI part,
230  // here only support it under ELFv2.
231  if (MF->getSubtarget<PPCSubtarget>().isELFv2ABI()) {
233 
234  MachineBasicBlock *Entry = &MF->front();
235  uint64_t CurrBlockFreq = MBFI->getBlockFreq(MI->getParent()).getFrequency();
236 
237  // If the block in which the TOC save resides is in a block that
238  // post-dominates Entry, or a block that is hotter than entry (keep in mind
239  // that early MachineLICM has already run so the TOC save won't be hoisted)
240  // we can just do the save in the prologue.
241  if (CurrBlockFreq > EntryFreq || MPDT->dominates(MI->getParent(), Entry))
242  FI->setMustSaveTOC(true);
243 
244  // If we are saving the TOC in the prologue, all the TOC saves can be
245  // removed from the code.
246  if (FI->mustSaveTOC()) {
247  for (auto &TOCSave : TOCSaves)
248  TOCSave.second = false;
249  // Add new instruction to map.
250  TOCSaves[MI] = false;
251  return;
252  }
253  }
254 
255  bool Keep = true;
256  for (auto It = TOCSaves.begin(); It != TOCSaves.end(); It++ ) {
257  MachineInstr *CurrInst = It->first;
258  // If new instruction dominates an existing one, mark existing one as
259  // redundant.
260  if (It->second && MDT->dominates(MI, CurrInst))
261  It->second = false;
262  // Check if the new instruction is redundant.
263  if (MDT->dominates(CurrInst, MI)) {
264  Keep = false;
265  break;
266  }
267  }
268  // Add new instruction to map.
269  TOCSaves[MI] = Keep;
270 }
271 
272 // This function returns a list of all PHI nodes in the tree starting from
273 // the RootPHI node. We perform a BFS traversal to get an ordered list of nodes.
274 // The list initially only contains the root PHI. When we visit a PHI node, we
275 // add it to the list. We continue to look for other PHI node operands while
276 // there are nodes to visit in the list. The function returns false if the
277 // optimization cannot be applied on this tree.
278 static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
279  MachineInstr *RootPHI,
281  PHIs.push_back(RootPHI);
282  unsigned VisitedIndex = 0;
283  while (VisitedIndex < PHIs.size()) {
284  MachineInstr *VisitedPHI = PHIs[VisitedIndex];
285  for (unsigned PHIOp = 1, NumOps = VisitedPHI->getNumOperands();
286  PHIOp != NumOps; PHIOp += 2) {
287  Register RegOp = VisitedPHI->getOperand(PHIOp).getReg();
288  if (!Register::isVirtualRegister(RegOp))
289  return false;
290  MachineInstr *Instr = MRI->getVRegDef(RegOp);
291  // While collecting the PHI nodes, we check if they can be converted (i.e.
292  // all the operands are either copies, implicit defs or PHI nodes).
293  unsigned Opcode = Instr->getOpcode();
294  if (Opcode == PPC::COPY) {
295  Register Reg = Instr->getOperand(1).getReg();
297  MRI->getRegClass(Reg) != &PPC::ACCRCRegClass)
298  return false;
299  } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI)
300  return false;
301  // If we detect a cycle in the PHI nodes, we exit. It would be
302  // possible to change cycles as well, but that would add a lot
303  // of complexity for a case that is unlikely to occur with MMA
304  // code.
305  if (Opcode != PPC::PHI)
306  continue;
307  if (llvm::is_contained(PHIs, Instr))
308  return false;
309  PHIs.push_back(Instr);
310  }
311  VisitedIndex++;
312  }
313  return true;
314 }
315 
316 // This function changes the unprimed accumulator PHI nodes in the PHIs list to
317 // primed accumulator PHI nodes. The list is traversed in reverse order to
318 // change all the PHI operands of a PHI node before changing the node itself.
319 // We keep a map to associate each changed PHI node to its non-changed form.
320 static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
323  Register Dst) {
325  for (auto It = PHIs.rbegin(), End = PHIs.rend(); It != End; ++It) {
326  MachineInstr *PHI = *It;
328  // We check if the current PHI node can be changed by looking at its
329  // operands. If all the operands are either copies from primed
330  // accumulators, implicit definitions or other unprimed accumulator
331  // PHI nodes, we change it.
332  for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
333  PHIOp += 2) {
334  Register RegOp = PHI->getOperand(PHIOp).getReg();
335  MachineInstr *PHIInput = MRI->getVRegDef(RegOp);
336  unsigned Opcode = PHIInput->getOpcode();
337  assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF ||
338  Opcode == PPC::PHI) &&
339  "Unexpected instruction");
340  if (Opcode == PPC::COPY) {
341  assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) ==
342  &PPC::ACCRCRegClass &&
343  "Unexpected register class");
344  PHIOps.push_back({PHIInput->getOperand(1), PHI->getOperand(PHIOp + 1)});
345  } else if (Opcode == PPC::IMPLICIT_DEF) {
346  Register AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
347  BuildMI(*PHIInput->getParent(), PHIInput, PHIInput->getDebugLoc(),
348  TII->get(PPC::IMPLICIT_DEF), AccReg);
349  PHIOps.push_back({MachineOperand::CreateReg(AccReg, false),
350  PHI->getOperand(PHIOp + 1)});
351  } else if (Opcode == PPC::PHI) {
352  // We found a PHI operand. At this point we know this operand
353  // has already been changed so we get its associated changed form
354  // from the map.
355  assert(ChangedPHIMap.count(PHIInput) == 1 &&
356  "This PHI node should have already been changed.");
357  MachineInstr *PrimedAccPHI = ChangedPHIMap.lookup(PHIInput);
358  PHIOps.push_back({MachineOperand::CreateReg(
359  PrimedAccPHI->getOperand(0).getReg(), false),
360  PHI->getOperand(PHIOp + 1)});
361  }
362  }
363  Register AccReg = Dst;
364  // If the PHI node we are changing is the root node, the register it defines
365  // will be the destination register of the original copy (of the PHI def).
366  // For all other PHI's in the list, we need to create another primed
367  // accumulator virtual register as the PHI will no longer define the
368  // unprimed accumulator.
369  if (PHI != PHIs[0])
370  AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
371  MachineInstrBuilder NewPHI = BuildMI(
372  *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg);
373  for (auto RegMBB : PHIOps)
374  NewPHI.add(RegMBB.first).add(RegMBB.second);
375  ChangedPHIMap[PHI] = NewPHI.getInstr();
376  }
377 }
378 
379 // Perform peephole optimizations.
380 bool PPCMIPeephole::simplifyCode(void) {
381  bool Simplified = false;
382  MachineInstr* ToErase = nullptr;
383  std::map<MachineInstr *, bool> TOCSaves;
384  const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
385  NumFunctionsEnteredInMIPeephole++;
386  if (ConvertRegReg) {
387  // Fixed-point conversion of reg/reg instructions fed by load-immediate
388  // into reg/imm instructions. FIXME: This is expensive, control it with
389  // an option.
390  bool SomethingChanged = false;
391  do {
392  NumFixedPointIterations++;
393  SomethingChanged = false;
394  for (MachineBasicBlock &MBB : *MF) {
395  for (MachineInstr &MI : MBB) {
396  if (MI.isDebugInstr())
397  continue;
398 
399  if (TII->convertToImmediateForm(MI)) {
400  // We don't erase anything in case the def has other uses. Let DCE
401  // remove it if it can be removed.
402  LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
403  LLVM_DEBUG(MI.dump());
404  NumConvertedToImmediateForm++;
405  SomethingChanged = true;
406  Simplified = true;
407  continue;
408  }
409  }
410  }
411  } while (SomethingChanged && FixedPointRegToImm);
412  }
413 
414  for (MachineBasicBlock &MBB : *MF) {
415  for (MachineInstr &MI : MBB) {
416 
417  // If the previous instruction was marked for elimination,
418  // remove it now.
419  if (ToErase) {
420  ToErase->eraseFromParent();
421  ToErase = nullptr;
422  }
423 
424  // Ignore debug instructions.
425  if (MI.isDebugInstr())
426  continue;
427 
428  // Per-opcode peepholes.
429  switch (MI.getOpcode()) {
430 
431  default:
432  break;
433  case PPC::COPY: {
434  Register Src = MI.getOperand(1).getReg();
435  Register Dst = MI.getOperand(0).getReg();
436  if (!Register::isVirtualRegister(Src) ||
438  break;
439  if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass ||
440  MRI->getRegClass(Dst) != &PPC::ACCRCRegClass)
441  break;
442 
443  // We are copying an unprimed accumulator to a primed accumulator.
444  // If the input to the copy is a PHI that is fed only by (i) copies in
445  // the other direction (ii) implicitly defined unprimed accumulators or
446  // (iii) other PHI nodes satisfying (i) and (ii), we can change
447  // the PHI to a PHI on primed accumulators (as long as we also change
448  // its operands). To detect and change such copies, we first get a list
449  // of all the PHI nodes starting from the root PHI node in BFS order.
450  // We then visit all these PHI nodes to check if they can be changed to
451  // primed accumulator PHI nodes and if so, we change them.
452  MachineInstr *RootPHI = MRI->getVRegDef(Src);
453  if (RootPHI->getOpcode() != PPC::PHI)
454  break;
455 
457  if (!collectUnprimedAccPHIs(MRI, RootPHI, PHIs))
458  break;
459 
460  convertUnprimedAccPHIs(TII, MRI, PHIs, Dst);
461 
462  ToErase = &MI;
463  break;
464  }
465  case PPC::LI:
466  case PPC::LI8: {
467  // If we are materializing a zero, look for any use operands for which
468  // zero means immediate zero. All such operands can be replaced with
469  // PPC::ZERO.
470  if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0)
471  break;
472  unsigned MIDestReg = MI.getOperand(0).getReg();
473  for (MachineInstr& UseMI : MRI->use_instructions(MIDestReg))
474  Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
475  if (MRI->use_nodbg_empty(MIDestReg)) {
476  ++NumLoadImmZeroFoldedAndRemoved;
477  ToErase = &MI;
478  }
479  break;
480  }
481  case PPC::STW:
482  case PPC::STD: {
483  MachineFrameInfo &MFI = MF->getFrameInfo();
484  if (MFI.hasVarSizedObjects() ||
485  (!MF->getSubtarget<PPCSubtarget>().isELFv2ABI() &&
486  !MF->getSubtarget<PPCSubtarget>().isAIXABI()))
487  break;
488  // When encountering a TOC save instruction, call UpdateTOCSaves
489  // to add it to the TOCSaves map and mark any existing TOC saves
490  // it dominates as redundant.
491  if (TII->isTOCSaveMI(MI))
492  UpdateTOCSaves(TOCSaves, &MI);
493  break;
494  }
495  case PPC::XXPERMDI: {
496  // Perform simplifications of 2x64 vector swaps and splats.
497  // A swap is identified by an immediate value of 2, and a splat
498  // is identified by an immediate value of 0 or 3.
499  int Immed = MI.getOperand(3).getImm();
500 
501  if (Immed == 1)
502  break;
503 
504  // For each of these simplifications, we need the two source
505  // regs to match. Unfortunately, MachineCSE ignores COPY and
506  // SUBREG_TO_REG, so for example we can see
507  // XXPERMDI t, SUBREG_TO_REG(s), SUBREG_TO_REG(s), immed.
508  // We have to look through chains of COPY and SUBREG_TO_REG
509  // to find the real source values for comparison.
510  unsigned TrueReg1 =
511  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
512  unsigned TrueReg2 =
513  TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
514 
515  if (!(TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)))
516  break;
517 
518  MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
519 
520  if (!DefMI)
521  break;
522 
523  unsigned DefOpc = DefMI->getOpcode();
524 
525  // If this is a splat fed by a splatting load, the splat is
526  // redundant. Replace with a copy. This doesn't happen directly due
527  // to code in PPCDAGToDAGISel.cpp, but it can happen when converting
528  // a load of a double to a vector of 64-bit integers.
529  auto isConversionOfLoadAndSplat = [=]() -> bool {
530  if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS)
531  return false;
532  unsigned FeedReg1 =
534  if (Register::isVirtualRegister(FeedReg1)) {
535  MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1);
536  if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX)
537  return true;
538  }
539  return false;
540  };
541  if ((Immed == 0 || Immed == 3) &&
542  (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) {
543  LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
544  "to load-and-splat/copy: ");
545  LLVM_DEBUG(MI.dump());
546  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
547  MI.getOperand(0).getReg())
548  .add(MI.getOperand(1));
549  ToErase = &MI;
550  Simplified = true;
551  }
552 
553  // If this is a splat or a swap fed by another splat, we
554  // can replace it with a copy.
555  if (DefOpc == PPC::XXPERMDI) {
556  unsigned DefReg1 = DefMI->getOperand(1).getReg();
557  unsigned DefReg2 = DefMI->getOperand(2).getReg();
558  unsigned DefImmed = DefMI->getOperand(3).getImm();
559 
560  // If the two inputs are not the same register, check to see if
561  // they originate from the same virtual register after only
562  // copy-like instructions.
563  if (DefReg1 != DefReg2) {
564  unsigned FeedReg1 = TRI->lookThruCopyLike(DefReg1, MRI);
565  unsigned FeedReg2 = TRI->lookThruCopyLike(DefReg2, MRI);
566 
567  if (!(FeedReg1 == FeedReg2 &&
568  Register::isVirtualRegister(FeedReg1)))
569  break;
570  }
571 
572  if (DefImmed == 0 || DefImmed == 3) {
573  LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
574  "to splat/copy: ");
575  LLVM_DEBUG(MI.dump());
576  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
577  MI.getOperand(0).getReg())
578  .add(MI.getOperand(1));
579  ToErase = &MI;
580  Simplified = true;
581  }
582 
583  // If this is a splat fed by a swap, we can simplify modify
584  // the splat to splat the other value from the swap's input
585  // parameter.
586  else if ((Immed == 0 || Immed == 3) && DefImmed == 2) {
587  LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
588  LLVM_DEBUG(MI.dump());
589  MI.getOperand(1).setReg(DefReg1);
590  MI.getOperand(2).setReg(DefReg2);
591  MI.getOperand(3).setImm(3 - Immed);
592  Simplified = true;
593  }
594 
595  // If this is a swap fed by a swap, we can replace it
596  // with a copy from the first swap's input.
597  else if (Immed == 2 && DefImmed == 2) {
598  LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
599  LLVM_DEBUG(MI.dump());
600  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
601  MI.getOperand(0).getReg())
602  .add(DefMI->getOperand(1));
603  ToErase = &MI;
604  Simplified = true;
605  }
606  } else if ((Immed == 0 || Immed == 3) && DefOpc == PPC::XXPERMDIs &&
607  (DefMI->getOperand(2).getImm() == 0 ||
608  DefMI->getOperand(2).getImm() == 3)) {
609  // Splat fed by another splat - switch the output of the first
610  // and remove the second.
611  DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
612  ToErase = &MI;
613  Simplified = true;
614  LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
615  LLVM_DEBUG(MI.dump());
616  }
617  break;
618  }
619  case PPC::VSPLTB:
620  case PPC::VSPLTH:
621  case PPC::XXSPLTW: {
622  unsigned MyOpcode = MI.getOpcode();
623  unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
624  unsigned TrueReg =
625  TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
626  if (!Register::isVirtualRegister(TrueReg))
627  break;
628  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
629  if (!DefMI)
630  break;
631  unsigned DefOpcode = DefMI->getOpcode();
632  auto isConvertOfSplat = [=]() -> bool {
633  if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS)
634  return false;
635  Register ConvReg = DefMI->getOperand(1).getReg();
636  if (!Register::isVirtualRegister(ConvReg))
637  return false;
638  MachineInstr *Splt = MRI->getVRegDef(ConvReg);
639  return Splt && (Splt->getOpcode() == PPC::LXVWSX ||
640  Splt->getOpcode() == PPC::XXSPLTW);
641  };
642  bool AlreadySplat = (MyOpcode == DefOpcode) ||
643  (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
644  (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
645  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) ||
646  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) ||
647  (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)||
648  (MyOpcode == PPC::XXSPLTW && isConvertOfSplat());
649  // If the instruction[s] that feed this splat have already splat
650  // the value, this splat is redundant.
651  if (AlreadySplat) {
652  LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
653  LLVM_DEBUG(MI.dump());
654  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
655  MI.getOperand(0).getReg())
656  .add(MI.getOperand(OpNo));
657  ToErase = &MI;
658  Simplified = true;
659  }
660  // Splat fed by a shift. Usually when we align value to splat into
661  // vector element zero.
662  if (DefOpcode == PPC::XXSLDWI) {
663  Register ShiftRes = DefMI->getOperand(0).getReg();
664  Register ShiftOp1 = DefMI->getOperand(1).getReg();
665  Register ShiftOp2 = DefMI->getOperand(2).getReg();
666  unsigned ShiftImm = DefMI->getOperand(3).getImm();
667  unsigned SplatImm =
668  MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm();
669  if (ShiftOp1 == ShiftOp2) {
670  unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
671  if (MRI->hasOneNonDBGUse(ShiftRes)) {
672  LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
673  LLVM_DEBUG(DefMI->dump());
674  ToErase = DefMI;
675  }
676  Simplified = true;
677  LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
678  << " to " << NewElem << " in instruction: ");
679  LLVM_DEBUG(MI.dump());
680  MI.getOperand(1).setReg(ShiftOp1);
681  MI.getOperand(2).setImm(NewElem);
682  }
683  }
684  break;
685  }
686  case PPC::XVCVDPSP: {
687  // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
688  unsigned TrueReg =
689  TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
690  if (!Register::isVirtualRegister(TrueReg))
691  break;
692  MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
693 
694  // This can occur when building a vector of single precision or integer
695  // values.
696  if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) {
697  unsigned DefsReg1 =
699  unsigned DefsReg2 =
701  if (!Register::isVirtualRegister(DefsReg1) ||
702  !Register::isVirtualRegister(DefsReg2))
703  break;
704  MachineInstr *P1 = MRI->getVRegDef(DefsReg1);
705  MachineInstr *P2 = MRI->getVRegDef(DefsReg2);
706 
707  if (!P1 || !P2)
708  break;
709 
710  // Remove the passed FRSP/XSRSP instruction if it only feeds this MI
711  // and set any uses of that FRSP/XSRSP (in this MI) to the source of
712  // the FRSP/XSRSP.
713  auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
714  unsigned Opc = RoundInstr->getOpcode();
715  if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) &&
716  MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
717  Simplified = true;
718  Register ConvReg1 = RoundInstr->getOperand(1).getReg();
719  Register FRSPDefines = RoundInstr->getOperand(0).getReg();
720  MachineInstr &Use = *(MRI->use_instr_nodbg_begin(FRSPDefines));
721  for (int i = 0, e = Use.getNumOperands(); i < e; ++i)
722  if (Use.getOperand(i).isReg() &&
723  Use.getOperand(i).getReg() == FRSPDefines)
724  Use.getOperand(i).setReg(ConvReg1);
725  LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n");
726  LLVM_DEBUG(RoundInstr->dump());
727  LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
728  LLVM_DEBUG(MI.dump());
729  LLVM_DEBUG(dbgs() << "Through instruction:\n");
730  LLVM_DEBUG(DefMI->dump());
731  RoundInstr->eraseFromParent();
732  }
733  };
734 
735  // If the input to XVCVDPSP is a vector that was built (even
736  // partially) out of FRSP's, the FRSP(s) can safely be removed
737  // since this instruction performs the same operation.
738  if (P1 != P2) {
739  removeFRSPIfPossible(P1);
740  removeFRSPIfPossible(P2);
741  break;
742  }
743  removeFRSPIfPossible(P1);
744  }
745  break;
746  }
747  case PPC::EXTSH:
748  case PPC::EXTSH8:
749  case PPC::EXTSH8_32_64: {
750  if (!EnableSExtElimination) break;
751  Register NarrowReg = MI.getOperand(1).getReg();
752  if (!Register::isVirtualRegister(NarrowReg))
753  break;
754 
755  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
756  // If we've used a zero-extending load that we will sign-extend,
757  // just do a sign-extending load.
758  if (SrcMI->getOpcode() == PPC::LHZ ||
759  SrcMI->getOpcode() == PPC::LHZX) {
760  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
761  break;
762  auto is64Bit = [] (unsigned Opcode) {
763  return Opcode == PPC::EXTSH8;
764  };
765  auto isXForm = [] (unsigned Opcode) {
766  return Opcode == PPC::LHZX;
767  };
768  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
769  if (is64Bit)
770  if (isXForm) return PPC::LHAX8;
771  else return PPC::LHA8;
772  else
773  if (isXForm) return PPC::LHAX;
774  else return PPC::LHA;
775  };
776  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
777  isXForm(SrcMI->getOpcode()));
778  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
779  LLVM_DEBUG(SrcMI->dump());
780  LLVM_DEBUG(dbgs() << "and sign-extension\n");
781  LLVM_DEBUG(MI.dump());
782  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
783  SrcMI->setDesc(TII->get(Opc));
784  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
785  ToErase = &MI;
786  Simplified = true;
787  NumEliminatedSExt++;
788  }
789  break;
790  }
791  case PPC::EXTSW:
792  case PPC::EXTSW_32:
793  case PPC::EXTSW_32_64: {
794  if (!EnableSExtElimination) break;
795  Register NarrowReg = MI.getOperand(1).getReg();
796  if (!Register::isVirtualRegister(NarrowReg))
797  break;
798 
799  MachineInstr *SrcMI = MRI->getVRegDef(NarrowReg);
800  // If we've used a zero-extending load that we will sign-extend,
801  // just do a sign-extending load.
802  if (SrcMI->getOpcode() == PPC::LWZ ||
803  SrcMI->getOpcode() == PPC::LWZX) {
804  if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
805  break;
806  auto is64Bit = [] (unsigned Opcode) {
807  return Opcode == PPC::EXTSW || Opcode == PPC::EXTSW_32_64;
808  };
809  auto isXForm = [] (unsigned Opcode) {
810  return Opcode == PPC::LWZX;
811  };
812  auto getSextLoadOp = [] (bool is64Bit, bool isXForm) {
813  if (is64Bit)
814  if (isXForm) return PPC::LWAX;
815  else return PPC::LWA;
816  else
817  if (isXForm) return PPC::LWAX_32;
818  else return PPC::LWA_32;
819  };
820  unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()),
821  isXForm(SrcMI->getOpcode()));
822  LLVM_DEBUG(dbgs() << "Zero-extending load\n");
823  LLVM_DEBUG(SrcMI->dump());
824  LLVM_DEBUG(dbgs() << "and sign-extension\n");
825  LLVM_DEBUG(MI.dump());
826  LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
827  SrcMI->setDesc(TII->get(Opc));
828  SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
829  ToErase = &MI;
830  Simplified = true;
831  NumEliminatedSExt++;
832  } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
833  TII->isSignExtended(*SrcMI)) {
834  // We can eliminate EXTSW if the input is known to be already
835  // sign-extended.
836  LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
837  Register TmpReg =
838  MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
839  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
840  TmpReg);
841  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
842  MI.getOperand(0).getReg())
843  .addReg(TmpReg)
844  .addReg(NarrowReg)
845  .addImm(PPC::sub_32);
846  ToErase = &MI;
847  Simplified = true;
848  NumEliminatedSExt++;
849  }
850  break;
851  }
852  case PPC::RLDICL: {
853  // We can eliminate RLDICL (e.g. for zero-extension)
854  // if all bits to clear are already zero in the input.
855  // This code assume following code sequence for zero-extension.
856  // %6 = COPY %5:sub_32; (optional)
857  // %8 = IMPLICIT_DEF;
858  // %7<def,tied1> = INSERT_SUBREG %8<tied0>, %6, sub_32;
859  if (!EnableZExtElimination) break;
860 
861  if (MI.getOperand(2).getImm() != 0)
862  break;
863 
864  Register SrcReg = MI.getOperand(1).getReg();
865  if (!Register::isVirtualRegister(SrcReg))
866  break;
867 
868  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
869  if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG &&
870  SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
871  break;
872 
873  MachineInstr *ImpDefMI, *SubRegMI;
874  ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
875  SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
876  if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break;
877 
878  SrcMI = SubRegMI;
879  if (SubRegMI->getOpcode() == PPC::COPY) {
880  Register CopyReg = SubRegMI->getOperand(1).getReg();
881  if (Register::isVirtualRegister(CopyReg))
882  SrcMI = MRI->getVRegDef(CopyReg);
883  }
884 
885  unsigned KnownZeroCount = getKnownLeadingZeroCount(SrcMI, TII);
886  if (MI.getOperand(3).getImm() <= KnownZeroCount) {
887  LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
888  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
889  MI.getOperand(0).getReg())
890  .addReg(SrcReg);
891  ToErase = &MI;
892  Simplified = true;
893  NumEliminatedZExt++;
894  }
895  break;
896  }
897 
898  // TODO: Any instruction that has an immediate form fed only by a PHI
899  // whose operands are all load immediate can be folded away. We currently
900  // do this for ADD instructions, but should expand it to arithmetic and
901  // binary instructions with immediate forms in the future.
902  case PPC::ADD4:
903  case PPC::ADD8: {
904  auto isSingleUsePHI = [&](MachineOperand *PhiOp) {
905  assert(PhiOp && "Invalid Operand!");
906  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
907 
908  return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) &&
909  MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg());
910  };
911 
912  auto dominatesAllSingleUseLIs = [&](MachineOperand *DominatorOp,
913  MachineOperand *PhiOp) {
914  assert(PhiOp && "Invalid Operand!");
915  assert(DominatorOp && "Invalid Operand!");
916  MachineInstr *DefPhiMI = getVRegDefOrNull(PhiOp, MRI);
917  MachineInstr *DefDomMI = getVRegDefOrNull(DominatorOp, MRI);
918 
919  // Note: the vregs only show up at odd indices position of PHI Node,
920  // the even indices position save the BB info.
921  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
922  MachineInstr *LiMI =
923  getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
924  if (!LiMI ||
925  (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8)
926  || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) ||
927  !MDT->dominates(DefDomMI, LiMI))
928  return false;
929  }
930 
931  return true;
932  };
933 
934  MachineOperand Op1 = MI.getOperand(1);
935  MachineOperand Op2 = MI.getOperand(2);
936  if (isSingleUsePHI(&Op2) && dominatesAllSingleUseLIs(&Op1, &Op2))
937  std::swap(Op1, Op2);
938  else if (!isSingleUsePHI(&Op1) || !dominatesAllSingleUseLIs(&Op2, &Op1))
939  break; // We don't have an ADD fed by LI's that can be transformed
940 
941  // Now we know that Op1 is the PHI node and Op2 is the dominator
942  Register DominatorReg = Op2.getReg();
943 
944  const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
945  ? &PPC::G8RC_and_G8RC_NOX0RegClass
946  : &PPC::GPRC_and_GPRC_NOR0RegClass;
947  MRI->setRegClass(DominatorReg, TRC);
948 
949  // replace LIs with ADDIs
950  MachineInstr *DefPhiMI = getVRegDefOrNull(&Op1, MRI);
951  for (unsigned i = 1; i < DefPhiMI->getNumOperands(); i += 2) {
952  MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
953  LLVM_DEBUG(dbgs() << "Optimizing LI to ADDI: ");
954  LLVM_DEBUG(LiMI->dump());
955 
956  // There could be repeated registers in the PHI, e.g: %1 =
957  // PHI %6, <%bb.2>, %8, <%bb.3>, %8, <%bb.6>; So if we've
958  // already replaced the def instruction, skip.
959  if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8)
960  continue;
961 
962  assert((LiMI->getOpcode() == PPC::LI ||
963  LiMI->getOpcode() == PPC::LI8) &&
964  "Invalid Opcode!");
965  auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI
966  LiMI->RemoveOperand(1); // remove the imm of LI
967  LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
968  : PPC::ADDI8));
969  MachineInstrBuilder(*LiMI->getParent()->getParent(), *LiMI)
970  .addReg(DominatorReg)
971  .addImm(LiImm); // restore the imm of LI
972  LLVM_DEBUG(LiMI->dump());
973  }
974 
975  // Replace ADD with COPY
976  LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
977  LLVM_DEBUG(MI.dump());
978  BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
979  MI.getOperand(0).getReg())
980  .add(Op1);
981  ToErase = &MI;
982  Simplified = true;
983  NumOptADDLIs++;
984  break;
985  }
986  case PPC::RLDICR: {
987  Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
988  combineSEXTAndSHL(MI, ToErase);
989  break;
990  }
991  case PPC::RLWINM:
992  case PPC::RLWINM_rec:
993  case PPC::RLWINM8:
994  case PPC::RLWINM8_rec: {
995  Simplified = TII->combineRLWINM(MI, &ToErase);
996  if (Simplified)
997  ++NumRotatesCollapsed;
998  break;
999  }
1000  }
1001  }
1002 
1003  // If the last instruction was marked for elimination,
1004  // remove it now.
1005  if (ToErase) {
1006  ToErase->eraseFromParent();
1007  ToErase = nullptr;
1008  }
1009  }
1010 
1011  // Eliminate all the TOC save instructions which are redundant.
1012  Simplified |= eliminateRedundantTOCSaves(TOCSaves);
1013  PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
1014  if (FI->mustSaveTOC())
1015  NumTOCSavesInPrologue++;
1016 
1017  // We try to eliminate redundant compare instruction.
1018  Simplified |= eliminateRedundantCompare();
1019 
1020  return Simplified;
1021 }
1022 
1023 // helper functions for eliminateRedundantCompare
1024 static bool isEqOrNe(MachineInstr *BI) {
1026  unsigned PredCond = PPC::getPredicateCondition(Pred);
1027  return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE);
1028 }
1029 
1030 static bool isSupportedCmpOp(unsigned opCode) {
1031  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1032  opCode == PPC::CMPLW || opCode == PPC::CMPW ||
1033  opCode == PPC::CMPLDI || opCode == PPC::CMPDI ||
1034  opCode == PPC::CMPLWI || opCode == PPC::CMPWI);
1035 }
1036 
1037 static bool is64bitCmpOp(unsigned opCode) {
1038  return (opCode == PPC::CMPLD || opCode == PPC::CMPD ||
1039  opCode == PPC::CMPLDI || opCode == PPC::CMPDI);
1040 }
1041 
1042 static bool isSignedCmpOp(unsigned opCode) {
1043  return (opCode == PPC::CMPD || opCode == PPC::CMPW ||
1044  opCode == PPC::CMPDI || opCode == PPC::CMPWI);
1045 }
1046 
1047 static unsigned getSignedCmpOpCode(unsigned opCode) {
1048  if (opCode == PPC::CMPLD) return PPC::CMPD;
1049  if (opCode == PPC::CMPLW) return PPC::CMPW;
1050  if (opCode == PPC::CMPLDI) return PPC::CMPDI;
1051  if (opCode == PPC::CMPLWI) return PPC::CMPWI;
1052  return opCode;
1053 }
1054 
1055 // We can decrement immediate x in (GE x) by changing it to (GT x-1) or
1056 // (LT x) to (LE x-1)
1057 static unsigned getPredicateToDecImm(MachineInstr *BI, MachineInstr *CMPI) {
1058  uint64_t Imm = CMPI->getOperand(2).getImm();
1059  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
1060  if ((!SignedCmp && Imm == 0) || (SignedCmp && Imm == 0x8000))
1061  return 0;
1062 
1064  unsigned PredCond = PPC::getPredicateCondition(Pred);
1065  unsigned PredHint = PPC::getPredicateHint(Pred);
1066  if (PredCond == PPC::PRED_GE)
1067  return PPC::getPredicate(PPC::PRED_GT, PredHint);
1068  if (PredCond == PPC::PRED_LT)
1069  return PPC::getPredicate(PPC::PRED_LE, PredHint);
1070 
1071  return 0;
1072 }
1073 
1074 // We can increment immediate x in (GT x) by changing it to (GE x+1) or
1075 // (LE x) to (LT x+1)
1076 static unsigned getPredicateToIncImm(MachineInstr *BI, MachineInstr *CMPI) {
1077  uint64_t Imm = CMPI->getOperand(2).getImm();
1078  bool SignedCmp = isSignedCmpOp(CMPI->getOpcode());
1079  if ((!SignedCmp && Imm == 0xFFFF) || (SignedCmp && Imm == 0x7FFF))
1080  return 0;
1081 
1083  unsigned PredCond = PPC::getPredicateCondition(Pred);
1084  unsigned PredHint = PPC::getPredicateHint(Pred);
1085  if (PredCond == PPC::PRED_GT)
1086  return PPC::getPredicate(PPC::PRED_GE, PredHint);
1087  if (PredCond == PPC::PRED_LE)
1088  return PPC::getPredicate(PPC::PRED_LT, PredHint);
1089 
1090  return 0;
1091 }
1092 
1093 // This takes a Phi node and returns a register value for the specified BB.
1094 static unsigned getIncomingRegForBlock(MachineInstr *Phi,
1096  for (unsigned I = 2, E = Phi->getNumOperands() + 1; I != E; I += 2) {
1097  MachineOperand &MO = Phi->getOperand(I);
1098  if (MO.getMBB() == MBB)
1099  return Phi->getOperand(I-1).getReg();
1100  }
1101  llvm_unreachable("invalid src basic block for this Phi node\n");
1102  return 0;
1103 }
1104 
1105 // This function tracks the source of the register through register copy.
1106 // If BB1 and BB2 are non-NULL, we also track PHI instruction in BB2
1107 // assuming that the control comes from BB1 into BB2.
1108 static unsigned getSrcVReg(unsigned Reg, MachineBasicBlock *BB1,
1110  unsigned SrcReg = Reg;
1111  while (1) {
1112  unsigned NextReg = SrcReg;
1113  MachineInstr *Inst = MRI->getVRegDef(SrcReg);
1114  if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) {
1115  NextReg = getIncomingRegForBlock(Inst, BB1);
1116  // We track through PHI only once to avoid infinite loop.
1117  BB1 = nullptr;
1118  }
1119  else if (Inst->isFullCopy())
1120  NextReg = Inst->getOperand(1).getReg();
1121  if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
1122  break;
1123  SrcReg = NextReg;
1124  }
1125  return SrcReg;
1126 }
1127 
1128 static bool eligibleForCompareElimination(MachineBasicBlock &MBB,
1129  MachineBasicBlock *&PredMBB,
1130  MachineBasicBlock *&MBBtoMoveCmp,
1132 
1133  auto isEligibleBB = [&](MachineBasicBlock &BB) {
1134  auto BII = BB.getFirstInstrTerminator();
1135  // We optimize BBs ending with a conditional branch.
1136  // We check only for BCC here, not BCCLR, because BCCLR
1137  // will be formed only later in the pipeline.
1138  if (BB.succ_size() == 2 &&
1139  BII != BB.instr_end() &&
1140  (*BII).getOpcode() == PPC::BCC &&
1141  (*BII).getOperand(1).isReg()) {
1142  // We optimize only if the condition code is used only by one BCC.
1143  Register CndReg = (*BII).getOperand(1).getReg();
1144  if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg))
1145  return false;
1146 
1147  MachineInstr *CMPI = MRI->getVRegDef(CndReg);
1148  // We assume compare and branch are in the same BB for ease of analysis.
1149  if (CMPI->getParent() != &BB)
1150  return false;
1151 
1152  // We skip this BB if a physical register is used in comparison.
1153  for (MachineOperand &MO : CMPI->operands())
1154  if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1155  return false;
1156 
1157  return true;
1158  }
1159  return false;
1160  };
1161 
1162  // If this BB has more than one successor, we can create a new BB and
1163  // move the compare instruction in the new BB.
1164  // So far, we do not move compare instruction to a BB having multiple
1165  // successors to avoid potentially increasing code size.
1166  auto isEligibleForMoveCmp = [](MachineBasicBlock &BB) {
1167  return BB.succ_size() == 1;
1168  };
1169 
1170  if (!isEligibleBB(MBB))
1171  return false;
1172 
1173  unsigned NumPredBBs = MBB.pred_size();
1174  if (NumPredBBs == 1) {
1175  MachineBasicBlock *TmpMBB = *MBB.pred_begin();
1176  if (isEligibleBB(*TmpMBB)) {
1177  PredMBB = TmpMBB;
1178  MBBtoMoveCmp = nullptr;
1179  return true;
1180  }
1181  }
1182  else if (NumPredBBs == 2) {
1183  // We check for partially redundant case.
1184  // So far, we support cases with only two predecessors
1185  // to avoid increasing the number of instructions.
1187  MachineBasicBlock *Pred1MBB = *PI;
1188  MachineBasicBlock *Pred2MBB = *(PI+1);
1189 
1190  if (isEligibleBB(*Pred1MBB) && isEligibleForMoveCmp(*Pred2MBB)) {
1191  // We assume Pred1MBB is the BB containing the compare to be merged and
1192  // Pred2MBB is the BB to which we will append a compare instruction.
1193  // Hence we can proceed as is.
1194  }
1195  else if (isEligibleBB(*Pred2MBB) && isEligibleForMoveCmp(*Pred1MBB)) {
1196  // We need to swap Pred1MBB and Pred2MBB to canonicalize.
1197  std::swap(Pred1MBB, Pred2MBB);
1198  }
1199  else return false;
1200 
1201  // Here, Pred2MBB is the BB to which we need to append a compare inst.
1202  // We cannot move the compare instruction if operands are not available
1203  // in Pred2MBB (i.e. defined in MBB by an instruction other than PHI).
1205  MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
1206  for (int I = 1; I <= 2; I++)
1207  if (CMPI->getOperand(I).isReg()) {
1208  MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg());
1209  if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI)
1210  return false;
1211  }
1212 
1213  PredMBB = Pred1MBB;
1214  MBBtoMoveCmp = Pred2MBB;
1215  return true;
1216  }
1217 
1218  return false;
1219 }
1220 
1221 // This function will iterate over the input map containing a pair of TOC save
1222 // instruction and a flag. The flag will be set to false if the TOC save is
1223 // proven redundant. This function will erase from the basic block all the TOC
1224 // saves marked as redundant.
1225 bool PPCMIPeephole::eliminateRedundantTOCSaves(
1226  std::map<MachineInstr *, bool> &TOCSaves) {
1227  bool Simplified = false;
1228  int NumKept = 0;
1229  for (auto TOCSave : TOCSaves) {
1230  if (!TOCSave.second) {
1231  TOCSave.first->eraseFromParent();
1232  RemoveTOCSave++;
1233  Simplified = true;
1234  } else {
1235  NumKept++;
1236  }
1237  }
1238 
1239  if (NumKept > 1)
1240  MultiTOCSaves++;
1241 
1242  return Simplified;
1243 }
1244 
1245 // If multiple conditional branches are executed based on the (essentially)
1246 // same comparison, we merge compare instructions into one and make multiple
1247 // conditional branches on this comparison.
1248 // For example,
1249 // if (a == 0) { ... }
1250 // else if (a < 0) { ... }
1251 // can be executed by one compare and two conditional branches instead of
1252 // two pairs of a compare and a conditional branch.
1253 //
1254 // This method merges two compare instructions in two MBBs and modifies the
1255 // compare and conditional branch instructions if needed.
1256 // For the above example, the input for this pass looks like:
1257 // cmplwi r3, 0
1258 // beq 0, .LBB0_3
1259 // cmpwi r3, -1
1260 // bgt 0, .LBB0_4
1261 // So, before merging two compares, we need to modify these instructions as
1262 // cmpwi r3, 0 ; cmplwi and cmpwi yield same result for beq
1263 // beq 0, .LBB0_3
1264 // cmpwi r3, 0 ; greather than -1 means greater or equal to 0
1265 // bge 0, .LBB0_4
1266 
1267 bool PPCMIPeephole::eliminateRedundantCompare(void) {
1268  bool Simplified = false;
1269 
1270  for (MachineBasicBlock &MBB2 : *MF) {
1271  MachineBasicBlock *MBB1 = nullptr, *MBBtoMoveCmp = nullptr;
1272 
1273  // For fully redundant case, we select two basic blocks MBB1 and MBB2
1274  // as an optimization target if
1275  // - both MBBs end with a conditional branch,
1276  // - MBB1 is the only predecessor of MBB2, and
1277  // - compare does not take a physical register as a operand in both MBBs.
1278  // In this case, eligibleForCompareElimination sets MBBtoMoveCmp nullptr.
1279  //
1280  // As partially redundant case, we additionally handle if MBB2 has one
1281  // additional predecessor, which has only one successor (MBB2).
1282  // In this case, we move the compare instruction originally in MBB2 into
1283  // MBBtoMoveCmp. This partially redundant case is typically appear by
1284  // compiling a while loop; here, MBBtoMoveCmp is the loop preheader.
1285  //
1286  // Overview of CFG of related basic blocks
1287  // Fully redundant case Partially redundant case
1288  // -------- ---------------- --------
1289  // | MBB1 | (w/ 2 succ) | MBBtoMoveCmp | | MBB1 | (w/ 2 succ)
1290  // -------- ---------------- --------
1291  // | \ (w/ 1 succ) \ | \
1292  // | \ \ | \
1293  // | \ |
1294  // -------- --------
1295  // | MBB2 | (w/ 1 pred | MBB2 | (w/ 2 pred
1296  // -------- and 2 succ) -------- and 2 succ)
1297  // | \ | \
1298  // | \ | \
1299  //
1300  if (!eligibleForCompareElimination(MBB2, MBB1, MBBtoMoveCmp, MRI))
1301  continue;
1302 
1303  MachineInstr *BI1 = &*MBB1->getFirstInstrTerminator();
1304  MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
1305 
1306  MachineInstr *BI2 = &*MBB2.getFirstInstrTerminator();
1307  MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
1308  bool IsPartiallyRedundant = (MBBtoMoveCmp != nullptr);
1309 
1310  // We cannot optimize an unsupported compare opcode or
1311  // a mix of 32-bit and 64-bit comaprisons
1312  if (!isSupportedCmpOp(CMPI1->getOpcode()) ||
1313  !isSupportedCmpOp(CMPI2->getOpcode()) ||
1314  is64bitCmpOp(CMPI1->getOpcode()) != is64bitCmpOp(CMPI2->getOpcode()))
1315  continue;
1316 
1317  unsigned NewOpCode = 0;
1318  unsigned NewPredicate1 = 0, NewPredicate2 = 0;
1319  int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;
1320  bool SwapOperands = false;
1321 
1322  if (CMPI1->getOpcode() != CMPI2->getOpcode()) {
1323  // Typically, unsigned comparison is used for equality check, but
1324  // we replace it with a signed comparison if the comparison
1325  // to be merged is a signed comparison.
1326  // In other cases of opcode mismatch, we cannot optimize this.
1327 
1328  // We cannot change opcode when comparing against an immediate
1329  // if the most significant bit of the immediate is one
1330  // due to the difference in sign extension.
1331  auto CmpAgainstImmWithSignBit = [](MachineInstr *I) {
1332  if (!I->getOperand(2).isImm())
1333  return false;
1334  int16_t Imm = (int16_t)I->getOperand(2).getImm();
1335  return Imm < 0;
1336  };
1337 
1338  if (isEqOrNe(BI2) && !CmpAgainstImmWithSignBit(CMPI2) &&
1339  CMPI1->getOpcode() == getSignedCmpOpCode(CMPI2->getOpcode()))
1340  NewOpCode = CMPI1->getOpcode();
1341  else if (isEqOrNe(BI1) && !CmpAgainstImmWithSignBit(CMPI1) &&
1342  getSignedCmpOpCode(CMPI1->getOpcode()) == CMPI2->getOpcode())
1343  NewOpCode = CMPI2->getOpcode();
1344  else continue;
1345  }
1346 
1347  if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1348  // In case of comparisons between two registers, these two registers
1349  // must be same to merge two comparisons.
1350  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1351  nullptr, nullptr, MRI);
1352  unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(),
1353  nullptr, nullptr, MRI);
1354  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1355  MBB1, &MBB2, MRI);
1356  unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(),
1357  MBB1, &MBB2, MRI);
1358 
1359  if (Cmp1Operand1 == Cmp2Operand1 && Cmp1Operand2 == Cmp2Operand2) {
1360  // Same pair of registers in the same order; ready to merge as is.
1361  }
1362  else if (Cmp1Operand1 == Cmp2Operand2 && Cmp1Operand2 == Cmp2Operand1) {
1363  // Same pair of registers in different order.
1364  // We reverse the predicate to merge compare instructions.
1365  PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm();
1366  NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred);
1367  // In case of partial redundancy, we need to swap operands
1368  // in another compare instruction.
1369  SwapOperands = true;
1370  }
1371  else continue;
1372  }
1373  else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
1374  // In case of comparisons between a register and an immediate,
1375  // the operand register must be same for two compare instructions.
1376  unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1377  nullptr, nullptr, MRI);
1378  unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1379  MBB1, &MBB2, MRI);
1380  if (Cmp1Operand1 != Cmp2Operand1)
1381  continue;
1382 
1383  NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm();
1384  NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm();
1385 
1386  // If immediate are not same, we try to adjust by changing predicate;
1387  // e.g. GT imm means GE (imm+1).
1388  if (Imm1 != Imm2 && (!isEqOrNe(BI2) || !isEqOrNe(BI1))) {
1389  int Diff = Imm1 - Imm2;
1390  if (Diff < -2 || Diff > 2)
1391  continue;
1392 
1393  unsigned PredToInc1 = getPredicateToIncImm(BI1, CMPI1);
1394  unsigned PredToDec1 = getPredicateToDecImm(BI1, CMPI1);
1395  unsigned PredToInc2 = getPredicateToIncImm(BI2, CMPI2);
1396  unsigned PredToDec2 = getPredicateToDecImm(BI2, CMPI2);
1397  if (Diff == 2) {
1398  if (PredToInc2 && PredToDec1) {
1399  NewPredicate2 = PredToInc2;
1400  NewPredicate1 = PredToDec1;
1401  NewImm2++;
1402  NewImm1--;
1403  }
1404  }
1405  else if (Diff == 1) {
1406  if (PredToInc2) {
1407  NewImm2++;
1408  NewPredicate2 = PredToInc2;
1409  }
1410  else if (PredToDec1) {
1411  NewImm1--;
1412  NewPredicate1 = PredToDec1;
1413  }
1414  }
1415  else if (Diff == -1) {
1416  if (PredToDec2) {
1417  NewImm2--;
1418  NewPredicate2 = PredToDec2;
1419  }
1420  else if (PredToInc1) {
1421  NewImm1++;
1422  NewPredicate1 = PredToInc1;
1423  }
1424  }
1425  else if (Diff == -2) {
1426  if (PredToDec2 && PredToInc1) {
1427  NewPredicate2 = PredToDec2;
1428  NewPredicate1 = PredToInc1;
1429  NewImm2--;
1430  NewImm1++;
1431  }
1432  }
1433  }
1434 
1435  // We cannot merge two compares if the immediates are not same.
1436  if (NewImm2 != NewImm1)
1437  continue;
1438  }
1439 
1440  LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
1441  LLVM_DEBUG(CMPI1->dump());
1442  LLVM_DEBUG(BI1->dump());
1443  LLVM_DEBUG(CMPI2->dump());
1444  LLVM_DEBUG(BI2->dump());
1445 
1446  // We adjust opcode, predicates and immediate as we determined above.
1447  if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
1448  CMPI1->setDesc(TII->get(NewOpCode));
1449  }
1450  if (NewPredicate1) {
1451  BI1->getOperand(0).setImm(NewPredicate1);
1452  }
1453  if (NewPredicate2) {
1454  BI2->getOperand(0).setImm(NewPredicate2);
1455  }
1456  if (NewImm1 != Imm1) {
1457  CMPI1->getOperand(2).setImm(NewImm1);
1458  }
1459 
1460  if (IsPartiallyRedundant) {
1461  // We touch up the compare instruction in MBB2 and move it to
1462  // a previous BB to handle partially redundant case.
1463  if (SwapOperands) {
1464  Register Op1 = CMPI2->getOperand(1).getReg();
1465  Register Op2 = CMPI2->getOperand(2).getReg();
1466  CMPI2->getOperand(1).setReg(Op2);
1467  CMPI2->getOperand(2).setReg(Op1);
1468  }
1469  if (NewImm2 != Imm2)
1470  CMPI2->getOperand(2).setImm(NewImm2);
1471 
1472  for (int I = 1; I <= 2; I++) {
1473  if (CMPI2->getOperand(I).isReg()) {
1474  MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
1475  if (Inst->getParent() != &MBB2)
1476  continue;
1477 
1478  assert(Inst->getOpcode() == PPC::PHI &&
1479  "We cannot support if an operand comes from this BB.");
1480  unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp);
1481  CMPI2->getOperand(I).setReg(SrcReg);
1482  }
1483  }
1484  auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
1485  MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2));
1486 
1487  DebugLoc DL = CMPI2->getDebugLoc();
1488  Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
1489  BuildMI(MBB2, MBB2.begin(), DL,
1490  TII->get(PPC::PHI), NewVReg)
1491  .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1492  .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
1493  BI2->getOperand(1).setReg(NewVReg);
1494  }
1495  else {
1496  // We finally eliminate compare instruction in MBB2.
1497  BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1498  CMPI2->eraseFromParent();
1499  }
1500  BI2->getOperand(1).setIsKill(true);
1501  BI1->getOperand(1).setIsKill(false);
1502 
1503  LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
1504  LLVM_DEBUG(CMPI1->dump());
1505  LLVM_DEBUG(BI1->dump());
1506  LLVM_DEBUG(BI2->dump());
1507  if (IsPartiallyRedundant) {
1508  LLVM_DEBUG(dbgs() << "The following compare is moved into "
1509  << printMBBReference(*MBBtoMoveCmp)
1510  << " to handle partial redundancy.\n");
1511  LLVM_DEBUG(CMPI2->dump());
1512  }
1513 
1514  Simplified = true;
1515  }
1516 
1517  return Simplified;
1518 }
1519 
1520 // We miss the opportunity to emit an RLDIC when lowering jump tables
1521 // since ISEL sees only a single basic block. When selecting, the clear
1522 // and shift left will be in different blocks.
1523 bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
1524  if (MI.getOpcode() != PPC::RLDICR)
1525  return false;
1526 
1527  Register SrcReg = MI.getOperand(1).getReg();
1528  if (!Register::isVirtualRegister(SrcReg))
1529  return false;
1530 
1531  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1532  if (SrcMI->getOpcode() != PPC::RLDICL)
1533  return false;
1534 
1535  MachineOperand MOpSHSrc = SrcMI->getOperand(2);
1536  MachineOperand MOpMBSrc = SrcMI->getOperand(3);
1537  MachineOperand MOpSHMI = MI.getOperand(2);
1538  MachineOperand MOpMEMI = MI.getOperand(3);
1539  if (!(MOpSHSrc.isImm() && MOpMBSrc.isImm() && MOpSHMI.isImm() &&
1540  MOpMEMI.isImm()))
1541  return false;
1542 
1543  uint64_t SHSrc = MOpSHSrc.getImm();
1544  uint64_t MBSrc = MOpMBSrc.getImm();
1545  uint64_t SHMI = MOpSHMI.getImm();
1546  uint64_t MEMI = MOpMEMI.getImm();
1547  uint64_t NewSH = SHSrc + SHMI;
1548  uint64_t NewMB = MBSrc - SHMI;
1549  if (NewMB > 63 || NewSH > 63)
1550  return false;
1551 
1552  // The bits cleared with RLDICL are [0, MBSrc).
1553  // The bits cleared with RLDICR are (MEMI, 63].
1554  // After the sequence, the bits cleared are:
1555  // [0, MBSrc-SHMI) and (MEMI, 63).
1556  //
1557  // The bits cleared with RLDIC are [0, NewMB) and (63-NewSH, 63].
1558  if ((63 - NewSH) != MEMI)
1559  return false;
1560 
1561  LLVM_DEBUG(dbgs() << "Converting pair: ");
1562  LLVM_DEBUG(SrcMI->dump());
1563  LLVM_DEBUG(MI.dump());
1564 
1565  MI.setDesc(TII->get(PPC::RLDIC));
1566  MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1567  MI.getOperand(2).setImm(NewSH);
1568  MI.getOperand(3).setImm(NewMB);
1569  MI.getOperand(1).setIsKill(SrcMI->getOperand(1).isKill());
1570  SrcMI->getOperand(1).setIsKill(false);
1571 
1572  LLVM_DEBUG(dbgs() << "To: ");
1573  LLVM_DEBUG(MI.dump());
1574  NumRotatesCollapsed++;
1575  // If SrcReg has no non-debug use it's safe to delete its def SrcMI.
1576  if (MRI->use_nodbg_empty(SrcReg)) {
1577  assert(!SrcMI->hasImplicitDef() &&
1578  "Not expecting an implicit def with this instr.");
1579  SrcMI->eraseFromParent();
1580  }
1581  return true;
1582 }
1583 
1584 // For case in LLVM IR
1585 // entry:
1586 // %iconv = sext i32 %index to i64
1587 // br i1 undef label %true, label %false
1588 // true:
1589 // %ptr = getelementptr inbounds i32, i32* null, i64 %iconv
1590 // ...
1591 // PPCISelLowering::combineSHL fails to combine, because sext and shl are in
1592 // different BBs when conducting instruction selection. We can do a peephole
1593 // optimization to combine these two instructions into extswsli after
1594 // instruction selection.
1595 bool PPCMIPeephole::combineSEXTAndSHL(MachineInstr &MI,
1596  MachineInstr *&ToErase) {
1597  if (MI.getOpcode() != PPC::RLDICR)
1598  return false;
1599 
1600  if (!MF->getSubtarget<PPCSubtarget>().isISA3_0())
1601  return false;
1602 
1603  assert(MI.getNumOperands() == 4 && "RLDICR should have 4 operands");
1604 
1605  MachineOperand MOpSHMI = MI.getOperand(2);
1606  MachineOperand MOpMEMI = MI.getOperand(3);
1607  if (!(MOpSHMI.isImm() && MOpMEMI.isImm()))
1608  return false;
1609 
1610  uint64_t SHMI = MOpSHMI.getImm();
1611  uint64_t MEMI = MOpMEMI.getImm();
1612  if (SHMI + MEMI != 63)
1613  return false;
1614 
1615  Register SrcReg = MI.getOperand(1).getReg();
1616  if (!Register::isVirtualRegister(SrcReg))
1617  return false;
1618 
1619  MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
1620  if (SrcMI->getOpcode() != PPC::EXTSW &&
1621  SrcMI->getOpcode() != PPC::EXTSW_32_64)
1622  return false;
1623 
1624  // If the register defined by extsw has more than one use, combination is not
1625  // needed.
1626  if (!MRI->hasOneNonDBGUse(SrcReg))
1627  return false;
1628 
1629  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
1630  assert(SrcMI->getOperand(1).isReg() &&
1631  "EXTSW's second operand should be a register");
1632  if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
1633  return false;
1634 
1635  LLVM_DEBUG(dbgs() << "Combining pair: ");
1636  LLVM_DEBUG(SrcMI->dump());
1637  LLVM_DEBUG(MI.dump());
1638 
1639  MachineInstr *NewInstr =
1640  BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
1641  SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI)
1642  : TII->get(PPC::EXTSWSLI_32_64),
1643  MI.getOperand(0).getReg())
1644  .add(SrcMI->getOperand(1))
1645  .add(MOpSHMI);
1646  (void)NewInstr;
1647 
1648  LLVM_DEBUG(dbgs() << "TO: ");
1649  LLVM_DEBUG(NewInstr->dump());
1650  ++NumEXTSWAndSLDICombined;
1651  ToErase = &MI;
1652  // SrcMI, which is extsw, is of no use now, erase it.
1653  SrcMI->eraseFromParent();
1654  return true;
1655 }
1656 
1657 } // end default namespace
1658 
1659 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
1660  "PowerPC MI Peephole Optimization", false, false)
1665  "PowerPC MI Peephole Optimization", false, false)
1666 
1667 char PPCMIPeephole::ID = 0;
1668 FunctionPass*
1669 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }
1670 
i
i
Definition: README.txt:29
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
ConvertRegReg
static cl::opt< bool > ConvertRegReg("ppc-convert-rr-to-ri", cl::Hidden, cl::init(true), cl::desc("Convert eligible reg+reg instructions to reg+imm"))
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::PPC::PRED_LT
@ PRED_LT
Definition: PPCPredicates.h:27
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:197
llvm::PPC::PRED_GE
@ PRED_GE
Definition: PPCPredicates.h:30
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1023
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:303
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
PPCInstrBuilder.h
Statistic.h
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::PPCInstrInfo
Definition: PPCInstrInfo.h:191
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::PPC::getSwappedPredicate
Predicate getSwappedPredicate(Predicate Opcode)
Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions s...
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineRegisterInfo::use_instructions
iterator_range< use_instr_iterator > use_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:485
Optimization
PowerPC MI Peephole Optimization
Definition: PPCMIPeephole.cpp:1665
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::PPCFunctionInfo
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
Definition: PPCMachineFunctionInfo.h:24
EnableZExtElimination
static cl::opt< bool > EnableZExtElimination("ppc-eliminate-zeroext", cl::desc("enable elimination of zero-extensions"), cl::init(false), cl::Hidden)
initialize
static void initialize(TargetLibraryInfoImpl &TLI, const Triple &T, ArrayRef< StringLiteral > StandardNames)
Initialize the set of available library functions based on the specified target triple.
Definition: TargetLibraryInfo.cpp:116
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
llvm::PPC::PRED_GT
@ PRED_GT
Definition: PPCPredicates.h:31
PPCMCTargetDesc.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineBlockFrequencyInfo::getBlockFreq
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
Definition: MachineBlockFrequencyInfo.cpp:230
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::PPCFunctionInfo::setMustSaveTOC
void setMustSaveTOC(bool U)
Definition: PPCMachineFunctionInfo.h:189
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MachineBasicBlock::getFirstInstrTerminator
instr_iterator getFirstInstrTerminator()
Same getFirstTerminator but it ignores bundles and return an instr_iterator instead.
Definition: MachineBasicBlock.cpp:251
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:820
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineBlockFrequencyInfo
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
Definition: MachineBlockFrequencyInfo.h:33
llvm::PPCSubtarget
Definition: PPCSubtarget.h:71
P2
This might compile to this xmm1 xorps xmm0 movss xmm0 ret Now consider if the code caused xmm1 to get spilled This might produce this xmm1 movaps xmm0 movaps xmm1 movss xmm0 ret since the reload is only used by these we could fold it into the producing something like xmm1 movaps xmm0 ret saving two instructions The basic idea is that a reload from a spill if only one byte chunk is bring in zeros the one element instead of elements This can be used to simplify a variety of shuffle where the elements are fixed zeros This code generates ugly probably due to costs being off or< 4 x float > * P2
Definition: README-SSE.txt:278
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::JumpTable::Simplified
@ Simplified
Definition: TargetOptions.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::PPCSubtarget::isISA3_0
bool isISA3_0() const
Definition: PPCSubtarget.h:326
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
PPC.h
llvm::PPC::PRED_LE
@ PRED_LE
Definition: PPCPredicates.h:28
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE, "PowerPC MI Peephole Optimization", false, false) INITIALIZE_PASS_END(PPCMIPeephole
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::PPC::PRED_EQ
@ PRED_EQ
Definition: PPCPredicates.h:29
llvm::PPC::getPredicateCondition
unsigned getPredicateCondition(Predicate Opcode)
Return the condition without hint bits.
Definition: PPCPredicates.h:77
llvm::PPCSubtarget::isAIXABI
bool isAIXABI() const
Definition: PPCSubtarget.h:345
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::initializePPCMIPeepholePass
void initializePPCMIPeepholePass(PassRegistry &)
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
PPCInstrInfo.h
llvm::MachineFunction::dump
void dump() const
dump - Print the current MachineFunction to cerr, useful for debugger use.
Definition: MachineFunction.cpp:536
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1612
MachineFunctionPass.h
llvm::MachineBasicBlock::pred_iterator
std::vector< MachineBasicBlock * >::iterator pred_iterator
Definition: MachineBasicBlock.h:304
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::PPC::PRED_NE
@ PRED_NE
Definition: PPCPredicates.h:32
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::PPC::getPredicateHint
unsigned getPredicateHint(Predicate Opcode)
Return the hint bits of the predicate.
Definition: PPCPredicates.h:82
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
MachinePostDominators.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1540
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::MachineInstr::hasImplicitDef
bool hasImplicitDef() const
Returns true if the instruction has implicit definition.
Definition: MachineInstr.h:572
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
FixedPointRegToImm
static cl::opt< bool > FixedPointRegToImm("ppc-reg-to-imm-fixed-point", cl::Hidden, cl::init(true), cl::desc("Iterate to a fixed point when attempting to " "convert reg-reg instructions to reg-imm"))
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
llvm::PPCFunctionInfo::mustSaveTOC
bool mustSaveTOC() const
Definition: PPCMachineFunctionInfo.h:190
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::MachinePostDominatorTree
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Definition: MachinePostDominators.h:27
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachinePostDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachinePostDominators.h:54
llvm::createPPCMIPeepholePass
FunctionPass * createPPCMIPeepholePass()
Definition: PPCMIPeephole.cpp:1669
llvm::PPC::getPredicate
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:595
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::countLeadingZeros
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
Definition: MathExtras.h:225
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::PPCISD::EXTSWSLI
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
Definition: PPCISelLowering.h:174
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::PPCSubtarget::isUsingPCRelativeCalls
bool isUsingPCRelativeCalls() const
Definition: PPCSubtarget.cpp:245
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
PPCMachineFunctionInfo.h
llvm::PPCISD::XXPERMDI
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
Definition: PPCISelLowering.h:125
llvm::SmallVectorImpl< MachineInstr * >
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1741
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:414
DEBUG_TYPE
#define DEBUG_TYPE
Definition: PPCMIPeephole.cpp:40
EnableSExtElimination
static cl::opt< bool > EnableSExtElimination("ppc-eliminate-signext", cl::desc("enable elimination of sign-extensions"), cl::init(false), cl::Hidden)
llvm::MachineInstr::isFullCopy
bool isFullCopy() const
Definition: MachineInstr.h:1295
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
PPCPredicates.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBlockFrequencyInfo::getEntryFreq
uint64_t getEntryFreq() const
Divide a block's BlockFrequency::getFrequency() value by this value to obtain the entry block - relat...
Definition: MachineBlockFrequencyInfo.cpp:289
InitializePasses.h
llvm::MachineInstr::operands
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:618
MachineBlockFrequencyInfo.h
Debug.h
PPCTargetMachine.h
llvm::MachineRegisterInfo::setRegClass
void setRegClass(Register Reg, const TargetRegisterClass *RC)
setRegClass - Set the register class of the specified virtual register.
Definition: MachineRegisterInfo.cpp:58
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::PPCSubtarget::isELFv2ABI
bool isELFv2ABI() const
Definition: PPCSubtarget.cpp:242