79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsAMDGPU.h"
81#include "llvm/IR/IntrinsicsWebAssembly.h"
112using namespace PatternMatch;
113using namespace SwitchCG;
115#define DEBUG_TYPE "isel"
123 cl::desc(
"Insert the experimental `assertalign` node."),
128 cl::desc(
"Generate low-precision inline sequences "
129 "for some float libcalls"),
135 cl::desc(
"Set the case probability threshold for peeling the case from a "
136 "switch statement. A value greater than 100 will void this "
156 const SDValue *Parts,
unsigned NumParts,
159 std::optional<CallingConv::ID>
CC);
168 unsigned NumParts,
MVT PartVT,
EVT ValueVT,
const Value *V,
170 std::optional<CallingConv::ID>
CC = std::nullopt,
171 std::optional<ISD::NodeType> AssertOp = std::nullopt) {
175 PartVT, ValueVT,
CC))
182 assert(NumParts > 0 &&
"No parts to assemble!");
193 unsigned RoundBits = PartBits * RoundParts;
194 EVT RoundVT = RoundBits == ValueBits ?
200 if (RoundParts > 2) {
204 PartVT, HalfVT, V, InChain);
215 if (RoundParts < NumParts) {
217 unsigned OddParts = NumParts - RoundParts;
220 OddVT, V, InChain,
CC);
237 assert(ValueVT ==
EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
248 !PartVT.
isVector() &&
"Unexpected split");
260 if (PartEVT == ValueVT)
264 ValueVT.
bitsLT(PartEVT)) {
277 if (ValueVT.
bitsLT(PartEVT)) {
282 Val = DAG.
getNode(*AssertOp,
DL, PartEVT, Val,
297 llvm::Attribute::StrictFP)) {
299 DAG.
getVTList(ValueVT, MVT::Other), InChain, Val,
311 if (PartEVT == MVT::x86mmx && ValueVT.
isInteger() &&
312 ValueVT.
bitsLT(PartEVT)) {
321 const Twine &ErrMsg) {
322 const Instruction *
I = dyn_cast_or_null<Instruction>(V);
326 const char *AsmError =
", possible invalid constraint for vector type";
327 if (
const CallInst *CI = dyn_cast<CallInst>(
I))
328 if (CI->isInlineAsm())
340 const SDValue *Parts,
unsigned NumParts,
343 std::optional<CallingConv::ID> CallConv) {
345 assert(NumParts > 0 &&
"No parts to assemble!");
346 const bool IsABIRegCopy = CallConv.has_value();
355 unsigned NumIntermediates;
360 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT,
361 NumIntermediates, RegisterVT);
365 NumIntermediates, RegisterVT);
368 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
370 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
373 "Part type sizes don't match!");
377 if (NumIntermediates == NumParts) {
380 for (
unsigned i = 0; i != NumParts; ++i)
382 V, InChain, CallConv);
383 }
else if (NumParts > 0) {
386 assert(NumParts % NumIntermediates == 0 &&
387 "Must expand into a divisible number of parts!");
388 unsigned Factor = NumParts / NumIntermediates;
389 for (
unsigned i = 0; i != NumIntermediates; ++i)
391 IntermediateVT, V, InChain, CallConv);
406 DL, BuiltVectorTy, Ops);
412 if (PartEVT == ValueVT)
428 "Cannot narrow, it would be a lossy transformation");
434 if (PartEVT == ValueVT)
459 }
else if (ValueVT.
bitsLT(PartEVT)) {
468 *DAG.
getContext(), V,
"non-trivial scalar-to-vector conversion");
499 std::optional<CallingConv::ID> CallConv);
506 unsigned NumParts,
MVT PartVT,
const Value *V,
507 std::optional<CallingConv::ID> CallConv = std::nullopt,
521 unsigned OrigNumParts = NumParts;
523 "Copying to an illegal type!");
529 EVT PartEVT = PartVT;
530 if (PartEVT == ValueVT) {
531 assert(NumParts == 1 &&
"No-op copy with multiple parts!");
540 assert(NumParts == 1 &&
"Do not know what to promote to!");
551 "Unknown mismatch!");
553 Val = DAG.
getNode(ExtendKind,
DL, ValueVT, Val);
554 if (PartVT == MVT::x86mmx)
559 assert(NumParts == 1 && PartEVT != ValueVT);
565 "Unknown mismatch!");
568 if (PartVT == MVT::x86mmx)
575 "Failed to tile the value with PartVT!");
578 if (PartEVT != ValueVT) {
580 "scalar-to-vector conversion failed");
589 if (NumParts & (NumParts - 1)) {
592 "Do not know what to expand to!");
594 unsigned RoundBits = RoundParts * PartBits;
595 unsigned OddParts = NumParts - RoundParts;
604 std::reverse(Parts + RoundParts, Parts + NumParts);
606 NumParts = RoundParts;
618 for (
unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
619 for (
unsigned i = 0; i < NumParts; i += StepSize) {
620 unsigned ThisBits = StepSize * PartBits / 2;
623 SDValue &Part1 = Parts[i+StepSize/2];
630 if (ThisBits == PartBits && ThisVT != PartVT) {
638 std::reverse(Parts, Parts + OrigNumParts);
655 if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) ||
660 if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
662 "Cannot widen to illegal type");
665 }
else if (PartEVT != ValueEVT) {
680 Ops.
append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef);
691 std::optional<CallingConv::ID> CallConv) {
695 const bool IsABIRegCopy = CallConv.has_value();
698 EVT PartEVT = PartVT;
699 if (PartEVT == ValueVT) {
718 TargetLowering::TypeWidenVector) {
736 "lossy conversion of vector to scalar type");
751 unsigned NumIntermediates;
755 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates,
760 NumIntermediates, RegisterVT);
763 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
765 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
768 "Mixing scalable and fixed vectors when copying in parts");
770 std::optional<ElementCount> DestEltCnt;
780 if (ValueVT == BuiltVectorTy) {
804 for (
unsigned i = 0; i != NumIntermediates; ++i) {
819 if (NumParts == NumIntermediates) {
822 for (
unsigned i = 0; i != NumParts; ++i)
824 }
else if (NumParts > 0) {
827 assert(NumIntermediates != 0 &&
"division by zero");
828 assert(NumParts % NumIntermediates == 0 &&
829 "Must expand into a divisible number of parts!");
830 unsigned Factor = NumParts / NumIntermediates;
831 for (
unsigned i = 0; i != NumIntermediates; ++i)
838 EVT valuevt, std::optional<CallingConv::ID>
CC)
839 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
840 RegCount(1, regs.
size()), CallConv(
CC) {}
844 std::optional<CallingConv::ID>
CC) {
858 for (
unsigned i = 0; i != NumRegs; ++i)
860 RegVTs.push_back(RegisterVT);
889 for (
unsigned i = 0; i != NumRegs; ++i) {
895 *Glue =
P.getValue(2);
898 Chain =
P.getValue(1);
927 EVT FromVT(MVT::Other);
931 }
else if (NumSignBits > 1) {
939 assert(FromVT != MVT::Other);
945 RegisterVT, ValueVT, V, Chain,
CallConv);
975 NumParts, RegisterVT, V,
CallConv, ExtendKind);
981 for (
unsigned i = 0; i != NumRegs; ++i) {
993 if (NumRegs == 1 || Glue)
1004 Chain = Chains[NumRegs-1];
1010 unsigned MatchingIdx,
const SDLoc &dl,
1012 std::vector<SDValue> &Ops)
const {
1017 Flag.setMatchingOp(MatchingIdx);
1026 Flag.setRegClass(RC->
getID());
1037 "No 1:1 mapping from clobbers to regs?");
1040 for (
unsigned I = 0, E =
ValueVTs.size();
I != E; ++
I) {
1045 "If we clobbered the stack pointer, MFI should know about it.");
1054 for (
unsigned i = 0; i != NumRegs; ++i) {
1056 unsigned TheReg =
Regs[Reg++];
1067 unsigned RegCount = std::get<0>(CountAndVT);
1068 MVT RegisterVT = std::get<1>(CountAndVT);
1092 UnusedArgNodeMap.clear();
1094 PendingExports.clear();
1095 PendingConstrainedFP.clear();
1096 PendingConstrainedFPStrict.clear();
1104 DanglingDebugInfoMap.clear();
1111 if (Pending.
empty())
1117 unsigned i = 0, e = Pending.
size();
1118 for (; i != e; ++i) {
1119 assert(Pending[i].getNode()->getNumOperands() > 1);
1120 if (Pending[i].getNode()->getOperand(0) == Root)
1128 if (Pending.
size() == 1)
1147 PendingConstrainedFP.size() +
1148 PendingConstrainedFPStrict.size());
1150 PendingConstrainedFP.end());
1151 PendingLoads.append(PendingConstrainedFPStrict.begin(),
1152 PendingConstrainedFPStrict.end());
1153 PendingConstrainedFP.clear();
1154 PendingConstrainedFPStrict.clear();
1161 PendingExports.append(PendingConstrainedFPStrict.begin(),
1162 PendingConstrainedFPStrict.end());
1163 PendingConstrainedFPStrict.clear();
1164 return updateRoot(PendingExports);
1171 assert(Variable &&
"Missing variable");
1178 <<
"dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
1185 if (!
N.getNode() && isa<Argument>(
Address))
1193 auto *FINode = dyn_cast<FrameIndexSDNode>(
N.getNode());
1194 if (IsParameter && FINode) {
1197 true,
DL, SDNodeOrder);
1198 }
else if (isa<Argument>(
Address)) {
1202 FuncArgumentDbgValueKind::Declare,
N);
1206 true,
DL, SDNodeOrder);
1213 FuncArgumentDbgValueKind::Declare,
N)) {
1215 <<
" (could not emit func-arg dbg_value)\n");
1227 for (
auto It = FnVarLocs->locs_begin(&
I),
End = FnVarLocs->locs_end(&
I);
1229 auto *Var = FnVarLocs->getDILocalVariable(It->VariableID);
1231 if (It->Values.isKillLocation(It->Expr)) {
1237 It->Values.hasArgList())) {
1239 for (
Value *V : It->Values.location_ops())
1242 FnVarLocs->getDILocalVariable(It->VariableID),
1243 It->Expr, Vals.
size() > 1, It->DL, SDNodeOrder);
1259 for (
DbgRecord &DR :
I.getDbgRecordRange()) {
1261 assert(DLR->getLabel() &&
"Missing label");
1263 DAG.
getDbgLabel(DLR->getLabel(), DLR->getDebugLoc(), SDNodeOrder);
1268 if (SkipDbgVariableRecords)
1278 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DVR
1287 if (Values.
empty()) {
1296 [](
Value *V) {
return !V || isa<UndefValue>(V); })) {
1304 SDNodeOrder, IsVariadic)) {
1315 if (
I.isTerminator()) {
1316 HandlePHINodesInSuccessorBlocks(
I.getParent());
1320 if (!isa<DbgInfoIntrinsic>(
I))
1326 bool NodeInserted =
false;
1327 std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1328 MDNode *PCSectionsMD =
I.getMetadata(LLVMContext::MD_pcsections);
1330 InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1331 DAG, [&](
SDNode *) { NodeInserted =
true; });
1337 !isa<GCStatepointInst>(
I))
1342 auto It = NodeMap.find(&
I);
1343 if (It != NodeMap.end()) {
1345 }
else if (NodeInserted) {
1348 errs() <<
"warning: loosing !pcsections metadata ["
1349 <<
I.getModule()->getName() <<
"]\n";
1358void SelectionDAGBuilder::visitPHI(
const PHINode &) {
1368#define HANDLE_INST(NUM, OPCODE, CLASS) \
1369 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1370#include "llvm/IR/Instruction.def"
1382 for (
const Value *V : Values) {
1407 DanglingDebugInfoMap[Values[0]].emplace_back(Var, Expr,
DL, Order);
1412 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1413 DIVariable *DanglingVariable = DDI.getVariable();
1415 if (DanglingVariable == Variable && Expr->
fragmentsOverlap(DanglingExpr)) {
1417 << printDDI(
nullptr, DDI) <<
"\n");
1423 for (
auto &DDIMI : DanglingDebugInfoMap) {
1424 DanglingDebugInfoVector &DDIV = DDIMI.second;
1428 for (
auto &DDI : DDIV)
1429 if (isMatchingDbgValue(DDI))
1432 erase_if(DDIV, isMatchingDbgValue);
1440 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1441 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1444 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1445 for (
auto &DDI : DDIV) {
1448 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1452 "Expected inlined-at fields to agree");
1461 if (!EmitFuncArgumentDbgValue(V, Variable, Expr,
DL,
1462 FuncArgumentDbgValueKind::Value, Val)) {
1464 << printDDI(V, DDI) <<
"\n");
1471 <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to "
1472 << ValSDNodeOrder <<
"\n");
1473 SDV = getDbgValue(Val, Variable, Expr,
DL,
1474 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1479 <<
" in EmitFuncArgumentDbgValue\n");
1481 LLVM_DEBUG(
dbgs() <<
"Dropping debug info for " << printDDI(V, DDI)
1493 DanglingDebugInfo &DDI) {
1498 const Value *OrigV = V;
1502 unsigned SDOrder = DDI.getSDNodeOrder();
1506 bool StackValue =
true;
1515 while (isa<Instruction>(V)) {
1516 const Instruction &VAsInst = *cast<const Instruction>(V);
1531 if (!AdditionalValues.
empty())
1541 dbgs() <<
"Salvaged debug location info for:\n " << *Var <<
"\n"
1542 << *OrigV <<
"\nBy stripping back to:\n " << *V <<
"\n");
1550 assert(OrigV &&
"V shouldn't be null");
1555 << printDDI(OrigV, DDI) <<
"\n");
1572 unsigned Order,
bool IsVariadic) {
1577 if (visitEntryValueDbgValue(Values, Var, Expr, DbgLoc))
1582 for (
const Value *V : Values) {
1584 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1585 isa<ConstantPointerNull>(V)) {
1591 if (
auto *CE = dyn_cast<ConstantExpr>(V))
1592 if (CE->getOpcode() == Instruction::IntToPtr) {
1599 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1610 if (!
N.getNode() && isa<Argument>(V))
1611 N = UnusedArgNodeMap[V];
1615 EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc,
1616 FuncArgumentDbgValueKind::Value,
N))
1618 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
1643 bool IsParamOfFunc =
1653 unsigned Reg = VMI->second;
1657 V->getType(), std::nullopt);
1663 unsigned BitsToDescribe = 0;
1665 BitsToDescribe = *VarSize;
1667 BitsToDescribe = Fragment->SizeInBits;
1670 if (
Offset >= BitsToDescribe)
1673 unsigned RegisterSize = RegAndSize.second;
1674 unsigned FragmentSize = (
Offset + RegisterSize > BitsToDescribe)
1675 ? BitsToDescribe -
Offset
1678 Expr,
Offset, FragmentSize);
1682 Var, *FragmentExpr, RegAndSize.first,
false, DbgLoc, SDNodeOrder);
1701 SDNodeOrder, IsVariadic);
1708 for (
auto &Pair : DanglingDebugInfoMap)
1709 for (
auto &DDI : Pair.second)
1741 if (
N.getNode())
return N;
1783 if (
const Constant *
C = dyn_cast<Constant>(V)) {
1792 if (isa<ConstantPointerNull>(
C)) {
1793 unsigned AS = V->getType()->getPointerAddressSpace();
1801 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(
C))
1804 if (isa<UndefValue>(
C) && !V->getType()->isAggregateType())
1808 visit(CE->getOpcode(), *CE);
1810 assert(N1.
getNode() &&
"visit didn't populate the NodeMap!");
1814 if (isa<ConstantStruct>(
C) || isa<ConstantArray>(
C)) {
1816 for (
const Use &U :
C->operands()) {
1822 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1830 dyn_cast<ConstantDataSequential>(
C)) {
1832 for (
unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1836 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1840 if (isa<ArrayType>(CDS->getType()))
1845 if (
C->getType()->isStructTy() ||
C->getType()->isArrayTy()) {
1846 assert((isa<ConstantAggregateZero>(
C) || isa<UndefValue>(
C)) &&
1847 "Unknown struct or array constant!");
1851 unsigned NumElts = ValueVTs.
size();
1855 for (
unsigned i = 0; i != NumElts; ++i) {
1856 EVT EltVT = ValueVTs[i];
1857 if (isa<UndefValue>(
C))
1871 if (
const auto *Equiv = dyn_cast<DSOLocalEquivalent>(
C))
1872 return getValue(Equiv->getGlobalValue());
1874 if (
const auto *
NC = dyn_cast<NoCFIValue>(
C))
1877 if (VT == MVT::aarch64svcount) {
1878 assert(
C->isNullValue() &&
"Can only zero this target type!");
1883 VectorType *VecTy = cast<VectorType>(V->getType());
1889 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
1890 for (
unsigned i = 0; i != NumElements; ++i)
1896 if (isa<ConstantAggregateZero>(
C)) {
1914 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1923 if (
const Instruction *Inst = dyn_cast<Instruction>(V)) {
1927 Inst->getType(), std::nullopt);
1935 if (
const auto *BB = dyn_cast<BasicBlock>(V))
1941void SelectionDAGBuilder::visitCatchPad(
const CatchPadInst &
I) {
1950 if (IsMSVCCXX || IsCoreCLR)
1977 Value *ParentPad =
I.getCatchSwitchParentPad();
1979 if (isa<ConstantTokenNone>(ParentPad))
1982 SuccessorColor = cast<Instruction>(ParentPad)->
getParent();
1983 assert(SuccessorColor &&
"No parent funclet for catchret!");
1985 assert(SuccessorColorMBB &&
"No MBB for SuccessorColor!");
1994void SelectionDAGBuilder::visitCleanupPad(
const CleanupPadInst &CPI) {
2038 if (isa<CleanupPadInst>(Pad)) {
2040 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2041 UnwindDests.back().first->setIsEHScopeEntry();
2043 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2046 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2047 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2048 UnwindDests.back().first->setIsEHScopeEntry();
2079 assert(UnwindDests.size() <= 1 &&
2080 "There should be at most one unwind destination for wasm");
2087 if (isa<LandingPadInst>(Pad)) {
2089 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2091 }
else if (isa<CleanupPadInst>(Pad)) {
2094 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2095 UnwindDests.
back().first->setIsEHScopeEntry();
2096 UnwindDests.back().first->setIsEHFuncletEntry();
2098 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2100 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2101 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2103 if (IsMSVCCXX || IsCoreCLR)
2104 UnwindDests.back().first->setIsEHFuncletEntry();
2106 UnwindDests.back().first->setIsEHScopeEntry();
2108 NewEHPadBB = CatchSwitch->getUnwindDest();
2114 if (BPI && NewEHPadBB)
2116 EHPadBB = NewEHPadBB;
2123 auto UnwindDest =
I.getUnwindDest();
2130 for (
auto &UnwindDest : UnwindDests) {
2131 UnwindDest.first->setIsEHPad();
2132 addSuccessorWithProb(
FuncInfo.
MBB, UnwindDest.first, UnwindDest.second);
2142void SelectionDAGBuilder::visitCatchSwitch(
const CatchSwitchInst &CSI) {
2146void SelectionDAGBuilder::visitRet(
const ReturnInst &
I) {
2160 if (
I.getParent()->getTerminatingDeoptimizeCall()) {
2167 const Function *
F =
I.getParent()->getParent();
2186 unsigned NumValues = ValueVTs.
size();
2189 Align BaseAlign =
DL.getPrefTypeAlign(
I.getOperand(0)->getType());
2190 for (
unsigned i = 0; i != NumValues; ++i) {
2197 if (MemVTs[i] != ValueVTs[i])
2207 MVT::Other, Chains);
2208 }
else if (
I.getNumOperands() != 0) {
2211 unsigned NumValues = ValueVTs.
size();
2215 const Function *
F =
I.getParent()->getParent();
2218 I.getOperand(0)->getType(),
F->getCallingConv(),
2222 if (
F->getAttributes().hasRetAttr(Attribute::SExt))
2224 else if (
F->getAttributes().hasRetAttr(Attribute::ZExt))
2228 bool RetInReg =
F->getAttributes().hasRetAttr(Attribute::InReg);
2230 for (
unsigned j = 0;
j != NumValues; ++
j) {
2231 EVT VT = ValueVTs[
j];
2243 &Parts[0], NumParts, PartVT, &
I,
CC, ExtendKind);
2250 if (
I.getOperand(0)->getType()->isPointerTy()) {
2252 Flags.setPointerAddrSpace(
2253 cast<PointerType>(
I.getOperand(0)->getType())->getAddressSpace());
2256 if (NeedsRegBlock) {
2257 Flags.setInConsecutiveRegs();
2258 if (j == NumValues - 1)
2259 Flags.setInConsecutiveRegsLast();
2268 for (
unsigned i = 0; i < NumParts; ++i) {
2270 Parts[i].getValueType().getSimpleVT(),
2281 const Function *
F =
I.getParent()->getParent();
2283 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
2286 Flags.setSwiftError();
2305 "LowerReturn didn't return a valid chain!");
2316 if (V->getType()->isEmptyTy())
2321 assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2322 "Unused value assigned virtual registers!");
2332 if (!isa<Instruction>(V) && !isa<Argument>(V))
return;
2345 if (
const Instruction *VI = dyn_cast<Instruction>(V)) {
2347 if (VI->getParent() == FromBB)
2356 if (isa<Argument>(V)) {
2373 const BasicBlock *SrcBB = Src->getBasicBlock();
2374 const BasicBlock *DstBB = Dst->getBasicBlock();
2378 auto SuccSize = std::max<uint32_t>(
succ_size(SrcBB), 1);
2388 Src->addSuccessorWithoutProb(Dst);
2391 Prob = getEdgeProbability(Src, Dst);
2392 Src->addSuccessor(Dst, Prob);
2398 return I->getParent() == BB;
2418 if (
const CmpInst *BOp = dyn_cast<CmpInst>(
Cond)) {
2422 if (CurBB == SwitchBB ||
2428 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2433 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2439 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1),
nullptr,
2441 SL->SwitchCases.push_back(CB);
2450 SL->SwitchCases.push_back(CB);
2458 unsigned Depth = 0) {
2463 auto *
I = dyn_cast<Instruction>(V);
2467 if (Necessary !=
nullptr) {
2470 if (Necessary->contains(
I))
2478 for (
unsigned OpIdx = 0, E =
I->getNumOperands(); OpIdx < E; ++OpIdx)
2489 if (
I.getNumSuccessors() != 2)
2492 if (!
I.isConditional())
2504 if (BPI !=
nullptr) {
2510 std::optional<bool> Likely;
2513 else if (BPI->
isEdgeHot(
I.getParent(), IfFalse))
2517 if (Opc == (*Likely ? Instruction::And : Instruction::Or))
2529 if (CostThresh <= 0)
2543 if (
const auto *RhsI = dyn_cast<Instruction>(Rhs))
2554 Value *BrCond =
I.getCondition();
2555 auto ShouldCountInsn = [&RhsDeps, &BrCond](
const Instruction *Ins) {
2556 for (
const auto *U : Ins->users()) {
2558 if (
auto *UIns = dyn_cast<Instruction>(U))
2559 if (UIns != BrCond && !RhsDeps.
contains(UIns))
2572 for (
unsigned PruneIters = 0; PruneIters < MaxPruneIters; ++PruneIters) {
2574 for (
const auto &InsPair : RhsDeps) {
2575 if (!ShouldCountInsn(InsPair.first)) {
2576 ToDrop = InsPair.first;
2580 if (ToDrop ==
nullptr)
2582 RhsDeps.erase(ToDrop);
2585 for (
const auto &InsPair : RhsDeps) {
2593 if (CostOfIncluding > CostThresh)
2619 const Value *BOpOp0, *BOpOp1;
2633 if (BOpc == Instruction::And)
2634 BOpc = Instruction::Or;
2635 else if (BOpc == Instruction::Or)
2636 BOpc = Instruction::And;
2642 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->
hasOneUse();
2647 TProb, FProb, InvertCond);
2657 if (Opc == Instruction::Or) {
2678 auto NewTrueProb = TProb / 2;
2679 auto NewFalseProb = TProb / 2 + FProb;
2682 NewFalseProb, InvertCond);
2689 Probs[1], InvertCond);
2691 assert(Opc == Instruction::And &&
"Unknown merge op!");
2711 auto NewTrueProb = TProb + FProb / 2;
2712 auto NewFalseProb = FProb / 2;
2715 NewFalseProb, InvertCond);
2722 Probs[1], InvertCond);
2731 if (Cases.size() != 2)
return true;
2735 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2736 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2737 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2738 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2744 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2745 Cases[0].
CC == Cases[1].
CC &&
2746 isa<Constant>(Cases[0].CmpRHS) &&
2747 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2748 if (Cases[0].
CC ==
ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2750 if (Cases[0].
CC ==
ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2757void SelectionDAGBuilder::visitBr(
const BranchInst &
I) {
2763 if (
I.isUnconditional()) {
2769 if (Succ0MBB != NextBlock(BrMBB) ||
2782 const Value *CondVal =
I.getCondition();
2802 const Instruction *BOp = dyn_cast<Instruction>(CondVal);
2804 BOp->
hasOneUse() && !
I.hasMetadata(LLVMContext::MD_unpredictable)) {
2806 const Value *BOp0, *BOp1;
2809 Opcode = Instruction::And;
2811 Opcode = Instruction::Or;
2819 Opcode, BOp0, BOp1))) {
2821 getEdgeProbability(BrMBB, Succ0MBB),
2822 getEdgeProbability(BrMBB, Succ1MBB),
2827 assert(
SL->SwitchCases[0].ThisBB == BrMBB &&
"Unexpected lowering!");
2831 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i) {
2838 SL->SwitchCases.erase(
SL->SwitchCases.begin());
2844 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i)
2847 SL->SwitchCases.clear();
2853 nullptr, Succ0MBB, Succ1MBB, BrMBB,
getCurSDLoc());
2872 if (CB.
TrueBB != NextBlock(SwitchBB)) {
2914 if (cast<ConstantInt>(CB.
CmpLHS)->isMinValue(
true)) {
2935 if (CB.
TrueBB == NextBlock(SwitchBB)) {
2959 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2960 assert(JT.Reg != -1U &&
"Should lower JT Header first!");
2974 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2975 const SDLoc &dl = *JT.SL;
2991 unsigned JumpTableReg =
2994 JumpTableReg, SwitchOp);
2995 JT.Reg = JumpTableReg;
3007 MVT::Other, CopyTo, CMP,
3011 if (JT.MBB != NextBlock(SwitchBB))
3018 if (JT.MBB != NextBlock(SwitchBB))
3046 if (PtrTy != PtrMemTy)
3094 Entry.Node = GuardVal;
3096 if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg))
3097 Entry.IsInReg =
true;
3098 Args.push_back(Entry);
3104 getValue(GuardCheckFn), std::move(Args));
3106 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
3120 Guard =
DAG.
getLoad(PtrMemTy, dl, Chain, GuardPtr,
3157 TLI.
makeLibCall(
DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
3188 bool UsePtrType =
false;
3192 for (
unsigned i = 0, e =
B.Cases.size(); i != e; ++i)
3212 if (!
B.FallthroughUnreachable)
3213 addSuccessorWithProb(SwitchBB,
B.Default,
B.DefaultProb);
3214 addSuccessorWithProb(SwitchBB,
MBB,
B.Prob);
3218 if (!
B.FallthroughUnreachable) {
3231 if (
MBB != NextBlock(SwitchBB))
3250 if (PopCount == 1) {
3257 }
else if (PopCount == BB.
Range) {
3276 addSuccessorWithProb(SwitchBB,
B.TargetBB,
B.ExtraProb);
3278 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
3289 if (NextMBB != NextBlock(SwitchBB))
3296void SelectionDAGBuilder::visitInvoke(
const InvokeInst &
I) {
3307 assert(!
I.hasOperandBundlesOtherThan(
3308 {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3309 LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3310 LLVMContext::OB_cfguardtarget,
3311 LLVMContext::OB_clang_arc_attachedcall}) &&
3312 "Cannot lower invokes with arbitrary operand bundles yet!");
3314 const Value *Callee(
I.getCalledOperand());
3315 const Function *Fn = dyn_cast<Function>(Callee);
3316 if (isa<InlineAsm>(Callee))
3317 visitInlineAsm(
I, EHPadBB);
3322 case Intrinsic::donothing:
3324 case Intrinsic::seh_try_begin:
3325 case Intrinsic::seh_scope_begin:
3326 case Intrinsic::seh_try_end:
3327 case Intrinsic::seh_scope_end:
3333 case Intrinsic::experimental_patchpoint_void:
3334 case Intrinsic::experimental_patchpoint:
3335 visitPatchpoint(
I, EHPadBB);
3337 case Intrinsic::experimental_gc_statepoint:
3340 case Intrinsic::wasm_rethrow: {
3369 if (!isa<GCStatepointInst>(
I)) {
3381 addSuccessorWithProb(InvokeMBB, Return);
3382 for (
auto &UnwindDest : UnwindDests) {
3383 UnwindDest.first->setIsEHPad();
3384 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
3393void SelectionDAGBuilder::visitCallBr(
const CallBrInst &
I) {
3398 assert(!
I.hasOperandBundlesOtherThan(
3399 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
3400 "Cannot lower callbrs with arbitrary operand bundles yet!");
3402 assert(
I.isInlineAsm() &&
"Only know how to handle inlineasm callbr");
3408 Dests.
insert(
I.getDefaultDest());
3413 for (
unsigned i = 0, e =
I.getNumIndirectDests(); i < e; ++i) {
3416 Target->setIsInlineAsmBrIndirectTarget();
3417 Target->setMachineBlockAddressTaken();
3418 Target->setLabelMustBeEmitted();
3420 if (Dests.
insert(Dest).second)
3431void SelectionDAGBuilder::visitResume(
const ResumeInst &RI) {
3432 llvm_unreachable(
"SelectionDAGBuilder shouldn't visit resume instructions!");
3435void SelectionDAGBuilder::visitLandingPad(
const LandingPadInst &LP) {
3437 "Call to landingpad not in landing pad!");
3457 assert(ValueVTs.
size() == 2 &&
"Only two-valued landingpads are supported");
3487 if (JTB.first.HeaderBB ==
First)
3488 JTB.first.HeaderBB =
Last;
3501 for (
unsigned i = 0, e =
I.getNumSuccessors(); i != e; ++i) {
3503 bool Inserted =
Done.insert(BB).second;
3508 addSuccessorWithProb(IndirectBrMBB, Succ);
3523 if (
const CallInst *Call = dyn_cast_or_null<CallInst>(
I.getPrevNode())) {
3524 if (
Call->doesNotReturn())
3532void SelectionDAGBuilder::visitUnary(
const User &
I,
unsigned Opcode) {
3534 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3535 Flags.copyFMF(*FPOp);
3543void SelectionDAGBuilder::visitBinary(
const User &
I,
unsigned Opcode) {
3545 if (
auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&
I)) {
3546 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3547 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3549 if (
auto *ExactOp = dyn_cast<PossiblyExactOperator>(&
I))
3550 Flags.setExact(ExactOp->isExact());
3551 if (
auto *DisjointOp = dyn_cast<PossiblyDisjointInst>(&
I))
3552 Flags.setDisjoint(DisjointOp->isDisjoint());
3553 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3554 Flags.copyFMF(*FPOp);
3563void SelectionDAGBuilder::visitShift(
const User &
I,
unsigned Opcode) {
3572 if (!
I.getType()->isVectorTy() && Op2.
getValueType() != ShiftTy) {
3574 "Unexpected shift type");
3585 dyn_cast<const OverflowingBinaryOperator>(&
I)) {
3586 nuw = OFBinOp->hasNoUnsignedWrap();
3587 nsw = OFBinOp->hasNoSignedWrap();
3590 dyn_cast<const PossiblyExactOperator>(&
I))
3591 exact = ExactOp->isExact();
3594 Flags.setExact(exact);
3595 Flags.setNoSignedWrap(nsw);
3596 Flags.setNoUnsignedWrap(nuw);
3602void SelectionDAGBuilder::visitSDiv(
const User &
I) {
3607 Flags.setExact(isa<PossiblyExactOperator>(&
I) &&
3608 cast<PossiblyExactOperator>(&
I)->isExact());
3613void SelectionDAGBuilder::visitICmp(
const User &
I) {
3615 if (
const ICmpInst *IC = dyn_cast<ICmpInst>(&
I))
3616 predicate = IC->getPredicate();
3617 else if (
const ConstantExpr *IC = dyn_cast<ConstantExpr>(&
I))
3640void SelectionDAGBuilder::visitFCmp(
const User &
I) {
3642 if (
const FCmpInst *FC = dyn_cast<FCmpInst>(&
I))
3643 predicate =
FC->getPredicate();
3644 else if (
const ConstantExpr *FC = dyn_cast<ConstantExpr>(&
I))
3650 auto *FPMO = cast<FPMathOperator>(&
I);
3655 Flags.copyFMF(*FPMO);
3667 return isa<SelectInst>(V);
3671void SelectionDAGBuilder::visitSelect(
const User &
I) {
3675 unsigned NumValues = ValueVTs.
size();
3676 if (NumValues == 0)
return;
3686 bool IsUnaryAbs =
false;
3687 bool Negate =
false;
3690 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3691 Flags.copyFMF(*FPOp);
3693 Flags.setUnpredictable(
3694 cast<SelectInst>(
I).getMetadata(LLVMContext::MD_unpredictable));
3698 EVT VT = ValueVTs[0];
3710 bool UseScalarMinMax = VT.
isVector() &&
3719 switch (SPR.Flavor) {
3725 switch (SPR.NaNBehavior) {
3738 switch (SPR.NaNBehavior) {
3782 for (
unsigned i = 0; i != NumValues; ++i) {
3791 for (
unsigned i = 0; i != NumValues; ++i) {
3805void SelectionDAGBuilder::visitTrunc(
const User &
I) {
3813void SelectionDAGBuilder::visitZExt(
const User &
I) {
3821 if (
auto *PNI = dyn_cast<PossiblyNonNegInst>(&
I))
3822 Flags.setNonNeg(PNI->hasNonNeg());
3827 if (
Flags.hasNonNeg() &&
3836void SelectionDAGBuilder::visitSExt(
const User &
I) {
3845void SelectionDAGBuilder::visitFPTrunc(
const User &
I) {
3856void SelectionDAGBuilder::visitFPExt(
const User &
I) {
3864void SelectionDAGBuilder::visitFPToUI(
const User &
I) {
3872void SelectionDAGBuilder::visitFPToSI(
const User &
I) {
3880void SelectionDAGBuilder::visitUIToFP(
const User &
I) {
3888void SelectionDAGBuilder::visitSIToFP(
const User &
I) {
3896void SelectionDAGBuilder::visitPtrToInt(
const User &
I) {
3910void SelectionDAGBuilder::visitIntToPtr(
const User &
I) {
3922void SelectionDAGBuilder::visitBitCast(
const User &
I) {
3930 if (DestVT !=
N.getValueType())
3937 else if(
ConstantInt *
C = dyn_cast<ConstantInt>(
I.getOperand(0)))
3944void SelectionDAGBuilder::visitAddrSpaceCast(
const User &
I) {
3946 const Value *SV =
I.getOperand(0);
3951 unsigned DestAS =
I.getType()->getPointerAddressSpace();
3959void SelectionDAGBuilder::visitInsertElement(
const User &
I) {
3967 InVec, InVal, InIdx));
3970void SelectionDAGBuilder::visitExtractElement(
const User &
I) {
3980void SelectionDAGBuilder::visitShuffleVector(
const User &
I) {
3984 if (
auto *SVI = dyn_cast<ShuffleVectorInst>(&
I))
3985 Mask = SVI->getShuffleMask();
3987 Mask = cast<ConstantExpr>(
I).getShuffleMask();
3993 if (
all_of(Mask, [](
int Elem) {
return Elem == 0; }) &&
4009 unsigned MaskNumElts =
Mask.size();
4011 if (SrcNumElts == MaskNumElts) {
4017 if (SrcNumElts < MaskNumElts) {
4021 if (MaskNumElts % SrcNumElts == 0) {
4025 unsigned NumConcat = MaskNumElts / SrcNumElts;
4026 bool IsConcat =
true;
4028 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4034 if ((
Idx % SrcNumElts != (i % SrcNumElts)) ||
4035 (ConcatSrcs[i / SrcNumElts] >= 0 &&
4036 ConcatSrcs[i / SrcNumElts] != (
int)(
Idx / SrcNumElts))) {
4041 ConcatSrcs[i / SrcNumElts] =
Idx / SrcNumElts;
4048 for (
auto Src : ConcatSrcs) {
4061 unsigned PaddedMaskNumElts =
alignTo(MaskNumElts, SrcNumElts);
4062 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
4079 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4081 if (
Idx >= (
int)SrcNumElts)
4082 Idx -= SrcNumElts - PaddedMaskNumElts;
4090 if (MaskNumElts != PaddedMaskNumElts)
4098 if (SrcNumElts > MaskNumElts) {
4101 int StartIdx[2] = { -1, -1 };
4102 bool CanExtract =
true;
4103 for (
int Idx : Mask) {
4108 if (
Idx >= (
int)SrcNumElts) {
4117 if (NewStartIdx + MaskNumElts > SrcNumElts ||
4118 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
4122 StartIdx[Input] = NewStartIdx;
4125 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
4131 for (
unsigned Input = 0; Input < 2; ++Input) {
4132 SDValue &Src = Input == 0 ? Src1 : Src2;
4133 if (StartIdx[Input] < 0)
4143 for (
int &
Idx : MappedOps) {
4144 if (
Idx >= (
int)SrcNumElts)
4145 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
4160 for (
int Idx : Mask) {
4166 SDValue &Src =
Idx < (int)SrcNumElts ? Src1 : Src2;
4167 if (
Idx >= (
int)SrcNumElts)
Idx -= SrcNumElts;
4181 const Value *Op0 =
I.getOperand(0);
4182 const Value *Op1 =
I.getOperand(1);
4183 Type *AggTy =
I.getType();
4185 bool IntoUndef = isa<UndefValue>(Op0);
4186 bool FromUndef = isa<UndefValue>(Op1);
4196 unsigned NumAggValues = AggValueVTs.
size();
4197 unsigned NumValValues = ValValueVTs.
size();
4201 if (!NumAggValues) {
4209 for (; i != LinearIndex; ++i)
4210 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4215 for (; i != LinearIndex + NumValValues; ++i)
4216 Values[i] = FromUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4220 for (; i != NumAggValues; ++i)
4221 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4230 const Value *Op0 =
I.getOperand(0);
4232 Type *ValTy =
I.getType();
4233 bool OutOfUndef = isa<UndefValue>(Op0);
4241 unsigned NumValValues = ValValueVTs.
size();
4244 if (!NumValValues) {
4253 for (
unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
4254 Values[i - LinearIndex] =
4263void SelectionDAGBuilder::visitGetElementPtr(
const User &
I) {
4264 Value *Op0 =
I.getOperand(0);
4274 bool IsVectorGEP =
I.getType()->isVectorTy();
4276 IsVectorGEP ? cast<VectorType>(
I.getType())->getElementCount()
4279 if (IsVectorGEP && !
N.getValueType().isVector()) {
4287 const Value *
Idx = GTI.getOperand();
4288 if (
StructType *StTy = GTI.getStructTypeOrNull()) {
4289 unsigned Field = cast<Constant>(
Idx)->getUniqueInteger().getZExtValue();
4298 if (int64_t(
Offset) >= 0 && cast<GEPOperator>(
I).isInBounds())
4299 Flags.setNoUnsignedWrap(
true);
4315 bool ElementScalable = ElementSize.
isScalable();
4319 const auto *
C = dyn_cast<Constant>(
Idx);
4320 if (
C && isa<VectorType>(
C->getType()))
4321 C =
C->getSplatValue();
4323 const auto *CI = dyn_cast_or_null<ConstantInt>(
C);
4324 if (CI && CI->isZero())
4326 if (CI && !ElementScalable) {
4340 Flags.setNoUnsignedWrap(
true);
4353 VectorElementCount);
4361 if (ElementScalable) {
4362 EVT VScaleTy =
N.getValueType().getScalarType();
4372 if (ElementMul != 1) {
4373 if (ElementMul.isPowerOf2()) {
4374 unsigned Amt = ElementMul.logBase2();
4376 N.getValueType(), IdxN,
4382 N.getValueType(), IdxN, Scale);
4388 N.getValueType(),
N, IdxN);
4399 if (PtrMemTy != PtrTy && !cast<GEPOperator>(
I).isInBounds())
4405void SelectionDAGBuilder::visitAlloca(
const AllocaInst &
I) {
4412 Type *Ty =
I.getAllocatedType();
4416 MaybeAlign Alignment = std::max(
DL.getPrefTypeAlign(Ty),
I.getAlign());
4440 if (*Alignment <= StackAlign)
4441 Alignment = std::nullopt;
4448 Flags.setNoUnsignedWrap(
true);
4458 DAG.
getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
4474 if (!
I.hasMetadata(LLVMContext::MD_noundef))
4476 return I.getMetadata(LLVMContext::MD_range);
4479void SelectionDAGBuilder::visitLoad(
const LoadInst &
I) {
4481 return visitAtomicLoad(
I);
4484 const Value *SV =
I.getOperand(0);
4488 if (
const Argument *Arg = dyn_cast<Argument>(SV)) {
4489 if (Arg->hasSwiftErrorAttr())
4490 return visitLoadFromSwiftError(
I);
4493 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
4494 if (Alloca->isSwiftError())
4495 return visitLoadFromSwiftError(
I);
4501 Type *Ty =
I.getType();
4505 unsigned NumValues = ValueVTs.
size();
4509 Align Alignment =
I.getAlign();
4512 bool isVolatile =
I.isVolatile();
4517 bool ConstantMemory =
false;
4530 ConstantMemory =
true;
4545 unsigned ChainI = 0;
4546 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4569 MMOFlags, AAInfo, Ranges);
4570 Chains[ChainI] =
L.getValue(1);
4572 if (MemVTs[i] != ValueVTs[i])
4578 if (!ConstantMemory) {
4591void SelectionDAGBuilder::visitStoreToSwiftError(
const StoreInst &
I) {
4593 "call visitStoreToSwiftError when backend supports swifterror");
4597 const Value *SrcV =
I.getOperand(0);
4599 SrcV->
getType(), ValueVTs, &Offsets, 0);
4600 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4601 "expect a single EVT for swifterror");
4610 SDValue(Src.getNode(), Src.getResNo()));
4614void SelectionDAGBuilder::visitLoadFromSwiftError(
const LoadInst &
I) {
4616 "call visitLoadFromSwiftError when backend supports swifterror");
4619 !
I.hasMetadata(LLVMContext::MD_nontemporal) &&
4620 !
I.hasMetadata(LLVMContext::MD_invariant_load) &&
4621 "Support volatile, non temporal, invariant for load_from_swift_error");
4623 const Value *SV =
I.getOperand(0);
4624 Type *Ty =
I.getType();
4629 I.getAAMetadata()))) &&
4630 "load_from_swift_error should not be constant memory");
4635 ValueVTs, &Offsets, 0);
4636 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4637 "expect a single EVT for swifterror");
4647void SelectionDAGBuilder::visitStore(
const StoreInst &
I) {
4649 return visitAtomicStore(
I);
4651 const Value *SrcV =
I.getOperand(0);
4652 const Value *PtrV =
I.getOperand(1);
4658 if (
const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4659 if (Arg->hasSwiftErrorAttr())
4660 return visitStoreToSwiftError(
I);
4663 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4664 if (Alloca->isSwiftError())
4665 return visitStoreToSwiftError(
I);
4672 SrcV->
getType(), ValueVTs, &MemVTs, &Offsets);
4673 unsigned NumValues = ValueVTs.
size();
4686 Align Alignment =
I.getAlign();
4691 unsigned ChainI = 0;
4692 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4709 if (MemVTs[i] != ValueVTs[i])
4712 DAG.
getStore(Root, dl, Val,
Add, PtrInfo, Alignment, MMOFlags, AAInfo);
4713 Chains[ChainI] = St;
4722void SelectionDAGBuilder::visitMaskedStore(
const CallInst &
I,
4723 bool IsCompressing) {
4729 Src0 =
I.getArgOperand(0);
4730 Ptr =
I.getArgOperand(1);
4731 Alignment = cast<ConstantInt>(
I.getArgOperand(2))->getAlignValue();
4732 Mask =
I.getArgOperand(3);
4737 Src0 =
I.getArgOperand(0);
4738 Ptr =
I.getArgOperand(1);
4739 Mask =
I.getArgOperand(2);
4740 Alignment =
I.getParamAlign(1).valueOrOne();
4743 Value *PtrOperand, *MaskOperand, *Src0Operand;
4746 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4748 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4790 assert(
Ptr->getType()->isVectorTy() &&
"Unexpected pointer type");
4793 if (
auto *
C = dyn_cast<Constant>(
Ptr)) {
4794 C =
C->getSplatValue();
4800 ElementCount NumElts = cast<VectorType>(
Ptr->getType())->getElementCount();
4809 if (!
GEP ||
GEP->getParent() != CurBB)
4812 if (
GEP->getNumOperands() != 2)
4815 const Value *BasePtr =
GEP->getPointerOperand();
4816 const Value *IndexVal =
GEP->getOperand(
GEP->getNumOperands() - 1);
4822 TypeSize ScaleVal =
DL.getTypeAllocSize(
GEP->getResultElementType());
4827 if (ScaleVal != 1 &&
4840void SelectionDAGBuilder::visitMaskedScatter(
const CallInst &
I) {
4848 Align Alignment = cast<ConstantInt>(
I.getArgOperand(2))
4849 ->getMaybeAlignValue()
4860 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
4880 Ops, MMO, IndexType,
false);
4885void SelectionDAGBuilder::visitMaskedLoad(
const CallInst &
I,
bool IsExpanding) {
4891 Ptr =
I.getArgOperand(0);
4892 Alignment = cast<ConstantInt>(
I.getArgOperand(1))->getAlignValue();
4893 Mask =
I.getArgOperand(2);
4894 Src0 =
I.getArgOperand(3);
4899 Ptr =
I.getArgOperand(0);
4900 Alignment =
I.getParamAlign(0).valueOrOne();
4901 Mask =
I.getArgOperand(1);
4902 Src0 =
I.getArgOperand(2);
4905 Value *PtrOperand, *MaskOperand, *Src0Operand;
4908 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4910 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4939void SelectionDAGBuilder::visitMaskedGather(
const CallInst &
I) {
4949 Align Alignment = cast<ConstantInt>(
I.getArgOperand(1))
4950 ->getMaybeAlignValue()
4962 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
5008 AAMDNodes(),
nullptr, SSID, SuccessOrdering, FailureOrdering);
5011 dl, MemVT, VTs, InChain,
5022void SelectionDAGBuilder::visitAtomicRMW(
const AtomicRMWInst &
I) {
5025 switch (
I.getOperation()) {
5075void SelectionDAGBuilder::visitFence(
const FenceInst &
I) {
5089void SelectionDAGBuilder::visitAtomicLoad(
const LoadInst &
I) {
5109 nullptr, SSID, Order);
5125void SelectionDAGBuilder::visitAtomicStore(
const StoreInst &
I) {
5147 nullptr, SSID, Ordering);
5163void SelectionDAGBuilder::visitTargetIntrinsic(
const CallInst &
I,
5164 unsigned Intrinsic) {
5169 bool HasChain = !
F->doesNotAccessMemory();
5170 bool OnlyLoad = HasChain &&
F->onlyReadsMemory();
5197 for (
unsigned i = 0, e =
I.arg_size(); i != e; ++i) {
5198 const Value *Arg =
I.getArgOperand(i);
5199 if (!
I.paramHasAttr(i, Attribute::ImmArg)) {
5206 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
5207 assert(CI->getBitWidth() <= 64 &&
5208 "large intrinsic immediates not handled");
5226 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
5227 Flags.copyFMF(*FPMO);
5234 auto *Token = Bundle->Inputs[0].get();
5236 assert(Ops.
back().getValueType() != MVT::Glue &&
5237 "Did not expected another glue node here.");
5245 if (IsTgtIntrinsic) {
5253 else if (
Info.fallbackAddressSpace)
5257 Info.size,
I.getAAMetadata());
5258 }
else if (!HasChain) {
5260 }
else if (!
I.getType()->isVoidTy()) {
5274 if (!
I.getType()->isVoidTy()) {
5275 if (!isa<VectorType>(
I.getType()))
5347 SDValue TwoToFractionalPartOfX;
5424 if (
Op.getValueType() == MVT::f32 &&
5448 if (
Op.getValueType() == MVT::f32 &&
5547 if (
Op.getValueType() == MVT::f32 &&
5631 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5644 if (
Op.getValueType() == MVT::f32 &&
5721 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5732 if (
Op.getValueType() == MVT::f32 &&
5745 bool IsExp10 =
false;
5746 if (
LHS.getValueType() == MVT::f32 &&
RHS.getValueType() == MVT::f32 &&
5750 IsExp10 = LHSC->isExactlyValue(Ten);
5777 unsigned Val = RHSC->getSExtValue();
5806 CurSquare, CurSquare);
5811 if (RHSC->getSExtValue() < 0)
5825 EVT VT =
LHS.getValueType();
5848 if ((ScaleInt > 0 || (Saturating &&
Signed)) &&
5852 Opcode, VT, ScaleInt);
5887 switch (
N.getOpcode()) {
5890 Regs.emplace_back(cast<RegisterSDNode>(
Op)->
getReg(),
5891 Op.getValueType().getSizeInBits());
5916bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5919 const Argument *Arg = dyn_cast<Argument>(V);
5933 auto &Inst =
TII->get(TargetOpcode::DBG_INSTR_REF);
5940 auto *NewDIExpr = FragExpr;
5947 return BuildMI(MF,
DL, Inst,
false, MOs, Variable, NewDIExpr);
5950 auto &Inst =
TII->get(TargetOpcode::DBG_VALUE);
5951 return BuildMI(MF,
DL, Inst, Indirect, Reg, Variable, FragExpr);
5955 if (Kind == FuncArgumentDbgValueKind::Value) {
5960 if (!IsInEntryBlock)
5976 bool VariableIsFunctionInputArg = Variable->
isParameter() &&
5977 !
DL->getInlinedAt();
5979 if (!IsInPrologue && !VariableIsFunctionInputArg)
6013 if (VariableIsFunctionInputArg) {
6018 return !NodeMap[
V].getNode();
6023 bool IsIndirect =
false;
6024 std::optional<MachineOperand>
Op;
6027 if (FI != std::numeric_limits<int>::max())
6031 if (!
Op &&
N.getNode()) {
6034 if (ArgRegsAndSizes.
size() == 1)
6035 Reg = ArgRegsAndSizes.
front().first;
6037 if (Reg &&
Reg.isVirtual()) {
6045 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6049 if (!
Op &&
N.getNode()) {
6054 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6063 for (
const auto &RegAndSize : SplitRegs) {
6067 int RegFragmentSizeInBits = RegAndSize.second;
6069 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
6072 if (
Offset >= ExprFragmentSizeInBits)
6076 if (
Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
6077 RegFragmentSizeInBits = ExprFragmentSizeInBits -
Offset;
6082 Expr,
Offset, RegFragmentSizeInBits);
6083 Offset += RegAndSize.second;
6086 if (!FragmentExpr) {
6093 MakeVRegDbgValue(RegAndSize.first, *FragmentExpr,
6094 Kind != FuncArgumentDbgValueKind::Value);
6105 V->getType(), std::nullopt);
6106 if (RFV.occupiesMultipleRegs()) {
6107 splitMultiRegDbgValue(RFV.getRegsAndSizes());
6112 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6113 }
else if (ArgRegsAndSizes.
size() > 1) {
6116 splitMultiRegDbgValue(ArgRegsAndSizes);
6125 "Expected inlined-at fields to agree");
6129 NewMI = MakeVRegDbgValue(
Op->getReg(), Expr, IsIndirect);
6131 NewMI =
BuildMI(MF,
DL,
TII->get(TargetOpcode::DBG_VALUE),
true, *
Op,
6144 unsigned DbgSDNodeOrder) {
6145 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
6157 false, dl, DbgSDNodeOrder);
6160 false, dl, DbgSDNodeOrder);
6164 switch (Intrinsic) {
6165 case Intrinsic::smul_fix:
6167 case Intrinsic::umul_fix:
6169 case Intrinsic::smul_fix_sat:
6171 case Intrinsic::umul_fix_sat:
6173 case Intrinsic::sdiv_fix:
6175 case Intrinsic::udiv_fix:
6177 case Intrinsic::sdiv_fix_sat:
6179 case Intrinsic::udiv_fix_sat:
6186void SelectionDAGBuilder::lowerCallToExternalSymbol(
const CallInst &
I,
6187 const char *FunctionName) {
6188 assert(FunctionName &&
"FunctionName must not be nullptr");
6198 assert(cast<CallBase>(PreallocatedSetup)
6201 "expected call_preallocated_setup Value");
6202 for (
const auto *U : PreallocatedSetup->
users()) {
6203 auto *UseCall = cast<CallBase>(U);
6204 const Function *Fn = UseCall->getCalledFunction();
6205 if (!Fn || Fn->
getIntrinsicID() != Intrinsic::call_preallocated_arg) {
6215bool SelectionDAGBuilder::visitEntryValueDbgValue(
6222 const Argument *Arg = cast<Argument>(Values[0]);
6228 dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6229 "couldn't find an associated register for the Argument\n");
6232 Register ArgVReg = ArgIt->getSecond();
6235 if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
6237 Variable, Expr, PhysReg,
false , DbgLoc, SDNodeOrder);
6241 LLVM_DEBUG(
dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6242 "couldn't find a physical register\n");
6247void SelectionDAGBuilder::visitConvergenceControl(
const CallInst &
I,
6248 unsigned Intrinsic) {
6250 switch (Intrinsic) {
6251 case Intrinsic::experimental_convergence_anchor:
6254 case Intrinsic::experimental_convergence_entry:
6257 case Intrinsic::experimental_convergence_loop: {
6259 auto *Token = Bundle->Inputs[0].get();
6268void SelectionDAGBuilder::visitIntrinsicCall(
const CallInst &
I,
6269 unsigned Intrinsic) {
6276 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
6277 Flags.copyFMF(*FPOp);
6279 switch (Intrinsic) {
6282 visitTargetIntrinsic(
I, Intrinsic);
6284 case Intrinsic::vscale: {
6289 case Intrinsic::vastart: visitVAStart(
I);
return;
6290 case Intrinsic::vaend: visitVAEnd(
I);
return;
6291 case Intrinsic::vacopy: visitVACopy(
I);
return;
6292 case Intrinsic::returnaddress:
6297 case Intrinsic::addressofreturnaddress:
6302 case Intrinsic::sponentry:
6307 case Intrinsic::frameaddress:
6312 case Intrinsic::read_volatile_register:
6313 case Intrinsic::read_register: {
6317 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6325 case Intrinsic::write_register: {
6327 Value *RegValue =
I.getArgOperand(1);
6330 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6335 case Intrinsic::memcpy: {
6336 const auto &MCI = cast<MemCpyInst>(
I);
6341 Align DstAlign = MCI.getDestAlign().valueOrOne();
6342 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6343 Align Alignment = std::min(DstAlign, SrcAlign);
6344 bool isVol = MCI.isVolatile();
6350 Root, sdl, Op1, Op2, Op3, Alignment, isVol,
6353 updateDAGForMaybeTailCall(MC);
6356 case Intrinsic::memcpy_inline: {
6357 const auto &MCI = cast<MemCpyInlineInst>(
I);
6361 assert(isa<ConstantSDNode>(
Size) &&
"memcpy_inline needs constant size");
6363 Align DstAlign = MCI.getDestAlign().valueOrOne();
6364 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6365 Align Alignment = std::min(DstAlign, SrcAlign);
6366 bool isVol = MCI.isVolatile();
6374 updateDAGForMaybeTailCall(MC);
6377 case Intrinsic::memset: {
6378 const auto &MSI = cast<MemSetInst>(
I);
6383 Align Alignment = MSI.getDestAlign().valueOrOne();
6384 bool isVol = MSI.isVolatile();
6388 Root, sdl, Op1, Op2, Op3, Alignment, isVol,
false,
6390 updateDAGForMaybeTailCall(MS);
6393 case Intrinsic::memset_inline: {
6394 const auto &MSII = cast<MemSetInlineInst>(
I);
6398 assert(isa<ConstantSDNode>(
Size) &&
"memset_inline needs constant size");
6400 Align DstAlign = MSII.getDestAlign().valueOrOne();
6401 bool isVol = MSII.isVolatile();
6408 updateDAGForMaybeTailCall(MC);
6411 case Intrinsic::memmove: {
6412 const auto &MMI = cast<MemMoveInst>(
I);
6417 Align DstAlign = MMI.getDestAlign().valueOrOne();
6418 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6419 Align Alignment = std::min(DstAlign, SrcAlign);
6420 bool isVol = MMI.isVolatile();
6428 I.getAAMetadata(),
AA);
6429 updateDAGForMaybeTailCall(MM);
6432 case Intrinsic::memcpy_element_unordered_atomic: {
6438 Type *LengthTy =
MI.getLength()->getType();
6439 unsigned ElemSz =
MI.getElementSizeInBytes();
6445 updateDAGForMaybeTailCall(MC);
6448 case Intrinsic::memmove_element_unordered_atomic: {
6449 auto &
MI = cast<AtomicMemMoveInst>(
I);
6454 Type *LengthTy =
MI.getLength()->getType();
6455 unsigned ElemSz =
MI.getElementSizeInBytes();
6461 updateDAGForMaybeTailCall(MC);
6464 case Intrinsic::memset_element_unordered_atomic: {
6465 auto &
MI = cast<AtomicMemSetInst>(
I);
6470 Type *LengthTy =
MI.getLength()->getType();
6471 unsigned ElemSz =
MI.getElementSizeInBytes();
6476 updateDAGForMaybeTailCall(MC);
6479 case Intrinsic::call_preallocated_setup: {
6488 case Intrinsic::call_preallocated_arg: {
6503 case Intrinsic::dbg_declare: {
6504 const auto &DI = cast<DbgDeclareInst>(
I);
6507 if (AssignmentTrackingEnabled ||
6510 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DI <<
"\n");
6516 assert(!DI.hasArgList() &&
"Only dbg.value should currently use DIArgList");
6521 case Intrinsic::dbg_label: {
6524 assert(Label &&
"Missing label");
6531 case Intrinsic::dbg_assign: {
6533 if (AssignmentTrackingEnabled)
6539 case Intrinsic::dbg_value: {
6541 if (AssignmentTrackingEnabled)
6561 SDNodeOrder, IsVariadic))
6567 case Intrinsic::eh_typeid_for: {
6576 case Intrinsic::eh_return_i32:
6577 case Intrinsic::eh_return_i64:
6585 case Intrinsic::eh_unwind_init:
6588 case Intrinsic::eh_dwarf_cfa:
6593 case Intrinsic::eh_sjlj_callsite: {
6595 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(0));
6601 case Intrinsic::eh_sjlj_functioncontext: {
6605 cast<AllocaInst>(
I.getArgOperand(0)->stripPointerCasts());
6610 case Intrinsic::eh_sjlj_setjmp: {
6620 case Intrinsic::eh_sjlj_longjmp:
6624 case Intrinsic::eh_sjlj_setup_dispatch:
6628 case Intrinsic::masked_gather:
6629 visitMaskedGather(
I);
6631 case Intrinsic::masked_load:
6634 case Intrinsic::masked_scatter:
6635 visitMaskedScatter(
I);
6637 case Intrinsic::masked_store:
6638 visitMaskedStore(
I);
6640 case Intrinsic::masked_expandload:
6641 visitMaskedLoad(
I,
true );
6643 case Intrinsic::masked_compressstore:
6644 visitMaskedStore(
I,
true );
6646 case Intrinsic::powi:
6650 case Intrinsic::log:
6653 case Intrinsic::log2:
6657 case Intrinsic::log10:
6661 case Intrinsic::exp:
6664 case Intrinsic::exp2:
6668 case Intrinsic::pow:
6672 case Intrinsic::sqrt:
6673 case Intrinsic::fabs:
6674 case Intrinsic::sin:
6675 case Intrinsic::cos:
6676 case Intrinsic::exp10:
6677 case Intrinsic::floor:
6678 case Intrinsic::ceil:
6679 case Intrinsic::trunc:
6680 case Intrinsic::rint:
6681 case Intrinsic::nearbyint:
6682 case Intrinsic::round:
6683 case Intrinsic::roundeven:
6684 case Intrinsic::canonicalize: {
6686 switch (Intrinsic) {
6688 case Intrinsic::sqrt: Opcode =
ISD::FSQRT;
break;
6689 case Intrinsic::fabs: Opcode =
ISD::FABS;
break;
6690 case Intrinsic::sin: Opcode =
ISD::FSIN;
break;
6691 case Intrinsic::cos: Opcode =
ISD::FCOS;
break;
6692 case Intrinsic::exp10: Opcode =
ISD::FEXP10;
break;
6693 case Intrinsic::floor: Opcode =
ISD::FFLOOR;
break;
6694 case Intrinsic::ceil: Opcode =
ISD::FCEIL;
break;
6695 case Intrinsic::trunc: Opcode =
ISD::FTRUNC;
break;
6696 case Intrinsic::rint: Opcode =
ISD::FRINT;
break;
6698 case Intrinsic::round: Opcode =
ISD::FROUND;
break;
6708 case Intrinsic::lround:
6709 case Intrinsic::llround:
6710 case Intrinsic::lrint:
6711 case Intrinsic::llrint: {
6713 switch (Intrinsic) {
6715 case Intrinsic::lround: Opcode =
ISD::LROUND;
break;
6717 case Intrinsic::lrint: Opcode =
ISD::LRINT;
break;
6718 case Intrinsic::llrint: Opcode =
ISD::LLRINT;
break;
6726 case Intrinsic::minnum:
6732 case Intrinsic::maxnum:
6738 case Intrinsic::minimum:
6744 case Intrinsic::maximum:
6750 case Intrinsic::copysign:
6756 case Intrinsic::ldexp:
6762 case Intrinsic::frexp: {
6770 case Intrinsic::arithmetic_fence: {
6776 case Intrinsic::fma:
6782#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
6783 case Intrinsic::INTRINSIC:
6784#include "llvm/IR/ConstrainedOps.def"
6785 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(
I));
6787#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
6788#include "llvm/IR/VPIntrinsics.def"
6789 visitVectorPredicationIntrinsic(cast<VPIntrinsic>(
I));
6791 case Intrinsic::fptrunc_round: {
6794 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(1))->getMetadata();
6795 std::optional<RoundingMode> RoundMode =
6802 Flags.copyFMF(*cast<FPMathOperator>(&
I));
6814 case Intrinsic::fmuladd: {
6835 case Intrinsic::convert_to_fp16:
6842 case Intrinsic::convert_from_fp16:
6848 case Intrinsic::fptosi_sat: {
6855 case Intrinsic::fptoui_sat: {
6862 case Intrinsic::set_rounding:
6868 case Intrinsic::is_fpclass: {
6873 cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue());
6878 Flags.setNoFPExcept(
6879 !
F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP));
6894 case Intrinsic::get_fpenv: {
6909 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
6916 Res =
DAG.
getLoad(EnvVT, sdl, Chain, Temp, MPI);
6922 case Intrinsic::set_fpenv: {
6936 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
6939 Chain =
DAG.
getStore(Chain, sdl, Env, Temp, MPI, TempAlign,
6949 case Intrinsic::reset_fpenv:
6952 case Intrinsic::get_fpmode:
6961 case Intrinsic::set_fpmode:
6966 case Intrinsic::reset_fpmode: {
6971 case Intrinsic::pcmarker: {
6976 case Intrinsic::readcyclecounter: {
6984 case Intrinsic::readsteadycounter: {
6992 case Intrinsic::bitreverse:
6997 case Intrinsic::bswap:
7002 case Intrinsic::cttz: {
7004 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7010 case Intrinsic::ctlz: {
7012 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7018 case Intrinsic::ctpop: {
7024 case Intrinsic::fshl:
7025 case Intrinsic::fshr: {
7026 bool IsFSHL =
Intrinsic == Intrinsic::fshl;
7030 EVT VT =
X.getValueType();
7041 case Intrinsic::sadd_sat: {
7047 case Intrinsic::uadd_sat: {
7053 case Intrinsic::ssub_sat: {
7059 case Intrinsic::usub_sat: {
7065 case Intrinsic::sshl_sat: {
7071 case Intrinsic::ushl_sat: {
7077 case Intrinsic::smul_fix:
7078 case Intrinsic::umul_fix:
7079 case Intrinsic::smul_fix_sat:
7080 case Intrinsic::umul_fix_sat: {
7088 case Intrinsic::sdiv_fix:
7089 case Intrinsic::udiv_fix:
7090 case Intrinsic::sdiv_fix_sat:
7091 case Intrinsic::udiv_fix_sat: {
7096 Op1, Op2, Op3,
DAG, TLI));
7099 case Intrinsic::smax: {
7105 case Intrinsic::smin: {
7111 case Intrinsic::umax: {
7117 case Intrinsic::umin: {
7123 case Intrinsic::abs: {
7129 case Intrinsic::stacksave: {
7137 case Intrinsic::stackrestore:
7141 case Intrinsic::get_dynamic_area_offset: {
7156 case Intrinsic::stackguard: {
7177 case Intrinsic::stackprotector: {
7198 Chain, sdl, Src, FIN,
7205 case Intrinsic::objectsize:
7208 case Intrinsic::is_constant:
7211 case Intrinsic::annotation:
7212 case Intrinsic::ptr_annotation:
7213 case Intrinsic::launder_invariant_group:
7214 case Intrinsic::strip_invariant_group:
7219 case Intrinsic::assume:
7220 case Intrinsic::experimental_noalias_scope_decl:
7221 case Intrinsic::var_annotation:
7222 case Intrinsic::sideeffect:
7227 case Intrinsic::codeview_annotation: {
7232 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(0))->getMetadata();
7239 case Intrinsic::init_trampoline: {
7240 const Function *
F = cast<Function>(
I.getArgOperand(1)->stripPointerCasts());
7255 case Intrinsic::adjust_trampoline:
7260 case Intrinsic::gcroot: {
7262 "only valid in functions with gc specified, enforced by Verifier");
7264 const Value *Alloca =
I.getArgOperand(0)->stripPointerCasts();
7265 const Constant *TypeMap = cast<Constant>(
I.getArgOperand(1));
7271 case Intrinsic::gcread:
7272 case Intrinsic::gcwrite:
7274 case Intrinsic::get_rounding:
7280 case Intrinsic::expect:
7285 case Intrinsic::ubsantrap:
7286 case Intrinsic::debugtrap:
7287 case Intrinsic::trap: {
7289 I.getAttributes().getFnAttr(
"trap-func-name").getValueAsString();
7290 if (TrapFuncName.
empty()) {
7291 switch (Intrinsic) {
7292 case Intrinsic::trap:
7295 case Intrinsic::debugtrap:
7298 case Intrinsic::ubsantrap:
7302 cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue(), sdl,
7310 if (Intrinsic == Intrinsic::ubsantrap) {
7312 Args[0].Val =
I.getArgOperand(0);
7314 Args[0].Ty =
Args[0].Val->getType();
7318 CLI.setDebugLoc(sdl).setChain(
getRoot()).setLibCallee(
7329 case Intrinsic::uadd_with_overflow:
7330 case Intrinsic::sadd_with_overflow:
7331 case Intrinsic::usub_with_overflow:
7332 case Intrinsic::ssub_with_overflow:
7333 case Intrinsic::umul_with_overflow:
7334 case Intrinsic::smul_with_overflow: {
7336 switch (Intrinsic) {
7338 case Intrinsic::uadd_with_overflow:
Op =
ISD::UADDO;
break;
7339 case Intrinsic::sadd_with_overflow:
Op =
ISD::SADDO;
break;
7340 case Intrinsic::usub_with_overflow:
Op =
ISD::USUBO;
break;
7341 case Intrinsic::ssub_with_overflow:
Op =
ISD::SSUBO;
break;
7342 case Intrinsic::umul_with_overflow:
Op =
ISD::UMULO;
break;
7343 case Intrinsic::smul_with_overflow:
Op =
ISD::SMULO;
break;
7349 EVT OverflowVT = MVT::i1;
7358 case Intrinsic::prefetch: {
7360 unsigned rw = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7373 std::nullopt, Flags);
7382 case Intrinsic::lifetime_start:
7383 case Intrinsic::lifetime_end: {
7384 bool IsStart = (
Intrinsic == Intrinsic::lifetime_start);
7389 const int64_t ObjectSize =
7390 cast<ConstantInt>(
I.getArgOperand(0))->getSExtValue();
7395 for (
const Value *Alloca : Allocas) {
7396 const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca);
7399 if (!LifetimeObject)
7419 case Intrinsic::pseudoprobe: {
7420 auto Guid = cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue();
7421 auto Index = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7422 auto Attr = cast<ConstantInt>(
I.getArgOperand(2))->getZExtValue();
7427 case Intrinsic::invariant_start:
7432 case Intrinsic::invariant_end:
7435 case Intrinsic::clear_cache:
7438 lowerCallToExternalSymbol(
I, FunctionName);
7440 case Intrinsic::donothing:
7441 case Intrinsic::seh_try_begin:
7442 case Intrinsic::seh_scope_begin:
7443 case Intrinsic::seh_try_end:
7444 case Intrinsic::seh_scope_end:
7447 case Intrinsic::experimental_stackmap:
7450 case Intrinsic::experimental_patchpoint_void:
7451 case Intrinsic::experimental_patchpoint:
7454 case Intrinsic::experimental_gc_statepoint:
7457 case Intrinsic::experimental_gc_result:
7458 visitGCResult(cast<GCResultInst>(
I));
7460 case Intrinsic::experimental_gc_relocate:
7461 visitGCRelocate(cast<GCRelocateInst>(
I));
7463 case Intrinsic::instrprof_cover:
7465 case Intrinsic::instrprof_increment:
7467 case Intrinsic::instrprof_timestamp:
7469 case Intrinsic::instrprof_value_profile:
7471 case Intrinsic::instrprof_mcdc_parameters:
7473 case Intrinsic::instrprof_mcdc_tvbitmap_update:
7475 case Intrinsic::instrprof_mcdc_condbitmap_update:
7477 case Intrinsic::localescape: {
7483 for (
unsigned Idx = 0, E =
I.arg_size();
Idx < E; ++
Idx) {
7484 Value *Arg =
I.getArgOperand(
Idx)->stripPointerCasts();
7485 if (isa<ConstantPointerNull>(Arg))
7489 "can only escape static allocas");
7495 TII->get(TargetOpcode::LOCAL_ESCAPE))
7503 case Intrinsic::localrecover: {
7508 auto *Fn = cast<Function>(
I.getArgOperand(0)->stripPointerCasts());
7509 auto *
Idx = cast<ConstantInt>(
I.getArgOperand(2));
7511 unsigned(
Idx->getLimitedValue(std::numeric_limits<int>::max()));
7533 case Intrinsic::eh_exceptionpointer:
7534 case Intrinsic::eh_exceptioncode: {
7536 const auto *CPI = cast<CatchPadInst>(
I.getArgOperand(0));
7541 if (Intrinsic == Intrinsic::eh_exceptioncode)
7546 case Intrinsic::xray_customevent: {
7575 case Intrinsic::xray_typedevent: {
7602 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops);
7608 case Intrinsic::experimental_deoptimize:
7611 case Intrinsic::experimental_stepvector:
7614 case Intrinsic::vector_reduce_fadd:
7615 case Intrinsic::vector_reduce_fmul:
7616 case Intrinsic::vector_reduce_add:
7617 case Intrinsic::vector_reduce_mul:
7618 case Intrinsic::vector_reduce_and:
7619 case Intrinsic::vector_reduce_or:
7620 case Intrinsic::vector_reduce_xor:
7621 case Intrinsic::vector_reduce_smax:
7622 case Intrinsic::vector_reduce_smin:
7623 case Intrinsic::vector_reduce_umax:
7624 case Intrinsic::vector_reduce_umin:
7625 case Intrinsic::vector_reduce_fmax:
7626 case Intrinsic::vector_reduce_fmin:
7627 case Intrinsic::vector_reduce_fmaximum:
7628 case Intrinsic::vector_reduce_fminimum:
7629 visitVectorReduce(
I, Intrinsic);
7632 case Intrinsic::icall_branch_funnel: {
7641 "llvm.icall.branch.funnel operand must be a GlobalValue");
7644 struct BranchFunnelTarget {
7650 for (
unsigned Op = 1,
N =
I.arg_size();
Op !=
N;
Op += 2) {
7653 if (ElemBase !=
Base)
7655 "to the same GlobalValue");
7658 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
7661 "llvm.icall.branch.funnel operand must be a GlobalValue");
7667 [](
const BranchFunnelTarget &T1,
const BranchFunnelTarget &T2) {
7668 return T1.Offset < T2.Offset;
7671 for (
auto &
T : Targets) {
7686 case Intrinsic::wasm_landingpad_index:
7692 case Intrinsic::aarch64_settag:
7693 case Intrinsic::aarch64_settag_zero: {
7695 bool ZeroMemory =
Intrinsic == Intrinsic::aarch64_settag_zero;
7704 case Intrinsic::amdgcn_cs_chain: {
7705 assert(
I.arg_size() == 5 &&
"Additional args not supported yet");
7706 assert(cast<ConstantInt>(
I.getOperand(4))->isZero() &&
7707 "Non-zero flags not supported yet");
7723 for (
unsigned Idx : {2, 3, 1}) {
7726 Arg.
Ty =
I.getOperand(
Idx)->getType();
7728 Args.push_back(Arg);
7731 assert(Args[0].IsInReg &&
"SGPR args should be marked inreg");
7732 assert(!Args[1].IsInReg &&
"VGPR args should not be marked inreg");
7733 Args[2].IsInReg =
true;
7738 .setCallee(
CC,
RetTy, Callee, std::move(Args))
7741 .setConvergent(
I.isConvergent());
7743 std::pair<SDValue, SDValue>
Result =
7747 "Should've lowered as tail call");
7752 case Intrinsic::ptrmask: {
7756 EVT PtrVT =
Ptr.getValueType();
7758 "Pointers with different index type are not supported by SDAG");
7762 case Intrinsic::threadlocal_address: {
7766 case Intrinsic::get_active_lane_mask: {
7769 EVT ElementVT =
Index.getValueType();
7772 visitTargetIntrinsic(
I, Intrinsic);
7790 case Intrinsic::experimental_get_vector_length: {
7791 assert(cast<ConstantInt>(
I.getOperand(1))->getSExtValue() > 0 &&
7792 "Expected positive VF");
7793 unsigned VF = cast<ConstantInt>(
I.getOperand(1))->getZExtValue();
7794 bool IsScalable = cast<ConstantInt>(
I.getOperand(2))->isOne();
7800 visitTargetIntrinsic(
I, Intrinsic);
7809 if (CountVT.
bitsLT(VT)) {
7824 case Intrinsic::experimental_cttz_elts: {
7827 EVT OpVT =
Op.getValueType();
7830 visitTargetIntrinsic(
I, Intrinsic);
7850 if (!cast<ConstantSDNode>(
getValue(
I.getOperand(1)))->isZero())
7851 CR = CR.subtract(
APInt(64, 1));
7853 unsigned EltWidth =
I.getType()->getScalarSizeInBits();
7854 EltWidth = std::min(EltWidth, (
unsigned)CR.getActiveBits());
7880 case Intrinsic::vector_insert: {
7888 if (
Index.getValueType() != VectorIdxTy)
7896 case Intrinsic::vector_extract: {
7904 if (
Index.getValueType() != VectorIdxTy)
7911 case Intrinsic::experimental_vector_reverse:
7912 visitVectorReverse(
I);
7914 case Intrinsic::experimental_vector_splice:
7915 visitVectorSplice(
I);
7917 case Intrinsic::callbr_landingpad:
7918 visitCallBrLandingPad(
I);
7920 case Intrinsic::experimental_vector_interleave2:
7921 visitVectorInterleave(
I);
7923 case Intrinsic::experimental_vector_deinterleave2:
7924 visitVectorDeinterleave(
I);
7926 case Intrinsic::experimental_convergence_anchor:
7927 case Intrinsic::experimental_convergence_entry:
7928 case Intrinsic::experimental_convergence_loop:
7929 visitConvergenceControl(
I, Intrinsic);
7933void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
7969 PendingConstrainedFP.push_back(OutChain);
7975 PendingConstrainedFPStrict.push_back(OutChain);
7987 Flags.setNoFPExcept(
true);
7989 if (
auto *FPOp = dyn_cast<FPMathOperator>(&FPI))
7990 Flags.copyFMF(*FPOp);
7995#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
7996 case Intrinsic::INTRINSIC: \
7997 Opcode = ISD::STRICT_##DAGN; \
7999#include "llvm/IR/ConstrainedOps.def"
8000 case Intrinsic::experimental_constrained_fmuladd: {
8007 pushOutChain(
Mul, EB);
8028 auto *
FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI);
8038 pushOutChain(Result, EB);
8045 std::optional<unsigned> ResOPC;
8047 case Intrinsic::vp_ctlz: {
8048 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8049 ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
8052 case Intrinsic::vp_cttz: {
8053 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8054 ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
8057#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
8058 case Intrinsic::VPID: \
8059 ResOPC = ISD::VPSD; \
8061#include "llvm/IR/VPIntrinsics.def"
8066 "Inconsistency: no SDNode available for this VPIntrinsic!");
8068 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
8069 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
8071 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
8072 : ISD::VP_REDUCE_FMUL;
8078void SelectionDAGBuilder::visitVPLoad(
8104void SelectionDAGBuilder::visitVPGather(
8140 {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
8146void SelectionDAGBuilder::visitVPStore(
8150 EVT VT = OpValues[0].getValueType();
8168void SelectionDAGBuilder::visitVPScatter(
8173 EVT VT = OpValues[0].getValueType();
8203 {getMemoryRoot(), OpValues[0], Base, Index, Scale,
8204 OpValues[2], OpValues[3]},
8210void SelectionDAGBuilder::visitVPStridedLoad(
8229 OpValues[2], OpValues[3], MMO,
8237void SelectionDAGBuilder::visitVPStridedStore(
8241 EVT VT = OpValues[0].getValueType();
8253 DAG.
getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3],
8261void SelectionDAGBuilder::visitVPCmp(
const VPCmpIntrinsic &VPIntrin) {
8286 "Unexpected target EVL type");
8295void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
8302 if (
const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin))
8303 return visitVPCmp(*CmpI);
8314 "Unexpected target EVL type");
8318 for (
unsigned I = 0;
I < VPIntrin.
arg_size(); ++
I) {
8320 if (
I == EVLParamPos)
8328 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8335 visitVPLoad(VPIntrin, ValueVTs[0], OpValues);
8337 case ISD::VP_GATHER:
8338 visitVPGather(VPIntrin, ValueVTs[0], OpValues);
8340 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
8341 visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues);
8344 visitVPStore(VPIntrin, OpValues);
8346 case ISD::VP_SCATTER:
8347 visitVPScatter(VPIntrin, OpValues);
8349 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
8350 visitVPStridedStore(VPIntrin, OpValues);
8352 case ISD::VP_FMULADD: {
8353 assert(OpValues.
size() == 5 &&
"Unexpected number of operands");
8355 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8362 ISD::VP_FMUL,
DL, VTs,
8363 {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags);
8366 {
Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags);
8371 case ISD::VP_IS_FPCLASS: {
8374 auto Constant = OpValues[1]->getAsZExtVal();
8377 {OpValues[0],
Check, OpValues[2], OpValues[3]});
8381 case ISD::VP_INTTOPTR: {
8392 case ISD::VP_PTRTOINT: {
8407 case ISD::VP_CTLZ_ZERO_UNDEF:
8409 case ISD::VP_CTTZ_ZERO_UNDEF: {
8411 DAG.
getNode(Opcode,
DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
8431 if (CallSiteIndex) {
8445 assert(BeginLabel &&
"BeginLabel should've been set");
8460 assert(II &&
"II should've been set");
8471std::pair<SDValue, SDValue>
8485 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
8488 "Non-null chain expected with non-tail call!");
8489 assert((Result.second.getNode() || !Result.first.getNode()) &&
8490 "Null value expected with tail call!");
8492 if (!Result.second.getNode()) {
8499 PendingExports.clear();
8514 bool isMustTailCall,
8523 const Value *SwiftErrorVal =
nullptr;
8530 if (Caller->getFnAttribute(
"disable-tail-calls").getValueAsString() ==
8531 "true" && !isMustTailCall)
8538 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
8547 if (V->getType()->isEmptyTy())
8551 Entry.Node = ArgNode; Entry.Ty = V->getType();
8553 Entry.setAttributes(&CB,
I - CB.
arg_begin());
8565 Args.push_back(Entry);
8569 if (Entry.IsSRet && isa<Instruction>(V))
8577 Value *V = Bundle->Inputs[0];
8579 Entry.Node = ArgNode;
8580 Entry.Ty = V->getType();
8581 Entry.IsCFGuardTarget =
true;
8582 Args.push_back(Entry);
8600 "Target doesn't support calls with kcfi operand bundles.");
8601 CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
8608 auto *Token = Bundle->Inputs[0].get();
8609 ConvControlToken =
getValue(Token);
8624 std::pair<SDValue, SDValue> Result =
lowerInvokable(CLI, EHPadBB);
8626 if (Result.first.getNode()) {
8648 if (
const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
8667 bool ConstantMemory =
false;
8672 ConstantMemory =
true;
8683 if (!ConstantMemory)
8690void SelectionDAGBuilder::processIntegerCallValue(
const Instruction &
I,
8704bool SelectionDAGBuilder::visitMemCmpBCmpCall(
const CallInst &
I) {
8705 const Value *
LHS =
I.getArgOperand(0), *
RHS =
I.getArgOperand(1);
8719 if (Res.first.getNode()) {
8720 processIntegerCallValue(
I, Res.first,
true);
8734 auto hasFastLoadsAndCompare = [&](
unsigned NumBits) {
8757 switch (NumBitsToCompare) {
8769 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
8787 processIntegerCallValue(
I, Cmp,
false);
8796bool SelectionDAGBuilder::visitMemChrCall(
const CallInst &
I) {
8797 const Value *Src =
I.getArgOperand(0);
8802 std::pair<SDValue, SDValue> Res =
8806 if (Res.first.getNode()) {
8820bool SelectionDAGBuilder::visitMemPCpyCall(
const CallInst &
I) {
8828 Align Alignment = std::min(DstAlign, SrcAlign);
8842 "** memcpy should not be lowered as TailCall in mempcpy context **");
8860bool SelectionDAGBuilder::visitStrCpyCall(
const CallInst &
I,
bool isStpcpy) {
8861 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
8864 std::pair<SDValue, SDValue> Res =
8869 if (Res.first.getNode()) {
8883bool SelectionDAGBuilder::visitStrCmpCall(
const CallInst &
I) {
8884 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
8887 std::pair<SDValue, SDValue> Res =
8892 if (Res.first.getNode()) {
8893 processIntegerCallValue(
I, Res.first,
true);
8906bool SelectionDAGBuilder::visitStrLenCall(
const CallInst &
I) {
8907 const Value *Arg0 =
I.getArgOperand(0);
8910 std::pair<SDValue, SDValue> Res =
8913 if (Res.first.getNode()) {
8914 processIntegerCallValue(
I, Res.first,
false);
8927bool SelectionDAGBuilder::visitStrNLenCall(
const CallInst &
I) {
8928 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
8931 std::pair<SDValue, SDValue> Res =
8935 if (Res.first.getNode()) {
8936 processIntegerCallValue(
I, Res.first,
false);
8949bool SelectionDAGBuilder::visitUnaryFloatCall(
const CallInst &
I,
8952 if (!
I.onlyReadsMemory())
8956 Flags.copyFMF(cast<FPMathOperator>(
I));
8969bool SelectionDAGBuilder::visitBinaryFloatCall(
const CallInst &
I,
8972 if (!
I.onlyReadsMemory())
8976 Flags.copyFMF(cast<FPMathOperator>(
I));
8985void SelectionDAGBuilder::visitCall(
const CallInst &
I) {
8987 if (
I.isInlineAsm()) {
8995 if (
F->isDeclaration()) {
8997 unsigned IID =
F->getIntrinsicID();
9003 visitIntrinsicCall(
I, IID);
9012 if (!
I.isNoBuiltin() && !
I.isStrictFP() && !
F->hasLocalLinkage() &&
9018 if (visitMemCmpBCmpCall(
I))
9021 case LibFunc_copysign:
9022 case LibFunc_copysignf:
9023 case LibFunc_copysignl:
9026 if (
I.onlyReadsMemory()) {
9030 LHS.getValueType(), LHS, RHS));
9067 case LibFunc_sqrt_finite:
9068 case LibFunc_sqrtf_finite:
9069 case LibFunc_sqrtl_finite:
9074 case LibFunc_floorf:
9075 case LibFunc_floorl:
9079 case LibFunc_nearbyint:
9080 case LibFunc_nearbyintf:
9081 case LibFunc_nearbyintl:
9098 case LibFunc_roundf:
9099 case LibFunc_roundl:
9104 case LibFunc_truncf:
9105 case LibFunc_truncl:
9122 case LibFunc_exp10f:
9123 case LibFunc_exp10l:
9128 case LibFunc_ldexpf:
9129 case LibFunc_ldexpl:
9133 case LibFunc_memcmp:
9134 if (visitMemCmpBCmpCall(
I))
9137 case LibFunc_mempcpy:
9138 if (visitMemPCpyCall(
I))
9141 case LibFunc_memchr:
9142 if (visitMemChrCall(
I))
9145 case LibFunc_strcpy:
9146 if (visitStrCpyCall(
I,
false))
9149 case LibFunc_stpcpy:
9150 if (visitStrCpyCall(
I,
true))
9153 case LibFunc_strcmp:
9154 if (visitStrCmpCall(
I))
9157 case LibFunc_strlen:
9158 if (visitStrLenCall(
I))
9161 case LibFunc_strnlen:
9162 if (visitStrNLenCall(
I))
9172 assert(!
I.hasOperandBundlesOtherThan(
9173 {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
9174 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
9175 LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi,
9176 LLVMContext::OB_convergencectrl}) &&
9177 "Cannot lower calls with arbitrary operand bundles!");
9215 for (
const auto &Code : Codes)
9230 SDISelAsmOperandInfo &MatchingOpInfo,
9232 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
9238 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
9240 OpInfo.ConstraintVT);
9241 std::pair<unsigned, const TargetRegisterClass *> InputRC =
9243 MatchingOpInfo.ConstraintVT);
9244 if ((OpInfo.ConstraintVT.isInteger() !=
9245 MatchingOpInfo.ConstraintVT.isInteger()) ||
9246 (MatchRC.second != InputRC.second)) {
9249 " with a matching output constraint of"
9250 " incompatible type!");
9252 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
9259 SDISelAsmOperandInfo &OpInfo,
9272 const Value *OpVal = OpInfo.CallOperandVal;
9273 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
9274 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
9286 TySize,
DL.getPrefTypeAlign(Ty),
false);
9288 Chain = DAG.
getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
9291 OpInfo.CallOperand = StackSlot;
9304static std::optional<unsigned>
9306 SDISelAsmOperandInfo &OpInfo,
9307 SDISelAsmOperandInfo &RefOpInfo) {
9318 return std::nullopt;
9322 unsigned AssignedReg;
9325 &
TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
9328 return std::nullopt;
9333 const MVT RegVT = *
TRI.legalclasstypes_begin(*RC);
9335 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
9344 !
TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
9349 if (RegVT.
getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
9354 OpInfo.CallOperand =
9356 OpInfo.ConstraintVT = RegVT;
9360 }
else if (RegVT.
isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
9363 OpInfo.CallOperand =
9365 OpInfo.ConstraintVT = VT;
9372 if (OpInfo.isMatchingInputConstraint())
9373 return std::nullopt;
9375 EVT ValueVT = OpInfo.ConstraintVT;
9376 if (OpInfo.ConstraintVT == MVT::Other)
9380 unsigned NumRegs = 1;
9381 if (OpInfo.ConstraintVT != MVT::Other)
9396 I = std::find(
I, RC->
end(), AssignedReg);
9397 if (
I == RC->
end()) {
9400 return {AssignedReg};
9404 for (; NumRegs; --NumRegs, ++
I) {
9405 assert(
I != RC->
end() &&
"Ran out of registers to allocate!");
9410 OpInfo.AssignedRegs =
RegsForValue(Regs, RegVT, ValueVT);
9411 return std::nullopt;
9416 const std::vector<SDValue> &AsmNodeOperands) {
9419 for (; OperandNo; --OperandNo) {
9421 unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
9424 (
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
F.isMemKind()) &&
9425 "Skipped past definitions?");
9426 CurOp +=
F.getNumOperandRegisters() + 1;
9437 explicit ExtraFlags(
const CallBase &Call) {
9439 if (
IA->hasSideEffects())
9441 if (
IA->isAlignStack())
9443 if (
Call.isConvergent())
9464 unsigned get()
const {
return Flags; }
9471 if (
auto *GA = dyn_cast<GlobalAddressSDNode>(
Op)) {
9472 auto Fn = dyn_cast_or_null<Function>(GA->getGlobal());
9487void SelectionDAGBuilder::visitInlineAsm(
const CallBase &Call,
9500 bool HasSideEffect =
IA->hasSideEffects();
9501 ExtraFlags ExtraInfo(Call);
9503 for (
auto &
T : TargetConstraints) {
9504 ConstraintOperands.
push_back(SDISelAsmOperandInfo(
T));
9505 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.
back();
9507 if (OpInfo.CallOperandVal)
9508 OpInfo.CallOperand =
getValue(OpInfo.CallOperandVal);
9511 HasSideEffect = OpInfo.hasMemory(TLI);
9520 OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
9523 return emitInlineAsmError(Call,
"constraint '" +
Twine(
T.ConstraintCode) +
9524 "' expects an integer constant "
9527 ExtraInfo.update(
T);
9534 bool EmitEHLabels = isa<InvokeInst>(Call);
9536 assert(EHPadBB &&
"InvokeInst must have an EHPadBB");
9538 bool IsCallBr = isa<CallBrInst>(Call);
9540 if (IsCallBr || EmitEHLabels) {
9549 Chain = lowerStartEH(Chain, EHPadBB, BeginLabel);
9554 IA->collectAsmStrs(AsmStrs);
9557 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9565 if (OpInfo.hasMatchingInput()) {
9566 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
9597 if (OpInfo.isIndirect &&
isFunction(OpInfo.CallOperand) &&
9600 OpInfo.isIndirect =
false;
9607 !OpInfo.isIndirect) {
9608 assert((OpInfo.isMultipleAlternative ||
9610 "Can only indirectify direct input operands!");
9616 OpInfo.CallOperandVal =
nullptr;
9619 OpInfo.isIndirect =
true;
9625 std::vector<SDValue> AsmNodeOperands;
9626 AsmNodeOperands.push_back(
SDValue());
9633 const MDNode *SrcLoc =
Call.getMetadata(
"srcloc");
9643 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9645 SDISelAsmOperandInfo &RefOpInfo =
9646 OpInfo.isMatchingInputConstraint()
9647 ? ConstraintOperands[OpInfo.getMatchedOperand()]
9649 const auto RegError =
9654 const char *
RegName =
TRI.getName(*RegError);
9655 emitInlineAsmError(Call,
"register '" +
Twine(
RegName) +
9656 "' allocated for constraint '" +
9657 Twine(OpInfo.ConstraintCode) +
9658 "' does not match required type");
9662 auto DetectWriteToReservedRegister = [&]() {
9665 for (
unsigned Reg : OpInfo.AssignedRegs.Regs) {
9667 TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
9669 emitInlineAsmError(Call,
"write to reserved register '" +
9678 !OpInfo.isMatchingInputConstraint())) &&
9679 "Only address as input operand is allowed.");
9681 switch (OpInfo.Type) {
9687 "Failed to convert memory constraint code to constraint id.");
9691 OpFlags.setMemConstraint(ConstraintID);
9694 AsmNodeOperands.push_back(OpInfo.CallOperand);
9699 if (OpInfo.AssignedRegs.Regs.empty()) {
9701 Call,
"couldn't allocate output register for constraint '" +
9702 Twine(OpInfo.ConstraintCode) +
"'");
9706 if (DetectWriteToReservedRegister())
9711 OpInfo.AssignedRegs.AddInlineAsmOperands(
9720 SDValue InOperandVal = OpInfo.CallOperand;
9722 if (OpInfo.isMatchingInputConstraint()) {
9728 if (
Flag.isRegDefKind() ||
Flag.isRegDefEarlyClobberKind()) {
9729 if (OpInfo.isIndirect) {
9731 emitInlineAsmError(Call,
"inline asm not supported yet: "
9732 "don't know how to handle tied "
9733 "indirect register inputs");
9741 auto *
R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]);
9743 MVT RegVT =
R->getSimpleValueType(0);
9747 :
TRI.getMinimalPhysRegClass(TiedReg);
9748 for (
unsigned i = 0, e =
Flag.getNumOperandRegisters(); i != e; ++i)
9755 MatchedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue, &Call);
9757 OpInfo.getMatchedOperand(), dl,
DAG,
9762 assert(
Flag.isMemKind() &&
"Unknown matching constraint!");
9764 "Unexpected number of operands");
9767 Flag.clearMemConstraint();
9768 Flag.setMatchingOp(OpInfo.getMatchedOperand());
9771 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
9782 std::vector<SDValue> Ops;
9787 if (isa<ConstantSDNode>(InOperandVal)) {
9788 emitInlineAsmError(Call,
"value out of range for constraint '" +
9789 Twine(OpInfo.ConstraintCode) +
"'");
9793 emitInlineAsmError(Call,
9794 "invalid operand for inline asm constraint '" +
9795 Twine(OpInfo.ConstraintCode) +
"'");
9808 assert((OpInfo.isIndirect ||
9810 "Operand must be indirect to be a mem!");
9813 "Memory operands expect pointer values");
9818 "Failed to convert memory constraint code to constraint id.");
9822 ResOpType.setMemConstraint(ConstraintID);
9826 AsmNodeOperands.push_back(InOperandVal);
9834 "Failed to convert memory constraint code to constraint id.");
9840 auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
9848 ResOpType.setMemConstraint(ConstraintID);
9850 AsmNodeOperands.push_back(
9853 AsmNodeOperands.push_back(AsmOp);
9859 "Unknown constraint type!");
9862 if (OpInfo.isIndirect) {
9864 Call,
"Don't know how to handle indirect register inputs yet "
9865 "for constraint '" +
9866 Twine(OpInfo.ConstraintCode) +
"'");
9871 if (OpInfo.AssignedRegs.Regs.empty()) {
9872 emitInlineAsmError(Call,
9873 "couldn't allocate input reg for constraint '" +
9874 Twine(OpInfo.ConstraintCode) +
"'");
9878 if (DetectWriteToReservedRegister())
9883 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue,
9887 0, dl,
DAG, AsmNodeOperands);
9893 if (!OpInfo.AssignedRegs.Regs.empty())
9903 if (Glue.
getNode()) AsmNodeOperands.push_back(Glue);
9907 DAG.
getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
9918 if (
StructType *StructResult = dyn_cast<StructType>(CallResultType))
9919 ResultTypes = StructResult->elements();
9920 else if (!CallResultType->
isVoidTy())
9921 ResultTypes =
ArrayRef(CallResultType);
9923 auto CurResultType = ResultTypes.
begin();
9924 auto handleRegAssign = [&](
SDValue V) {
9925 assert(CurResultType != ResultTypes.
end() &&
"Unexpected value");
9926 assert((*CurResultType)->isSized() &&
"Unexpected unsized type");
9939 if (ResultVT !=
V.getValueType() &&
9942 else if (ResultVT !=
V.getValueType() && ResultVT.
isInteger() &&
9943 V.getValueType().isInteger()) {
9949 assert(ResultVT ==
V.getValueType() &&
"Asm result value mismatch!");
9955 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9959 if (OpInfo.AssignedRegs.Regs.empty())
9962 switch (OpInfo.ConstraintType) {
9966 Chain, &Glue, &Call);
9978 assert(
false &&
"Unexpected unknown constraint");
9982 if (OpInfo.isIndirect) {
9983 const Value *
Ptr = OpInfo.CallOperandVal;
9984 assert(
Ptr &&
"Expected value CallOperandVal for indirect asm operand");
9990 assert(!
Call.getType()->isVoidTy() &&
"Bad inline asm!");
9995 handleRegAssign(Val);
10001 if (!ResultValues.
empty()) {
10002 assert(CurResultType == ResultTypes.
end() &&
10003 "Mismatch in number of ResultTypes");
10005 "Mismatch in number of output operands in asm result");
10013 if (!OutChains.
empty())
10016 if (EmitEHLabels) {
10017 Chain = lowerEndEH(Chain, cast<InvokeInst>(&Call), EHPadBB, BeginLabel);
10021 if (ResultValues.
empty() || HasSideEffect || !OutChains.
empty() || IsCallBr ||
10026void SelectionDAGBuilder::emitInlineAsmError(
const CallBase &Call,
10027 const Twine &Message) {
10036 if (ValueVTs.
empty())
10040 for (
unsigned i = 0, e = ValueVTs.
size(); i != e; ++i)
10046void SelectionDAGBuilder::visitVAStart(
const CallInst &
I) {
10053void SelectionDAGBuilder::visitVAArg(
const VAArgInst &
I) {
10059 DL.getABITypeAlign(
I.getType()).value());
10062 if (
I.getType()->isPointerTy())
10068void SelectionDAGBuilder::visitVAEnd(
const CallInst &
I) {
10075void SelectionDAGBuilder::visitVACopy(
const CallInst &
I) {
10096 if (!
Lo.isMinValue())
10100 unsigned Bits = std::max(
Hi.getActiveBits(),
10109 unsigned NumVals =
Op.getNode()->getNumValues();
10116 for (
unsigned I = 1;
I != NumVals; ++
I)
10130 unsigned ArgIdx,
unsigned NumArgs,
SDValue Callee,
Type *ReturnTy,
10133 Args.reserve(NumArgs);
10137 for (
unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
10138 ArgI != ArgE; ++ArgI) {
10139 const Value *V = Call->getOperand(ArgI);
10141 assert(!V->getType()->isEmptyTy() &&
"Empty type passed to intrinsic.");
10145 Entry.Ty = V->getType();
10146 Entry.setAttributes(Call, ArgI);
10147 Args.push_back(Entry);
10152 .
setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args),
10181 for (
unsigned I = StartIdx;
I < Call.arg_size();
I++) {
10196void SelectionDAGBuilder::visitStackmap(
const CallInst &CI) {
10230 assert(
ID.getValueType() == MVT::i64);
10261void SelectionDAGBuilder::visitPatchpoint(
const CallBase &CB,
10277 if (
auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
10280 else if (
auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
10282 SDLoc(SymbolicCallee),
10283 SymbolicCallee->getValueType(0));
10293 "Not enough arguments provided to the patchpoint intrinsic");
10296 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
10312 "Expected a callseq node.");
10314 bool HasGlue =
Call->getGluedNode();
10344 unsigned NumCallRegArgs =
Call->getNumOperands() - (HasGlue ? 4 : 3);
10345 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
10354 for (
unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i !=
e; ++i)
10365 if (IsAnyRegCC && HasDef) {
10370 assert(ValueVTs.
size() == 1 &&
"Expected only one return value type.");
10394 if (IsAnyRegCC && HasDef) {
10406void SelectionDAGBuilder::visitVectorReduce(
const CallInst &
I,
10407 unsigned Intrinsic) {
10411 if (
I.arg_size() > 1)
10417 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
10420 switch (Intrinsic) {
10421 case Intrinsic::vector_reduce_fadd:
10429 case Intrinsic::vector_reduce_fmul:
10437 case Intrinsic::vector_reduce_add:
10440 case Intrinsic::vector_reduce_mul:
10443 case Intrinsic::vector_reduce_and:
10446 case Intrinsic::vector_reduce_or:
10449 case Intrinsic::vector_reduce_xor:
10452 case Intrinsic::vector_reduce_smax:
10455 case Intrinsic::vector_reduce_smin:
10458 case Intrinsic::vector_reduce_umax:
10461 case Intrinsic::vector_reduce_umin:
10464 case Intrinsic::vector_reduce_fmax:
10467 case Intrinsic::vector_reduce_fmin:
10470 case Intrinsic::vector_reduce_fmaximum:
10473 case Intrinsic::vector_reduce_fminimum:
10487 Attrs.push_back(Attribute::SExt);
10489 Attrs.push_back(Attribute::ZExt);
10491 Attrs.push_back(Attribute::InReg);
10501std::pair<SDValue, SDValue>
10515 RetTys.
swap(OldRetTys);
10516 Offsets.swap(OldOffsets);
10518 for (
size_t i = 0, e = OldRetTys.
size(); i != e; ++i) {
10519 EVT RetVT = OldRetTys[i];
10523 unsigned RegisterVTByteSZ = RegisterVT.
getSizeInBits() / 8;
10524 RetTys.
append(NumRegs, RegisterVT);
10525 for (
unsigned j = 0; j != NumRegs; ++j)
10538 int DemoteStackIdx = -100;
10549 DL.getAllocaAddrSpace());
10553 Entry.Node = DemoteStackSlot;
10554 Entry.Ty = StackSlotPtrType;
10555 Entry.IsSExt =
false;
10556 Entry.IsZExt =
false;
10557 Entry.IsInReg =
false;
10558 Entry.IsSRet =
true;
10559 Entry.IsNest =
false;
10560 Entry.IsByVal =
false;
10561 Entry.IsByRef =
false;
10562 Entry.IsReturned =
false;
10563 Entry.IsSwiftSelf =
false;
10564 Entry.IsSwiftAsync =
false;
10565 Entry.IsSwiftError =
false;
10566 Entry.IsCFGuardTarget =
false;
10567 Entry.Alignment = Alignment;
10579 for (
unsigned I = 0, E = RetTys.
size();
I != E; ++
I) {
10581 if (NeedsRegBlock) {
10582 Flags.setInConsecutiveRegs();
10583 if (
I == RetTys.
size() - 1)
10584 Flags.setInConsecutiveRegsLast();
10586 EVT VT = RetTys[
I];
10591 for (
unsigned i = 0; i != NumRegs; ++i) {
10593 MyFlags.
Flags = Flags;
10594 MyFlags.
VT = RegisterVT;
10595 MyFlags.
ArgVT = VT;
10600 cast<PointerType>(CLI.
RetTy)->getAddressSpace());
10608 CLI.
Ins.push_back(MyFlags);
10622 CLI.
Ins.push_back(MyFlags);
10630 for (
unsigned i = 0, e = Args.size(); i != e; ++i) {
10634 Type *FinalType = Args[i].Ty;
10635 if (Args[i].IsByVal)
10636 FinalType = Args[i].IndirectType;
10639 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
Value != NumValues;
10644 Args[i].Node.getResNo() +
Value);
10651 Flags.setOrigAlign(OriginalAlignment);
10653 if (Args[i].Ty->isPointerTy()) {
10654 Flags.setPointer();
10655 Flags.setPointerAddrSpace(
10656 cast<PointerType>(Args[i].Ty)->getAddressSpace());
10658 if (Args[i].IsZExt)
10660 if (Args[i].IsSExt)
10662 if (Args[i].IsInReg) {
10666 isa<StructType>(FinalType)) {
10669 Flags.setHvaStart();
10675 if (Args[i].IsSRet)
10677 if (Args[i].IsSwiftSelf)
10678 Flags.setSwiftSelf();
10679 if (Args[i].IsSwiftAsync)
10680 Flags.setSwiftAsync();
10681 if (Args[i].IsSwiftError)
10682 Flags.setSwiftError();
10683 if (Args[i].IsCFGuardTarget)
10684 Flags.setCFGuardTarget();
10685 if (Args[i].IsByVal)
10687 if (Args[i].IsByRef)
10689 if (Args[i].IsPreallocated) {
10690 Flags.setPreallocated();
10698 if (Args[i].IsInAlloca) {
10699 Flags.setInAlloca();
10708 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
10709 unsigned FrameSize =
DL.getTypeAllocSize(Args[i].IndirectType);
10710 Flags.setByValSize(FrameSize);
10713 if (
auto MA = Args[i].Alignment)
10717 }
else if (
auto MA = Args[i].Alignment) {
10720 MemAlign = OriginalAlignment;
10722 Flags.setMemAlign(MemAlign);
10723 if (Args[i].IsNest)
10726 Flags.setInConsecutiveRegs();
10735 if (Args[i].IsSExt)
10737 else if (Args[i].IsZExt)
10742 if (Args[i].IsReturned && !
Op.getValueType().isVector() &&
10747 Args[i].Ty->getPointerAddressSpace())) &&
10748 RetTys.
size() == NumValues &&
"unexpected use of 'returned'");
10761 CLI.
RetZExt == Args[i].IsZExt))
10762 Flags.setReturned();
10768 for (
unsigned j = 0; j != NumParts; ++j) {
10775 j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
10776 if (NumParts > 1 && j == 0)
10780 if (j == NumParts - 1)
10784 CLI.
Outs.push_back(MyFlags);
10785 CLI.
OutVals.push_back(Parts[j]);
10788 if (NeedsRegBlock &&
Value == NumValues - 1)
10789 CLI.
Outs[CLI.
Outs.size() - 1].Flags.setInConsecutiveRegsLast();
10801 "LowerCall didn't return a valid chain!");
10803 "LowerCall emitted a return value for a tail call!");
10805 "LowerCall didn't emit the correct number of values!");
10817 for (
unsigned i = 0, e = CLI.
Ins.size(); i != e; ++i) {
10818 assert(InVals[i].getNode() &&
"LowerCall emitted a null value!");
10819 assert(
EVT(CLI.
Ins[i].VT) == InVals[i].getValueType() &&
10820 "LowerCall emitted a value with the wrong type!");
10833 assert(PVTs.
size() == 1 &&
"Pointers should fit in one register");
10834 EVT PtrVT = PVTs[0];
10836 unsigned NumValues = RetTys.
size();
10837 ReturnValues.
resize(NumValues);
10843 Flags.setNoUnsignedWrap(
true);
10847 for (
unsigned i = 0; i < NumValues; ++i) {
10854 DemoteStackIdx, Offsets[i]),
10856 ReturnValues[i] = L;
10857 Chains[i] = L.getValue(1);
10864 std::optional<ISD::NodeType> AssertOp;
10869 unsigned CurReg = 0;
10870 for (
EVT VT : RetTys) {
10877 CLI.
DAG, CLI.
DL, &InVals[CurReg], NumRegs, RegisterVT, VT,
nullptr,
10885 if (ReturnValues.
empty())
10891 return std::make_pair(Res, CLI.
Chain);
10908 if (
N->getNumValues() == 1) {
10916 "Lowering returned the wrong number of results!");
10919 for (
unsigned I = 0, E =
N->getNumValues();
I != E; ++
I)
10932 cast<RegisterSDNode>(
Op.getOperand(1))->getReg() != Reg) &&
10933 "Copy from a reg to the same reg!");
10947 ExtendType = PreferredExtendIt->second;
10950 PendingExports.push_back(Chain);
10962 return A->use_empty();
10964 const BasicBlock &Entry =
A->getParent()->front();
10965 for (
const User *U :
A->users())
10966 if (cast<Instruction>(U)->
getParent() != &Entry || isa<SwitchInst>(U))
10974 std::pair<const AllocaInst *, const StoreInst *>>;
10986 enum StaticAllocaInfo {
Unknown, Clobbered, Elidable };
10988 unsigned NumArgs = FuncInfo->
Fn->
arg_size();
10989 StaticAllocas.
reserve(NumArgs * 2);
10991 auto GetInfoIfStaticAlloca = [&](
const Value *V) -> StaticAllocaInfo * {
10994 V = V->stripPointerCasts();
10995 const auto *AI = dyn_cast<AllocaInst>(V);
10996 if (!AI || !AI->isStaticAlloca() || !FuncInfo->
StaticAllocaMap.count(AI))
10999 return &Iter.first->second;
11009 const auto *SI = dyn_cast<StoreInst>(&
I);
11016 if (
I.isDebugOrPseudoInst())
11020 for (
const Use &U :
I.operands()) {
11021 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(U))
11022 *
Info = StaticAllocaInfo::Clobbered;
11028 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
11029 *
Info = StaticAllocaInfo::Clobbered;
11032 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
11033 StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(Dst);
11036 const AllocaInst *AI = cast<AllocaInst>(Dst);
11039 if (*
Info != StaticAllocaInfo::Unknown)
11047 const Value *Val = SI->getValueOperand()->stripPointerCasts();
11048 const auto *Arg = dyn_cast<Argument>(Val);
11049 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
11050 Arg->getType()->isEmptyTy() ||
11051 DL.getTypeStoreSize(Arg->getType()) !=
11053 !
DL.typeSizeEqualsStoreSize(Arg->getType()) ||
11054 ArgCopyElisionCandidates.
count(Arg)) {
11055 *
Info = StaticAllocaInfo::Clobbered;
11059 LLVM_DEBUG(
dbgs() <<
"Found argument copy elision candidate: " << *AI
11063 *
Info = StaticAllocaInfo::Elidable;
11064 ArgCopyElisionCandidates.
insert({Arg, {AI, SI}});
11069 if (ArgCopyElisionCandidates.
size() == NumArgs)
11083 auto *LNode = dyn_cast<LoadSDNode>(ArgVals[0]);
11086 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
11093 auto ArgCopyIter = ArgCopyElisionCandidates.
find(&Arg);
11094 assert(ArgCopyIter != ArgCopyElisionCandidates.
end());
11095 const AllocaInst *AI = ArgCopyIter->second.first;
11096 int FixedIndex = FINode->getIndex();
11098 int OldIndex = AllocaIndex;
11102 dbgs() <<
" argument copy elision failed due to bad fixed stack "
11108 LLVM_DEBUG(
dbgs() <<
" argument copy elision failed: alignment of alloca "
11109 "greater than stack argument alignment ("
11110 <<
DebugStr(RequiredAlignment) <<
" vs "
11118 dbgs() <<
"Eliding argument copy from " << Arg <<
" to " << *AI <<
'\n'
11119 <<
" Replacing frame index " << OldIndex <<
" with " << FixedIndex
11124 AllocaIndex = FixedIndex;
11125 ArgCopyElisionFrameIndexMap.
insert({OldIndex, FixedIndex});
11126 for (
SDValue ArgVal : ArgVals)
11130 const StoreInst *SI = ArgCopyIter->second.second;
11131 ElidedArgCopyInstrs.
insert(SI);
11143void SelectionDAGISel::LowerArguments(
const Function &
F) {
11150 if (
F.hasFnAttribute(Attribute::Naked))
11168 Ins.push_back(RetArg);
11176 ArgCopyElisionCandidates);
11180 unsigned ArgNo = Arg.getArgNo();
11183 bool isArgValueUsed = !Arg.use_empty();
11184 unsigned PartBase = 0;
11185 Type *FinalType = Arg.getType();
11186 if (Arg.hasAttribute(Attribute::ByVal))
11187 FinalType = Arg.getParamByValType();
11189 FinalType,
F.getCallingConv(),
F.isVarArg(),
DL);
11190 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
11197 if (Arg.getType()->isPointerTy()) {
11198 Flags.setPointer();
11199 Flags.setPointerAddrSpace(
11200 cast<PointerType>(Arg.getType())->getAddressSpace());
11202 if (Arg.hasAttribute(Attribute::ZExt))
11204 if (Arg.hasAttribute(Attribute::SExt))
11206 if (Arg.hasAttribute(Attribute::InReg)) {
11210 isa<StructType>(Arg.getType())) {
11213 Flags.setHvaStart();
11219 if (Arg.hasAttribute(Attribute::StructRet))
11221 if (Arg.hasAttribute(Attribute::SwiftSelf))
11222 Flags.setSwiftSelf();
11223 if (Arg.hasAttribute(Attribute::SwiftAsync))
11224 Flags.setSwiftAsync();
11225 if (Arg.hasAttribute(Attribute::SwiftError))
11226 Flags.setSwiftError();
11227 if (Arg.hasAttribute(Attribute::ByVal))
11229 if (Arg.hasAttribute(Attribute::ByRef))
11231 if (Arg.hasAttribute(Attribute::InAlloca)) {
11232 Flags.setInAlloca();
11240 if (Arg.hasAttribute(Attribute::Preallocated)) {
11241 Flags.setPreallocated();
11253 const Align OriginalAlignment(
11255 Flags.setOrigAlign(OriginalAlignment);
11258 Type *ArgMemTy =
nullptr;
11259 if (
Flags.isByVal() ||
Flags.isInAlloca() ||
Flags.isPreallocated() ||
11262 ArgMemTy = Arg.getPointeeInMemoryValueType();
11264 uint64_t MemSize =
DL.getTypeAllocSize(ArgMemTy);
11269 if (
auto ParamAlign = Arg.getParamStackAlign())
11270 MemAlign = *ParamAlign;
11271 else if ((ParamAlign = Arg.getParamAlign()))
11272 MemAlign = *ParamAlign;
11275 if (
Flags.isByRef())
11276 Flags.setByRefSize(MemSize);
11278 Flags.setByValSize(MemSize);
11279 }
else if (
auto ParamAlign = Arg.getParamStackAlign()) {
11280 MemAlign = *ParamAlign;
11282 MemAlign = OriginalAlignment;
11284 Flags.setMemAlign(MemAlign);
11286 if (Arg.hasAttribute(Attribute::Nest))
11289 Flags.setInConsecutiveRegs();
11290 if (ArgCopyElisionCandidates.
count(&Arg))
11291 Flags.setCopyElisionCandidate();
11292 if (Arg.hasAttribute(Attribute::Returned))
11293 Flags.setReturned();
11299 for (
unsigned i = 0; i != NumRegs; ++i) {
11304 Flags, RegisterVT, VT, isArgValueUsed, ArgNo,
11306 if (NumRegs > 1 && i == 0)
11307 MyFlags.Flags.setSplit();
11310 MyFlags.Flags.setOrigAlign(
Align(1));
11311 if (i == NumRegs - 1)
11312 MyFlags.Flags.setSplitEnd();
11314 Ins.push_back(MyFlags);
11316 if (NeedsRegBlock &&
Value == NumValues - 1)
11317 Ins[
Ins.size() - 1].Flags.setInConsecutiveRegsLast();
11325 DAG.
getRoot(),
F.getCallingConv(),
F.isVarArg(), Ins, dl, DAG, InVals);
11329 "LowerFormalArguments didn't return a valid chain!");
11331 "LowerFormalArguments didn't emit the correct number of values!");
11333 for (
unsigned i = 0, e =
Ins.size(); i != e; ++i) {
11334 assert(InVals[i].getNode() &&
11335 "LowerFormalArguments emitted a null value!");
11336 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
11337 "LowerFormalArguments emitted a value with the wrong type!");
11354 MVT VT = ValueVTs[0].getSimpleVT();
11356 std::optional<ISD::NodeType> AssertOp;
11359 F.getCallingConv(), AssertOp);
11365 FuncInfo->DemoteRegister = SRetReg;
11367 SDB->DAG.getCopyToReg(NewRoot,
SDB->getCurSDLoc(), SRetReg, ArgValue);
11380 unsigned NumValues = ValueVTs.
size();
11381 if (NumValues == 0)
11384 bool ArgHasUses = !Arg.use_empty();
11388 if (Ins[i].
Flags.isCopyElisionCandidate()) {
11389 unsigned NumParts = 0;
11390 for (
EVT VT : ValueVTs)
11392 F.getCallingConv(), VT);
11396 ArrayRef(&InVals[i], NumParts), ArgHasUses);
11401 bool isSwiftErrorArg =
11403 Arg.hasAttribute(Attribute::SwiftError);
11404 if (!ArgHasUses && !isSwiftErrorArg) {
11405 SDB->setUnusedArgValue(&Arg, InVals[i]);
11409 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
11410 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11413 for (
unsigned Val = 0; Val != NumValues; ++Val) {
11414 EVT VT = ValueVTs[Val];
11416 F.getCallingConv(), VT);
11423 if (ArgHasUses || isSwiftErrorArg) {
11424 std::optional<ISD::NodeType> AssertOp;
11425 if (Arg.hasAttribute(Attribute::SExt))
11427 else if (Arg.hasAttribute(Attribute::ZExt))
11431 PartVT, VT,
nullptr, NewRoot,
11432 F.getCallingConv(), AssertOp));
11439 if (ArgValues.
empty())
11444 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
11445 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11448 SDB->getCurSDLoc());
11450 SDB->setValue(&Arg, Res);
11463 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
11464 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11473 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11485 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11492 FuncInfo->InitializeRegForValue(&Arg);
11493 SDB->CopyToExportRegsIfNeeded(&Arg);
11497 if (!Chains.
empty()) {
11504 assert(i == InVals.
size() &&
"Argument register count mismatch!");
11508 if (!ArgCopyElisionFrameIndexMap.
empty()) {
11511 auto I = ArgCopyElisionFrameIndexMap.
find(
VI.getStackSlot());
11512 if (
I != ArgCopyElisionFrameIndexMap.
end())
11513 VI.updateStackSlot(
I->second);
11528SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB) {
11536 if (!isa<PHINode>(SuccBB->begin()))
continue;
11541 if (!SuccsHandled.
insert(SuccMBB).second)
11549 for (
const PHINode &PN : SuccBB->phis()) {
11551 if (PN.use_empty())
11555 if (PN.getType()->isEmptyTy())
11559 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
11561 if (
const auto *
C = dyn_cast<Constant>(PHIOp)) {
11568 if (
auto *CI = dyn_cast<ConstantInt>(
C))
11580 assert(isa<AllocaInst>(PHIOp) &&
11582 "Didn't codegen value into a register!??");
11592 for (
EVT VT : ValueVTs) {
11594 for (
unsigned i = 0; i != NumRegisters; ++i)
11596 std::make_pair(&*
MBBI++, Reg + i));
11597 Reg += NumRegisters;
11617void SelectionDAGBuilder::updateDAGForMaybeTailCall(
SDValue MaybeTC) {
11619 if (MaybeTC.
getNode() !=
nullptr)
11634 unsigned Size =
W.LastCluster -
W.FirstCluster + 1;
11638 if (
Size == 2 &&
W.MBB == SwitchMBB) {
11651 const APInt &SmallValue =
Small.Low->getValue();
11652 const APInt &BigValue =
Big.Low->getValue();
11655 APInt CommonBit = BigValue ^ SmallValue;
11670 addSuccessorWithProb(SwitchMBB,
Small.MBB,
Small.Prob +
Big.Prob);
11672 addSuccessorWithProb(
11673 SwitchMBB, DefaultMBB,
11677 addSuccessorWithProb(SwitchMBB, DefaultMBB);
11700 return a.Prob != b.Prob ?
11702 a.Low->getValue().slt(b.Low->getValue());
11709 if (
I->Prob >
W.LastCluster->Prob)
11711 if (
I->Kind ==
CC_Range &&
I->MBB == NextMBB) {
11722 UnhandledProbs +=
I->Prob;
11726 bool FallthroughUnreachable =
false;
11728 if (
I ==
W.LastCluster) {
11730 Fallthrough = DefaultMBB;
11731 FallthroughUnreachable = isa<UnreachableInst>(
11735 CurMF->
insert(BBI, Fallthrough);
11739 UnhandledProbs -=
I->Prob;
11749 CurMF->
insert(BBI, JumpMBB);
11751 auto JumpProb =
I->Prob;
11752 auto FallthroughProb = UnhandledProbs;
11760 if (*SI == DefaultMBB) {
11761 JumpProb += DefaultProb / 2;
11762 FallthroughProb -= DefaultProb / 2;
11780 if (FallthroughUnreachable) {
11782 bool HasBranchTargetEnforcement =
false;
11784 HasBranchTargetEnforcement =
11788 HasBranchTargetEnforcement =
11790 "branch-target-enforcement");
11792 if (!HasBranchTargetEnforcement)
11797 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
11798 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
11804 JT->Default = Fallthrough;
11807 if (CurMBB == SwitchMBB) {
11830 BTB->
Prob += DefaultProb / 2;
11834 if (FallthroughUnreachable)
11838 if (CurMBB == SwitchMBB) {
11847 if (
I->Low ==
I->High) {
11862 if (FallthroughUnreachable)
11866 CaseBlock CB(
CC, LHS, RHS, MHS,
I->MBB, Fallthrough, CurMBB,
11869 if (CurMBB == SwitchMBB)
11872 SL->SwitchCases.push_back(CB);
11877 CurMBB = Fallthrough;
11881void SelectionDAGBuilder::splitWorkItem(
SwitchWorkList &WorkList,
11885 assert(
W.FirstCluster->Low->getValue().slt(
W.LastCluster->Low->getValue()) &&
11886 "Clusters not sorted?");
11887 assert(
W.LastCluster -
W.FirstCluster + 1 >= 2 &&
"Too small to split!");
11889 auto [LastLeft, FirstRight, LeftProb, RightProb] =
11890 SL->computeSplitWorkItemInfo(W);
11895 assert(PivotCluster >
W.FirstCluster);
11896 assert(PivotCluster <=
W.LastCluster);
11911 if (FirstLeft == LastLeft && FirstLeft->Kind ==
CC_Range &&
11912 FirstLeft->Low ==
W.GE &&
11913 (FirstLeft->High->getValue() + 1LL) == Pivot->
getValue()) {
11914 LeftMBB = FirstLeft->MBB;
11919 {LeftMBB, FirstLeft, LastLeft,
W.GE, Pivot,
W.DefaultProb / 2});
11928 if (FirstRight == LastRight && FirstRight->Kind ==
CC_Range &&
11929 W.LT && (FirstRight->High->getValue() + 1ULL) ==
W.LT->getValue()) {
11930 RightMBB = FirstRight->MBB;
11935 {RightMBB, FirstRight, LastRight, Pivot,
W.LT,
W.DefaultProb / 2});
11944 if (
W.MBB == SwitchMBB)
11947 SL->SwitchCases.push_back(CB);
11980 unsigned PeeledCaseIndex = 0;
11981 bool SwitchPeeled =
false;
11984 if (
CC.Prob < TopCaseProb)
11986 TopCaseProb =
CC.Prob;
11987 PeeledCaseIndex =
Index;
11988 SwitchPeeled =
true;
11993 LLVM_DEBUG(
dbgs() <<
"Peeled one top case in switch stmt, prob: "
11994 << TopCaseProb <<
"\n");
12004 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
12006 nullptr,
nullptr, TopCaseProb.
getCompl()};
12007 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
12009 Clusters.erase(PeeledCaseIt);
12012 dbgs() <<
"Scale the probablity for one cluster, before scaling: "
12013 <<
CC.Prob <<
"\n");
12017 PeeledCaseProb = TopCaseProb;
12018 return PeeledSwitchMBB;
12021void SelectionDAGBuilder::visitSwitch(
const SwitchInst &SI) {
12025 Clusters.reserve(
SI.getNumCases());
12026 for (
auto I :
SI.cases()) {
12045 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
12049 if (Clusters.empty()) {
12050 assert(PeeledSwitchMBB == SwitchMBB);
12052 if (DefaultMBB != NextBlock(SwitchMBB)) {
12061 SL->findBitTestClusters(Clusters, &SI);
12064 dbgs() <<
"Case clusters: ";
12071 C.Low->getValue().print(
dbgs(),
true);
12072 if (
C.Low !=
C.High) {
12074 C.High->getValue().print(
dbgs(),
true);
12081 assert(!Clusters.empty());
12085 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
12092 {PeeledSwitchMBB,
First,
Last,
nullptr,
nullptr, DefaultProb});
12094 while (!WorkList.
empty()) {
12096 unsigned NumClusters =
W.LastCluster -
W.FirstCluster + 1;
12101 splitWorkItem(WorkList, W,
SI.getCondition(), SwitchMBB);
12105 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, DefaultMBB);
12109void SelectionDAGBuilder::visitStepVector(
const CallInst &
I) {
12116void SelectionDAGBuilder::visitVectorReverse(
const CallInst &
I) {
12122 assert(VT ==
V.getValueType() &&
"Malformed vector.reverse!");
12133 for (
unsigned i = 0; i != NumElts; ++i)
12134 Mask.push_back(NumElts - 1 - i);
12139void SelectionDAGBuilder::visitVectorDeinterleave(
const CallInst &
I) {
12170void SelectionDAGBuilder::visitVectorInterleave(
const CallInst &
I) {
12195void SelectionDAGBuilder::visitFreeze(
const FreezeInst &
I) {
12199 unsigned NumValues = ValueVTs.
size();
12200 if (NumValues == 0)
return;
12205 for (
unsigned i = 0; i != NumValues; ++i)
12213void SelectionDAGBuilder::visitVectorSplice(
const CallInst &
I) {
12220 int64_t
Imm = cast<ConstantInt>(
I.getOperand(2))->getSExtValue();
12236 for (
unsigned i = 0; i < NumElts; ++i)
12265 assert(
MI->getOpcode() == TargetOpcode::COPY &&
12266 "start of copy chain MUST be COPY");
12267 Reg =
MI->getOperand(1).getReg();
12268 MI =
MRI.def_begin(Reg)->getParent();
12270 if (
MI->getOpcode() == TargetOpcode::COPY) {
12271 assert(Reg.isVirtual() &&
"expected COPY of virtual register");
12272 Reg =
MI->getOperand(1).getReg();
12273 assert(Reg.isPhysical() &&
"expected COPY of physical register");
12274 MI =
MRI.def_begin(Reg)->getParent();
12277 assert(
MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
12278 "end of copy chain MUST be INLINEASM_BR");
12286void SelectionDAGBuilder::visitCallBrLandingPad(
const CallInst &
I) {
12290 cast<CallBrInst>(
I.getParent()->getUniquePredecessor()->getTerminator());
12302 for (
auto &
T : TargetConstraints) {
12303 SDISelAsmOperandInfo OpInfo(
T);
12311 switch (OpInfo.ConstraintType) {
12319 for (
size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) {
12324 OpInfo.AssignedRegs.Regs[i] = OriginalDef;
12327 SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
12330 ResultVTs.
push_back(OpInfo.ConstraintVT);
12339 ResultVTs.
push_back(OpInfo.ConstraintVT);
unsigned const MachineRegisterInfo * MRI
static unsigned getIntrinsicID(const SDNode *N)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
Function Alias Analysis Results
Atomic ordering constants.
This file contains the simple types necessary to represent the attributes associated with functions a...
static const Function * getParent(const Value *V)
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
const HexagonInstrInfo * TII
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
static void getRegistersForValue(MachineFunction &MF, MachineIRBuilder &MIRBuilder, GISelAsmOperandInfo &OpInfo, GISelAsmOperandInfo &RefOpInfo)
Assign virtual/physical registers for the specified register operand.
This file defines an InstructionCost class that is used when calculating the cost of an instruction,...
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool hasOnlySelectUsers(const Value *Cond)
static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain)
Create a LOAD_STACK_GUARD node, and let it carry the target specific global variable if there exists ...
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
static const unsigned MaxParallelChains
static void getUnderlyingArgRegs(SmallVectorImpl< std::pair< unsigned, TypeSize > > &Regs, const SDValue &N)
static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
visitPow - Lower a pow intrinsic.
static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, ISD::MemIndexType &IndexType, SDValue &Scale, SelectionDAGBuilder *SDB, const BasicBlock *CurBB, uint64_t ElemSize)
static const CallBase * FindPreallocatedCall(const Value *PreallocatedSetup)
Given a @llvm.call.preallocated.setup, return the corresponding preallocated call.
static cl::opt< unsigned > SwitchPeelThreshold("switch-peel-threshold", cl::Hidden, cl::init(66), cl::desc("Set the case probability threshold for peeling the case from a " "switch statement. A value greater than 100 will void this " "optimization"))
static cl::opt< bool > InsertAssertAlign("insert-assert-align", cl::init(true), cl::desc("Insert the experimental `assertalign` node."), cl::ReallyHidden)
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin)
static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG, DILocalVariable *Variable, DebugLoc DL, unsigned Order, SmallVectorImpl< Value * > &Values, DIExpression *Expression)
static unsigned findMatchingInlineAsmOperand(unsigned OperandNo, const std::vector< SDValue > &AsmNodeOperands)
static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG)
Make sure that the output operand OpInfo and its corresponding input operand MatchingOpInfo have comp...
static void findUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
When an invoke or a cleanupret unwinds to the next EH pad, there are many places it could ultimately ...
static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic)
static BranchProbability scaleCaseProbality(BranchProbability CaseProb, BranchProbability PeeledCaseProb)
static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp2 - Lower an exp2 intrinsic.
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue Scale, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, const SDLoc &dl)
getF32Constant - Get 32-bit floating point constant.
static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, const SDLoc &DL, EVT PartVT)
static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog10 - Lower a log10 intrinsic.
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv)
getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal par...
static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv=std::nullopt, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
getCopyToParts - Create a series of nodes that contain the specified value split into legal parts.
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, SelectionDAGBuilder &Builder)
static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog2 - Lower a log2 intrinsic.
static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG)
Get a direct memory input to behave well as an indirect operand.
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel)
isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block,...
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, const Twine &ErrMsg)
static bool collectInstructionDeps(SmallMapVector< const Instruction *, bool, 8 > *Deps, const Value *V, SmallMapVector< const Instruction *, bool, 8 > *Necessary=nullptr, unsigned Depth=0)
static void findArgumentCopyElisionCandidates(const DataLayout &DL, FunctionLoweringInfo *FuncInfo, ArgCopyElisionMapTy &ArgCopyElisionCandidates)
Scan the entry block of the function in FuncInfo for arguments that look like copies into a local all...
static bool isFunction(SDValue Op)
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl)
GetExponent - Get the exponent:
static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg)
static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG)
ExpandPowI - Expand a llvm.powi intrinsic.
static void findWasmUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog - Lower a log intrinsic.
static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC=std::nullopt, std::optional< ISD::NodeType > AssertOp=std::nullopt)
getCopyFromParts - Create a value that contains the specified legal parts combined into the value the...
static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, SelectionDAG &DAG)
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl)
GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:
static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp - Lower an exp intrinsic.
static const MDNode * getRangeMetadata(const Instruction &I)
static cl::opt< unsigned, true > LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences " "for some float libcalls"), cl::location(LimitFloatPrecision), cl::Hidden, cl::init(0))
static void tryToElideArgumentCopy(FunctionLoweringInfo &FuncInfo, SmallVectorImpl< SDValue > &Chains, DenseMap< int, int > &ArgCopyElisionFrameIndexMap, SmallPtrSetImpl< const Instruction * > &ElidedArgCopyInstrs, ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, ArrayRef< SDValue > ArgVals, bool &ArgHasUses)
Try to elide argument copies from memory into a local alloca.
static unsigned LimitFloatPrecision
LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6,...
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC)
getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the val...
static bool InBlock(const Value *V, const BasicBlock *BB)
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
static SymbolRef::Type getType(const Symbol *Sym)
support::ulittle16_t & Lo
support::ulittle16_t & Hi
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Class for arbitrary precision integers.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
an instruction to allocate memory on the stack
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
This class represents an incoming formal argument to a Function.
bool hasAttribute(Attribute::AttrKind Kind) const
Check if an argument has a given attribute.
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
This class represents the atomic memcpy intrinsic i.e.
an instruction that atomically reads a memory location, combines it with another value,...
@ Min
*p = old <signed v ? old : v
@ UIncWrap
Increment one up to a maximum value.
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
@ UMax
*p = old >unsigned v ? old : v
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
@ UDecWrap
Decrement one until a minimum value or zero.
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute > > Attrs)
Create an AttributeList with the specified parameters in it.
AttributeSet getRetAttrs() const
The attributes for the ret value are returned.
bool hasFnAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the function.
bool getValueAsBool() const
Return the attribute's value as a boolean.
LLVM Basic Block Representation.
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool isEntryBlock() const
Return true if this is the entry block of the containing function.
const Function * getParent() const
Return the enclosing method, or null if none.
const Instruction * getFirstNonPHIOrDbg(bool SkipPseudoOp=true) const
Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
const Instruction & back() const
This class represents a no-op cast from one type to another.
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
size_type size() const
size - Returns the number of bits in this bitvector.
The address of a basic block.
Conditional or Unconditional Branch instruction.
Analysis providing branch probability information.
BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get an edge's probability, relative to other out-edges of the Src.
bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const
Test if an edge is hot relative to other out-edges of the Src.
static uint32_t getDenominator()
static BranchProbability getOne()
uint32_t getNumerator() const
uint64_t scale(uint64_t Num) const
Scale a large integer.
BranchProbability getCompl() const
static BranchProbability getZero()
static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Value * getCalledOperand() const
Value * getArgOperand(unsigned i) const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
bool isConvergent() const
Determine if the invoke is convergent.
FunctionType * getFunctionType() const
Intrinsic::ID getIntrinsicID() const
Returns the intrinsic ID of the intrinsic called or Intrinsic::not_intrinsic if the called function i...
unsigned arg_size() const
AttributeList getAttributes() const
Return the parameter attributes for this call.
CallBr instruction, tracking function calls that may not return control but instead transfer it to a ...
This class represents a function call, abstracting a target machine's calling convention.
This class is the base class for the comparison instructions.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
ConstantDataSequential - A vector or array constant whose element type is a simple 1/2/4/8-byte integ...
A constant value that is initialized with an expression using other constant values.
static Constant * getBitCast(Constant *C, Type *Ty, bool OnlyIfReduced=false)
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
static ConstantInt * getTrue(LLVMContext &Context)
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
static ConstantInt * getFalse(LLVMContext &Context)
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
const APInt & getValue() const
Return the constant as an APInt value reference.
This class represents a range of values.
APInt getUnsignedMin() const
Return the smallest unsigned value contained in the ConstantRange.
bool isFullSet() const
Return true if this set contains all of the elements possible for this data-type.
bool isEmptySet() const
Return true if this set contains no members.
bool isUpperWrapped() const
Return true if the exclusive upper bound wraps around the unsigned domain.
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
uint64_t getZExtValue() const
Constant Vector Declarations.
This is an important base class in LLVM.
This is the common base class for constrained floating point intrinsics.
std::optional< fp::ExceptionBehavior > getExceptionBehavior() const
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool fragmentsOverlap(const FragmentInfo &A, const FragmentInfo &B)
Check if fragments overlap between a pair of FragmentInfos.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static std::optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
uint64_t getNumLocationOperands() const
Return the number of unique location operands referred to (via DW_OP_LLVM_arg) in this expression; th...
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Base class for variables.
std::optional< uint64_t > getSizeInBits() const
Determines the size of the variable's type.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
unsigned getAllocaAddrSpace() const
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
This represents the llvm.dbg.label instruction.
DILabel * getLabel() const
Records a position in IR for a source label (DILabel).
Base class for non-instruction debug metadata records that have positions within IR.
DebugLoc getDebugLoc() const
This represents the llvm.dbg.value instruction.
iterator_range< location_op_iterator > getValues() const
DILocalVariable * getVariable() const
DIExpression * getExpression() const
bool isKillLocation() const
Record of a variable value-assignment, aka a non instruction representation of the dbg....
LocationType getType() const
DIExpression * getExpression() const
Value * getVariableLocationOp(unsigned OpIdx) const
DILocalVariable * getVariable() const
iterator_range< location_op_iterator > location_ops() const
Get the locations corresponding to the variable referenced by the debug info intrinsic.
DILocation * getInlinedAt() const
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
static constexpr ElementCount getFixed(ScalarTy MinVal)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
constexpr bool isScalar() const
Exactly one element.
Class representing an expression and its matching format.
This instruction compares its operands according to the predicate given to the constructor.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
bool allowReassoc() const
Flag queries.
An instruction for ordering other memory operations.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
This class represents a freeze function that returns random concrete value if an operand is either a ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
BranchProbabilityInfo * BPI
Register CreateRegs(const Value *V)
SmallPtrSet< const DbgVariableRecord *, 8 > PreprocessedDVRDeclares
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineBasicBlock * MBB
MBB - The current block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
unsigned ExceptionSelectorVirtReg
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
Class to represent function types.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Type * getParamType(unsigned i) const
Parameter type accessors.
Type * getReturnType() const
Data structure describing the variable locations in a function.
const BasicBlock & getEntryBlock() const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Constant * getPersonalityFn() const
Get the personality function associated with this function.
AttributeList getAttributes() const
Return the attribute list for this Function.
bool isIntrinsic() const
isIntrinsic - Returns true if the function's name starts with "llvm.".
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Garbage collection metadata for a single function.
void addStackRoot(int Num, const Constant *Metadata)
addStackRoot - Registers a root that lives on the stack.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
static StringRef dropLLVMManglingEscape(StringRef Name)
If the given string begins with the GlobalValue name mangling escape character '\1',...
bool hasDLLImportStorageClass() const
Module * getParent()
Get the module that this global value is contained inside of...
This instruction compares its operands according to the predicate given to the constructor.
Indirect Branch Instruction.
This instruction inserts a struct field of array element value into an aggregate value.
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
const BasicBlock * getParent() const
FastMathFlags getFastMathFlags() const LLVM_READONLY
Convenience function for getting all the fast-math flags, which must be an operator which supports th...
AAMDNodes getAAMetadata() const
Returns the AA metadata for this instruction.
@ MIN_INT_BITS
Minimum number of bits that can be specified.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
The landingpad instruction holds all of the information necessary to generate correct exception handl...
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateFrameAllocSymbol(const Twine &FuncName, unsigned Idx)
Gets a symbol that will be defined to the final stack offset of a local variable after codegen.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
uint64_t getScalarSizeInBits() const
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool bitsGE(MVT VT) const
Return true if this has no less bits than VT.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
bool isEHPad() const
Returns true if the block is a landing pad.
void setIsEHCatchretTarget(bool V=true)
Indicates if this is a target block of a catchret.
void setIsCleanupFuncletEntry(bool V=true)
Indicates if this is the entry block of a cleanup funclet.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
succ_iterator succ_begin()
std::vector< MachineBasicBlock * >::iterator succ_iterator
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
void setIsImmutableObjectIndex(int ObjectIdx, bool IsImmutable)
Marks the immutability of an object.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasPatchPoint(bool s=true)
void setHasStackMap(bool s=true)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
int getStackProtectorIndex() const
Return the index for the stack protector object.
void setStackProtectorIndex(int I)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
void setFunctionContextIndex(int I)
Description of the location of a variable whose Address is valid and unchanging during function execu...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
void setCallsUnwindInit(bool b)
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
void setCallSiteBeginLabel(MCSymbol *BeginLabel, unsigned Site)
Map the begin label for a call site.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void setHasEHCatchret(bool V)
void setCallsEHReturn(bool b)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
auto getInStackSlotVariableDbgInfo()
Returns the collection of variables for which we have debug info and that have been assigned a stack ...
void addCodeViewAnnotation(MCSymbol *Label, MDNode *MD)
Record annotations associated with a particular label.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
const MachineBasicBlock & front() const
bool hasEHFunclets() const
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void erase(iterator MBBI)
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
This class contains meta information specific to a module.
const MCContext & getContext() const
const Module * getModule() const
void setCurrentCallSite(unsigned Site)
Set the call site currently being processed.
unsigned getCurrentCallSite()
Get the call site currently being processed, if any.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ArrayRef< std::pair< MCRegister, Register > > liveins() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool contains(const KeyT &Key) const
std::pair< iterator, bool > try_emplace(const KeyT &Key, Ts &&...Args)
Representation for a specific memory location.
static MemoryLocation getAfter(const Value *Ptr, const AAMDNodes &AATags=AAMDNodes())
Return a location that may access any location after Ptr, while remaining within the underlying objec...
A Module instance is used to store all the information related to an LLVM module.
Metadata * getModuleFlag(StringRef Key) const
Return the corresponding value if Key appears in module flags, otherwise return null.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Resume the propagation of an exception.
Return a value (possibly void), from a function.
Holds the information from a dbg_label node through SDISel.
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
void addDanglingDebugInfo(SmallVectorImpl< Value * > &Values, DILocalVariable *Var, DIExpression *Expr, bool IsVariadic, DebugLoc DL, unsigned Order)
Register a dbg_value which relies on a Value which we have not yet seen.
void visitDbgInfo(const Instruction &I)
void clearDanglingDebugInfo()
Clear the dangling debug information map.
void clear()
Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuilder obje...
void visitBitTestHeader(SwitchCG::BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests"
void LowerStatepoint(const GCStatepointInst &I, const BasicBlock *EHPadBB=nullptr)
std::unique_ptr< SDAGSwitchLowering > SL
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
bool HasTailCall
This is set to true if a call in the current block has been translated as a tail call.
bool ShouldEmitAsBranches(const std::vector< SwitchCG::CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
void LowerDeoptimizeCall(const CallInst *CI)
void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB)
SwiftErrorValueTracking & SwiftError
Information about the swifterror values used throughout the function.
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo....
void CopyValueToVirtualRegister(const Value *V, unsigned Reg, ISD::NodeType ExtendType=ISD::ANY_EXTEND)
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
Map a landing pad to the call site indexes.
void handleDebugDeclare(Value *Address, DILocalVariable *Variable, DIExpression *Expression, DebugLoc DL)
void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
bool shouldKeepJumpConditionsTogether(const FunctionLoweringInfo &FuncInfo, const BranchInst &I, Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs, TargetLoweringBase::CondMergingParams Params) const
void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, bool IsMustTailCall, const BasicBlock *EHPadBB=nullptr)
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
void init(GCFunctionInfo *gfi, AAResults *AA, AssumptionCache *AC, const TargetLibraryInfo *li)
DenseMap< const Constant *, unsigned > ConstantsOut
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, AttributeSet RetAttrs, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
void salvageUnresolvedDbgValue(const Value *V, DanglingDebugInfo &DDI)
For the given dangling debuginfo record, perform last-ditch efforts to resolve the debuginfo to somet...
SmallVector< SDValue, 8 > PendingLoads
Loads are not emitted to the program immediately.
GCFunctionInfo * GFI
Garbage collection metadata for the function.
SDValue getRoot()
Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) items.
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block,...
DebugLoc getCurDebugLoc() const
void resolveOrClearDbgInfo()
Evict any dangling debug information, attempting to salvage it first.
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
SDValue getMemoryRoot()
Return the current virtual root of the Selection DAG, flushing any PendingLoad items.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
If we saw an earlier dbg_value referring to V, generate the debug data structures now that we've seen...
SDLoc getCurSDLoc() const
void visit(const Instruction &I)
void dropDanglingDebugInfo(const DILocalVariable *Variable, const DIExpression *Expr)
If we have dangling debug info that describes Variable, or an overlapping part of variable considerin...
SDValue getCopyFromRegs(const Value *V, Type *Ty)
If there was virtual register allocated for the value V emit CopyFromReg of the specified type Ty.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it,...
void handleKillDebugValue(DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order)
Create a record for a kill location debug intrinsic.
void visitJumpTable(SwitchCG::JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
void visitJumpTableHeader(SwitchCG::JumpTable &JT, SwitchCG::JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void LowerDeoptimizingReturn()
FunctionLoweringInfo & FuncInfo
Information about the function as a whole.
void setValue(const Value *V, SDValue NewN)
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
const TargetLibraryInfo * LibInfo
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
bool handleDebugValue(ArrayRef< const Value * > Values, DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order, bool IsVariadic)
For a given list of Values, attempt to create and record a SDDbgValue in the SelectionDAG.
SDValue getControlRoot()
Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports (...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
When an MBB was split during scheduling, update the references that need to refer to the last resulti...
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
std::unique_ptr< FunctionLoweringInfo > FuncInfo
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
const TargetLowering * TLI
virtual void emitFunctionEntryCode()
SwiftErrorValueTracking * SwiftError
std::unique_ptr< SelectionDAGBuilder > SDB
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a memcmp/bcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const
Emit target-specific code that performs a strcpy or stpcpy, in cases where that is faster than a libc...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memchr, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a strcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const
virtual SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const
Help to insert SDNodeFlags automatically in transforming.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending ...
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
BlockFrequencyInfo * getBFI() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
bool shouldOptForSize() const
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
const DataLayout & getDataLayout() const
ProfileSummaryInfo * getPSI() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
const SelectionDAGTargetInfo & getSelectionDAGInfo() const
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const FunctionVarLocs * getFunctionVarLocs() const
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr...
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
void addPCSections(const SDNode *Node, MDNode *MD)
Set PCSections to be associated with Node.
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue getSetCCVP(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL)
Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an ...
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void swap(SmallVectorImpl &RHS)
void push_back(const T &Elt)
pointer data()
Return a pointer to the vector's buffer, even if empty().
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Encapsulates all of the information needed to generate a stack protector check, and signals to isel w...
MachineBasicBlock * getSuccessMBB()
MachineBasicBlock * getFailureMBB()
void clear()
Clear the memory usage of this object.
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
TypeSize getElementOffset(unsigned Idx) const
Class to represent struct types.
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register)
Set the swifterror virtual register in the VRegDefMap for this basic block.
Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a use of a swifterror by an instruction.
Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a def of a swifterror by an instruction.
const Value * getFunctionArg() const
Get the (unique) function argument that was marked swifterror, or nullptr if this function has no swi...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
bool hasOptimizedCodeGen(LibFunc F) const
Tests if the function is both available and a candidate for optimized code generation.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
void setAttributes(const CallBase *Call, unsigned ArgIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes.
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
EVT getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const
Returns true if the index type for a masked gather/scatter requires extending.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales.
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const
Certain targets have context sensitive alignment requirements, where one type has the alignment requi...
virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
virtual bool shouldExpandCttzElements(EVT VT) const
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
std::vector< ArgListEntry > ArgListTy
bool isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const
Return true if it is beneficial to expand an @llvm.powi.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual MVT getVPExplicitVectorLengthTy() const
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool supportKCFIBundles() const
Return true if the target supports kcfi operand bundles.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
std::vector< AsmOperandInfo > AsmOperandInfoVector
SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const
Expand check for floating point class.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
Target-specific splitting of values into parts that fit a register storing a legal type.
virtual SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
Target-specific combining of register parts into its original value.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array,...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const
Return a TargetTransformInfo for a given function.
CodeModel::Model getCodeModel() const
Returns the code model.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fp-contract=xxx option.
unsigned getID() const
Return the register class ID number.
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isPS() const
Tests whether the target is the PS4 or PS5 platform.
bool isWasm() const
Tests whether the target is wasm (32- and 64-bit).
bool isAArch64() const
Tests whether the target is AArch64 (little and big endian).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isPointerTy() const
True if this is an instance of PointerType.
static IntegerType * getInt1Ty(LLVMContext &C)
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
TypeID
Definitions of all of the base types for the Type system.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static Type * getVoidTy(LLVMContext &C)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
bool isTokenTy() const
Return true if this is 'token'.
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
bool isVoidTy() const
Return true if this is 'void'.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
This function has undefined behavior.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
This class represents the va_arg llvm instruction, which returns an argument of the specified type gi...
CmpInst::Predicate getPredicate() const
This is the common base class for vector predication intrinsics.
static std::optional< unsigned > getVectorLengthParamPos(Intrinsic::ID IntrinsicID)
MaybeAlign getPointerAlignment() const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
LLVMContext & getContext() const
All values hold a context through their type.
StringRef getName() const
Return a constant reference to the value's name.
Base class of all SIMD vector types.
Type * getElementType() const
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ RESET_FPENV
Set floating-point environment to default state.
@ ADD
Simple integer binary arithmetic operators.
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ SET_ROUNDING
Set rounding mode.
@ SIGN_EXTEND
Conversion operators.
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
@ BR
Control flow instructions. These all have token chains.
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SSUBO
Same for subtraction.
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the same...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ BRCOND
BRCOND - Conditional branch.
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the sa...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool match(Val *V, const Pattern &P)
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
OneUse_match< T > m_OneUse(const T &SubPattern)
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
VScaleVal_match m_VScale()
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
BinaryOp_match< cst_pred_ty< is_all_ones >, ValTy, Instruction::Xor, true > m_Not(const ValTy &V)
Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
std::vector< CaseCluster > CaseClusterVector
void sortAndRangeify(CaseClusterVector &Clusters)
Sort Clusters and merge adjacent cases.
CaseClusterVector::iterator CaseClusterIt
std::pair< JumpTableHeader, JumpTable > JumpTableBlock
@ CC_Range
A cluster of adjacent case labels with the same destination, or just one case.
@ CC_JumpTable
A cluster of cases suitable for jump table lowering.
@ CC_BitTests
A cluster of cases suitable for bit test lowering.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
ExceptionBehavior
Exception behavior used for floating point operations.
@ ebStrict
This corresponds to "fpexcept.strict".
@ ebMayTrap
This corresponds to "fpexcept.maytrap".
@ ebIgnore
This corresponds to "fpexcept.ignore".
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
int popcount(T Value) noexcept
Count the number of set bits in a value.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isOnlyUsedInZeroEqualityComparison(const Instruction *CxtI)
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
void diagnoseDontCall(const CallInst &CI)
auto successors(const MachineBasicBlock *BB)
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Value * GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, const DataLayout &DL, bool AllowNonInbounds=true)
Analyze the specified pointer to see if it can be expressed as a base pointer plus a constant offset.
gep_type_iterator gep_type_end(const User *GEP)
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
@ SPF_ABS
Floating point maxnum.
@ SPF_NABS
Absolute value.
@ SPF_FMAXNUM
Floating point minnum.
@ SPF_UMIN
Signed minimum.
@ SPF_UMAX
Signed maximum.
@ SPF_SMAX
Unsigned minimum.
@ SPF_FMINNUM
Unsigned maximum.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
detail::zippy< detail::zip_first, T, U, Args... > zip_first(T &&t, U &&u, Args &&...args)
zip iterator that, for the sake of efficiency, assumes the first iteratee to be the shortest.
void sort(IteratorTy Start, IteratorTy End)
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Value * salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps, SmallVectorImpl< uint64_t > &Ops, SmallVectorImpl< Value * > &AdditionalValues)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Global
Append to llvm.global_dtors.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to getUnderlyingObject except that it can look through phi and select instruct...
bool isAssignmentTrackingEnabled(const Module &M)
Return true if assignment tracking is enabled for module M.
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
@ UMin
Unsigned integer min implemented in terms of select(cmp()).
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ And
Bitwise or logical AND of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
@ SPNB_RETURNS_NAN
NaN behavior not applicable.
@ SPNB_RETURNS_OTHER
Given one NaN input, returns the NaN.
@ SPNB_RETURNS_ANY
Given one NaN input, returns the non-NaN.
DWARFExpression::Operation Op
ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC)
getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, return the equivalent code if w...
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
std::optional< RoundingMode > convertStrToRoundingMode(StringRef)
Returns a valid RoundingMode enumerator when given a string that is valid as input in constrained int...
gep_type_iterator gep_type_begin(const User *GEP)
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
bool all_equal(std::initializer_list< T > Values)
Returns true if all Values in the initializer lists are equal or the list.
Constant * ConstantFoldLoadFromConstPtr(Constant *C, Type *Ty, APInt Offset, const DataLayout &DL)
Return the value that a load from C with offset Offset would produce if it is constant and determinab...
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
unsigned succ_size(const MachineBasicBlock *BB)
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
uint64_t getScalarStoreSize() const
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isScalableVT() const
Return true if the type is a scalable type.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
EVT changeVectorElementType(EVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setPointerAddrSpace(unsigned AS)
void setOrigAlign(Align A)
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber/label.
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This struct represents the registers (physical or virtual) that a particular set of values is assigne...
SmallVector< unsigned, 4 > Regs
This list holds the registers assigned to the values.
SmallVector< unsigned, 4 > RegCount
This list holds the number of registers for each value.
bool isABIMangled() const
SmallVector< EVT, 4 > ValueVTs
The value types of the values, which may not be legal, and may need be promoted or synthesized from o...
SmallVector< std::pair< unsigned, TypeSize >, 4 > getRegsAndSizes() const
Return a list of registers and their sizes.
void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
Add this value to the specified inlineasm node operand list.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr) const
Emit a series of CopyFromReg nodes that copies from this value and returns the result as a ValueVTs v...
SmallVector< MVT, 4 > RegVTs
The value types of the registers.
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
Emit a series of CopyToReg nodes that copies the specified value into the registers specified by this...
std::optional< CallingConv::ID > CallConv
Records if this value needs to be treated in an ABI dependant manner, different to normal type legali...
bool occupiesMultipleRegs() const
Check if the total RegCount is greater than one.
These are IR-level optimization flags that may be propagated to SDNodes.
void copyFMF(const FPMathOperator &FPMO)
Propagate the fast-math-flags from an IR FPMathOperator.
bool hasAllowReassociation() const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
A MapVector that performs no allocations if smaller than a certain size.
MachineBasicBlock * Default
BranchProbability DefaultProb
MachineBasicBlock * Parent
bool FallthroughUnreachable
MachineBasicBlock * ThisBB
This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...
BranchProbability TrueProb
BranchProbability FalseProb
MachineBasicBlock * TrueBB
MachineBasicBlock * FalseBB
SDLoc DL
The debug location of the instruction this CaseBlock was produced from.
A cluster of case labels.
static CaseCluster range(const ConstantInt *Low, const ConstantInt *High, MachineBasicBlock *MBB, BranchProbability Prob)
This contains information for each constraint that we are lowering.
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setConvergent(bool Value=true)
CallLoweringInfo & setCFIType(const ConstantInt *Type)
SmallVector< ISD::InputArg, 32 > Ins
bool IsPostTypeLegalization
SmallVector< SDValue, 4 > InVals
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setIsPreallocated(bool Value=true)
CallLoweringInfo & setConvergenceControlToken(SDValue Token)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setDiscardResult(bool Value=true)
void addIPToStateRange(const InvokeInst *II, MCSymbol *InvokeBegin, MCSymbol *InvokeEnd)