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ARMLoadStoreOptimizer.cpp
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1 //===- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file contains a pass that performs load / store related peephole
10 /// optimizations. This pass should be run after register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARM.h"
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
22 #include "Utils/ARMBaseInfo.h"
23 #include "llvm/ADT/ArrayRef.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/DenseSet.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallSet.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/Statistic.h"
49 #include "llvm/IR/DataLayout.h"
50 #include "llvm/IR/DebugLoc.h"
51 #include "llvm/IR/DerivedTypes.h"
52 #include "llvm/IR/Function.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/InitializePasses.h"
55 #include "llvm/MC/MCInstrDesc.h"
56 #include "llvm/Pass.h"
57 #include "llvm/Support/Allocator.h"
59 #include "llvm/Support/Debug.h"
62 #include <algorithm>
63 #include <cassert>
64 #include <cstddef>
65 #include <cstdlib>
66 #include <iterator>
67 #include <limits>
68 #include <utility>
69 
70 using namespace llvm;
71 
72 #define DEBUG_TYPE "arm-ldst-opt"
73 
74 STATISTIC(NumLDMGened , "Number of ldm instructions generated");
75 STATISTIC(NumSTMGened , "Number of stm instructions generated");
76 STATISTIC(NumVLDMGened, "Number of vldm instructions generated");
77 STATISTIC(NumVSTMGened, "Number of vstm instructions generated");
78 STATISTIC(NumLdStMoved, "Number of load / store instructions moved");
79 STATISTIC(NumLDRDFormed,"Number of ldrd created before allocation");
80 STATISTIC(NumSTRDFormed,"Number of strd created before allocation");
81 STATISTIC(NumLDRD2LDM, "Number of ldrd instructions turned back into ldm");
82 STATISTIC(NumSTRD2STM, "Number of strd instructions turned back into stm");
83 STATISTIC(NumLDRD2LDR, "Number of ldrd instructions turned back into ldr's");
84 STATISTIC(NumSTRD2STR, "Number of strd instructions turned back into str's");
85 
86 /// This switch disables formation of double/multi instructions that could
87 /// potentially lead to (new) alignment traps even with CCR.UNALIGN_TRP
88 /// disabled. This can be used to create libraries that are robust even when
89 /// users provoke undefined behaviour by supplying misaligned pointers.
90 /// \see mayCombineMisaligned()
91 static cl::opt<bool>
92 AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
93  cl::init(false), cl::desc("Be more conservative in ARM load/store opt"));
94 
95 #define ARM_LOAD_STORE_OPT_NAME "ARM load / store optimization pass"
96 
97 namespace {
98 
99  /// Post- register allocation pass the combine load / store instructions to
100  /// form ldm / stm instructions.
101  struct ARMLoadStoreOpt : public MachineFunctionPass {
102  static char ID;
103 
104  const MachineFunction *MF;
105  const TargetInstrInfo *TII;
106  const TargetRegisterInfo *TRI;
107  const ARMSubtarget *STI;
108  const TargetLowering *TL;
109  ARMFunctionInfo *AFI;
110  LivePhysRegs LiveRegs;
111  RegisterClassInfo RegClassInfo;
113  bool LiveRegsValid;
114  bool RegClassInfoValid;
115  bool isThumb1, isThumb2;
116 
117  ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
118 
119  bool runOnMachineFunction(MachineFunction &Fn) override;
120 
121  MachineFunctionProperties getRequiredProperties() const override {
124  }
125 
126  StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; }
127 
128  private:
129  /// A set of load/store MachineInstrs with same base register sorted by
130  /// offset.
131  struct MemOpQueueEntry {
132  MachineInstr *MI;
133  int Offset; ///< Load/Store offset.
134  unsigned Position; ///< Position as counted from end of basic block.
135 
136  MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
137  : MI(&MI), Offset(Offset), Position(Position) {}
138  };
139  using MemOpQueue = SmallVector<MemOpQueueEntry, 8>;
140 
141  /// A set of MachineInstrs that fulfill (nearly all) conditions to get
142  /// merged into a LDM/STM.
143  struct MergeCandidate {
144  /// List of instructions ordered by load/store offset.
146 
147  /// Index in Instrs of the instruction being latest in the schedule.
148  unsigned LatestMIIdx;
149 
150  /// Index in Instrs of the instruction being earliest in the schedule.
151  unsigned EarliestMIIdx;
152 
153  /// Index into the basic block where the merged instruction will be
154  /// inserted. (See MemOpQueueEntry.Position)
155  unsigned InsertPos;
156 
157  /// Whether the instructions can be merged into a ldm/stm instruction.
158  bool CanMergeToLSMulti;
159 
160  /// Whether the instructions can be merged into a ldrd/strd instruction.
161  bool CanMergeToLSDouble;
162  };
165  SmallVector<MachineInstr*,4> MergeBaseCandidates;
166 
167  void moveLiveRegsBefore(const MachineBasicBlock &MBB,
169  unsigned findFreeReg(const TargetRegisterClass &RegClass);
170  void UpdateBaseRegUses(MachineBasicBlock &MBB,
172  unsigned Base, unsigned WordOffset,
173  ARMCC::CondCodes Pred, unsigned PredReg);
174  MachineInstr *CreateLoadStoreMulti(
176  int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
177  ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
178  ArrayRef<std::pair<unsigned, bool>> Regs,
179  ArrayRef<MachineInstr*> Instrs);
180  MachineInstr *CreateLoadStoreDouble(
182  int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
183  ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
184  ArrayRef<std::pair<unsigned, bool>> Regs,
185  ArrayRef<MachineInstr*> Instrs) const;
186  void FormCandidates(const MemOpQueue &MemOps);
187  MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
188  bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
190  bool MergeBaseUpdateLoadStore(MachineInstr *MI);
191  bool MergeBaseUpdateLSMultiple(MachineInstr *MI);
192  bool MergeBaseUpdateLSDouble(MachineInstr &MI) const;
193  bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
194  bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
195  bool CombineMovBx(MachineBasicBlock &MBB);
196  };
197 
198 } // end anonymous namespace
199 
200 char ARMLoadStoreOpt::ID = 0;
201 
202 INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false,
203  false)
204 
205 static bool definesCPSR(const MachineInstr &MI) {
206  for (const auto &MO : MI.operands()) {
207  if (!MO.isReg())
208  continue;
209  if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
210  // If the instruction has live CPSR def, then it's not safe to fold it
211  // into load / store.
212  return true;
213  }
214 
215  return false;
216 }
217 
218 static int getMemoryOpOffset(const MachineInstr &MI) {
219  unsigned Opcode = MI.getOpcode();
220  bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
221  unsigned NumOperands = MI.getDesc().getNumOperands();
222  unsigned OffField = MI.getOperand(NumOperands - 3).getImm();
223 
224  if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
225  Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
226  Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
227  Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
228  return OffField;
229 
230  // Thumb1 immediate offsets are scaled by 4
231  if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||
232  Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
233  return OffField * 4;
234 
235  int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField)
236  : ARM_AM::getAM5Offset(OffField) * 4;
237  ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField)
238  : ARM_AM::getAM5Op(OffField);
239 
240  if (Op == ARM_AM::sub)
241  return -Offset;
242 
243  return Offset;
244 }
245 
247  return MI.getOperand(1);
248 }
249 
251  return MI.getOperand(0);
252 }
253 
254 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {
255  switch (Opcode) {
256  default: llvm_unreachable("Unhandled opcode!");
257  case ARM::LDRi12:
258  ++NumLDMGened;
259  switch (Mode) {
260  default: llvm_unreachable("Unhandled submode!");
261  case ARM_AM::ia: return ARM::LDMIA;
262  case ARM_AM::da: return ARM::LDMDA;
263  case ARM_AM::db: return ARM::LDMDB;
264  case ARM_AM::ib: return ARM::LDMIB;
265  }
266  case ARM::STRi12:
267  ++NumSTMGened;
268  switch (Mode) {
269  default: llvm_unreachable("Unhandled submode!");
270  case ARM_AM::ia: return ARM::STMIA;
271  case ARM_AM::da: return ARM::STMDA;
272  case ARM_AM::db: return ARM::STMDB;
273  case ARM_AM::ib: return ARM::STMIB;
274  }
275  case ARM::tLDRi:
276  case ARM::tLDRspi:
277  // tLDMIA is writeback-only - unless the base register is in the input
278  // reglist.
279  ++NumLDMGened;
280  switch (Mode) {
281  default: llvm_unreachable("Unhandled submode!");
282  case ARM_AM::ia: return ARM::tLDMIA;
283  }
284  case ARM::tSTRi:
285  case ARM::tSTRspi:
286  // There is no non-writeback tSTMIA either.
287  ++NumSTMGened;
288  switch (Mode) {
289  default: llvm_unreachable("Unhandled submode!");
290  case ARM_AM::ia: return ARM::tSTMIA_UPD;
291  }
292  case ARM::t2LDRi8:
293  case ARM::t2LDRi12:
294  ++NumLDMGened;
295  switch (Mode) {
296  default: llvm_unreachable("Unhandled submode!");
297  case ARM_AM::ia: return ARM::t2LDMIA;
298  case ARM_AM::db: return ARM::t2LDMDB;
299  }
300  case ARM::t2STRi8:
301  case ARM::t2STRi12:
302  ++NumSTMGened;
303  switch (Mode) {
304  default: llvm_unreachable("Unhandled submode!");
305  case ARM_AM::ia: return ARM::t2STMIA;
306  case ARM_AM::db: return ARM::t2STMDB;
307  }
308  case ARM::VLDRS:
309  ++NumVLDMGened;
310  switch (Mode) {
311  default: llvm_unreachable("Unhandled submode!");
312  case ARM_AM::ia: return ARM::VLDMSIA;
313  case ARM_AM::db: return 0; // Only VLDMSDB_UPD exists.
314  }
315  case ARM::VSTRS:
316  ++NumVSTMGened;
317  switch (Mode) {
318  default: llvm_unreachable("Unhandled submode!");
319  case ARM_AM::ia: return ARM::VSTMSIA;
320  case ARM_AM::db: return 0; // Only VSTMSDB_UPD exists.
321  }
322  case ARM::VLDRD:
323  ++NumVLDMGened;
324  switch (Mode) {
325  default: llvm_unreachable("Unhandled submode!");
326  case ARM_AM::ia: return ARM::VLDMDIA;
327  case ARM_AM::db: return 0; // Only VLDMDDB_UPD exists.
328  }
329  case ARM::VSTRD:
330  ++NumVSTMGened;
331  switch (Mode) {
332  default: llvm_unreachable("Unhandled submode!");
333  case ARM_AM::ia: return ARM::VSTMDIA;
334  case ARM_AM::db: return 0; // Only VSTMDDB_UPD exists.
335  }
336  }
337 }
338 
340  switch (Opcode) {
341  default: llvm_unreachable("Unhandled opcode!");
342  case ARM::LDMIA_RET:
343  case ARM::LDMIA:
344  case ARM::LDMIA_UPD:
345  case ARM::STMIA:
346  case ARM::STMIA_UPD:
347  case ARM::tLDMIA:
348  case ARM::tLDMIA_UPD:
349  case ARM::tSTMIA_UPD:
350  case ARM::t2LDMIA_RET:
351  case ARM::t2LDMIA:
352  case ARM::t2LDMIA_UPD:
353  case ARM::t2STMIA:
354  case ARM::t2STMIA_UPD:
355  case ARM::VLDMSIA:
356  case ARM::VLDMSIA_UPD:
357  case ARM::VSTMSIA:
358  case ARM::VSTMSIA_UPD:
359  case ARM::VLDMDIA:
360  case ARM::VLDMDIA_UPD:
361  case ARM::VSTMDIA:
362  case ARM::VSTMDIA_UPD:
363  return ARM_AM::ia;
364 
365  case ARM::LDMDA:
366  case ARM::LDMDA_UPD:
367  case ARM::STMDA:
368  case ARM::STMDA_UPD:
369  return ARM_AM::da;
370 
371  case ARM::LDMDB:
372  case ARM::LDMDB_UPD:
373  case ARM::STMDB:
374  case ARM::STMDB_UPD:
375  case ARM::t2LDMDB:
376  case ARM::t2LDMDB_UPD:
377  case ARM::t2STMDB:
378  case ARM::t2STMDB_UPD:
379  case ARM::VLDMSDB_UPD:
380  case ARM::VSTMSDB_UPD:
381  case ARM::VLDMDDB_UPD:
382  case ARM::VSTMDDB_UPD:
383  return ARM_AM::db;
384 
385  case ARM::LDMIB:
386  case ARM::LDMIB_UPD:
387  case ARM::STMIB:
388  case ARM::STMIB_UPD:
389  return ARM_AM::ib;
390  }
391 }
392 
393 static bool isT1i32Load(unsigned Opc) {
394  return Opc == ARM::tLDRi || Opc == ARM::tLDRspi;
395 }
396 
397 static bool isT2i32Load(unsigned Opc) {
398  return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
399 }
400 
401 static bool isi32Load(unsigned Opc) {
402  return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ;
403 }
404 
405 static bool isT1i32Store(unsigned Opc) {
406  return Opc == ARM::tSTRi || Opc == ARM::tSTRspi;
407 }
408 
409 static bool isT2i32Store(unsigned Opc) {
410  return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8;
411 }
412 
413 static bool isi32Store(unsigned Opc) {
414  return Opc == ARM::STRi12 || isT1i32Store(Opc) || isT2i32Store(Opc);
415 }
416 
417 static bool isLoadSingle(unsigned Opc) {
418  return isi32Load(Opc) || Opc == ARM::VLDRS || Opc == ARM::VLDRD;
419 }
420 
421 static unsigned getImmScale(unsigned Opc) {
422  switch (Opc) {
423  default: llvm_unreachable("Unhandled opcode!");
424  case ARM::tLDRi:
425  case ARM::tSTRi:
426  case ARM::tLDRspi:
427  case ARM::tSTRspi:
428  return 1;
429  case ARM::tLDRHi:
430  case ARM::tSTRHi:
431  return 2;
432  case ARM::tLDRBi:
433  case ARM::tSTRBi:
434  return 4;
435  }
436 }
437 
438 static unsigned getLSMultipleTransferSize(const MachineInstr *MI) {
439  switch (MI->getOpcode()) {
440  default: return 0;
441  case ARM::LDRi12:
442  case ARM::STRi12:
443  case ARM::tLDRi:
444  case ARM::tSTRi:
445  case ARM::tLDRspi:
446  case ARM::tSTRspi:
447  case ARM::t2LDRi8:
448  case ARM::t2LDRi12:
449  case ARM::t2STRi8:
450  case ARM::t2STRi12:
451  case ARM::VLDRS:
452  case ARM::VSTRS:
453  return 4;
454  case ARM::VLDRD:
455  case ARM::VSTRD:
456  return 8;
457  case ARM::LDMIA:
458  case ARM::LDMDA:
459  case ARM::LDMDB:
460  case ARM::LDMIB:
461  case ARM::STMIA:
462  case ARM::STMDA:
463  case ARM::STMDB:
464  case ARM::STMIB:
465  case ARM::tLDMIA:
466  case ARM::tLDMIA_UPD:
467  case ARM::tSTMIA_UPD:
468  case ARM::t2LDMIA:
469  case ARM::t2LDMDB:
470  case ARM::t2STMIA:
471  case ARM::t2STMDB:
472  case ARM::VLDMSIA:
473  case ARM::VSTMSIA:
474  return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4;
475  case ARM::VLDMDIA:
476  case ARM::VSTMDIA:
477  return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8;
478  }
479 }
480 
481 /// Update future uses of the base register with the offset introduced
482 /// due to writeback. This function only works on Thumb1.
483 void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
485  const DebugLoc &DL, unsigned Base,
486  unsigned WordOffset,
487  ARMCC::CondCodes Pred,
488  unsigned PredReg) {
489  assert(isThumb1 && "Can only update base register uses for Thumb1!");
490  // Start updating any instructions with immediate offsets. Insert a SUB before
491  // the first non-updateable instruction (if any).
492  for (; MBBI != MBB.end(); ++MBBI) {
493  bool InsertSub = false;
494  unsigned Opc = MBBI->getOpcode();
495 
496  if (MBBI->readsRegister(Base)) {
497  int Offset;
498  bool IsLoad =
499  Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi;
500  bool IsStore =
501  Opc == ARM::tSTRi || Opc == ARM::tSTRHi || Opc == ARM::tSTRBi;
502 
503  if (IsLoad || IsStore) {
504  // Loads and stores with immediate offsets can be updated, but only if
505  // the new offset isn't negative.
506  // The MachineOperand containing the offset immediate is the last one
507  // before predicates.
508  MachineOperand &MO =
509  MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
510  // The offsets are scaled by 1, 2 or 4 depending on the Opcode.
511  Offset = MO.getImm() - WordOffset * getImmScale(Opc);
512 
513  // If storing the base register, it needs to be reset first.
514  Register InstrSrcReg = getLoadStoreRegOp(*MBBI).getReg();
515 
516  if (Offset >= 0 && !(IsStore && InstrSrcReg == Base))
517  MO.setImm(Offset);
518  else
519  InsertSub = true;
520  } else if ((Opc == ARM::tSUBi8 || Opc == ARM::tADDi8) &&
521  !definesCPSR(*MBBI)) {
522  // SUBS/ADDS using this register, with a dead def of the CPSR.
523  // Merge it with the update; if the merged offset is too large,
524  // insert a new sub instead.
525  MachineOperand &MO =
526  MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
527  Offset = (Opc == ARM::tSUBi8) ?
528  MO.getImm() + WordOffset * 4 :
529  MO.getImm() - WordOffset * 4 ;
530  if (Offset >= 0 && TL->isLegalAddImmediate(Offset)) {
531  // FIXME: Swap ADDS<->SUBS if Offset < 0, erase instruction if
532  // Offset == 0.
533  MO.setImm(Offset);
534  // The base register has now been reset, so exit early.
535  return;
536  } else {
537  InsertSub = true;
538  }
539  } else {
540  // Can't update the instruction.
541  InsertSub = true;
542  }
543  } else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
544  // Since SUBS sets the condition flags, we can't place the base reset
545  // after an instruction that has a live CPSR def.
546  // The base register might also contain an argument for a function call.
547  InsertSub = true;
548  }
549 
550  if (InsertSub) {
551  // An instruction above couldn't be updated, so insert a sub.
552  BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
553  .add(t1CondCodeOp(true))
554  .addReg(Base)
555  .addImm(WordOffset * 4)
556  .addImm(Pred)
557  .addReg(PredReg);
558  return;
559  }
560 
561  if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base))
562  // Register got killed. Stop updating.
563  return;
564  }
565 
566  // End of block was reached.
567  if (MBB.succ_size() > 0) {
568  // FIXME: Because of a bug, live registers are sometimes missing from
569  // the successor blocks' live-in sets. This means we can't trust that
570  // information and *always* have to reset at the end of a block.
571  // See PR21029.
572  if (MBBI != MBB.end()) --MBBI;
573  BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
574  .add(t1CondCodeOp(true))
575  .addReg(Base)
576  .addImm(WordOffset * 4)
577  .addImm(Pred)
578  .addReg(PredReg);
579  }
580 }
581 
582 /// Return the first register of class \p RegClass that is not in \p Regs.
583 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
584  if (!RegClassInfoValid) {
585  RegClassInfo.runOnMachineFunction(*MF);
586  RegClassInfoValid = true;
587  }
588 
589  for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
590  if (!LiveRegs.contains(Reg))
591  return Reg;
592  return 0;
593 }
594 
595 /// Compute live registers just before instruction \p Before (in normal schedule
596 /// direction). Computes backwards so multiple queries in the same block must
597 /// come in reverse order.
598 void ARMLoadStoreOpt::moveLiveRegsBefore(const MachineBasicBlock &MBB,
600  // Initialize if we never queried in this block.
601  if (!LiveRegsValid) {
602  LiveRegs.init(*TRI);
603  LiveRegs.addLiveOuts(MBB);
604  LiveRegPos = MBB.end();
605  LiveRegsValid = true;
606  }
607  // Move backward just before the "Before" position.
608  while (LiveRegPos != Before) {
609  --LiveRegPos;
610  LiveRegs.stepBackward(*LiveRegPos);
611  }
612 }
613 
614 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
615  unsigned Reg) {
616  for (const std::pair<unsigned, bool> &R : Regs)
617  if (R.first == Reg)
618  return true;
619  return false;
620 }
621 
622 /// Create and insert a LDM or STM with Base as base register and registers in
623 /// Regs as the register operands that would be loaded / stored. It returns
624 /// true if the transformation is done.
625 MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(
627  int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
628  ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
629  ArrayRef<std::pair<unsigned, bool>> Regs,
630  ArrayRef<MachineInstr*> Instrs) {
631  unsigned NumRegs = Regs.size();
632  assert(NumRegs > 1);
633 
634  // For Thumb1 targets, it might be necessary to clobber the CPSR to merge.
635  // Compute liveness information for that register to make the decision.
636  bool SafeToClobberCPSR = !isThumb1 ||
637  (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
639 
640  bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
641 
642  // Exception: If the base register is in the input reglist, Thumb1 LDM is
643  // non-writeback.
644  // It's also not possible to merge an STR of the base register in Thumb1.
645  if (isThumb1 && ContainsReg(Regs, Base)) {
646  assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
647  if (Opcode == ARM::tLDRi)
648  Writeback = false;
649  else if (Opcode == ARM::tSTRi)
650  return nullptr;
651  }
652 
654  // VFP and Thumb2 do not support IB or DA modes. Thumb1 only supports IA.
655  bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
656  bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;
657 
658  if (Offset == 4 && haveIBAndDA) {
659  Mode = ARM_AM::ib;
660  } else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) {
661  Mode = ARM_AM::da;
662  } else if (Offset == -4 * (int)NumRegs && isNotVFP && !isThumb1) {
663  // VLDM/VSTM do not support DB mode without also updating the base reg.
664  Mode = ARM_AM::db;
665  } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {
666  // Check if this is a supported opcode before inserting instructions to
667  // calculate a new base register.
668  if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;
669 
670  // If starting offset isn't zero, insert a MI to materialize a new base.
671  // But only do so if it is cost effective, i.e. merging more than two
672  // loads / stores.
673  if (NumRegs <= 2)
674  return nullptr;
675 
676  // On Thumb1, it's not worth materializing a new base register without
677  // clobbering the CPSR (i.e. not using ADDS/SUBS).
678  if (!SafeToClobberCPSR)
679  return nullptr;
680 
681  unsigned NewBase;
682  if (isi32Load(Opcode)) {
683  // If it is a load, then just use one of the destination registers
684  // as the new base. Will no longer be writeback in Thumb1.
685  NewBase = Regs[NumRegs-1].first;
686  Writeback = false;
687  } else {
688  // Find a free register that we can use as scratch register.
689  moveLiveRegsBefore(MBB, InsertBefore);
690  // The merged instruction does not exist yet but will use several Regs if
691  // it is a Store.
692  if (!isLoadSingle(Opcode))
693  for (const std::pair<unsigned, bool> &R : Regs)
694  LiveRegs.addReg(R.first);
695 
696  NewBase = findFreeReg(isThumb1 ? ARM::tGPRRegClass : ARM::GPRRegClass);
697  if (NewBase == 0)
698  return nullptr;
699  }
700 
701  int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm
702  : ARM::t2ADDri)
703  : (isThumb1 && Base == ARM::SP)
704  ? ARM::tADDrSPi
705  : (isThumb1 && Offset < 8)
706  ? ARM::tADDi3
707  : isThumb1 ? ARM::tADDi8 : ARM::ADDri;
708 
709  if (Offset < 0) {
710  // FIXME: There are no Thumb1 load/store instructions with negative
711  // offsets. So the Base != ARM::SP might be unnecessary.
712  Offset = -Offset;
713  BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm
714  : ARM::t2SUBri)
715  : (isThumb1 && Offset < 8 && Base != ARM::SP)
716  ? ARM::tSUBi3
717  : isThumb1 ? ARM::tSUBi8 : ARM::SUBri;
718  }
719 
720  if (!TL->isLegalAddImmediate(Offset))
721  // FIXME: Try add with register operand?
722  return nullptr; // Probably not worth it then.
723 
724  // We can only append a kill flag to the add/sub input if the value is not
725  // used in the register list of the stm as well.
726  bool KillOldBase = BaseKill &&
727  (!isi32Store(Opcode) || !ContainsReg(Regs, Base));
728 
729  if (isThumb1) {
730  // Thumb1: depending on immediate size, use either
731  // ADDS NewBase, Base, #imm3
732  // or
733  // MOV NewBase, Base
734  // ADDS NewBase, #imm8.
735  if (Base != NewBase &&
736  (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) {
737  // Need to insert a MOV to the new base first.
738  if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&
739  !STI->hasV6Ops()) {
740  // thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr
741  if (Pred != ARMCC::AL)
742  return nullptr;
743  BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
744  .addReg(Base, getKillRegState(KillOldBase));
745  } else
746  BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
747  .addReg(Base, getKillRegState(KillOldBase))
748  .add(predOps(Pred, PredReg));
749 
750  // The following ADDS/SUBS becomes an update.
751  Base = NewBase;
752  KillOldBase = true;
753  }
754  if (BaseOpc == ARM::tADDrSPi) {
755  assert(Offset % 4 == 0 && "tADDrSPi offset is scaled by 4");
756  BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
757  .addReg(Base, getKillRegState(KillOldBase))
758  .addImm(Offset / 4)
759  .add(predOps(Pred, PredReg));
760  } else
761  BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
762  .add(t1CondCodeOp(true))
763  .addReg(Base, getKillRegState(KillOldBase))
764  .addImm(Offset)
765  .add(predOps(Pred, PredReg));
766  } else {
767  BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
768  .addReg(Base, getKillRegState(KillOldBase))
769  .addImm(Offset)
770  .add(predOps(Pred, PredReg))
771  .add(condCodeOp());
772  }
773  Base = NewBase;
774  BaseKill = true; // New base is always killed straight away.
775  }
776 
777  bool isDef = isLoadSingle(Opcode);
778 
779  // Get LS multiple opcode. Note that for Thumb1 this might be an opcode with
780  // base register writeback.
781  Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
782  if (!Opcode)
783  return nullptr;
784 
785  // Check if a Thumb1 LDM/STM merge is safe. This is the case if:
786  // - There is no writeback (LDM of base register),
787  // - the base register is killed by the merged instruction,
788  // - or it's safe to overwrite the condition flags, i.e. to insert a SUBS
789  // to reset the base register.
790  // Otherwise, don't merge.
791  // It's safe to return here since the code to materialize a new base register
792  // above is also conditional on SafeToClobberCPSR.
793  if (isThumb1 && !SafeToClobberCPSR && Writeback && !BaseKill)
794  return nullptr;
795 
797 
798  if (Writeback) {
799  assert(isThumb1 && "expected Writeback only inThumb1");
800  if (Opcode == ARM::tLDMIA) {
801  assert(!(ContainsReg(Regs, Base)) && "Thumb1 can't LDM ! with Base in Regs");
802  // Update tLDMIA with writeback if necessary.
803  Opcode = ARM::tLDMIA_UPD;
804  }
805 
806  MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
807 
808  // Thumb1: we might need to set base writeback when building the MI.
809  MIB.addReg(Base, getDefRegState(true))
810  .addReg(Base, getKillRegState(BaseKill));
811 
812  // The base isn't dead after a merged instruction with writeback.
813  // Insert a sub instruction after the newly formed instruction to reset.
814  if (!BaseKill)
815  UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
816  } else {
817  // No writeback, simply build the MachineInstr.
818  MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
819  MIB.addReg(Base, getKillRegState(BaseKill));
820  }
821 
822  MIB.addImm(Pred).addReg(PredReg);
823 
824  for (const std::pair<unsigned, bool> &R : Regs)
825  MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
826 
827  MIB.cloneMergedMemRefs(Instrs);
828 
829  return MIB.getInstr();
830 }
831 
832 MachineInstr *ARMLoadStoreOpt::CreateLoadStoreDouble(
834  int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
835  ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
836  ArrayRef<std::pair<unsigned, bool>> Regs,
837  ArrayRef<MachineInstr*> Instrs) const {
838  bool IsLoad = isi32Load(Opcode);
839  assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
840  unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8;
841 
842  assert(Regs.size() == 2);
843  MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
844  TII->get(LoadStoreOpcode));
845  if (IsLoad) {
846  MIB.addReg(Regs[0].first, RegState::Define)
847  .addReg(Regs[1].first, RegState::Define);
848  } else {
849  MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
850  .addReg(Regs[1].first, getKillRegState(Regs[1].second));
851  }
852  MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
853  MIB.cloneMergedMemRefs(Instrs);
854  return MIB.getInstr();
855 }
856 
857 /// Call MergeOps and update MemOps and merges accordingly on success.
858 MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
859  const MachineInstr *First = Cand.Instrs.front();
860  unsigned Opcode = First->getOpcode();
861  bool IsLoad = isLoadSingle(Opcode);
863  SmallVector<unsigned, 4> ImpDefs;
864  DenseSet<unsigned> KilledRegs;
865  DenseSet<unsigned> UsedRegs;
866  // Determine list of registers and list of implicit super-register defs.
867  for (const MachineInstr *MI : Cand.Instrs) {
868  const MachineOperand &MO = getLoadStoreRegOp(*MI);
869  Register Reg = MO.getReg();
870  bool IsKill = MO.isKill();
871  if (IsKill)
872  KilledRegs.insert(Reg);
873  Regs.push_back(std::make_pair(Reg, IsKill));
874  UsedRegs.insert(Reg);
875 
876  if (IsLoad) {
877  // Collect any implicit defs of super-registers, after merging we can't
878  // be sure anymore that we properly preserved these live ranges and must
879  // removed these implicit operands.
880  for (const MachineOperand &MO : MI->implicit_operands()) {
881  if (!MO.isReg() || !MO.isDef() || MO.isDead())
882  continue;
883  assert(MO.isImplicit());
884  Register DefReg = MO.getReg();
885 
886  if (is_contained(ImpDefs, DefReg))
887  continue;
888  // We can ignore cases where the super-reg is read and written.
889  if (MI->readsRegister(DefReg))
890  continue;
891  ImpDefs.push_back(DefReg);
892  }
893  }
894  }
895 
896  // Attempt the merge.
897  using iterator = MachineBasicBlock::iterator;
898 
899  MachineInstr *LatestMI = Cand.Instrs[Cand.LatestMIIdx];
900  iterator InsertBefore = std::next(iterator(LatestMI));
901  MachineBasicBlock &MBB = *LatestMI->getParent();
902  unsigned Offset = getMemoryOpOffset(*First);
903  Register Base = getLoadStoreBaseOp(*First).getReg();
904  bool BaseKill = LatestMI->killsRegister(Base);
905  Register PredReg;
906  ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
907  DebugLoc DL = First->getDebugLoc();
908  MachineInstr *Merged = nullptr;
909  if (Cand.CanMergeToLSDouble)
910  Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
911  Opcode, Pred, PredReg, DL, Regs,
912  Cand.Instrs);
913  if (!Merged && Cand.CanMergeToLSMulti)
914  Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
915  Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);
916  if (!Merged)
917  return nullptr;
918 
919  // Determine earliest instruction that will get removed. We then keep an
920  // iterator just above it so the following erases don't invalidated it.
921  iterator EarliestI(Cand.Instrs[Cand.EarliestMIIdx]);
922  bool EarliestAtBegin = false;
923  if (EarliestI == MBB.begin()) {
924  EarliestAtBegin = true;
925  } else {
926  EarliestI = std::prev(EarliestI);
927  }
928 
929  // Remove instructions which have been merged.
930  for (MachineInstr *MI : Cand.Instrs)
931  MBB.erase(MI);
932 
933  // Determine range between the earliest removed instruction and the new one.
934  if (EarliestAtBegin)
935  EarliestI = MBB.begin();
936  else
937  EarliestI = std::next(EarliestI);
938  auto FixupRange = make_range(EarliestI, iterator(Merged));
939 
940  if (isLoadSingle(Opcode)) {
941  // If the previous loads defined a super-reg, then we have to mark earlier
942  // operands undef; Replicate the super-reg def on the merged instruction.
943  for (MachineInstr &MI : FixupRange) {
944  for (unsigned &ImpDefReg : ImpDefs) {
945  for (MachineOperand &MO : MI.implicit_operands()) {
946  if (!MO.isReg() || MO.getReg() != ImpDefReg)
947  continue;
948  if (MO.readsReg())
949  MO.setIsUndef();
950  else if (MO.isDef())
951  ImpDefReg = 0;
952  }
953  }
954  }
955 
956  MachineInstrBuilder MIB(*Merged->getParent()->getParent(), Merged);
957  for (unsigned ImpDef : ImpDefs)
958  MIB.addReg(ImpDef, RegState::ImplicitDefine);
959  } else {
960  // Remove kill flags: We are possibly storing the values later now.
961  assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);
962  for (MachineInstr &MI : FixupRange) {
963  for (MachineOperand &MO : MI.uses()) {
964  if (!MO.isReg() || !MO.isKill())
965  continue;
966  if (UsedRegs.count(MO.getReg()))
967  MO.setIsKill(false);
968  }
969  }
970  assert(ImpDefs.empty());
971  }
972 
973  return Merged;
974 }
975 
976 static bool isValidLSDoubleOffset(int Offset) {
977  unsigned Value = abs(Offset);
978  // t2LDRDi8/t2STRDi8 supports an 8 bit immediate which is internally
979  // multiplied by 4.
980  return (Value % 4) == 0 && Value < 1024;
981 }
982 
983 /// Return true for loads/stores that can be combined to a double/multi
984 /// operation without increasing the requirements for alignment.
986  const MachineInstr &MI) {
987  // vldr/vstr trap on misaligned pointers anyway, forming vldm makes no
988  // difference.
989  unsigned Opcode = MI.getOpcode();
990  if (!isi32Load(Opcode) && !isi32Store(Opcode))
991  return true;
992 
993  // Stack pointer alignment is out of the programmers control so we can trust
994  // SP-relative loads/stores.
995  if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
997  return true;
998  return false;
999 }
1000 
1001 /// Find candidates for load/store multiple merge in list of MemOpQueueEntries.
1002 void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
1003  const MachineInstr *FirstMI = MemOps[0].MI;
1004  unsigned Opcode = FirstMI->getOpcode();
1005  bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
1006  unsigned Size = getLSMultipleTransferSize(FirstMI);
1007 
1008  unsigned SIndex = 0;
1009  unsigned EIndex = MemOps.size();
1010  do {
1011  // Look at the first instruction.
1012  const MachineInstr *MI = MemOps[SIndex].MI;
1013  int Offset = MemOps[SIndex].Offset;
1014  const MachineOperand &PMO = getLoadStoreRegOp(*MI);
1015  Register PReg = PMO.getReg();
1016  unsigned PRegNum = PMO.isUndef() ? std::numeric_limits<unsigned>::max()
1017  : TRI->getEncodingValue(PReg);
1018  unsigned Latest = SIndex;
1019  unsigned Earliest = SIndex;
1020  unsigned Count = 1;
1021  bool CanMergeToLSDouble =
1022  STI->isThumb2() && isNotVFP && isValidLSDoubleOffset(Offset);
1023  // ARM errata 602117: LDRD with base in list may result in incorrect base
1024  // register when interrupted or faulted.
1025  if (STI->isCortexM3() && isi32Load(Opcode) &&
1026  PReg == getLoadStoreBaseOp(*MI).getReg())
1027  CanMergeToLSDouble = false;
1028 
1029  bool CanMergeToLSMulti = true;
1030  // On swift vldm/vstm starting with an odd register number as that needs
1031  // more uops than single vldrs.
1032  if (STI->hasSlowOddRegister() && !isNotVFP && (PRegNum % 2) == 1)
1033  CanMergeToLSMulti = false;
1034 
1035  // LDRD/STRD do not allow SP/PC. LDM/STM do not support it or have it
1036  // deprecated; LDM to PC is fine but cannot happen here.
1037  if (PReg == ARM::SP || PReg == ARM::PC)
1038  CanMergeToLSMulti = CanMergeToLSDouble = false;
1039 
1040  // Should we be conservative?
1042  CanMergeToLSMulti = CanMergeToLSDouble = false;
1043 
1044  // vldm / vstm limit are 32 for S variants, 16 for D variants.
1045  unsigned Limit;
1046  switch (Opcode) {
1047  default:
1048  Limit = UINT_MAX;
1049  break;
1050  case ARM::VLDRD:
1051  case ARM::VSTRD:
1052  Limit = 16;
1053  break;
1054  }
1055 
1056  // Merge following instructions where possible.
1057  for (unsigned I = SIndex+1; I < EIndex; ++I, ++Count) {
1058  int NewOffset = MemOps[I].Offset;
1059  if (NewOffset != Offset + (int)Size)
1060  break;
1061  const MachineOperand &MO = getLoadStoreRegOp(*MemOps[I].MI);
1062  Register Reg = MO.getReg();
1063  if (Reg == ARM::SP || Reg == ARM::PC)
1064  break;
1065  if (Count == Limit)
1066  break;
1067 
1068  // See if the current load/store may be part of a multi load/store.
1069  unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max()
1070  : TRI->getEncodingValue(Reg);
1071  bool PartOfLSMulti = CanMergeToLSMulti;
1072  if (PartOfLSMulti) {
1073  // Register numbers must be in ascending order.
1074  if (RegNum <= PRegNum)
1075  PartOfLSMulti = false;
1076  // For VFP / NEON load/store multiples, the registers must be
1077  // consecutive and within the limit on the number of registers per
1078  // instruction.
1079  else if (!isNotVFP && RegNum != PRegNum+1)
1080  PartOfLSMulti = false;
1081  }
1082  // See if the current load/store may be part of a double load/store.
1083  bool PartOfLSDouble = CanMergeToLSDouble && Count <= 1;
1084 
1085  if (!PartOfLSMulti && !PartOfLSDouble)
1086  break;
1087  CanMergeToLSMulti &= PartOfLSMulti;
1088  CanMergeToLSDouble &= PartOfLSDouble;
1089  // Track MemOp with latest and earliest position (Positions are
1090  // counted in reverse).
1091  unsigned Position = MemOps[I].Position;
1092  if (Position < MemOps[Latest].Position)
1093  Latest = I;
1094  else if (Position > MemOps[Earliest].Position)
1095  Earliest = I;
1096  // Prepare for next MemOp.
1097  Offset += Size;
1098  PRegNum = RegNum;
1099  }
1100 
1101  // Form a candidate from the Ops collected so far.
1102  MergeCandidate *Candidate = new(Allocator.Allocate()) MergeCandidate;
1103  for (unsigned C = SIndex, CE = SIndex + Count; C < CE; ++C)
1104  Candidate->Instrs.push_back(MemOps[C].MI);
1105  Candidate->LatestMIIdx = Latest - SIndex;
1106  Candidate->EarliestMIIdx = Earliest - SIndex;
1107  Candidate->InsertPos = MemOps[Latest].Position;
1108  if (Count == 1)
1109  CanMergeToLSMulti = CanMergeToLSDouble = false;
1110  Candidate->CanMergeToLSMulti = CanMergeToLSMulti;
1111  Candidate->CanMergeToLSDouble = CanMergeToLSDouble;
1112  Candidates.push_back(Candidate);
1113  // Continue after the chain.
1114  SIndex += Count;
1115  } while (SIndex < EIndex);
1116 }
1117 
1118 static unsigned getUpdatingLSMultipleOpcode(unsigned Opc,
1120  switch (Opc) {
1121  default: llvm_unreachable("Unhandled opcode!");
1122  case ARM::LDMIA:
1123  case ARM::LDMDA:
1124  case ARM::LDMDB:
1125  case ARM::LDMIB:
1126  switch (Mode) {
1127  default: llvm_unreachable("Unhandled submode!");
1128  case ARM_AM::ia: return ARM::LDMIA_UPD;
1129  case ARM_AM::ib: return ARM::LDMIB_UPD;
1130  case ARM_AM::da: return ARM::LDMDA_UPD;
1131  case ARM_AM::db: return ARM::LDMDB_UPD;
1132  }
1133  case ARM::STMIA:
1134  case ARM::STMDA:
1135  case ARM::STMDB:
1136  case ARM::STMIB:
1137  switch (Mode) {
1138  default: llvm_unreachable("Unhandled submode!");
1139  case ARM_AM::ia: return ARM::STMIA_UPD;
1140  case ARM_AM::ib: return ARM::STMIB_UPD;
1141  case ARM_AM::da: return ARM::STMDA_UPD;
1142  case ARM_AM::db: return ARM::STMDB_UPD;
1143  }
1144  case ARM::t2LDMIA:
1145  case ARM::t2LDMDB:
1146  switch (Mode) {
1147  default: llvm_unreachable("Unhandled submode!");
1148  case ARM_AM::ia: return ARM::t2LDMIA_UPD;
1149  case ARM_AM::db: return ARM::t2LDMDB_UPD;
1150  }
1151  case ARM::t2STMIA:
1152  case ARM::t2STMDB:
1153  switch (Mode) {
1154  default: llvm_unreachable("Unhandled submode!");
1155  case ARM_AM::ia: return ARM::t2STMIA_UPD;
1156  case ARM_AM::db: return ARM::t2STMDB_UPD;
1157  }
1158  case ARM::VLDMSIA:
1159  switch (Mode) {
1160  default: llvm_unreachable("Unhandled submode!");
1161  case ARM_AM::ia: return ARM::VLDMSIA_UPD;
1162  case ARM_AM::db: return ARM::VLDMSDB_UPD;
1163  }
1164  case ARM::VLDMDIA:
1165  switch (Mode) {
1166  default: llvm_unreachable("Unhandled submode!");
1167  case ARM_AM::ia: return ARM::VLDMDIA_UPD;
1168  case ARM_AM::db: return ARM::VLDMDDB_UPD;
1169  }
1170  case ARM::VSTMSIA:
1171  switch (Mode) {
1172  default: llvm_unreachable("Unhandled submode!");
1173  case ARM_AM::ia: return ARM::VSTMSIA_UPD;
1174  case ARM_AM::db: return ARM::VSTMSDB_UPD;
1175  }
1176  case ARM::VSTMDIA:
1177  switch (Mode) {
1178  default: llvm_unreachable("Unhandled submode!");
1179  case ARM_AM::ia: return ARM::VSTMDIA_UPD;
1180  case ARM_AM::db: return ARM::VSTMDDB_UPD;
1181  }
1182  }
1183 }
1184 
1185 /// Check if the given instruction increments or decrements a register and
1186 /// return the amount it is incremented/decremented. Returns 0 if the CPSR flags
1187 /// generated by the instruction are possibly read as well.
1189  ARMCC::CondCodes Pred, Register PredReg) {
1190  bool CheckCPSRDef;
1191  int Scale;
1192  switch (MI.getOpcode()) {
1193  case ARM::tADDi8: Scale = 4; CheckCPSRDef = true; break;
1194  case ARM::tSUBi8: Scale = -4; CheckCPSRDef = true; break;
1195  case ARM::t2SUBri:
1196  case ARM::t2SUBspImm:
1197  case ARM::SUBri: Scale = -1; CheckCPSRDef = true; break;
1198  case ARM::t2ADDri:
1199  case ARM::t2ADDspImm:
1200  case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break;
1201  case ARM::tADDspi: Scale = 4; CheckCPSRDef = false; break;
1202  case ARM::tSUBspi: Scale = -4; CheckCPSRDef = false; break;
1203  default: return 0;
1204  }
1205 
1206  Register MIPredReg;
1207  if (MI.getOperand(0).getReg() != Reg ||
1208  MI.getOperand(1).getReg() != Reg ||
1209  getInstrPredicate(MI, MIPredReg) != Pred ||
1210  MIPredReg != PredReg)
1211  return 0;
1212 
1213  if (CheckCPSRDef && definesCPSR(MI))
1214  return 0;
1215  return MI.getOperand(2).getImm() * Scale;
1216 }
1217 
1218 /// Searches for an increment or decrement of \p Reg before \p MBBI.
1221  ARMCC::CondCodes Pred, Register PredReg, int &Offset) {
1222  Offset = 0;
1224  MachineBasicBlock::iterator BeginMBBI = MBB.begin();
1225  MachineBasicBlock::iterator EndMBBI = MBB.end();
1226  if (MBBI == BeginMBBI)
1227  return EndMBBI;
1228 
1229  // Skip debug values.
1230  MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
1231  while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
1232  --PrevMBBI;
1233 
1234  Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
1235  return Offset == 0 ? EndMBBI : PrevMBBI;
1236 }
1237 
1238 /// Searches for a increment or decrement of \p Reg after \p MBBI.
1241  ARMCC::CondCodes Pred, Register PredReg, int &Offset,
1242  const TargetRegisterInfo *TRI) {
1243  Offset = 0;
1245  MachineBasicBlock::iterator EndMBBI = MBB.end();
1246  MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
1247  while (NextMBBI != EndMBBI) {
1248  // Skip debug values.
1249  while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
1250  ++NextMBBI;
1251  if (NextMBBI == EndMBBI)
1252  return EndMBBI;
1253 
1254  unsigned Off = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
1255  if (Off) {
1256  Offset = Off;
1257  return NextMBBI;
1258  }
1259 
1260  // SP can only be combined if it is the next instruction after the original
1261  // MBBI, otherwise we may be incrementing the stack pointer (invalidating
1262  // anything below the new pointer) when its frame elements are still in
1263  // use. Other registers can attempt to look further, until a different use
1264  // or def of the register is found.
1265  if (Reg == ARM::SP || NextMBBI->readsRegister(Reg, TRI) ||
1266  NextMBBI->definesRegister(Reg, TRI))
1267  return EndMBBI;
1268 
1269  ++NextMBBI;
1270  }
1271  return EndMBBI;
1272 }
1273 
1274 /// Fold proceeding/trailing inc/dec of base register into the
1275 /// LDM/STM/VLDM{D|S}/VSTM{D|S} op when possible:
1276 ///
1277 /// stmia rn, <ra, rb, rc>
1278 /// rn := rn + 4 * 3;
1279 /// =>
1280 /// stmia rn!, <ra, rb, rc>
1281 ///
1282 /// rn := rn - 4 * 3;
1283 /// ldmia rn, <ra, rb, rc>
1284 /// =>
1285 /// ldmdb rn!, <ra, rb, rc>
1286 bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
1287  // Thumb1 is already using updating loads/stores.
1288  if (isThumb1) return false;
1289  LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
1290 
1291  const MachineOperand &BaseOP = MI->getOperand(0);
1292  Register Base = BaseOP.getReg();
1293  bool BaseKill = BaseOP.isKill();
1294  Register PredReg;
1295  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1296  unsigned Opcode = MI->getOpcode();
1297  DebugLoc DL = MI->getDebugLoc();
1298 
1299  // Can't use an updating ld/st if the base register is also a dest
1300  // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
1301  for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i)
1302  if (MI->getOperand(i).getReg() == Base)
1303  return false;
1304 
1305  int Bytes = getLSMultipleTransferSize(MI);
1306  MachineBasicBlock &MBB = *MI->getParent();
1308  int Offset;
1309  MachineBasicBlock::iterator MergeInstr
1310  = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1312  if (Mode == ARM_AM::ia && Offset == -Bytes) {
1313  Mode = ARM_AM::db;
1314  } else if (Mode == ARM_AM::ib && Offset == -Bytes) {
1315  Mode = ARM_AM::da;
1316  } else {
1317  MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1318  if (((Mode != ARM_AM::ia && Mode != ARM_AM::ib) || Offset != Bytes) &&
1319  ((Mode != ARM_AM::da && Mode != ARM_AM::db) || Offset != -Bytes)) {
1320 
1321  // We couldn't find an inc/dec to merge. But if the base is dead, we
1322  // can still change to a writeback form as that will save us 2 bytes
1323  // of code size. It can create WAW hazards though, so only do it if
1324  // we're minimizing code size.
1325  if (!STI->hasMinSize() || !BaseKill)
1326  return false;
1327 
1328  bool HighRegsUsed = false;
1329  for (unsigned i = 2, e = MI->getNumOperands(); i != e; ++i)
1330  if (MI->getOperand(i).getReg() >= ARM::R8) {
1331  HighRegsUsed = true;
1332  break;
1333  }
1334 
1335  if (!HighRegsUsed)
1336  MergeInstr = MBB.end();
1337  else
1338  return false;
1339  }
1340  }
1341  if (MergeInstr != MBB.end()) {
1342  LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
1343  MBB.erase(MergeInstr);
1344  }
1345 
1346  unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
1347  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1348  .addReg(Base, getDefRegState(true)) // WB base register
1349  .addReg(Base, getKillRegState(BaseKill))
1350  .addImm(Pred).addReg(PredReg);
1351 
1352  // Transfer the rest of operands.
1353  for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum)
1354  MIB.add(MI->getOperand(OpNum));
1355 
1356  // Transfer memoperands.
1357  MIB.setMemRefs(MI->memoperands());
1358 
1359  LLVM_DEBUG(dbgs() << " Added new load/store: " << *MIB);
1360  MBB.erase(MBBI);
1361  return true;
1362 }
1363 
1364 static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc,
1366  switch (Opc) {
1367  case ARM::LDRi12:
1368  return ARM::LDR_PRE_IMM;
1369  case ARM::STRi12:
1370  return ARM::STR_PRE_IMM;
1371  case ARM::VLDRS:
1372  return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
1373  case ARM::VLDRD:
1374  return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
1375  case ARM::VSTRS:
1376  return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
1377  case ARM::VSTRD:
1378  return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
1379  case ARM::t2LDRi8:
1380  case ARM::t2LDRi12:
1381  return ARM::t2LDR_PRE;
1382  case ARM::t2STRi8:
1383  case ARM::t2STRi12:
1384  return ARM::t2STR_PRE;
1385  default: llvm_unreachable("Unhandled opcode!");
1386  }
1387 }
1388 
1389 static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc,
1391  switch (Opc) {
1392  case ARM::LDRi12:
1393  return ARM::LDR_POST_IMM;
1394  case ARM::STRi12:
1395  return ARM::STR_POST_IMM;
1396  case ARM::VLDRS:
1397  return Mode == ARM_AM::add ? ARM::VLDMSIA_UPD : ARM::VLDMSDB_UPD;
1398  case ARM::VLDRD:
1399  return Mode == ARM_AM::add ? ARM::VLDMDIA_UPD : ARM::VLDMDDB_UPD;
1400  case ARM::VSTRS:
1401  return Mode == ARM_AM::add ? ARM::VSTMSIA_UPD : ARM::VSTMSDB_UPD;
1402  case ARM::VSTRD:
1403  return Mode == ARM_AM::add ? ARM::VSTMDIA_UPD : ARM::VSTMDDB_UPD;
1404  case ARM::t2LDRi8:
1405  case ARM::t2LDRi12:
1406  return ARM::t2LDR_POST;
1407  case ARM::t2LDRBi8:
1408  case ARM::t2LDRBi12:
1409  return ARM::t2LDRB_POST;
1410  case ARM::t2LDRSBi8:
1411  case ARM::t2LDRSBi12:
1412  return ARM::t2LDRSB_POST;
1413  case ARM::t2LDRHi8:
1414  case ARM::t2LDRHi12:
1415  return ARM::t2LDRH_POST;
1416  case ARM::t2LDRSHi8:
1417  case ARM::t2LDRSHi12:
1418  return ARM::t2LDRSH_POST;
1419  case ARM::t2STRi8:
1420  case ARM::t2STRi12:
1421  return ARM::t2STR_POST;
1422  case ARM::t2STRBi8:
1423  case ARM::t2STRBi12:
1424  return ARM::t2STRB_POST;
1425  case ARM::t2STRHi8:
1426  case ARM::t2STRHi12:
1427  return ARM::t2STRH_POST;
1428 
1429  case ARM::MVE_VLDRBS16:
1430  return ARM::MVE_VLDRBS16_post;
1431  case ARM::MVE_VLDRBS32:
1432  return ARM::MVE_VLDRBS32_post;
1433  case ARM::MVE_VLDRBU16:
1434  return ARM::MVE_VLDRBU16_post;
1435  case ARM::MVE_VLDRBU32:
1436  return ARM::MVE_VLDRBU32_post;
1437  case ARM::MVE_VLDRHS32:
1438  return ARM::MVE_VLDRHS32_post;
1439  case ARM::MVE_VLDRHU32:
1440  return ARM::MVE_VLDRHU32_post;
1441  case ARM::MVE_VLDRBU8:
1442  return ARM::MVE_VLDRBU8_post;
1443  case ARM::MVE_VLDRHU16:
1444  return ARM::MVE_VLDRHU16_post;
1445  case ARM::MVE_VLDRWU32:
1446  return ARM::MVE_VLDRWU32_post;
1447  case ARM::MVE_VSTRB16:
1448  return ARM::MVE_VSTRB16_post;
1449  case ARM::MVE_VSTRB32:
1450  return ARM::MVE_VSTRB32_post;
1451  case ARM::MVE_VSTRH32:
1452  return ARM::MVE_VSTRH32_post;
1453  case ARM::MVE_VSTRBU8:
1454  return ARM::MVE_VSTRBU8_post;
1455  case ARM::MVE_VSTRHU16:
1456  return ARM::MVE_VSTRHU16_post;
1457  case ARM::MVE_VSTRWU32:
1458  return ARM::MVE_VSTRWU32_post;
1459 
1460  default: llvm_unreachable("Unhandled opcode!");
1461  }
1462 }
1463 
1464 /// Fold proceeding/trailing inc/dec of base register into the
1465 /// LDR/STR/FLD{D|S}/FST{D|S} op when possible:
1466 bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
1467  // Thumb1 doesn't have updating LDR/STR.
1468  // FIXME: Use LDM/STM with single register instead.
1469  if (isThumb1) return false;
1470  LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << *MI);
1471 
1472  Register Base = getLoadStoreBaseOp(*MI).getReg();
1473  bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
1474  unsigned Opcode = MI->getOpcode();
1475  DebugLoc DL = MI->getDebugLoc();
1476  bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
1477  Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
1478  bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
1479  if (isi32Load(Opcode) || isi32Store(Opcode))
1480  if (MI->getOperand(2).getImm() != 0)
1481  return false;
1482  if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
1483  return false;
1484 
1485  // Can't do the merge if the destination register is the same as the would-be
1486  // writeback register.
1487  if (MI->getOperand(0).getReg() == Base)
1488  return false;
1489 
1490  Register PredReg;
1491  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1492  int Bytes = getLSMultipleTransferSize(MI);
1493  MachineBasicBlock &MBB = *MI->getParent();
1495  int Offset;
1496  MachineBasicBlock::iterator MergeInstr
1497  = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1498  unsigned NewOpc;
1499  if (!isAM5 && Offset == Bytes) {
1500  NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1501  } else if (Offset == -Bytes) {
1502  NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1503  } else {
1504  MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1505  if (MergeInstr == MBB.end())
1506  return false;
1507 
1508  NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);
1509  if ((isAM5 && Offset != Bytes) ||
1510  (!isAM5 && !isLegalAddressImm(NewOpc, Offset, TII))) {
1511  NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);
1512  if (isAM5 || !isLegalAddressImm(NewOpc, Offset, TII))
1513  return false;
1514  }
1515  }
1516  LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
1517  MBB.erase(MergeInstr);
1518 
1520 
1521  bool isLd = isLoadSingle(Opcode);
1522  if (isAM5) {
1523  // VLDM[SD]_UPD, VSTM[SD]_UPD
1524  // (There are no base-updating versions of VLDR/VSTR instructions, but the
1525  // updating load/store-multiple instructions can be used with only one
1526  // register.)
1527  MachineOperand &MO = MI->getOperand(0);
1528  auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1529  .addReg(Base, getDefRegState(true)) // WB base register
1530  .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1531  .addImm(Pred)
1532  .addReg(PredReg)
1533  .addReg(MO.getReg(), (isLd ? getDefRegState(true)
1534  : getKillRegState(MO.isKill())))
1535  .cloneMemRefs(*MI);
1536  (void)MIB;
1537  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1538  } else if (isLd) {
1539  if (isAM2) {
1540  // LDR_PRE, LDR_POST
1541  if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
1542  auto MIB =
1543  BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1544  .addReg(Base, RegState::Define)
1545  .addReg(Base)
1546  .addImm(Offset)
1547  .addImm(Pred)
1548  .addReg(PredReg)
1549  .cloneMemRefs(*MI);
1550  (void)MIB;
1551  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1552  } else {
1553  int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
1554  auto MIB =
1555  BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1556  .addReg(Base, RegState::Define)
1557  .addReg(Base)
1558  .addReg(0)
1559  .addImm(Imm)
1560  .add(predOps(Pred, PredReg))
1561  .cloneMemRefs(*MI);
1562  (void)MIB;
1563  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1564  }
1565  } else {
1566  // t2LDR_PRE, t2LDR_POST
1567  auto MIB =
1568  BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1569  .addReg(Base, RegState::Define)
1570  .addReg(Base)
1571  .addImm(Offset)
1572  .add(predOps(Pred, PredReg))
1573  .cloneMemRefs(*MI);
1574  (void)MIB;
1575  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1576  }
1577  } else {
1578  MachineOperand &MO = MI->getOperand(0);
1579  // FIXME: post-indexed stores use am2offset_imm, which still encodes
1580  // the vestigal zero-reg offset register. When that's fixed, this clause
1581  // can be removed entirely.
1582  if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
1583  int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift);
1584  // STR_PRE, STR_POST
1585  auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1586  .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1587  .addReg(Base)
1588  .addReg(0)
1589  .addImm(Imm)
1590  .add(predOps(Pred, PredReg))
1591  .cloneMemRefs(*MI);
1592  (void)MIB;
1593  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1594  } else {
1595  // t2STR_PRE, t2STR_POST
1596  auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1597  .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1598  .addReg(Base)
1599  .addImm(Offset)
1600  .add(predOps(Pred, PredReg))
1601  .cloneMemRefs(*MI);
1602  (void)MIB;
1603  LLVM_DEBUG(dbgs() << " Added new instruction: " << *MIB);
1604  }
1605  }
1606  MBB.erase(MBBI);
1607 
1608  return true;
1609 }
1610 
1611 bool ARMLoadStoreOpt::MergeBaseUpdateLSDouble(MachineInstr &MI) const {
1612  unsigned Opcode = MI.getOpcode();
1613  assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&
1614  "Must have t2STRDi8 or t2LDRDi8");
1615  if (MI.getOperand(3).getImm() != 0)
1616  return false;
1617  LLVM_DEBUG(dbgs() << "Attempting to merge update of: " << MI);
1618 
1619  // Behaviour for writeback is undefined if base register is the same as one
1620  // of the others.
1621  const MachineOperand &BaseOp = MI.getOperand(2);
1622  Register Base = BaseOp.getReg();
1623  const MachineOperand &Reg0Op = MI.getOperand(0);
1624  const MachineOperand &Reg1Op = MI.getOperand(1);
1625  if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
1626  return false;
1627 
1628  Register PredReg;
1629  ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1631  MachineBasicBlock &MBB = *MI.getParent();
1632  int Offset;
1633  MachineBasicBlock::iterator MergeInstr = findIncDecBefore(MBBI, Base, Pred,
1634  PredReg, Offset);
1635  unsigned NewOpc;
1636  if (Offset == 8 || Offset == -8) {
1637  NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;
1638  } else {
1639  MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset, TRI);
1640  if (MergeInstr == MBB.end())
1641  return false;
1642  NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;
1643  if (!isLegalAddressImm(NewOpc, Offset, TII))
1644  return false;
1645  }
1646  LLVM_DEBUG(dbgs() << " Erasing old increment: " << *MergeInstr);
1647  MBB.erase(MergeInstr);
1648 
1649  DebugLoc DL = MI.getDebugLoc();
1650  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1651  if (NewOpc == ARM::t2LDRD_PRE || NewOpc == ARM::t2LDRD_POST) {
1652  MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define);
1653  } else {
1654  assert(NewOpc == ARM::t2STRD_PRE || NewOpc == ARM::t2STRD_POST);
1655  MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op);
1656  }
1657  MIB.addReg(BaseOp.getReg(), RegState::Kill)
1658  .addImm(Offset).addImm(Pred).addReg(PredReg);
1659  assert(TII->get(Opcode).getNumOperands() == 6 &&
1660  TII->get(NewOpc).getNumOperands() == 7 &&
1661  "Unexpected number of operands in Opcode specification.");
1662 
1663  // Transfer implicit operands.
1664  for (const MachineOperand &MO : MI.implicit_operands())
1665  MIB.add(MO);
1666  MIB.cloneMemRefs(MI);
1667 
1668  LLVM_DEBUG(dbgs() << " Added new load/store: " << *MIB);
1669  MBB.erase(MBBI);
1670  return true;
1671 }
1672 
1673 /// Returns true if instruction is a memory operation that this pass is capable
1674 /// of operating on.
1675 static bool isMemoryOp(const MachineInstr &MI) {
1676  unsigned Opcode = MI.getOpcode();
1677  switch (Opcode) {
1678  case ARM::VLDRS:
1679  case ARM::VSTRS:
1680  case ARM::VLDRD:
1681  case ARM::VSTRD:
1682  case ARM::LDRi12:
1683  case ARM::STRi12:
1684  case ARM::tLDRi:
1685  case ARM::tSTRi:
1686  case ARM::tLDRspi:
1687  case ARM::tSTRspi:
1688  case ARM::t2LDRi8:
1689  case ARM::t2LDRi12:
1690  case ARM::t2STRi8:
1691  case ARM::t2STRi12:
1692  break;
1693  default:
1694  return false;
1695  }
1696  if (!MI.getOperand(1).isReg())
1697  return false;
1698 
1699  // When no memory operands are present, conservatively assume unaligned,
1700  // volatile, unfoldable.
1701  if (!MI.hasOneMemOperand())
1702  return false;
1703 
1704  const MachineMemOperand &MMO = **MI.memoperands_begin();
1705 
1706  // Don't touch volatile memory accesses - we may be changing their order.
1707  // TODO: We could allow unordered and monotonic atomics here, but we need to
1708  // make sure the resulting ldm/stm is correctly marked as atomic.
1709  if (MMO.isVolatile() || MMO.isAtomic())
1710  return false;
1711 
1712  // Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
1713  // not.
1714  if (MMO.getAlign() < Align(4))
1715  return false;
1716 
1717  // str <undef> could probably be eliminated entirely, but for now we just want
1718  // to avoid making a mess of it.
1719  // FIXME: Use str <undef> as a wildcard to enable better stm folding.
1720  if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
1721  return false;
1722 
1723  // Likewise don't mess with references to undefined addresses.
1724  if (MI.getOperand(1).isUndef())
1725  return false;
1726 
1727  return true;
1728 }
1729 
1732  bool isDef, unsigned NewOpc, unsigned Reg,
1733  bool RegDeadKill, bool RegUndef, unsigned BaseReg,
1734  bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred,
1735  unsigned PredReg, const TargetInstrInfo *TII,
1736  MachineInstr *MI) {
1737  if (isDef) {
1738  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1739  TII->get(NewOpc))
1740  .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1741  .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1742  MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1743  // FIXME: This is overly conservative; the new instruction accesses 4
1744  // bytes, not 8.
1745  MIB.cloneMemRefs(*MI);
1746  } else {
1747  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1748  TII->get(NewOpc))
1749  .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1750  .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1751  MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1752  // FIXME: This is overly conservative; the new instruction accesses 4
1753  // bytes, not 8.
1754  MIB.cloneMemRefs(*MI);
1755  }
1756 }
1757 
1758 bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
1760  MachineInstr *MI = &*MBBI;
1761  unsigned Opcode = MI->getOpcode();
1762  // FIXME: Code/comments below check Opcode == t2STRDi8, but this check returns
1763  // if we see this opcode.
1764  if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)
1765  return false;
1766 
1767  const MachineOperand &BaseOp = MI->getOperand(2);
1768  Register BaseReg = BaseOp.getReg();
1769  Register EvenReg = MI->getOperand(0).getReg();
1770  Register OddReg = MI->getOperand(1).getReg();
1771  unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);
1772  unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false);
1773 
1774  // ARM errata 602117: LDRD with base in list may result in incorrect base
1775  // register when interrupted or faulted.
1776  bool Errata602117 = EvenReg == BaseReg &&
1777  (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();
1778  // ARM LDRD/STRD needs consecutive registers.
1779  bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&
1780  (EvenRegNum % 2 != 0 || EvenRegNum + 1 != OddRegNum);
1781 
1782  if (!Errata602117 && !NonConsecutiveRegs)
1783  return false;
1784 
1785  bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
1786  bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1787  bool EvenDeadKill = isLd ?
1788  MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
1789  bool EvenUndef = MI->getOperand(0).isUndef();
1790  bool OddDeadKill = isLd ?
1791  MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
1792  bool OddUndef = MI->getOperand(1).isUndef();
1793  bool BaseKill = BaseOp.isKill();
1794  bool BaseUndef = BaseOp.isUndef();
1795  assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
1796  "register offset not handled below");
1797  int OffImm = getMemoryOpOffset(*MI);
1798  Register PredReg;
1799  ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1800 
1801  if (OddRegNum > EvenRegNum && OffImm == 0) {
1802  // Ascending register numbers and no offset. It's safe to change it to a
1803  // ldm or stm.
1804  unsigned NewOpc = (isLd)
1805  ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
1806  : (isT2 ? ARM::t2STMIA : ARM::STMIA);
1807  if (isLd) {
1808  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1809  .addReg(BaseReg, getKillRegState(BaseKill))
1810  .addImm(Pred).addReg(PredReg)
1811  .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1812  .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill))
1813  .cloneMemRefs(*MI);
1814  ++NumLDRD2LDM;
1815  } else {
1816  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1817  .addReg(BaseReg, getKillRegState(BaseKill))
1818  .addImm(Pred).addReg(PredReg)
1819  .addReg(EvenReg,
1820  getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
1821  .addReg(OddReg,
1822  getKillRegState(OddDeadKill) | getUndefRegState(OddUndef))
1823  .cloneMemRefs(*MI);
1824  ++NumSTRD2STM;
1825  }
1826  } else {
1827  // Split into two instructions.
1828  unsigned NewOpc = (isLd)
1829  ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
1830  : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
1831  // Be extra careful for thumb2. t2LDRi8 can't reference a zero offset,
1832  // so adjust and use t2LDRi12 here for that.
1833  unsigned NewOpc2 = (isLd)
1834  ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
1835  : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
1836  // If this is a load, make sure the first load does not clobber the base
1837  // register before the second load reads it.
1838  if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {
1839  assert(!TRI->regsOverlap(OddReg, BaseReg));
1840  InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1841  false, BaseReg, false, BaseUndef, Pred, PredReg, TII, MI);
1842  InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1843  false, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1844  MI);
1845  } else {
1846  if (OddReg == EvenReg && EvenDeadKill) {
1847  // If the two source operands are the same, the kill marker is
1848  // probably on the first one. e.g.
1849  // t2STRDi8 killed %r5, %r5, killed %r9, 0, 14, %reg0
1850  EvenDeadKill = false;
1851  OddDeadKill = true;
1852  }
1853  // Never kill the base register in the first instruction.
1854  if (EvenReg == BaseReg)
1855  EvenDeadKill = false;
1856  InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,
1857  EvenUndef, BaseReg, false, BaseUndef, Pred, PredReg, TII,
1858  MI);
1859  InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,
1860  OddUndef, BaseReg, BaseKill, BaseUndef, Pred, PredReg, TII,
1861  MI);
1862  }
1863  if (isLd)
1864  ++NumLDRD2LDR;
1865  else
1866  ++NumSTRD2STR;
1867  }
1868 
1869  MBBI = MBB.erase(MBBI);
1870  return true;
1871 }
1872 
1873 /// An optimization pass to turn multiple LDR / STR ops of the same base and
1874 /// incrementing offset into LDM / STM ops.
1875 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
1876  MemOpQueue MemOps;
1877  unsigned CurrBase = 0;
1878  unsigned CurrOpc = ~0u;
1879  ARMCC::CondCodes CurrPred = ARMCC::AL;
1880  unsigned Position = 0;
1881  assert(Candidates.size() == 0);
1882  assert(MergeBaseCandidates.size() == 0);
1883  LiveRegsValid = false;
1884 
1885  for (MachineBasicBlock::iterator I = MBB.end(), MBBI; I != MBB.begin();
1886  I = MBBI) {
1887  // The instruction in front of the iterator is the one we look at.
1888  MBBI = std::prev(I);
1889  if (FixInvalidRegPairOp(MBB, MBBI))
1890  continue;
1891  ++Position;
1892 
1893  if (isMemoryOp(*MBBI)) {
1894  unsigned Opcode = MBBI->getOpcode();
1895  const MachineOperand &MO = MBBI->getOperand(0);
1896  Register Reg = MO.getReg();
1897  Register Base = getLoadStoreBaseOp(*MBBI).getReg();
1898  Register PredReg;
1899  ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1900  int Offset = getMemoryOpOffset(*MBBI);
1901  if (CurrBase == 0) {
1902  // Start of a new chain.
1903  CurrBase = Base;
1904  CurrOpc = Opcode;
1905  CurrPred = Pred;
1906  MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
1907  continue;
1908  }
1909  // Note: No need to match PredReg in the next if.
1910  if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
1911  // Watch out for:
1912  // r4 := ldr [r0, #8]
1913  // r4 := ldr [r0, #4]
1914  // or
1915  // r0 := ldr [r0]
1916  // If a load overrides the base register or a register loaded by
1917  // another load in our chain, we cannot take this instruction.
1918  bool Overlap = false;
1919  if (isLoadSingle(Opcode)) {
1920  Overlap = (Base == Reg);
1921  if (!Overlap) {
1922  for (const MemOpQueueEntry &E : MemOps) {
1923  if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) {
1924  Overlap = true;
1925  break;
1926  }
1927  }
1928  }
1929  }
1930 
1931  if (!Overlap) {
1932  // Check offset and sort memory operation into the current chain.
1933  if (Offset > MemOps.back().Offset) {
1934  MemOps.push_back(MemOpQueueEntry(*MBBI, Offset, Position));
1935  continue;
1936  } else {
1937  MemOpQueue::iterator MI, ME;
1938  for (MI = MemOps.begin(), ME = MemOps.end(); MI != ME; ++MI) {
1939  if (Offset < MI->Offset) {
1940  // Found a place to insert.
1941  break;
1942  }
1943  if (Offset == MI->Offset) {
1944  // Collision, abort.
1945  MI = ME;
1946  break;
1947  }
1948  }
1949  if (MI != MemOps.end()) {
1950  MemOps.insert(MI, MemOpQueueEntry(*MBBI, Offset, Position));
1951  continue;
1952  }
1953  }
1954  }
1955  }
1956 
1957  // Don't advance the iterator; The op will start a new chain next.
1958  MBBI = I;
1959  --Position;
1960  // Fallthrough to look into existing chain.
1961  } else if (MBBI->isDebugInstr()) {
1962  continue;
1963  } else if (MBBI->getOpcode() == ARM::t2LDRDi8 ||
1964  MBBI->getOpcode() == ARM::t2STRDi8) {
1965  // ARMPreAllocLoadStoreOpt has already formed some LDRD/STRD instructions
1966  // remember them because we may still be able to merge add/sub into them.
1967  MergeBaseCandidates.push_back(&*MBBI);
1968  }
1969 
1970  // If we are here then the chain is broken; Extract candidates for a merge.
1971  if (MemOps.size() > 0) {
1972  FormCandidates(MemOps);
1973  // Reset for the next chain.
1974  CurrBase = 0;
1975  CurrOpc = ~0u;
1976  CurrPred = ARMCC::AL;
1977  MemOps.clear();
1978  }
1979  }
1980  if (MemOps.size() > 0)
1981  FormCandidates(MemOps);
1982 
1983  // Sort candidates so they get processed from end to begin of the basic
1984  // block later; This is necessary for liveness calculation.
1985  auto LessThan = [](const MergeCandidate* M0, const MergeCandidate *M1) {
1986  return M0->InsertPos < M1->InsertPos;
1987  };
1988  llvm::sort(Candidates, LessThan);
1989 
1990  // Go through list of candidates and merge.
1991  bool Changed = false;
1992  for (const MergeCandidate *Candidate : Candidates) {
1993  if (Candidate->CanMergeToLSMulti || Candidate->CanMergeToLSDouble) {
1994  MachineInstr *Merged = MergeOpsUpdate(*Candidate);
1995  // Merge preceding/trailing base inc/dec into the merged op.
1996  if (Merged) {
1997  Changed = true;
1998  unsigned Opcode = Merged->getOpcode();
1999  if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)
2000  MergeBaseUpdateLSDouble(*Merged);
2001  else
2002  MergeBaseUpdateLSMultiple(Merged);
2003  } else {
2004  for (MachineInstr *MI : Candidate->Instrs) {
2005  if (MergeBaseUpdateLoadStore(MI))
2006  Changed = true;
2007  }
2008  }
2009  } else {
2010  assert(Candidate->Instrs.size() == 1);
2011  if (MergeBaseUpdateLoadStore(Candidate->Instrs.front()))
2012  Changed = true;
2013  }
2014  }
2015  Candidates.clear();
2016  // Try to fold add/sub into the LDRD/STRD formed by ARMPreAllocLoadStoreOpt.
2017  for (MachineInstr *MI : MergeBaseCandidates)
2018  MergeBaseUpdateLSDouble(*MI);
2019  MergeBaseCandidates.clear();
2020 
2021  return Changed;
2022 }
2023 
2024 /// If this is a exit BB, try merging the return ops ("bx lr" and "mov pc, lr")
2025 /// into the preceding stack restore so it directly restore the value of LR
2026 /// into pc.
2027 /// ldmfd sp!, {..., lr}
2028 /// bx lr
2029 /// or
2030 /// ldmfd sp!, {..., lr}
2031 /// mov pc, lr
2032 /// =>
2033 /// ldmfd sp!, {..., pc}
2034 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
2035  // Thumb1 LDM doesn't allow high registers.
2036  if (isThumb1) return false;
2037  if (MBB.empty()) return false;
2038 
2040  if (MBBI != MBB.begin() && MBBI != MBB.end() &&
2041  (MBBI->getOpcode() == ARM::BX_RET ||
2042  MBBI->getOpcode() == ARM::tBX_RET ||
2043  MBBI->getOpcode() == ARM::MOVPCLR)) {
2044  MachineBasicBlock::iterator PrevI = std::prev(MBBI);
2045  // Ignore any debug instructions.
2046  while (PrevI->isDebugInstr() && PrevI != MBB.begin())
2047  --PrevI;
2048  MachineInstr &PrevMI = *PrevI;
2049  unsigned Opcode = PrevMI.getOpcode();
2050  if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
2051  Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
2052  Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
2053  MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
2054  if (MO.getReg() != ARM::LR)
2055  return false;
2056  unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
2057  assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
2058  Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
2059  PrevMI.setDesc(TII->get(NewOpc));
2060  MO.setReg(ARM::PC);
2061  PrevMI.copyImplicitOps(*MBB.getParent(), *MBBI);
2062  MBB.erase(MBBI);
2063  // We now restore LR into PC so it is not live-out of the return block
2064  // anymore: Clear the CSI Restored bit.
2066  // CSI should be fixed after PrologEpilog Insertion
2067  assert(MFI.isCalleeSavedInfoValid() && "CSI should be valid");
2068  for (CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
2069  if (Info.getReg() == ARM::LR) {
2070  Info.setRestored(false);
2071  break;
2072  }
2073  }
2074  return true;
2075  }
2076  }
2077  return false;
2078 }
2079 
2080 bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
2082  if (MBBI == MBB.begin() || MBBI == MBB.end() ||
2083  MBBI->getOpcode() != ARM::tBX_RET)
2084  return false;
2085 
2087  --Prev;
2088  if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))
2089  return false;
2090 
2091  for (auto Use : Prev->uses())
2092  if (Use.isKill()) {
2093  assert(STI->hasV4TOps());
2094  BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
2095  .addReg(Use.getReg(), RegState::Kill)
2096  .add(predOps(ARMCC::AL))
2097  .copyImplicitOps(*MBBI);
2098  MBB.erase(MBBI);
2099  MBB.erase(Prev);
2100  return true;
2101  }
2102 
2103  llvm_unreachable("tMOVr doesn't kill a reg before tBX_RET?");
2104 }
2105 
2106 bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
2107  if (skipFunction(Fn.getFunction()))
2108  return false;
2109 
2110  MF = &Fn;
2111  STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
2112  TL = STI->getTargetLowering();
2113  AFI = Fn.getInfo<ARMFunctionInfo>();
2114  TII = STI->getInstrInfo();
2115  TRI = STI->getRegisterInfo();
2116 
2117  RegClassInfoValid = false;
2118  isThumb2 = AFI->isThumb2Function();
2119  isThumb1 = AFI->isThumbFunction() && !isThumb2;
2120 
2121  bool Modified = false;
2122  for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
2123  ++MFI) {
2124  MachineBasicBlock &MBB = *MFI;
2125  Modified |= LoadStoreMultipleOpti(MBB);
2126  if (STI->hasV5TOps())
2127  Modified |= MergeReturnIntoLDM(MBB);
2128  if (isThumb1)
2129  Modified |= CombineMovBx(MBB);
2130  }
2131 
2132  Allocator.DestroyAll();
2133  return Modified;
2134 }
2135 
2136 #define ARM_PREALLOC_LOAD_STORE_OPT_NAME \
2137  "ARM pre- register allocation load / store optimization pass"
2138 
2139 namespace {
2140 
2141  /// Pre- register allocation pass that move load / stores from consecutive
2142  /// locations close to make it more likely they will be combined later.
2143  struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
2144  static char ID;
2145 
2146  AliasAnalysis *AA;
2147  const DataLayout *TD;
2148  const TargetInstrInfo *TII;
2149  const TargetRegisterInfo *TRI;
2150  const ARMSubtarget *STI;
2153  MachineFunction *MF;
2154 
2155  ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
2156 
2157  bool runOnMachineFunction(MachineFunction &Fn) override;
2158 
2159  StringRef getPassName() const override {
2161  }
2162 
2163  void getAnalysisUsage(AnalysisUsage &AU) const override {
2168  }
2169 
2170  private:
2171  bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
2172  unsigned &NewOpc, Register &EvenReg, Register &OddReg,
2173  Register &BaseReg, int &Offset, Register &PredReg,
2174  ARMCC::CondCodes &Pred, bool &isT2);
2175  bool RescheduleOps(MachineBasicBlock *MBB,
2177  unsigned Base, bool isLd,
2179  bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
2180  bool DistributeIncrements();
2181  bool DistributeIncrements(Register Base);
2182  };
2183 
2184 } // end anonymous namespace
2185 
2187 
2188 INITIALIZE_PASS_BEGIN(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
2189  ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false)
2191 INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt",
2193 
2194 // Limit the number of instructions to be rescheduled.
2195 // FIXME: tune this limit, and/or come up with some better heuristics.
2196 static cl::opt<unsigned> InstReorderLimit("arm-prera-ldst-opt-reorder-limit",
2197  cl::init(8), cl::Hidden);
2198 
2199 bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
2200  if (AssumeMisalignedLoadStores || skipFunction(Fn.getFunction()))
2201  return false;
2202 
2203  TD = &Fn.getDataLayout();
2204  STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
2205  TII = STI->getInstrInfo();
2206  TRI = STI->getRegisterInfo();
2207  MRI = &Fn.getRegInfo();
2208  DT = &getAnalysis<MachineDominatorTree>();
2209  MF = &Fn;
2210  AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
2211 
2212  bool Modified = DistributeIncrements();
2213  for (MachineBasicBlock &MFI : Fn)
2214  Modified |= RescheduleLoadStoreInstrs(&MFI);
2215 
2216  return Modified;
2217 }
2218 
2219 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
2223  SmallSet<unsigned, 4> &MemRegs,
2224  const TargetRegisterInfo *TRI,
2225  AliasAnalysis *AA) {
2226  // Are there stores / loads / calls between them?
2227  SmallSet<unsigned, 4> AddedRegPressure;
2228  while (++I != E) {
2229  if (I->isDebugInstr() || MemOps.count(&*I))
2230  continue;
2231  if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
2232  return false;
2233  if (I->mayStore() || (!isLd && I->mayLoad()))
2234  for (MachineInstr *MemOp : MemOps)
2235  if (I->mayAlias(AA, *MemOp, /*UseTBAA*/ false))
2236  return false;
2237  for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
2238  MachineOperand &MO = I->getOperand(j);
2239  if (!MO.isReg())
2240  continue;
2241  Register Reg = MO.getReg();
2242  if (MO.isDef() && TRI->regsOverlap(Reg, Base))
2243  return false;
2244  if (Reg != Base && !MemRegs.count(Reg))
2245  AddedRegPressure.insert(Reg);
2246  }
2247  }
2248 
2249  // Estimate register pressure increase due to the transformation.
2250  if (MemRegs.size() <= 4)
2251  // Ok if we are moving small number of instructions.
2252  return true;
2253  return AddedRegPressure.size() <= MemRegs.size() * 2;
2254 }
2255 
2256 bool ARMPreAllocLoadStoreOpt::CanFormLdStDWord(
2257  MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc,
2258  Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,
2259  Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) {
2260  // Make sure we're allowed to generate LDRD/STRD.
2261  if (!STI->hasV5TEOps())
2262  return false;
2263 
2264  // FIXME: VLDRS / VSTRS -> VLDRD / VSTRD
2265  unsigned Scale = 1;
2266  unsigned Opcode = Op0->getOpcode();
2267  if (Opcode == ARM::LDRi12) {
2268  NewOpc = ARM::LDRD;
2269  } else if (Opcode == ARM::STRi12) {
2270  NewOpc = ARM::STRD;
2271  } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
2272  NewOpc = ARM::t2LDRDi8;
2273  Scale = 4;
2274  isT2 = true;
2275  } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
2276  NewOpc = ARM::t2STRDi8;
2277  Scale = 4;
2278  isT2 = true;
2279  } else {
2280  return false;
2281  }
2282 
2283  // Make sure the base address satisfies i64 ld / st alignment requirement.
2284  // At the moment, we ignore the memoryoperand's value.
2285  // If we want to use AliasAnalysis, we should check it accordingly.
2286  if (!Op0->hasOneMemOperand() ||
2287  (*Op0->memoperands_begin())->isVolatile() ||
2288  (*Op0->memoperands_begin())->isAtomic())
2289  return false;
2290 
2291  Align Alignment = (*Op0->memoperands_begin())->getAlign();
2292  const Function &Func = MF->getFunction();
2293  Align ReqAlign =
2294  STI->hasV6Ops() ? TD->getABITypeAlign(Type::getInt64Ty(Func.getContext()))
2295  : Align(8); // Pre-v6 need 8-byte align
2296  if (Alignment < ReqAlign)
2297  return false;
2298 
2299  // Then make sure the immediate offset fits.
2300  int OffImm = getMemoryOpOffset(*Op0);
2301  if (isT2) {
2302  int Limit = (1 << 8) * Scale;
2303  if (OffImm >= Limit || (OffImm <= -Limit) || (OffImm & (Scale-1)))
2304  return false;
2305  Offset = OffImm;
2306  } else {
2308  if (OffImm < 0) {
2309  AddSub = ARM_AM::sub;
2310  OffImm = - OffImm;
2311  }
2312  int Limit = (1 << 8) * Scale;
2313  if (OffImm >= Limit || (OffImm & (Scale-1)))
2314  return false;
2315  Offset = ARM_AM::getAM3Opc(AddSub, OffImm);
2316  }
2317  FirstReg = Op0->getOperand(0).getReg();
2318  SecondReg = Op1->getOperand(0).getReg();
2319  if (FirstReg == SecondReg)
2320  return false;
2321  BaseReg = Op0->getOperand(1).getReg();
2322  Pred = getInstrPredicate(*Op0, PredReg);
2323  dl = Op0->getDebugLoc();
2324  return true;
2325 }
2326 
2327 bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
2329  unsigned Base, bool isLd,
2330  DenseMap<MachineInstr*, unsigned> &MI2LocMap) {
2331  bool RetVal = false;
2332 
2333  // Sort by offset (in reverse order).
2334  llvm::sort(Ops, [](const MachineInstr *LHS, const MachineInstr *RHS) {
2335  int LOffset = getMemoryOpOffset(*LHS);
2336  int ROffset = getMemoryOpOffset(*RHS);
2337  assert(LHS == RHS || LOffset != ROffset);
2338  return LOffset > ROffset;
2339  });
2340 
2341  // The loads / stores of the same base are in order. Scan them from first to
2342  // last and check for the following:
2343  // 1. Any def of base.
2344  // 2. Any gaps.
2345  while (Ops.size() > 1) {
2346  unsigned FirstLoc = ~0U;
2347  unsigned LastLoc = 0;
2348  MachineInstr *FirstOp = nullptr;
2349  MachineInstr *LastOp = nullptr;
2350  int LastOffset = 0;
2351  unsigned LastOpcode = 0;
2352  unsigned LastBytes = 0;
2353  unsigned NumMove = 0;
2354  for (int i = Ops.size() - 1; i >= 0; --i) {
2355  // Make sure each operation has the same kind.
2356  MachineInstr *Op = Ops[i];
2357  unsigned LSMOpcode
2358  = getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
2359  if (LastOpcode && LSMOpcode != LastOpcode)
2360  break;
2361 
2362  // Check that we have a continuous set of offsets.
2363  int Offset = getMemoryOpOffset(*Op);
2364  unsigned Bytes = getLSMultipleTransferSize(Op);
2365  if (LastBytes) {
2366  if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
2367  break;
2368  }
2369 
2370  // Don't try to reschedule too many instructions.
2371  if (NumMove == InstReorderLimit)
2372  break;
2373 
2374  // Found a mergable instruction; save information about it.
2375  ++NumMove;
2376  LastOffset = Offset;
2377  LastBytes = Bytes;
2378  LastOpcode = LSMOpcode;
2379 
2380  unsigned Loc = MI2LocMap[Op];
2381  if (Loc <= FirstLoc) {
2382  FirstLoc = Loc;
2383  FirstOp = Op;
2384  }
2385  if (Loc >= LastLoc) {
2386  LastLoc = Loc;
2387  LastOp = Op;
2388  }
2389  }
2390 
2391  if (NumMove <= 1)
2392  Ops.pop_back();
2393  else {
2395  SmallSet<unsigned, 4> MemRegs;
2396  for (size_t i = Ops.size() - NumMove, e = Ops.size(); i != e; ++i) {
2397  MemOps.insert(Ops[i]);
2398  MemRegs.insert(Ops[i]->getOperand(0).getReg());
2399  }
2400 
2401  // Be conservative, if the instructions are too far apart, don't
2402  // move them. We want to limit the increase of register pressure.
2403  bool DoMove = (LastLoc - FirstLoc) <= NumMove*4; // FIXME: Tune this.
2404  if (DoMove)
2405  DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,
2406  MemOps, MemRegs, TRI, AA);
2407  if (!DoMove) {
2408  for (unsigned i = 0; i != NumMove; ++i)
2409  Ops.pop_back();
2410  } else {
2411  // This is the new location for the loads / stores.
2412  MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
2413  while (InsertPos != MBB->end() &&
2414  (MemOps.count(&*InsertPos) || InsertPos->isDebugInstr()))
2415  ++InsertPos;
2416 
2417  // If we are moving a pair of loads / stores, see if it makes sense
2418  // to try to allocate a pair of registers that can form register pairs.
2419  MachineInstr *Op0 = Ops.back();
2420  MachineInstr *Op1 = Ops[Ops.size()-2];
2421  Register FirstReg, SecondReg;
2422  Register BaseReg, PredReg;
2423  ARMCC::CondCodes Pred = ARMCC::AL;
2424  bool isT2 = false;
2425  unsigned NewOpc = 0;
2426  int Offset = 0;
2427  DebugLoc dl;
2428  if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
2429  FirstReg, SecondReg, BaseReg,
2430  Offset, PredReg, Pred, isT2)) {
2431  Ops.pop_back();
2432  Ops.pop_back();
2433 
2434  const MCInstrDesc &MCID = TII->get(NewOpc);
2435  const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
2436  MRI->constrainRegClass(FirstReg, TRC);
2437  MRI->constrainRegClass(SecondReg, TRC);
2438 
2439  // Form the pair instruction.
2440  if (isLd) {
2441  MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2442  .addReg(FirstReg, RegState::Define)
2443  .addReg(SecondReg, RegState::Define)
2444  .addReg(BaseReg);
2445  // FIXME: We're converting from LDRi12 to an insn that still
2446  // uses addrmode2, so we need an explicit offset reg. It should
2447  // always by reg0 since we're transforming LDRi12s.
2448  if (!isT2)
2449  MIB.addReg(0);
2450  MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2451  MIB.cloneMergedMemRefs({Op0, Op1});
2452  LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
2453  ++NumLDRDFormed;
2454  } else {
2455  MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2456  .addReg(FirstReg)
2457  .addReg(SecondReg)
2458  .addReg(BaseReg);
2459  // FIXME: We're converting from LDRi12 to an insn that still
2460  // uses addrmode2, so we need an explicit offset reg. It should
2461  // always by reg0 since we're transforming STRi12s.
2462  if (!isT2)
2463  MIB.addReg(0);
2464  MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2465  MIB.cloneMergedMemRefs({Op0, Op1});
2466  LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
2467  ++NumSTRDFormed;
2468  }
2469  MBB->erase(Op0);
2470  MBB->erase(Op1);
2471 
2472  if (!isT2) {
2473  // Add register allocation hints to form register pairs.
2474  MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
2475  MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg);
2476  }
2477  } else {
2478  for (unsigned i = 0; i != NumMove; ++i) {
2479  MachineInstr *Op = Ops.back();
2480  Ops.pop_back();
2481  MBB->splice(InsertPos, MBB, Op);
2482  }
2483  }
2484 
2485  NumLdStMoved += NumMove;
2486  RetVal = true;
2487  }
2488  }
2489  }
2490 
2491  return RetVal;
2492 }
2493 
2494 bool
2495 ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
2496  bool RetVal = false;
2497 
2499  using MapIt = DenseMap<unsigned, SmallVector<MachineInstr *, 4>>::iterator;
2501  using BaseVec = SmallVector<unsigned, 4>;
2502  Base2InstMap Base2LdsMap;
2503  Base2InstMap Base2StsMap;
2504  BaseVec LdBases;
2505  BaseVec StBases;
2506 
2507  unsigned Loc = 0;
2510  while (MBBI != E) {
2511  for (; MBBI != E; ++MBBI) {
2512  MachineInstr &MI = *MBBI;
2513  if (MI.isCall() || MI.isTerminator()) {
2514  // Stop at barriers.
2515  ++MBBI;
2516  break;
2517  }
2518 
2519  if (!MI.isDebugInstr())
2520  MI2LocMap[&MI] = ++Loc;
2521 
2522  if (!isMemoryOp(MI))
2523  continue;
2524  Register PredReg;
2525  if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
2526  continue;
2527 
2528  int Opc = MI.getOpcode();
2529  bool isLd = isLoadSingle(Opc);
2530  Register Base = MI.getOperand(1).getReg();
2531  int Offset = getMemoryOpOffset(MI);
2532  bool StopHere = false;
2533  auto FindBases = [&] (Base2InstMap &Base2Ops, BaseVec &Bases) {
2534  MapIt BI = Base2Ops.find(Base);
2535  if (BI == Base2Ops.end()) {
2536  Base2Ops[Base].push_back(&MI);
2537  Bases.push_back(Base);
2538  return;
2539  }
2540  for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
2541  if (Offset == getMemoryOpOffset(*BI->second[i])) {
2542  StopHere = true;
2543  break;
2544  }
2545  }
2546  if (!StopHere)
2547  BI->second.push_back(&MI);
2548  };
2549 
2550  if (isLd)
2551  FindBases(Base2LdsMap, LdBases);
2552  else
2553  FindBases(Base2StsMap, StBases);
2554 
2555  if (StopHere) {
2556  // Found a duplicate (a base+offset combination that's seen earlier).
2557  // Backtrack.
2558  --Loc;
2559  break;
2560  }
2561  }
2562 
2563  // Re-schedule loads.
2564  for (unsigned i = 0, e = LdBases.size(); i != e; ++i) {
2565  unsigned Base = LdBases[i];
2566  SmallVectorImpl<MachineInstr *> &Lds = Base2LdsMap[Base];
2567  if (Lds.size() > 1)
2568  RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
2569  }
2570 
2571  // Re-schedule stores.
2572  for (unsigned i = 0, e = StBases.size(); i != e; ++i) {
2573  unsigned Base = StBases[i];
2574  SmallVectorImpl<MachineInstr *> &Sts = Base2StsMap[Base];
2575  if (Sts.size() > 1)
2576  RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
2577  }
2578 
2579  if (MBBI != E) {
2580  Base2LdsMap.clear();
2581  Base2StsMap.clear();
2582  LdBases.clear();
2583  StBases.clear();
2584  }
2585  }
2586 
2587  return RetVal;
2588 }
2589 
2590 // Get the Base register operand index from the memory access MachineInst if we
2591 // should attempt to distribute postinc on it. Return -1 if not of a valid
2592 // instruction type. If it returns an index, it is assumed that instruction is a
2593 // r+i indexing mode, and getBaseOperandIndex() + 1 is the Offset index.
2595  switch (MI.getOpcode()) {
2596  case ARM::MVE_VLDRBS16:
2597  case ARM::MVE_VLDRBS32:
2598  case ARM::MVE_VLDRBU16:
2599  case ARM::MVE_VLDRBU32:
2600  case ARM::MVE_VLDRHS32:
2601  case ARM::MVE_VLDRHU32:
2602  case ARM::MVE_VLDRBU8:
2603  case ARM::MVE_VLDRHU16:
2604  case ARM::MVE_VLDRWU32:
2605  case ARM::MVE_VSTRB16:
2606  case ARM::MVE_VSTRB32:
2607  case ARM::MVE_VSTRH32:
2608  case ARM::MVE_VSTRBU8:
2609  case ARM::MVE_VSTRHU16:
2610  case ARM::MVE_VSTRWU32:
2611  case ARM::t2LDRHi8:
2612  case ARM::t2LDRHi12:
2613  case ARM::t2LDRSHi8:
2614  case ARM::t2LDRSHi12:
2615  case ARM::t2LDRBi8:
2616  case ARM::t2LDRBi12:
2617  case ARM::t2LDRSBi8:
2618  case ARM::t2LDRSBi12:
2619  case ARM::t2STRBi8:
2620  case ARM::t2STRBi12:
2621  case ARM::t2STRHi8:
2622  case ARM::t2STRHi12:
2623  return 1;
2624  case ARM::MVE_VLDRBS16_post:
2625  case ARM::MVE_VLDRBS32_post:
2626  case ARM::MVE_VLDRBU16_post:
2627  case ARM::MVE_VLDRBU32_post:
2628  case ARM::MVE_VLDRHS32_post:
2629  case ARM::MVE_VLDRHU32_post:
2630  case ARM::MVE_VLDRBU8_post:
2631  case ARM::MVE_VLDRHU16_post:
2632  case ARM::MVE_VLDRWU32_post:
2633  case ARM::MVE_VSTRB16_post:
2634  case ARM::MVE_VSTRB32_post:
2635  case ARM::MVE_VSTRH32_post:
2636  case ARM::MVE_VSTRBU8_post:
2637  case ARM::MVE_VSTRHU16_post:
2638  case ARM::MVE_VSTRWU32_post:
2639  case ARM::MVE_VLDRBS16_pre:
2640  case ARM::MVE_VLDRBS32_pre:
2641  case ARM::MVE_VLDRBU16_pre:
2642  case ARM::MVE_VLDRBU32_pre:
2643  case ARM::MVE_VLDRHS32_pre:
2644  case ARM::MVE_VLDRHU32_pre:
2645  case ARM::MVE_VLDRBU8_pre:
2646  case ARM::MVE_VLDRHU16_pre:
2647  case ARM::MVE_VLDRWU32_pre:
2648  case ARM::MVE_VSTRB16_pre:
2649  case ARM::MVE_VSTRB32_pre:
2650  case ARM::MVE_VSTRH32_pre:
2651  case ARM::MVE_VSTRBU8_pre:
2652  case ARM::MVE_VSTRHU16_pre:
2653  case ARM::MVE_VSTRWU32_pre:
2654  return 2;
2655  }
2656  return -1;
2657 }
2658 
2659 static bool isPostIndex(MachineInstr &MI) {
2660  switch (MI.getOpcode()) {
2661  case ARM::MVE_VLDRBS16_post:
2662  case ARM::MVE_VLDRBS32_post:
2663  case ARM::MVE_VLDRBU16_post:
2664  case ARM::MVE_VLDRBU32_post:
2665  case ARM::MVE_VLDRHS32_post:
2666  case ARM::MVE_VLDRHU32_post:
2667  case ARM::MVE_VLDRBU8_post:
2668  case ARM::MVE_VLDRHU16_post:
2669  case ARM::MVE_VLDRWU32_post:
2670  case ARM::MVE_VSTRB16_post:
2671  case ARM::MVE_VSTRB32_post:
2672  case ARM::MVE_VSTRH32_post:
2673  case ARM::MVE_VSTRBU8_post:
2674  case ARM::MVE_VSTRHU16_post:
2675  case ARM::MVE_VSTRWU32_post:
2676  return true;
2677  }
2678  return false;
2679 }
2680 
2681 static bool isPreIndex(MachineInstr &MI) {
2682  switch (MI.getOpcode()) {
2683  case ARM::MVE_VLDRBS16_pre:
2684  case ARM::MVE_VLDRBS32_pre:
2685  case ARM::MVE_VLDRBU16_pre:
2686  case ARM::MVE_VLDRBU32_pre:
2687  case ARM::MVE_VLDRHS32_pre:
2688  case ARM::MVE_VLDRHU32_pre:
2689  case ARM::MVE_VLDRBU8_pre:
2690  case ARM::MVE_VLDRHU16_pre:
2691  case ARM::MVE_VLDRWU32_pre:
2692  case ARM::MVE_VSTRB16_pre:
2693  case ARM::MVE_VSTRB32_pre:
2694  case ARM::MVE_VSTRH32_pre:
2695  case ARM::MVE_VSTRBU8_pre:
2696  case ARM::MVE_VSTRHU16_pre:
2697  case ARM::MVE_VSTRWU32_pre:
2698  return true;
2699  }
2700  return false;
2701 }
2702 
2703 // Given a memory access Opcode, check that the give Imm would be a valid Offset
2704 // for this instruction (same as isLegalAddressImm), Or if the instruction
2705 // could be easily converted to one where that was valid. For example converting
2706 // t2LDRi12 to t2LDRi8 for negative offsets. Works in conjunction with
2707 // AdjustBaseAndOffset below.
2708 static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm,
2709  const TargetInstrInfo *TII,
2710  int &CodesizeEstimate) {
2711  if (isLegalAddressImm(Opcode, Imm, TII))
2712  return true;
2713 
2714  // We can convert AddrModeT2_i12 to AddrModeT2_i8.
2715  const MCInstrDesc &Desc = TII->get(Opcode);
2716  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2717  switch (AddrMode) {
2718  case ARMII::AddrModeT2_i12:
2719  CodesizeEstimate += 1;
2720  return std::abs(Imm) < (((1 << 8) * 1) - 1);
2721  }
2722  return false;
2723 }
2724 
2725 // Given an MI adjust its address BaseReg to use NewBaseReg and address offset
2726 // by -Offset. This can either happen in-place or be a replacement as MI is
2727 // converted to another instruction type.
2728 static void AdjustBaseAndOffset(MachineInstr *MI, Register NewBaseReg,
2729  int Offset, const TargetInstrInfo *TII) {
2730  unsigned BaseOp = getBaseOperandIndex(*MI);
2731  MI->getOperand(BaseOp).setReg(NewBaseReg);
2732  int OldOffset = MI->getOperand(BaseOp + 1).getImm();
2733  if (isLegalAddressImm(MI->getOpcode(), OldOffset - Offset, TII))
2734  MI->getOperand(BaseOp + 1).setImm(OldOffset - Offset);
2735  else {
2736  unsigned ConvOpcode;
2737  switch (MI->getOpcode()) {
2738  case ARM::t2LDRHi12:
2739  ConvOpcode = ARM::t2LDRHi8;
2740  break;
2741  case ARM::t2LDRSHi12:
2742  ConvOpcode = ARM::t2LDRSHi8;
2743  break;
2744  case ARM::t2LDRBi12:
2745  ConvOpcode = ARM::t2LDRBi8;
2746  break;
2747  case ARM::t2LDRSBi12:
2748  ConvOpcode = ARM::t2LDRSBi8;
2749  break;
2750  case ARM::t2STRHi12:
2751  ConvOpcode = ARM::t2STRHi8;
2752  break;
2753  case ARM::t2STRBi12:
2754  ConvOpcode = ARM::t2STRBi8;
2755  break;
2756  default:
2757  llvm_unreachable("Unhandled convertable opcode");
2758  }
2759  assert(isLegalAddressImm(ConvOpcode, OldOffset - Offset, TII) &&
2760  "Illegal Address Immediate after convert!");
2761 
2762  const MCInstrDesc &MCID = TII->get(ConvOpcode);
2763  BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
2764  .add(MI->getOperand(0))
2765  .add(MI->getOperand(1))
2766  .addImm(OldOffset - Offset)
2767  .add(MI->getOperand(3))
2768  .add(MI->getOperand(4))
2769  .cloneMemRefs(*MI);
2770  MI->eraseFromParent();
2771  }
2772 }
2773 
2775  Register NewReg,
2776  const TargetInstrInfo *TII,
2777  const TargetRegisterInfo *TRI) {
2778  MachineFunction *MF = MI->getMF();
2780 
2781  unsigned NewOpcode = getPostIndexedLoadStoreOpcode(
2782  MI->getOpcode(), Offset > 0 ? ARM_AM::add : ARM_AM::sub);
2783 
2784  const MCInstrDesc &MCID = TII->get(NewOpcode);
2785  // Constrain the def register class
2786  const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
2787  MRI.constrainRegClass(NewReg, TRC);
2788  // And do the same for the base operand
2789  TRC = TII->getRegClass(MCID, 2, TRI, *MF);
2790  MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC);
2791 
2792  unsigned AddrMode = (MCID.TSFlags & ARMII::AddrModeMask);
2793  switch (AddrMode) {
2794  case ARMII::AddrModeT2_i7:
2797  // Any MVE load/store
2798  return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
2799  .addReg(NewReg, RegState::Define)
2800  .add(MI->getOperand(0))
2801  .add(MI->getOperand(1))
2802  .addImm(Offset)
2803  .add(MI->getOperand(3))
2804  .add(MI->getOperand(4))
2805  .cloneMemRefs(*MI);
2806  case ARMII::AddrModeT2_i8:
2807  if (MI->mayLoad()) {
2808  return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
2809  .add(MI->getOperand(0))
2810  .addReg(NewReg, RegState::Define)
2811  .add(MI->getOperand(1))
2812  .addImm(Offset)
2813  .add(MI->getOperand(3))
2814  .add(MI->getOperand(4))
2815  .cloneMemRefs(*MI);
2816  } else {
2817  return BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), MCID)
2818  .addReg(NewReg, RegState::Define)
2819  .add(MI->getOperand(0))
2820  .add(MI->getOperand(1))
2821  .addImm(Offset)
2822  .add(MI->getOperand(3))
2823  .add(MI->getOperand(4))
2824  .cloneMemRefs(*MI);
2825  }
2826  default:
2827  llvm_unreachable("Unhandled createPostIncLoadStore");
2828  }
2829 }
2830 
2831 // Given a Base Register, optimise the load/store uses to attempt to create more
2832 // post-inc accesses and less register moves. We do this by taking zero offset
2833 // loads/stores with an add, and convert them to a postinc load/store of the
2834 // same type. Any subsequent accesses will be adjusted to use and account for
2835 // the post-inc value.
2836 // For example:
2837 // LDR #0 LDR_POSTINC #16
2838 // LDR #4 LDR #-12
2839 // LDR #8 LDR #-8
2840 // LDR #12 LDR #-4
2841 // ADD #16
2842 //
2843 // At the same time if we do not find an increment but do find an existing
2844 // pre/post inc instruction, we can still adjust the offsets of subsequent
2845 // instructions to save the register move that would otherwise be needed for the
2846 // in-place increment.
2847 bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) {
2848  // We are looking for:
2849  // One zero offset load/store that can become postinc
2850  MachineInstr *BaseAccess = nullptr;
2851  MachineInstr *PrePostInc = nullptr;
2852  // An increment that can be folded in
2853  MachineInstr *Increment = nullptr;
2854  // Other accesses after BaseAccess that will need to be updated to use the
2855  // postinc value.
2856  SmallPtrSet<MachineInstr *, 8> OtherAccesses;
2857  for (auto &Use : MRI->use_nodbg_instructions(Base)) {
2858  if (!Increment && getAddSubImmediate(Use) != 0) {
2859  Increment = &Use;
2860  continue;
2861  }
2862 
2863  int BaseOp = getBaseOperandIndex(Use);
2864  if (BaseOp == -1)
2865  return false;
2866 
2867  if (!Use.getOperand(BaseOp).isReg() ||
2868  Use.getOperand(BaseOp).getReg() != Base)
2869  return false;
2870  if (isPreIndex(Use) || isPostIndex(Use))
2871  PrePostInc = &Use;
2872  else if (Use.getOperand(BaseOp + 1).getImm() == 0)
2873  BaseAccess = &Use;
2874  else
2875  OtherAccesses.insert(&Use);
2876  }
2877 
2878  int IncrementOffset;
2879  Register NewBaseReg;
2880  if (BaseAccess && Increment) {
2881  if (PrePostInc || BaseAccess->getParent() != Increment->getParent())
2882  return false;
2883  Register PredReg;
2884  if (Increment->definesRegister(ARM::CPSR) ||
2885  getInstrPredicate(*Increment, PredReg) != ARMCC::AL)
2886  return false;
2887 
2888  LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on VirtualReg "
2889  << Base.virtRegIndex() << "\n");
2890 
2891  // Make sure that Increment has no uses before BaseAccess.
2892  for (MachineInstr &Use :
2893  MRI->use_nodbg_instructions(Increment->getOperand(0).getReg())) {
2894  if (!DT->dominates(BaseAccess, &Use) || &Use == BaseAccess) {
2895  LLVM_DEBUG(dbgs() << " BaseAccess doesn't dominate use of increment\n");
2896  return false;
2897  }
2898  }
2899 
2900  // Make sure that Increment can be folded into Base
2901  IncrementOffset = getAddSubImmediate(*Increment);
2902  unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode(
2903  BaseAccess->getOpcode(), IncrementOffset > 0 ? ARM_AM::add : ARM_AM::sub);
2904  if (!isLegalAddressImm(NewPostIncOpcode, IncrementOffset, TII)) {
2905  LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on postinc\n");
2906  return false;
2907  }
2908  }
2909  else if (PrePostInc) {
2910  // If we already have a pre/post index load/store then set BaseAccess,
2911  // IncrementOffset and NewBaseReg to the values it already produces,
2912  // allowing us to update and subsequent uses of BaseOp reg with the
2913  // incremented value.
2914  if (Increment)
2915  return false;
2916 
2917  LLVM_DEBUG(dbgs() << "\nAttempting to distribute increments on already "
2918  << "indexed VirtualReg " << Base.virtRegIndex() << "\n");
2919  int BaseOp = getBaseOperandIndex(*PrePostInc);
2920  IncrementOffset = PrePostInc->getOperand(BaseOp+1).getImm();
2921  BaseAccess = PrePostInc;
2922  NewBaseReg = PrePostInc->getOperand(0).getReg();
2923  }
2924  else
2925  return false;
2926 
2927  // And make sure that the negative value of increment can be added to all
2928  // other offsets after the BaseAccess. We rely on either
2929  // dominates(BaseAccess, OtherAccess) or dominates(OtherAccess, BaseAccess)
2930  // to keep things simple.
2931  // This also adds a simple codesize metric, to detect if an instruction (like
2932  // t2LDRBi12) which can often be shrunk to a thumb1 instruction (tLDRBi)
2933  // cannot because it is converted to something else (t2LDRBi8). We start this
2934  // at -1 for the gain from removing the increment.
2935  SmallPtrSet<MachineInstr *, 4> SuccessorAccesses;
2936  int CodesizeEstimate = -1;
2937  for (auto *Use : OtherAccesses) {
2938  if (DT->dominates(BaseAccess, Use)) {
2939  SuccessorAccesses.insert(Use);
2940  unsigned BaseOp = getBaseOperandIndex(*Use);
2941  if (!isLegalOrConvertableAddressImm(Use->getOpcode(),
2942  Use->getOperand(BaseOp + 1).getImm() -
2943  IncrementOffset,
2944  TII, CodesizeEstimate)) {
2945  LLVM_DEBUG(dbgs() << " Illegal addressing mode immediate on use\n");
2946  return false;
2947  }
2948  } else if (!DT->dominates(Use, BaseAccess)) {
2949  LLVM_DEBUG(
2950  dbgs() << " Unknown dominance relation between Base and Use\n");
2951  return false;
2952  }
2953  }
2954  if (STI->hasMinSize() && CodesizeEstimate > 0) {
2955  LLVM_DEBUG(dbgs() << " Expected to grow instructions under minsize\n");
2956  return false;
2957  }
2958 
2959  if (!PrePostInc) {
2960  // Replace BaseAccess with a post inc
2961  LLVM_DEBUG(dbgs() << "Changing: "; BaseAccess->dump());
2962  LLVM_DEBUG(dbgs() << " And : "; Increment->dump());
2963  NewBaseReg = Increment->getOperand(0).getReg();
2964  MachineInstr *BaseAccessPost =
2965  createPostIncLoadStore(BaseAccess, IncrementOffset, NewBaseReg, TII, TRI);
2966  BaseAccess->eraseFromParent();
2967  Increment->eraseFromParent();
2968  (void)BaseAccessPost;
2969  LLVM_DEBUG(dbgs() << " To : "; BaseAccessPost->dump());
2970  }
2971 
2972  for (auto *Use : SuccessorAccesses) {
2973  LLVM_DEBUG(dbgs() << "Changing: "; Use->dump());
2974  AdjustBaseAndOffset(Use, NewBaseReg, IncrementOffset, TII);
2975  LLVM_DEBUG(dbgs() << " To : "; Use->dump());
2976  }
2977 
2978  // Remove the kill flag from all uses of NewBaseReg, in case any old uses
2979  // remain.
2980  for (MachineOperand &Op : MRI->use_nodbg_operands(NewBaseReg))
2981  Op.setIsKill(false);
2982  return true;
2983 }
2984 
2985 bool ARMPreAllocLoadStoreOpt::DistributeIncrements() {
2986  bool Changed = false;
2988  for (auto &MBB : *MF) {
2989  for (auto &MI : MBB) {
2990  int BaseOp = getBaseOperandIndex(MI);
2991  if (BaseOp == -1 || !MI.getOperand(BaseOp).isReg())
2992  continue;
2993 
2994  Register Base = MI.getOperand(BaseOp).getReg();
2995  if (!Base.isVirtual() || Visited.count(Base))
2996  continue;
2997 
2998  Visited.insert(Base);
2999  }
3000  }
3001 
3002  for (auto Base : Visited)
3003  Changed |= DistributeIncrements(Base);
3004 
3005  return Changed;
3006 }
3007 
3008 /// Returns an instance of the load / store optimization pass.
3010  if (PreAlloc)
3011  return new ARMPreAllocLoadStoreOpt();
3012  return new ARMLoadStoreOpt();
3013 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
getLoadStoreRegOp
static const MachineOperand & getLoadStoreRegOp(const MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:250
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::Register::virtRegIndex
unsigned virtRegIndex() const
Convert a virtual register number to a 0-based index.
Definition: Register.h:103
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:316
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
getLoadStoreBaseOp
static const MachineOperand & getLoadStoreBaseOp(const MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:246
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
TargetFrameLowering.h
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1069
MCInstrDesc.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:697
llvm::Value::dump
void dump() const
Support for debugging, callable in GDB: V->dump()
Definition: AsmWriter.cpp:4764
Pass.h
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:497
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
llvm::ms_demangle::IntrinsicFunctionKind::LessThan
@ LessThan
llvm::MachineFunction::end
iterator end()
Definition: MachineFunction.h:739
ErrorHandling.h
llvm::MCRegisterInfo::getDwarfRegNum
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Definition: MCRegisterInfo.cpp:68
Allocator.h
ARMMachineFunctionInfo.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
isT1i32Load
static bool isT1i32Load(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:393
RegisterClassInfo.h
MachineBasicBlock.h
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
llvm::MemOp
Definition: TargetLowering.h:108
llvm::ARMISD::LDRD
@ LDRD
Definition: ARMISelLowering.h:330
llvm::MachineRegisterInfo::use_nodbg_instructions
iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const
Definition: MachineRegisterInfo.h:543
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:652
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::SpecificBumpPtrAllocator
A BumpPtrAllocator that allows only elements of a specific type to be allocated.
Definition: Allocator.h:376
getUpdatingLSMultipleOpcode
static unsigned getUpdatingLSMultipleOpcode(unsigned Opc, ARM_AM::AMSubMode Mode)
Definition: ARMLoadStoreOptimizer.cpp:1118
DenseMap.h
llvm::ARMSubtarget::getTargetLowering
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:557
TargetInstrInfo.h
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:512
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:449
findIncDecBefore
static MachineBasicBlock::iterator findIncDecBefore(MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset)
Searches for an increment or decrement of Reg before MBBI.
Definition: ARMLoadStoreOptimizer.cpp:1220
STLExtras.h
llvm::detail::DenseSetImpl::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::detail::DenseSetImpl::count
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:97
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
INITIALIZE_PASS_END
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
Definition: RegBankSelect.cpp:69
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Return true if this instruction has exactly one MachineMemOperand.
Definition: MachineInstr.h:712
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:129
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:515
MachineRegisterInfo.h
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::TargetFrameLowering::getTransientStackAlign
Align getTransientStackAlign() const
getTransientStackAlignment - This method returns the number of bytes to which the stack pointer must ...
Definition: TargetFrameLowering.h:125
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1322
AliasAnalysis.h
llvm::getAddSubImmediate
int getAddSubImmediate(MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:855
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
ContainsReg
static bool ContainsReg(const ArrayRef< std::pair< unsigned, bool >> &Regs, unsigned Reg)
Definition: ARMLoadStoreOptimizer.cpp:614
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:387
isPreIndex
static bool isPreIndex(MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:2681
CommandLine.h
TargetLowering.h
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:503
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:204
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineRegisterInfo::use_nodbg_operands
iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const
Definition: MachineRegisterInfo.h:526
llvm::ARM_AM::AddrOpc
AddrOpc
Definition: ARMAddressingModes.h:37
ARMBaseInfo.h
llvm::AAResults
Definition: AliasAnalysis.h:456
getPreIndexedLoadStoreOpcode
static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc, ARM_AM::AddrOpc Mode)
Definition: ARMLoadStoreOptimizer.cpp:1364
llvm::MachineInstr::copyImplicitOps
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition: MachineInstr.cpp:1488
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3141
IsSafeAndProfitableToMove
static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base, MachineBasicBlock::iterator I, MachineBasicBlock::iterator E, SmallPtrSetImpl< MachineInstr * > &MemOps, SmallSet< unsigned, 4 > &MemRegs, const TargetRegisterInfo *TRI, AliasAnalysis *AA)
Definition: ARMLoadStoreOptimizer.cpp:2219
llvm::ARM_AM::no_shift
@ no_shift
Definition: ARMAddressingModes.h:28
llvm::X86::FirstMacroFusionInstKind::AddSub
@ AddSub
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:205
DenseSet.h
false
Definition: StackSlotColoring.cpp:142
isIncrementOrDecrement
static int isIncrementOrDecrement(const MachineInstr &MI, Register Reg, ARMCC::CondCodes Pred, Register PredReg)
Check if the given instruction increments or decrements a register and return the amount it is increm...
Definition: ARMLoadStoreOptimizer.cpp:1188
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
opt
arm prera ldst opt
Definition: ARMLoadStoreOptimizer.cpp:2191
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:166
ARMBaseInfo.h
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
getBaseOperandIndex
static int getBaseOperandIndex(MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:2594
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:299
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
LoopDeletionResult::Modified
@ Modified
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:402
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:737
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:45
DebugLoc.h
SmallPtrSet.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
getImmScale
static unsigned getImmScale(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:421
llvm::ARMRI::RegPairEven
@ RegPairEven
Definition: ARMBaseRegisterInfo.h:37
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineInstr::killsRegister
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1376
llvm::ARM_AM::AMSubMode
AMSubMode
Definition: ARMAddressingModes.h:66
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:49
llvm::MachineFrameInfo::isCalleeSavedInfoValid
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
Definition: MachineFrameInfo.h:809
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:207
Type.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:214
isMemoryOp
static bool isMemoryOp(const MachineInstr &MI)
Returns true if instruction is a memory operation that this pass is capable of operating on.
Definition: ARMLoadStoreOptimizer.cpp:1675
getLoadStoreMultipleSubMode
static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode)
Definition: ARMLoadStoreOptimizer.cpp:339
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::DenseSet< unsigned >
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::cl::opt< bool >
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::ms_demangle::IntrinsicFunctionKind::Increment
@ Increment
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
ARMBaseRegisterInfo.h
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::getInstrPredicate
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
Definition: ARMBaseInstrInfo.cpp:2220
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:382
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:548
I
#define I(x, y, z)
Definition: MD5.cpp:59
isi32Load
static bool isi32Load(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:401
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1570
ArrayRef.h
MachineFunctionPass.h
llvm::ARMISD::STRD
@ STRD
Definition: ARMISelLowering.h:331
INITIALIZE_PASS
INITIALIZE_PASS(ARMLoadStoreOpt, "arm-ldst-opt", ARM_LOAD_STORE_OPT_NAME, false, false) static bool definesCPSR(const MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:202
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
isPostIndex
static bool isPostIndex(MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:2659
llvm::elfabi::ELFSymbolType::Func
@ Func
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::isLegalAddressImm
bool isLegalAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII)
Definition: ARMBaseInstrInfo.h:880
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
ARM_LOAD_STORE_OPT_NAME
#define ARM_LOAD_STORE_OPT_NAME
Definition: ARMLoadStoreOptimizer.cpp:95
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
ARMBaseInstrInfo.h
isT2i32Load
static bool isT2i32Load(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:397
iterator_range.h
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::WinEH::EncodingType::CE
@ CE
Windows NT (Windows on ARM)
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:98
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:206
ARM.h
llvm::MachineBasicBlock::LQR_Dead
@ LQR_Dead
Register is known to be fully dead.
Definition: MachineBasicBlock.h:928
isT1i32Store
static bool isT1i32Store(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:405
llvm::SmallPtrSetImpl::count
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
Definition: SmallPtrSet.h:382
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineInstr::dump
void dump() const
Definition: MachineInstr.cpp:1540
llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:796
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:233
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
ARMAddressingModes.h
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:859
llvm::ARM_AM::getAM3Opc
unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, unsigned IdxMode=0)
getAM3Opc - This function encodes the addrmode3 opc field.
Definition: ARMAddressingModes.h:445
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=false)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:478
cl
http eax xorl edx cl sete al setne dl sall cl
Definition: README.txt:25
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MachineRegisterInfo::setRegAllocationHint
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)
setRegAllocationHint - Specify a register allocation hint for the specified virtual register.
Definition: MachineRegisterInfo.h:765
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
llvm::MachineOperand::setIsUndef
void setIsUndef(bool Val=true)
Definition: MachineOperand.h:508
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::MachineInstrBuilder::cloneMergedMemRefs
const MachineInstrBuilder & cloneMergedMemRefs(ArrayRef< const MachineInstr * > OtherMIs) const
Definition: MachineInstrBuilder.h:220
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:90
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isLoadSingle
static bool isLoadSingle(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:417
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
AssumeMisalignedLoadStores
static cl::opt< bool > AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden, cl::init(false), cl::desc("Be more conservative in ARM load/store opt"))
This switch disables formation of double/multi instructions that could potentially lead to (new) alig...
llvm::ARM_AM::getAM2Opc
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
Definition: ARMAddressingModes.h:413
getPostIndexedLoadStoreOpcode
static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc, ARM_AM::AddrOpc Mode)
Definition: ARMLoadStoreOptimizer.cpp:1389
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
mayCombineMisaligned
static bool mayCombineMisaligned(const TargetSubtargetInfo &STI, const MachineInstr &MI)
Return true for loads/stores that can be combined to a double/multi operation without increasing the ...
Definition: ARMLoadStoreOptimizer.cpp:985
j
return j(j<< 16)
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:268
ARM_PREALLOC_LOAD_STORE_OPT_NAME
#define ARM_PREALLOC_LOAD_STORE_OPT_NAME
Definition: ARMLoadStoreOptimizer.cpp:2136
findIncDecAfter
static MachineBasicBlock::iterator findIncDecAfter(MachineBasicBlock::iterator MBBI, Register Reg, ARMCC::CondCodes Pred, Register PredReg, int &Offset, const TargetRegisterInfo *TRI)
Searches for a increment or decrement of Reg after MBBI.
Definition: ARMLoadStoreOptimizer.cpp:1240
llvm::ARM_AM::ia
@ ia
Definition: ARMAddressingModes.h:68
llvm::Type::getInt64Ty
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:205
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(ARMPreAllocLoadStoreOpt, "arm-prera-ldst-opt", ARM_PREALLOC_LOAD_STORE_OPT_NAME, false, false) INITIALIZE_PASS_END(ARMPreAllocLoadStoreOpt
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:455
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::MachineBasicBlock::computeRegisterLiveness
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
Definition: MachineBasicBlock.cpp:1508
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::ARMII::AddrModeT2_i8
@ AddrModeT2_i8
Definition: ARMBaseInfo.h:198
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
getLoadStoreMultipleOpcode
static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode)
Definition: ARMLoadStoreOptimizer.cpp:254
Function.h
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1446
llvm::ARM_AM::da
@ da
Definition: ARMAddressingModes.h:70
llvm::SetVector< T, SmallVector< T, N >, SmallDenseSet< T, N > >::count
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:215
isLegalOrConvertableAddressImm
static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm, const TargetInstrInfo *TII, int &CodesizeEstimate)
Definition: ARMLoadStoreOptimizer.cpp:2708
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:209
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:275
InsertLDR_STR
static void InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, MachineInstr *MI)
Definition: ARMLoadStoreOptimizer.cpp:1730
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
AdjustBaseAndOffset
static void AdjustBaseAndOffset(MachineInstr *MI, Register NewBaseReg, int Offset, const TargetInstrInfo *TII)
Definition: ARMLoadStoreOptimizer.cpp:2728
getMemoryOpOffset
static int getMemoryOpOffset(const MachineInstr &MI)
Definition: ARMLoadStoreOptimizer.cpp:218
llvm::ARM_AM::db
@ db
Definition: ARMAddressingModes.h:71
llvm::getAlign
bool getAlign(const Function &F, unsigned index, unsigned &align)
Definition: NVPTXUtilities.cpp:284
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:509
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
ARMISelLowering.h
InstReorderLimit
arm prera ldst static false cl::opt< unsigned > InstReorderLimit("arm-prera-ldst-opt-reorder-limit", cl::init(8), cl::Hidden)
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::SmallSet::size
size_type size() const
Definition: SmallSet.h:159
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:146
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:329
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::AAResultsWrapperPass
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
Definition: AliasAnalysis.h:1269
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:481
llvm::ARM_AM::ib
@ ib
Definition: ARMAddressingModes.h:69
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
isT2i32Store
static bool isT2i32Store(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:409
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::MachineRegisterInfo::constrainRegClass
const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)
constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...
Definition: MachineRegisterInfo.cpp:85
MachineMemOperand.h
llvm::SmallVectorImpl< MachineInstr * >
MachineOperand.h
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1731
isValidLSDoubleOffset
static bool isValidLSDoubleOffset(int Offset)
Definition: ARMLoadStoreOptimizer.cpp:976
DerivedTypes.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::SmallSetVector
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:307
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:540
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:411
llvm::M1
unsigned M1(unsigned Val)
Definition: VE.h:372
isi32Store
static bool isi32Store(unsigned Opc)
Definition: ARMLoadStoreOptimizer.cpp:413
raw_ostream.h
createPostIncLoadStore
static MachineInstr * createPostIncLoadStore(MachineInstr *MI, int Offset, Register NewReg, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: ARMLoadStoreOptimizer.cpp:2774
llvm::createARMLoadStoreOptimizationPass
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
Definition: ARMLoadStoreOptimizer.cpp:3009
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::ARMRI::RegPairOdd
@ RegPairOdd
Definition: ARMBaseRegisterInfo.h:36
MachineFunction.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< const MachineInstr >
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:64
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1272
InitializePasses.h
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::t1CondCodeOp
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
Definition: ARMBaseInstrInfo.h:555
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
SmallSet.h
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:364
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
LivePhysRegs.h
getLSMultipleTransferSize
static unsigned getLSMultipleTransferSize(const MachineInstr *MI)
Definition: ARMLoadStoreOptimizer.cpp:438