LLVM  14.0.0git
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/Debug.h"
35 #include <cstdlib>
36 
37 #define DEBUG_TYPE "x86-fl"
38 
39 STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue");
40 STATISTIC(NumFrameExtraProbe,
41  "Number of extra stack probes generated in prologue");
42 
43 using namespace llvm;
44 
46  MaybeAlign StackAlignOverride)
47  : TargetFrameLowering(StackGrowsDown, StackAlignOverride.valueOrOne(),
48  STI.is64Bit() ? -8 : -4),
49  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
50  // Cache a bunch of frame-related predicates for this subtarget.
52  Is64Bit = STI.is64Bit();
54  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
57 }
58 
60  return !MF.getFrameInfo().hasVarSizedObjects() &&
61  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences() &&
62  !MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall();
63 }
64 
65 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
66 /// call frame pseudos can be simplified. Having a FP, as in the default
67 /// implementation, is not sufficient here since we can't always use it.
68 /// Use a more nuanced condition.
69 bool
71  return hasReservedCallFrame(MF) ||
72  MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall() ||
73  (hasFP(MF) && !TRI->hasStackRealignment(MF)) ||
74  TRI->hasBasePointer(MF);
75 }
76 
77 // needsFrameIndexResolution - Do we need to perform FI resolution for
78 // this function. Normally, this is required only when the function
79 // has any stack objects. However, FI resolution actually has another job,
80 // not apparent from the title - it resolves callframesetup/destroy
81 // that were not simplified earlier.
82 // So, this is required for x86 functions that have push sequences even
83 // when there are no stack objects.
84 bool
86  return MF.getFrameInfo().hasStackObjects() ||
87  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
88 }
89 
90 /// hasFP - Return true if the specified function should have a dedicated frame
91 /// pointer register. This is true if the function has variable sized allocas
92 /// or if frame pointer elimination is disabled.
94  const MachineFrameInfo &MFI = MF.getFrameInfo();
95  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
96  TRI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
100  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
101  MFI.hasStackMap() || MFI.hasPatchPoint() ||
103 }
104 
105 static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) {
106  if (IsLP64) {
107  if (isInt<8>(Imm))
108  return X86::SUB64ri8;
109  return X86::SUB64ri32;
110  } else {
111  if (isInt<8>(Imm))
112  return X86::SUB32ri8;
113  return X86::SUB32ri;
114  }
115 }
116 
117 static unsigned getADDriOpcode(bool IsLP64, int64_t Imm) {
118  if (IsLP64) {
119  if (isInt<8>(Imm))
120  return X86::ADD64ri8;
121  return X86::ADD64ri32;
122  } else {
123  if (isInt<8>(Imm))
124  return X86::ADD32ri8;
125  return X86::ADD32ri;
126  }
127 }
128 
129 static unsigned getSUBrrOpcode(bool IsLP64) {
130  return IsLP64 ? X86::SUB64rr : X86::SUB32rr;
131 }
132 
133 static unsigned getADDrrOpcode(bool IsLP64) {
134  return IsLP64 ? X86::ADD64rr : X86::ADD32rr;
135 }
136 
137 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
138  if (IsLP64) {
139  if (isInt<8>(Imm))
140  return X86::AND64ri8;
141  return X86::AND64ri32;
142  }
143  if (isInt<8>(Imm))
144  return X86::AND32ri8;
145  return X86::AND32ri;
146 }
147 
148 static unsigned getLEArOpcode(bool IsLP64) {
149  return IsLP64 ? X86::LEA64r : X86::LEA32r;
150 }
151 
154  unsigned Reg = RegMask.PhysReg;
155 
156  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
157  Reg == X86::AH || Reg == X86::AL)
158  return true;
159  }
160 
161  return false;
162 }
163 
164 /// Check if the flags need to be preserved before the terminators.
165 /// This would be the case, if the eflags is live-in of the region
166 /// composed by the terminators or live-out of that region, without
167 /// being defined by a terminator.
168 static bool
170  for (const MachineInstr &MI : MBB.terminators()) {
171  bool BreakNext = false;
172  for (const MachineOperand &MO : MI.operands()) {
173  if (!MO.isReg())
174  continue;
175  Register Reg = MO.getReg();
176  if (Reg != X86::EFLAGS)
177  continue;
178 
179  // This terminator needs an eflags that is not defined
180  // by a previous another terminator:
181  // EFLAGS is live-in of the region composed by the terminators.
182  if (!MO.isDef())
183  return true;
184  // This terminator defines the eflags, i.e., we don't need to preserve it.
185  // However, we still need to check this specific terminator does not
186  // read a live-in value.
187  BreakNext = true;
188  }
189  // We found a definition of the eflags, no need to preserve them.
190  if (BreakNext)
191  return false;
192  }
193 
194  // None of the terminators use or define the eflags.
195  // Check if they are live-out, that would imply we need to preserve them.
196  for (const MachineBasicBlock *Succ : MBB.successors())
197  if (Succ->isLiveIn(X86::EFLAGS))
198  return true;
199 
200  return false;
201 }
202 
203 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
204 /// stack pointer by a constant value.
207  const DebugLoc &DL,
208  int64_t NumBytes, bool InEpilogue) const {
209  bool isSub = NumBytes < 0;
210  uint64_t Offset = isSub ? -NumBytes : NumBytes;
213 
214  uint64_t Chunk = (1LL << 31) - 1;
215 
216  MachineFunction &MF = *MBB.getParent();
217  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
218  const X86TargetLowering &TLI = *STI.getTargetLowering();
219  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
220 
221  // It's ok to not take into account large chunks when probing, as the
222  // allocation is split in smaller chunks anyway.
223  if (EmitInlineStackProbe && !InEpilogue) {
224 
225  // This pseudo-instruction is going to be expanded, potentially using a
226  // loop, by inlineStackProbe().
227  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset);
228  return;
229  } else if (Offset > Chunk) {
230  // Rather than emit a long series of instructions for large offsets,
231  // load the offset into a register and do one sub/add
232  unsigned Reg = 0;
233  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
234 
235  if (isSub && !isEAXLiveIn(MBB))
236  Reg = Rax;
237  else
239 
240  unsigned MovRIOpc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
241  unsigned AddSubRROpc =
243  if (Reg) {
244  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
245  .addImm(Offset)
246  .setMIFlag(Flag);
247  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
248  .addReg(StackPtr)
249  .addReg(Reg);
250  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
251  return;
252  } else if (Offset > 8 * Chunk) {
253  // If we would need more than 8 add or sub instructions (a >16GB stack
254  // frame), it's worth spilling RAX to materialize this immediate.
255  // pushq %rax
256  // movabsq +-$Offset+-SlotSize, %rax
257  // addq %rsp, %rax
258  // xchg %rax, (%rsp)
259  // movq (%rsp), %rsp
260  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
261  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
262  .addReg(Rax, RegState::Kill)
263  .setMIFlag(Flag);
264  // Subtract is not commutative, so negate the offset and always use add.
265  // Subtract 8 less and add 8 more to account for the PUSH we just did.
266  if (isSub)
267  Offset = -(Offset - SlotSize);
268  else
269  Offset = Offset + SlotSize;
270  BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
271  .addImm(Offset)
272  .setMIFlag(Flag);
273  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
274  .addReg(Rax)
275  .addReg(StackPtr);
276  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
277  // Exchange the new SP in RAX with the top of the stack.
278  addRegOffset(
279  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
280  StackPtr, false, 0);
281  // Load new SP from the top of the stack into RSP.
282  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
283  StackPtr, false, 0);
284  return;
285  }
286  }
287 
288  while (Offset) {
289  uint64_t ThisVal = std::min(Offset, Chunk);
290  if (ThisVal == SlotSize) {
291  // Use push / pop for slot sized adjustments as a size optimization. We
292  // need to find a dead register when using pop.
293  unsigned Reg = isSub
294  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
296  if (Reg) {
297  unsigned Opc = isSub
298  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
299  : (Is64Bit ? X86::POP64r : X86::POP32r);
300  BuildMI(MBB, MBBI, DL, TII.get(Opc))
301  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
302  .setMIFlag(Flag);
303  Offset -= ThisVal;
304  continue;
305  }
306  }
307 
308  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
309  .setMIFlag(Flag);
310 
311  Offset -= ThisVal;
312  }
313 }
314 
315 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
317  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
318  assert(Offset != 0 && "zero offset stack adjustment requested");
319 
320  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
321  // is tricky.
322  bool UseLEA;
323  if (!InEpilogue) {
324  // Check if inserting the prologue at the beginning
325  // of MBB would require to use LEA operations.
326  // We need to use LEA operations if EFLAGS is live in, because
327  // it means an instruction will read it before it gets defined.
328  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
329  } else {
330  // If we can use LEA for SP but we shouldn't, check that none
331  // of the terminators uses the eflags. Otherwise we will insert
332  // a ADD that will redefine the eflags and break the condition.
333  // Alternatively, we could move the ADD, but this may not be possible
334  // and is an optimization anyway.
336  if (UseLEA && !STI.useLeaForSP())
338  // If that assert breaks, that means we do not do the right thing
339  // in canUseAsEpilogue.
341  "We shouldn't have allowed this insertion point");
342  }
343 
345  if (UseLEA) {
348  StackPtr),
349  StackPtr, false, Offset);
350  } else {
351  bool IsSub = Offset < 0;
352  uint64_t AbsOffset = IsSub ? -Offset : Offset;
353  const unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
354  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
355  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
356  .addReg(StackPtr)
357  .addImm(AbsOffset);
358  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
359  }
360  return MI;
361 }
362 
365  bool doMergeWithPrevious) const {
366  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
367  (!doMergeWithPrevious && MBBI == MBB.end()))
368  return 0;
369 
370  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
371 
373  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
374  // instruction, and that there are no DBG_VALUE or other instructions between
375  // ADD/SUB/LEA and its corresponding CFI instruction.
376  /* TODO: Add support for the case where there are multiple CFI instructions
377  below the ADD/SUB/LEA, e.g.:
378  ...
379  add
380  cfi_def_cfa_offset
381  cfi_offset
382  ...
383  */
384  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
385  PI = std::prev(PI);
386 
387  unsigned Opc = PI->getOpcode();
388  int Offset = 0;
389 
390  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
391  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
392  PI->getOperand(0).getReg() == StackPtr){
393  assert(PI->getOperand(1).getReg() == StackPtr);
394  Offset = PI->getOperand(2).getImm();
395  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
396  PI->getOperand(0).getReg() == StackPtr &&
397  PI->getOperand(1).getReg() == StackPtr &&
398  PI->getOperand(2).getImm() == 1 &&
399  PI->getOperand(3).getReg() == X86::NoRegister &&
400  PI->getOperand(5).getReg() == X86::NoRegister) {
401  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
402  Offset = PI->getOperand(4).getImm();
403  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
404  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
405  PI->getOperand(0).getReg() == StackPtr) {
406  assert(PI->getOperand(1).getReg() == StackPtr);
407  Offset = -PI->getOperand(2).getImm();
408  } else
409  return 0;
410 
411  PI = MBB.erase(PI);
412  if (PI != MBB.end() && PI->isCFIInstruction()) {
413  auto CIs = MBB.getParent()->getFrameInstructions();
414  MCCFIInstruction CI = CIs[PI->getOperand(0).getCFIIndex()];
417  PI = MBB.erase(PI);
418  }
419  if (!doMergeWithPrevious)
421 
422  return Offset;
423 }
424 
427  const DebugLoc &DL,
428  const MCCFIInstruction &CFIInst) const {
429  MachineFunction &MF = *MBB.getParent();
430  unsigned CFIIndex = MF.addFrameInst(CFIInst);
431  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
432  .addCFIIndex(CFIIndex);
433 }
434 
435 /// Emits Dwarf Info specifying offsets of callee saved registers and
436 /// frame pointer. This is called only when basic block sections are enabled.
439  MachineFunction &MF = *MBB.getParent();
440  if (!hasFP(MF)) {
442  return;
443  }
444  const MachineModuleInfo &MMI = MF.getMMI();
445  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
446  const Register FramePtr = TRI->getFrameRegister(MF);
447  const Register MachineFramePtr =
449  : FramePtr;
450  unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true);
451  // Offset = space for return address + size of the frame pointer itself.
452  unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
454  MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset));
456 }
457 
460  const DebugLoc &DL, bool IsPrologue) const {
461  MachineFunction &MF = *MBB.getParent();
462  MachineFrameInfo &MFI = MF.getFrameInfo();
463  MachineModuleInfo &MMI = MF.getMMI();
464  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
465 
466  // Add callee saved registers to move list.
467  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
468  if (CSI.empty()) return;
469 
470  // Calculate offsets.
471  for (std::vector<CalleeSavedInfo>::const_iterator
472  I = CSI.begin(), E = CSI.end(); I != E; ++I) {
473  int64_t Offset = MFI.getObjectOffset(I->getFrameIdx());
474  unsigned Reg = I->getReg();
475  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
476 
477  if (IsPrologue) {
478  BuildCFI(MBB, MBBI, DL,
479  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
480  } else {
481  BuildCFI(MBB, MBBI, DL,
482  MCCFIInstruction::createRestore(nullptr, DwarfReg));
483  }
484  }
485 }
486 
490  const DebugLoc &DL, bool InProlog) const {
491  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
492  if (STI.isTargetWindowsCoreCLR()) {
493  if (InProlog) {
494  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING))
495  .addImm(0 /* no explicit stack size */);
496  } else {
497  emitStackProbeInline(MF, MBB, MBBI, DL, false);
498  }
499  } else {
500  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
501  }
502 }
503 
505  MachineBasicBlock &PrologMBB) const {
506  auto Where = llvm::find_if(PrologMBB, [](MachineInstr &MI) {
507  return MI.getOpcode() == X86::STACKALLOC_W_PROBING;
508  });
509  if (Where != PrologMBB.end()) {
510  DebugLoc DL = PrologMBB.findDebugLoc(Where);
511  emitStackProbeInline(MF, PrologMBB, Where, DL, true);
512  Where->eraseFromParent();
513  }
514 }
515 
516 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
519  const DebugLoc &DL,
520  bool InProlog) const {
521  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
523  emitStackProbeInlineWindowsCoreCLR64(MF, MBB, MBBI, DL, InProlog);
524  else
525  emitStackProbeInlineGeneric(MF, MBB, MBBI, DL, InProlog);
526 }
527 
528 void X86FrameLowering::emitStackProbeInlineGeneric(
530  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
531  MachineInstr &AllocWithProbe = *MBBI;
532  uint64_t Offset = AllocWithProbe.getOperand(0).getImm();
533 
534  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
535  const X86TargetLowering &TLI = *STI.getTargetLowering();
537  "different expansion expected for CoreCLR 64 bit");
538 
539  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
540  uint64_t ProbeChunk = StackProbeSize * 8;
541 
542  uint64_t MaxAlign =
543  TRI->hasStackRealignment(MF) ? calculateMaxStackAlign(MF) : 0;
544 
545  // Synthesize a loop or unroll it, depending on the number of iterations.
546  // BuildStackAlignAND ensures that only MaxAlign % StackProbeSize bits left
547  // between the unaligned rsp and current rsp.
548  if (Offset > ProbeChunk) {
549  emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL, Offset,
550  MaxAlign % StackProbeSize);
551  } else {
552  emitStackProbeInlineGenericBlock(MF, MBB, MBBI, DL, Offset,
553  MaxAlign % StackProbeSize);
554  }
555 }
556 
557 void X86FrameLowering::emitStackProbeInlineGenericBlock(
560  uint64_t AlignOffset) const {
561 
562  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
563  const bool HasFP = hasFP(MF);
564  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
565  const X86TargetLowering &TLI = *STI.getTargetLowering();
566  const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, Offset);
567  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
568  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
569 
570  uint64_t CurrentOffset = 0;
571 
572  assert(AlignOffset < StackProbeSize);
573 
574  // If the offset is so small it fits within a page, there's nothing to do.
575  if (StackProbeSize < Offset + AlignOffset) {
576 
577  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
578  .addReg(StackPtr)
579  .addImm(StackProbeSize - AlignOffset)
581  if (!HasFP && NeedsDwarfCFI) {
582  BuildCFI(MBB, MBBI, DL,
584  nullptr, StackProbeSize - AlignOffset));
585  }
586  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
587 
588  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
590  StackPtr, false, 0)
591  .addImm(0)
593  NumFrameExtraProbe++;
594  CurrentOffset = StackProbeSize - AlignOffset;
595  }
596 
597  // For the next N - 1 pages, just probe. I tried to take advantage of
598  // natural probes but it implies much more logic and there was very few
599  // interesting natural probes to interleave.
600  while (CurrentOffset + StackProbeSize < Offset) {
601  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
602  .addReg(StackPtr)
603  .addImm(StackProbeSize)
605  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
606 
607  if (!HasFP && NeedsDwarfCFI) {
608  BuildCFI(
609  MBB, MBBI, DL,
610  MCCFIInstruction::createAdjustCfaOffset(nullptr, StackProbeSize));
611  }
612  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
614  StackPtr, false, 0)
615  .addImm(0)
617  NumFrameExtraProbe++;
618  CurrentOffset += StackProbeSize;
619  }
620 
621  // No need to probe the tail, it is smaller than a Page.
622  uint64_t ChunkSize = Offset - CurrentOffset;
623  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
624  .addReg(StackPtr)
625  .addImm(ChunkSize)
627  // No need to adjust Dwarf CFA offset here, the last position of the stack has
628  // been defined
629  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
630 }
631 
632 void X86FrameLowering::emitStackProbeInlineGenericLoop(
635  uint64_t AlignOffset) const {
636  assert(Offset && "null offset");
637 
638  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
639  const X86TargetLowering &TLI = *STI.getTargetLowering();
640  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
641  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
642 
643  if (AlignOffset) {
644  if (AlignOffset < StackProbeSize) {
645  // Perform a first smaller allocation followed by a probe.
646  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, AlignOffset);
647  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), StackPtr)
648  .addReg(StackPtr)
649  .addImm(AlignOffset)
651  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
652 
653  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
655  StackPtr, false, 0)
656  .addImm(0)
658  NumFrameExtraProbe++;
659  Offset -= AlignOffset;
660  }
661  }
662 
663  // Synthesize a loop
664  NumFrameLoopProbe++;
665  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
666 
667  MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
668  MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
669 
671  MF.insert(MBBIter, testMBB);
672  MF.insert(MBBIter, tailMBB);
673 
674  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
675  : Is64Bit ? X86::R11D
676  : X86::EAX;
677  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
678  .addReg(StackPtr)
680 
681  // save loop bound
682  {
683  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, Offset);
684  BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), FinalStackProbed)
685  .addReg(FinalStackProbed)
686  .addImm(Offset / StackProbeSize * StackProbeSize)
688  }
689 
690  // allocate a page
691  {
692  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
693  BuildMI(testMBB, DL, TII.get(SUBOpc), StackPtr)
694  .addReg(StackPtr)
695  .addImm(StackProbeSize)
697  }
698 
699  // touch the page
700  addRegOffset(BuildMI(testMBB, DL, TII.get(MovMIOpc))
702  StackPtr, false, 0)
703  .addImm(0)
705 
706  // cmp with stack pointer bound
707  BuildMI(testMBB, DL, TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
708  .addReg(StackPtr)
709  .addReg(FinalStackProbed)
711 
712  // jump
713  BuildMI(testMBB, DL, TII.get(X86::JCC_1))
714  .addMBB(testMBB)
717  testMBB->addSuccessor(testMBB);
718  testMBB->addSuccessor(tailMBB);
719 
720  // BB management
721  tailMBB->splice(tailMBB->end(), &MBB, MBBI, MBB.end());
723  MBB.addSuccessor(testMBB);
724 
725  // handle tail
726  unsigned TailOffset = Offset % StackProbeSize;
727  if (TailOffset) {
728  const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, TailOffset);
729  BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(Opc), StackPtr)
730  .addReg(StackPtr)
731  .addImm(TailOffset)
733  }
734 
735  // Update Live In information
736  recomputeLiveIns(*testMBB);
737  recomputeLiveIns(*tailMBB);
738 }
739 
740 void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
742  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
743  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
744  assert(STI.is64Bit() && "different expansion needed for 32 bit");
745  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
746  const TargetInstrInfo &TII = *STI.getInstrInfo();
747  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
748 
749  // RAX contains the number of bytes of desired stack adjustment.
750  // The handling here assumes this value has already been updated so as to
751  // maintain stack alignment.
752  //
753  // We need to exit with RSP modified by this amount and execute suitable
754  // page touches to notify the OS that we're growing the stack responsibly.
755  // All stack probing must be done without modifying RSP.
756  //
757  // MBB:
758  // SizeReg = RAX;
759  // ZeroReg = 0
760  // CopyReg = RSP
761  // Flags, TestReg = CopyReg - SizeReg
762  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
763  // LimitReg = gs magic thread env access
764  // if FinalReg >= LimitReg goto ContinueMBB
765  // RoundBB:
766  // RoundReg = page address of FinalReg
767  // LoopMBB:
768  // LoopReg = PHI(LimitReg,ProbeReg)
769  // ProbeReg = LoopReg - PageSize
770  // [ProbeReg] = 0
771  // if (ProbeReg > RoundReg) goto LoopMBB
772  // ContinueMBB:
773  // RSP = RSP - RAX
774  // [rest of original MBB]
775 
776  // Set up the new basic blocks
777  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
778  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
779  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
780 
781  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
782  MF.insert(MBBIter, RoundMBB);
783  MF.insert(MBBIter, LoopMBB);
784  MF.insert(MBBIter, ContinueMBB);
785 
786  // Split MBB and move the tail portion down to ContinueMBB.
787  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
788  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
789  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
790 
791  // Some useful constants
792  const int64_t ThreadEnvironmentStackLimit = 0x10;
793  const int64_t PageSize = 0x1000;
794  const int64_t PageMask = ~(PageSize - 1);
795 
796  // Registers we need. For the normal case we use virtual
797  // registers. For the prolog expansion we use RAX, RCX and RDX.
799  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
800  const Register SizeReg = InProlog ? X86::RAX
801  : MRI.createVirtualRegister(RegClass),
802  ZeroReg = InProlog ? X86::RCX
803  : MRI.createVirtualRegister(RegClass),
804  CopyReg = InProlog ? X86::RDX
805  : MRI.createVirtualRegister(RegClass),
806  TestReg = InProlog ? X86::RDX
807  : MRI.createVirtualRegister(RegClass),
808  FinalReg = InProlog ? X86::RDX
809  : MRI.createVirtualRegister(RegClass),
810  RoundedReg = InProlog ? X86::RDX
811  : MRI.createVirtualRegister(RegClass),
812  LimitReg = InProlog ? X86::RCX
813  : MRI.createVirtualRegister(RegClass),
814  JoinReg = InProlog ? X86::RCX
815  : MRI.createVirtualRegister(RegClass),
816  ProbeReg = InProlog ? X86::RCX
817  : MRI.createVirtualRegister(RegClass);
818 
819  // SP-relative offsets where we can save RCX and RDX.
820  int64_t RCXShadowSlot = 0;
821  int64_t RDXShadowSlot = 0;
822 
823  // If inlining in the prolog, save RCX and RDX.
824  if (InProlog) {
825  // Compute the offsets. We need to account for things already
826  // pushed onto the stack at this point: return address, frame
827  // pointer (if used), and callee saves.
829  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
830  const bool HasFP = hasFP(MF);
831 
832  // Check if we need to spill RCX and/or RDX.
833  // Here we assume that no earlier prologue instruction changes RCX and/or
834  // RDX, so checking the block live-ins is enough.
835  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
836  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
837  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
838  // Assign the initial slot to both registers, then change RDX's slot if both
839  // need to be spilled.
840  if (IsRCXLiveIn)
841  RCXShadowSlot = InitSlot;
842  if (IsRDXLiveIn)
843  RDXShadowSlot = InitSlot;
844  if (IsRDXLiveIn && IsRCXLiveIn)
845  RDXShadowSlot += 8;
846  // Emit the saves if needed.
847  if (IsRCXLiveIn)
848  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
849  RCXShadowSlot)
850  .addReg(X86::RCX);
851  if (IsRDXLiveIn)
852  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
853  RDXShadowSlot)
854  .addReg(X86::RDX);
855  } else {
856  // Not in the prolog. Copy RAX to a virtual reg.
857  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
858  }
859 
860  // Add code to MBB to check for overflow and set the new target stack pointer
861  // to zero if so.
862  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
863  .addReg(ZeroReg, RegState::Undef)
864  .addReg(ZeroReg, RegState::Undef);
865  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
866  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
867  .addReg(CopyReg)
868  .addReg(SizeReg);
869  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
870  .addReg(TestReg)
871  .addReg(ZeroReg)
873 
874  // FinalReg now holds final stack pointer value, or zero if
875  // allocation would overflow. Compare against the current stack
876  // limit from the thread environment block. Note this limit is the
877  // lowest touched page on the stack, not the point at which the OS
878  // will cause an overflow exception, so this is just an optimization
879  // to avoid unnecessarily touching pages that are below the current
880  // SP but already committed to the stack by the OS.
881  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
882  .addReg(0)
883  .addImm(1)
884  .addReg(0)
885  .addImm(ThreadEnvironmentStackLimit)
886  .addReg(X86::GS);
887  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
888  // Jump if the desired stack pointer is at or above the stack limit.
889  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
890 
891  // Add code to roundMBB to round the final stack pointer to a page boundary.
892  RoundMBB->addLiveIn(FinalReg);
893  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
894  .addReg(FinalReg)
895  .addImm(PageMask);
896  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
897 
898  // LimitReg now holds the current stack limit, RoundedReg page-rounded
899  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
900  // and probe until we reach RoundedReg.
901  if (!InProlog) {
902  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
903  .addReg(LimitReg)
904  .addMBB(RoundMBB)
905  .addReg(ProbeReg)
906  .addMBB(LoopMBB);
907  }
908 
909  LoopMBB->addLiveIn(JoinReg);
910  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
911  false, -PageSize);
912 
913  // Probe by storing a byte onto the stack.
914  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
915  .addReg(ProbeReg)
916  .addImm(1)
917  .addReg(0)
918  .addImm(0)
919  .addReg(0)
920  .addImm(0);
921 
922  LoopMBB->addLiveIn(RoundedReg);
923  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
924  .addReg(RoundedReg)
925  .addReg(ProbeReg);
926  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
927 
928  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
929 
930  // If in prolog, restore RDX and RCX.
931  if (InProlog) {
932  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
933  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
934  TII.get(X86::MOV64rm), X86::RCX),
935  X86::RSP, false, RCXShadowSlot);
936  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
937  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
938  TII.get(X86::MOV64rm), X86::RDX),
939  X86::RSP, false, RDXShadowSlot);
940  }
941 
942  // Now that the probing is done, add code to continueMBB to update
943  // the stack pointer for real.
944  ContinueMBB->addLiveIn(SizeReg);
945  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
946  .addReg(X86::RSP)
947  .addReg(SizeReg);
948 
949  // Add the control flow edges we need.
950  MBB.addSuccessor(ContinueMBB);
951  MBB.addSuccessor(RoundMBB);
952  RoundMBB->addSuccessor(LoopMBB);
953  LoopMBB->addSuccessor(ContinueMBB);
954  LoopMBB->addSuccessor(LoopMBB);
955 
956  // Mark all the instructions added to the prolog as frame setup.
957  if (InProlog) {
958  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
959  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
960  }
961  for (MachineInstr &MI : *RoundMBB) {
962  MI.setFlag(MachineInstr::FrameSetup);
963  }
964  for (MachineInstr &MI : *LoopMBB) {
965  MI.setFlag(MachineInstr::FrameSetup);
966  }
967  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
968  CMBBI != ContinueMBBI; ++CMBBI) {
969  CMBBI->setFlag(MachineInstr::FrameSetup);
970  }
971  }
972 }
973 
974 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
977  const DebugLoc &DL,
978  bool InProlog) const {
979  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
980 
981  // FIXME: Add indirect thunk support and remove this.
982  if (Is64Bit && IsLargeCodeModel && STI.useIndirectThunkCalls())
983  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
984  "code model and indirect thunks not yet implemented.");
985 
986  unsigned CallOp;
987  if (Is64Bit)
988  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
989  else
990  CallOp = X86::CALLpcrel32;
991 
993 
995  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
996 
997  // All current stack probes take AX and SP as input, clobber flags, and
998  // preserve all registers. x86_64 probes leave RSP unmodified.
999  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1000  // For the large code model, we have to call through a register. Use R11,
1001  // as it is scratch in all supported calling conventions.
1002  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
1004  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
1005  } else {
1006  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
1008  }
1009 
1010  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
1011  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
1012  CI.addReg(AX, RegState::Implicit)
1016  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1017 
1018  if (STI.isTargetWin64() || !STI.isOSWindows()) {
1019  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
1020  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
1021  // themselves. They also does not clobber %rax so we can reuse it when
1022  // adjusting %rsp.
1023  // All other platforms do not specify a particular ABI for the stack probe
1024  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
1026  .addReg(SP)
1027  .addReg(AX);
1028  }
1029 
1030  if (InProlog) {
1031  // Apply the frame setup flag to all inserted instrs.
1032  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
1033  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
1034  }
1035 }
1036 
1037 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
1038  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
1039  // and might require smaller successive adjustments.
1040  const uint64_t Win64MaxSEHOffset = 128;
1041  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
1042  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
1043  return SEHFrameOffset & -16;
1044 }
1045 
1046 // If we're forcing a stack realignment we can't rely on just the frame
1047 // info, we need to know the ABI stack alignment as well in case we
1048 // have a call out. Otherwise just make sure we have some alignment - we'll
1049 // go with the minimum SlotSize.
1050 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
1051  const MachineFrameInfo &MFI = MF.getFrameInfo();
1052  Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
1054  if (MF.getFunction().hasFnAttribute("stackrealign")) {
1055  if (MFI.hasCalls())
1056  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1057  else if (MaxAlign < SlotSize)
1058  MaxAlign = Align(SlotSize);
1059  }
1060  return MaxAlign.value();
1061 }
1062 
1063 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
1065  const DebugLoc &DL, unsigned Reg,
1066  uint64_t MaxAlign) const {
1067  uint64_t Val = -MaxAlign;
1068  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
1069 
1070  MachineFunction &MF = *MBB.getParent();
1071  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1072  const X86TargetLowering &TLI = *STI.getTargetLowering();
1073  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
1074  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
1075 
1076  // We want to make sure that (in worst case) less than StackProbeSize bytes
1077  // are not probed after the AND. This assumption is used in
1078  // emitStackProbeInlineGeneric.
1079  if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
1080  {
1081  NumFrameLoopProbe++;
1082  MachineBasicBlock *entryMBB =
1084  MachineBasicBlock *headMBB =
1086  MachineBasicBlock *bodyMBB =
1088  MachineBasicBlock *footMBB =
1090 
1092  MF.insert(MBBIter, entryMBB);
1093  MF.insert(MBBIter, headMBB);
1094  MF.insert(MBBIter, bodyMBB);
1095  MF.insert(MBBIter, footMBB);
1096  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
1097  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
1098  : Is64Bit ? X86::R11D
1099  : X86::EAX;
1100 
1101  // Setup entry block
1102  {
1103 
1104  entryMBB->splice(entryMBB->end(), &MBB, MBB.begin(), MBBI);
1105  BuildMI(entryMBB, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
1106  .addReg(StackPtr)
1108  MachineInstr *MI =
1109  BuildMI(entryMBB, DL, TII.get(AndOp), FinalStackProbed)
1110  .addReg(FinalStackProbed)
1111  .addImm(Val)
1113 
1114  // The EFLAGS implicit def is dead.
1115  MI->getOperand(3).setIsDead();
1116 
1117  BuildMI(entryMBB, DL,
1118  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1119  .addReg(FinalStackProbed)
1120  .addReg(StackPtr)
1122  BuildMI(entryMBB, DL, TII.get(X86::JCC_1))
1123  .addMBB(&MBB)
1126  entryMBB->addSuccessor(headMBB);
1127  entryMBB->addSuccessor(&MBB);
1128  }
1129 
1130  // Loop entry block
1131 
1132  {
1133  const unsigned SUBOpc =
1134  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1135  BuildMI(headMBB, DL, TII.get(SUBOpc), StackPtr)
1136  .addReg(StackPtr)
1137  .addImm(StackProbeSize)
1139 
1140  BuildMI(headMBB, DL,
1141  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1142  .addReg(FinalStackProbed)
1143  .addReg(StackPtr)
1145 
1146  // jump
1147  BuildMI(headMBB, DL, TII.get(X86::JCC_1))
1148  .addMBB(footMBB)
1151 
1152  headMBB->addSuccessor(bodyMBB);
1153  headMBB->addSuccessor(footMBB);
1154  }
1155 
1156  // setup loop body
1157  {
1158  addRegOffset(BuildMI(bodyMBB, DL, TII.get(MovMIOpc))
1160  StackPtr, false, 0)
1161  .addImm(0)
1163 
1164  const unsigned SUBOpc =
1165  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1166  BuildMI(bodyMBB, DL, TII.get(SUBOpc), StackPtr)
1167  .addReg(StackPtr)
1168  .addImm(StackProbeSize)
1170 
1171  // cmp with stack pointer bound
1172  BuildMI(bodyMBB, DL,
1173  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1174  .addReg(FinalStackProbed)
1175  .addReg(StackPtr)
1177 
1178  // jump
1179  BuildMI(bodyMBB, DL, TII.get(X86::JCC_1))
1180  .addMBB(bodyMBB)
1183  bodyMBB->addSuccessor(bodyMBB);
1184  bodyMBB->addSuccessor(footMBB);
1185  }
1186 
1187  // setup loop footer
1188  {
1189  BuildMI(footMBB, DL, TII.get(TargetOpcode::COPY), StackPtr)
1190  .addReg(FinalStackProbed)
1192  addRegOffset(BuildMI(footMBB, DL, TII.get(MovMIOpc))
1194  StackPtr, false, 0)
1195  .addImm(0)
1197  footMBB->addSuccessor(&MBB);
1198  }
1199 
1200  recomputeLiveIns(*headMBB);
1201  recomputeLiveIns(*bodyMBB);
1202  recomputeLiveIns(*footMBB);
1204  }
1205  } else {
1206  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1207  .addReg(Reg)
1208  .addImm(Val)
1210 
1211  // The EFLAGS implicit def is dead.
1212  MI->getOperand(3).setIsDead();
1213  }
1214 }
1215 
1217  // x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
1218  // clobbered by any interrupt handler.
1219  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1220  "MF used frame lowering for wrong subtarget");
1221  const Function &Fn = MF.getFunction();
1222  const bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
1223  return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone);
1224 }
1225 
1226 bool X86FrameLowering::isWin64Prologue(const MachineFunction &MF) const {
1227  return MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1228 }
1229 
1230 bool X86FrameLowering::needsDwarfCFI(const MachineFunction &MF) const {
1231  return !isWin64Prologue(MF) && MF.needsFrameMoves();
1232 }
1233 
1234 /// emitPrologue - Push callee-saved registers onto the stack, which
1235 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
1236 /// space for local variables. Also emit labels used by the exception handler to
1237 /// generate the exception handling frames.
1238 
1239 /*
1240  Here's a gist of what gets emitted:
1241 
1242  ; Establish frame pointer, if needed
1243  [if needs FP]
1244  push %rbp
1245  .cfi_def_cfa_offset 16
1246  .cfi_offset %rbp, -16
1247  .seh_pushreg %rpb
1248  mov %rsp, %rbp
1249  .cfi_def_cfa_register %rbp
1250 
1251  ; Spill general-purpose registers
1252  [for all callee-saved GPRs]
1253  pushq %<reg>
1254  [if not needs FP]
1255  .cfi_def_cfa_offset (offset from RETADDR)
1256  .seh_pushreg %<reg>
1257 
1258  ; If the required stack alignment > default stack alignment
1259  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
1260  ; of unknown size in the stack frame.
1261  [if stack needs re-alignment]
1262  and $MASK, %rsp
1263 
1264  ; Allocate space for locals
1265  [if target is Windows and allocated space > 4096 bytes]
1266  ; Windows needs special care for allocations larger
1267  ; than one page.
1268  mov $NNN, %rax
1269  call ___chkstk_ms/___chkstk
1270  sub %rax, %rsp
1271  [else]
1272  sub $NNN, %rsp
1273 
1274  [if needs FP]
1275  .seh_stackalloc (size of XMM spill slots)
1276  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
1277  [else]
1278  .seh_stackalloc NNN
1279 
1280  ; Spill XMMs
1281  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
1282  ; they may get spilled on any platform, if the current function
1283  ; calls @llvm.eh.unwind.init
1284  [if needs FP]
1285  [for all callee-saved XMM registers]
1286  movaps %<xmm reg>, -MMM(%rbp)
1287  [for all callee-saved XMM registers]
1288  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
1289  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
1290  [else]
1291  [for all callee-saved XMM registers]
1292  movaps %<xmm reg>, KKK(%rsp)
1293  [for all callee-saved XMM registers]
1294  .seh_savexmm %<xmm reg>, KKK
1295 
1296  .seh_endprologue
1297 
1298  [if needs base pointer]
1299  mov %rsp, %rbx
1300  [if needs to restore base pointer]
1301  mov %rsp, -MMM(%rbp)
1302 
1303  ; Emit CFI info
1304  [if needs FP]
1305  [for all callee-saved registers]
1306  .cfi_offset %<reg>, (offset from %rbp)
1307  [else]
1308  .cfi_def_cfa_offset (offset from RETADDR)
1309  [for all callee-saved registers]
1310  .cfi_offset %<reg>, (offset from %rsp)
1311 
1312  Notes:
1313  - .seh directives are emitted only for Windows 64 ABI
1314  - .cv_fpo directives are emitted on win32 when emitting CodeView
1315  - .cfi directives are emitted for all other ABIs
1316  - for 32-bit code, substitute %e?? registers for %r??
1317 */
1318 
1320  MachineBasicBlock &MBB) const {
1321  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1322  "MF used frame lowering for wrong subtarget");
1324  MachineFrameInfo &MFI = MF.getFrameInfo();
1325  const Function &Fn = MF.getFunction();
1326  MachineModuleInfo &MMI = MF.getMMI();
1328  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
1329  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
1330  bool IsFunclet = MBB.isEHFuncletEntry();
1331  EHPersonality Personality = EHPersonality::Unknown;
1332  if (Fn.hasPersonalityFn())
1333  Personality = classifyEHPersonality(Fn.getPersonalityFn());
1334  bool FnHasClrFunclet =
1335  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
1336  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
1337  bool HasFP = hasFP(MF);
1338  bool IsWin64Prologue = isWin64Prologue(MF);
1339  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
1340  // FIXME: Emit FPO data for EH funclets.
1341  bool NeedsWinFPO =
1342  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
1343  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
1344  bool NeedsDwarfCFI = needsDwarfCFI(MF);
1345  Register FramePtr = TRI->getFrameRegister(MF);
1346  const Register MachineFramePtr =
1348  ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
1349  Register BasePtr = TRI->getBaseRegister();
1350  bool HasWinCFI = false;
1351 
1352  // Debug location must be unknown since the first debug location is used
1353  // to determine the end of the prologue.
1354  DebugLoc DL;
1355 
1356  // Space reserved for stack-based arguments when making a (ABI-guaranteed)
1357  // tail call.
1358  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
1359  if (TailCallArgReserveSize && IsWin64Prologue)
1360  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1361 
1362  const bool EmitStackProbeCall =
1364  unsigned StackProbeSize = STI.getTargetLowering()->getStackProbeSize(MF);
1365 
1366  if (HasFP && X86FI->hasSwiftAsyncContext()) {
1367  switch (MF.getTarget().Options.SwiftAsyncFramePointer) {
1370  // The special symbol below is absolute and has a *value* suitable to be
1371  // combined with the frame pointer directly.
1372  BuildMI(MBB, MBBI, DL, TII.get(X86::OR64rm), MachineFramePtr)
1373  .addUse(MachineFramePtr)
1374  .addUse(X86::RIP)
1375  .addImm(1)
1376  .addUse(X86::NoRegister)
1377  .addExternalSymbol("swift_async_extendedFramePointerFlags",
1379  .addUse(X86::NoRegister);
1380  break;
1381  }
1383 
1385  BuildMI(MBB, MBBI, DL, TII.get(X86::BTS64ri8), MachineFramePtr)
1386  .addUse(MachineFramePtr)
1387  .addImm(60)
1389  break;
1390 
1392  break;
1393  }
1394  }
1395 
1396  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1397  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1398  // stack alignment.
1399  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1400  Fn.arg_size() == 2) {
1401  StackSize += 8;
1402  MFI.setStackSize(StackSize);
1403  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1404  }
1405 
1406  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1407  // function, and use up to 128 bytes of stack space, don't have a frame
1408  // pointer, calls, or dynamic alloca then we do not need to adjust the
1409  // stack pointer (we fit in the Red Zone). We also check that we don't
1410  // push and pop from the stack.
1411  if (has128ByteRedZone(MF) && !TRI->hasStackRealignment(MF) &&
1412  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1413  !MFI.adjustsStack() && // No calls.
1414  !EmitStackProbeCall && // No stack probes.
1415  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1416  !MF.shouldSplitStack()) { // Regular stack
1417  uint64_t MinSize =
1418  X86FI->getCalleeSavedFrameSize() - X86FI->getTCReturnAddrDelta();
1419  if (HasFP) MinSize += SlotSize;
1420  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1421  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1422  MFI.setStackSize(StackSize);
1423  }
1424 
1425  // Insert stack pointer adjustment for later moving of return addr. Only
1426  // applies to tail call optimized functions where the callee argument stack
1427  // size is bigger than the callers.
1428  if (TailCallArgReserveSize != 0) {
1429  BuildStackAdjustment(MBB, MBBI, DL, -(int)TailCallArgReserveSize,
1430  /*InEpilogue=*/false)
1432  }
1433 
1434  // Mapping for machine moves:
1435  //
1436  // DST: VirtualFP AND
1437  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1438  // ELSE => DW_CFA_def_cfa
1439  //
1440  // SRC: VirtualFP AND
1441  // DST: Register => DW_CFA_def_cfa_register
1442  //
1443  // ELSE
1444  // OFFSET < 0 => DW_CFA_offset_extended_sf
1445  // REG < 64 => DW_CFA_offset + Reg
1446  // ELSE => DW_CFA_offset_extended
1447 
1448  uint64_t NumBytes = 0;
1449  int stackGrowth = -SlotSize;
1450 
1451  // Find the funclet establisher parameter
1452  Register Establisher = X86::NoRegister;
1453  if (IsClrFunclet)
1454  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1455  else if (IsFunclet)
1456  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1457 
1458  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1459  // Immediately spill establisher into the home slot.
1460  // The runtime cares about this.
1461  // MOV64mr %rdx, 16(%rsp)
1462  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1463  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1464  .addReg(Establisher)
1466  MBB.addLiveIn(Establisher);
1467  }
1468 
1469  if (HasFP) {
1470  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1471 
1472  // Calculate required stack adjustment.
1473  uint64_t FrameSize = StackSize - SlotSize;
1474  // If required, include space for extra hidden slot for stashing base pointer.
1475  if (X86FI->getRestoreBasePointer())
1476  FrameSize += SlotSize;
1477 
1478  NumBytes = FrameSize -
1479  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1480 
1481  // Callee-saved registers are pushed on stack before the stack is realigned.
1482  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
1483  NumBytes = alignTo(NumBytes, MaxAlign);
1484 
1485  // Save EBP/RBP into the appropriate stack slot.
1486  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1487  .addReg(MachineFramePtr, RegState::Kill)
1489 
1490  if (NeedsDwarfCFI) {
1491  // Mark the place where EBP/RBP was saved.
1492  // Define the current CFA rule to use the provided offset.
1493  assert(StackSize);
1494  BuildCFI(MBB, MBBI, DL,
1495  MCCFIInstruction::cfiDefCfaOffset(nullptr, -2 * stackGrowth));
1496 
1497  // Change the rule for the FramePtr to be an "offset" rule.
1498  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1500  nullptr, DwarfFramePtr, 2 * stackGrowth));
1501  }
1502 
1503  if (NeedsWinCFI) {
1504  HasWinCFI = true;
1505  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1506  .addImm(FramePtr)
1508  }
1509 
1510  if (!IsFunclet) {
1511  if (X86FI->hasSwiftAsyncContext()) {
1512  const auto &Attrs = MF.getFunction().getAttributes();
1513 
1514  // Before we update the live frame pointer we have to ensure there's a
1515  // valid (or null) asynchronous context in its slot just before FP in
1516  // the frame record, so store it now.
1517  if (Attrs.hasAttrSomewhere(Attribute::SwiftAsync)) {
1518  // We have an initial context in r14, store it just before the frame
1519  // pointer.
1520  MBB.addLiveIn(X86::R14);
1521  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1522  .addReg(X86::R14)
1524  } else {
1525  // No initial context, store null so that there's no pointer that
1526  // could be misused.
1527  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64i8))
1528  .addImm(0)
1530  }
1531 
1532  if (NeedsWinCFI) {
1533  HasWinCFI = true;
1534  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1535  .addImm(X86::R14)
1537  }
1538 
1539  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr)
1540  .addUse(X86::RSP)
1541  .addImm(1)
1542  .addUse(X86::NoRegister)
1543  .addImm(8)
1544  .addUse(X86::NoRegister)
1546  BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri8), X86::RSP)
1547  .addUse(X86::RSP)
1548  .addImm(8)
1550  }
1551 
1552  if (!IsWin64Prologue && !IsFunclet) {
1553  // Update EBP with the new base value.
1554  if (!X86FI->hasSwiftAsyncContext())
1555  BuildMI(MBB, MBBI, DL,
1556  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1557  FramePtr)
1558  .addReg(StackPtr)
1560 
1561  if (NeedsDwarfCFI) {
1562  // Mark effective beginning of when frame pointer becomes valid.
1563  // Define the current CFA to use the EBP/RBP register.
1564  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1565  BuildCFI(
1566  MBB, MBBI, DL,
1567  MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
1568  }
1569 
1570  if (NeedsWinFPO) {
1571  // .cv_fpo_setframe $FramePtr
1572  HasWinCFI = true;
1573  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1574  .addImm(FramePtr)
1575  .addImm(0)
1577  }
1578  }
1579  }
1580  } else {
1581  assert(!IsFunclet && "funclets without FPs not yet implemented");
1582  NumBytes = StackSize -
1583  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1584  }
1585 
1586  // Update the offset adjustment, which is mainly used by codeview to translate
1587  // from ESP to VFRAME relative local variable offsets.
1588  if (!IsFunclet) {
1589  if (HasFP && TRI->hasStackRealignment(MF))
1590  MFI.setOffsetAdjustment(-NumBytes);
1591  else
1592  MFI.setOffsetAdjustment(-StackSize);
1593  }
1594 
1595  // For EH funclets, only allocate enough space for outgoing calls. Save the
1596  // NumBytes value that we would've used for the parent frame.
1597  unsigned ParentFrameNumBytes = NumBytes;
1598  if (IsFunclet)
1599  NumBytes = getWinEHFuncletFrameSize(MF);
1600 
1601  // Skip the callee-saved push instructions.
1602  bool PushedRegs = false;
1603  int StackOffset = 2 * stackGrowth;
1604 
1605  while (MBBI != MBB.end() &&
1606  MBBI->getFlag(MachineInstr::FrameSetup) &&
1607  (MBBI->getOpcode() == X86::PUSH32r ||
1608  MBBI->getOpcode() == X86::PUSH64r)) {
1609  PushedRegs = true;
1610  Register Reg = MBBI->getOperand(0).getReg();
1611  ++MBBI;
1612 
1613  if (!HasFP && NeedsDwarfCFI) {
1614  // Mark callee-saved push instruction.
1615  // Define the current CFA rule to use the provided offset.
1616  assert(StackSize);
1617  BuildCFI(MBB, MBBI, DL,
1619  StackOffset += stackGrowth;
1620  }
1621 
1622  if (NeedsWinCFI) {
1623  HasWinCFI = true;
1624  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1625  .addImm(Reg)
1627  }
1628  }
1629 
1630  // Realign stack after we pushed callee-saved registers (so that we'll be
1631  // able to calculate their offsets from the frame pointer).
1632  // Don't do this for Win64, it needs to realign the stack after the prologue.
1633  if (!IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF)) {
1634  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1635  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1636 
1637  if (NeedsWinCFI) {
1638  HasWinCFI = true;
1639  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1640  .addImm(MaxAlign)
1642  }
1643  }
1644 
1645  // If there is an SUB32ri of ESP immediately before this instruction, merge
1646  // the two. This can be the case when tail call elimination is enabled and
1647  // the callee has more arguments then the caller.
1648  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1649 
1650  // Adjust stack pointer: ESP -= numbytes.
1651 
1652  // Windows and cygwin/mingw require a prologue helper routine when allocating
1653  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1654  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1655  // stack and adjust the stack pointer in one go. The 64-bit version of
1656  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1657  // responsible for adjusting the stack pointer. Touching the stack at 4K
1658  // increments is necessary to ensure that the guard pages used by the OS
1659  // virtual memory manager are allocated in correct sequence.
1660  uint64_t AlignedNumBytes = NumBytes;
1661  if (IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF))
1662  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1663  if (AlignedNumBytes >= StackProbeSize && EmitStackProbeCall) {
1664  assert(!X86FI->getUsesRedZone() &&
1665  "The Red Zone is not accounted for in stack probes");
1666 
1667  // Check whether EAX is livein for this block.
1668  bool isEAXAlive = isEAXLiveIn(MBB);
1669 
1670  if (isEAXAlive) {
1671  if (Is64Bit) {
1672  // Save RAX
1673  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1674  .addReg(X86::RAX, RegState::Kill)
1676  } else {
1677  // Save EAX
1678  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1681  }
1682  }
1683 
1684  if (Is64Bit) {
1685  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1686  // Function prologue is responsible for adjusting the stack pointer.
1687  int64_t Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1688  if (isUInt<32>(Alloc)) {
1689  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1690  .addImm(Alloc)
1692  } else if (isInt<32>(Alloc)) {
1693  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1694  .addImm(Alloc)
1696  } else {
1697  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1698  .addImm(Alloc)
1700  }
1701  } else {
1702  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1703  // We'll also use 4 already allocated bytes for EAX.
1704  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1705  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1707  }
1708 
1709  // Call __chkstk, __chkstk_ms, or __alloca.
1710  emitStackProbe(MF, MBB, MBBI, DL, true);
1711 
1712  if (isEAXAlive) {
1713  // Restore RAX/EAX
1714  MachineInstr *MI;
1715  if (Is64Bit)
1716  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1717  StackPtr, false, NumBytes - 8);
1718  else
1719  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1720  StackPtr, false, NumBytes - 4);
1721  MI->setFlag(MachineInstr::FrameSetup);
1722  MBB.insert(MBBI, MI);
1723  }
1724  } else if (NumBytes) {
1725  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1726  }
1727 
1728  if (NeedsWinCFI && NumBytes) {
1729  HasWinCFI = true;
1730  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1731  .addImm(NumBytes)
1733  }
1734 
1735  int SEHFrameOffset = 0;
1736  unsigned SPOrEstablisher;
1737  if (IsFunclet) {
1738  if (IsClrFunclet) {
1739  // The establisher parameter passed to a CLR funclet is actually a pointer
1740  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1741  // to find the root function establisher frame by loading the PSPSym from
1742  // the intermediate frame.
1743  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1744  MachinePointerInfo NoInfo;
1745  MBB.addLiveIn(Establisher);
1746  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1747  Establisher, false, PSPSlotOffset)
1750  ;
1751  // Save the root establisher back into the current funclet's (mostly
1752  // empty) frame, in case a sub-funclet or the GC needs it.
1753  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1754  false, PSPSlotOffset)
1755  .addReg(Establisher)
1757  NoInfo,
1759  SlotSize, Align(SlotSize)));
1760  }
1761  SPOrEstablisher = Establisher;
1762  } else {
1763  SPOrEstablisher = StackPtr;
1764  }
1765 
1766  if (IsWin64Prologue && HasFP) {
1767  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1768  // this calculation on the incoming establisher, which holds the value of
1769  // RSP from the parent frame at the end of the prologue.
1770  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1771  if (SEHFrameOffset)
1772  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1773  SPOrEstablisher, false, SEHFrameOffset);
1774  else
1775  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1776  .addReg(SPOrEstablisher);
1777 
1778  // If this is not a funclet, emit the CFI describing our frame pointer.
1779  if (NeedsWinCFI && !IsFunclet) {
1780  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1781  HasWinCFI = true;
1782  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1783  .addImm(FramePtr)
1784  .addImm(SEHFrameOffset)
1786  if (isAsynchronousEHPersonality(Personality))
1787  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1788  }
1789  } else if (IsFunclet && STI.is32Bit()) {
1790  // Reset EBP / ESI to something good for funclets.
1792  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1793  // into the registration node so that the runtime will restore it for us.
1794  if (!MBB.isCleanupFuncletEntry()) {
1795  assert(Personality == EHPersonality::MSVC_CXX);
1796  Register FrameReg;
1797  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1798  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg).getFixed();
1799  // ESP is the first field, so no extra displacement is needed.
1800  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1801  false, EHRegOffset)
1802  .addReg(X86::ESP);
1803  }
1804  }
1805 
1806  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1807  const MachineInstr &FrameInstr = *MBBI;
1808  ++MBBI;
1809 
1810  if (NeedsWinCFI) {
1811  int FI;
1812  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1813  if (X86::FR64RegClass.contains(Reg)) {
1814  int Offset;
1815  Register IgnoredFrameReg;
1816  if (IsWin64Prologue && IsFunclet)
1817  Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg);
1818  else
1819  Offset =
1820  getFrameIndexReference(MF, FI, IgnoredFrameReg).getFixed() +
1821  SEHFrameOffset;
1822 
1823  HasWinCFI = true;
1824  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1825  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1826  .addImm(Reg)
1827  .addImm(Offset)
1829  }
1830  }
1831  }
1832  }
1833 
1834  if (NeedsWinCFI && HasWinCFI)
1835  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1837 
1838  if (FnHasClrFunclet && !IsFunclet) {
1839  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1840  // immediately after the prolog) into the PSPSlot so that funclets
1841  // and the GC can recover it.
1842  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1843  auto PSPInfo = MachinePointerInfo::getFixedStack(
1844  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1845  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1846  PSPSlotOffset)
1847  .addReg(StackPtr)
1850  SlotSize, Align(SlotSize)));
1851  }
1852 
1853  // Realign stack after we spilled callee-saved registers (so that we'll be
1854  // able to calculate their offsets from the frame pointer).
1855  // Win64 requires aligning the stack after the prologue.
1856  if (IsWin64Prologue && TRI->hasStackRealignment(MF)) {
1857  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1858  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1859  }
1860 
1861  // We already dealt with stack realignment and funclets above.
1862  if (IsFunclet && STI.is32Bit())
1863  return;
1864 
1865  // If we need a base pointer, set it up here. It's whatever the value
1866  // of the stack pointer is at this point. Any variable size objects
1867  // will be allocated after this, so we can still use the base pointer
1868  // to reference locals.
1869  if (TRI->hasBasePointer(MF)) {
1870  // Update the base pointer with the current stack pointer.
1871  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1872  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1873  .addReg(SPOrEstablisher)
1875  if (X86FI->getRestoreBasePointer()) {
1876  // Stash value of base pointer. Saving RSP instead of EBP shortens
1877  // dependence chain. Used by SjLj EH.
1878  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1879  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1880  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1881  .addReg(SPOrEstablisher)
1883  }
1884 
1885  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1886  // Stash the value of the frame pointer relative to the base pointer for
1887  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1888  // it recovers the frame pointer from the base pointer rather than the
1889  // other way around.
1890  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1891  Register UsedReg;
1892  int Offset =
1893  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
1894  .getFixed();
1895  assert(UsedReg == BasePtr);
1896  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1897  .addReg(FramePtr)
1899  }
1900  }
1901 
1902  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1903  // Mark end of stack pointer adjustment.
1904  if (!HasFP && NumBytes) {
1905  // Define the current CFA rule to use the provided offset.
1906  assert(StackSize);
1907  BuildCFI(
1908  MBB, MBBI, DL,
1909  MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize - stackGrowth));
1910  }
1911 
1912  // Emit DWARF info specifying the offsets of the callee-saved registers.
1914  }
1915 
1916  // X86 Interrupt handling function cannot assume anything about the direction
1917  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1918  // in each prologue of interrupt handler function.
1919  //
1920  // FIXME: Create "cld" instruction only in these cases:
1921  // 1. The interrupt handling function uses any of the "rep" instructions.
1922  // 2. Interrupt handling function calls another function.
1923  //
1925  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1927 
1928  // At this point we know if the function has WinCFI or not.
1929  MF.setHasWinCFI(HasWinCFI);
1930 }
1931 
1933  const MachineFunction &MF) const {
1934  // We can't use LEA instructions for adjusting the stack pointer if we don't
1935  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1936  // to deallocate the stack.
1937  // This means that we can use LEA for SP in two situations:
1938  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1939  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1940  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1941 }
1942 
1944  switch (MI.getOpcode()) {
1945  case X86::CATCHRET:
1946  case X86::CLEANUPRET:
1947  return true;
1948  default:
1949  return false;
1950  }
1951  llvm_unreachable("impossible");
1952 }
1953 
1954 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
1955 // stack. It holds a pointer to the bottom of the root function frame. The
1956 // establisher frame pointer passed to a nested funclet may point to the
1957 // (mostly empty) frame of its parent funclet, but it will need to find
1958 // the frame of the root function to access locals. To facilitate this,
1959 // every funclet copies the pointer to the bottom of the root function
1960 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
1961 // same offset for the PSPSym in the root function frame that's used in the
1962 // funclets' frames allows each funclet to dynamically accept any ancestor
1963 // frame as its establisher argument (the runtime doesn't guarantee the
1964 // immediate parent for some reason lost to history), and also allows the GC,
1965 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
1966 // frame with only a single offset reported for the entire method.
1967 unsigned
1968 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
1969  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
1970  Register SPReg;
1971  int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg,
1972  /*IgnoreSPUpdates*/ true)
1973  .getFixed();
1974  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
1975  return static_cast<unsigned>(Offset);
1976 }
1977 
1978 unsigned
1979 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1981  // This is the size of the pushed CSRs.
1982  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1983  // This is the size of callee saved XMMs.
1984  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
1985  unsigned XMMSize = WinEHXMMSlotInfo.size() *
1986  TRI->getSpillSize(X86::VR128RegClass);
1987  // This is the amount of stack a funclet needs to allocate.
1988  unsigned UsedSize;
1989  EHPersonality Personality =
1991  if (Personality == EHPersonality::CoreCLR) {
1992  // CLR funclets need to hold enough space to include the PSPSym, at the
1993  // same offset from the stack pointer (immediately after the prolog) as it
1994  // resides at in the main function.
1995  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
1996  } else {
1997  // Other funclets just need enough stack for outgoing call arguments.
1998  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
1999  }
2000  // RBP is not included in the callee saved register block. After pushing RBP,
2001  // everything is 16 byte aligned. Everything we allocate before an outgoing
2002  // call must also be 16 byte aligned.
2003  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlign());
2004  // Subtract out the size of the callee saved registers. This is how much stack
2005  // each funclet will allocate.
2006  return FrameSizeMinusRBP + XMMSize - CSSize;
2007 }
2008 
2009 static bool isTailCallOpcode(unsigned Opc) {
2010  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
2011  Opc == X86::TCRETURNmi ||
2012  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
2013  Opc == X86::TCRETURNmi64;
2014 }
2015 
2017  MachineBasicBlock &MBB) const {
2018  const MachineFrameInfo &MFI = MF.getFrameInfo();
2022  DebugLoc DL;
2023  if (MBBI != MBB.end())
2024  DL = MBBI->getDebugLoc();
2025  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
2026  const bool Is64BitILP32 = STI.isTarget64BitILP32();
2027  Register FramePtr = TRI->getFrameRegister(MF);
2028  Register MachineFramePtr =
2029  Is64BitILP32 ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
2030 
2031  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2032  bool NeedsWin64CFI =
2033  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
2034  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
2035 
2036  // Get the number of bytes to allocate from the FrameInfo.
2037  uint64_t StackSize = MFI.getStackSize();
2038  uint64_t MaxAlign = calculateMaxStackAlign(MF);
2039  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2040  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
2041  bool HasFP = hasFP(MF);
2042  uint64_t NumBytes = 0;
2043 
2044  bool NeedsDwarfCFI = (!MF.getTarget().getTargetTriple().isOSDarwin() &&
2045  !MF.getTarget().getTargetTriple().isOSWindows()) &&
2046  MF.needsFrameMoves();
2047 
2048  if (IsFunclet) {
2049  assert(HasFP && "EH funclets without FP not yet implemented");
2050  NumBytes = getWinEHFuncletFrameSize(MF);
2051  } else if (HasFP) {
2052  // Calculate required stack adjustment.
2053  uint64_t FrameSize = StackSize - SlotSize;
2054  NumBytes = FrameSize - CSSize - TailCallArgReserveSize;
2055 
2056  // Callee-saved registers were pushed on stack before the stack was
2057  // realigned.
2058  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
2059  NumBytes = alignTo(FrameSize, MaxAlign);
2060  } else {
2061  NumBytes = StackSize - CSSize - TailCallArgReserveSize;
2062  }
2063  uint64_t SEHStackAllocAmt = NumBytes;
2064 
2065  // AfterPop is the position to insert .cfi_restore.
2066  MachineBasicBlock::iterator AfterPop = MBBI;
2067  if (HasFP) {
2068  if (X86FI->hasSwiftAsyncContext()) {
2069  // Discard the context.
2070  int Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
2071  emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/true);
2072  }
2073  // Pop EBP.
2074  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
2075  MachineFramePtr)
2077 
2078  // We need to reset FP to its untagged state on return. Bit 60 is currently
2079  // used to show the presence of an extended frame.
2080  if (X86FI->hasSwiftAsyncContext()) {
2081  BuildMI(MBB, MBBI, DL, TII.get(X86::BTR64ri8),
2082  MachineFramePtr)
2083  .addUse(MachineFramePtr)
2084  .addImm(60)
2086  }
2087 
2088  if (NeedsDwarfCFI) {
2089  unsigned DwarfStackPtr =
2090  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
2091  BuildCFI(MBB, MBBI, DL,
2092  MCCFIInstruction::cfiDefCfa(nullptr, DwarfStackPtr, SlotSize));
2093  if (!MBB.succ_empty() && !MBB.isReturnBlock()) {
2094  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
2095  BuildCFI(MBB, AfterPop, DL,
2096  MCCFIInstruction::createRestore(nullptr, DwarfFramePtr));
2097  --MBBI;
2098  --AfterPop;
2099  }
2100  --MBBI;
2101  }
2102  }
2103 
2104  MachineBasicBlock::iterator FirstCSPop = MBBI;
2105  // Skip the callee-saved pop instructions.
2106  while (MBBI != MBB.begin()) {
2107  MachineBasicBlock::iterator PI = std::prev(MBBI);
2108  unsigned Opc = PI->getOpcode();
2109 
2110  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
2111  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2112  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2113  (Opc != X86::BTR64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2114  (Opc != X86::ADD64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)))
2115  break;
2116  FirstCSPop = PI;
2117  }
2118 
2119  --MBBI;
2120  }
2121  MBBI = FirstCSPop;
2122 
2123  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
2124  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
2125 
2126  if (MBBI != MBB.end())
2127  DL = MBBI->getDebugLoc();
2128  // If there is an ADD32ri or SUB32ri of ESP immediately before this
2129  // instruction, merge the two instructions.
2130  if (NumBytes || MFI.hasVarSizedObjects())
2131  NumBytes += mergeSPUpdates(MBB, MBBI, true);
2132 
2133  // If dynamic alloca is used, then reset esp to point to the last callee-saved
2134  // slot before popping them off! Same applies for the case, when stack was
2135  // realigned. Don't do this if this was a funclet epilogue, since the funclets
2136  // will not do realignment or dynamic stack allocation.
2137  if (((TRI->hasStackRealignment(MF)) || MFI.hasVarSizedObjects()) &&
2138  !IsFunclet) {
2139  if (TRI->hasStackRealignment(MF))
2140  MBBI = FirstCSPop;
2141  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
2142  uint64_t LEAAmount =
2143  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
2144 
2145  if (X86FI->hasSwiftAsyncContext())
2146  LEAAmount -= 16;
2147 
2148  // There are only two legal forms of epilogue:
2149  // - add SEHAllocationSize, %rsp
2150  // - lea SEHAllocationSize(%FramePtr), %rsp
2151  //
2152  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
2153  // However, we may use this sequence if we have a frame pointer because the
2154  // effects of the prologue can safely be undone.
2155  if (LEAAmount != 0) {
2156  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
2157  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
2158  FramePtr, false, LEAAmount);
2159  --MBBI;
2160  } else {
2161  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
2162  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
2163  .addReg(FramePtr);
2164  --MBBI;
2165  }
2166  } else if (NumBytes) {
2167  // Adjust stack pointer back: ESP += numbytes.
2168  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
2169  if (!HasFP && NeedsDwarfCFI) {
2170  // Define the current CFA rule to use the provided offset.
2171  BuildCFI(MBB, MBBI, DL,
2173  nullptr, CSSize + TailCallArgReserveSize + SlotSize));
2174  }
2175  --MBBI;
2176  }
2177 
2178  // Windows unwinder will not invoke function's exception handler if IP is
2179  // either in prologue or in epilogue. This behavior causes a problem when a
2180  // call immediately precedes an epilogue, because the return address points
2181  // into the epilogue. To cope with that, we insert an epilogue marker here,
2182  // then replace it with a 'nop' if it ends up immediately after a CALL in the
2183  // final emitted code.
2184  if (NeedsWin64CFI && MF.hasWinCFI())
2185  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2186 
2187  if (!HasFP && NeedsDwarfCFI) {
2188  MBBI = FirstCSPop;
2189  int64_t Offset = -CSSize - SlotSize;
2190  // Mark callee-saved pop instruction.
2191  // Define the current CFA rule to use the provided offset.
2192  while (MBBI != MBB.end()) {
2194  unsigned Opc = PI->getOpcode();
2195  ++MBBI;
2196  if (Opc == X86::POP32r || Opc == X86::POP64r) {
2197  Offset += SlotSize;
2198  BuildCFI(MBB, MBBI, DL,
2200  }
2201  }
2202  }
2203 
2204  // Emit DWARF info specifying the restores of the callee-saved registers.
2205  // For epilogue with return inside or being other block without successor,
2206  // no need to generate .cfi_restore for callee-saved registers.
2207  if (NeedsDwarfCFI && !MBB.succ_empty())
2208  emitCalleeSavedFrameMoves(MBB, AfterPop, DL, false);
2209 
2210  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
2211  // Add the return addr area delta back since we are not tail calling.
2212  int Offset = -1 * X86FI->getTCReturnAddrDelta();
2213  assert(Offset >= 0 && "TCDelta should never be positive");
2214  if (Offset) {
2215  // Check for possible merge with preceding ADD instruction.
2216  Offset += mergeSPUpdates(MBB, Terminator, true);
2217  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
2218  }
2219  }
2220 
2221  // Emit tilerelease for AMX kernel.
2222  const MachineRegisterInfo &MRI = MF.getRegInfo();
2223  const TargetRegisterClass *RC = TRI->getRegClass(X86::TILERegClassID);
2224  for (unsigned I = 0; I < RC->getNumRegs(); I++)
2225  if (!MRI.reg_nodbg_empty(X86::TMM0 + I)) {
2226  BuildMI(MBB, Terminator, DL, TII.get(X86::TILERELEASE));
2227  break;
2228  }
2229 }
2230 
2232  int FI,
2233  Register &FrameReg) const {
2234  const MachineFrameInfo &MFI = MF.getFrameInfo();
2235 
2236  bool IsFixed = MFI.isFixedObjectIndex(FI);
2237  // We can't calculate offset from frame pointer if the stack is realigned,
2238  // so enforce usage of stack/base pointer. The base pointer is used when we
2239  // have dynamic allocas in addition to dynamic realignment.
2240  if (TRI->hasBasePointer(MF))
2241  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
2242  else if (TRI->hasStackRealignment(MF))
2243  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
2244  else
2245  FrameReg = TRI->getFrameRegister(MF);
2246 
2247  // Offset will hold the offset from the stack pointer at function entry to the
2248  // object.
2249  // We need to factor in additional offsets applied during the prologue to the
2250  // frame, base, and stack pointer depending on which is used.
2251  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
2253  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2254  uint64_t StackSize = MFI.getStackSize();
2255  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2256  int64_t FPDelta = 0;
2257 
2258  // In an x86 interrupt, remove the offset we added to account for the return
2259  // address from any stack object allocated in the caller's frame. Interrupts
2260  // do not have a standard return address. Fixed objects in the current frame,
2261  // such as SSE register spills, should not get this treatment.
2263  Offset >= 0) {
2265  }
2266 
2267  if (IsWin64Prologue) {
2268  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
2269 
2270  // Calculate required stack adjustment.
2271  uint64_t FrameSize = StackSize - SlotSize;
2272  // If required, include space for extra hidden slot for stashing base pointer.
2273  if (X86FI->getRestoreBasePointer())
2274  FrameSize += SlotSize;
2275  uint64_t NumBytes = FrameSize - CSSize;
2276 
2277  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
2278  if (FI && FI == X86FI->getFAIndex())
2279  return StackOffset::getFixed(-SEHFrameOffset);
2280 
2281  // FPDelta is the offset from the "traditional" FP location of the old base
2282  // pointer followed by return address and the location required by the
2283  // restricted Win64 prologue.
2284  // Add FPDelta to all offsets below that go through the frame pointer.
2285  FPDelta = FrameSize - SEHFrameOffset;
2286  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
2287  "FPDelta isn't aligned per the Win64 ABI!");
2288  }
2289 
2290  if (FrameReg == TRI->getFramePtr()) {
2291  // Skip saved EBP/RBP
2292  Offset += SlotSize;
2293 
2294  // Account for restricted Windows prologue.
2295  Offset += FPDelta;
2296 
2297  // Skip the RETADDR move area
2298  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2299  if (TailCallReturnAddrDelta < 0)
2300  Offset -= TailCallReturnAddrDelta;
2301 
2302  return StackOffset::getFixed(Offset);
2303  }
2304 
2305  // FrameReg is either the stack pointer or a base pointer. But the base is
2306  // located at the end of the statically known StackSize so the distinction
2307  // doesn't really matter.
2308  if (TRI->hasStackRealignment(MF) || TRI->hasBasePointer(MF))
2309  assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize)));
2310  return StackOffset::getFixed(Offset + StackSize);
2311 }
2312 
2314  Register &FrameReg) const {
2315  const MachineFrameInfo &MFI = MF.getFrameInfo();
2317  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2318  const auto it = WinEHXMMSlotInfo.find(FI);
2319 
2320  if (it == WinEHXMMSlotInfo.end())
2321  return getFrameIndexReference(MF, FI, FrameReg).getFixed();
2322 
2323  FrameReg = TRI->getStackRegister();
2324  return alignDown(MFI.getMaxCallFrameSize(), getStackAlign().value()) +
2325  it->second;
2326 }
2327 
2330  Register &FrameReg,
2331  int Adjustment) const {
2332  const MachineFrameInfo &MFI = MF.getFrameInfo();
2333  FrameReg = TRI->getStackRegister();
2334  return StackOffset::getFixed(MFI.getObjectOffset(FI) -
2335  getOffsetOfLocalArea() + Adjustment);
2336 }
2337 
2340  int FI, Register &FrameReg,
2341  bool IgnoreSPUpdates) const {
2342 
2343  const MachineFrameInfo &MFI = MF.getFrameInfo();
2344  // Does not include any dynamic realign.
2345  const uint64_t StackSize = MFI.getStackSize();
2346  // LLVM arranges the stack as follows:
2347  // ...
2348  // ARG2
2349  // ARG1
2350  // RETADDR
2351  // PUSH RBP <-- RBP points here
2352  // PUSH CSRs
2353  // ~~~~~~~ <-- possible stack realignment (non-win64)
2354  // ...
2355  // STACK OBJECTS
2356  // ... <-- RSP after prologue points here
2357  // ~~~~~~~ <-- possible stack realignment (win64)
2358  //
2359  // if (hasVarSizedObjects()):
2360  // ... <-- "base pointer" (ESI/RBX) points here
2361  // DYNAMIC ALLOCAS
2362  // ... <-- RSP points here
2363  //
2364  // Case 1: In the simple case of no stack realignment and no dynamic
2365  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
2366  // with fixed offsets from RSP.
2367  //
2368  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
2369  // stack objects are addressed with RBP and regular stack objects with RSP.
2370  //
2371  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
2372  // to address stack arguments for outgoing calls and nothing else. The "base
2373  // pointer" points to local variables, and RBP points to fixed objects.
2374  //
2375  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
2376  // answer we give is relative to the SP after the prologue, and not the
2377  // SP in the middle of the function.
2378 
2379  if (MFI.isFixedObjectIndex(FI) && TRI->hasStackRealignment(MF) &&
2380  !STI.isTargetWin64())
2381  return getFrameIndexReference(MF, FI, FrameReg);
2382 
2383  // If !hasReservedCallFrame the function might have SP adjustement in the
2384  // body. So, even though the offset is statically known, it depends on where
2385  // we are in the function.
2386  if (!IgnoreSPUpdates && !hasReservedCallFrame(MF))
2387  return getFrameIndexReference(MF, FI, FrameReg);
2388 
2389  // We don't handle tail calls, and shouldn't be seeing them either.
2391  "we don't handle this case!");
2392 
2393  // This is how the math works out:
2394  //
2395  // %rsp grows (i.e. gets lower) left to right. Each box below is
2396  // one word (eight bytes). Obj0 is the stack slot we're trying to
2397  // get to.
2398  //
2399  // ----------------------------------
2400  // | BP | Obj0 | Obj1 | ... | ObjN |
2401  // ----------------------------------
2402  // ^ ^ ^ ^
2403  // A B C E
2404  //
2405  // A is the incoming stack pointer.
2406  // (B - A) is the local area offset (-8 for x86-64) [1]
2407  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
2408  //
2409  // |(E - B)| is the StackSize (absolute value, positive). For a
2410  // stack that grown down, this works out to be (B - E). [3]
2411  //
2412  // E is also the value of %rsp after stack has been set up, and we
2413  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
2414  // (C - E) == (C - A) - (B - A) + (B - E)
2415  // { Using [1], [2] and [3] above }
2416  // == getObjectOffset - LocalAreaOffset + StackSize
2417 
2418  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
2419 }
2420 
2423  std::vector<CalleeSavedInfo> &CSI) const {
2424  MachineFrameInfo &MFI = MF.getFrameInfo();
2426 
2427  unsigned CalleeSavedFrameSize = 0;
2428  unsigned XMMCalleeSavedFrameSize = 0;
2429  auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2430  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
2431 
2432  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2433 
2434  if (TailCallReturnAddrDelta < 0) {
2435  // create RETURNADDR area
2436  // arg
2437  // arg
2438  // RETADDR
2439  // { ...
2440  // RETADDR area
2441  // ...
2442  // }
2443  // [EBP]
2444  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
2445  TailCallReturnAddrDelta - SlotSize, true);
2446  }
2447 
2448  // Spill the BasePtr if it's used.
2449  if (this->TRI->hasBasePointer(MF)) {
2450  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
2451  if (MF.hasEHFunclets()) {
2453  X86FI->setHasSEHFramePtrSave(true);
2454  X86FI->setSEHFramePtrSaveIndex(FI);
2455  }
2456  }
2457 
2458  if (hasFP(MF)) {
2459  // emitPrologue always spills frame register the first thing.
2460  SpillSlotOffset -= SlotSize;
2461  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2462 
2463  // The async context lives directly before the frame pointer, and we
2464  // allocate a second slot to preserve stack alignment.
2465  if (X86FI->hasSwiftAsyncContext()) {
2466  SpillSlotOffset -= SlotSize;
2467  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2468  SpillSlotOffset -= SlotSize;
2469  }
2470 
2471  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
2472  // the frame register, we can delete it from CSI list and not have to worry
2473  // about avoiding it later.
2474  Register FPReg = TRI->getFrameRegister(MF);
2475  for (unsigned i = 0; i < CSI.size(); ++i) {
2476  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
2477  CSI.erase(CSI.begin() + i);
2478  break;
2479  }
2480  }
2481  }
2482 
2483  // Assign slots for GPRs. It increases frame size.
2484  for (unsigned i = CSI.size(); i != 0; --i) {
2485  unsigned Reg = CSI[i - 1].getReg();
2486 
2487  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2488  continue;
2489 
2490  SpillSlotOffset -= SlotSize;
2491  CalleeSavedFrameSize += SlotSize;
2492 
2493  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2494  CSI[i - 1].setFrameIdx(SlotIndex);
2495  }
2496 
2497  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2498  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2499 
2500  // Assign slots for XMMs.
2501  for (unsigned i = CSI.size(); i != 0; --i) {
2502  unsigned Reg = CSI[i - 1].getReg();
2503  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2504  continue;
2505 
2506  // If this is k-register make sure we lookup via the largest legal type.
2507  MVT VT = MVT::Other;
2508  if (X86::VK16RegClass.contains(Reg))
2509  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2510 
2511  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2512  unsigned Size = TRI->getSpillSize(*RC);
2513  Align Alignment = TRI->getSpillAlign(*RC);
2514  // ensure alignment
2515  assert(SpillSlotOffset < 0 && "SpillSlotOffset should always < 0 on X86");
2516  SpillSlotOffset = -alignTo(-SpillSlotOffset, Alignment);
2517 
2518  // spill into slot
2519  SpillSlotOffset -= Size;
2520  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2521  CSI[i - 1].setFrameIdx(SlotIndex);
2522  MFI.ensureMaxAlignment(Alignment);
2523 
2524  // Save the start offset and size of XMM in stack frame for funclets.
2525  if (X86::VR128RegClass.contains(Reg)) {
2526  WinEHXMMSlotInfo[SlotIndex] = XMMCalleeSavedFrameSize;
2527  XMMCalleeSavedFrameSize += Size;
2528  }
2529  }
2530 
2531  return true;
2532 }
2533 
2536  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
2538 
2539  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2540  // for us, and there are no XMM CSRs on Win32.
2541  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2542  return true;
2543 
2544  // Push GPRs. It increases frame size.
2545  const MachineFunction &MF = *MBB.getParent();
2546  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2547  for (unsigned i = CSI.size(); i != 0; --i) {
2548  unsigned Reg = CSI[i - 1].getReg();
2549 
2550  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2551  continue;
2552 
2553  const MachineRegisterInfo &MRI = MF.getRegInfo();
2554  bool isLiveIn = MRI.isLiveIn(Reg);
2555  if (!isLiveIn)
2556  MBB.addLiveIn(Reg);
2557 
2558  // Decide whether we can add a kill flag to the use.
2559  bool CanKill = !isLiveIn;
2560  // Check if any subregister is live-in
2561  if (CanKill) {
2562  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2563  if (MRI.isLiveIn(*AReg)) {
2564  CanKill = false;
2565  break;
2566  }
2567  }
2568  }
2569 
2570  // Do not set a kill flag on values that are also marked as live-in. This
2571  // happens with the @llvm-returnaddress intrinsic and with arguments
2572  // passed in callee saved registers.
2573  // Omitting the kill flags is conservatively correct even if the live-in
2574  // is not used after all.
2575  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2577  }
2578 
2579  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2580  // It can be done by spilling XMMs to stack frame.
2581  for (unsigned i = CSI.size(); i != 0; --i) {
2582  unsigned Reg = CSI[i-1].getReg();
2583  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2584  continue;
2585 
2586  // If this is k-register make sure we lookup via the largest legal type.
2587  MVT VT = MVT::Other;
2588  if (X86::VK16RegClass.contains(Reg))
2589  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2590 
2591  // Add the callee-saved register as live-in. It's killed at the spill.
2592  MBB.addLiveIn(Reg);
2593  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2594 
2595  TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
2596  TRI);
2597  --MI;
2598  MI->setFlag(MachineInstr::FrameSetup);
2599  ++MI;
2600  }
2601 
2602  return true;
2603 }
2604 
2605 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2607  MachineInstr *CatchRet) const {
2608  // SEH shouldn't use catchret.
2611  "SEH should not use CATCHRET");
2612  const DebugLoc &DL = CatchRet->getDebugLoc();
2613  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2614 
2615  // Fill EAX/RAX with the address of the target block.
2616  if (STI.is64Bit()) {
2617  // LEA64r CatchRetTarget(%rip), %rax
2618  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2619  .addReg(X86::RIP)
2620  .addImm(0)
2621  .addReg(0)
2622  .addMBB(CatchRetTarget)
2623  .addReg(0);
2624  } else {
2625  // MOV32ri $CatchRetTarget, %eax
2626  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2627  .addMBB(CatchRetTarget);
2628  }
2629 
2630  // Record that we've taken the address of CatchRetTarget and no longer just
2631  // reference it in a terminator.
2632  CatchRetTarget->setHasAddressTaken();
2633 }
2634 
2638  if (CSI.empty())
2639  return false;
2640 
2641  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2642  // Don't restore CSRs in 32-bit EH funclets. Matches
2643  // spillCalleeSavedRegisters.
2644  if (STI.is32Bit())
2645  return true;
2646  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2647  // funclets. emitEpilogue transforms these to normal jumps.
2648  if (MI->getOpcode() == X86::CATCHRET) {
2649  const Function &F = MBB.getParent()->getFunction();
2650  bool IsSEH = isAsynchronousEHPersonality(
2651  classifyEHPersonality(F.getPersonalityFn()));
2652  if (IsSEH)
2653  return true;
2654  }
2655  }
2656 
2658 
2659  // Reload XMMs from stack frame.
2660  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2661  unsigned Reg = CSI[i].getReg();
2662  if (X86::GR64RegClass.contains(Reg) ||
2663  X86::GR32RegClass.contains(Reg))
2664  continue;
2665 
2666  // If this is k-register make sure we lookup via the largest legal type.
2667  MVT VT = MVT::Other;
2668  if (X86::VK16RegClass.contains(Reg))
2669  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2670 
2671  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2672  TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
2673  }
2674 
2675  // POP GPRs.
2676  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2677  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2678  unsigned Reg = CSI[i].getReg();
2679  if (!X86::GR64RegClass.contains(Reg) &&
2680  !X86::GR32RegClass.contains(Reg))
2681  continue;
2682 
2683  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2685  }
2686  return true;
2687 }
2688 
2690  BitVector &SavedRegs,
2691  RegScavenger *RS) const {
2692  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2693 
2694  // Spill the BasePtr if it's used.
2695  if (TRI->hasBasePointer(MF)){
2696  Register BasePtr = TRI->getBaseRegister();
2697  if (STI.isTarget64BitILP32())
2698  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2699  SavedRegs.set(BasePtr);
2700  }
2701 }
2702 
2703 static bool
2705  const Function &F = MF->getFunction();
2706  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2707  I != E; I++) {
2708  if (I->hasNestAttr() && !I->use_empty())
2709  return true;
2710  }
2711  return false;
2712 }
2713 
2714 /// GetScratchRegister - Get a temp register for performing work in the
2715 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2716 /// and the properties of the function either one or two registers will be
2717 /// needed. Set primary to true for the first register, false for the second.
2718 static unsigned
2719 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2721 
2722  // Erlang stuff.
2724  if (Is64Bit)
2725  return Primary ? X86::R14 : X86::R13;
2726  else
2727  return Primary ? X86::EBX : X86::EDI;
2728  }
2729 
2730  if (Is64Bit) {
2731  if (IsLP64)
2732  return Primary ? X86::R11 : X86::R12;
2733  else
2734  return Primary ? X86::R11D : X86::R12D;
2735  }
2736 
2737  bool IsNested = HasNestArgument(&MF);
2738 
2742  if (IsNested)
2743  report_fatal_error("Segmented stacks does not support fastcall with "
2744  "nested function.");
2745  return Primary ? X86::EAX : X86::ECX;
2746  }
2747  if (IsNested)
2748  return Primary ? X86::EDX : X86::EAX;
2749  return Primary ? X86::ECX : X86::EAX;
2750 }
2751 
2752 // The stack limit in the TCB is set to this many bytes above the actual stack
2753 // limit.
2754 static const uint64_t kSplitStackAvailable = 256;
2755 
2757  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2758  MachineFrameInfo &MFI = MF.getFrameInfo();
2759  uint64_t StackSize;
2760  unsigned TlsReg, TlsOffset;
2761  DebugLoc DL;
2762 
2763  // To support shrink-wrapping we would need to insert the new blocks
2764  // at the right place and update the branches to PrologueMBB.
2765  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2766 
2767  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2768  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2769  "Scratch register is live-in");
2770 
2771  if (MF.getFunction().isVarArg())
2772  report_fatal_error("Segmented stacks do not support vararg functions.");
2773  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2774  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2776  report_fatal_error("Segmented stacks not supported on this platform.");
2777 
2778  // Eventually StackSize will be calculated by a link-time pass; which will
2779  // also decide whether checking code needs to be injected into this particular
2780  // prologue.
2781  StackSize = MFI.getStackSize();
2782 
2783  // Do not generate a prologue for leaf functions with a stack of size zero.
2784  // For non-leaf functions we have to allow for the possibility that the
2785  // callis to a non-split function, as in PR37807. This function could also
2786  // take the address of a non-split function. When the linker tries to adjust
2787  // its non-existent prologue, it would fail with an error. Mark the object
2788  // file so that such failures are not errors. See this Go language bug-report
2789  // https://go-review.googlesource.com/c/go/+/148819/
2790  if (StackSize == 0 && !MFI.hasTailCall()) {
2791  MF.getMMI().setHasNosplitStack(true);
2792  return;
2793  }
2794 
2795  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2796  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2798  bool IsNested = false;
2799 
2800  // We need to know if the function has a nest argument only in 64 bit mode.
2801  if (Is64Bit)
2802  IsNested = HasNestArgument(&MF);
2803 
2804  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2805  // allocMBB needs to be last (terminating) instruction.
2806 
2807  for (const auto &LI : PrologueMBB.liveins()) {
2808  allocMBB->addLiveIn(LI);
2809  checkMBB->addLiveIn(LI);
2810  }
2811 
2812  if (IsNested)
2813  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2814 
2815  MF.push_front(allocMBB);
2816  MF.push_front(checkMBB);
2817 
2818  // When the frame size is less than 256 we just compare the stack
2819  // boundary directly to the value of the stack pointer, per gcc.
2820  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2821 
2822  // Read the limit off the current stacklet off the stack_guard location.
2823  if (Is64Bit) {
2824  if (STI.isTargetLinux()) {
2825  TlsReg = X86::FS;
2826  TlsOffset = IsLP64 ? 0x70 : 0x40;
2827  } else if (STI.isTargetDarwin()) {
2828  TlsReg = X86::GS;
2829  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2830  } else if (STI.isTargetWin64()) {
2831  TlsReg = X86::GS;
2832  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2833  } else if (STI.isTargetFreeBSD()) {
2834  TlsReg = X86::FS;
2835  TlsOffset = 0x18;
2836  } else if (STI.isTargetDragonFly()) {
2837  TlsReg = X86::FS;
2838  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2839  } else {
2840  report_fatal_error("Segmented stacks not supported on this platform.");
2841  }
2842 
2843  if (CompareStackPointer)
2844  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2845  else
2846  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2847  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2848 
2849  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2850  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2851  } else {
2852  if (STI.isTargetLinux()) {
2853  TlsReg = X86::GS;
2854  TlsOffset = 0x30;
2855  } else if (STI.isTargetDarwin()) {
2856  TlsReg = X86::GS;
2857  TlsOffset = 0x48 + 90*4;
2858  } else if (STI.isTargetWin32()) {
2859  TlsReg = X86::FS;
2860  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2861  } else if (STI.isTargetDragonFly()) {
2862  TlsReg = X86::FS;
2863  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2864  } else if (STI.isTargetFreeBSD()) {
2865  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2866  } else {
2867  report_fatal_error("Segmented stacks not supported on this platform.");
2868  }
2869 
2870  if (CompareStackPointer)
2871  ScratchReg = X86::ESP;
2872  else
2873  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2874  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2875 
2876  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2877  STI.isTargetDragonFly()) {
2878  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2879  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2880  } else if (STI.isTargetDarwin()) {
2881 
2882  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2883  unsigned ScratchReg2;
2884  bool SaveScratch2;
2885  if (CompareStackPointer) {
2886  // The primary scratch register is available for holding the TLS offset.
2887  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2888  SaveScratch2 = false;
2889  } else {
2890  // Need to use a second register to hold the TLS offset
2891  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2892 
2893  // Unfortunately, with fastcc the second scratch register may hold an
2894  // argument.
2895  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2896  }
2897 
2898  // If Scratch2 is live-in then it needs to be saved.
2899  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2900  "Scratch register is live-in and not saved");
2901 
2902  if (SaveScratch2)
2903  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2904  .addReg(ScratchReg2, RegState::Kill);
2905 
2906  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2907  .addImm(TlsOffset);
2908  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2909  .addReg(ScratchReg)
2910  .addReg(ScratchReg2).addImm(1).addReg(0)
2911  .addImm(0)
2912  .addReg(TlsReg);
2913 
2914  if (SaveScratch2)
2915  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2916  }
2917  }
2918 
2919  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2920  // It jumps to normal execution of the function body.
2921  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2922 
2923  // On 32 bit we first push the arguments size and then the frame size. On 64
2924  // bit, we pass the stack frame size in r10 and the argument size in r11.
2925  if (Is64Bit) {
2926  // Functions with nested arguments use R10, so it needs to be saved across
2927  // the call to _morestack
2928 
2929  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2930  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2931  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2932  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2933  const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2934 
2935  if (IsNested)
2936  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2937 
2938  BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2939  .addImm(StackSize);
2940  BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2941  .addImm(X86FI->getArgumentStackSize());
2942  } else {
2943  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2944  .addImm(X86FI->getArgumentStackSize());
2945  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2946  .addImm(StackSize);
2947  }
2948 
2949  // __morestack is in libgcc
2950  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2951  // Under the large code model, we cannot assume that __morestack lives
2952  // within 2^31 bytes of the call site, so we cannot use pc-relative
2953  // addressing. We cannot perform the call via a temporary register,
2954  // as the rax register may be used to store the static chain, and all
2955  // other suitable registers may be either callee-save or used for
2956  // parameter passing. We cannot use the stack at this point either
2957  // because __morestack manipulates the stack directly.
2958  //
2959  // To avoid these issues, perform an indirect call via a read-only memory
2960  // location containing the address.
2961  //
2962  // This solution is not perfect, as it assumes that the .rodata section
2963  // is laid out within 2^31 bytes of each function body, but this seems
2964  // to be sufficient for JIT.
2965  // FIXME: Add retpoline support and remove the error here..
2966  if (STI.useIndirectThunkCalls())
2967  report_fatal_error("Emitting morestack calls on 64-bit with the large "
2968  "code model and thunks not yet implemented.");
2969  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2970  .addReg(X86::RIP)
2971  .addImm(0)
2972  .addReg(0)
2973  .addExternalSymbol("__morestack_addr")
2974  .addReg(0);
2975  MF.getMMI().setUsesMorestackAddr(true);
2976  } else {
2977  if (Is64Bit)
2978  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2979  .addExternalSymbol("__morestack");
2980  else
2981  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2982  .addExternalSymbol("__morestack");
2983  }
2984 
2985  if (IsNested)
2986  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2987  else
2988  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2989 
2990  allocMBB->addSuccessor(&PrologueMBB);
2991 
2992  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
2993  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
2994 
2995 #ifdef EXPENSIVE_CHECKS
2996  MF.verify();
2997 #endif
2998 }
2999 
3000 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
3001 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
3002 /// to fields it needs, through a named metadata node "hipe.literals" containing
3003 /// name-value pairs.
3004 static unsigned getHiPELiteral(
3005  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
3006  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
3007  MDNode *Node = HiPELiteralsMD->getOperand(i);
3008  if (Node->getNumOperands() != 2) continue;
3009  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
3010  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
3011  if (!NodeName || !NodeVal) continue;
3012  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
3013  if (ValConst && NodeName->getString() == LiteralName) {
3014  return ValConst->getZExtValue();
3015  }
3016  }
3017 
3018  report_fatal_error("HiPE literal " + LiteralName
3019  + " required but not provided");
3020 }
3021 
3022 // Return true if there are no non-ehpad successors to MBB and there are no
3023 // non-meta instructions between MBBI and MBB.end().
3026  return llvm::all_of(
3027  MBB.successors(),
3028  [](const MachineBasicBlock *Succ) { return Succ->isEHPad(); }) &&
3029  std::all_of(MBBI, MBB.end(), [](const MachineInstr &MI) {
3030  return MI.isMetaInstruction();
3031  });
3032 }
3033 
3034 /// Erlang programs may need a special prologue to handle the stack size they
3035 /// might need at runtime. That is because Erlang/OTP does not implement a C
3036 /// stack but uses a custom implementation of hybrid stack/heap architecture.
3037 /// (for more information see Eric Stenman's Ph.D. thesis:
3038 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
3039 ///
3040 /// CheckStack:
3041 /// temp0 = sp - MaxStack
3042 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3043 /// OldStart:
3044 /// ...
3045 /// IncStack:
3046 /// call inc_stack # doubles the stack space
3047 /// temp0 = sp - MaxStack
3048 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3050  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
3051  MachineFrameInfo &MFI = MF.getFrameInfo();
3052  DebugLoc DL;
3053 
3054  // To support shrink-wrapping we would need to insert the new blocks
3055  // at the right place and update the branches to PrologueMBB.
3056  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
3057 
3058  // HiPE-specific values
3059  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
3060  ->getNamedMetadata("hipe.literals");
3061  if (!HiPELiteralsMD)
3063  "Can't generate HiPE prologue without runtime parameters");
3064  const unsigned HipeLeafWords
3065  = getHiPELiteral(HiPELiteralsMD,
3066  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
3067  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
3068  const unsigned Guaranteed = HipeLeafWords * SlotSize;
3069  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
3070  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
3071  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
3072 
3073  assert(STI.isTargetLinux() &&
3074  "HiPE prologue is only supported on Linux operating systems.");
3075 
3076  // Compute the largest caller's frame that is needed to fit the callees'
3077  // frames. This 'MaxStack' is computed from:
3078  //
3079  // a) the fixed frame size, which is the space needed for all spilled temps,
3080  // b) outgoing on-stack parameter areas, and
3081  // c) the minimum stack space this function needs to make available for the
3082  // functions it calls (a tunable ABI property).
3083  if (MFI.hasCalls()) {
3084  unsigned MoreStackForCalls = 0;
3085 
3086  for (auto &MBB : MF) {
3087  for (auto &MI : MBB) {
3088  if (!MI.isCall())
3089  continue;
3090 
3091  // Get callee operand.
3092  const MachineOperand &MO = MI.getOperand(0);
3093 
3094  // Only take account of global function calls (no closures etc.).
3095  if (!MO.isGlobal())
3096  continue;
3097 
3098  const Function *F = dyn_cast<Function>(MO.getGlobal());
3099  if (!F)
3100  continue;
3101 
3102  // Do not update 'MaxStack' for primitive and built-in functions
3103  // (encoded with names either starting with "erlang."/"bif_" or not
3104  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
3105  // "_", such as the BIF "suspend_0") as they are executed on another
3106  // stack.
3107  if (F->getName().find("erlang.") != StringRef::npos ||
3108  F->getName().find("bif_") != StringRef::npos ||
3109  F->getName().find_first_of("._") == StringRef::npos)
3110  continue;
3111 
3112  unsigned CalleeStkArity =
3113  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
3114  if (HipeLeafWords - 1 > CalleeStkArity)
3115  MoreStackForCalls = std::max(MoreStackForCalls,
3116  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
3117  }
3118  }
3119  MaxStack += MoreStackForCalls;
3120  }
3121 
3122  // If the stack frame needed is larger than the guaranteed then runtime checks
3123  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
3124  if (MaxStack > Guaranteed) {
3125  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
3126  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
3127 
3128  for (const auto &LI : PrologueMBB.liveins()) {
3129  stackCheckMBB->addLiveIn(LI);
3130  incStackMBB->addLiveIn(LI);
3131  }
3132 
3133  MF.push_front(incStackMBB);
3134  MF.push_front(stackCheckMBB);
3135 
3136  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
3137  unsigned LEAop, CMPop, CALLop;
3138  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
3139  if (Is64Bit) {
3140  SPReg = X86::RSP;
3141  PReg = X86::RBP;
3142  LEAop = X86::LEA64r;
3143  CMPop = X86::CMP64rm;
3144  CALLop = X86::CALL64pcrel32;
3145  } else {
3146  SPReg = X86::ESP;
3147  PReg = X86::EBP;
3148  LEAop = X86::LEA32r;
3149  CMPop = X86::CMP32rm;
3150  CALLop = X86::CALLpcrel32;
3151  }
3152 
3153  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
3154  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
3155  "HiPE prologue scratch register is live-in");
3156 
3157  // Create new MBB for StackCheck:
3158  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
3159  SPReg, false, -MaxStack);
3160  // SPLimitOffset is in a fixed heap location (pointed by BP).
3161  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
3162  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3163  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
3164 
3165  // Create new MBB for IncStack:
3166  BuildMI(incStackMBB, DL, TII.get(CALLop)).
3167  addExternalSymbol("inc_stack_0");
3168  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
3169  SPReg, false, -MaxStack);
3170  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
3171  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3172  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
3173 
3174  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
3175  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
3176  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
3177  incStackMBB->addSuccessor(incStackMBB, {1, 100});
3178  }
3179 #ifdef EXPENSIVE_CHECKS
3180  MF.verify();
3181 #endif
3182 }
3183 
3184 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
3186  const DebugLoc &DL,
3187  int Offset) const {
3188  if (Offset <= 0)
3189  return false;
3190 
3191  if (Offset % SlotSize)
3192  return false;
3193 
3194  int NumPops = Offset / SlotSize;
3195  // This is only worth it if we have at most 2 pops.
3196  if (NumPops != 1 && NumPops != 2)
3197  return false;
3198 
3199  // Handle only the trivial case where the adjustment directly follows
3200  // a call. This is the most common one, anyway.
3201  if (MBBI == MBB.begin())
3202  return false;
3203  MachineBasicBlock::iterator Prev = std::prev(MBBI);
3204  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
3205  return false;
3206 
3207  unsigned Regs[2];
3208  unsigned FoundRegs = 0;
3209 
3211  const MachineOperand &RegMask = Prev->getOperand(1);
3212 
3213  auto &RegClass =
3214  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
3215  // Try to find up to NumPops free registers.
3216  for (auto Candidate : RegClass) {
3217  // Poor man's liveness:
3218  // Since we're immediately after a call, any register that is clobbered
3219  // by the call and not defined by it can be considered dead.
3220  if (!RegMask.clobbersPhysReg(Candidate))
3221  continue;
3222 
3223  // Don't clobber reserved registers
3224  if (MRI.isReserved(Candidate))
3225  continue;
3226 
3227  bool IsDef = false;
3228  for (const MachineOperand &MO : Prev->implicit_operands()) {
3229  if (MO.isReg() && MO.isDef() &&
3230  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
3231  IsDef = true;
3232  break;
3233  }
3234  }
3235 
3236  if (IsDef)
3237  continue;
3238 
3239  Regs[FoundRegs++] = Candidate;
3240  if (FoundRegs == (unsigned)NumPops)
3241  break;
3242  }
3243 
3244  if (FoundRegs == 0)
3245  return false;
3246 
3247  // If we found only one free register, but need two, reuse the same one twice.
3248  while (FoundRegs < (unsigned)NumPops)
3249  Regs[FoundRegs++] = Regs[0];
3250 
3251  for (int i = 0; i < NumPops; ++i)
3252  BuildMI(MBB, MBBI, DL,
3253  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
3254 
3255  return true;
3256 }
3257 
3261  bool reserveCallFrame = hasReservedCallFrame(MF);
3262  unsigned Opcode = I->getOpcode();
3263  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
3264  DebugLoc DL = I->getDebugLoc(); // copy DebugLoc as I will be erased.
3265  uint64_t Amount = TII.getFrameSize(*I);
3266  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
3267  I = MBB.erase(I);
3268  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
3269 
3270  // Try to avoid emitting dead SP adjustments if the block end is unreachable,
3271  // typically because the function is marked noreturn (abort, throw,
3272  // assert_fail, etc).
3273  if (isDestroy && blockEndIsUnreachable(MBB, I))
3274  return I;
3275 
3276  if (!reserveCallFrame) {
3277  // If the stack pointer can be changed after prologue, turn the
3278  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
3279  // adjcallstackdown instruction into 'add ESP, <amt>'
3280 
3281  // We need to keep the stack aligned properly. To do this, we round the
3282  // amount of space needed for the outgoing arguments up to the next
3283  // alignment boundary.
3284  Amount = alignTo(Amount, getStackAlign());
3285 
3286  const Function &F = MF.getFunction();
3287  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3288  bool DwarfCFI = !WindowsCFI && MF.needsFrameMoves();
3289 
3290  // If we have any exception handlers in this function, and we adjust
3291  // the SP before calls, we may need to indicate this to the unwinder
3292  // using GNU_ARGS_SIZE. Note that this may be necessary even when
3293  // Amount == 0, because the preceding function may have set a non-0
3294  // GNU_ARGS_SIZE.
3295  // TODO: We don't need to reset this between subsequent functions,
3296  // if it didn't change.
3297  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
3298 
3299  if (HasDwarfEHHandlers && !isDestroy &&
3301  BuildCFI(MBB, InsertPos, DL,
3302  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
3303 
3304  if (Amount == 0)
3305  return I;
3306 
3307  // Factor out the amount that gets handled inside the sequence
3308  // (Pushes of argument for frame setup, callee pops for frame destroy)
3309  Amount -= InternalAmt;
3310 
3311  // TODO: This is needed only if we require precise CFA.
3312  // If this is a callee-pop calling convention, emit a CFA adjust for
3313  // the amount the callee popped.
3314  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
3315  BuildCFI(MBB, InsertPos, DL,
3316  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
3317 
3318  // Add Amount to SP to destroy a frame, or subtract to setup.
3319  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
3320 
3321  if (StackAdjustment) {
3322  // Merge with any previous or following adjustment instruction. Note: the
3323  // instructions merged with here do not have CFI, so their stack
3324  // adjustments do not feed into CfaAdjustment.
3325  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
3326  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
3327 
3328  if (StackAdjustment) {
3329  if (!(F.hasMinSize() &&
3330  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
3331  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
3332  /*InEpilogue=*/false);
3333  }
3334  }
3335 
3336  if (DwarfCFI && !hasFP(MF)) {
3337  // If we don't have FP, but need to generate unwind information,
3338  // we need to set the correct CFA offset after the stack adjustment.
3339  // How much we adjust the CFA offset depends on whether we're emitting
3340  // CFI only for EH purposes or for debugging. EH only requires the CFA
3341  // offset to be correct at each call site, while for debugging we want
3342  // it to be more precise.
3343 
3344  int64_t CfaAdjustment = -StackAdjustment;
3345  // TODO: When not using precise CFA, we also need to adjust for the
3346  // InternalAmt here.
3347  if (CfaAdjustment) {
3348  BuildCFI(MBB, InsertPos, DL,
3350  CfaAdjustment));
3351  }
3352  }
3353 
3354  return I;
3355  }
3356 
3357  if (InternalAmt) {
3360  while (CI != B && !std::prev(CI)->isCall())
3361  --CI;
3362  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
3363  }
3364 
3365  return I;
3366 }
3367 
3369  assert(MBB.getParent() && "Block is not attached to a function!");
3370  const MachineFunction &MF = *MBB.getParent();
3371  if (!MBB.isLiveIn(X86::EFLAGS))
3372  return true;
3373 
3375  return !TRI->hasStackRealignment(MF) && !X86FI->hasSwiftAsyncContext();
3376 }
3377 
3379  assert(MBB.getParent() && "Block is not attached to a function!");
3380 
3381  // Win64 has strict requirements in terms of epilogue and we are
3382  // not taking a chance at messing with them.
3383  // I.e., unless this block is already an exit block, we can't use
3384  // it as an epilogue.
3385  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
3386  return false;
3387 
3388  // Swift async context epilogue has a BTR instruction that clobbers parts of
3389  // EFLAGS.
3390  const MachineFunction &MF = *MBB.getParent();
3393 
3395  return true;
3396 
3397  // If we cannot use LEA to adjust SP, we may need to use ADD, which
3398  // clobbers the EFLAGS. Check that we do not need to preserve it,
3399  // otherwise, conservatively assume this is not
3400  // safe to insert the epilogue here.
3402 }
3403 
3405  // If we may need to emit frameless compact unwind information, give
3406  // up as this is currently broken: PR25614.
3407  bool CompactUnwind =
3409  nullptr;
3410  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF) ||
3411  !CompactUnwind) &&
3412  // The lowering of segmented stack and HiPE only support entry
3413  // blocks as prologue blocks: PR26107. This limitation may be
3414  // lifted if we fix:
3415  // - adjustForSegmentedStacks
3416  // - adjustForHiPEPrologue
3418  !MF.shouldSplitStack();
3419 }
3420 
3423  const DebugLoc &DL, bool RestoreSP) const {
3424  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
3425  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
3427  "restoring EBP/ESI on non-32-bit target");
3428 
3429  MachineFunction &MF = *MBB.getParent();
3430  Register FramePtr = TRI->getFrameRegister(MF);
3431  Register BasePtr = TRI->getBaseRegister();
3432  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
3434  MachineFrameInfo &MFI = MF.getFrameInfo();
3435 
3436  // FIXME: Don't set FrameSetup flag in catchret case.
3437 
3438  int FI = FuncInfo.EHRegNodeFrameIndex;
3439  int EHRegSize = MFI.getObjectSize(FI);
3440 
3441  if (RestoreSP) {
3442  // MOV32rm -EHRegSize(%ebp), %esp
3443  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
3444  X86::EBP, true, -EHRegSize)
3446  }
3447 
3448  Register UsedReg;
3449  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed();
3450  int EndOffset = -EHRegOffset - EHRegSize;
3451  FuncInfo.EHRegNodeEndOffset = EndOffset;
3452 
3453  if (UsedReg == FramePtr) {
3454  // ADD $offset, %ebp
3455  unsigned ADDri = getADDriOpcode(false, EndOffset);
3456  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
3457  .addReg(FramePtr)
3458  .addImm(EndOffset)
3460  ->getOperand(3)
3461  .setIsDead();
3462  assert(EndOffset >= 0 &&
3463  "end of registration object above normal EBP position!");
3464  } else if (UsedReg == BasePtr) {
3465  // LEA offset(%ebp), %esi
3466  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
3467  FramePtr, false, EndOffset)
3469  // MOV32rm SavedEBPOffset(%esi), %ebp
3470  assert(X86FI->getHasSEHFramePtrSave());
3471  int Offset =
3472  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
3473  .getFixed();
3474  assert(UsedReg == BasePtr);
3475  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
3476  UsedReg, true, Offset)
3478  } else {
3479  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
3480  }
3481  return MBBI;
3482 }
3483 
3485  return TRI->getSlotSize();
3486 }
3487 
3488 Register
3490  return TRI->getDwarfRegNum(StackPtr, true);
3491 }
3492 
3493 namespace {
3494 // Struct used by orderFrameObjects to help sort the stack objects.
3495 struct X86FrameSortingObject {
3496  bool IsValid = false; // true if we care about this Object.
3497  unsigned ObjectIndex = 0; // Index of Object into MFI list.
3498  unsigned ObjectSize = 0; // Size of Object in bytes.
3499  Align ObjectAlignment = Align(1); // Alignment of Object in bytes.
3500  unsigned ObjectNumUses = 0; // Object static number of uses.
3501 };
3502 
3503 // The comparison function we use for std::sort to order our local
3504 // stack symbols. The current algorithm is to use an estimated
3505 // "density". This takes into consideration the size and number of
3506 // uses each object has in order to roughly minimize code size.
3507 // So, for example, an object of size 16B that is referenced 5 times
3508 // will get higher priority than 4 4B objects referenced 1 time each.
3509 // It's not perfect and we may be able to squeeze a few more bytes out of
3510 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
3511 // fringe end can have special consideration, given their size is less
3512 // important, etc.), but the algorithmic complexity grows too much to be
3513 // worth the extra gains we get. This gets us pretty close.
3514 // The final order leaves us with objects with highest priority going
3515 // at the end of our list.
3516 struct X86FrameSortingComparator {
3517  inline bool operator()(const X86FrameSortingObject &A,
3518  const X86FrameSortingObject &B) const {
3519  uint64_t DensityAScaled, DensityBScaled;
3520 
3521  // For consistency in our comparison, all invalid objects are placed
3522  // at the end. This also allows us to stop walking when we hit the
3523  // first invalid item after it's all sorted.
3524  if (!A.IsValid)
3525  return false;
3526  if (!B.IsValid)
3527  return true;
3528 
3529  // The density is calculated by doing :
3530  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3531  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3532  // Since this approach may cause inconsistencies in
3533  // the floating point <, >, == comparisons, depending on the floating
3534  // point model with which the compiler was built, we're going
3535  // to scale both sides by multiplying with
3536  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3537  // the division and, with it, the need for any floating point
3538  // arithmetic.
3539  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3540  static_cast<uint64_t>(B.ObjectSize);
3541  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3542  static_cast<uint64_t>(A.ObjectSize);
3543 
3544  // If the two densities are equal, prioritize highest alignment
3545  // objects. This allows for similar alignment objects
3546  // to be packed together (given the same density).
3547  // There's room for improvement here, also, since we can pack
3548  // similar alignment (different density) objects next to each
3549  // other to save padding. This will also require further
3550  // complexity/iterations, and the overall gain isn't worth it,
3551  // in general. Something to keep in mind, though.
3552  if (DensityAScaled == DensityBScaled)
3553  return A.ObjectAlignment < B.ObjectAlignment;
3554 
3555  return DensityAScaled < DensityBScaled;
3556  }
3557 };
3558 } // namespace
3559 
3560 // Order the symbols in the local stack.
3561 // We want to place the local stack objects in some sort of sensible order.
3562 // The heuristic we use is to try and pack them according to static number
3563 // of uses and size of object in order to minimize code size.
3565  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3566  const MachineFrameInfo &MFI = MF.getFrameInfo();
3567 
3568  // Don't waste time if there's nothing to do.
3569  if (ObjectsToAllocate.empty())
3570  return;
3571 
3572  // Create an array of all MFI objects. We won't need all of these
3573  // objects, but we're going to create a full array of them to make
3574  // it easier to index into when we're counting "uses" down below.
3575  // We want to be able to easily/cheaply access an object by simply
3576  // indexing into it, instead of having to search for it every time.
3577  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3578 
3579  // Walk the objects we care about and mark them as such in our working
3580  // struct.
3581  for (auto &Obj : ObjectsToAllocate) {
3582  SortingObjects[Obj].IsValid = true;
3583  SortingObjects[Obj].ObjectIndex = Obj;
3584  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlign(Obj);
3585  // Set the size.
3586  int ObjectSize = MFI.getObjectSize(Obj);
3587  if (ObjectSize == 0)
3588  // Variable size. Just use 4.
3589  SortingObjects[Obj].ObjectSize = 4;
3590  else
3591  SortingObjects[Obj].ObjectSize = ObjectSize;
3592  }
3593 
3594  // Count the number of uses for each object.
3595  for (auto &MBB : MF) {
3596  for (auto &MI : MBB) {
3597  if (MI.isDebugInstr())
3598  continue;
3599  for (const MachineOperand &MO : MI.operands()) {
3600  // Check to see if it's a local stack symbol.
3601  if (!MO.isFI())
3602  continue;
3603  int Index = MO.getIndex();
3604  // Check to see if it falls within our range, and is tagged
3605  // to require ordering.
3606  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3607  SortingObjects[Index].IsValid)
3608  SortingObjects[Index].ObjectNumUses++;
3609  }
3610  }
3611  }
3612 
3613  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3614  // info).
3615  llvm::stable_sort(SortingObjects, X86FrameSortingComparator());
3616 
3617  // Now modify the original list to represent the final order that
3618  // we want. The order will depend on whether we're going to access them
3619  // from the stack pointer or the frame pointer. For SP, the list should
3620  // end up with the END containing objects that we want with smaller offsets.
3621  // For FP, it should be flipped.
3622  int i = 0;
3623  for (auto &Obj : SortingObjects) {
3624  // All invalid items are sorted at the end, so it's safe to stop.
3625  if (!Obj.IsValid)
3626  break;
3627  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3628  }
3629 
3630  // Flip it if we're accessing off of the FP.
3631  if (!TRI->hasStackRealignment(MF) && hasFP(MF))
3632  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3633 }
3634 
3635 
3637  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3638  unsigned Offset = 16;
3639  // RBP is immediately pushed.
3640  Offset += SlotSize;
3641  // All callee-saved registers are then pushed.
3642  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3643  // Every funclet allocates enough stack space for the largest outgoing call.
3644  Offset += getWinEHFuncletFrameSize(MF);
3645  return Offset;
3646 }
3647 
3649  MachineFunction &MF, RegScavenger *RS) const {
3650  // Mark the function as not having WinCFI. We will set it back to true in
3651  // emitPrologue if it gets called and emits CFI.
3652  MF.setHasWinCFI(false);
3653 
3654  // If we are using Windows x64 CFI, ensure that the stack is always 8 byte
3655  // aligned. The format doesn't support misaligned stack adjustments.
3656  if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
3658 
3659  // If this function isn't doing Win64-style C++ EH, we don't need to do
3660  // anything.
3661  if (STI.is64Bit() && MF.hasEHFunclets() &&
3664  adjustFrameForMsvcCxxEh(MF);
3665  }
3666 }
3667 
3668 void X86FrameLowering::adjustFrameForMsvcCxxEh(MachineFunction &MF) const {
3669  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3670  // relative to RSP after the prologue. Find the offset of the last fixed
3671  // object, so that we can allocate a slot immediately following it. If there
3672  // were no fixed objects, use offset -SlotSize, which is immediately after the
3673  // return address. Fixed objects have negative frame indices.
3674  MachineFrameInfo &MFI = MF.getFrameInfo();
3675  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3676  int64_t MinFixedObjOffset = -SlotSize;
3677  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3678  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3679 
3680  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3681  for (WinEHHandlerType &H : TBME.HandlerArray) {
3682  int FrameIndex = H.CatchObj.FrameIndex;
3683  if (FrameIndex != INT_MAX) {
3684  // Ensure alignment.
3685  unsigned Align = MFI.getObjectAlign(FrameIndex).value();
3686  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3687  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3688  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3689  }
3690  }
3691  }
3692 
3693  // Ensure alignment.
3694  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3695  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3696  int UnwindHelpFI =
3697  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*IsImmutable=*/false);
3698  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3699 
3700  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3701  // other frame setup instructions.
3702  MachineBasicBlock &MBB = MF.front();
3703  auto MBBI = MBB.begin();
3704  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3705  ++MBBI;
3706 
3708  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3709  UnwindHelpFI)
3710  .addImm(-2);
3711 }
3712 
3714  MachineFunction &MF, RegScavenger *RS) const {
3715  if (STI.is32Bit() && MF.hasEHFunclets())
3717 }
3718 
3720  MachineFunction &MF) const {
3721  // 32-bit functions have to restore stack pointers when control is transferred
3722  // back to the parent function. These blocks are identified as eh pads that
3723  // are not funclet entries.
3724  bool IsSEH = isAsynchronousEHPersonality(
3726  for (MachineBasicBlock &MBB : MF) {
3727  bool NeedsRestore = MBB.isEHPad() && !MBB.isEHFuncletEntry();
3728  if (NeedsRestore)
3730  /*RestoreSP=*/IsSEH);
3731  }
3732 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:708
llvm::EHPersonality::MSVC_CXX
@ MSVC_CXX
llvm::X86Subtarget::hasBWI
bool hasBWI() const
Definition: X86Subtarget.h:750
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::X86FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: X86FrameLowering.cpp:59
llvm::isAsynchronousEHPersonality
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
Definition: EHPersonalities.h:50
getADDriOpcode
static unsigned getADDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:117
llvm::X86FrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: X86FrameLowering.cpp:3378
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::dwarf::CallingConvention
CallingConvention
Definition: Dwarf.h:330
llvm::MCContext::getObjectFileInfo
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:427
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::X86FrameLowering::TRI
const X86RegisterInfo * TRI
Definition: X86FrameLowering.h:35
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::X86MachineFunctionInfo::getArgumentStackSize
unsigned getArgumentStackSize() const
Definition: X86MachineFunctionInfo.h:179
llvm::X86FrameLowering::adjustForHiPEPrologue
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime.
Definition: X86FrameLowering.cpp:3049
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
calculateSetFPREG
static unsigned calculateSetFPREG(uint64_t SPAdjust)
Definition: X86FrameLowering.cpp:1037
llvm::X86FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: X86FrameLowering.cpp:2534
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
it
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Definition: README-SSE.txt:81
llvm::NamedMDNode
A tuple of MDNodes.
Definition: Metadata.h:1396
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:575
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:53718
llvm::X86MachineFunctionInfo::getRestoreBasePointer
bool getRestoreBasePointer() const
Definition: X86MachineFunctionInfo.h:138
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::NamedMDNode::getNumOperands
unsigned getNumOperands() const
Definition: Metadata.cpp:1120
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:167
X86Subtarget.h
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Function
Definition: Function.h:61
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:852
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:93
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:560
llvm::X86MachineFunctionInfo::hasSwiftAsyncContext
bool hasSwiftAsyncContext() const
Definition: X86MachineFunctionInfo.h:207
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1023
X86InstrBuilder.h
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::MachineFrameInfo::hasCopyImplyingStackAdjustment
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
Definition: MachineFrameInfo.h:590
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:552
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineFrameInfo::setCVBytesOfCalleeSavedRegisters
void setCVBytesOfCalleeSavedRegisters(unsigned S)
Definition: MachineFrameInfo.h:639
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:60
llvm::X86InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:917
Statistic.h
llvm::Module::getCodeViewFlag
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:571
llvm::X86MachineFunctionInfo::setCalleeSavedFrameSize
void setCalleeSavedFrameSize(unsigned bytes)
Definition: X86MachineFunctionInfo.h:147
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:852
llvm::recomputeLiveIns
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Definition: LivePhysRegs.h:196
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:619
isEAXLiveIn
static bool isEAXLiveIn(MachineBasicBlock &MBB)
Definition: X86FrameLowering.cpp:152
llvm::WinEHHandlerType
Definition: WinEHFuncInfo.h:60
llvm::X86FrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: X86FrameLowering.cpp:2421
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:805
llvm::X86FrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: X86FrameLowering.cpp:3404
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1373
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
getSUBrrOpcode
static unsigned getSUBrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:129
llvm::X86TargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: X86ISelLowering.cpp:53764
MCObjectFileInfo.h
llvm::MachineFunction::push_front
void push_front(MachineBasicBlock *MBB)
Definition: MachineFunction.h:826
llvm::Function::arg_size
size_t arg_size() const
Definition: Function.h:781
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::X86MachineFunctionInfo::setHasSEHFramePtrSave
void setHasSEHFramePtrSave(bool V)
Definition: X86MachineFunctionInfo.h:186
llvm::WinEHFuncInfo::TryBlockMap
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
llvm::BranchProbability::getZero
static BranchProbability getZero()
Definition: BranchProbability.h:49
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:412
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:556
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:333
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::X86FrameLowering::orderFrameObjects
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
Definition: X86FrameLowering.cpp:3564
getANDriOpcode
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:137
llvm::addRegOffset
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset],...
Definition: X86InstrBuilder.h:157
EHPersonalities.h
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:827
llvm::X86FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: X86FrameLowering.cpp:3259
llvm::MachineFunction::callsUnwindInit
bool callsUnwindInit() const
Definition: MachineFunction.h:1041
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::X86MachineFunctionInfo::getRestoreBasePointerOffset
int getRestoreBasePointerOffset() const
Definition: X86MachineFunctionInfo.h:140
llvm::X86FrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: X86FrameLowering.cpp:3368
HasNestArgument
static bool HasNestArgument(const MachineFunction *MF)
Definition: X86FrameLowering.cpp:2704
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:288
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:886
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:622
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
llvm::X86FrameLowering::has128ByteRedZone
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
Definition: X86FrameLowering.cpp:1216
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:502
llvm::X86Subtarget::is32Bit
bool is32Bit() const
Definition: X86Subtarget.h:610
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineFunction::getFrameInstructions
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the function's prologue.
Definition: MachineFunction.h:1006
isTailCallOpcode
static bool isTailCallOpcode(unsigned Opc)
Definition: X86FrameLowering.cpp:2009
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
flagsNeedToBePreservedBeforeTheTerminators
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
Definition: X86FrameLowering.cpp:169
X86FrameLowering.h
llvm::SwiftAsyncFramePointerMode::Never
@ Never
Never set the bit.
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:348
llvm::X86MachineFunctionInfo::getHasPushSequences
bool getHasPushSequences() const
Definition: X86MachineFunctionInfo.h:135
llvm::X86FrameLowering::getFrameIndexReferencePreferSP
StackOffset getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, Register &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
Definition: X86FrameLowering.cpp:2339
llvm::X86MachineFunctionInfo::hasPreallocatedCall
bool hasPreallocatedCall() const
Definition: X86MachineFunctionInfo.h:204
getADDrrOpcode
static unsigned getADDrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:133
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:21
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:746
getLEArOpcode
static unsigned getLEArOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:148
llvm::X86FrameLowering::restoreWinEHStackPointersInParent
void restoreWinEHStackPointersInParent(MachineFunction &MF) const
Definition: X86FrameLowering.cpp:3719
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
X86MachineFunctionInfo.h
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1551
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:820
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
PageSize
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
llvm::X86FrameLowering::getWin64EHFrameIndexRef
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
Definition: X86FrameLowering.cpp:2313
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::X86FrameLowering::needsFrameIndexResolution
bool needsFrameIndexResolution(const MachineFunction &MF) const override
Definition: X86FrameLowering.cpp:85
llvm::X86MachineFunctionInfo::setSEHFramePtrSaveIndex
void setSEHFramePtrSaveIndex(int Index)
Definition: X86MachineFunctionInfo.h:189
llvm::X86FrameLowering::getFrameIndexReferenceSP
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
Definition: X86FrameLowering.cpp:2329
llvm::MachineFrameInfo::ensureMaxAlignment
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
Definition: MachineFrameInfo.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:484
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::X86FrameLowering::BuildCFI
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
Definition: X86FrameLowering.cpp:425
llvm::X86Subtarget::isTargetWin32
bool isTargetWin32() const
Definition: X86Subtarget.h:888
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:999
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::X86MachineFunctionInfo::getTCReturnAddrDelta
int getTCReturnAddrDelta() const
Definition: X86MachineFunctionInfo.h:158
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::WinEHFuncInfo::EHRegNodeFrameIndex
int EHRegNodeFrameIndex
Definition: WinEHFuncInfo.h:107
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::X86RegisterInfo::getFramePtr
Register getFramePtr() const
Returns physical register used as frame pointer.
Definition: X86RegisterInfo.h:144
MCSymbol.h
llvm::X86MachineFunctionInfo::getCalleeSavedFrameSize
unsigned getCalleeSavedFrameSize() const
Definition: X86MachineFunctionInfo.h:146
llvm::MVT::v64i1
@ v64i1
Definition: MachineValueType.h:70
llvm::X86FrameLowering::canUseLEAForSPInEpilogue
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
Definition: X86FrameLowering.cpp:1932
llvm::X86RegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: X86RegisterInfo.h:139
llvm::X86Subtarget::isTargetWindowsCoreCLR
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:866
llvm::X86FrameLowering::TII
const X86InstrInfo & TII
Definition: X86FrameLowering.h:34
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::MVT::v16i1
@ v16i1
Definition: MachineValueType.h:68
llvm::MCObjectFileInfo::getCompactUnwindSection
MCSection * getCompactUnwindSection() const
Definition: MCObjectFileInfo.h:263
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:753
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::codeview::ProcSymFlags::HasFP
@ HasFP
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
STATISTIC
STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue")
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:78
llvm::X86::COND_A
@ COND_A
Definition: X86BaseInfo.h:88
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::X86FrameLowering::processFunctionBeforeFrameIndicesReplaced
void processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameIndicesReplaced - This method is called immediately before MO_FrameIndex op...
Definition: X86FrameLowering.cpp:3713
llvm::Function::hasPersonalityFn
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:785
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:280
llvm::X86InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3862
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:808
llvm::X86TargetLowering
Definition: X86ISelLowering.h:918
llvm::MachineFunction::setHasWinCFI
void setHasWinCFI(bool v)
Definition: MachineFunction.h:711
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:597
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::X86FrameLowering::restoreWin32EHStackPointers
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
Definition: X86FrameLowering.cpp:3421
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineBasicBlock::isCleanupFuncletEntry
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
Definition: MachineBasicBlock.h:558
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:326
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:656
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isOSWindows
bool isOSWindows() const
Definition: X86Subtarget.h:884
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:390
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:53723
llvm::X86FrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: X86FrameLowering.cpp:3648
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:434
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:495
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:624
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:326
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:577
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::X86FrameLowering::emitSPUpdate
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value.
Definition: X86FrameLowering.cpp:205
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::WinEHTryBlockMapEntry
Definition: WinEHFuncInfo.h:72
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::WinEHFuncInfo
Definition: WinEHFuncInfo.h:90
llvm::X86::COND_AE
@ COND_AE
Definition: X86BaseInfo.h:84
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:443
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFunction::callsEHReturn
bool callsEHReturn() const
Definition: MachineFunction.h:1038
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::X86MachineFunctionInfo::getUsesRedZone
bool getUsesRedZone() const
Definition: X86MachineFunctionInfo.h:198
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::CallingConv::HiPE
@ HiPE
Definition: CallingConv.h:55
llvm::MCCFIInstruction::createGnuArgsSize
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:593
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:786
AH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference AH
Definition: README-X86-64.txt:44
llvm::X86MachineFunctionInfo::getWinEHXMMSlotInfo
DenseMap< int, unsigned > & getWinEHXMMSlotInfo()
Definition: X86MachineFunctionInfo.h:142
llvm::X86FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: X86FrameLowering.cpp:1319
llvm::TargetOptions::SwiftAsyncFramePointer
SwiftAsyncFramePointerMode SwiftAsyncFramePointer
Control when and how the Swift async frame pointer bit should be set.
Definition: TargetOptions.h:235
llvm::X86FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: X86FrameLowering.cpp:2635
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::WinEHTryBlockMapEntry::HandlerArray
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1003
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::X86InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3894
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:528
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:200
llvm::CallingConv::X86_INTR
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:189
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:414
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::NamedMDNode::getOperand
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1124
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:556
llvm::MachineBasicBlock::setHasAddressTaken
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
Definition: MachineBasicBlock.h:215
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::X86FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: X86FrameLowering.cpp:2016
llvm::X86FrameLowering::mergeSPUpdates
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
Definition: X86FrameLowering.cpp:363
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
blockEndIsUnreachable
static bool blockEndIsUnreachable(const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI)
Definition: X86FrameLowering.cpp:3024
llvm::MachineFunction::getLandingPads
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
Definition: MachineFunction.h:1061
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:446
MachineModuleInfo.h
llvm::WinEHFuncInfo::UnwindHelpFrameIdx
int UnwindHelpFrameIdx
Definition: WinEHFuncInfo.h:99
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::X86Subtarget::isTargetDragonFly
bool isTargetDragonFly() const
Definition: X86Subtarget.h:844
GetScratchRegister
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
Definition: X86FrameLowering.cpp:2719
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::ValueAsMetadata::getValue
Value * getValue() const
Definition: Metadata.h:384
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::EHPersonality::CoreCLR
@ CoreCLR
llvm::X86::COND_LE
@ COND_LE
Definition: X86BaseInfo.h:95
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineModuleInfo::setHasNosplitStack
void setHasNosplitStack(bool b)
Definition: MachineModuleInfo.h:230
llvm::BranchProbability::getOne
static BranchProbability getOne()
Definition: BranchProbability.h:50
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:755
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:207
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1206
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:842
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFrameInfo::hasPatchPoint
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:386
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
DataLayout.h
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:526
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:950
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::X86MachineFunctionInfo::getFAIndex
int getFAIndex() const
Definition: X86MachineFunctionInfo.h:155
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SwiftAsyncFramePointerMode::DeploymentBased
@ DeploymentBased
Determine whether to set the bit statically or dynamically based on the deployment target.
llvm::X86FrameLowering::emitStackProbe
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const
Emit target stack probe code.
Definition: X86FrameLowering.cpp:487
llvm::MCCFIInstruction::createAdjustCfaOffset
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:509
llvm::WinEHFuncInfo::EHRegNodeEndOffset
int EHRegNodeEndOffset
Definition: WinEHFuncInfo.h:108
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::X86FrameLowering::adjustForSegmentedStacks
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
Definition: X86FrameLowering.cpp:2756
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:273
llvm::EHPersonality
EHPersonality
Definition: EHPersonalities.h:22
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:139
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::X86InstrInfo::getFrameAdjustment
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:153
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:368
llvm::WinEHFuncInfo::PSPSymFrameIdx
int PSPSymFrameIdx
Definition: WinEHFuncInfo.h:100
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1578
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
llvm::X86AS::GS
@ GS
Definition: X86.h:187
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:547
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::EHPersonality::Unknown
@ Unknown
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86Subtarget::isTargetFreeBSD
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:843
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1686
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:436
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::X86FrameLowering::SlotSize
unsigned SlotSize
Definition: X86FrameLowering.h:37
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
H
#define H(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:587
llvm::X86Subtarget::isTargetWindowsMSVC
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:862
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::X86FrameLowering::STI
const X86Subtarget & STI
Definition: X86FrameLowering.h:33
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:899
X86TargetMachine.h
llvm::X86RegisterInfo::findDeadCallerSavedReg
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
Definition: X86RegisterInfo.cpp:803
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1312
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineFunction::getWinEHFuncInfo
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
Definition: MachineFunction.h:670
llvm::X86FrameLowering::inlineStackProbe
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
Definition: X86FrameLowering.cpp:504
llvm::X86RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:645
Function.h
llvm::DenseMapBase::size
unsigned size() const
Definition: DenseMap.h:100
llvm::X86FrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: X86FrameLowering.cpp:2689
llvm::X86MachineFunctionInfo::setUsesRedZone
void setUsesRedZone(bool V)
Definition: X86MachineFunctionInfo.h:199
llvm::Function::needsUnwindTableEntry
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:646
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::X86MachineFunctionInfo::getHasSEHFramePtrSave
bool getHasSEHFramePtrSave() const
Definition: X86MachineFunctionInfo.h:185
llvm::Function::getPersonalityFn
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1823
llvm::MachineFunction::hasEHFunclets
bool hasEHFunclets() const
Definition: MachineFunction.h:1050
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
WinEHFuncInfo.h
llvm::X86FrameLowering::IsLP64
bool IsLP64
Definition: X86FrameLowering.h:42
llvm::X86MachineFunctionInfo::getForceFramePointer
bool getForceFramePointer() const
Definition: X86MachineFunctionInfo.h:132
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::X86FrameLowering::X86FrameLowering
X86FrameLowering(const X86Subtarget &STI, MaybeAlign StackAlignOverride)
Definition: X86FrameLowering.cpp:45
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:189
false
Function Alias Analysis false
Definition: AliasAnalysis.cpp:847
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:285
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::CallingConv::X86_FastCall
@ X86_FastCall
X86_FastCall - 'fast' analog of X86_StdCall.
Definition: CallingConv.h:107
llvm::skipDebugInstructionsBackward
IterT skipDebugInstructionsBackward(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It until it points to a non-debug instruction or to Begin and return the resulting iterator...
Definition: MachineBasicBlock.h:1219
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
isFuncletReturnInstr
static bool isFuncletReturnInstr(MachineInstr &MI)
Definition: X86FrameLowering.cpp:1943
llvm::X86FrameLowering::canSimplifyCallFramePseudos
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
Definition: X86FrameLowering.cpp:70
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:146
llvm::ARM::WinEH::StackAdjustment
uint16_t StackAdjustment(const RuntimeFunction &RF)
StackAdjustment - calculated stack adjustment in words.
Definition: ARMWinEH.h:199
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::X86FrameLowering::Is64Bit
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
Definition: X86FrameLowering.h:40
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:128
llvm::X86TargetLowering::getStackProbeSymbolName
StringRef getStackProbeSymbolName(MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition: X86ISelLowering.cpp:53741
llvm::Module::getNamedMetadata
NamedMDNode * getNamedMetadata(const Twine &Name) const
Return the first NamedMDNode in the module with the specified name.
Definition: Module.cpp:254
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::WinEHFuncInfo::SEHSetFrameOffset
int SEHSetFrameOffset
Definition: WinEHFuncInfo.h:110
llvm::X86FrameLowering::Uses64BitFramePtr
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
Definition: