LLVM  14.0.0git
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
14 #include "X86InstrBuilder.h"
15 #include "X86InstrInfo.h"
16 #include "X86MachineFunctionInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/Statistic.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCSymbol.h"
33 #include "llvm/Support/Debug.h"
35 #include <cstdlib>
36 
37 #define DEBUG_TYPE "x86-fl"
38 
39 STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue");
40 STATISTIC(NumFrameExtraProbe,
41  "Number of extra stack probes generated in prologue");
42 
43 using namespace llvm;
44 
46  MaybeAlign StackAlignOverride)
47  : TargetFrameLowering(StackGrowsDown, StackAlignOverride.valueOrOne(),
48  STI.is64Bit() ? -8 : -4),
49  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
50  // Cache a bunch of frame-related predicates for this subtarget.
52  Is64Bit = STI.is64Bit();
54  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
57 }
58 
60  return !MF.getFrameInfo().hasVarSizedObjects() &&
61  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences() &&
62  !MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall();
63 }
64 
65 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
66 /// call frame pseudos can be simplified. Having a FP, as in the default
67 /// implementation, is not sufficient here since we can't always use it.
68 /// Use a more nuanced condition.
69 bool
71  return hasReservedCallFrame(MF) ||
72  MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall() ||
73  (hasFP(MF) && !TRI->hasStackRealignment(MF)) ||
74  TRI->hasBasePointer(MF);
75 }
76 
77 // needsFrameIndexResolution - Do we need to perform FI resolution for
78 // this function. Normally, this is required only when the function
79 // has any stack objects. However, FI resolution actually has another job,
80 // not apparent from the title - it resolves callframesetup/destroy
81 // that were not simplified earlier.
82 // So, this is required for x86 functions that have push sequences even
83 // when there are no stack objects.
84 bool
86  return MF.getFrameInfo().hasStackObjects() ||
87  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
88 }
89 
90 /// hasFP - Return true if the specified function should have a dedicated frame
91 /// pointer register. This is true if the function has variable sized allocas
92 /// or if frame pointer elimination is disabled.
94  const MachineFrameInfo &MFI = MF.getFrameInfo();
95  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
96  TRI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
100  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
101  MFI.hasStackMap() || MFI.hasPatchPoint() ||
103 }
104 
105 static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) {
106  if (IsLP64) {
107  if (isInt<8>(Imm))
108  return X86::SUB64ri8;
109  return X86::SUB64ri32;
110  } else {
111  if (isInt<8>(Imm))
112  return X86::SUB32ri8;
113  return X86::SUB32ri;
114  }
115 }
116 
117 static unsigned getADDriOpcode(bool IsLP64, int64_t Imm) {
118  if (IsLP64) {
119  if (isInt<8>(Imm))
120  return X86::ADD64ri8;
121  return X86::ADD64ri32;
122  } else {
123  if (isInt<8>(Imm))
124  return X86::ADD32ri8;
125  return X86::ADD32ri;
126  }
127 }
128 
129 static unsigned getSUBrrOpcode(bool IsLP64) {
130  return IsLP64 ? X86::SUB64rr : X86::SUB32rr;
131 }
132 
133 static unsigned getADDrrOpcode(bool IsLP64) {
134  return IsLP64 ? X86::ADD64rr : X86::ADD32rr;
135 }
136 
137 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
138  if (IsLP64) {
139  if (isInt<8>(Imm))
140  return X86::AND64ri8;
141  return X86::AND64ri32;
142  }
143  if (isInt<8>(Imm))
144  return X86::AND32ri8;
145  return X86::AND32ri;
146 }
147 
148 static unsigned getLEArOpcode(bool IsLP64) {
149  return IsLP64 ? X86::LEA64r : X86::LEA32r;
150 }
151 
152 static unsigned getMOVriOpcode(bool Use64BitReg, int64_t Imm) {
153  if (Use64BitReg) {
154  if (isUInt<32>(Imm))
155  return X86::MOV32ri64;
156  if (isInt<32>(Imm))
157  return X86::MOV64ri32;
158  return X86::MOV64ri;
159  }
160  return X86::MOV32ri;
161 }
162 
165  unsigned Reg = RegMask.PhysReg;
166 
167  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
168  Reg == X86::AH || Reg == X86::AL)
169  return true;
170  }
171 
172  return false;
173 }
174 
175 /// Check if the flags need to be preserved before the terminators.
176 /// This would be the case, if the eflags is live-in of the region
177 /// composed by the terminators or live-out of that region, without
178 /// being defined by a terminator.
179 static bool
181  for (const MachineInstr &MI : MBB.terminators()) {
182  bool BreakNext = false;
183  for (const MachineOperand &MO : MI.operands()) {
184  if (!MO.isReg())
185  continue;
186  Register Reg = MO.getReg();
187  if (Reg != X86::EFLAGS)
188  continue;
189 
190  // This terminator needs an eflags that is not defined
191  // by a previous another terminator:
192  // EFLAGS is live-in of the region composed by the terminators.
193  if (!MO.isDef())
194  return true;
195  // This terminator defines the eflags, i.e., we don't need to preserve it.
196  // However, we still need to check this specific terminator does not
197  // read a live-in value.
198  BreakNext = true;
199  }
200  // We found a definition of the eflags, no need to preserve them.
201  if (BreakNext)
202  return false;
203  }
204 
205  // None of the terminators use or define the eflags.
206  // Check if they are live-out, that would imply we need to preserve them.
207  for (const MachineBasicBlock *Succ : MBB.successors())
208  if (Succ->isLiveIn(X86::EFLAGS))
209  return true;
210 
211  return false;
212 }
213 
214 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
215 /// stack pointer by a constant value.
218  const DebugLoc &DL,
219  int64_t NumBytes, bool InEpilogue) const {
220  bool isSub = NumBytes < 0;
221  uint64_t Offset = isSub ? -NumBytes : NumBytes;
224 
225  uint64_t Chunk = (1LL << 31) - 1;
226 
227  MachineFunction &MF = *MBB.getParent();
228  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
229  const X86TargetLowering &TLI = *STI.getTargetLowering();
230  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
231 
232  // It's ok to not take into account large chunks when probing, as the
233  // allocation is split in smaller chunks anyway.
234  if (EmitInlineStackProbe && !InEpilogue) {
235 
236  // This pseudo-instruction is going to be expanded, potentially using a
237  // loop, by inlineStackProbe().
238  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset);
239  return;
240  } else if (Offset > Chunk) {
241  // Rather than emit a long series of instructions for large offsets,
242  // load the offset into a register and do one sub/add
243  unsigned Reg = 0;
244  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
245 
246  if (isSub && !isEAXLiveIn(MBB))
247  Reg = Rax;
248  else
250 
251  unsigned AddSubRROpc =
253  if (Reg) {
255  .addImm(Offset)
256  .setMIFlag(Flag);
257  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
258  .addReg(StackPtr)
259  .addReg(Reg);
260  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
261  return;
262  } else if (Offset > 8 * Chunk) {
263  // If we would need more than 8 add or sub instructions (a >16GB stack
264  // frame), it's worth spilling RAX to materialize this immediate.
265  // pushq %rax
266  // movabsq +-$Offset+-SlotSize, %rax
267  // addq %rsp, %rax
268  // xchg %rax, (%rsp)
269  // movq (%rsp), %rsp
270  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
271  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
272  .addReg(Rax, RegState::Kill)
273  .setMIFlag(Flag);
274  // Subtract is not commutative, so negate the offset and always use add.
275  // Subtract 8 less and add 8 more to account for the PUSH we just did.
276  if (isSub)
277  Offset = -(Offset - SlotSize);
278  else
279  Offset = Offset + SlotSize;
281  .addImm(Offset)
282  .setMIFlag(Flag);
283  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
284  .addReg(Rax)
285  .addReg(StackPtr);
286  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
287  // Exchange the new SP in RAX with the top of the stack.
288  addRegOffset(
289  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
290  StackPtr, false, 0);
291  // Load new SP from the top of the stack into RSP.
292  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
293  StackPtr, false, 0);
294  return;
295  }
296  }
297 
298  while (Offset) {
299  uint64_t ThisVal = std::min(Offset, Chunk);
300  if (ThisVal == SlotSize) {
301  // Use push / pop for slot sized adjustments as a size optimization. We
302  // need to find a dead register when using pop.
303  unsigned Reg = isSub
304  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
306  if (Reg) {
307  unsigned Opc = isSub
308  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
309  : (Is64Bit ? X86::POP64r : X86::POP32r);
310  BuildMI(MBB, MBBI, DL, TII.get(Opc))
311  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
312  .setMIFlag(Flag);
313  Offset -= ThisVal;
314  continue;
315  }
316  }
317 
318  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
319  .setMIFlag(Flag);
320 
321  Offset -= ThisVal;
322  }
323 }
324 
325 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
327  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
328  assert(Offset != 0 && "zero offset stack adjustment requested");
329 
330  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
331  // is tricky.
332  bool UseLEA;
333  if (!InEpilogue) {
334  // Check if inserting the prologue at the beginning
335  // of MBB would require to use LEA operations.
336  // We need to use LEA operations if EFLAGS is live in, because
337  // it means an instruction will read it before it gets defined.
338  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
339  } else {
340  // If we can use LEA for SP but we shouldn't, check that none
341  // of the terminators uses the eflags. Otherwise we will insert
342  // a ADD that will redefine the eflags and break the condition.
343  // Alternatively, we could move the ADD, but this may not be possible
344  // and is an optimization anyway.
346  if (UseLEA && !STI.useLeaForSP())
348  // If that assert breaks, that means we do not do the right thing
349  // in canUseAsEpilogue.
351  "We shouldn't have allowed this insertion point");
352  }
353 
355  if (UseLEA) {
358  StackPtr),
359  StackPtr, false, Offset);
360  } else {
361  bool IsSub = Offset < 0;
362  uint64_t AbsOffset = IsSub ? -Offset : Offset;
363  const unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
364  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
365  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
366  .addReg(StackPtr)
367  .addImm(AbsOffset);
368  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
369  }
370  return MI;
371 }
372 
375  bool doMergeWithPrevious) const {
376  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
377  (!doMergeWithPrevious && MBBI == MBB.end()))
378  return 0;
379 
380  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
381 
383  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
384  // instruction, and that there are no DBG_VALUE or other instructions between
385  // ADD/SUB/LEA and its corresponding CFI instruction.
386  /* TODO: Add support for the case where there are multiple CFI instructions
387  below the ADD/SUB/LEA, e.g.:
388  ...
389  add
390  cfi_def_cfa_offset
391  cfi_offset
392  ...
393  */
394  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
395  PI = std::prev(PI);
396 
397  unsigned Opc = PI->getOpcode();
398  int Offset = 0;
399 
400  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
401  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
402  PI->getOperand(0).getReg() == StackPtr){
403  assert(PI->getOperand(1).getReg() == StackPtr);
404  Offset = PI->getOperand(2).getImm();
405  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
406  PI->getOperand(0).getReg() == StackPtr &&
407  PI->getOperand(1).getReg() == StackPtr &&
408  PI->getOperand(2).getImm() == 1 &&
409  PI->getOperand(3).getReg() == X86::NoRegister &&
410  PI->getOperand(5).getReg() == X86::NoRegister) {
411  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
412  Offset = PI->getOperand(4).getImm();
413  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
414  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
415  PI->getOperand(0).getReg() == StackPtr) {
416  assert(PI->getOperand(1).getReg() == StackPtr);
417  Offset = -PI->getOperand(2).getImm();
418  } else
419  return 0;
420 
421  PI = MBB.erase(PI);
422  if (PI != MBB.end() && PI->isCFIInstruction()) {
423  auto CIs = MBB.getParent()->getFrameInstructions();
424  MCCFIInstruction CI = CIs[PI->getOperand(0).getCFIIndex()];
427  PI = MBB.erase(PI);
428  }
429  if (!doMergeWithPrevious)
431 
432  return Offset;
433 }
434 
437  const DebugLoc &DL,
438  const MCCFIInstruction &CFIInst) const {
439  MachineFunction &MF = *MBB.getParent();
440  unsigned CFIIndex = MF.addFrameInst(CFIInst);
441  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
442  .addCFIIndex(CFIIndex);
443 }
444 
445 /// Emits Dwarf Info specifying offsets of callee saved registers and
446 /// frame pointer. This is called only when basic block sections are enabled.
449  MachineFunction &MF = *MBB.getParent();
450  if (!hasFP(MF)) {
452  return;
453  }
454  const MachineModuleInfo &MMI = MF.getMMI();
455  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
456  const Register FramePtr = TRI->getFrameRegister(MF);
457  const Register MachineFramePtr =
459  : FramePtr;
460  unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true);
461  // Offset = space for return address + size of the frame pointer itself.
462  unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
464  MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset));
466 }
467 
470  const DebugLoc &DL, bool IsPrologue) const {
471  MachineFunction &MF = *MBB.getParent();
472  MachineFrameInfo &MFI = MF.getFrameInfo();
473  MachineModuleInfo &MMI = MF.getMMI();
474  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
475 
476  // Add callee saved registers to move list.
477  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
478 
479  // Calculate offsets.
480  for (const CalleeSavedInfo &I : CSI) {
481  int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
482  unsigned Reg = I.getReg();
483  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
484 
485  if (IsPrologue) {
486  BuildCFI(MBB, MBBI, DL,
487  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
488  } else {
489  BuildCFI(MBB, MBBI, DL,
490  MCCFIInstruction::createRestore(nullptr, DwarfReg));
491  }
492  }
493 }
494 
497  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog,
499  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
500  if (STI.isTargetWindowsCoreCLR()) {
501  if (InProlog) {
502  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING))
503  .addImm(0 /* no explicit stack size */);
504  } else {
505  emitStackProbeInline(MF, MBB, MBBI, DL, false);
506  }
507  } else {
508  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog, InstrNum);
509  }
510 }
511 
513  return STI.isOSWindows() && !STI.isTargetWin64();
514 }
515 
517  MachineBasicBlock &PrologMBB) const {
518  auto Where = llvm::find_if(PrologMBB, [](MachineInstr &MI) {
519  return MI.getOpcode() == X86::STACKALLOC_W_PROBING;
520  });
521  if (Where != PrologMBB.end()) {
522  DebugLoc DL = PrologMBB.findDebugLoc(Where);
523  emitStackProbeInline(MF, PrologMBB, Where, DL, true);
524  Where->eraseFromParent();
525  }
526 }
527 
528 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
531  const DebugLoc &DL,
532  bool InProlog) const {
533  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
535  emitStackProbeInlineWindowsCoreCLR64(MF, MBB, MBBI, DL, InProlog);
536  else
537  emitStackProbeInlineGeneric(MF, MBB, MBBI, DL, InProlog);
538 }
539 
540 void X86FrameLowering::emitStackProbeInlineGeneric(
542  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
543  MachineInstr &AllocWithProbe = *MBBI;
544  uint64_t Offset = AllocWithProbe.getOperand(0).getImm();
545 
546  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
547  const X86TargetLowering &TLI = *STI.getTargetLowering();
549  "different expansion expected for CoreCLR 64 bit");
550 
551  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
552  uint64_t ProbeChunk = StackProbeSize * 8;
553 
554  uint64_t MaxAlign =
555  TRI->hasStackRealignment(MF) ? calculateMaxStackAlign(MF) : 0;
556 
557  // Synthesize a loop or unroll it, depending on the number of iterations.
558  // BuildStackAlignAND ensures that only MaxAlign % StackProbeSize bits left
559  // between the unaligned rsp and current rsp.
560  if (Offset > ProbeChunk) {
561  emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL, Offset,
562  MaxAlign % StackProbeSize);
563  } else {
564  emitStackProbeInlineGenericBlock(MF, MBB, MBBI, DL, Offset,
565  MaxAlign % StackProbeSize);
566  }
567 }
568 
569 void X86FrameLowering::emitStackProbeInlineGenericBlock(
572  uint64_t AlignOffset) const {
573 
574  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
575  const bool HasFP = hasFP(MF);
576  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
577  const X86TargetLowering &TLI = *STI.getTargetLowering();
578  const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, Offset);
579  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
580  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
581 
582  uint64_t CurrentOffset = 0;
583 
584  assert(AlignOffset < StackProbeSize);
585 
586  // If the offset is so small it fits within a page, there's nothing to do.
587  if (StackProbeSize < Offset + AlignOffset) {
588 
589  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
590  .addReg(StackPtr)
591  .addImm(StackProbeSize - AlignOffset)
593  if (!HasFP && NeedsDwarfCFI) {
594  BuildCFI(MBB, MBBI, DL,
596  nullptr, StackProbeSize - AlignOffset));
597  }
598  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
599 
600  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
602  StackPtr, false, 0)
603  .addImm(0)
605  NumFrameExtraProbe++;
606  CurrentOffset = StackProbeSize - AlignOffset;
607  }
608 
609  // For the next N - 1 pages, just probe. I tried to take advantage of
610  // natural probes but it implies much more logic and there was very few
611  // interesting natural probes to interleave.
612  while (CurrentOffset + StackProbeSize < Offset) {
613  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
614  .addReg(StackPtr)
615  .addImm(StackProbeSize)
617  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
618 
619  if (!HasFP && NeedsDwarfCFI) {
620  BuildCFI(
621  MBB, MBBI, DL,
622  MCCFIInstruction::createAdjustCfaOffset(nullptr, StackProbeSize));
623  }
624  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
626  StackPtr, false, 0)
627  .addImm(0)
629  NumFrameExtraProbe++;
630  CurrentOffset += StackProbeSize;
631  }
632 
633  // No need to probe the tail, it is smaller than a Page.
634  uint64_t ChunkSize = Offset - CurrentOffset;
635  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
636  .addReg(StackPtr)
637  .addImm(ChunkSize)
639  // No need to adjust Dwarf CFA offset here, the last position of the stack has
640  // been defined
641  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
642 }
643 
644 void X86FrameLowering::emitStackProbeInlineGenericLoop(
647  uint64_t AlignOffset) const {
648  assert(Offset && "null offset");
649 
650  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
651  const bool HasFP = hasFP(MF);
652  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
653  const X86TargetLowering &TLI = *STI.getTargetLowering();
654  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
655  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
656 
657  if (AlignOffset) {
658  if (AlignOffset < StackProbeSize) {
659  // Perform a first smaller allocation followed by a probe.
660  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, AlignOffset);
661  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), StackPtr)
662  .addReg(StackPtr)
663  .addImm(AlignOffset)
665  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
666 
667  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
669  StackPtr, false, 0)
670  .addImm(0)
672  NumFrameExtraProbe++;
673  Offset -= AlignOffset;
674  }
675  }
676 
677  // Synthesize a loop
678  NumFrameLoopProbe++;
679  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
680 
681  MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
682  MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
683 
685  MF.insert(MBBIter, testMBB);
686  MF.insert(MBBIter, tailMBB);
687 
688  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
689  : Is64Bit ? X86::R11D
690  : X86::EAX;
691 
692  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
693  .addReg(StackPtr)
695 
696  // save loop bound
697  {
698  const unsigned BoundOffset = alignDown(Offset, StackProbeSize);
699  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, BoundOffset);
700  BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), FinalStackProbed)
701  .addReg(FinalStackProbed)
702  .addImm(BoundOffset)
704 
705  // while in the loop, use loop-invariant reg for CFI,
706  // instead of the stack pointer, which changes during the loop
707  if (!HasFP && NeedsDwarfCFI) {
708  // x32 uses the same DWARF register numbers as x86-64,
709  // so there isn't a register number for r11d, we must use r11 instead
710  const Register DwarfFinalStackProbed =
712  ? Register(getX86SubSuperRegister(FinalStackProbed, 64))
713  : FinalStackProbed;
714 
715  BuildCFI(MBB, MBBI, DL,
717  nullptr, TRI->getDwarfRegNum(DwarfFinalStackProbed, true)));
718  BuildCFI(MBB, MBBI, DL,
719  MCCFIInstruction::createAdjustCfaOffset(nullptr, BoundOffset));
720  }
721  }
722 
723  // allocate a page
724  {
725  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
726  BuildMI(testMBB, DL, TII.get(SUBOpc), StackPtr)
727  .addReg(StackPtr)
728  .addImm(StackProbeSize)
730  }
731 
732  // touch the page
733  addRegOffset(BuildMI(testMBB, DL, TII.get(MovMIOpc))
735  StackPtr, false, 0)
736  .addImm(0)
738 
739  // cmp with stack pointer bound
740  BuildMI(testMBB, DL, TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
741  .addReg(StackPtr)
742  .addReg(FinalStackProbed)
744 
745  // jump
746  BuildMI(testMBB, DL, TII.get(X86::JCC_1))
747  .addMBB(testMBB)
750  testMBB->addSuccessor(testMBB);
751  testMBB->addSuccessor(tailMBB);
752 
753  // BB management
754  tailMBB->splice(tailMBB->end(), &MBB, MBBI, MBB.end());
756  MBB.addSuccessor(testMBB);
757 
758  // handle tail
759  const unsigned TailOffset = Offset % StackProbeSize;
760  MachineBasicBlock::iterator TailMBBIter = tailMBB->begin();
761  if (TailOffset) {
762  const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, TailOffset);
763  BuildMI(*tailMBB, TailMBBIter, DL, TII.get(Opc), StackPtr)
764  .addReg(StackPtr)
765  .addImm(TailOffset)
767  }
768 
769  // after the loop, switch back to stack pointer for CFI
770  if (!HasFP && NeedsDwarfCFI) {
771  // x32 uses the same DWARF register numbers as x86-64,
772  // so there isn't a register number for esp, we must use rsp instead
773  const Register DwarfStackPtr =
776  : Register(StackPtr);
777 
778  BuildCFI(*tailMBB, TailMBBIter, DL,
780  nullptr, TRI->getDwarfRegNum(DwarfStackPtr, true)));
781  }
782 
783  // Update Live In information
784  recomputeLiveIns(*testMBB);
785  recomputeLiveIns(*tailMBB);
786 }
787 
788 void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
790  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
791  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
792  assert(STI.is64Bit() && "different expansion needed for 32 bit");
793  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
794  const TargetInstrInfo &TII = *STI.getInstrInfo();
795  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
796 
797  // RAX contains the number of bytes of desired stack adjustment.
798  // The handling here assumes this value has already been updated so as to
799  // maintain stack alignment.
800  //
801  // We need to exit with RSP modified by this amount and execute suitable
802  // page touches to notify the OS that we're growing the stack responsibly.
803  // All stack probing must be done without modifying RSP.
804  //
805  // MBB:
806  // SizeReg = RAX;
807  // ZeroReg = 0
808  // CopyReg = RSP
809  // Flags, TestReg = CopyReg - SizeReg
810  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
811  // LimitReg = gs magic thread env access
812  // if FinalReg >= LimitReg goto ContinueMBB
813  // RoundBB:
814  // RoundReg = page address of FinalReg
815  // LoopMBB:
816  // LoopReg = PHI(LimitReg,ProbeReg)
817  // ProbeReg = LoopReg - PageSize
818  // [ProbeReg] = 0
819  // if (ProbeReg > RoundReg) goto LoopMBB
820  // ContinueMBB:
821  // RSP = RSP - RAX
822  // [rest of original MBB]
823 
824  // Set up the new basic blocks
825  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
826  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
827  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
828 
829  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
830  MF.insert(MBBIter, RoundMBB);
831  MF.insert(MBBIter, LoopMBB);
832  MF.insert(MBBIter, ContinueMBB);
833 
834  // Split MBB and move the tail portion down to ContinueMBB.
835  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
836  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
837  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
838 
839  // Some useful constants
840  const int64_t ThreadEnvironmentStackLimit = 0x10;
841  const int64_t PageSize = 0x1000;
842  const int64_t PageMask = ~(PageSize - 1);
843 
844  // Registers we need. For the normal case we use virtual
845  // registers. For the prolog expansion we use RAX, RCX and RDX.
847  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
848  const Register SizeReg = InProlog ? X86::RAX
849  : MRI.createVirtualRegister(RegClass),
850  ZeroReg = InProlog ? X86::RCX
851  : MRI.createVirtualRegister(RegClass),
852  CopyReg = InProlog ? X86::RDX
853  : MRI.createVirtualRegister(RegClass),
854  TestReg = InProlog ? X86::RDX
855  : MRI.createVirtualRegister(RegClass),
856  FinalReg = InProlog ? X86::RDX
857  : MRI.createVirtualRegister(RegClass),
858  RoundedReg = InProlog ? X86::RDX
859  : MRI.createVirtualRegister(RegClass),
860  LimitReg = InProlog ? X86::RCX
861  : MRI.createVirtualRegister(RegClass),
862  JoinReg = InProlog ? X86::RCX
863  : MRI.createVirtualRegister(RegClass),
864  ProbeReg = InProlog ? X86::RCX
865  : MRI.createVirtualRegister(RegClass);
866 
867  // SP-relative offsets where we can save RCX and RDX.
868  int64_t RCXShadowSlot = 0;
869  int64_t RDXShadowSlot = 0;
870 
871  // If inlining in the prolog, save RCX and RDX.
872  if (InProlog) {
873  // Compute the offsets. We need to account for things already
874  // pushed onto the stack at this point: return address, frame
875  // pointer (if used), and callee saves.
877  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
878  const bool HasFP = hasFP(MF);
879 
880  // Check if we need to spill RCX and/or RDX.
881  // Here we assume that no earlier prologue instruction changes RCX and/or
882  // RDX, so checking the block live-ins is enough.
883  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
884  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
885  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
886  // Assign the initial slot to both registers, then change RDX's slot if both
887  // need to be spilled.
888  if (IsRCXLiveIn)
889  RCXShadowSlot = InitSlot;
890  if (IsRDXLiveIn)
891  RDXShadowSlot = InitSlot;
892  if (IsRDXLiveIn && IsRCXLiveIn)
893  RDXShadowSlot += 8;
894  // Emit the saves if needed.
895  if (IsRCXLiveIn)
896  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
897  RCXShadowSlot)
898  .addReg(X86::RCX);
899  if (IsRDXLiveIn)
900  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
901  RDXShadowSlot)
902  .addReg(X86::RDX);
903  } else {
904  // Not in the prolog. Copy RAX to a virtual reg.
905  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
906  }
907 
908  // Add code to MBB to check for overflow and set the new target stack pointer
909  // to zero if so.
910  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
911  .addReg(ZeroReg, RegState::Undef)
912  .addReg(ZeroReg, RegState::Undef);
913  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
914  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
915  .addReg(CopyReg)
916  .addReg(SizeReg);
917  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
918  .addReg(TestReg)
919  .addReg(ZeroReg)
921 
922  // FinalReg now holds final stack pointer value, or zero if
923  // allocation would overflow. Compare against the current stack
924  // limit from the thread environment block. Note this limit is the
925  // lowest touched page on the stack, not the point at which the OS
926  // will cause an overflow exception, so this is just an optimization
927  // to avoid unnecessarily touching pages that are below the current
928  // SP but already committed to the stack by the OS.
929  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
930  .addReg(0)
931  .addImm(1)
932  .addReg(0)
933  .addImm(ThreadEnvironmentStackLimit)
934  .addReg(X86::GS);
935  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
936  // Jump if the desired stack pointer is at or above the stack limit.
937  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
938 
939  // Add code to roundMBB to round the final stack pointer to a page boundary.
940  RoundMBB->addLiveIn(FinalReg);
941  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
942  .addReg(FinalReg)
943  .addImm(PageMask);
944  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
945 
946  // LimitReg now holds the current stack limit, RoundedReg page-rounded
947  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
948  // and probe until we reach RoundedReg.
949  if (!InProlog) {
950  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
951  .addReg(LimitReg)
952  .addMBB(RoundMBB)
953  .addReg(ProbeReg)
954  .addMBB(LoopMBB);
955  }
956 
957  LoopMBB->addLiveIn(JoinReg);
958  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
959  false, -PageSize);
960 
961  // Probe by storing a byte onto the stack.
962  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
963  .addReg(ProbeReg)
964  .addImm(1)
965  .addReg(0)
966  .addImm(0)
967  .addReg(0)
968  .addImm(0);
969 
970  LoopMBB->addLiveIn(RoundedReg);
971  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
972  .addReg(RoundedReg)
973  .addReg(ProbeReg);
974  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
975 
976  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
977 
978  // If in prolog, restore RDX and RCX.
979  if (InProlog) {
980  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
981  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
982  TII.get(X86::MOV64rm), X86::RCX),
983  X86::RSP, false, RCXShadowSlot);
984  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
985  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
986  TII.get(X86::MOV64rm), X86::RDX),
987  X86::RSP, false, RDXShadowSlot);
988  }
989 
990  // Now that the probing is done, add code to continueMBB to update
991  // the stack pointer for real.
992  ContinueMBB->addLiveIn(SizeReg);
993  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
994  .addReg(X86::RSP)
995  .addReg(SizeReg);
996 
997  // Add the control flow edges we need.
998  MBB.addSuccessor(ContinueMBB);
999  MBB.addSuccessor(RoundMBB);
1000  RoundMBB->addSuccessor(LoopMBB);
1001  LoopMBB->addSuccessor(ContinueMBB);
1002  LoopMBB->addSuccessor(LoopMBB);
1003 
1004  // Mark all the instructions added to the prolog as frame setup.
1005  if (InProlog) {
1006  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
1007  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
1008  }
1009  for (MachineInstr &MI : *RoundMBB) {
1010  MI.setFlag(MachineInstr::FrameSetup);
1011  }
1012  for (MachineInstr &MI : *LoopMBB) {
1013  MI.setFlag(MachineInstr::FrameSetup);
1014  }
1015  for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
1016  CMBBI != ContinueMBBI; ++CMBBI) {
1017  CMBBI->setFlag(MachineInstr::FrameSetup);
1018  }
1019  }
1020 }
1021 
1022 void X86FrameLowering::emitStackProbeCall(
1024  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog,
1026  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
1027 
1028  // FIXME: Add indirect thunk support and remove this.
1029  if (Is64Bit && IsLargeCodeModel && STI.useIndirectThunkCalls())
1030  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
1031  "code model and indirect thunks not yet implemented.");
1032 
1033  unsigned CallOp;
1034  if (Is64Bit)
1035  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
1036  else
1037  CallOp = X86::CALLpcrel32;
1038 
1040 
1042  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
1043 
1044  // All current stack probes take AX and SP as input, clobber flags, and
1045  // preserve all registers. x86_64 probes leave RSP unmodified.
1046  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1047  // For the large code model, we have to call through a register. Use R11,
1048  // as it is scratch in all supported calling conventions.
1049  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
1051  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
1052  } else {
1053  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
1055  }
1056 
1057  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
1058  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
1059  CI.addReg(AX, RegState::Implicit)
1063  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1064 
1065  MachineInstr *ModInst = CI;
1066  if (STI.isTargetWin64() || !STI.isOSWindows()) {
1067  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
1068  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
1069  // themselves. They also does not clobber %rax so we can reuse it when
1070  // adjusting %rsp.
1071  // All other platforms do not specify a particular ABI for the stack probe
1072  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
1073  ModInst =
1075  .addReg(SP)
1076  .addReg(AX);
1077  }
1078 
1079  // DebugInfo variable locations -- if there's an instruction number for the
1080  // allocation (i.e., DYN_ALLOC_*), substitute it for the instruction that
1081  // modifies SP.
1082  if (InstrNum) {
1083  if (STI.isTargetWin64() || !STI.isOSWindows()) {
1084  // Label destination operand of the subtract.
1085  MF.makeDebugValueSubstitution(*InstrNum,
1086  {ModInst->getDebugInstrNum(), 0});
1087  } else {
1088  // Label the call. The operand number is the penultimate operand, zero
1089  // based.
1090  unsigned SPDefOperand = ModInst->getNumOperands() - 2;
1092  *InstrNum, {ModInst->getDebugInstrNum(), SPDefOperand});
1093  }
1094  }
1095 
1096  if (InProlog) {
1097  // Apply the frame setup flag to all inserted instrs.
1098  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
1099  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
1100  }
1101 }
1102 
1103 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
1104  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
1105  // and might require smaller successive adjustments.
1106  const uint64_t Win64MaxSEHOffset = 128;
1107  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
1108  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
1109  return SEHFrameOffset & -16;
1110 }
1111 
1112 // If we're forcing a stack realignment we can't rely on just the frame
1113 // info, we need to know the ABI stack alignment as well in case we
1114 // have a call out. Otherwise just make sure we have some alignment - we'll
1115 // go with the minimum SlotSize.
1116 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
1117  const MachineFrameInfo &MFI = MF.getFrameInfo();
1118  Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
1120  if (MF.getFunction().hasFnAttribute("stackrealign")) {
1121  if (MFI.hasCalls())
1122  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1123  else if (MaxAlign < SlotSize)
1124  MaxAlign = Align(SlotSize);
1125  }
1126  return MaxAlign.value();
1127 }
1128 
1129 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
1131  const DebugLoc &DL, unsigned Reg,
1132  uint64_t MaxAlign) const {
1133  uint64_t Val = -MaxAlign;
1134  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
1135 
1136  MachineFunction &MF = *MBB.getParent();
1137  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1138  const X86TargetLowering &TLI = *STI.getTargetLowering();
1139  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
1140  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
1141 
1142  // We want to make sure that (in worst case) less than StackProbeSize bytes
1143  // are not probed after the AND. This assumption is used in
1144  // emitStackProbeInlineGeneric.
1145  if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
1146  {
1147  NumFrameLoopProbe++;
1148  MachineBasicBlock *entryMBB =
1150  MachineBasicBlock *headMBB =
1152  MachineBasicBlock *bodyMBB =
1154  MachineBasicBlock *footMBB =
1156 
1158  MF.insert(MBBIter, entryMBB);
1159  MF.insert(MBBIter, headMBB);
1160  MF.insert(MBBIter, bodyMBB);
1161  MF.insert(MBBIter, footMBB);
1162  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
1163  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
1164  : Is64Bit ? X86::R11D
1165  : X86::EAX;
1166 
1167  // Setup entry block
1168  {
1169 
1170  entryMBB->splice(entryMBB->end(), &MBB, MBB.begin(), MBBI);
1171  BuildMI(entryMBB, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
1172  .addReg(StackPtr)
1174  MachineInstr *MI =
1175  BuildMI(entryMBB, DL, TII.get(AndOp), FinalStackProbed)
1176  .addReg(FinalStackProbed)
1177  .addImm(Val)
1179 
1180  // The EFLAGS implicit def is dead.
1181  MI->getOperand(3).setIsDead();
1182 
1183  BuildMI(entryMBB, DL,
1184  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1185  .addReg(FinalStackProbed)
1186  .addReg(StackPtr)
1188  BuildMI(entryMBB, DL, TII.get(X86::JCC_1))
1189  .addMBB(&MBB)
1192  entryMBB->addSuccessor(headMBB);
1193  entryMBB->addSuccessor(&MBB);
1194  }
1195 
1196  // Loop entry block
1197 
1198  {
1199  const unsigned SUBOpc =
1200  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1201  BuildMI(headMBB, DL, TII.get(SUBOpc), StackPtr)
1202  .addReg(StackPtr)
1203  .addImm(StackProbeSize)
1205 
1206  BuildMI(headMBB, DL,
1207  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1208  .addReg(FinalStackProbed)
1209  .addReg(StackPtr)
1211 
1212  // jump
1213  BuildMI(headMBB, DL, TII.get(X86::JCC_1))
1214  .addMBB(footMBB)
1217 
1218  headMBB->addSuccessor(bodyMBB);
1219  headMBB->addSuccessor(footMBB);
1220  }
1221 
1222  // setup loop body
1223  {
1224  addRegOffset(BuildMI(bodyMBB, DL, TII.get(MovMIOpc))
1226  StackPtr, false, 0)
1227  .addImm(0)
1229 
1230  const unsigned SUBOpc =
1231  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1232  BuildMI(bodyMBB, DL, TII.get(SUBOpc), StackPtr)
1233  .addReg(StackPtr)
1234  .addImm(StackProbeSize)
1236 
1237  // cmp with stack pointer bound
1238  BuildMI(bodyMBB, DL,
1239  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1240  .addReg(FinalStackProbed)
1241  .addReg(StackPtr)
1243 
1244  // jump
1245  BuildMI(bodyMBB, DL, TII.get(X86::JCC_1))
1246  .addMBB(bodyMBB)
1249  bodyMBB->addSuccessor(bodyMBB);
1250  bodyMBB->addSuccessor(footMBB);
1251  }
1252 
1253  // setup loop footer
1254  {
1255  BuildMI(footMBB, DL, TII.get(TargetOpcode::COPY), StackPtr)
1256  .addReg(FinalStackProbed)
1258  addRegOffset(BuildMI(footMBB, DL, TII.get(MovMIOpc))
1260  StackPtr, false, 0)
1261  .addImm(0)
1263  footMBB->addSuccessor(&MBB);
1264  }
1265 
1266  recomputeLiveIns(*headMBB);
1267  recomputeLiveIns(*bodyMBB);
1268  recomputeLiveIns(*footMBB);
1270  }
1271  } else {
1272  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1273  .addReg(Reg)
1274  .addImm(Val)
1276 
1277  // The EFLAGS implicit def is dead.
1278  MI->getOperand(3).setIsDead();
1279  }
1280 }
1281 
1283  // x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
1284  // clobbered by any interrupt handler.
1285  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1286  "MF used frame lowering for wrong subtarget");
1287  const Function &Fn = MF.getFunction();
1288  const bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
1289  return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone);
1290 }
1291 
1292 bool X86FrameLowering::isWin64Prologue(const MachineFunction &MF) const {
1293  return MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1294 }
1295 
1296 bool X86FrameLowering::needsDwarfCFI(const MachineFunction &MF) const {
1297  return !isWin64Prologue(MF) && MF.needsFrameMoves();
1298 }
1299 
1300 /// emitPrologue - Push callee-saved registers onto the stack, which
1301 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
1302 /// space for local variables. Also emit labels used by the exception handler to
1303 /// generate the exception handling frames.
1304 
1305 /*
1306  Here's a gist of what gets emitted:
1307 
1308  ; Establish frame pointer, if needed
1309  [if needs FP]
1310  push %rbp
1311  .cfi_def_cfa_offset 16
1312  .cfi_offset %rbp, -16
1313  .seh_pushreg %rpb
1314  mov %rsp, %rbp
1315  .cfi_def_cfa_register %rbp
1316 
1317  ; Spill general-purpose registers
1318  [for all callee-saved GPRs]
1319  pushq %<reg>
1320  [if not needs FP]
1321  .cfi_def_cfa_offset (offset from RETADDR)
1322  .seh_pushreg %<reg>
1323 
1324  ; If the required stack alignment > default stack alignment
1325  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
1326  ; of unknown size in the stack frame.
1327  [if stack needs re-alignment]
1328  and $MASK, %rsp
1329 
1330  ; Allocate space for locals
1331  [if target is Windows and allocated space > 4096 bytes]
1332  ; Windows needs special care for allocations larger
1333  ; than one page.
1334  mov $NNN, %rax
1335  call ___chkstk_ms/___chkstk
1336  sub %rax, %rsp
1337  [else]
1338  sub $NNN, %rsp
1339 
1340  [if needs FP]
1341  .seh_stackalloc (size of XMM spill slots)
1342  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
1343  [else]
1344  .seh_stackalloc NNN
1345 
1346  ; Spill XMMs
1347  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
1348  ; they may get spilled on any platform, if the current function
1349  ; calls @llvm.eh.unwind.init
1350  [if needs FP]
1351  [for all callee-saved XMM registers]
1352  movaps %<xmm reg>, -MMM(%rbp)
1353  [for all callee-saved XMM registers]
1354  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
1355  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
1356  [else]
1357  [for all callee-saved XMM registers]
1358  movaps %<xmm reg>, KKK(%rsp)
1359  [for all callee-saved XMM registers]
1360  .seh_savexmm %<xmm reg>, KKK
1361 
1362  .seh_endprologue
1363 
1364  [if needs base pointer]
1365  mov %rsp, %rbx
1366  [if needs to restore base pointer]
1367  mov %rsp, -MMM(%rbp)
1368 
1369  ; Emit CFI info
1370  [if needs FP]
1371  [for all callee-saved registers]
1372  .cfi_offset %<reg>, (offset from %rbp)
1373  [else]
1374  .cfi_def_cfa_offset (offset from RETADDR)
1375  [for all callee-saved registers]
1376  .cfi_offset %<reg>, (offset from %rsp)
1377 
1378  Notes:
1379  - .seh directives are emitted only for Windows 64 ABI
1380  - .cv_fpo directives are emitted on win32 when emitting CodeView
1381  - .cfi directives are emitted for all other ABIs
1382  - for 32-bit code, substitute %e?? registers for %r??
1383 */
1384 
1386  MachineBasicBlock &MBB) const {
1387  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1388  "MF used frame lowering for wrong subtarget");
1390  MachineFrameInfo &MFI = MF.getFrameInfo();
1391  const Function &Fn = MF.getFunction();
1392  MachineModuleInfo &MMI = MF.getMMI();
1394  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
1395  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
1396  bool IsFunclet = MBB.isEHFuncletEntry();
1397  EHPersonality Personality = EHPersonality::Unknown;
1398  if (Fn.hasPersonalityFn())
1399  Personality = classifyEHPersonality(Fn.getPersonalityFn());
1400  bool FnHasClrFunclet =
1401  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
1402  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
1403  bool HasFP = hasFP(MF);
1404  bool IsWin64Prologue = isWin64Prologue(MF);
1405  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
1406  // FIXME: Emit FPO data for EH funclets.
1407  bool NeedsWinFPO =
1408  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
1409  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
1410  bool NeedsDwarfCFI = needsDwarfCFI(MF);
1411  Register FramePtr = TRI->getFrameRegister(MF);
1412  const Register MachineFramePtr =
1414  ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
1415  Register BasePtr = TRI->getBaseRegister();
1416  bool HasWinCFI = false;
1417 
1418  // Debug location must be unknown since the first debug location is used
1419  // to determine the end of the prologue.
1420  DebugLoc DL;
1421 
1422  // Space reserved for stack-based arguments when making a (ABI-guaranteed)
1423  // tail call.
1424  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
1425  if (TailCallArgReserveSize && IsWin64Prologue)
1426  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1427 
1428  const bool EmitStackProbeCall =
1430  unsigned StackProbeSize = STI.getTargetLowering()->getStackProbeSize(MF);
1431 
1432  if (HasFP && X86FI->hasSwiftAsyncContext()) {
1433  switch (MF.getTarget().Options.SwiftAsyncFramePointer) {
1436  // The special symbol below is absolute and has a *value* suitable to be
1437  // combined with the frame pointer directly.
1438  BuildMI(MBB, MBBI, DL, TII.get(X86::OR64rm), MachineFramePtr)
1439  .addUse(MachineFramePtr)
1440  .addUse(X86::RIP)
1441  .addImm(1)
1442  .addUse(X86::NoRegister)
1443  .addExternalSymbol("swift_async_extendedFramePointerFlags",
1445  .addUse(X86::NoRegister);
1446  break;
1447  }
1449 
1451  BuildMI(MBB, MBBI, DL, TII.get(X86::BTS64ri8), MachineFramePtr)
1452  .addUse(MachineFramePtr)
1453  .addImm(60)
1455  break;
1456 
1458  break;
1459  }
1460  }
1461 
1462  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1463  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1464  // stack alignment.
1465  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1466  Fn.arg_size() == 2) {
1467  StackSize += 8;
1468  MFI.setStackSize(StackSize);
1469  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1470  }
1471 
1472  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1473  // function, and use up to 128 bytes of stack space, don't have a frame
1474  // pointer, calls, or dynamic alloca then we do not need to adjust the
1475  // stack pointer (we fit in the Red Zone). We also check that we don't
1476  // push and pop from the stack.
1477  if (has128ByteRedZone(MF) && !TRI->hasStackRealignment(MF) &&
1478  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1479  !MFI.adjustsStack() && // No calls.
1480  !EmitStackProbeCall && // No stack probes.
1481  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1482  !MF.shouldSplitStack()) { // Regular stack
1483  uint64_t MinSize =
1484  X86FI->getCalleeSavedFrameSize() - X86FI->getTCReturnAddrDelta();
1485  if (HasFP) MinSize += SlotSize;
1486  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1487  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1488  MFI.setStackSize(StackSize);
1489  }
1490 
1491  // Insert stack pointer adjustment for later moving of return addr. Only
1492  // applies to tail call optimized functions where the callee argument stack
1493  // size is bigger than the callers.
1494  if (TailCallArgReserveSize != 0) {
1495  BuildStackAdjustment(MBB, MBBI, DL, -(int)TailCallArgReserveSize,
1496  /*InEpilogue=*/false)
1498  }
1499 
1500  // Mapping for machine moves:
1501  //
1502  // DST: VirtualFP AND
1503  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1504  // ELSE => DW_CFA_def_cfa
1505  //
1506  // SRC: VirtualFP AND
1507  // DST: Register => DW_CFA_def_cfa_register
1508  //
1509  // ELSE
1510  // OFFSET < 0 => DW_CFA_offset_extended_sf
1511  // REG < 64 => DW_CFA_offset + Reg
1512  // ELSE => DW_CFA_offset_extended
1513 
1514  uint64_t NumBytes = 0;
1515  int stackGrowth = -SlotSize;
1516 
1517  // Find the funclet establisher parameter
1518  Register Establisher = X86::NoRegister;
1519  if (IsClrFunclet)
1520  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1521  else if (IsFunclet)
1522  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1523 
1524  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1525  // Immediately spill establisher into the home slot.
1526  // The runtime cares about this.
1527  // MOV64mr %rdx, 16(%rsp)
1528  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1529  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1530  .addReg(Establisher)
1532  MBB.addLiveIn(Establisher);
1533  }
1534 
1535  if (HasFP) {
1536  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1537 
1538  // Calculate required stack adjustment.
1539  uint64_t FrameSize = StackSize - SlotSize;
1540  // If required, include space for extra hidden slot for stashing base pointer.
1541  if (X86FI->getRestoreBasePointer())
1542  FrameSize += SlotSize;
1543 
1544  NumBytes = FrameSize -
1545  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1546 
1547  // Callee-saved registers are pushed on stack before the stack is realigned.
1548  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
1549  NumBytes = alignTo(NumBytes, MaxAlign);
1550 
1551  // Save EBP/RBP into the appropriate stack slot.
1552  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1553  .addReg(MachineFramePtr, RegState::Kill)
1555 
1556  if (NeedsDwarfCFI) {
1557  // Mark the place where EBP/RBP was saved.
1558  // Define the current CFA rule to use the provided offset.
1559  assert(StackSize);
1560  BuildCFI(MBB, MBBI, DL,
1561  MCCFIInstruction::cfiDefCfaOffset(nullptr, -2 * stackGrowth));
1562 
1563  // Change the rule for the FramePtr to be an "offset" rule.
1564  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1566  nullptr, DwarfFramePtr, 2 * stackGrowth));
1567  }
1568 
1569  if (NeedsWinCFI) {
1570  HasWinCFI = true;
1571  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1572  .addImm(FramePtr)
1574  }
1575 
1576  if (!IsFunclet) {
1577  if (X86FI->hasSwiftAsyncContext()) {
1578  const auto &Attrs = MF.getFunction().getAttributes();
1579 
1580  // Before we update the live frame pointer we have to ensure there's a
1581  // valid (or null) asynchronous context in its slot just before FP in
1582  // the frame record, so store it now.
1583  if (Attrs.hasAttrSomewhere(Attribute::SwiftAsync)) {
1584  // We have an initial context in r14, store it just before the frame
1585  // pointer.
1586  MBB.addLiveIn(X86::R14);
1587  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1588  .addReg(X86::R14)
1590  } else {
1591  // No initial context, store null so that there's no pointer that
1592  // could be misused.
1593  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64i8))
1594  .addImm(0)
1596  }
1597 
1598  if (NeedsWinCFI) {
1599  HasWinCFI = true;
1600  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1601  .addImm(X86::R14)
1603  }
1604 
1605  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr)
1606  .addUse(X86::RSP)
1607  .addImm(1)
1608  .addUse(X86::NoRegister)
1609  .addImm(8)
1610  .addUse(X86::NoRegister)
1612  BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri8), X86::RSP)
1613  .addUse(X86::RSP)
1614  .addImm(8)
1616  }
1617 
1618  if (!IsWin64Prologue && !IsFunclet) {
1619  // Update EBP with the new base value.
1620  if (!X86FI->hasSwiftAsyncContext())
1621  BuildMI(MBB, MBBI, DL,
1622  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1623  FramePtr)
1624  .addReg(StackPtr)
1626 
1627  if (NeedsDwarfCFI) {
1628  // Mark effective beginning of when frame pointer becomes valid.
1629  // Define the current CFA to use the EBP/RBP register.
1630  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1631  BuildCFI(
1632  MBB, MBBI, DL,
1633  MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
1634  }
1635 
1636  if (NeedsWinFPO) {
1637  // .cv_fpo_setframe $FramePtr
1638  HasWinCFI = true;
1639  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1640  .addImm(FramePtr)
1641  .addImm(0)
1643  }
1644  }
1645  }
1646  } else {
1647  assert(!IsFunclet && "funclets without FPs not yet implemented");
1648  NumBytes = StackSize -
1649  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1650  }
1651 
1652  // Update the offset adjustment, which is mainly used by codeview to translate
1653  // from ESP to VFRAME relative local variable offsets.
1654  if (!IsFunclet) {
1655  if (HasFP && TRI->hasStackRealignment(MF))
1656  MFI.setOffsetAdjustment(-NumBytes);
1657  else
1658  MFI.setOffsetAdjustment(-StackSize);
1659  }
1660 
1661  // For EH funclets, only allocate enough space for outgoing calls. Save the
1662  // NumBytes value that we would've used for the parent frame.
1663  unsigned ParentFrameNumBytes = NumBytes;
1664  if (IsFunclet)
1665  NumBytes = getWinEHFuncletFrameSize(MF);
1666 
1667  // Skip the callee-saved push instructions.
1668  bool PushedRegs = false;
1669  int StackOffset = 2 * stackGrowth;
1670 
1671  while (MBBI != MBB.end() &&
1672  MBBI->getFlag(MachineInstr::FrameSetup) &&
1673  (MBBI->getOpcode() == X86::PUSH32r ||
1674  MBBI->getOpcode() == X86::PUSH64r)) {
1675  PushedRegs = true;
1676  Register Reg = MBBI->getOperand(0).getReg();
1677  ++MBBI;
1678 
1679  if (!HasFP && NeedsDwarfCFI) {
1680  // Mark callee-saved push instruction.
1681  // Define the current CFA rule to use the provided offset.
1682  assert(StackSize);
1683  BuildCFI(MBB, MBBI, DL,
1685  StackOffset += stackGrowth;
1686  }
1687 
1688  if (NeedsWinCFI) {
1689  HasWinCFI = true;
1690  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1691  .addImm(Reg)
1693  }
1694  }
1695 
1696  // Realign stack after we pushed callee-saved registers (so that we'll be
1697  // able to calculate their offsets from the frame pointer).
1698  // Don't do this for Win64, it needs to realign the stack after the prologue.
1699  if (!IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF)) {
1700  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1701  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1702 
1703  if (NeedsWinCFI) {
1704  HasWinCFI = true;
1705  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1706  .addImm(MaxAlign)
1708  }
1709  }
1710 
1711  // If there is an SUB32ri of ESP immediately before this instruction, merge
1712  // the two. This can be the case when tail call elimination is enabled and
1713  // the callee has more arguments then the caller.
1714  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1715 
1716  // Adjust stack pointer: ESP -= numbytes.
1717 
1718  // Windows and cygwin/mingw require a prologue helper routine when allocating
1719  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1720  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1721  // stack and adjust the stack pointer in one go. The 64-bit version of
1722  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1723  // responsible for adjusting the stack pointer. Touching the stack at 4K
1724  // increments is necessary to ensure that the guard pages used by the OS
1725  // virtual memory manager are allocated in correct sequence.
1726  uint64_t AlignedNumBytes = NumBytes;
1727  if (IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF))
1728  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1729  if (AlignedNumBytes >= StackProbeSize && EmitStackProbeCall) {
1730  assert(!X86FI->getUsesRedZone() &&
1731  "The Red Zone is not accounted for in stack probes");
1732 
1733  // Check whether EAX is livein for this block.
1734  bool isEAXAlive = isEAXLiveIn(MBB);
1735 
1736  if (isEAXAlive) {
1737  if (Is64Bit) {
1738  // Save RAX
1739  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1740  .addReg(X86::RAX, RegState::Kill)
1742  } else {
1743  // Save EAX
1744  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1747  }
1748  }
1749 
1750  if (Is64Bit) {
1751  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1752  // Function prologue is responsible for adjusting the stack pointer.
1753  int64_t Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1754  BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Alloc)), X86::RAX)
1755  .addImm(Alloc)
1757  } else {
1758  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1759  // We'll also use 4 already allocated bytes for EAX.
1760  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1761  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1763  }
1764 
1765  // Call __chkstk, __chkstk_ms, or __alloca.
1766  emitStackProbe(MF, MBB, MBBI, DL, true);
1767 
1768  if (isEAXAlive) {
1769  // Restore RAX/EAX
1770  MachineInstr *MI;
1771  if (Is64Bit)
1772  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1773  StackPtr, false, NumBytes - 8);
1774  else
1775  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1776  StackPtr, false, NumBytes - 4);
1777  MI->setFlag(MachineInstr::FrameSetup);
1778  MBB.insert(MBBI, MI);
1779  }
1780  } else if (NumBytes) {
1781  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1782  }
1783 
1784  if (NeedsWinCFI && NumBytes) {
1785  HasWinCFI = true;
1786  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1787  .addImm(NumBytes)
1789  }
1790 
1791  int SEHFrameOffset = 0;
1792  unsigned SPOrEstablisher;
1793  if (IsFunclet) {
1794  if (IsClrFunclet) {
1795  // The establisher parameter passed to a CLR funclet is actually a pointer
1796  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1797  // to find the root function establisher frame by loading the PSPSym from
1798  // the intermediate frame.
1799  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1800  MachinePointerInfo NoInfo;
1801  MBB.addLiveIn(Establisher);
1802  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1803  Establisher, false, PSPSlotOffset)
1806  ;
1807  // Save the root establisher back into the current funclet's (mostly
1808  // empty) frame, in case a sub-funclet or the GC needs it.
1809  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1810  false, PSPSlotOffset)
1811  .addReg(Establisher)
1813  NoInfo,
1815  SlotSize, Align(SlotSize)));
1816  }
1817  SPOrEstablisher = Establisher;
1818  } else {
1819  SPOrEstablisher = StackPtr;
1820  }
1821 
1822  if (IsWin64Prologue && HasFP) {
1823  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1824  // this calculation on the incoming establisher, which holds the value of
1825  // RSP from the parent frame at the end of the prologue.
1826  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1827  if (SEHFrameOffset)
1828  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1829  SPOrEstablisher, false, SEHFrameOffset);
1830  else
1831  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1832  .addReg(SPOrEstablisher);
1833 
1834  // If this is not a funclet, emit the CFI describing our frame pointer.
1835  if (NeedsWinCFI && !IsFunclet) {
1836  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1837  HasWinCFI = true;
1838  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1839  .addImm(FramePtr)
1840  .addImm(SEHFrameOffset)
1842  if (isAsynchronousEHPersonality(Personality))
1843  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1844  }
1845  } else if (IsFunclet && STI.is32Bit()) {
1846  // Reset EBP / ESI to something good for funclets.
1848  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1849  // into the registration node so that the runtime will restore it for us.
1850  if (!MBB.isCleanupFuncletEntry()) {
1851  assert(Personality == EHPersonality::MSVC_CXX);
1852  Register FrameReg;
1853  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1854  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg).getFixed();
1855  // ESP is the first field, so no extra displacement is needed.
1856  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1857  false, EHRegOffset)
1858  .addReg(X86::ESP);
1859  }
1860  }
1861 
1862  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1863  const MachineInstr &FrameInstr = *MBBI;
1864  ++MBBI;
1865 
1866  if (NeedsWinCFI) {
1867  int FI;
1868  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1869  if (X86::FR64RegClass.contains(Reg)) {
1870  int Offset;
1871  Register IgnoredFrameReg;
1872  if (IsWin64Prologue && IsFunclet)
1873  Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg);
1874  else
1875  Offset =
1876  getFrameIndexReference(MF, FI, IgnoredFrameReg).getFixed() +
1877  SEHFrameOffset;
1878 
1879  HasWinCFI = true;
1880  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1881  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1882  .addImm(Reg)
1883  .addImm(Offset)
1885  }
1886  }
1887  }
1888  }
1889 
1890  if (NeedsWinCFI && HasWinCFI)
1891  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1893 
1894  if (FnHasClrFunclet && !IsFunclet) {
1895  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1896  // immediately after the prolog) into the PSPSlot so that funclets
1897  // and the GC can recover it.
1898  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1899  auto PSPInfo = MachinePointerInfo::getFixedStack(
1900  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1901  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1902  PSPSlotOffset)
1903  .addReg(StackPtr)
1906  SlotSize, Align(SlotSize)));
1907  }
1908 
1909  // Realign stack after we spilled callee-saved registers (so that we'll be
1910  // able to calculate their offsets from the frame pointer).
1911  // Win64 requires aligning the stack after the prologue.
1912  if (IsWin64Prologue && TRI->hasStackRealignment(MF)) {
1913  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1914  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1915  }
1916 
1917  // We already dealt with stack realignment and funclets above.
1918  if (IsFunclet && STI.is32Bit())
1919  return;
1920 
1921  // If we need a base pointer, set it up here. It's whatever the value
1922  // of the stack pointer is at this point. Any variable size objects
1923  // will be allocated after this, so we can still use the base pointer
1924  // to reference locals.
1925  if (TRI->hasBasePointer(MF)) {
1926  // Update the base pointer with the current stack pointer.
1927  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1928  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1929  .addReg(SPOrEstablisher)
1931  if (X86FI->getRestoreBasePointer()) {
1932  // Stash value of base pointer. Saving RSP instead of EBP shortens
1933  // dependence chain. Used by SjLj EH.
1934  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1935  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1936  FramePtr, true, X86FI->getRestoreBasePointerOffset())
1937  .addReg(SPOrEstablisher)
1939  }
1940 
1941  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1942  // Stash the value of the frame pointer relative to the base pointer for
1943  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1944  // it recovers the frame pointer from the base pointer rather than the
1945  // other way around.
1946  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1947  Register UsedReg;
1948  int Offset =
1949  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
1950  .getFixed();
1951  assert(UsedReg == BasePtr);
1952  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1953  .addReg(FramePtr)
1955  }
1956  }
1957 
1958  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1959  // Mark end of stack pointer adjustment.
1960  if (!HasFP && NumBytes) {
1961  // Define the current CFA rule to use the provided offset.
1962  assert(StackSize);
1963  BuildCFI(
1964  MBB, MBBI, DL,
1965  MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize - stackGrowth));
1966  }
1967 
1968  // Emit DWARF info specifying the offsets of the callee-saved registers.
1970  }
1971 
1972  // X86 Interrupt handling function cannot assume anything about the direction
1973  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
1974  // in each prologue of interrupt handler function.
1975  //
1976  // FIXME: Create "cld" instruction only in these cases:
1977  // 1. The interrupt handling function uses any of the "rep" instructions.
1978  // 2. Interrupt handling function calls another function.
1979  //
1981  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1983 
1984  // At this point we know if the function has WinCFI or not.
1985  MF.setHasWinCFI(HasWinCFI);
1986 }
1987 
1989  const MachineFunction &MF) const {
1990  // We can't use LEA instructions for adjusting the stack pointer if we don't
1991  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
1992  // to deallocate the stack.
1993  // This means that we can use LEA for SP in two situations:
1994  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1995  // 2. We *have* a frame pointer which means we are permitted to use LEA.
1996  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1997 }
1998 
2000  switch (MI.getOpcode()) {
2001  case X86::CATCHRET:
2002  case X86::CLEANUPRET:
2003  return true;
2004  default:
2005  return false;
2006  }
2007  llvm_unreachable("impossible");
2008 }
2009 
2010 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
2011 // stack. It holds a pointer to the bottom of the root function frame. The
2012 // establisher frame pointer passed to a nested funclet may point to the
2013 // (mostly empty) frame of its parent funclet, but it will need to find
2014 // the frame of the root function to access locals. To facilitate this,
2015 // every funclet copies the pointer to the bottom of the root function
2016 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
2017 // same offset for the PSPSym in the root function frame that's used in the
2018 // funclets' frames allows each funclet to dynamically accept any ancestor
2019 // frame as its establisher argument (the runtime doesn't guarantee the
2020 // immediate parent for some reason lost to history), and also allows the GC,
2021 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
2022 // frame with only a single offset reported for the entire method.
2023 unsigned
2024 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
2025  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
2026  Register SPReg;
2027  int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg,
2028  /*IgnoreSPUpdates*/ true)
2029  .getFixed();
2030  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
2031  return static_cast<unsigned>(Offset);
2032 }
2033 
2034 unsigned
2035 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
2037  // This is the size of the pushed CSRs.
2038  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2039  // This is the size of callee saved XMMs.
2040  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2041  unsigned XMMSize = WinEHXMMSlotInfo.size() *
2042  TRI->getSpillSize(X86::VR128RegClass);
2043  // This is the amount of stack a funclet needs to allocate.
2044  unsigned UsedSize;
2045  EHPersonality Personality =
2047  if (Personality == EHPersonality::CoreCLR) {
2048  // CLR funclets need to hold enough space to include the PSPSym, at the
2049  // same offset from the stack pointer (immediately after the prolog) as it
2050  // resides at in the main function.
2051  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
2052  } else {
2053  // Other funclets just need enough stack for outgoing call arguments.
2054  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
2055  }
2056  // RBP is not included in the callee saved register block. After pushing RBP,
2057  // everything is 16 byte aligned. Everything we allocate before an outgoing
2058  // call must also be 16 byte aligned.
2059  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlign());
2060  // Subtract out the size of the callee saved registers. This is how much stack
2061  // each funclet will allocate.
2062  return FrameSizeMinusRBP + XMMSize - CSSize;
2063 }
2064 
2065 static bool isTailCallOpcode(unsigned Opc) {
2066  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
2067  Opc == X86::TCRETURNmi ||
2068  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
2069  Opc == X86::TCRETURNmi64;
2070 }
2071 
2073  MachineBasicBlock &MBB) const {
2074  const MachineFrameInfo &MFI = MF.getFrameInfo();
2078  DebugLoc DL;
2079  if (MBBI != MBB.end())
2080  DL = MBBI->getDebugLoc();
2081  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
2082  const bool Is64BitILP32 = STI.isTarget64BitILP32();
2083  Register FramePtr = TRI->getFrameRegister(MF);
2084  Register MachineFramePtr =
2085  Is64BitILP32 ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
2086 
2087  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2088  bool NeedsWin64CFI =
2089  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
2090  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
2091 
2092  // Get the number of bytes to allocate from the FrameInfo.
2093  uint64_t StackSize = MFI.getStackSize();
2094  uint64_t MaxAlign = calculateMaxStackAlign(MF);
2095  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2096  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
2097  bool HasFP = hasFP(MF);
2098  uint64_t NumBytes = 0;
2099 
2100  bool NeedsDwarfCFI = (!MF.getTarget().getTargetTriple().isOSDarwin() &&
2101  !MF.getTarget().getTargetTriple().isOSWindows()) &&
2102  MF.needsFrameMoves();
2103 
2104  if (IsFunclet) {
2105  assert(HasFP && "EH funclets without FP not yet implemented");
2106  NumBytes = getWinEHFuncletFrameSize(MF);
2107  } else if (HasFP) {
2108  // Calculate required stack adjustment.
2109  uint64_t FrameSize = StackSize - SlotSize;
2110  NumBytes = FrameSize - CSSize - TailCallArgReserveSize;
2111 
2112  // Callee-saved registers were pushed on stack before the stack was
2113  // realigned.
2114  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
2115  NumBytes = alignTo(FrameSize, MaxAlign);
2116  } else {
2117  NumBytes = StackSize - CSSize - TailCallArgReserveSize;
2118  }
2119  uint64_t SEHStackAllocAmt = NumBytes;
2120 
2121  // AfterPop is the position to insert .cfi_restore.
2122  MachineBasicBlock::iterator AfterPop = MBBI;
2123  if (HasFP) {
2124  if (X86FI->hasSwiftAsyncContext()) {
2125  // Discard the context.
2126  int Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
2127  emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/true);
2128  }
2129  // Pop EBP.
2130  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
2131  MachineFramePtr)
2133 
2134  // We need to reset FP to its untagged state on return. Bit 60 is currently
2135  // used to show the presence of an extended frame.
2136  if (X86FI->hasSwiftAsyncContext()) {
2137  BuildMI(MBB, MBBI, DL, TII.get(X86::BTR64ri8),
2138  MachineFramePtr)
2139  .addUse(MachineFramePtr)
2140  .addImm(60)
2142  }
2143 
2144  if (NeedsDwarfCFI) {
2145  unsigned DwarfStackPtr =
2146  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
2147  BuildCFI(MBB, MBBI, DL,
2148  MCCFIInstruction::cfiDefCfa(nullptr, DwarfStackPtr, SlotSize));
2149  if (!MBB.succ_empty() && !MBB.isReturnBlock()) {
2150  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
2151  BuildCFI(MBB, AfterPop, DL,
2152  MCCFIInstruction::createRestore(nullptr, DwarfFramePtr));
2153  --MBBI;
2154  --AfterPop;
2155  }
2156  --MBBI;
2157  }
2158  }
2159 
2160  MachineBasicBlock::iterator FirstCSPop = MBBI;
2161  // Skip the callee-saved pop instructions.
2162  while (MBBI != MBB.begin()) {
2163  MachineBasicBlock::iterator PI = std::prev(MBBI);
2164  unsigned Opc = PI->getOpcode();
2165 
2166  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
2167  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2168  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2169  (Opc != X86::BTR64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2170  (Opc != X86::ADD64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)))
2171  break;
2172  FirstCSPop = PI;
2173  }
2174 
2175  --MBBI;
2176  }
2177  MBBI = FirstCSPop;
2178 
2179  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
2180  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
2181 
2182  if (MBBI != MBB.end())
2183  DL = MBBI->getDebugLoc();
2184  // If there is an ADD32ri or SUB32ri of ESP immediately before this
2185  // instruction, merge the two instructions.
2186  if (NumBytes || MFI.hasVarSizedObjects())
2187  NumBytes += mergeSPUpdates(MBB, MBBI, true);
2188 
2189  // If dynamic alloca is used, then reset esp to point to the last callee-saved
2190  // slot before popping them off! Same applies for the case, when stack was
2191  // realigned. Don't do this if this was a funclet epilogue, since the funclets
2192  // will not do realignment or dynamic stack allocation.
2193  if (((TRI->hasStackRealignment(MF)) || MFI.hasVarSizedObjects()) &&
2194  !IsFunclet) {
2195  if (TRI->hasStackRealignment(MF))
2196  MBBI = FirstCSPop;
2197  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
2198  uint64_t LEAAmount =
2199  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
2200 
2201  if (X86FI->hasSwiftAsyncContext())
2202  LEAAmount -= 16;
2203 
2204  // There are only two legal forms of epilogue:
2205  // - add SEHAllocationSize, %rsp
2206  // - lea SEHAllocationSize(%FramePtr), %rsp
2207  //
2208  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
2209  // However, we may use this sequence if we have a frame pointer because the
2210  // effects of the prologue can safely be undone.
2211  if (LEAAmount != 0) {
2212  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
2213  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
2214  FramePtr, false, LEAAmount);
2215  --MBBI;
2216  } else {
2217  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
2218  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
2219  .addReg(FramePtr);
2220  --MBBI;
2221  }
2222  } else if (NumBytes) {
2223  // Adjust stack pointer back: ESP += numbytes.
2224  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
2225  if (!HasFP && NeedsDwarfCFI) {
2226  // Define the current CFA rule to use the provided offset.
2227  BuildCFI(MBB, MBBI, DL,
2229  nullptr, CSSize + TailCallArgReserveSize + SlotSize));
2230  }
2231  --MBBI;
2232  }
2233 
2234  // Windows unwinder will not invoke function's exception handler if IP is
2235  // either in prologue or in epilogue. This behavior causes a problem when a
2236  // call immediately precedes an epilogue, because the return address points
2237  // into the epilogue. To cope with that, we insert an epilogue marker here,
2238  // then replace it with a 'nop' if it ends up immediately after a CALL in the
2239  // final emitted code.
2240  if (NeedsWin64CFI && MF.hasWinCFI())
2241  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2242 
2243  if (!HasFP && NeedsDwarfCFI) {
2244  MBBI = FirstCSPop;
2245  int64_t Offset = -CSSize - SlotSize;
2246  // Mark callee-saved pop instruction.
2247  // Define the current CFA rule to use the provided offset.
2248  while (MBBI != MBB.end()) {
2250  unsigned Opc = PI->getOpcode();
2251  ++MBBI;
2252  if (Opc == X86::POP32r || Opc == X86::POP64r) {
2253  Offset += SlotSize;
2254  BuildCFI(MBB, MBBI, DL,
2256  }
2257  }
2258  }
2259 
2260  // Emit DWARF info specifying the restores of the callee-saved registers.
2261  // For epilogue with return inside or being other block without successor,
2262  // no need to generate .cfi_restore for callee-saved registers.
2263  if (NeedsDwarfCFI && !MBB.succ_empty())
2264  emitCalleeSavedFrameMoves(MBB, AfterPop, DL, false);
2265 
2266  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
2267  // Add the return addr area delta back since we are not tail calling.
2268  int Offset = -1 * X86FI->getTCReturnAddrDelta();
2269  assert(Offset >= 0 && "TCDelta should never be positive");
2270  if (Offset) {
2271  // Check for possible merge with preceding ADD instruction.
2272  Offset += mergeSPUpdates(MBB, Terminator, true);
2273  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
2274  }
2275  }
2276 
2277  // Emit tilerelease for AMX kernel.
2278  if (X86FI->hasVirtualTileReg())
2279  BuildMI(MBB, Terminator, DL, TII.get(X86::TILERELEASE));
2280 }
2281 
2283  int FI,
2284  Register &FrameReg) const {
2285  const MachineFrameInfo &MFI = MF.getFrameInfo();
2286 
2287  bool IsFixed = MFI.isFixedObjectIndex(FI);
2288  // We can't calculate offset from frame pointer if the stack is realigned,
2289  // so enforce usage of stack/base pointer. The base pointer is used when we
2290  // have dynamic allocas in addition to dynamic realignment.
2291  if (TRI->hasBasePointer(MF))
2292  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
2293  else if (TRI->hasStackRealignment(MF))
2294  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
2295  else
2296  FrameReg = TRI->getFrameRegister(MF);
2297 
2298  // Offset will hold the offset from the stack pointer at function entry to the
2299  // object.
2300  // We need to factor in additional offsets applied during the prologue to the
2301  // frame, base, and stack pointer depending on which is used.
2302  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
2304  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2305  uint64_t StackSize = MFI.getStackSize();
2306  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2307  int64_t FPDelta = 0;
2308 
2309  // In an x86 interrupt, remove the offset we added to account for the return
2310  // address from any stack object allocated in the caller's frame. Interrupts
2311  // do not have a standard return address. Fixed objects in the current frame,
2312  // such as SSE register spills, should not get this treatment.
2314  Offset >= 0) {
2316  }
2317 
2318  if (IsWin64Prologue) {
2319  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
2320 
2321  // Calculate required stack adjustment.
2322  uint64_t FrameSize = StackSize - SlotSize;
2323  // If required, include space for extra hidden slot for stashing base pointer.
2324  if (X86FI->getRestoreBasePointer())
2325  FrameSize += SlotSize;
2326  uint64_t NumBytes = FrameSize - CSSize;
2327 
2328  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
2329  if (FI && FI == X86FI->getFAIndex())
2330  return StackOffset::getFixed(-SEHFrameOffset);
2331 
2332  // FPDelta is the offset from the "traditional" FP location of the old base
2333  // pointer followed by return address and the location required by the
2334  // restricted Win64 prologue.
2335  // Add FPDelta to all offsets below that go through the frame pointer.
2336  FPDelta = FrameSize - SEHFrameOffset;
2337  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
2338  "FPDelta isn't aligned per the Win64 ABI!");
2339  }
2340 
2341  if (FrameReg == TRI->getFramePtr()) {
2342  // Skip saved EBP/RBP
2343  Offset += SlotSize;
2344 
2345  // Account for restricted Windows prologue.
2346  Offset += FPDelta;
2347 
2348  // Skip the RETADDR move area
2349  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2350  if (TailCallReturnAddrDelta < 0)
2351  Offset -= TailCallReturnAddrDelta;
2352 
2353  return StackOffset::getFixed(Offset);
2354  }
2355 
2356  // FrameReg is either the stack pointer or a base pointer. But the base is
2357  // located at the end of the statically known StackSize so the distinction
2358  // doesn't really matter.
2359  if (TRI->hasStackRealignment(MF) || TRI->hasBasePointer(MF))
2360  assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize)));
2361  return StackOffset::getFixed(Offset + StackSize);
2362 }
2363 
2365  Register &FrameReg) const {
2366  const MachineFrameInfo &MFI = MF.getFrameInfo();
2368  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2369  const auto it = WinEHXMMSlotInfo.find(FI);
2370 
2371  if (it == WinEHXMMSlotInfo.end())
2372  return getFrameIndexReference(MF, FI, FrameReg).getFixed();
2373 
2374  FrameReg = TRI->getStackRegister();
2375  return alignDown(MFI.getMaxCallFrameSize(), getStackAlign().value()) +
2376  it->second;
2377 }
2378 
2381  Register &FrameReg,
2382  int Adjustment) const {
2383  const MachineFrameInfo &MFI = MF.getFrameInfo();
2384  FrameReg = TRI->getStackRegister();
2385  return StackOffset::getFixed(MFI.getObjectOffset(FI) -
2386  getOffsetOfLocalArea() + Adjustment);
2387 }
2388 
2391  int FI, Register &FrameReg,
2392  bool IgnoreSPUpdates) const {
2393 
2394  const MachineFrameInfo &MFI = MF.getFrameInfo();
2395  // Does not include any dynamic realign.
2396  const uint64_t StackSize = MFI.getStackSize();
2397  // LLVM arranges the stack as follows:
2398  // ...
2399  // ARG2
2400  // ARG1
2401  // RETADDR
2402  // PUSH RBP <-- RBP points here
2403  // PUSH CSRs
2404  // ~~~~~~~ <-- possible stack realignment (non-win64)
2405  // ...
2406  // STACK OBJECTS
2407  // ... <-- RSP after prologue points here
2408  // ~~~~~~~ <-- possible stack realignment (win64)
2409  //
2410  // if (hasVarSizedObjects()):
2411  // ... <-- "base pointer" (ESI/RBX) points here
2412  // DYNAMIC ALLOCAS
2413  // ... <-- RSP points here
2414  //
2415  // Case 1: In the simple case of no stack realignment and no dynamic
2416  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
2417  // with fixed offsets from RSP.
2418  //
2419  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
2420  // stack objects are addressed with RBP and regular stack objects with RSP.
2421  //
2422  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
2423  // to address stack arguments for outgoing calls and nothing else. The "base
2424  // pointer" points to local variables, and RBP points to fixed objects.
2425  //
2426  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
2427  // answer we give is relative to the SP after the prologue, and not the
2428  // SP in the middle of the function.
2429 
2430  if (MFI.isFixedObjectIndex(FI) && TRI->hasStackRealignment(MF) &&
2431  !STI.isTargetWin64())
2432  return getFrameIndexReference(MF, FI, FrameReg);
2433 
2434  // If !hasReservedCallFrame the function might have SP adjustement in the
2435  // body. So, even though the offset is statically known, it depends on where
2436  // we are in the function.
2437  if (!IgnoreSPUpdates && !hasReservedCallFrame(MF))
2438  return getFrameIndexReference(MF, FI, FrameReg);
2439 
2440  // We don't handle tail calls, and shouldn't be seeing them either.
2442  "we don't handle this case!");
2443 
2444  // This is how the math works out:
2445  //
2446  // %rsp grows (i.e. gets lower) left to right. Each box below is
2447  // one word (eight bytes). Obj0 is the stack slot we're trying to
2448  // get to.
2449  //
2450  // ----------------------------------
2451  // | BP | Obj0 | Obj1 | ... | ObjN |
2452  // ----------------------------------
2453  // ^ ^ ^ ^
2454  // A B C E
2455  //
2456  // A is the incoming stack pointer.
2457  // (B - A) is the local area offset (-8 for x86-64) [1]
2458  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
2459  //
2460  // |(E - B)| is the StackSize (absolute value, positive). For a
2461  // stack that grown down, this works out to be (B - E). [3]
2462  //
2463  // E is also the value of %rsp after stack has been set up, and we
2464  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
2465  // (C - E) == (C - A) - (B - A) + (B - E)
2466  // { Using [1], [2] and [3] above }
2467  // == getObjectOffset - LocalAreaOffset + StackSize
2468 
2469  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
2470 }
2471 
2474  std::vector<CalleeSavedInfo> &CSI) const {
2475  MachineFrameInfo &MFI = MF.getFrameInfo();
2477 
2478  unsigned CalleeSavedFrameSize = 0;
2479  unsigned XMMCalleeSavedFrameSize = 0;
2480  auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2481  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
2482 
2483  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2484 
2485  if (TailCallReturnAddrDelta < 0) {
2486  // create RETURNADDR area
2487  // arg
2488  // arg
2489  // RETADDR
2490  // { ...
2491  // RETADDR area
2492  // ...
2493  // }
2494  // [EBP]
2495  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
2496  TailCallReturnAddrDelta - SlotSize, true);
2497  }
2498 
2499  // Spill the BasePtr if it's used.
2500  if (this->TRI->hasBasePointer(MF)) {
2501  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
2502  if (MF.hasEHFunclets()) {
2504  X86FI->setHasSEHFramePtrSave(true);
2505  X86FI->setSEHFramePtrSaveIndex(FI);
2506  }
2507  }
2508 
2509  if (hasFP(MF)) {
2510  // emitPrologue always spills frame register the first thing.
2511  SpillSlotOffset -= SlotSize;
2512  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2513 
2514  // The async context lives directly before the frame pointer, and we
2515  // allocate a second slot to preserve stack alignment.
2516  if (X86FI->hasSwiftAsyncContext()) {
2517  SpillSlotOffset -= SlotSize;
2518  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2519  SpillSlotOffset -= SlotSize;
2520  }
2521 
2522  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
2523  // the frame register, we can delete it from CSI list and not have to worry
2524  // about avoiding it later.
2525  Register FPReg = TRI->getFrameRegister(MF);
2526  for (unsigned i = 0; i < CSI.size(); ++i) {
2527  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
2528  CSI.erase(CSI.begin() + i);
2529  break;
2530  }
2531  }
2532  }
2533 
2534  // Assign slots for GPRs. It increases frame size.
2535  for (CalleeSavedInfo &I : llvm::reverse(CSI)) {
2536  unsigned Reg = I.getReg();
2537 
2538  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2539  continue;
2540 
2541  SpillSlotOffset -= SlotSize;
2542  CalleeSavedFrameSize += SlotSize;
2543 
2544  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2545  I.setFrameIdx(SlotIndex);
2546  }
2547 
2548  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2549  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2550 
2551  // Assign slots for XMMs.
2552  for (CalleeSavedInfo &I : llvm::reverse(CSI)) {
2553  unsigned Reg = I.getReg();
2554  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2555  continue;
2556 
2557  // If this is k-register make sure we lookup via the largest legal type.
2558  MVT VT = MVT::Other;
2559  if (X86::VK16RegClass.contains(Reg))
2560  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2561 
2562  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2563  unsigned Size = TRI->getSpillSize(*RC);
2564  Align Alignment = TRI->getSpillAlign(*RC);
2565  // ensure alignment
2566  assert(SpillSlotOffset < 0 && "SpillSlotOffset should always < 0 on X86");
2567  SpillSlotOffset = -alignTo(-SpillSlotOffset, Alignment);
2568 
2569  // spill into slot
2570  SpillSlotOffset -= Size;
2571  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2572  I.setFrameIdx(SlotIndex);
2573  MFI.ensureMaxAlignment(Alignment);
2574 
2575  // Save the start offset and size of XMM in stack frame for funclets.
2576  if (X86::VR128RegClass.contains(Reg)) {
2577  WinEHXMMSlotInfo[SlotIndex] = XMMCalleeSavedFrameSize;
2578  XMMCalleeSavedFrameSize += Size;
2579  }
2580  }
2581 
2582  return true;
2583 }
2584 
2587  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
2589 
2590  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2591  // for us, and there are no XMM CSRs on Win32.
2592  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2593  return true;
2594 
2595  // Push GPRs. It increases frame size.
2596  const MachineFunction &MF = *MBB.getParent();
2597  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2598  for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
2599  unsigned Reg = I.getReg();
2600 
2601  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2602  continue;
2603 
2604  const MachineRegisterInfo &MRI = MF.getRegInfo();
2605  bool isLiveIn = MRI.isLiveIn(Reg);
2606  if (!isLiveIn)
2607  MBB.addLiveIn(Reg);
2608 
2609  // Decide whether we can add a kill flag to the use.
2610  bool CanKill = !isLiveIn;
2611  // Check if any subregister is live-in
2612  if (CanKill) {
2613  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2614  if (MRI.isLiveIn(*AReg)) {
2615  CanKill = false;
2616  break;
2617  }
2618  }
2619  }
2620 
2621  // Do not set a kill flag on values that are also marked as live-in. This
2622  // happens with the @llvm-returnaddress intrinsic and with arguments
2623  // passed in callee saved registers.
2624  // Omitting the kill flags is conservatively correct even if the live-in
2625  // is not used after all.
2626  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2628  }
2629 
2630  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2631  // It can be done by spilling XMMs to stack frame.
2632  for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
2633  unsigned Reg = I.getReg();
2634  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2635  continue;
2636 
2637  // If this is k-register make sure we lookup via the largest legal type.
2638  MVT VT = MVT::Other;
2639  if (X86::VK16RegClass.contains(Reg))
2640  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2641 
2642  // Add the callee-saved register as live-in. It's killed at the spill.
2643  MBB.addLiveIn(Reg);
2644  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2645 
2646  TII.storeRegToStackSlot(MBB, MI, Reg, true, I.getFrameIdx(), RC, TRI);
2647  --MI;
2648  MI->setFlag(MachineInstr::FrameSetup);
2649  ++MI;
2650  }
2651 
2652  return true;
2653 }
2654 
2655 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2657  MachineInstr *CatchRet) const {
2658  // SEH shouldn't use catchret.
2661  "SEH should not use CATCHRET");
2662  const DebugLoc &DL = CatchRet->getDebugLoc();
2663  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2664 
2665  // Fill EAX/RAX with the address of the target block.
2666  if (STI.is64Bit()) {
2667  // LEA64r CatchRetTarget(%rip), %rax
2668  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2669  .addReg(X86::RIP)
2670  .addImm(0)
2671  .addReg(0)
2672  .addMBB(CatchRetTarget)
2673  .addReg(0);
2674  } else {
2675  // MOV32ri $CatchRetTarget, %eax
2676  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2677  .addMBB(CatchRetTarget);
2678  }
2679 
2680  // Record that we've taken the address of CatchRetTarget and no longer just
2681  // reference it in a terminator.
2682  CatchRetTarget->setHasAddressTaken();
2683 }
2684 
2688  if (CSI.empty())
2689  return false;
2690 
2691  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2692  // Don't restore CSRs in 32-bit EH funclets. Matches
2693  // spillCalleeSavedRegisters.
2694  if (STI.is32Bit())
2695  return true;
2696  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2697  // funclets. emitEpilogue transforms these to normal jumps.
2698  if (MI->getOpcode() == X86::CATCHRET) {
2699  const Function &F = MBB.getParent()->getFunction();
2700  bool IsSEH = isAsynchronousEHPersonality(
2701  classifyEHPersonality(F.getPersonalityFn()));
2702  if (IsSEH)
2703  return true;
2704  }
2705  }
2706 
2708 
2709  // Reload XMMs from stack frame.
2710  for (const CalleeSavedInfo &I : CSI) {
2711  unsigned Reg = I.getReg();
2712  if (X86::GR64RegClass.contains(Reg) ||
2713  X86::GR32RegClass.contains(Reg))
2714  continue;
2715 
2716  // If this is k-register make sure we lookup via the largest legal type.
2717  MVT VT = MVT::Other;
2718  if (X86::VK16RegClass.contains(Reg))
2719  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2720 
2721  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2722  TII.loadRegFromStackSlot(MBB, MI, Reg, I.getFrameIdx(), RC, TRI);
2723  }
2724 
2725  // POP GPRs.
2726  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2727  for (const CalleeSavedInfo &I : CSI) {
2728  unsigned Reg = I.getReg();
2729  if (!X86::GR64RegClass.contains(Reg) &&
2730  !X86::GR32RegClass.contains(Reg))
2731  continue;
2732 
2733  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2735  }
2736  return true;
2737 }
2738 
2740  BitVector &SavedRegs,
2741  RegScavenger *RS) const {
2742  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2743 
2744  // Spill the BasePtr if it's used.
2745  if (TRI->hasBasePointer(MF)){
2746  Register BasePtr = TRI->getBaseRegister();
2747  if (STI.isTarget64BitILP32())
2748  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2749  SavedRegs.set(BasePtr);
2750  }
2751 }
2752 
2753 static bool
2755  const Function &F = MF->getFunction();
2756  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2757  I != E; I++) {
2758  if (I->hasNestAttr() && !I->use_empty())
2759  return true;
2760  }
2761  return false;
2762 }
2763 
2764 /// GetScratchRegister - Get a temp register for performing work in the
2765 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2766 /// and the properties of the function either one or two registers will be
2767 /// needed. Set primary to true for the first register, false for the second.
2768 static unsigned
2769 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2771 
2772  // Erlang stuff.
2774  if (Is64Bit)
2775  return Primary ? X86::R14 : X86::R13;
2776  else
2777  return Primary ? X86::EBX : X86::EDI;
2778  }
2779 
2780  if (Is64Bit) {
2781  if (IsLP64)
2782  return Primary ? X86::R11 : X86::R12;
2783  else
2784  return Primary ? X86::R11D : X86::R12D;
2785  }
2786 
2787  bool IsNested = HasNestArgument(&MF);
2788 
2792  if (IsNested)
2793  report_fatal_error("Segmented stacks does not support fastcall with "
2794  "nested function.");
2795  return Primary ? X86::EAX : X86::ECX;
2796  }
2797  if (IsNested)
2798  return Primary ? X86::EDX : X86::EAX;
2799  return Primary ? X86::ECX : X86::EAX;
2800 }
2801 
2802 // The stack limit in the TCB is set to this many bytes above the actual stack
2803 // limit.
2804 static const uint64_t kSplitStackAvailable = 256;
2805 
2807  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2808  MachineFrameInfo &MFI = MF.getFrameInfo();
2809  uint64_t StackSize;
2810  unsigned TlsReg, TlsOffset;
2811  DebugLoc DL;
2812 
2813  // To support shrink-wrapping we would need to insert the new blocks
2814  // at the right place and update the branches to PrologueMBB.
2815  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2816 
2817  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2818  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2819  "Scratch register is live-in");
2820 
2821  if (MF.getFunction().isVarArg())
2822  report_fatal_error("Segmented stacks do not support vararg functions.");
2823  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2824  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2826  report_fatal_error("Segmented stacks not supported on this platform.");
2827 
2828  // Eventually StackSize will be calculated by a link-time pass; which will
2829  // also decide whether checking code needs to be injected into this particular
2830  // prologue.
2831  StackSize = MFI.getStackSize();
2832 
2833  // Do not generate a prologue for leaf functions with a stack of size zero.
2834  // For non-leaf functions we have to allow for the possibility that the
2835  // callis to a non-split function, as in PR37807. This function could also
2836  // take the address of a non-split function. When the linker tries to adjust
2837  // its non-existent prologue, it would fail with an error. Mark the object
2838  // file so that such failures are not errors. See this Go language bug-report
2839  // https://go-review.googlesource.com/c/go/+/148819/
2840  if (StackSize == 0 && !MFI.hasTailCall()) {
2841  MF.getMMI().setHasNosplitStack(true);
2842  return;
2843  }
2844 
2845  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2846  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2848  bool IsNested = false;
2849 
2850  // We need to know if the function has a nest argument only in 64 bit mode.
2851  if (Is64Bit)
2852  IsNested = HasNestArgument(&MF);
2853 
2854  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2855  // allocMBB needs to be last (terminating) instruction.
2856 
2857  for (const auto &LI : PrologueMBB.liveins()) {
2858  allocMBB->addLiveIn(LI);
2859  checkMBB->addLiveIn(LI);
2860  }
2861 
2862  if (IsNested)
2863  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2864 
2865  MF.push_front(allocMBB);
2866  MF.push_front(checkMBB);
2867 
2868  // When the frame size is less than 256 we just compare the stack
2869  // boundary directly to the value of the stack pointer, per gcc.
2870  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2871 
2872  // Read the limit off the current stacklet off the stack_guard location.
2873  if (Is64Bit) {
2874  if (STI.isTargetLinux()) {
2875  TlsReg = X86::FS;
2876  TlsOffset = IsLP64 ? 0x70 : 0x40;
2877  } else if (STI.isTargetDarwin()) {
2878  TlsReg = X86::GS;
2879  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2880  } else if (STI.isTargetWin64()) {
2881  TlsReg = X86::GS;
2882  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2883  } else if (STI.isTargetFreeBSD()) {
2884  TlsReg = X86::FS;
2885  TlsOffset = 0x18;
2886  } else if (STI.isTargetDragonFly()) {
2887  TlsReg = X86::FS;
2888  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2889  } else {
2890  report_fatal_error("Segmented stacks not supported on this platform.");
2891  }
2892 
2893  if (CompareStackPointer)
2894  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2895  else
2896  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2897  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2898 
2899  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2900  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2901  } else {
2902  if (STI.isTargetLinux()) {
2903  TlsReg = X86::GS;
2904  TlsOffset = 0x30;
2905  } else if (STI.isTargetDarwin()) {
2906  TlsReg = X86::GS;
2907  TlsOffset = 0x48 + 90*4;
2908  } else if (STI.isTargetWin32()) {
2909  TlsReg = X86::FS;
2910  TlsOffset = 0x14; // pvArbitrary, reserved for application use
2911  } else if (STI.isTargetDragonFly()) {
2912  TlsReg = X86::FS;
2913  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2914  } else if (STI.isTargetFreeBSD()) {
2915  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2916  } else {
2917  report_fatal_error("Segmented stacks not supported on this platform.");
2918  }
2919 
2920  if (CompareStackPointer)
2921  ScratchReg = X86::ESP;
2922  else
2923  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2924  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2925 
2926  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2927  STI.isTargetDragonFly()) {
2928  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2929  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2930  } else if (STI.isTargetDarwin()) {
2931 
2932  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2933  unsigned ScratchReg2;
2934  bool SaveScratch2;
2935  if (CompareStackPointer) {
2936  // The primary scratch register is available for holding the TLS offset.
2937  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2938  SaveScratch2 = false;
2939  } else {
2940  // Need to use a second register to hold the TLS offset
2941  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2942 
2943  // Unfortunately, with fastcc the second scratch register may hold an
2944  // argument.
2945  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2946  }
2947 
2948  // If Scratch2 is live-in then it needs to be saved.
2949  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2950  "Scratch register is live-in and not saved");
2951 
2952  if (SaveScratch2)
2953  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2954  .addReg(ScratchReg2, RegState::Kill);
2955 
2956  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2957  .addImm(TlsOffset);
2958  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2959  .addReg(ScratchReg)
2960  .addReg(ScratchReg2).addImm(1).addReg(0)
2961  .addImm(0)
2962  .addReg(TlsReg);
2963 
2964  if (SaveScratch2)
2965  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2966  }
2967  }
2968 
2969  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2970  // It jumps to normal execution of the function body.
2971  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2972 
2973  // On 32 bit we first push the arguments size and then the frame size. On 64
2974  // bit, we pass the stack frame size in r10 and the argument size in r11.
2975  if (Is64Bit) {
2976  // Functions with nested arguments use R10, so it needs to be saved across
2977  // the call to _morestack
2978 
2979  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2980  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2981  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2982  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2983 
2984  if (IsNested)
2985  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2986 
2987  BuildMI(allocMBB, DL, TII.get(getMOVriOpcode(IsLP64, StackSize)), Reg10)
2988  .addImm(StackSize);
2989  BuildMI(allocMBB, DL,
2991  Reg11)
2992  .addImm(X86FI->getArgumentStackSize());
2993  } else {
2994  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2995  .addImm(X86FI->getArgumentStackSize());
2996  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2997  .addImm(StackSize);
2998  }
2999 
3000  // __morestack is in libgcc
3001  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
3002  // Under the large code model, we cannot assume that __morestack lives
3003  // within 2^31 bytes of the call site, so we cannot use pc-relative
3004  // addressing. We cannot perform the call via a temporary register,
3005  // as the rax register may be used to store the static chain, and all
3006  // other suitable registers may be either callee-save or used for
3007  // parameter passing. We cannot use the stack at this point either
3008  // because __morestack manipulates the stack directly.
3009  //
3010  // To avoid these issues, perform an indirect call via a read-only memory
3011  // location containing the address.
3012  //
3013  // This solution is not perfect, as it assumes that the .rodata section
3014  // is laid out within 2^31 bytes of each function body, but this seems
3015  // to be sufficient for JIT.
3016  // FIXME: Add retpoline support and remove the error here..
3017  if (STI.useIndirectThunkCalls())
3018  report_fatal_error("Emitting morestack calls on 64-bit with the large "
3019  "code model and thunks not yet implemented.");
3020  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
3021  .addReg(X86::RIP)
3022  .addImm(0)
3023  .addReg(0)
3024  .addExternalSymbol("__morestack_addr")
3025  .addReg(0);
3026  MF.getMMI().setUsesMorestackAddr(true);
3027  } else {
3028  if (Is64Bit)
3029  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
3030  .addExternalSymbol("__morestack");
3031  else
3032  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
3033  .addExternalSymbol("__morestack");
3034  }
3035 
3036  if (IsNested)
3037  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
3038  else
3039  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
3040 
3041  allocMBB->addSuccessor(&PrologueMBB);
3042 
3043  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
3044  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
3045 
3046 #ifdef EXPENSIVE_CHECKS
3047  MF.verify();
3048 #endif
3049 }
3050 
3051 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
3052 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
3053 /// to fields it needs, through a named metadata node "hipe.literals" containing
3054 /// name-value pairs.
3055 static unsigned getHiPELiteral(
3056  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
3057  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
3058  MDNode *Node = HiPELiteralsMD->getOperand(i);
3059  if (Node->getNumOperands() != 2) continue;
3060  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
3061  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
3062  if (!NodeName || !NodeVal) continue;
3063  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
3064  if (ValConst && NodeName->getString() == LiteralName) {
3065  return ValConst->getZExtValue();
3066  }
3067  }
3068 
3069  report_fatal_error("HiPE literal " + LiteralName
3070  + " required but not provided");
3071 }
3072 
3073 // Return true if there are no non-ehpad successors to MBB and there are no
3074 // non-meta instructions between MBBI and MBB.end().
3077  return llvm::all_of(
3078  MBB.successors(),
3079  [](const MachineBasicBlock *Succ) { return Succ->isEHPad(); }) &&
3080  std::all_of(MBBI, MBB.end(), [](const MachineInstr &MI) {
3081  return MI.isMetaInstruction();
3082  });
3083 }
3084 
3085 /// Erlang programs may need a special prologue to handle the stack size they
3086 /// might need at runtime. That is because Erlang/OTP does not implement a C
3087 /// stack but uses a custom implementation of hybrid stack/heap architecture.
3088 /// (for more information see Eric Stenman's Ph.D. thesis:
3089 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
3090 ///
3091 /// CheckStack:
3092 /// temp0 = sp - MaxStack
3093 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3094 /// OldStart:
3095 /// ...
3096 /// IncStack:
3097 /// call inc_stack # doubles the stack space
3098 /// temp0 = sp - MaxStack
3099 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3101  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
3102  MachineFrameInfo &MFI = MF.getFrameInfo();
3103  DebugLoc DL;
3104 
3105  // To support shrink-wrapping we would need to insert the new blocks
3106  // at the right place and update the branches to PrologueMBB.
3107  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
3108 
3109  // HiPE-specific values
3110  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
3111  ->getNamedMetadata("hipe.literals");
3112  if (!HiPELiteralsMD)
3114  "Can't generate HiPE prologue without runtime parameters");
3115  const unsigned HipeLeafWords
3116  = getHiPELiteral(HiPELiteralsMD,
3117  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
3118  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
3119  const unsigned Guaranteed = HipeLeafWords * SlotSize;
3120  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
3121  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
3122  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
3123 
3124  assert(STI.isTargetLinux() &&
3125  "HiPE prologue is only supported on Linux operating systems.");
3126 
3127  // Compute the largest caller's frame that is needed to fit the callees'
3128  // frames. This 'MaxStack' is computed from:
3129  //
3130  // a) the fixed frame size, which is the space needed for all spilled temps,
3131  // b) outgoing on-stack parameter areas, and
3132  // c) the minimum stack space this function needs to make available for the
3133  // functions it calls (a tunable ABI property).
3134  if (MFI.hasCalls()) {
3135  unsigned MoreStackForCalls = 0;
3136 
3137  for (auto &MBB : MF) {
3138  for (auto &MI : MBB) {
3139  if (!MI.isCall())
3140  continue;
3141 
3142  // Get callee operand.
3143  const MachineOperand &MO = MI.getOperand(0);
3144 
3145  // Only take account of global function calls (no closures etc.).
3146  if (!MO.isGlobal())
3147  continue;
3148 
3149  const Function *F = dyn_cast<Function>(MO.getGlobal());
3150  if (!F)
3151  continue;
3152 
3153  // Do not update 'MaxStack' for primitive and built-in functions
3154  // (encoded with names either starting with "erlang."/"bif_" or not
3155  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
3156  // "_", such as the BIF "suspend_0") as they are executed on another
3157  // stack.
3158  if (F->getName().contains("erlang.") || F->getName().contains("bif_") ||
3159  F->getName().find_first_of("._") == StringRef::npos)
3160  continue;
3161 
3162  unsigned CalleeStkArity =
3163  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
3164  if (HipeLeafWords - 1 > CalleeStkArity)
3165  MoreStackForCalls = std::max(MoreStackForCalls,
3166  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
3167  }
3168  }
3169  MaxStack += MoreStackForCalls;
3170  }
3171 
3172  // If the stack frame needed is larger than the guaranteed then runtime checks
3173  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
3174  if (MaxStack > Guaranteed) {
3175  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
3176  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
3177 
3178  for (const auto &LI : PrologueMBB.liveins()) {
3179  stackCheckMBB->addLiveIn(LI);
3180  incStackMBB->addLiveIn(LI);
3181  }
3182 
3183  MF.push_front(incStackMBB);
3184  MF.push_front(stackCheckMBB);
3185 
3186  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
3187  unsigned LEAop, CMPop, CALLop;
3188  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
3189  if (Is64Bit) {
3190  SPReg = X86::RSP;
3191  PReg = X86::RBP;
3192  LEAop = X86::LEA64r;
3193  CMPop = X86::CMP64rm;
3194  CALLop = X86::CALL64pcrel32;
3195  } else {
3196  SPReg = X86::ESP;
3197  PReg = X86::EBP;
3198  LEAop = X86::LEA32r;
3199  CMPop = X86::CMP32rm;
3200  CALLop = X86::CALLpcrel32;
3201  }
3202 
3203  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
3204  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
3205  "HiPE prologue scratch register is live-in");
3206 
3207  // Create new MBB for StackCheck:
3208  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
3209  SPReg, false, -MaxStack);
3210  // SPLimitOffset is in a fixed heap location (pointed by BP).
3211  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
3212  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3213  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
3214 
3215  // Create new MBB for IncStack:
3216  BuildMI(incStackMBB, DL, TII.get(CALLop)).
3217  addExternalSymbol("inc_stack_0");
3218  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
3219  SPReg, false, -MaxStack);
3220  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
3221  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3222  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
3223 
3224  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
3225  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
3226  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
3227  incStackMBB->addSuccessor(incStackMBB, {1, 100});
3228  }
3229 #ifdef EXPENSIVE_CHECKS
3230  MF.verify();
3231 #endif
3232 }
3233 
3234 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
3236  const DebugLoc &DL,
3237  int Offset) const {
3238  if (Offset <= 0)
3239  return false;
3240 
3241  if (Offset % SlotSize)
3242  return false;
3243 
3244  int NumPops = Offset / SlotSize;
3245  // This is only worth it if we have at most 2 pops.
3246  if (NumPops != 1 && NumPops != 2)
3247  return false;
3248 
3249  // Handle only the trivial case where the adjustment directly follows
3250  // a call. This is the most common one, anyway.
3251  if (MBBI == MBB.begin())
3252  return false;
3253  MachineBasicBlock::iterator Prev = std::prev(MBBI);
3254  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
3255  return false;
3256 
3257  unsigned Regs[2];
3258  unsigned FoundRegs = 0;
3259 
3261  const MachineOperand &RegMask = Prev->getOperand(1);
3262 
3263  auto &RegClass =
3264  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
3265  // Try to find up to NumPops free registers.
3266  for (auto Candidate : RegClass) {
3267  // Poor man's liveness:
3268  // Since we're immediately after a call, any register that is clobbered
3269  // by the call and not defined by it can be considered dead.
3270  if (!RegMask.clobbersPhysReg(Candidate))
3271  continue;
3272 
3273  // Don't clobber reserved registers
3274  if (MRI.isReserved(Candidate))
3275  continue;
3276 
3277  bool IsDef = false;
3278  for (const MachineOperand &MO : Prev->implicit_operands()) {
3279  if (MO.isReg() && MO.isDef() &&
3280  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
3281  IsDef = true;
3282  break;
3283  }
3284  }
3285 
3286  if (IsDef)
3287  continue;
3288 
3289  Regs[FoundRegs++] = Candidate;
3290  if (FoundRegs == (unsigned)NumPops)
3291  break;
3292  }
3293 
3294  if (FoundRegs == 0)
3295  return false;
3296 
3297  // If we found only one free register, but need two, reuse the same one twice.
3298  while (FoundRegs < (unsigned)NumPops)
3299  Regs[FoundRegs++] = Regs[0];
3300 
3301  for (int i = 0; i < NumPops; ++i)
3302  BuildMI(MBB, MBBI, DL,
3303  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
3304 
3305  return true;
3306 }
3307 
3311  bool reserveCallFrame = hasReservedCallFrame(MF);
3312  unsigned Opcode = I->getOpcode();
3313  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
3314  DebugLoc DL = I->getDebugLoc(); // copy DebugLoc as I will be erased.
3315  uint64_t Amount = TII.getFrameSize(*I);
3316  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
3317  I = MBB.erase(I);
3318  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
3319 
3320  // Try to avoid emitting dead SP adjustments if the block end is unreachable,
3321  // typically because the function is marked noreturn (abort, throw,
3322  // assert_fail, etc).
3323  if (isDestroy && blockEndIsUnreachable(MBB, I))
3324  return I;
3325 
3326  if (!reserveCallFrame) {
3327  // If the stack pointer can be changed after prologue, turn the
3328  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
3329  // adjcallstackdown instruction into 'add ESP, <amt>'
3330 
3331  // We need to keep the stack aligned properly. To do this, we round the
3332  // amount of space needed for the outgoing arguments up to the next
3333  // alignment boundary.
3334  Amount = alignTo(Amount, getStackAlign());
3335 
3336  const Function &F = MF.getFunction();
3337  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3338  bool DwarfCFI = !WindowsCFI && MF.needsFrameMoves();
3339 
3340  // If we have any exception handlers in this function, and we adjust
3341  // the SP before calls, we may need to indicate this to the unwinder
3342  // using GNU_ARGS_SIZE. Note that this may be necessary even when
3343  // Amount == 0, because the preceding function may have set a non-0
3344  // GNU_ARGS_SIZE.
3345  // TODO: We don't need to reset this between subsequent functions,
3346  // if it didn't change.
3347  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
3348 
3349  if (HasDwarfEHHandlers && !isDestroy &&
3351  BuildCFI(MBB, InsertPos, DL,
3352  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
3353 
3354  if (Amount == 0)
3355  return I;
3356 
3357  // Factor out the amount that gets handled inside the sequence
3358  // (Pushes of argument for frame setup, callee pops for frame destroy)
3359  Amount -= InternalAmt;
3360 
3361  // TODO: This is needed only if we require precise CFA.
3362  // If this is a callee-pop calling convention, emit a CFA adjust for
3363  // the amount the callee popped.
3364  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
3365  BuildCFI(MBB, InsertPos, DL,
3366  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
3367 
3368  // Add Amount to SP to destroy a frame, or subtract to setup.
3369  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
3370 
3371  if (StackAdjustment) {
3372  // Merge with any previous or following adjustment instruction. Note: the
3373  // instructions merged with here do not have CFI, so their stack
3374  // adjustments do not feed into CfaAdjustment.
3375  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
3376  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
3377 
3378  if (StackAdjustment) {
3379  if (!(F.hasMinSize() &&
3380  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
3381  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
3382  /*InEpilogue=*/false);
3383  }
3384  }
3385 
3386  if (DwarfCFI && !hasFP(MF)) {
3387  // If we don't have FP, but need to generate unwind information,
3388  // we need to set the correct CFA offset after the stack adjustment.
3389  // How much we adjust the CFA offset depends on whether we're emitting
3390  // CFI only for EH purposes or for debugging. EH only requires the CFA
3391  // offset to be correct at each call site, while for debugging we want
3392  // it to be more precise.
3393 
3394  int64_t CfaAdjustment = -StackAdjustment;
3395  // TODO: When not using precise CFA, we also need to adjust for the
3396  // InternalAmt here.
3397  if (CfaAdjustment) {
3398  BuildCFI(MBB, InsertPos, DL,
3400  CfaAdjustment));
3401  }
3402  }
3403 
3404  return I;
3405  }
3406 
3407  if (InternalAmt) {
3410  while (CI != B && !std::prev(CI)->isCall())
3411  --CI;
3412  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
3413  }
3414 
3415  return I;
3416 }
3417 
3419  assert(MBB.getParent() && "Block is not attached to a function!");
3420  const MachineFunction &MF = *MBB.getParent();
3421  if (!MBB.isLiveIn(X86::EFLAGS))
3422  return true;
3423 
3425  return !TRI->hasStackRealignment(MF) && !X86FI->hasSwiftAsyncContext();
3426 }
3427 
3429  assert(MBB.getParent() && "Block is not attached to a function!");
3430 
3431  // Win64 has strict requirements in terms of epilogue and we are
3432  // not taking a chance at messing with them.
3433  // I.e., unless this block is already an exit block, we can't use
3434  // it as an epilogue.
3435  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
3436  return false;
3437 
3438  // Swift async context epilogue has a BTR instruction that clobbers parts of
3439  // EFLAGS.
3440  const MachineFunction &MF = *MBB.getParent();
3443 
3445  return true;
3446 
3447  // If we cannot use LEA to adjust SP, we may need to use ADD, which
3448  // clobbers the EFLAGS. Check that we do not need to preserve it,
3449  // otherwise, conservatively assume this is not
3450  // safe to insert the epilogue here.
3452 }
3453 
3455  // If we may need to emit frameless compact unwind information, give
3456  // up as this is currently broken: PR25614.
3457  bool CompactUnwind =
3459  nullptr;
3460  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF) ||
3461  !CompactUnwind) &&
3462  // The lowering of segmented stack and HiPE only support entry
3463  // blocks as prologue blocks: PR26107. This limitation may be
3464  // lifted if we fix:
3465  // - adjustForSegmentedStacks
3466  // - adjustForHiPEPrologue
3468  !MF.shouldSplitStack();
3469 }
3470 
3473  const DebugLoc &DL, bool RestoreSP) const {
3474  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
3475  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
3477  "restoring EBP/ESI on non-32-bit target");
3478 
3479  MachineFunction &MF = *MBB.getParent();
3480  Register FramePtr = TRI->getFrameRegister(MF);
3481  Register BasePtr = TRI->getBaseRegister();
3482  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
3484  MachineFrameInfo &MFI = MF.getFrameInfo();
3485 
3486  // FIXME: Don't set FrameSetup flag in catchret case.
3487 
3488  int FI = FuncInfo.EHRegNodeFrameIndex;
3489  int EHRegSize = MFI.getObjectSize(FI);
3490 
3491  if (RestoreSP) {
3492  // MOV32rm -EHRegSize(%ebp), %esp
3493  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
3494  X86::EBP, true, -EHRegSize)
3496  }
3497 
3498  Register UsedReg;
3499  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed();
3500  int EndOffset = -EHRegOffset - EHRegSize;
3501  FuncInfo.EHRegNodeEndOffset = EndOffset;
3502 
3503  if (UsedReg == FramePtr) {
3504  // ADD $offset, %ebp
3505  unsigned ADDri = getADDriOpcode(false, EndOffset);
3506  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
3507  .addReg(FramePtr)
3508  .addImm(EndOffset)
3510  ->getOperand(3)
3511  .setIsDead();
3512  assert(EndOffset >= 0 &&
3513  "end of registration object above normal EBP position!");
3514  } else if (UsedReg == BasePtr) {
3515  // LEA offset(%ebp), %esi
3516  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
3517  FramePtr, false, EndOffset)
3519  // MOV32rm SavedEBPOffset(%esi), %ebp
3520  assert(X86FI->getHasSEHFramePtrSave());
3521  int Offset =
3522  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
3523  .getFixed();
3524  assert(UsedReg == BasePtr);
3525  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
3526  UsedReg, true, Offset)
3528  } else {
3529  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
3530  }
3531  return MBBI;
3532 }
3533 
3535  return TRI->getSlotSize();
3536 }
3537 
3538 Register
3540  return TRI->getDwarfRegNum(StackPtr, true);
3541 }
3542 
3543 namespace {
3544 // Struct used by orderFrameObjects to help sort the stack objects.
3545 struct X86FrameSortingObject {
3546  bool IsValid = false; // true if we care about this Object.
3547  unsigned ObjectIndex = 0; // Index of Object into MFI list.
3548  unsigned ObjectSize = 0; // Size of Object in bytes.
3549  Align ObjectAlignment = Align(1); // Alignment of Object in bytes.
3550  unsigned ObjectNumUses = 0; // Object static number of uses.
3551 };
3552 
3553 // The comparison function we use for std::sort to order our local
3554 // stack symbols. The current algorithm is to use an estimated
3555 // "density". This takes into consideration the size and number of
3556 // uses each object has in order to roughly minimize code size.
3557 // So, for example, an object of size 16B that is referenced 5 times
3558 // will get higher priority than 4 4B objects referenced 1 time each.
3559 // It's not perfect and we may be able to squeeze a few more bytes out of
3560 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
3561 // fringe end can have special consideration, given their size is less
3562 // important, etc.), but the algorithmic complexity grows too much to be
3563 // worth the extra gains we get. This gets us pretty close.
3564 // The final order leaves us with objects with highest priority going
3565 // at the end of our list.
3566 struct X86FrameSortingComparator {
3567  inline bool operator()(const X86FrameSortingObject &A,
3568  const X86FrameSortingObject &B) const {
3569  uint64_t DensityAScaled, DensityBScaled;
3570 
3571  // For consistency in our comparison, all invalid objects are placed
3572  // at the end. This also allows us to stop walking when we hit the
3573  // first invalid item after it's all sorted.
3574  if (!A.IsValid)
3575  return false;
3576  if (!B.IsValid)
3577  return true;
3578 
3579  // The density is calculated by doing :
3580  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3581  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3582  // Since this approach may cause inconsistencies in
3583  // the floating point <, >, == comparisons, depending on the floating
3584  // point model with which the compiler was built, we're going
3585  // to scale both sides by multiplying with
3586  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3587  // the division and, with it, the need for any floating point
3588  // arithmetic.
3589  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3590  static_cast<uint64_t>(B.ObjectSize);
3591  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3592  static_cast<uint64_t>(A.ObjectSize);
3593 
3594  // If the two densities are equal, prioritize highest alignment
3595  // objects. This allows for similar alignment objects
3596  // to be packed together (given the same density).
3597  // There's room for improvement here, also, since we can pack
3598  // similar alignment (different density) objects next to each
3599  // other to save padding. This will also require further
3600  // complexity/iterations, and the overall gain isn't worth it,
3601  // in general. Something to keep in mind, though.
3602  if (DensityAScaled == DensityBScaled)
3603  return A.ObjectAlignment < B.ObjectAlignment;
3604 
3605  return DensityAScaled < DensityBScaled;
3606  }
3607 };
3608 } // namespace
3609 
3610 // Order the symbols in the local stack.
3611 // We want to place the local stack objects in some sort of sensible order.
3612 // The heuristic we use is to try and pack them according to static number
3613 // of uses and size of object in order to minimize code size.
3615  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3616  const MachineFrameInfo &MFI = MF.getFrameInfo();
3617 
3618  // Don't waste time if there's nothing to do.
3619  if (ObjectsToAllocate.empty())
3620  return;
3621 
3622  // Create an array of all MFI objects. We won't need all of these
3623  // objects, but we're going to create a full array of them to make
3624  // it easier to index into when we're counting "uses" down below.
3625  // We want to be able to easily/cheaply access an object by simply
3626  // indexing into it, instead of having to search for it every time.
3627  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3628 
3629  // Walk the objects we care about and mark them as such in our working
3630  // struct.
3631  for (auto &Obj : ObjectsToAllocate) {
3632  SortingObjects[Obj].IsValid = true;
3633  SortingObjects[Obj].ObjectIndex = Obj;
3634  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlign(Obj);
3635  // Set the size.
3636  int ObjectSize = MFI.getObjectSize(Obj);
3637  if (ObjectSize == 0)
3638  // Variable size. Just use 4.
3639  SortingObjects[Obj].ObjectSize = 4;
3640  else
3641  SortingObjects[Obj].ObjectSize = ObjectSize;
3642  }
3643 
3644  // Count the number of uses for each object.
3645  for (auto &MBB : MF) {
3646  for (auto &MI : MBB) {
3647  if (MI.isDebugInstr())
3648  continue;
3649  for (const MachineOperand &MO : MI.operands()) {
3650  // Check to see if it's a local stack symbol.
3651  if (!MO.isFI())
3652  continue;
3653  int Index = MO.getIndex();
3654  // Check to see if it falls within our range, and is tagged
3655  // to require ordering.
3656  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3657  SortingObjects[Index].IsValid)
3658  SortingObjects[Index].ObjectNumUses++;
3659  }
3660  }
3661  }
3662 
3663  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3664  // info).
3665  llvm::stable_sort(SortingObjects, X86FrameSortingComparator());
3666 
3667  // Now modify the original list to represent the final order that
3668  // we want. The order will depend on whether we're going to access them
3669  // from the stack pointer or the frame pointer. For SP, the list should
3670  // end up with the END containing objects that we want with smaller offsets.
3671  // For FP, it should be flipped.
3672  int i = 0;
3673  for (auto &Obj : SortingObjects) {
3674  // All invalid items are sorted at the end, so it's safe to stop.
3675  if (!Obj.IsValid)
3676  break;
3677  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3678  }
3679 
3680  // Flip it if we're accessing off of the FP.
3681  if (!TRI->hasStackRealignment(MF) && hasFP(MF))
3682  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3683 }
3684 
3685 
3687  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3688  unsigned Offset = 16;
3689  // RBP is immediately pushed.
3690  Offset += SlotSize;
3691  // All callee-saved registers are then pushed.
3692  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3693  // Every funclet allocates enough stack space for the largest outgoing call.
3694  Offset += getWinEHFuncletFrameSize(MF);
3695  return Offset;
3696 }
3697 
3699  MachineFunction &MF, RegScavenger *RS) const {
3700  // Mark the function as not having WinCFI. We will set it back to true in
3701  // emitPrologue if it gets called and emits CFI.
3702  MF.setHasWinCFI(false);
3703 
3704  // If we are using Windows x64 CFI, ensure that the stack is always 8 byte
3705  // aligned. The format doesn't support misaligned stack adjustments.
3706  if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
3708 
3709  // If this function isn't doing Win64-style C++ EH, we don't need to do
3710  // anything.
3711  if (STI.is64Bit() && MF.hasEHFunclets() &&
3714  adjustFrameForMsvcCxxEh(MF);
3715  }
3716 }
3717 
3718 void X86FrameLowering::adjustFrameForMsvcCxxEh(MachineFunction &MF) const {
3719  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3720  // relative to RSP after the prologue. Find the offset of the last fixed
3721  // object, so that we can allocate a slot immediately following it. If there
3722  // were no fixed objects, use offset -SlotSize, which is immediately after the
3723  // return address. Fixed objects have negative frame indices.
3724  MachineFrameInfo &MFI = MF.getFrameInfo();
3725  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3726  int64_t MinFixedObjOffset = -SlotSize;
3727  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3728  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3729 
3730  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3731  for (WinEHHandlerType &H : TBME.HandlerArray) {
3732  int FrameIndex = H.CatchObj.FrameIndex;
3733  if (FrameIndex != INT_MAX) {
3734  // Ensure alignment.
3735  unsigned Align = MFI.getObjectAlign(FrameIndex).value();
3736  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3737  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3738  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3739  }
3740  }
3741  }
3742 
3743  // Ensure alignment.
3744  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3745  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3746  int UnwindHelpFI =
3747  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*IsImmutable=*/false);
3748  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3749 
3750  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3751  // other frame setup instructions.
3752  MachineBasicBlock &MBB = MF.front();
3753  auto MBBI = MBB.begin();
3754  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3755  ++MBBI;
3756 
3758  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3759  UnwindHelpFI)
3760  .addImm(-2);
3761 }
3762 
3764  MachineFunction &MF, RegScavenger *RS) const {
3765  if (STI.is32Bit() && MF.hasEHFunclets())
3767 }
3768 
3770  MachineFunction &MF) const {
3771  // 32-bit functions have to restore stack pointers when control is transferred
3772  // back to the parent function. These blocks are identified as eh pads that
3773  // are not funclet entries.
3774  bool IsSEH = isAsynchronousEHPersonality(
3776  for (MachineBasicBlock &MBB : MF) {
3777  bool NeedsRestore = MBB.isEHPad() && !MBB.isEHFuncletEntry();
3778  if (NeedsRestore)
3780  /*RestoreSP=*/IsSEH);
3781  }
3782 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:723
llvm::EHPersonality::MSVC_CXX
@ MSVC_CXX
llvm::X86Subtarget::hasBWI
bool hasBWI() const
Definition: X86Subtarget.h:756
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::X86FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: X86FrameLowering.cpp:59
llvm::isAsynchronousEHPersonality
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
Definition: EHPersonalities.h:50
getADDriOpcode
static unsigned getADDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:117
llvm::X86FrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: X86FrameLowering.cpp:3428
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::dwarf::CallingConvention
CallingConvention
Definition: Dwarf.h:330
llvm::MCContext::getObjectFileInfo
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:427
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::X86FrameLowering::TRI
const X86RegisterInfo * TRI
Definition: X86FrameLowering.h:36
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::X86MachineFunctionInfo::getArgumentStackSize
unsigned getArgumentStackSize() const
Definition: X86MachineFunctionInfo.h:183
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2353
llvm::X86FrameLowering::adjustForHiPEPrologue
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime.
Definition: X86FrameLowering.cpp:3100
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
calculateSetFPREG
static unsigned calculateSetFPREG(uint64_t SPAdjust)
Definition: X86FrameLowering.cpp:1103
llvm::X86FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: X86FrameLowering.cpp:2585
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
it
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Definition: README-SSE.txt:81
llvm::NamedMDNode
A tuple of MDNodes.
Definition: Metadata.h:1421
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:579
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:54957
llvm::X86MachineFunctionInfo::getRestoreBasePointer
bool getRestoreBasePointer() const
Definition: X86MachineFunctionInfo.h:142
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:206
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::NamedMDNode::getNumOperands
unsigned getNumOperands() const
Definition: Metadata.cpp:1120
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:166
X86Subtarget.h
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Function
Definition: Function.h:62
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:859
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:93
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:566
llvm::X86MachineFunctionInfo::hasSwiftAsyncContext
bool hasSwiftAsyncContext() const
Definition: X86MachineFunctionInfo.h:211
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
X86InstrBuilder.h
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::MachineFrameInfo::hasCopyImplyingStackAdjustment
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
Definition: MachineFrameInfo.h:590
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:569
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineFrameInfo::setCVBytesOfCalleeSavedRegisters
void setCVBytesOfCalleeSavedRegisters(unsigned S)
Definition: MachineFrameInfo.h:639
llvm::X86FrameLowering::emitCalleeSavedFrameMoves
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool IsPrologue) const
Definition: X86FrameLowering.cpp:468
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:59
llvm::X86InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:918
Statistic.h
llvm::Module::getCodeViewFlag
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:571
llvm::X86MachineFunctionInfo::setCalleeSavedFrameSize
void setCalleeSavedFrameSize(unsigned bytes)
Definition: X86MachineFunctionInfo.h:151
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:435
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:852
llvm::recomputeLiveIns
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Definition: LivePhysRegs.h:196
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:625
isEAXLiveIn
static bool isEAXLiveIn(MachineBasicBlock &MBB)
Definition: X86FrameLowering.cpp:163
llvm::WinEHHandlerType
Definition: WinEHFuncInfo.h:60
llvm::X86FrameLowering::emitCalleeSavedFrameMovesFullCFA
void emitCalleeSavedFrameMovesFullCFA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Emits Dwarf Info specifying offsets of callee saved registers and frame pointer.
Definition: X86FrameLowering.cpp:447
llvm::X86FrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: X86FrameLowering.cpp:2472
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:822
llvm::X86FrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: X86FrameLowering.cpp:3454
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1372
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
getSUBrrOpcode
static unsigned getSUBrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:129
llvm::X86TargetLowering::getStackProbeSize
unsigned getStackProbeSize(MachineFunction &MF) const
Definition: X86ISelLowering.cpp:55003
MCObjectFileInfo.h
llvm::MachineFunction::push_front
void push_front(MachineBasicBlock *MBB)
Definition: MachineFunction.h:841
llvm::Function::arg_size
size_t arg_size() const
Definition: Function.h:771
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::X86MachineFunctionInfo::setHasSEHFramePtrSave
void setHasSEHFramePtrSave(bool V)
Definition: X86MachineFunctionInfo.h:190
llvm::WinEHFuncInfo::TryBlockMap
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
llvm::BranchProbability::getZero
static BranchProbability getZero()
Definition: BranchProbability.h:49
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:416
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:556
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:414
llvm::X86FrameLowering::orderFrameObjects
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
Definition: X86FrameLowering.cpp:3614
getANDriOpcode
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:137
llvm::addRegOffset
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset],...
Definition: X86InstrBuilder.h:157
EHPersonalities.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:842
llvm::X86FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: X86FrameLowering.cpp:3309
llvm::Optional
Definition: APInt.h:33
llvm::MachineFunction::callsUnwindInit
bool callsUnwindInit() const
Definition: MachineFunction.h:1059
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::X86MachineFunctionInfo::getRestoreBasePointerOffset
int getRestoreBasePointerOffset() const
Definition: X86MachineFunctionInfo.h:144
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::X86FrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: X86FrameLowering.cpp:3418
HasNestArgument
static bool HasNestArgument(const MachineFunction *MF)
Definition: X86FrameLowering.cpp:2754
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:292
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:893
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:622
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
llvm::X86FrameLowering::has128ByteRedZone
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
Definition: X86FrameLowering.cpp:1282
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:538
llvm::X86Subtarget::is32Bit
bool is32Bit() const
Definition: X86Subtarget.h:616
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::MachineFunction::getFrameInstructions
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the function's prologue.
Definition: MachineFunction.h:1024
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
isTailCallOpcode
static bool isTailCallOpcode(unsigned Opc)
Definition: X86FrameLowering.cpp:2065
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1298
flagsNeedToBePreservedBeforeTheTerminators
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
Definition: X86FrameLowering.cpp:180
X86FrameLowering.h
llvm::SwiftAsyncFramePointerMode::Never
@ Never
Never set the bit.
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:348
llvm::X86MachineFunctionInfo::getHasPushSequences
bool getHasPushSequences() const
Definition: X86MachineFunctionInfo.h:139
llvm::X86FrameLowering::getFrameIndexReferencePreferSP
StackOffset getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, Register &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
Definition: X86FrameLowering.cpp:2390
llvm::X86MachineFunctionInfo::hasPreallocatedCall
bool hasPreallocatedCall() const
Definition: X86MachineFunctionInfo.h:208
getADDrrOpcode
static unsigned getADDrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:133
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:21
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:750
getLEArOpcode
static unsigned getLEArOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:148
llvm::X86FrameLowering::restoreWinEHStackPointersInParent
void restoreWinEHStackPointersInParent(MachineFunction &MF) const
Definition: X86FrameLowering.cpp:3769
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
X86MachineFunctionInfo.h
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1649
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::X86FrameLowering::stackProbeFunctionModifiesSP
bool stackProbeFunctionModifiesSP() const override
Does the stack probe function call return with a modified stack pointer?
Definition: X86FrameLowering.cpp:512
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
PageSize
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
llvm::X86FrameLowering::getWin64EHFrameIndexRef
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
Definition: X86FrameLowering.cpp:2364
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
llvm::X86FrameLowering::needsFrameIndexResolution
bool needsFrameIndexResolution(const MachineFunction &MF) const override
Definition: X86FrameLowering.cpp:85
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::X86MachineFunctionInfo::setSEHFramePtrSaveIndex
void setSEHFramePtrSaveIndex(int Index)
Definition: X86MachineFunctionInfo.h:193
llvm::X86FrameLowering::getFrameIndexReferenceSP
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
Definition: X86FrameLowering.cpp:2380
llvm::MachineFrameInfo::ensureMaxAlignment
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
Definition: MachineFrameInfo.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:468
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::X86FrameLowering::BuildCFI
void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const
Wraps up getting a CFI index and building a MachineInstr for it.
Definition: X86FrameLowering.cpp:435
llvm::X86Subtarget::isTargetWin32
bool isTargetWin32() const
Definition: X86Subtarget.h:895
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1003
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:928
llvm::X86MachineFunctionInfo::getTCReturnAddrDelta
int getTCReturnAddrDelta() const
Definition: X86MachineFunctionInfo.h:162
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::WinEHFuncInfo::EHRegNodeFrameIndex
int EHRegNodeFrameIndex
Definition: WinEHFuncInfo.h:107
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::X86RegisterInfo::getFramePtr
Register getFramePtr() const
Returns physical register used as frame pointer.
Definition: X86RegisterInfo.h:144
MCSymbol.h
llvm::X86MachineFunctionInfo::getCalleeSavedFrameSize
unsigned getCalleeSavedFrameSize() const
Definition: X86MachineFunctionInfo.h:150
llvm::MVT::v64i1
@ v64i1
Definition: MachineValueType.h:70
llvm::X86FrameLowering::canUseLEAForSPInEpilogue
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
Definition: X86FrameLowering.cpp:1988
llvm::X86RegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: X86RegisterInfo.h:139
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::X86Subtarget::isTargetWindowsCoreCLR
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:873
llvm::X86FrameLowering::TII
const X86InstrInfo & TII
Definition: X86FrameLowering.h:35
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::MVT::v16i1
@ v16i1
Definition: MachineValueType.h:68
llvm::MCObjectFileInfo::getCompactUnwindSection
MCSection * getCompactUnwindSection() const
Definition: MCObjectFileInfo.h:263
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:753
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::codeview::ProcSymFlags::HasFP
@ HasFP
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:101
STATISTIC
STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue")
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:77
llvm::X86FrameLowering::emitStackProbe
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog, Optional< MachineFunction::DebugInstrOperandPair > InstrNum=None) const
Emit target stack probe code.
Definition: X86FrameLowering.cpp:495
llvm::X86::COND_A
@ COND_A
Definition: X86BaseInfo.h:88
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::X86FrameLowering::processFunctionBeforeFrameIndicesReplaced
void processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameIndicesReplaced - This method is called immediately before MO_FrameIndex op...
Definition: X86FrameLowering.cpp:3763
llvm::Function::hasPersonalityFn
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:775
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:286
llvm::X86InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3945
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:823
llvm::X86TargetLowering
Definition: X86ISelLowering.h:937
llvm::MachineFunction::setHasWinCFI
void setHasWinCFI(bool v)
Definition: MachineFunction.h:726
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:633
llvm::X86FrameLowering::restoreWin32EHStackPointers
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
Definition: X86FrameLowering.cpp:3471
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineBasicBlock::isCleanupFuncletEntry
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
Definition: MachineBasicBlock.h:575
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:334
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:656
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isOSWindows
bool isOSWindows() const
Definition: X86Subtarget.h:891
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:390
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:54962
llvm::X86FrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: X86FrameLowering.cpp:3698
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:470
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:531
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:630
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:316
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:592
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::X86FrameLowering::emitSPUpdate
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value.
Definition: X86FrameLowering.cpp:216
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::WinEHTryBlockMapEntry
Definition: WinEHFuncInfo.h:72
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:617
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::WinEHFuncInfo
Definition: WinEHFuncInfo.h:90
llvm::X86::COND_AE
@ COND_AE
Definition: X86BaseInfo.h:84
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:479
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFunction::callsEHReturn
bool callsEHReturn() const
Definition: MachineFunction.h:1056
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::X86MachineFunctionInfo::getUsesRedZone
bool getUsesRedZone() const
Definition: X86MachineFunctionInfo.h:202
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::MCCFIInstruction::createGnuArgsSize
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:629
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:813
AH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference AH
Definition: README-X86-64.txt:44
llvm::X86MachineFunctionInfo::getWinEHXMMSlotInfo
DenseMap< int, unsigned > & getWinEHXMMSlotInfo()
Definition: X86MachineFunctionInfo.h:146
llvm::X86FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: X86FrameLowering.cpp:1385
llvm::TargetOptions::SwiftAsyncFramePointer
SwiftAsyncFramePointerMode SwiftAsyncFramePointer
Control when and how the Swift async frame pointer bit should be set.
Definition: TargetOptions.h:241
llvm::X86FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: X86FrameLowering.cpp:2685
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::WinEHTryBlockMapEntry::HandlerArray
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1007
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::X86InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3977
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:528
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:199
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:420
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::NamedMDNode::getOperand
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1124
llvm::CallingConv::X86_INTR
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:189
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:562
llvm::MachineBasicBlock::setHasAddressTaken
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
Definition: MachineBasicBlock.h:219
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
llvm::X86FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: X86FrameLowering.cpp:2072
llvm::X86FrameLowering::mergeSPUpdates
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
Definition: X86FrameLowering.cpp:373
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::X86MachineFunctionInfo::hasVirtualTileReg
bool hasVirtualTileReg() const
Definition: X86MachineFunctionInfo.h:214
blockEndIsUnreachable
static bool blockEndIsUnreachable(const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI)
Definition: X86FrameLowering.cpp:3075
llvm::MachineFunction::getLandingPads
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
Definition: MachineFunction.h:1079
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MachineFunction::makeDebugValueSubstitution
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)
Create a substitution between one <instr,operand> value to a different, new value.
Definition: MachineFunction.cpp:975
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:524
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:482
MachineModuleInfo.h
llvm::WinEHFuncInfo::UnwindHelpFrameIdx
int UnwindHelpFrameIdx
Definition: WinEHFuncInfo.h:99
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::X86Subtarget::isTargetDragonFly
bool isTargetDragonFly() const
Definition: X86Subtarget.h:851
GetScratchRegister
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
Definition: X86FrameLowering.cpp:2769
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::ValueAsMetadata::getValue
Value * getValue() const
Definition: Metadata.h:384
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::EHPersonality::CoreCLR
@ CoreCLR
llvm::X86AS::GS
@ GS
Definition: X86.h:187
llvm::X86::COND_LE
@ COND_LE
Definition: X86BaseInfo.h:95
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineModuleInfo::setHasNosplitStack
void setHasNosplitStack(bool b)
Definition: MachineModuleInfo.h:229
llvm::BranchProbability::getOne
static BranchProbability getOne()
Definition: BranchProbability.h:50
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:351
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:755
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:241
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:208
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1223
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:849
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFrameInfo::hasPatchPoint
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:386
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
DataLayout.h
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:359
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:543
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:967
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::X86MachineFunctionInfo::getFAIndex
int getFAIndex() const
Definition: X86MachineFunctionInfo.h:159
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SwiftAsyncFramePointerMode::DeploymentBased
@ DeploymentBased
Determine whether to set the bit statically or dynamically based on the deployment target.
llvm::MCCFIInstruction::createAdjustCfaOffset
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:545
llvm::WinEHFuncInfo::EHRegNodeEndOffset
int EHRegNodeEndOffset
Definition: WinEHFuncInfo.h:108
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::X86FrameLowering::adjustForSegmentedStacks
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
Definition: X86FrameLowering.cpp:2806
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::EHPersonality
EHPersonality
Definition: EHPersonalities.h:22
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:139
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::X86InstrInfo::getFrameAdjustment
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:153
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:368
llvm::WinEHFuncInfo::PSPSymFrameIdx
int PSPSymFrameIdx
Definition: WinEHFuncInfo.h:100
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1676
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:531
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::EHPersonality::Unknown
@ Unknown
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86Subtarget::isTargetFreeBSD
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:850
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1784
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:434
llvm::X86FrameLowering::SlotSize
unsigned SlotSize
Definition: X86FrameLowering.h:38
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
H
#define H(x, y, z)
Definition: MD5.cpp:57
llvm::MachineFunction::needsFrameMoves
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
Definition: MachineFunction.cpp:592
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
llvm::X86Subtarget::isTargetWindowsMSVC
bool isTargetWindowsMSVC() const
Definition: X86Subtarget.h:869
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::X86FrameLowering::STI
const X86Subtarget & STI
Definition: X86FrameLowering.h:34
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:906
X86TargetMachine.h
llvm::X86RegisterInfo::findDeadCallerSavedReg
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
Definition: X86RegisterInfo.cpp:803
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1311
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::MachineFunction::getWinEHFuncInfo
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
Definition: MachineFunction.h:685
llvm::X86FrameLowering::inlineStackProbe
void inlineStackProbe(MachineFunction &MF, MachineBasicBlock &PrologMBB) const override
Replace a StackProbe inline-stub with the actual probe code inline.
Definition: X86FrameLowering.cpp:516
llvm::X86RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:645
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
Function.h
llvm::DenseMapBase::size
unsigned size() const
Definition: DenseMap.h:100
llvm::X86FrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: X86FrameLowering.cpp:2739
llvm::X86MachineFunctionInfo::setUsesRedZone
void setUsesRedZone(bool V)
Definition: X86MachineFunctionInfo.h:203
llvm::Function::needsUnwindTableEntry
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
Definition: Function.h:636
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::X86MachineFunctionInfo::getHasSEHFramePtrSave
bool getHasSEHFramePtrSave() const
Definition: X86MachineFunctionInfo.h:189
llvm::Function::getPersonalityFn
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1844
llvm::MachineFunction::hasEHFunclets
bool hasEHFunclets() const
Definition: MachineFunction.h:1068
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
WinEHFuncInfo.h
llvm::X86FrameLowering::IsLP64
bool IsLP64
Definition: X86FrameLowering.h:43
llvm::X86MachineFunctionInfo::getForceFramePointer
bool getForceFramePointer() const
Definition: X86MachineFunctionInfo.h:136
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::X86FrameLowering::X86FrameLowering
X86FrameLowering(const X86Subtarget &STI, MaybeAlign StackAlignOverride)
Definition: X86FrameLowering.cpp:45
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:190
false
Function Alias Analysis false
Definition: AliasAnaly