LLVM  16.0.0git
X86FrameLowering.cpp
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1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/Statistic.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCSymbol.h"
35 #include "llvm/Support/Debug.h"
37 #include <cstdlib>
38 
39 #define DEBUG_TYPE "x86-fl"
40 
41 STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue");
42 STATISTIC(NumFrameExtraProbe,
43  "Number of extra stack probes generated in prologue");
44 
45 using namespace llvm;
46 
48  MaybeAlign StackAlignOverride)
49  : TargetFrameLowering(StackGrowsDown, StackAlignOverride.valueOrOne(),
50  STI.is64Bit() ? -8 : -4),
51  STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
52  // Cache a bunch of frame-related predicates for this subtarget.
54  Is64Bit = STI.is64Bit();
56  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
59 }
60 
62  return !MF.getFrameInfo().hasVarSizedObjects() &&
63  !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences() &&
64  !MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall();
65 }
66 
67 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
68 /// call frame pseudos can be simplified. Having a FP, as in the default
69 /// implementation, is not sufficient here since we can't always use it.
70 /// Use a more nuanced condition.
71 bool
73  return hasReservedCallFrame(MF) ||
74  MF.getInfo<X86MachineFunctionInfo>()->hasPreallocatedCall() ||
75  (hasFP(MF) && !TRI->hasStackRealignment(MF)) ||
76  TRI->hasBasePointer(MF);
77 }
78 
79 // needsFrameIndexResolution - Do we need to perform FI resolution for
80 // this function. Normally, this is required only when the function
81 // has any stack objects. However, FI resolution actually has another job,
82 // not apparent from the title - it resolves callframesetup/destroy
83 // that were not simplified earlier.
84 // So, this is required for x86 functions that have push sequences even
85 // when there are no stack objects.
86 bool
88  return MF.getFrameInfo().hasStackObjects() ||
89  MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
90 }
91 
92 /// hasFP - Return true if the specified function should have a dedicated frame
93 /// pointer register. This is true if the function has variable sized allocas
94 /// or if frame pointer elimination is disabled.
96  const MachineFrameInfo &MFI = MF.getFrameInfo();
97  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
98  TRI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
102  MF.callsUnwindInit() || MF.hasEHFunclets() || MF.callsEHReturn() ||
103  MFI.hasStackMap() || MFI.hasPatchPoint() ||
104  (isWin64Prologue(MF) && MFI.hasCopyImplyingStackAdjustment()));
105 }
106 
107 static unsigned getSUBriOpcode(bool IsLP64, int64_t Imm) {
108  if (IsLP64) {
109  if (isInt<8>(Imm))
110  return X86::SUB64ri8;
111  return X86::SUB64ri32;
112  } else {
113  if (isInt<8>(Imm))
114  return X86::SUB32ri8;
115  return X86::SUB32ri;
116  }
117 }
118 
119 static unsigned getADDriOpcode(bool IsLP64, int64_t Imm) {
120  if (IsLP64) {
121  if (isInt<8>(Imm))
122  return X86::ADD64ri8;
123  return X86::ADD64ri32;
124  } else {
125  if (isInt<8>(Imm))
126  return X86::ADD32ri8;
127  return X86::ADD32ri;
128  }
129 }
130 
131 static unsigned getSUBrrOpcode(bool IsLP64) {
132  return IsLP64 ? X86::SUB64rr : X86::SUB32rr;
133 }
134 
135 static unsigned getADDrrOpcode(bool IsLP64) {
136  return IsLP64 ? X86::ADD64rr : X86::ADD32rr;
137 }
138 
139 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
140  if (IsLP64) {
141  if (isInt<8>(Imm))
142  return X86::AND64ri8;
143  return X86::AND64ri32;
144  }
145  if (isInt<8>(Imm))
146  return X86::AND32ri8;
147  return X86::AND32ri;
148 }
149 
150 static unsigned getLEArOpcode(bool IsLP64) {
151  return IsLP64 ? X86::LEA64r : X86::LEA32r;
152 }
153 
154 static unsigned getMOVriOpcode(bool Use64BitReg, int64_t Imm) {
155  if (Use64BitReg) {
156  if (isUInt<32>(Imm))
157  return X86::MOV32ri64;
158  if (isInt<32>(Imm))
159  return X86::MOV64ri32;
160  return X86::MOV64ri;
161  }
162  return X86::MOV32ri;
163 }
164 
167  unsigned Reg = RegMask.PhysReg;
168 
169  if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
170  Reg == X86::AH || Reg == X86::AL)
171  return true;
172  }
173 
174  return false;
175 }
176 
177 /// Check if the flags need to be preserved before the terminators.
178 /// This would be the case, if the eflags is live-in of the region
179 /// composed by the terminators or live-out of that region, without
180 /// being defined by a terminator.
181 static bool
183  for (const MachineInstr &MI : MBB.terminators()) {
184  bool BreakNext = false;
185  for (const MachineOperand &MO : MI.operands()) {
186  if (!MO.isReg())
187  continue;
188  Register Reg = MO.getReg();
189  if (Reg != X86::EFLAGS)
190  continue;
191 
192  // This terminator needs an eflags that is not defined
193  // by a previous another terminator:
194  // EFLAGS is live-in of the region composed by the terminators.
195  if (!MO.isDef())
196  return true;
197  // This terminator defines the eflags, i.e., we don't need to preserve it.
198  // However, we still need to check this specific terminator does not
199  // read a live-in value.
200  BreakNext = true;
201  }
202  // We found a definition of the eflags, no need to preserve them.
203  if (BreakNext)
204  return false;
205  }
206 
207  // None of the terminators use or define the eflags.
208  // Check if they are live-out, that would imply we need to preserve them.
209  for (const MachineBasicBlock *Succ : MBB.successors())
210  if (Succ->isLiveIn(X86::EFLAGS))
211  return true;
212 
213  return false;
214 }
215 
216 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
217 /// stack pointer by a constant value.
220  const DebugLoc &DL,
221  int64_t NumBytes, bool InEpilogue) const {
222  bool isSub = NumBytes < 0;
223  uint64_t Offset = isSub ? -NumBytes : NumBytes;
226 
227  uint64_t Chunk = (1LL << 31) - 1;
228 
229  MachineFunction &MF = *MBB.getParent();
230  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
231  const X86TargetLowering &TLI = *STI.getTargetLowering();
232  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
233 
234  // It's ok to not take into account large chunks when probing, as the
235  // allocation is split in smaller chunks anyway.
236  if (EmitInlineStackProbe && !InEpilogue) {
237 
238  // This pseudo-instruction is going to be expanded, potentially using a
239  // loop, by inlineStackProbe().
240  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset);
241  return;
242  } else if (Offset > Chunk) {
243  // Rather than emit a long series of instructions for large offsets,
244  // load the offset into a register and do one sub/add
245  unsigned Reg = 0;
246  unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
247 
248  if (isSub && !isEAXLiveIn(MBB))
249  Reg = Rax;
250  else
252 
253  unsigned AddSubRROpc =
255  if (Reg) {
256  BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Reg)
257  .addImm(Offset)
258  .setMIFlag(Flag);
259  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
260  .addReg(StackPtr)
261  .addReg(Reg);
262  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
263  return;
264  } else if (Offset > 8 * Chunk) {
265  // If we would need more than 8 add or sub instructions (a >16GB stack
266  // frame), it's worth spilling RAX to materialize this immediate.
267  // pushq %rax
268  // movabsq +-$Offset+-SlotSize, %rax
269  // addq %rsp, %rax
270  // xchg %rax, (%rsp)
271  // movq (%rsp), %rsp
272  assert(Is64Bit && "can't have 32-bit 16GB stack frame");
273  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
274  .addReg(Rax, RegState::Kill)
275  .setMIFlag(Flag);
276  // Subtract is not commutative, so negate the offset and always use add.
277  // Subtract 8 less and add 8 more to account for the PUSH we just did.
278  if (isSub)
279  Offset = -(Offset - SlotSize);
280  else
281  Offset = Offset + SlotSize;
282  BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Rax)
283  .addImm(Offset)
284  .setMIFlag(Flag);
285  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
286  .addReg(Rax)
287  .addReg(StackPtr);
288  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
289  // Exchange the new SP in RAX with the top of the stack.
290  addRegOffset(
291  BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
292  StackPtr, false, 0);
293  // Load new SP from the top of the stack into RSP.
294  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
295  StackPtr, false, 0);
296  return;
297  }
298  }
299 
300  while (Offset) {
301  uint64_t ThisVal = std::min(Offset, Chunk);
302  if (ThisVal == SlotSize) {
303  // Use push / pop for slot sized adjustments as a size optimization. We
304  // need to find a dead register when using pop.
305  unsigned Reg = isSub
306  ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
308  if (Reg) {
309  unsigned Opc = isSub
310  ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
311  : (Is64Bit ? X86::POP64r : X86::POP32r);
312  BuildMI(MBB, MBBI, DL, TII.get(Opc))
313  .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
314  .setMIFlag(Flag);
315  Offset -= ThisVal;
316  continue;
317  }
318  }
319 
320  BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue)
321  .setMIFlag(Flag);
322 
323  Offset -= ThisVal;
324  }
325 }
326 
327 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
329  const DebugLoc &DL, int64_t Offset, bool InEpilogue) const {
330  assert(Offset != 0 && "zero offset stack adjustment requested");
331 
332  // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
333  // is tricky.
334  bool UseLEA;
335  if (!InEpilogue) {
336  // Check if inserting the prologue at the beginning
337  // of MBB would require to use LEA operations.
338  // We need to use LEA operations if EFLAGS is live in, because
339  // it means an instruction will read it before it gets defined.
340  UseLEA = STI.useLeaForSP() || MBB.isLiveIn(X86::EFLAGS);
341  } else {
342  // If we can use LEA for SP but we shouldn't, check that none
343  // of the terminators uses the eflags. Otherwise we will insert
344  // a ADD that will redefine the eflags and break the condition.
345  // Alternatively, we could move the ADD, but this may not be possible
346  // and is an optimization anyway.
348  if (UseLEA && !STI.useLeaForSP())
350  // If that assert breaks, that means we do not do the right thing
351  // in canUseAsEpilogue.
353  "We shouldn't have allowed this insertion point");
354  }
355 
357  if (UseLEA) {
360  StackPtr),
361  StackPtr, false, Offset);
362  } else {
363  bool IsSub = Offset < 0;
364  uint64_t AbsOffset = IsSub ? -Offset : Offset;
365  const unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
366  : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
367  MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
368  .addReg(StackPtr)
369  .addImm(AbsOffset);
370  MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
371  }
372  return MI;
373 }
374 
377  bool doMergeWithPrevious) const {
378  if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
379  (!doMergeWithPrevious && MBBI == MBB.end()))
380  return 0;
381 
382  MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
383 
385  // It is assumed that ADD/SUB/LEA instruction is succeded by one CFI
386  // instruction, and that there are no DBG_VALUE or other instructions between
387  // ADD/SUB/LEA and its corresponding CFI instruction.
388  /* TODO: Add support for the case where there are multiple CFI instructions
389  below the ADD/SUB/LEA, e.g.:
390  ...
391  add
392  cfi_def_cfa_offset
393  cfi_offset
394  ...
395  */
396  if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
397  PI = std::prev(PI);
398 
399  unsigned Opc = PI->getOpcode();
400  int Offset = 0;
401 
402  if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
403  Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
404  PI->getOperand(0).getReg() == StackPtr){
405  assert(PI->getOperand(1).getReg() == StackPtr);
406  Offset = PI->getOperand(2).getImm();
407  } else if ((Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
408  PI->getOperand(0).getReg() == StackPtr &&
409  PI->getOperand(1).getReg() == StackPtr &&
410  PI->getOperand(2).getImm() == 1 &&
411  PI->getOperand(3).getReg() == X86::NoRegister &&
412  PI->getOperand(5).getReg() == X86::NoRegister) {
413  // For LEAs we have: def = lea SP, FI, noreg, Offset, noreg.
414  Offset = PI->getOperand(4).getImm();
415  } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
416  Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
417  PI->getOperand(0).getReg() == StackPtr) {
418  assert(PI->getOperand(1).getReg() == StackPtr);
419  Offset = -PI->getOperand(2).getImm();
420  } else
421  return 0;
422 
423  PI = MBB.erase(PI);
424  if (PI != MBB.end() && PI->isCFIInstruction()) {
425  auto CIs = MBB.getParent()->getFrameInstructions();
426  MCCFIInstruction CI = CIs[PI->getOperand(0).getCFIIndex()];
429  PI = MBB.erase(PI);
430  }
431  if (!doMergeWithPrevious)
433 
434  return Offset;
435 }
436 
439  const DebugLoc &DL,
440  const MCCFIInstruction &CFIInst,
441  MachineInstr::MIFlag Flag) const {
442  MachineFunction &MF = *MBB.getParent();
443  unsigned CFIIndex = MF.addFrameInst(CFIInst);
444  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
445  .addCFIIndex(CFIIndex)
446  .setMIFlag(Flag);
447 }
448 
449 /// Emits Dwarf Info specifying offsets of callee saved registers and
450 /// frame pointer. This is called only when basic block sections are enabled.
453  MachineFunction &MF = *MBB.getParent();
454  if (!hasFP(MF)) {
456  return;
457  }
458  const MachineModuleInfo &MMI = MF.getMMI();
459  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
460  const Register FramePtr = TRI->getFrameRegister(MF);
461  const Register MachineFramePtr =
463  : FramePtr;
464  unsigned DwarfReg = MRI->getDwarfRegNum(MachineFramePtr, true);
465  // Offset = space for return address + size of the frame pointer itself.
466  unsigned Offset = (Is64Bit ? 8 : 4) + (Uses64BitFramePtr ? 8 : 4);
468  MCCFIInstruction::createOffset(nullptr, DwarfReg, -Offset));
470 }
471 
474  const DebugLoc &DL, bool IsPrologue) const {
475  MachineFunction &MF = *MBB.getParent();
476  MachineFrameInfo &MFI = MF.getFrameInfo();
477  MachineModuleInfo &MMI = MF.getMMI();
478  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
479 
480  // Add callee saved registers to move list.
481  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
482 
483  // Calculate offsets.
484  for (const CalleeSavedInfo &I : CSI) {
485  int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
486  Register Reg = I.getReg();
487  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
488 
489  if (IsPrologue) {
490  BuildCFI(MBB, MBBI, DL,
491  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
492  } else {
493  BuildCFI(MBB, MBBI, DL,
494  MCCFIInstruction::createRestore(nullptr, DwarfReg));
495  }
496  }
497 }
498 
499 void X86FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
500  MachineBasicBlock &MBB) const {
501  const MachineFunction &MF = *MBB.getParent();
502 
503  // Insertion point.
505 
506  // Fake a debug loc.
507  DebugLoc DL;
508  if (MBBI != MBB.end())
509  DL = MBBI->getDebugLoc();
510 
511  // Zero out FP stack if referenced. Do this outside of the loop below so that
512  // it's done only once.
513  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
514  for (MCRegister Reg : RegsToZero.set_bits()) {
515  if (!X86::RFP80RegClass.contains(Reg))
516  continue;
517 
518  unsigned NumFPRegs = ST.is64Bit() ? 8 : 7;
519  for (unsigned i = 0; i != NumFPRegs; ++i)
520  BuildMI(MBB, MBBI, DL, TII.get(X86::LD_F0));
521 
522  for (unsigned i = 0; i != NumFPRegs; ++i)
523  BuildMI(MBB, MBBI, DL, TII.get(X86::ST_FPrr)).addReg(X86::ST0);
524  break;
525  }
526 
527  // For GPRs, we only care to clear out the 32-bit register.
528  BitVector GPRsToZero(TRI->getNumRegs());
529  for (MCRegister Reg : RegsToZero.set_bits())
530  if (TRI->isGeneralPurposeRegister(MF, Reg)) {
531  GPRsToZero.set(getX86SubSuperRegisterOrZero(Reg, 32));
532  RegsToZero.reset(Reg);
533  }
534 
535  for (MCRegister Reg : GPRsToZero.set_bits())
536  BuildMI(MBB, MBBI, DL, TII.get(X86::XOR32rr), Reg)
539 
540  // Zero out registers.
541  for (MCRegister Reg : RegsToZero.set_bits()) {
542  if (ST.hasMMX() && X86::VR64RegClass.contains(Reg))
543  // FIXME: Ignore MMX registers?
544  continue;
545 
546  unsigned XorOp;
547  if (X86::VR128RegClass.contains(Reg)) {
548  // XMM#
549  if (!ST.hasSSE1())
550  continue;
551  XorOp = X86::PXORrr;
552  } else if (X86::VR256RegClass.contains(Reg)) {
553  // YMM#
554  if (!ST.hasAVX())
555  continue;
556  XorOp = X86::VPXORrr;
557  } else if (X86::VR512RegClass.contains(Reg)) {
558  // ZMM#
559  if (!ST.hasAVX512())
560  continue;
561  XorOp = X86::VPXORYrr;
562  } else if (X86::VK1RegClass.contains(Reg) ||
563  X86::VK2RegClass.contains(Reg) ||
564  X86::VK4RegClass.contains(Reg) ||
565  X86::VK8RegClass.contains(Reg) ||
566  X86::VK16RegClass.contains(Reg)) {
567  if (!ST.hasVLX())
568  continue;
569  XorOp = ST.hasBWI() ? X86::KXORQrr : X86::KXORWrr;
570  } else {
571  continue;
572  }
573 
574  BuildMI(MBB, MBBI, DL, TII.get(XorOp), Reg)
577  }
578 }
579 
582  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog,
584  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
585  if (STI.isTargetWindowsCoreCLR()) {
586  if (InProlog) {
587  BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING))
588  .addImm(0 /* no explicit stack size */);
589  } else {
590  emitStackProbeInline(MF, MBB, MBBI, DL, false);
591  }
592  } else {
593  emitStackProbeCall(MF, MBB, MBBI, DL, InProlog, InstrNum);
594  }
595 }
596 
598  return STI.isOSWindows() && !STI.isTargetWin64();
599 }
600 
602  MachineBasicBlock &PrologMBB) const {
603  auto Where = llvm::find_if(PrologMBB, [](MachineInstr &MI) {
604  return MI.getOpcode() == X86::STACKALLOC_W_PROBING;
605  });
606  if (Where != PrologMBB.end()) {
607  DebugLoc DL = PrologMBB.findDebugLoc(Where);
608  emitStackProbeInline(MF, PrologMBB, Where, DL, true);
609  Where->eraseFromParent();
610  }
611 }
612 
613 void X86FrameLowering::emitStackProbeInline(MachineFunction &MF,
616  const DebugLoc &DL,
617  bool InProlog) const {
618  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
619  if (STI.isTargetWindowsCoreCLR() && STI.is64Bit())
620  emitStackProbeInlineWindowsCoreCLR64(MF, MBB, MBBI, DL, InProlog);
621  else
622  emitStackProbeInlineGeneric(MF, MBB, MBBI, DL, InProlog);
623 }
624 
625 void X86FrameLowering::emitStackProbeInlineGeneric(
627  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
628  MachineInstr &AllocWithProbe = *MBBI;
629  uint64_t Offset = AllocWithProbe.getOperand(0).getImm();
630 
631  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
632  const X86TargetLowering &TLI = *STI.getTargetLowering();
633  assert(!(STI.is64Bit() && STI.isTargetWindowsCoreCLR()) &&
634  "different expansion expected for CoreCLR 64 bit");
635 
636  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
637  uint64_t ProbeChunk = StackProbeSize * 8;
638 
639  uint64_t MaxAlign =
640  TRI->hasStackRealignment(MF) ? calculateMaxStackAlign(MF) : 0;
641 
642  // Synthesize a loop or unroll it, depending on the number of iterations.
643  // BuildStackAlignAND ensures that only MaxAlign % StackProbeSize bits left
644  // between the unaligned rsp and current rsp.
645  if (Offset > ProbeChunk) {
646  emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL, Offset,
647  MaxAlign % StackProbeSize);
648  } else {
649  emitStackProbeInlineGenericBlock(MF, MBB, MBBI, DL, Offset,
650  MaxAlign % StackProbeSize);
651  }
652 }
653 
654 void X86FrameLowering::emitStackProbeInlineGenericBlock(
657  uint64_t AlignOffset) const {
658 
659  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
660  const bool HasFP = hasFP(MF);
661  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
662  const X86TargetLowering &TLI = *STI.getTargetLowering();
663  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
664  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
665 
666  uint64_t CurrentOffset = 0;
667 
668  assert(AlignOffset < StackProbeSize);
669 
670  // If the offset is so small it fits within a page, there's nothing to do.
671  if (StackProbeSize < Offset + AlignOffset) {
672 
673  uint64_t StackAdjustment = StackProbeSize - AlignOffset;
674  BuildStackAdjustment(MBB, MBBI, DL, -StackAdjustment, /*InEpilogue=*/false)
676  if (!HasFP && NeedsDwarfCFI) {
677  BuildCFI(
678  MBB, MBBI, DL,
680  }
681 
682  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
684  StackPtr, false, 0)
685  .addImm(0)
687  NumFrameExtraProbe++;
688  CurrentOffset = StackProbeSize - AlignOffset;
689  }
690 
691  // For the next N - 1 pages, just probe. I tried to take advantage of
692  // natural probes but it implies much more logic and there was very few
693  // interesting natural probes to interleave.
694  while (CurrentOffset + StackProbeSize < Offset) {
695  BuildStackAdjustment(MBB, MBBI, DL, -StackProbeSize, /*InEpilogue=*/false)
697 
698  if (!HasFP && NeedsDwarfCFI) {
699  BuildCFI(
700  MBB, MBBI, DL,
701  MCCFIInstruction::createAdjustCfaOffset(nullptr, StackProbeSize));
702  }
703  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
705  StackPtr, false, 0)
706  .addImm(0)
708  NumFrameExtraProbe++;
709  CurrentOffset += StackProbeSize;
710  }
711 
712  // No need to probe the tail, it is smaller than a Page.
713  uint64_t ChunkSize = Offset - CurrentOffset;
714  if (ChunkSize == SlotSize) {
715  // Use push for slot sized adjustments as a size optimization,
716  // like emitSPUpdate does when not probing.
717  unsigned Reg = Is64Bit ? X86::RAX : X86::EAX;
718  unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
719  BuildMI(MBB, MBBI, DL, TII.get(Opc))
722  } else {
723  BuildStackAdjustment(MBB, MBBI, DL, -ChunkSize, /*InEpilogue=*/false)
725  }
726  // No need to adjust Dwarf CFA offset here, the last position of the stack has
727  // been defined
728 }
729 
730 void X86FrameLowering::emitStackProbeInlineGenericLoop(
733  uint64_t AlignOffset) const {
734  assert(Offset && "null offset");
735 
736  assert(!MBB.isLiveIn(X86::EFLAGS) &&
737  "Inline stack probe loop will clobber live EFLAGS.");
738 
739  const bool NeedsDwarfCFI = needsDwarfCFI(MF);
740  const bool HasFP = hasFP(MF);
741  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
742  const X86TargetLowering &TLI = *STI.getTargetLowering();
743  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
744  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
745 
746  if (AlignOffset) {
747  if (AlignOffset < StackProbeSize) {
748  // Perform a first smaller allocation followed by a probe.
749  BuildStackAdjustment(MBB, MBBI, DL, -AlignOffset, /*InEpilogue=*/false)
751 
752  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MovMIOpc))
754  StackPtr, false, 0)
755  .addImm(0)
757  NumFrameExtraProbe++;
758  Offset -= AlignOffset;
759  }
760  }
761 
762  // Synthesize a loop
763  NumFrameLoopProbe++;
764  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
765 
766  MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
767  MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
768 
770  MF.insert(MBBIter, testMBB);
771  MF.insert(MBBIter, tailMBB);
772 
773  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
774  : Is64Bit ? X86::R11D
775  : X86::EAX;
776 
777  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
778  .addReg(StackPtr)
780 
781  // save loop bound
782  {
783  const unsigned BoundOffset = alignDown(Offset, StackProbeSize);
784  const unsigned SUBOpc = getSUBriOpcode(Uses64BitFramePtr, BoundOffset);
785  BuildMI(MBB, MBBI, DL, TII.get(SUBOpc), FinalStackProbed)
786  .addReg(FinalStackProbed)
787  .addImm(BoundOffset)
789 
790  // while in the loop, use loop-invariant reg for CFI,
791  // instead of the stack pointer, which changes during the loop
792  if (!HasFP && NeedsDwarfCFI) {
793  // x32 uses the same DWARF register numbers as x86-64,
794  // so there isn't a register number for r11d, we must use r11 instead
795  const Register DwarfFinalStackProbed =
797  ? Register(getX86SubSuperRegister(FinalStackProbed, 64))
798  : FinalStackProbed;
799 
800  BuildCFI(MBB, MBBI, DL,
802  nullptr, TRI->getDwarfRegNum(DwarfFinalStackProbed, true)));
803  BuildCFI(MBB, MBBI, DL,
804  MCCFIInstruction::createAdjustCfaOffset(nullptr, BoundOffset));
805  }
806  }
807 
808  // allocate a page
809  BuildStackAdjustment(*testMBB, testMBB->end(), DL, -StackProbeSize,
810  /*InEpilogue=*/false)
812 
813  // touch the page
814  addRegOffset(BuildMI(testMBB, DL, TII.get(MovMIOpc))
816  StackPtr, false, 0)
817  .addImm(0)
819 
820  // cmp with stack pointer bound
821  BuildMI(testMBB, DL, TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
822  .addReg(StackPtr)
823  .addReg(FinalStackProbed)
825 
826  // jump
827  BuildMI(testMBB, DL, TII.get(X86::JCC_1))
828  .addMBB(testMBB)
831  testMBB->addSuccessor(testMBB);
832  testMBB->addSuccessor(tailMBB);
833 
834  // BB management
835  tailMBB->splice(tailMBB->end(), &MBB, MBBI, MBB.end());
837  MBB.addSuccessor(testMBB);
838 
839  // handle tail
840  const uint64_t TailOffset = Offset % StackProbeSize;
841  MachineBasicBlock::iterator TailMBBIter = tailMBB->begin();
842  if (TailOffset) {
843  BuildStackAdjustment(*tailMBB, TailMBBIter, DL, -TailOffset,
844  /*InEpilogue=*/false)
846  }
847 
848  // after the loop, switch back to stack pointer for CFI
849  if (!HasFP && NeedsDwarfCFI) {
850  // x32 uses the same DWARF register numbers as x86-64,
851  // so there isn't a register number for esp, we must use rsp instead
852  const Register DwarfStackPtr =
855  : Register(StackPtr);
856 
857  BuildCFI(*tailMBB, TailMBBIter, DL,
859  nullptr, TRI->getDwarfRegNum(DwarfStackPtr, true)));
860  }
861 
862  // Update Live In information
863  recomputeLiveIns(*testMBB);
864  recomputeLiveIns(*tailMBB);
865 }
866 
867 void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
869  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
870  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
871  assert(STI.is64Bit() && "different expansion needed for 32 bit");
872  assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
873  const TargetInstrInfo &TII = *STI.getInstrInfo();
874  const BasicBlock *LLVM_BB = MBB.getBasicBlock();
875 
876  assert(!MBB.isLiveIn(X86::EFLAGS) &&
877  "Inline stack probe loop will clobber live EFLAGS.");
878 
879  // RAX contains the number of bytes of desired stack adjustment.
880  // The handling here assumes this value has already been updated so as to
881  // maintain stack alignment.
882  //
883  // We need to exit with RSP modified by this amount and execute suitable
884  // page touches to notify the OS that we're growing the stack responsibly.
885  // All stack probing must be done without modifying RSP.
886  //
887  // MBB:
888  // SizeReg = RAX;
889  // ZeroReg = 0
890  // CopyReg = RSP
891  // Flags, TestReg = CopyReg - SizeReg
892  // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
893  // LimitReg = gs magic thread env access
894  // if FinalReg >= LimitReg goto ContinueMBB
895  // RoundBB:
896  // RoundReg = page address of FinalReg
897  // LoopMBB:
898  // LoopReg = PHI(LimitReg,ProbeReg)
899  // ProbeReg = LoopReg - PageSize
900  // [ProbeReg] = 0
901  // if (ProbeReg > RoundReg) goto LoopMBB
902  // ContinueMBB:
903  // RSP = RSP - RAX
904  // [rest of original MBB]
905 
906  // Set up the new basic blocks
907  MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
908  MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
909  MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
910 
911  MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
912  MF.insert(MBBIter, RoundMBB);
913  MF.insert(MBBIter, LoopMBB);
914  MF.insert(MBBIter, ContinueMBB);
915 
916  // Split MBB and move the tail portion down to ContinueMBB.
917  MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
918  ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
919  ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
920 
921  // Some useful constants
922  const int64_t ThreadEnvironmentStackLimit = 0x10;
923  const int64_t PageSize = 0x1000;
924  const int64_t PageMask = ~(PageSize - 1);
925 
926  // Registers we need. For the normal case we use virtual
927  // registers. For the prolog expansion we use RAX, RCX and RDX.
929  const TargetRegisterClass *RegClass = &X86::GR64RegClass;
930  const Register SizeReg = InProlog ? X86::RAX
931  : MRI.createVirtualRegister(RegClass),
932  ZeroReg = InProlog ? X86::RCX
933  : MRI.createVirtualRegister(RegClass),
934  CopyReg = InProlog ? X86::RDX
935  : MRI.createVirtualRegister(RegClass),
936  TestReg = InProlog ? X86::RDX
937  : MRI.createVirtualRegister(RegClass),
938  FinalReg = InProlog ? X86::RDX
939  : MRI.createVirtualRegister(RegClass),
940  RoundedReg = InProlog ? X86::RDX
941  : MRI.createVirtualRegister(RegClass),
942  LimitReg = InProlog ? X86::RCX
943  : MRI.createVirtualRegister(RegClass),
944  JoinReg = InProlog ? X86::RCX
945  : MRI.createVirtualRegister(RegClass),
946  ProbeReg = InProlog ? X86::RCX
947  : MRI.createVirtualRegister(RegClass);
948 
949  // SP-relative offsets where we can save RCX and RDX.
950  int64_t RCXShadowSlot = 0;
951  int64_t RDXShadowSlot = 0;
952 
953  // If inlining in the prolog, save RCX and RDX.
954  if (InProlog) {
955  // Compute the offsets. We need to account for things already
956  // pushed onto the stack at this point: return address, frame
957  // pointer (if used), and callee saves.
959  const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
960  const bool HasFP = hasFP(MF);
961 
962  // Check if we need to spill RCX and/or RDX.
963  // Here we assume that no earlier prologue instruction changes RCX and/or
964  // RDX, so checking the block live-ins is enough.
965  const bool IsRCXLiveIn = MBB.isLiveIn(X86::RCX);
966  const bool IsRDXLiveIn = MBB.isLiveIn(X86::RDX);
967  int64_t InitSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
968  // Assign the initial slot to both registers, then change RDX's slot if both
969  // need to be spilled.
970  if (IsRCXLiveIn)
971  RCXShadowSlot = InitSlot;
972  if (IsRDXLiveIn)
973  RDXShadowSlot = InitSlot;
974  if (IsRDXLiveIn && IsRCXLiveIn)
975  RDXShadowSlot += 8;
976  // Emit the saves if needed.
977  if (IsRCXLiveIn)
978  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
979  RCXShadowSlot)
980  .addReg(X86::RCX);
981  if (IsRDXLiveIn)
982  addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
983  RDXShadowSlot)
984  .addReg(X86::RDX);
985  } else {
986  // Not in the prolog. Copy RAX to a virtual reg.
987  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
988  }
989 
990  // Add code to MBB to check for overflow and set the new target stack pointer
991  // to zero if so.
992  BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
993  .addReg(ZeroReg, RegState::Undef)
994  .addReg(ZeroReg, RegState::Undef);
995  BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
996  BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
997  .addReg(CopyReg)
998  .addReg(SizeReg);
999  BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
1000  .addReg(TestReg)
1001  .addReg(ZeroReg)
1002  .addImm(X86::COND_B);
1003 
1004  // FinalReg now holds final stack pointer value, or zero if
1005  // allocation would overflow. Compare against the current stack
1006  // limit from the thread environment block. Note this limit is the
1007  // lowest touched page on the stack, not the point at which the OS
1008  // will cause an overflow exception, so this is just an optimization
1009  // to avoid unnecessarily touching pages that are below the current
1010  // SP but already committed to the stack by the OS.
1011  BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
1012  .addReg(0)
1013  .addImm(1)
1014  .addReg(0)
1015  .addImm(ThreadEnvironmentStackLimit)
1016  .addReg(X86::GS);
1017  BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
1018  // Jump if the desired stack pointer is at or above the stack limit.
1019  BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
1020 
1021  // Add code to roundMBB to round the final stack pointer to a page boundary.
1022  RoundMBB->addLiveIn(FinalReg);
1023  BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
1024  .addReg(FinalReg)
1025  .addImm(PageMask);
1026  BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
1027 
1028  // LimitReg now holds the current stack limit, RoundedReg page-rounded
1029  // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
1030  // and probe until we reach RoundedReg.
1031  if (!InProlog) {
1032  BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
1033  .addReg(LimitReg)
1034  .addMBB(RoundMBB)
1035  .addReg(ProbeReg)
1036  .addMBB(LoopMBB);
1037  }
1038 
1039  LoopMBB->addLiveIn(JoinReg);
1040  addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
1041  false, -PageSize);
1042 
1043  // Probe by storing a byte onto the stack.
1044  BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
1045  .addReg(ProbeReg)
1046  .addImm(1)
1047  .addReg(0)
1048  .addImm(0)
1049  .addReg(0)
1050  .addImm(0);
1051 
1052  LoopMBB->addLiveIn(RoundedReg);
1053  BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
1054  .addReg(RoundedReg)
1055  .addReg(ProbeReg);
1056  BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
1057 
1058  MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
1059 
1060  // If in prolog, restore RDX and RCX.
1061  if (InProlog) {
1062  if (RCXShadowSlot) // It means we spilled RCX in the prologue.
1063  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
1064  TII.get(X86::MOV64rm), X86::RCX),
1065  X86::RSP, false, RCXShadowSlot);
1066  if (RDXShadowSlot) // It means we spilled RDX in the prologue.
1067  addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
1068  TII.get(X86::MOV64rm), X86::RDX),
1069  X86::RSP, false, RDXShadowSlot);
1070  }
1071 
1072  // Now that the probing is done, add code to continueMBB to update
1073  // the stack pointer for real.
1074  ContinueMBB->addLiveIn(SizeReg);
1075  BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
1076  .addReg(X86::RSP)
1077  .addReg(SizeReg);
1078 
1079  // Add the control flow edges we need.
1080  MBB.addSuccessor(ContinueMBB);
1081  MBB.addSuccessor(RoundMBB);
1082  RoundMBB->addSuccessor(LoopMBB);
1083  LoopMBB->addSuccessor(ContinueMBB);
1084  LoopMBB->addSuccessor(LoopMBB);
1085 
1086  // Mark all the instructions added to the prolog as frame setup.
1087  if (InProlog) {
1088  for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
1089  BeforeMBBI->setFlag(MachineInstr::FrameSetup);
1090  }
1091  for (MachineInstr &MI : *RoundMBB) {
1092  MI.setFlag(MachineInstr::FrameSetup);
1093  }
1094  for (MachineInstr &MI : *LoopMBB) {
1095  MI.setFlag(MachineInstr::FrameSetup);
1096  }
1097  for (MachineInstr &MI :
1098  llvm::make_range(ContinueMBB->begin(), ContinueMBBI)) {
1099  MI.setFlag(MachineInstr::FrameSetup);
1100  }
1101  }
1102 }
1103 
1104 void X86FrameLowering::emitStackProbeCall(
1106  MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog,
1108  bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
1109 
1110  // FIXME: Add indirect thunk support and remove this.
1111  if (Is64Bit && IsLargeCodeModel && STI.useIndirectThunkCalls())
1112  report_fatal_error("Emitting stack probe calls on 64-bit with the large "
1113  "code model and indirect thunks not yet implemented.");
1114 
1115  assert(!MBB.isLiveIn(X86::EFLAGS) &&
1116  "Stack probe calls will clobber live EFLAGS.");
1117 
1118  unsigned CallOp;
1119  if (Is64Bit)
1120  CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
1121  else
1122  CallOp = X86::CALLpcrel32;
1123 
1125 
1127  MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
1128 
1129  // All current stack probes take AX and SP as input, clobber flags, and
1130  // preserve all registers. x86_64 probes leave RSP unmodified.
1131  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1132  // For the large code model, we have to call through a register. Use R11,
1133  // as it is scratch in all supported calling conventions.
1134  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
1136  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
1137  } else {
1138  CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
1140  }
1141 
1142  unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX;
1143  unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP;
1144  CI.addReg(AX, RegState::Implicit)
1148  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
1149 
1150  MachineInstr *ModInst = CI;
1151  if (STI.isTargetWin64() || !STI.isOSWindows()) {
1152  // MSVC x32's _chkstk and cygwin/mingw's _alloca adjust %esp themselves.
1153  // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
1154  // themselves. They also does not clobber %rax so we can reuse it when
1155  // adjusting %rsp.
1156  // All other platforms do not specify a particular ABI for the stack probe
1157  // function, so we arbitrarily define it to not adjust %esp/%rsp itself.
1158  ModInst =
1160  .addReg(SP)
1161  .addReg(AX);
1162  }
1163 
1164  // DebugInfo variable locations -- if there's an instruction number for the
1165  // allocation (i.e., DYN_ALLOC_*), substitute it for the instruction that
1166  // modifies SP.
1167  if (InstrNum) {
1168  if (STI.isTargetWin64() || !STI.isOSWindows()) {
1169  // Label destination operand of the subtract.
1170  MF.makeDebugValueSubstitution(*InstrNum,
1171  {ModInst->getDebugInstrNum(), 0});
1172  } else {
1173  // Label the call. The operand number is the penultimate operand, zero
1174  // based.
1175  unsigned SPDefOperand = ModInst->getNumOperands() - 2;
1177  *InstrNum, {ModInst->getDebugInstrNum(), SPDefOperand});
1178  }
1179  }
1180 
1181  if (InProlog) {
1182  // Apply the frame setup flag to all inserted instrs.
1183  for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
1184  ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
1185  }
1186 }
1187 
1188 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
1189  // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
1190  // and might require smaller successive adjustments.
1191  const uint64_t Win64MaxSEHOffset = 128;
1192  uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
1193  // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
1194  return SEHFrameOffset & -16;
1195 }
1196 
1197 // If we're forcing a stack realignment we can't rely on just the frame
1198 // info, we need to know the ABI stack alignment as well in case we
1199 // have a call out. Otherwise just make sure we have some alignment - we'll
1200 // go with the minimum SlotSize.
1201 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
1202  const MachineFrameInfo &MFI = MF.getFrameInfo();
1203  Align MaxAlign = MFI.getMaxAlign(); // Desired stack alignment.
1205  if (MF.getFunction().hasFnAttribute("stackrealign")) {
1206  if (MFI.hasCalls())
1207  MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1208  else if (MaxAlign < SlotSize)
1209  MaxAlign = Align(SlotSize);
1210  }
1211  return MaxAlign.value();
1212 }
1213 
1214 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
1216  const DebugLoc &DL, unsigned Reg,
1217  uint64_t MaxAlign) const {
1218  uint64_t Val = -MaxAlign;
1219  unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
1220 
1221  MachineFunction &MF = *MBB.getParent();
1222  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1223  const X86TargetLowering &TLI = *STI.getTargetLowering();
1224  const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
1225  const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
1226 
1227  // We want to make sure that (in worst case) less than StackProbeSize bytes
1228  // are not probed after the AND. This assumption is used in
1229  // emitStackProbeInlineGeneric.
1230  if (Reg == StackPtr && EmitInlineStackProbe && MaxAlign >= StackProbeSize) {
1231  {
1232  NumFrameLoopProbe++;
1233  MachineBasicBlock *entryMBB =
1235  MachineBasicBlock *headMBB =
1237  MachineBasicBlock *bodyMBB =
1239  MachineBasicBlock *footMBB =
1241 
1243  MF.insert(MBBIter, entryMBB);
1244  MF.insert(MBBIter, headMBB);
1245  MF.insert(MBBIter, bodyMBB);
1246  MF.insert(MBBIter, footMBB);
1247  const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
1248  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11
1249  : Is64Bit ? X86::R11D
1250  : X86::EAX;
1251 
1252  // Setup entry block
1253  {
1254 
1255  entryMBB->splice(entryMBB->end(), &MBB, MBB.begin(), MBBI);
1256  BuildMI(entryMBB, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
1257  .addReg(StackPtr)
1259  MachineInstr *MI =
1260  BuildMI(entryMBB, DL, TII.get(AndOp), FinalStackProbed)
1261  .addReg(FinalStackProbed)
1262  .addImm(Val)
1264 
1265  // The EFLAGS implicit def is dead.
1266  MI->getOperand(3).setIsDead();
1267 
1268  BuildMI(entryMBB, DL,
1269  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1270  .addReg(FinalStackProbed)
1271  .addReg(StackPtr)
1273  BuildMI(entryMBB, DL, TII.get(X86::JCC_1))
1274  .addMBB(&MBB)
1277  entryMBB->addSuccessor(headMBB);
1278  entryMBB->addSuccessor(&MBB);
1279  }
1280 
1281  // Loop entry block
1282 
1283  {
1284  const unsigned SUBOpc =
1285  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1286  BuildMI(headMBB, DL, TII.get(SUBOpc), StackPtr)
1287  .addReg(StackPtr)
1288  .addImm(StackProbeSize)
1290 
1291  BuildMI(headMBB, DL,
1292  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1293  .addReg(FinalStackProbed)
1294  .addReg(StackPtr)
1296 
1297  // jump
1298  BuildMI(headMBB, DL, TII.get(X86::JCC_1))
1299  .addMBB(footMBB)
1302 
1303  headMBB->addSuccessor(bodyMBB);
1304  headMBB->addSuccessor(footMBB);
1305  }
1306 
1307  // setup loop body
1308  {
1309  addRegOffset(BuildMI(bodyMBB, DL, TII.get(MovMIOpc))
1311  StackPtr, false, 0)
1312  .addImm(0)
1314 
1315  const unsigned SUBOpc =
1316  getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
1317  BuildMI(bodyMBB, DL, TII.get(SUBOpc), StackPtr)
1318  .addReg(StackPtr)
1319  .addImm(StackProbeSize)
1321 
1322  // cmp with stack pointer bound
1323  BuildMI(bodyMBB, DL,
1324  TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
1325  .addReg(FinalStackProbed)
1326  .addReg(StackPtr)
1328 
1329  // jump
1330  BuildMI(bodyMBB, DL, TII.get(X86::JCC_1))
1331  .addMBB(bodyMBB)
1334  bodyMBB->addSuccessor(bodyMBB);
1335  bodyMBB->addSuccessor(footMBB);
1336  }
1337 
1338  // setup loop footer
1339  {
1340  BuildMI(footMBB, DL, TII.get(TargetOpcode::COPY), StackPtr)
1341  .addReg(FinalStackProbed)
1343  addRegOffset(BuildMI(footMBB, DL, TII.get(MovMIOpc))
1345  StackPtr, false, 0)
1346  .addImm(0)
1348  footMBB->addSuccessor(&MBB);
1349  }
1350 
1351  recomputeLiveIns(*headMBB);
1352  recomputeLiveIns(*bodyMBB);
1353  recomputeLiveIns(*footMBB);
1355  }
1356  } else {
1357  MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1358  .addReg(Reg)
1359  .addImm(Val)
1361 
1362  // The EFLAGS implicit def is dead.
1363  MI->getOperand(3).setIsDead();
1364  }
1365 }
1366 
1368  // x86-64 (non Win64) has a 128 byte red zone which is guaranteed not to be
1369  // clobbered by any interrupt handler.
1370  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1371  "MF used frame lowering for wrong subtarget");
1372  const Function &Fn = MF.getFunction();
1373  const bool IsWin64CC = STI.isCallingConvWin64(Fn.getCallingConv());
1374  return Is64Bit && !IsWin64CC && !Fn.hasFnAttribute(Attribute::NoRedZone);
1375 }
1376 
1377 /// Return true if we need to use the restricted Windows x64 prologue and
1378 /// epilogue code patterns that can be described with WinCFI (.seh_*
1379 /// directives).
1380 bool X86FrameLowering::isWin64Prologue(const MachineFunction &MF) const {
1381  return MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1382 }
1383 
1384 bool X86FrameLowering::needsDwarfCFI(const MachineFunction &MF) const {
1385  return !isWin64Prologue(MF) && MF.needsFrameMoves();
1386 }
1387 
1388 /// emitPrologue - Push callee-saved registers onto the stack, which
1389 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
1390 /// space for local variables. Also emit labels used by the exception handler to
1391 /// generate the exception handling frames.
1392 
1393 /*
1394  Here's a gist of what gets emitted:
1395 
1396  ; Establish frame pointer, if needed
1397  [if needs FP]
1398  push %rbp
1399  .cfi_def_cfa_offset 16
1400  .cfi_offset %rbp, -16
1401  .seh_pushreg %rpb
1402  mov %rsp, %rbp
1403  .cfi_def_cfa_register %rbp
1404 
1405  ; Spill general-purpose registers
1406  [for all callee-saved GPRs]
1407  pushq %<reg>
1408  [if not needs FP]
1409  .cfi_def_cfa_offset (offset from RETADDR)
1410  .seh_pushreg %<reg>
1411 
1412  ; If the required stack alignment > default stack alignment
1413  ; rsp needs to be re-aligned. This creates a "re-alignment gap"
1414  ; of unknown size in the stack frame.
1415  [if stack needs re-alignment]
1416  and $MASK, %rsp
1417 
1418  ; Allocate space for locals
1419  [if target is Windows and allocated space > 4096 bytes]
1420  ; Windows needs special care for allocations larger
1421  ; than one page.
1422  mov $NNN, %rax
1423  call ___chkstk_ms/___chkstk
1424  sub %rax, %rsp
1425  [else]
1426  sub $NNN, %rsp
1427 
1428  [if needs FP]
1429  .seh_stackalloc (size of XMM spill slots)
1430  .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
1431  [else]
1432  .seh_stackalloc NNN
1433 
1434  ; Spill XMMs
1435  ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
1436  ; they may get spilled on any platform, if the current function
1437  ; calls @llvm.eh.unwind.init
1438  [if needs FP]
1439  [for all callee-saved XMM registers]
1440  movaps %<xmm reg>, -MMM(%rbp)
1441  [for all callee-saved XMM registers]
1442  .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
1443  ; i.e. the offset relative to (%rbp - SEHFrameOffset)
1444  [else]
1445  [for all callee-saved XMM registers]
1446  movaps %<xmm reg>, KKK(%rsp)
1447  [for all callee-saved XMM registers]
1448  .seh_savexmm %<xmm reg>, KKK
1449 
1450  .seh_endprologue
1451 
1452  [if needs base pointer]
1453  mov %rsp, %rbx
1454  [if needs to restore base pointer]
1455  mov %rsp, -MMM(%rbp)
1456 
1457  ; Emit CFI info
1458  [if needs FP]
1459  [for all callee-saved registers]
1460  .cfi_offset %<reg>, (offset from %rbp)
1461  [else]
1462  .cfi_def_cfa_offset (offset from RETADDR)
1463  [for all callee-saved registers]
1464  .cfi_offset %<reg>, (offset from %rsp)
1465 
1466  Notes:
1467  - .seh directives are emitted only for Windows 64 ABI
1468  - .cv_fpo directives are emitted on win32 when emitting CodeView
1469  - .cfi directives are emitted for all other ABIs
1470  - for 32-bit code, substitute %e?? registers for %r??
1471 */
1472 
1474  MachineBasicBlock &MBB) const {
1475  assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
1476  "MF used frame lowering for wrong subtarget");
1478  MachineFrameInfo &MFI = MF.getFrameInfo();
1479  const Function &Fn = MF.getFunction();
1480  MachineModuleInfo &MMI = MF.getMMI();
1482  uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
1483  uint64_t StackSize = MFI.getStackSize(); // Number of bytes to allocate.
1484  bool IsFunclet = MBB.isEHFuncletEntry();
1485  EHPersonality Personality = EHPersonality::Unknown;
1486  if (Fn.hasPersonalityFn())
1487  Personality = classifyEHPersonality(Fn.getPersonalityFn());
1488  bool FnHasClrFunclet =
1489  MF.hasEHFunclets() && Personality == EHPersonality::CoreCLR;
1490  bool IsClrFunclet = IsFunclet && FnHasClrFunclet;
1491  bool HasFP = hasFP(MF);
1492  bool IsWin64Prologue = isWin64Prologue(MF);
1493  bool NeedsWin64CFI = IsWin64Prologue && Fn.needsUnwindTableEntry();
1494  // FIXME: Emit FPO data for EH funclets.
1495  bool NeedsWinFPO =
1496  !IsFunclet && STI.isTargetWin32() && MMI.getModule()->getCodeViewFlag();
1497  bool NeedsWinCFI = NeedsWin64CFI || NeedsWinFPO;
1498  bool NeedsDwarfCFI = needsDwarfCFI(MF);
1499  Register FramePtr = TRI->getFrameRegister(MF);
1500  const Register MachineFramePtr =
1502  ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
1503  Register BasePtr = TRI->getBaseRegister();
1504  bool HasWinCFI = false;
1505 
1506  // Debug location must be unknown since the first debug location is used
1507  // to determine the end of the prologue.
1508  DebugLoc DL;
1509 
1510  // Space reserved for stack-based arguments when making a (ABI-guaranteed)
1511  // tail call.
1512  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
1513  if (TailCallArgReserveSize && IsWin64Prologue)
1514  report_fatal_error("Can't handle guaranteed tail call under win64 yet");
1515 
1516  const bool EmitStackProbeCall =
1518  unsigned StackProbeSize = STI.getTargetLowering()->getStackProbeSize(MF);
1519 
1520  if (HasFP && X86FI->hasSwiftAsyncContext()) {
1521  switch (MF.getTarget().Options.SwiftAsyncFramePointer) {
1524  // The special symbol below is absolute and has a *value* suitable to be
1525  // combined with the frame pointer directly.
1526  BuildMI(MBB, MBBI, DL, TII.get(X86::OR64rm), MachineFramePtr)
1527  .addUse(MachineFramePtr)
1528  .addUse(X86::RIP)
1529  .addImm(1)
1530  .addUse(X86::NoRegister)
1531  .addExternalSymbol("swift_async_extendedFramePointerFlags",
1533  .addUse(X86::NoRegister);
1534  break;
1535  }
1536  [[fallthrough]];
1537 
1539  BuildMI(MBB, MBBI, DL, TII.get(X86::BTS64ri8), MachineFramePtr)
1540  .addUse(MachineFramePtr)
1541  .addImm(60)
1543  break;
1544 
1546  break;
1547  }
1548  }
1549 
1550  // Re-align the stack on 64-bit if the x86-interrupt calling convention is
1551  // used and an error code was pushed, since the x86-64 ABI requires a 16-byte
1552  // stack alignment.
1553  if (Fn.getCallingConv() == CallingConv::X86_INTR && Is64Bit &&
1554  Fn.arg_size() == 2) {
1555  StackSize += 8;
1556  MFI.setStackSize(StackSize);
1557  emitSPUpdate(MBB, MBBI, DL, -8, /*InEpilogue=*/false);
1558  }
1559 
1560  // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
1561  // function, and use up to 128 bytes of stack space, don't have a frame
1562  // pointer, calls, or dynamic alloca then we do not need to adjust the
1563  // stack pointer (we fit in the Red Zone). We also check that we don't
1564  // push and pop from the stack.
1565  if (has128ByteRedZone(MF) && !TRI->hasStackRealignment(MF) &&
1566  !MFI.hasVarSizedObjects() && // No dynamic alloca.
1567  !MFI.adjustsStack() && // No calls.
1568  !EmitStackProbeCall && // No stack probes.
1569  !MFI.hasCopyImplyingStackAdjustment() && // Don't push and pop.
1570  !MF.shouldSplitStack()) { // Regular stack
1571  uint64_t MinSize =
1572  X86FI->getCalleeSavedFrameSize() - X86FI->getTCReturnAddrDelta();
1573  if (HasFP) MinSize += SlotSize;
1574  X86FI->setUsesRedZone(MinSize > 0 || StackSize > 0);
1575  StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
1576  MFI.setStackSize(StackSize);
1577  }
1578 
1579  // Insert stack pointer adjustment for later moving of return addr. Only
1580  // applies to tail call optimized functions where the callee argument stack
1581  // size is bigger than the callers.
1582  if (TailCallArgReserveSize != 0) {
1583  BuildStackAdjustment(MBB, MBBI, DL, -(int)TailCallArgReserveSize,
1584  /*InEpilogue=*/false)
1586  }
1587 
1588  // Mapping for machine moves:
1589  //
1590  // DST: VirtualFP AND
1591  // SRC: VirtualFP => DW_CFA_def_cfa_offset
1592  // ELSE => DW_CFA_def_cfa
1593  //
1594  // SRC: VirtualFP AND
1595  // DST: Register => DW_CFA_def_cfa_register
1596  //
1597  // ELSE
1598  // OFFSET < 0 => DW_CFA_offset_extended_sf
1599  // REG < 64 => DW_CFA_offset + Reg
1600  // ELSE => DW_CFA_offset_extended
1601 
1602  uint64_t NumBytes = 0;
1603  int stackGrowth = -SlotSize;
1604 
1605  // Find the funclet establisher parameter
1606  Register Establisher = X86::NoRegister;
1607  if (IsClrFunclet)
1608  Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
1609  else if (IsFunclet)
1610  Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
1611 
1612  if (IsWin64Prologue && IsFunclet && !IsClrFunclet) {
1613  // Immediately spill establisher into the home slot.
1614  // The runtime cares about this.
1615  // MOV64mr %rdx, 16(%rsp)
1616  unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1617  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1618  .addReg(Establisher)
1620  MBB.addLiveIn(Establisher);
1621  }
1622 
1623  if (HasFP) {
1624  assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
1625 
1626  // Calculate required stack adjustment.
1627  uint64_t FrameSize = StackSize - SlotSize;
1628  // If required, include space for extra hidden slot for stashing base pointer.
1629  if (X86FI->getRestoreBasePointer())
1630  FrameSize += SlotSize;
1631 
1632  NumBytes = FrameSize -
1633  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1634 
1635  // Callee-saved registers are pushed on stack before the stack is realigned.
1636  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
1637  NumBytes = alignTo(NumBytes, MaxAlign);
1638 
1639  // Save EBP/RBP into the appropriate stack slot.
1640  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1641  .addReg(MachineFramePtr, RegState::Kill)
1643 
1644  if (NeedsDwarfCFI) {
1645  // Mark the place where EBP/RBP was saved.
1646  // Define the current CFA rule to use the provided offset.
1647  assert(StackSize);
1648  BuildCFI(MBB, MBBI, DL,
1649  MCCFIInstruction::cfiDefCfaOffset(nullptr, -2 * stackGrowth),
1651 
1652  // Change the rule for the FramePtr to be an "offset" rule.
1653  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1654  BuildCFI(MBB, MBBI, DL,
1655  MCCFIInstruction::createOffset(nullptr, DwarfFramePtr,
1656  2 * stackGrowth),
1658  }
1659 
1660  if (NeedsWinCFI) {
1661  HasWinCFI = true;
1662  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1663  .addImm(FramePtr)
1665  }
1666 
1667  if (!IsFunclet) {
1668  if (X86FI->hasSwiftAsyncContext()) {
1669  const auto &Attrs = MF.getFunction().getAttributes();
1670 
1671  // Before we update the live frame pointer we have to ensure there's a
1672  // valid (or null) asynchronous context in its slot just before FP in
1673  // the frame record, so store it now.
1674  if (Attrs.hasAttrSomewhere(Attribute::SwiftAsync)) {
1675  // We have an initial context in r14, store it just before the frame
1676  // pointer.
1677  MBB.addLiveIn(X86::R14);
1678  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1679  .addReg(X86::R14)
1681  } else {
1682  // No initial context, store null so that there's no pointer that
1683  // could be misused.
1684  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64i8))
1685  .addImm(0)
1687  }
1688 
1689  if (NeedsWinCFI) {
1690  HasWinCFI = true;
1691  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1692  .addImm(X86::R14)
1694  }
1695 
1696  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr)
1697  .addUse(X86::RSP)
1698  .addImm(1)
1699  .addUse(X86::NoRegister)
1700  .addImm(8)
1701  .addUse(X86::NoRegister)
1703  BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri8), X86::RSP)
1704  .addUse(X86::RSP)
1705  .addImm(8)
1707  }
1708 
1709  if (!IsWin64Prologue && !IsFunclet) {
1710  // Update EBP with the new base value.
1711  if (!X86FI->hasSwiftAsyncContext())
1712  BuildMI(MBB, MBBI, DL,
1713  TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1714  FramePtr)
1715  .addReg(StackPtr)
1717 
1718  if (NeedsDwarfCFI) {
1719  // Mark effective beginning of when frame pointer becomes valid.
1720  // Define the current CFA to use the EBP/RBP register.
1721  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1722  BuildCFI(
1723  MBB, MBBI, DL,
1724  MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr),
1726  }
1727 
1728  if (NeedsWinFPO) {
1729  // .cv_fpo_setframe $FramePtr
1730  HasWinCFI = true;
1731  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1732  .addImm(FramePtr)
1733  .addImm(0)
1735  }
1736  }
1737  }
1738  } else {
1739  assert(!IsFunclet && "funclets without FPs not yet implemented");
1740  NumBytes = StackSize -
1741  (X86FI->getCalleeSavedFrameSize() + TailCallArgReserveSize);
1742  }
1743 
1744  // Update the offset adjustment, which is mainly used by codeview to translate
1745  // from ESP to VFRAME relative local variable offsets.
1746  if (!IsFunclet) {
1747  if (HasFP && TRI->hasStackRealignment(MF))
1748  MFI.setOffsetAdjustment(-NumBytes);
1749  else
1750  MFI.setOffsetAdjustment(-StackSize);
1751  }
1752 
1753  // For EH funclets, only allocate enough space for outgoing calls. Save the
1754  // NumBytes value that we would've used for the parent frame.
1755  unsigned ParentFrameNumBytes = NumBytes;
1756  if (IsFunclet)
1757  NumBytes = getWinEHFuncletFrameSize(MF);
1758 
1759  // Skip the callee-saved push instructions.
1760  bool PushedRegs = false;
1761  int StackOffset = 2 * stackGrowth;
1762 
1763  while (MBBI != MBB.end() &&
1764  MBBI->getFlag(MachineInstr::FrameSetup) &&
1765  (MBBI->getOpcode() == X86::PUSH32r ||
1766  MBBI->getOpcode() == X86::PUSH64r)) {
1767  PushedRegs = true;
1768  Register Reg = MBBI->getOperand(0).getReg();
1769  ++MBBI;
1770 
1771  if (!HasFP && NeedsDwarfCFI) {
1772  // Mark callee-saved push instruction.
1773  // Define the current CFA rule to use the provided offset.
1774  assert(StackSize);
1775  BuildCFI(MBB, MBBI, DL,
1778  StackOffset += stackGrowth;
1779  }
1780 
1781  if (NeedsWinCFI) {
1782  HasWinCFI = true;
1783  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1784  .addImm(Reg)
1786  }
1787  }
1788 
1789  // Realign stack after we pushed callee-saved registers (so that we'll be
1790  // able to calculate their offsets from the frame pointer).
1791  // Don't do this for Win64, it needs to realign the stack after the prologue.
1792  if (!IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF)) {
1793  assert(HasFP && "There should be a frame pointer if stack is realigned.");
1794  BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1795 
1796  if (NeedsWinCFI) {
1797  HasWinCFI = true;
1798  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1799  .addImm(MaxAlign)
1801  }
1802  }
1803 
1804  // If there is an SUB32ri of ESP immediately before this instruction, merge
1805  // the two. This can be the case when tail call elimination is enabled and
1806  // the callee has more arguments then the caller.
1807  NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1808 
1809  // Adjust stack pointer: ESP -= numbytes.
1810 
1811  // Windows and cygwin/mingw require a prologue helper routine when allocating
1812  // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1813  // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1814  // stack and adjust the stack pointer in one go. The 64-bit version of
1815  // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1816  // responsible for adjusting the stack pointer. Touching the stack at 4K
1817  // increments is necessary to ensure that the guard pages used by the OS
1818  // virtual memory manager are allocated in correct sequence.
1819  uint64_t AlignedNumBytes = NumBytes;
1820  if (IsWin64Prologue && !IsFunclet && TRI->hasStackRealignment(MF))
1821  AlignedNumBytes = alignTo(AlignedNumBytes, MaxAlign);
1822  if (AlignedNumBytes >= StackProbeSize && EmitStackProbeCall) {
1823  assert(!X86FI->getUsesRedZone() &&
1824  "The Red Zone is not accounted for in stack probes");
1825 
1826  // Check whether EAX is livein for this block.
1827  bool isEAXAlive = isEAXLiveIn(MBB);
1828 
1829  if (isEAXAlive) {
1830  if (Is64Bit) {
1831  // Save RAX
1832  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1833  .addReg(X86::RAX, RegState::Kill)
1835  } else {
1836  // Save EAX
1837  BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1840  }
1841  }
1842 
1843  if (Is64Bit) {
1844  // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1845  // Function prologue is responsible for adjusting the stack pointer.
1846  int64_t Alloc = isEAXAlive ? NumBytes - 8 : NumBytes;
1847  BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Alloc)), X86::RAX)
1848  .addImm(Alloc)
1850  } else {
1851  // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1852  // We'll also use 4 already allocated bytes for EAX.
1853  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1854  .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1856  }
1857 
1858  // Call __chkstk, __chkstk_ms, or __alloca.
1859  emitStackProbe(MF, MBB, MBBI, DL, true);
1860 
1861  if (isEAXAlive) {
1862  // Restore RAX/EAX
1863  MachineInstr *MI;
1864  if (Is64Bit)
1865  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1866  StackPtr, false, NumBytes - 8);
1867  else
1868  MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1869  StackPtr, false, NumBytes - 4);
1870  MI->setFlag(MachineInstr::FrameSetup);
1871  MBB.insert(MBBI, MI);
1872  }
1873  } else if (NumBytes) {
1874  emitSPUpdate(MBB, MBBI, DL, -(int64_t)NumBytes, /*InEpilogue=*/false);
1875  }
1876 
1877  if (NeedsWinCFI && NumBytes) {
1878  HasWinCFI = true;
1879  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1880  .addImm(NumBytes)
1882  }
1883 
1884  int SEHFrameOffset = 0;
1885  unsigned SPOrEstablisher;
1886  if (IsFunclet) {
1887  if (IsClrFunclet) {
1888  // The establisher parameter passed to a CLR funclet is actually a pointer
1889  // to the (mostly empty) frame of its nearest enclosing funclet; we have
1890  // to find the root function establisher frame by loading the PSPSym from
1891  // the intermediate frame.
1892  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1893  MachinePointerInfo NoInfo;
1894  MBB.addLiveIn(Establisher);
1895  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1896  Establisher, false, PSPSlotOffset)
1899  ;
1900  // Save the root establisher back into the current funclet's (mostly
1901  // empty) frame, in case a sub-funclet or the GC needs it.
1902  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1903  false, PSPSlotOffset)
1904  .addReg(Establisher)
1906  NoInfo,
1908  SlotSize, Align(SlotSize)));
1909  }
1910  SPOrEstablisher = Establisher;
1911  } else {
1912  SPOrEstablisher = StackPtr;
1913  }
1914 
1915  if (IsWin64Prologue && HasFP) {
1916  // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1917  // this calculation on the incoming establisher, which holds the value of
1918  // RSP from the parent frame at the end of the prologue.
1919  SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1920  if (SEHFrameOffset)
1921  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1922  SPOrEstablisher, false, SEHFrameOffset);
1923  else
1924  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1925  .addReg(SPOrEstablisher);
1926 
1927  // If this is not a funclet, emit the CFI describing our frame pointer.
1928  if (NeedsWinCFI && !IsFunclet) {
1929  assert(!NeedsWinFPO && "this setframe incompatible with FPO data");
1930  HasWinCFI = true;
1931  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1932  .addImm(FramePtr)
1933  .addImm(SEHFrameOffset)
1935  if (isAsynchronousEHPersonality(Personality))
1936  MF.getWinEHFuncInfo()->SEHSetFrameOffset = SEHFrameOffset;
1937  }
1938  } else if (IsFunclet && STI.is32Bit()) {
1939  // Reset EBP / ESI to something good for funclets.
1941  // If we're a catch funclet, we can be returned to via catchret. Save ESP
1942  // into the registration node so that the runtime will restore it for us.
1943  if (!MBB.isCleanupFuncletEntry()) {
1944  assert(Personality == EHPersonality::MSVC_CXX);
1945  Register FrameReg;
1946  int FI = MF.getWinEHFuncInfo()->EHRegNodeFrameIndex;
1947  int64_t EHRegOffset = getFrameIndexReference(MF, FI, FrameReg).getFixed();
1948  // ESP is the first field, so no extra displacement is needed.
1949  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1950  false, EHRegOffset)
1951  .addReg(X86::ESP);
1952  }
1953  }
1954 
1955  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1956  const MachineInstr &FrameInstr = *MBBI;
1957  ++MBBI;
1958 
1959  if (NeedsWinCFI) {
1960  int FI;
1961  if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1962  if (X86::FR64RegClass.contains(Reg)) {
1963  int Offset;
1964  Register IgnoredFrameReg;
1965  if (IsWin64Prologue && IsFunclet)
1966  Offset = getWin64EHFrameIndexRef(MF, FI, IgnoredFrameReg);
1967  else
1968  Offset =
1969  getFrameIndexReference(MF, FI, IgnoredFrameReg).getFixed() +
1970  SEHFrameOffset;
1971 
1972  HasWinCFI = true;
1973  assert(!NeedsWinFPO && "SEH_SaveXMM incompatible with FPO data");
1974  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1975  .addImm(Reg)
1976  .addImm(Offset)
1978  }
1979  }
1980  }
1981  }
1982 
1983  if (NeedsWinCFI && HasWinCFI)
1984  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1986 
1987  if (FnHasClrFunclet && !IsFunclet) {
1988  // Save the so-called Initial-SP (i.e. the value of the stack pointer
1989  // immediately after the prolog) into the PSPSlot so that funclets
1990  // and the GC can recover it.
1991  unsigned PSPSlotOffset = getPSPSlotOffsetFromSP(MF);
1992  auto PSPInfo = MachinePointerInfo::getFixedStack(
1993  MF, MF.getWinEHFuncInfo()->PSPSymFrameIdx);
1994  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1995  PSPSlotOffset)
1996  .addReg(StackPtr)
1999  SlotSize, Align(SlotSize)));
2000  }
2001 
2002  // Realign stack after we spilled callee-saved registers (so that we'll be
2003  // able to calculate their offsets from the frame pointer).
2004  // Win64 requires aligning the stack after the prologue.
2005  if (IsWin64Prologue && TRI->hasStackRealignment(MF)) {
2006  assert(HasFP && "There should be a frame pointer if stack is realigned.");
2007  BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
2008  }
2009 
2010  // We already dealt with stack realignment and funclets above.
2011  if (IsFunclet && STI.is32Bit())
2012  return;
2013 
2014  // If we need a base pointer, set it up here. It's whatever the value
2015  // of the stack pointer is at this point. Any variable size objects
2016  // will be allocated after this, so we can still use the base pointer
2017  // to reference locals.
2018  if (TRI->hasBasePointer(MF)) {
2019  // Update the base pointer with the current stack pointer.
2020  unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
2021  BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
2022  .addReg(SPOrEstablisher)
2024  if (X86FI->getRestoreBasePointer()) {
2025  // Stash value of base pointer. Saving RSP instead of EBP shortens
2026  // dependence chain. Used by SjLj EH.
2027  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
2028  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
2029  FramePtr, true, X86FI->getRestoreBasePointerOffset())
2030  .addReg(SPOrEstablisher)
2032  }
2033 
2034  if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
2035  // Stash the value of the frame pointer relative to the base pointer for
2036  // Win32 EH. This supports Win32 EH, which does the inverse of the above:
2037  // it recovers the frame pointer from the base pointer rather than the
2038  // other way around.
2039  unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
2040  Register UsedReg;
2041  int Offset =
2042  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
2043  .getFixed();
2044  assert(UsedReg == BasePtr);
2045  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
2046  .addReg(FramePtr)
2048  }
2049  }
2050 
2051  if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
2052  // Mark end of stack pointer adjustment.
2053  if (!HasFP && NumBytes) {
2054  // Define the current CFA rule to use the provided offset.
2055  assert(StackSize);
2056  BuildCFI(
2057  MBB, MBBI, DL,
2058  MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize - stackGrowth),
2060  }
2061 
2062  // Emit DWARF info specifying the offsets of the callee-saved registers.
2064  }
2065 
2066  // X86 Interrupt handling function cannot assume anything about the direction
2067  // flag (DF in EFLAGS register). Clear this flag by creating "cld" instruction
2068  // in each prologue of interrupt handler function.
2069  //
2070  // FIXME: Create "cld" instruction only in these cases:
2071  // 1. The interrupt handling function uses any of the "rep" instructions.
2072  // 2. Interrupt handling function calls another function.
2073  //
2075  BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
2077 
2078  // At this point we know if the function has WinCFI or not.
2079  MF.setHasWinCFI(HasWinCFI);
2080 }
2081 
2083  const MachineFunction &MF) const {
2084  // We can't use LEA instructions for adjusting the stack pointer if we don't
2085  // have a frame pointer in the Win64 ABI. Only ADD instructions may be used
2086  // to deallocate the stack.
2087  // This means that we can use LEA for SP in two situations:
2088  // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
2089  // 2. We *have* a frame pointer which means we are permitted to use LEA.
2090  return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
2091 }
2092 
2094  switch (MI.getOpcode()) {
2095  case X86::CATCHRET:
2096  case X86::CLEANUPRET:
2097  return true;
2098  default:
2099  return false;
2100  }
2101  llvm_unreachable("impossible");
2102 }
2103 
2104 // CLR funclets use a special "Previous Stack Pointer Symbol" slot on the
2105 // stack. It holds a pointer to the bottom of the root function frame. The
2106 // establisher frame pointer passed to a nested funclet may point to the
2107 // (mostly empty) frame of its parent funclet, but it will need to find
2108 // the frame of the root function to access locals. To facilitate this,
2109 // every funclet copies the pointer to the bottom of the root function
2110 // frame into a PSPSym slot in its own (mostly empty) stack frame. Using the
2111 // same offset for the PSPSym in the root function frame that's used in the
2112 // funclets' frames allows each funclet to dynamically accept any ancestor
2113 // frame as its establisher argument (the runtime doesn't guarantee the
2114 // immediate parent for some reason lost to history), and also allows the GC,
2115 // which uses the PSPSym for some bookkeeping, to find it in any funclet's
2116 // frame with only a single offset reported for the entire method.
2117 unsigned
2118 X86FrameLowering::getPSPSlotOffsetFromSP(const MachineFunction &MF) const {
2119  const WinEHFuncInfo &Info = *MF.getWinEHFuncInfo();
2120  Register SPReg;
2121  int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg,
2122  /*IgnoreSPUpdates*/ true)
2123  .getFixed();
2124  assert(Offset >= 0 && SPReg == TRI->getStackRegister());
2125  return static_cast<unsigned>(Offset);
2126 }
2127 
2128 unsigned
2129 X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
2131  // This is the size of the pushed CSRs.
2132  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2133  // This is the size of callee saved XMMs.
2134  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2135  unsigned XMMSize = WinEHXMMSlotInfo.size() *
2136  TRI->getSpillSize(X86::VR128RegClass);
2137  // This is the amount of stack a funclet needs to allocate.
2138  unsigned UsedSize;
2139  EHPersonality Personality =
2141  if (Personality == EHPersonality::CoreCLR) {
2142  // CLR funclets need to hold enough space to include the PSPSym, at the
2143  // same offset from the stack pointer (immediately after the prolog) as it
2144  // resides at in the main function.
2145  UsedSize = getPSPSlotOffsetFromSP(MF) + SlotSize;
2146  } else {
2147  // Other funclets just need enough stack for outgoing call arguments.
2148  UsedSize = MF.getFrameInfo().getMaxCallFrameSize();
2149  }
2150  // RBP is not included in the callee saved register block. After pushing RBP,
2151  // everything is 16 byte aligned. Everything we allocate before an outgoing
2152  // call must also be 16 byte aligned.
2153  unsigned FrameSizeMinusRBP = alignTo(CSSize + UsedSize, getStackAlign());
2154  // Subtract out the size of the callee saved registers. This is how much stack
2155  // each funclet will allocate.
2156  return FrameSizeMinusRBP + XMMSize - CSSize;
2157 }
2158 
2159 static bool isTailCallOpcode(unsigned Opc) {
2160  return Opc == X86::TCRETURNri || Opc == X86::TCRETURNdi ||
2161  Opc == X86::TCRETURNmi ||
2162  Opc == X86::TCRETURNri64 || Opc == X86::TCRETURNdi64 ||
2163  Opc == X86::TCRETURNmi64;
2164 }
2165 
2167  MachineBasicBlock &MBB) const {
2168  const MachineFrameInfo &MFI = MF.getFrameInfo();
2172  DebugLoc DL;
2173  if (MBBI != MBB.end())
2174  DL = MBBI->getDebugLoc();
2175  // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
2176  const bool Is64BitILP32 = STI.isTarget64BitILP32();
2177  Register FramePtr = TRI->getFrameRegister(MF);
2178  Register MachineFramePtr =
2179  Is64BitILP32 ? Register(getX86SubSuperRegister(FramePtr, 64)) : FramePtr;
2180 
2181  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2182  bool NeedsWin64CFI =
2183  IsWin64Prologue && MF.getFunction().needsUnwindTableEntry();
2184  bool IsFunclet = MBBI == MBB.end() ? false : isFuncletReturnInstr(*MBBI);
2185 
2186  // Get the number of bytes to allocate from the FrameInfo.
2187  uint64_t StackSize = MFI.getStackSize();
2188  uint64_t MaxAlign = calculateMaxStackAlign(MF);
2189  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2190  unsigned TailCallArgReserveSize = -X86FI->getTCReturnAddrDelta();
2191  bool HasFP = hasFP(MF);
2192  uint64_t NumBytes = 0;
2193 
2194  bool NeedsDwarfCFI = (!MF.getTarget().getTargetTriple().isOSDarwin() &&
2195  !MF.getTarget().getTargetTriple().isOSWindows()) &&
2196  MF.needsFrameMoves();
2197 
2198  if (IsFunclet) {
2199  assert(HasFP && "EH funclets without FP not yet implemented");
2200  NumBytes = getWinEHFuncletFrameSize(MF);
2201  } else if (HasFP) {
2202  // Calculate required stack adjustment.
2203  uint64_t FrameSize = StackSize - SlotSize;
2204  NumBytes = FrameSize - CSSize - TailCallArgReserveSize;
2205 
2206  // Callee-saved registers were pushed on stack before the stack was
2207  // realigned.
2208  if (TRI->hasStackRealignment(MF) && !IsWin64Prologue)
2209  NumBytes = alignTo(FrameSize, MaxAlign);
2210  } else {
2211  NumBytes = StackSize - CSSize - TailCallArgReserveSize;
2212  }
2213  uint64_t SEHStackAllocAmt = NumBytes;
2214 
2215  // AfterPop is the position to insert .cfi_restore.
2216  MachineBasicBlock::iterator AfterPop = MBBI;
2217  if (HasFP) {
2218  if (X86FI->hasSwiftAsyncContext()) {
2219  // Discard the context.
2220  int Offset = 16 + mergeSPUpdates(MBB, MBBI, true);
2221  emitSPUpdate(MBB, MBBI, DL, Offset, /*InEpilogue*/true);
2222  }
2223  // Pop EBP.
2224  BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
2225  MachineFramePtr)
2227 
2228  // We need to reset FP to its untagged state on return. Bit 60 is currently
2229  // used to show the presence of an extended frame.
2230  if (X86FI->hasSwiftAsyncContext()) {
2231  BuildMI(MBB, MBBI, DL, TII.get(X86::BTR64ri8),
2232  MachineFramePtr)
2233  .addUse(MachineFramePtr)
2234  .addImm(60)
2236  }
2237 
2238  if (NeedsDwarfCFI) {
2239  unsigned DwarfStackPtr =
2240  TRI->getDwarfRegNum(Is64Bit ? X86::RSP : X86::ESP, true);
2241  BuildCFI(MBB, MBBI, DL,
2242  MCCFIInstruction::cfiDefCfa(nullptr, DwarfStackPtr, SlotSize),
2244  if (!MBB.succ_empty() && !MBB.isReturnBlock()) {
2245  unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
2246  BuildCFI(MBB, AfterPop, DL,
2247  MCCFIInstruction::createRestore(nullptr, DwarfFramePtr),
2249  --MBBI;
2250  --AfterPop;
2251  }
2252  --MBBI;
2253  }
2254  }
2255 
2256  MachineBasicBlock::iterator FirstCSPop = MBBI;
2257  // Skip the callee-saved pop instructions.
2258  while (MBBI != MBB.begin()) {
2259  MachineBasicBlock::iterator PI = std::prev(MBBI);
2260  unsigned Opc = PI->getOpcode();
2261 
2262  if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
2263  if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2264  (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2265  (Opc != X86::BTR64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)) &&
2266  (Opc != X86::ADD64ri8 || !PI->getFlag(MachineInstr::FrameDestroy)))
2267  break;
2268  FirstCSPop = PI;
2269  }
2270 
2271  --MBBI;
2272  }
2273  MBBI = FirstCSPop;
2274 
2275  if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
2276  emitCatchRetReturnValue(MBB, FirstCSPop, &*Terminator);
2277 
2278  if (MBBI != MBB.end())
2279  DL = MBBI->getDebugLoc();
2280  // If there is an ADD32ri or SUB32ri of ESP immediately before this
2281  // instruction, merge the two instructions.
2282  if (NumBytes || MFI.hasVarSizedObjects())
2283  NumBytes += mergeSPUpdates(MBB, MBBI, true);
2284 
2285  // If dynamic alloca is used, then reset esp to point to the last callee-saved
2286  // slot before popping them off! Same applies for the case, when stack was
2287  // realigned. Don't do this if this was a funclet epilogue, since the funclets
2288  // will not do realignment or dynamic stack allocation.
2289  if (((TRI->hasStackRealignment(MF)) || MFI.hasVarSizedObjects()) &&
2290  !IsFunclet) {
2291  if (TRI->hasStackRealignment(MF))
2292  MBBI = FirstCSPop;
2293  unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
2294  uint64_t LEAAmount =
2295  IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
2296 
2297  if (X86FI->hasSwiftAsyncContext())
2298  LEAAmount -= 16;
2299 
2300  // There are only two legal forms of epilogue:
2301  // - add SEHAllocationSize, %rsp
2302  // - lea SEHAllocationSize(%FramePtr), %rsp
2303  //
2304  // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
2305  // However, we may use this sequence if we have a frame pointer because the
2306  // effects of the prologue can safely be undone.
2307  if (LEAAmount != 0) {
2308  unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
2309  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
2310  FramePtr, false, LEAAmount);
2311  --MBBI;
2312  } else {
2313  unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
2314  BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
2315  .addReg(FramePtr);
2316  --MBBI;
2317  }
2318  } else if (NumBytes) {
2319  // Adjust stack pointer back: ESP += numbytes.
2320  emitSPUpdate(MBB, MBBI, DL, NumBytes, /*InEpilogue=*/true);
2321  if (!HasFP && NeedsDwarfCFI) {
2322  // Define the current CFA rule to use the provided offset.
2323  BuildCFI(MBB, MBBI, DL,
2325  nullptr, CSSize + TailCallArgReserveSize + SlotSize),
2327  }
2328  --MBBI;
2329  }
2330 
2331  // Windows unwinder will not invoke function's exception handler if IP is
2332  // either in prologue or in epilogue. This behavior causes a problem when a
2333  // call immediately precedes an epilogue, because the return address points
2334  // into the epilogue. To cope with that, we insert an epilogue marker here,
2335  // then replace it with a 'nop' if it ends up immediately after a CALL in the
2336  // final emitted code.
2337  if (NeedsWin64CFI && MF.hasWinCFI())
2338  BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2339 
2340  if (!HasFP && NeedsDwarfCFI) {
2341  MBBI = FirstCSPop;
2342  int64_t Offset = -CSSize - SlotSize;
2343  // Mark callee-saved pop instruction.
2344  // Define the current CFA rule to use the provided offset.
2345  while (MBBI != MBB.end()) {
2347  unsigned Opc = PI->getOpcode();
2348  ++MBBI;
2349  if (Opc == X86::POP32r || Opc == X86::POP64r) {
2350  Offset += SlotSize;
2351  BuildCFI(MBB, MBBI, DL,
2352  MCCFIInstruction::cfiDefCfaOffset(nullptr, -Offset),
2354  }
2355  }
2356  }
2357 
2358  // Emit DWARF info specifying the restores of the callee-saved registers.
2359  // For epilogue with return inside or being other block without successor,
2360  // no need to generate .cfi_restore for callee-saved registers.
2361  if (NeedsDwarfCFI && !MBB.succ_empty())
2362  emitCalleeSavedFrameMoves(MBB, AfterPop, DL, false);
2363 
2364  if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
2365  // Add the return addr area delta back since we are not tail calling.
2366  int Offset = -1 * X86FI->getTCReturnAddrDelta();
2367  assert(Offset >= 0 && "TCDelta should never be positive");
2368  if (Offset) {
2369  // Check for possible merge with preceding ADD instruction.
2370  Offset += mergeSPUpdates(MBB, Terminator, true);
2371  emitSPUpdate(MBB, Terminator, DL, Offset, /*InEpilogue=*/true);
2372  }
2373  }
2374 
2375  // Emit tilerelease for AMX kernel.
2376  if (X86FI->hasVirtualTileReg())
2377  BuildMI(MBB, Terminator, DL, TII.get(X86::TILERELEASE));
2378 }
2379 
2381  int FI,
2382  Register &FrameReg) const {
2383  const MachineFrameInfo &MFI = MF.getFrameInfo();
2384 
2385  bool IsFixed = MFI.isFixedObjectIndex(FI);
2386  // We can't calculate offset from frame pointer if the stack is realigned,
2387  // so enforce usage of stack/base pointer. The base pointer is used when we
2388  // have dynamic allocas in addition to dynamic realignment.
2389  if (TRI->hasBasePointer(MF))
2390  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getBaseRegister();
2391  else if (TRI->hasStackRealignment(MF))
2392  FrameReg = IsFixed ? TRI->getFramePtr() : TRI->getStackRegister();
2393  else
2394  FrameReg = TRI->getFrameRegister(MF);
2395 
2396  // Offset will hold the offset from the stack pointer at function entry to the
2397  // object.
2398  // We need to factor in additional offsets applied during the prologue to the
2399  // frame, base, and stack pointer depending on which is used.
2400  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
2402  unsigned CSSize = X86FI->getCalleeSavedFrameSize();
2403  uint64_t StackSize = MFI.getStackSize();
2404  bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2405  int64_t FPDelta = 0;
2406 
2407  // In an x86 interrupt, remove the offset we added to account for the return
2408  // address from any stack object allocated in the caller's frame. Interrupts
2409  // do not have a standard return address. Fixed objects in the current frame,
2410  // such as SSE register spills, should not get this treatment.
2412  Offset >= 0) {
2413  Offset += getOffsetOfLocalArea();
2414  }
2415 
2416  if (IsWin64Prologue) {
2417  assert(!MFI.hasCalls() || (StackSize % 16) == 8);
2418 
2419  // Calculate required stack adjustment.
2420  uint64_t FrameSize = StackSize - SlotSize;
2421  // If required, include space for extra hidden slot for stashing base pointer.
2422  if (X86FI->getRestoreBasePointer())
2423  FrameSize += SlotSize;
2424  uint64_t NumBytes = FrameSize - CSSize;
2425 
2426  uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
2427  if (FI && FI == X86FI->getFAIndex())
2428  return StackOffset::getFixed(-SEHFrameOffset);
2429 
2430  // FPDelta is the offset from the "traditional" FP location of the old base
2431  // pointer followed by return address and the location required by the
2432  // restricted Win64 prologue.
2433  // Add FPDelta to all offsets below that go through the frame pointer.
2434  FPDelta = FrameSize - SEHFrameOffset;
2435  assert((!MFI.hasCalls() || (FPDelta % 16) == 0) &&
2436  "FPDelta isn't aligned per the Win64 ABI!");
2437  }
2438 
2439  if (FrameReg == TRI->getFramePtr()) {
2440  // Skip saved EBP/RBP
2441  Offset += SlotSize;
2442 
2443  // Account for restricted Windows prologue.
2444  Offset += FPDelta;
2445 
2446  // Skip the RETADDR move area
2447  int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2448  if (TailCallReturnAddrDelta < 0)
2449  Offset -= TailCallReturnAddrDelta;
2450 
2451  return StackOffset::getFixed(Offset);
2452  }
2453 
2454  // FrameReg is either the stack pointer or a base pointer. But the base is
2455  // located at the end of the statically known StackSize so the distinction
2456  // doesn't really matter.
2457  if (TRI->hasStackRealignment(MF) || TRI->hasBasePointer(MF))
2458  assert(isAligned(MFI.getObjectAlign(FI), -(Offset + StackSize)));
2459  return StackOffset::getFixed(Offset + StackSize);
2460 }
2461 
2463  Register &FrameReg) const {
2464  const MachineFrameInfo &MFI = MF.getFrameInfo();
2466  const auto& WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2467  const auto it = WinEHXMMSlotInfo.find(FI);
2468 
2469  if (it == WinEHXMMSlotInfo.end())
2470  return getFrameIndexReference(MF, FI, FrameReg).getFixed();
2471 
2472  FrameReg = TRI->getStackRegister();
2473  return alignDown(MFI.getMaxCallFrameSize(), getStackAlign().value()) +
2474  it->second;
2475 }
2476 
2479  Register &FrameReg,
2480  int Adjustment) const {
2481  const MachineFrameInfo &MFI = MF.getFrameInfo();
2482  FrameReg = TRI->getStackRegister();
2483  return StackOffset::getFixed(MFI.getObjectOffset(FI) -
2484  getOffsetOfLocalArea() + Adjustment);
2485 }
2486 
2489  int FI, Register &FrameReg,
2490  bool IgnoreSPUpdates) const {
2491 
2492  const MachineFrameInfo &MFI = MF.getFrameInfo();
2493  // Does not include any dynamic realign.
2494  const uint64_t StackSize = MFI.getStackSize();
2495  // LLVM arranges the stack as follows:
2496  // ...
2497  // ARG2
2498  // ARG1
2499  // RETADDR
2500  // PUSH RBP <-- RBP points here
2501  // PUSH CSRs
2502  // ~~~~~~~ <-- possible stack realignment (non-win64)
2503  // ...
2504  // STACK OBJECTS
2505  // ... <-- RSP after prologue points here
2506  // ~~~~~~~ <-- possible stack realignment (win64)
2507  //
2508  // if (hasVarSizedObjects()):
2509  // ... <-- "base pointer" (ESI/RBX) points here
2510  // DYNAMIC ALLOCAS
2511  // ... <-- RSP points here
2512  //
2513  // Case 1: In the simple case of no stack realignment and no dynamic
2514  // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
2515  // with fixed offsets from RSP.
2516  //
2517  // Case 2: In the case of stack realignment with no dynamic allocas, fixed
2518  // stack objects are addressed with RBP and regular stack objects with RSP.
2519  //
2520  // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
2521  // to address stack arguments for outgoing calls and nothing else. The "base
2522  // pointer" points to local variables, and RBP points to fixed objects.
2523  //
2524  // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
2525  // answer we give is relative to the SP after the prologue, and not the
2526  // SP in the middle of the function.
2527 
2528  if (MFI.isFixedObjectIndex(FI) && TRI->hasStackRealignment(MF) &&
2529  !STI.isTargetWin64())
2530  return getFrameIndexReference(MF, FI, FrameReg);
2531 
2532  // If !hasReservedCallFrame the function might have SP adjustement in the
2533  // body. So, even though the offset is statically known, it depends on where
2534  // we are in the function.
2535  if (!IgnoreSPUpdates && !hasReservedCallFrame(MF))
2536  return getFrameIndexReference(MF, FI, FrameReg);
2537 
2538  // We don't handle tail calls, and shouldn't be seeing them either.
2540  "we don't handle this case!");
2541 
2542  // This is how the math works out:
2543  //
2544  // %rsp grows (i.e. gets lower) left to right. Each box below is
2545  // one word (eight bytes). Obj0 is the stack slot we're trying to
2546  // get to.
2547  //
2548  // ----------------------------------
2549  // | BP | Obj0 | Obj1 | ... | ObjN |
2550  // ----------------------------------
2551  // ^ ^ ^ ^
2552  // A B C E
2553  //
2554  // A is the incoming stack pointer.
2555  // (B - A) is the local area offset (-8 for x86-64) [1]
2556  // (C - A) is the Offset returned by MFI.getObjectOffset for Obj0 [2]
2557  //
2558  // |(E - B)| is the StackSize (absolute value, positive). For a
2559  // stack that grown down, this works out to be (B - E). [3]
2560  //
2561  // E is also the value of %rsp after stack has been set up, and we
2562  // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
2563  // (C - E) == (C - A) - (B - A) + (B - E)
2564  // { Using [1], [2] and [3] above }
2565  // == getObjectOffset - LocalAreaOffset + StackSize
2566 
2567  return getFrameIndexReferenceSP(MF, FI, FrameReg, StackSize);
2568 }
2569 
2572  std::vector<CalleeSavedInfo> &CSI) const {
2573  MachineFrameInfo &MFI = MF.getFrameInfo();
2575 
2576  unsigned CalleeSavedFrameSize = 0;
2577  unsigned XMMCalleeSavedFrameSize = 0;
2578  auto &WinEHXMMSlotInfo = X86FI->getWinEHXMMSlotInfo();
2579  int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
2580 
2581  int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
2582 
2583  if (TailCallReturnAddrDelta < 0) {
2584  // create RETURNADDR area
2585  // arg
2586  // arg
2587  // RETADDR
2588  // { ...
2589  // RETADDR area
2590  // ...
2591  // }
2592  // [EBP]
2593  MFI.CreateFixedObject(-TailCallReturnAddrDelta,
2594  TailCallReturnAddrDelta - SlotSize, true);
2595  }
2596 
2597  // Spill the BasePtr if it's used.
2598  if (this->TRI->hasBasePointer(MF)) {
2599  // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
2600  if (MF.hasEHFunclets()) {
2602  X86FI->setHasSEHFramePtrSave(true);
2603  X86FI->setSEHFramePtrSaveIndex(FI);
2604  }
2605  }
2606 
2607  if (hasFP(MF)) {
2608  // emitPrologue always spills frame register the first thing.
2609  SpillSlotOffset -= SlotSize;
2610  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2611 
2612  // The async context lives directly before the frame pointer, and we
2613  // allocate a second slot to preserve stack alignment.
2614  if (X86FI->hasSwiftAsyncContext()) {
2615  SpillSlotOffset -= SlotSize;
2616  MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2617  SpillSlotOffset -= SlotSize;
2618  }
2619 
2620  // Since emitPrologue and emitEpilogue will handle spilling and restoring of
2621  // the frame register, we can delete it from CSI list and not have to worry
2622  // about avoiding it later.
2623  Register FPReg = TRI->getFrameRegister(MF);
2624  for (unsigned i = 0; i < CSI.size(); ++i) {
2625  if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
2626  CSI.erase(CSI.begin() + i);
2627  break;
2628  }
2629  }
2630  }
2631 
2632  // Assign slots for GPRs. It increases frame size.
2633  for (CalleeSavedInfo &I : llvm::reverse(CSI)) {
2634  Register Reg = I.getReg();
2635 
2636  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2637  continue;
2638 
2639  SpillSlotOffset -= SlotSize;
2640  CalleeSavedFrameSize += SlotSize;
2641 
2642  int SlotIndex = MFI.CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
2643  I.setFrameIdx(SlotIndex);
2644  }
2645 
2646  X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
2647  MFI.setCVBytesOfCalleeSavedRegisters(CalleeSavedFrameSize);
2648 
2649  // Assign slots for XMMs.
2650  for (CalleeSavedInfo &I : llvm::reverse(CSI)) {
2651  Register Reg = I.getReg();
2652  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2653  continue;
2654 
2655  // If this is k-register make sure we lookup via the largest legal type.
2656  MVT VT = MVT::Other;
2657  if (X86::VK16RegClass.contains(Reg))
2658  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2659 
2660  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2661  unsigned Size = TRI->getSpillSize(*RC);
2662  Align Alignment = TRI->getSpillAlign(*RC);
2663  // ensure alignment
2664  assert(SpillSlotOffset < 0 && "SpillSlotOffset should always < 0 on X86");
2665  SpillSlotOffset = -alignTo(-SpillSlotOffset, Alignment);
2666 
2667  // spill into slot
2668  SpillSlotOffset -= Size;
2669  int SlotIndex = MFI.CreateFixedSpillStackObject(Size, SpillSlotOffset);
2670  I.setFrameIdx(SlotIndex);
2671  MFI.ensureMaxAlignment(Alignment);
2672 
2673  // Save the start offset and size of XMM in stack frame for funclets.
2674  if (X86::VR128RegClass.contains(Reg)) {
2675  WinEHXMMSlotInfo[SlotIndex] = XMMCalleeSavedFrameSize;
2676  XMMCalleeSavedFrameSize += Size;
2677  }
2678  }
2679 
2680  return true;
2681 }
2682 
2685  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
2687 
2688  // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
2689  // for us, and there are no XMM CSRs on Win32.
2690  if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
2691  return true;
2692 
2693  // Push GPRs. It increases frame size.
2694  const MachineFunction &MF = *MBB.getParent();
2695  unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
2696  for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
2697  Register Reg = I.getReg();
2698 
2699  if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2700  continue;
2701 
2702  const MachineRegisterInfo &MRI = MF.getRegInfo();
2703  bool isLiveIn = MRI.isLiveIn(Reg);
2704  if (!isLiveIn)
2705  MBB.addLiveIn(Reg);
2706 
2707  // Decide whether we can add a kill flag to the use.
2708  bool CanKill = !isLiveIn;
2709  // Check if any subregister is live-in
2710  if (CanKill) {
2711  for (MCRegAliasIterator AReg(Reg, TRI, false); AReg.isValid(); ++AReg) {
2712  if (MRI.isLiveIn(*AReg)) {
2713  CanKill = false;
2714  break;
2715  }
2716  }
2717  }
2718 
2719  // Do not set a kill flag on values that are also marked as live-in. This
2720  // happens with the @llvm-returnaddress intrinsic and with arguments
2721  // passed in callee saved registers.
2722  // Omitting the kill flags is conservatively correct even if the live-in
2723  // is not used after all.
2724  BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2726  }
2727 
2728  // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
2729  // It can be done by spilling XMMs to stack frame.
2730  for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
2731  Register Reg = I.getReg();
2732  if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2733  continue;
2734 
2735  // If this is k-register make sure we lookup via the largest legal type.
2736  MVT VT = MVT::Other;
2737  if (X86::VK16RegClass.contains(Reg))
2738  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2739 
2740  // Add the callee-saved register as live-in. It's killed at the spill.
2741  MBB.addLiveIn(Reg);
2742  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2743 
2744  TII.storeRegToStackSlot(MBB, MI, Reg, true, I.getFrameIdx(), RC, TRI);
2745  --MI;
2746  MI->setFlag(MachineInstr::FrameSetup);
2747  ++MI;
2748  }
2749 
2750  return true;
2751 }
2752 
2753 void X86FrameLowering::emitCatchRetReturnValue(MachineBasicBlock &MBB,
2755  MachineInstr *CatchRet) const {
2756  // SEH shouldn't use catchret.
2759  "SEH should not use CATCHRET");
2760  const DebugLoc &DL = CatchRet->getDebugLoc();
2761  MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2762 
2763  // Fill EAX/RAX with the address of the target block.
2764  if (STI.is64Bit()) {
2765  // LEA64r CatchRetTarget(%rip), %rax
2766  BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2767  .addReg(X86::RIP)
2768  .addImm(0)
2769  .addReg(0)
2770  .addMBB(CatchRetTarget)
2771  .addReg(0);
2772  } else {
2773  // MOV32ri $CatchRetTarget, %eax
2774  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2775  .addMBB(CatchRetTarget);
2776  }
2777 
2778  // Record that we've taken the address of CatchRetTarget and no longer just
2779  // reference it in a terminator.
2780  CatchRetTarget->setMachineBlockAddressTaken();
2781 }
2782 
2786  if (CSI.empty())
2787  return false;
2788 
2789  if (MI != MBB.end() && isFuncletReturnInstr(*MI) && STI.isOSWindows()) {
2790  // Don't restore CSRs in 32-bit EH funclets. Matches
2791  // spillCalleeSavedRegisters.
2792  if (STI.is32Bit())
2793  return true;
2794  // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
2795  // funclets. emitEpilogue transforms these to normal jumps.
2796  if (MI->getOpcode() == X86::CATCHRET) {
2797  const Function &F = MBB.getParent()->getFunction();
2798  bool IsSEH = isAsynchronousEHPersonality(
2799  classifyEHPersonality(F.getPersonalityFn()));
2800  if (IsSEH)
2801  return true;
2802  }
2803  }
2804 
2806 
2807  // Reload XMMs from stack frame.
2808  for (const CalleeSavedInfo &I : CSI) {
2809  Register Reg = I.getReg();
2810  if (X86::GR64RegClass.contains(Reg) ||
2811  X86::GR32RegClass.contains(Reg))
2812  continue;
2813 
2814  // If this is k-register make sure we lookup via the largest legal type.
2815  MVT VT = MVT::Other;
2816  if (X86::VK16RegClass.contains(Reg))
2817  VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2818 
2819  const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2820  TII.loadRegFromStackSlot(MBB, MI, Reg, I.getFrameIdx(), RC, TRI);
2821  }
2822 
2823  // POP GPRs.
2824  unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
2825  for (const CalleeSavedInfo &I : CSI) {
2826  Register Reg = I.getReg();
2827  if (!X86::GR64RegClass.contains(Reg) &&
2828  !X86::GR32RegClass.contains(Reg))
2829  continue;
2830 
2831  BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2833  }
2834  return true;
2835 }
2836 
2838  BitVector &SavedRegs,
2839  RegScavenger *RS) const {
2840  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2841 
2842  // Spill the BasePtr if it's used.
2843  if (TRI->hasBasePointer(MF)){
2844  Register BasePtr = TRI->getBaseRegister();
2845  if (STI.isTarget64BitILP32())
2846  BasePtr = getX86SubSuperRegister(BasePtr, 64);
2847  SavedRegs.set(BasePtr);
2848  }
2849 }
2850 
2851 static bool
2853  const Function &F = MF->getFunction();
2854  for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
2855  I != E; I++) {
2856  if (I->hasNestAttr() && !I->use_empty())
2857  return true;
2858  }
2859  return false;
2860 }
2861 
2862 /// GetScratchRegister - Get a temp register for performing work in the
2863 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
2864 /// and the properties of the function either one or two registers will be
2865 /// needed. Set primary to true for the first register, false for the second.
2866 static unsigned
2867 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
2869 
2870  // Erlang stuff.
2872  if (Is64Bit)
2873  return Primary ? X86::R14 : X86::R13;
2874  else
2875  return Primary ? X86::EBX : X86::EDI;
2876  }
2877 
2878  if (Is64Bit) {
2879  if (IsLP64)
2880  return Primary ? X86::R11 : X86::R12;
2881  else
2882  return Primary ? X86::R11D : X86::R12D;
2883  }
2884 
2885  bool IsNested = HasNestArgument(&MF);
2886 
2890  if (IsNested)
2891  report_fatal_error("Segmented stacks does not support fastcall with "
2892  "nested function.");
2893  return Primary ? X86::EAX : X86::ECX;
2894  }
2895  if (IsNested)
2896  return Primary ? X86::EDX : X86::EAX;
2897  return Primary ? X86::ECX : X86::EAX;
2898 }
2899 
2900 // The stack limit in the TCB is set to this many bytes above the actual stack
2901 // limit.
2902 static const uint64_t kSplitStackAvailable = 256;
2903 
2905  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2906  MachineFrameInfo &MFI = MF.getFrameInfo();
2907  uint64_t StackSize;
2908  unsigned TlsReg, TlsOffset;
2909  DebugLoc DL;
2910 
2911  // To support shrink-wrapping we would need to insert the new blocks
2912  // at the right place and update the branches to PrologueMBB.
2913  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
2914 
2915  unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2916  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2917  "Scratch register is live-in");
2918 
2919  if (MF.getFunction().isVarArg())
2920  report_fatal_error("Segmented stacks do not support vararg functions.");
2921  if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
2922  !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
2924  report_fatal_error("Segmented stacks not supported on this platform.");
2925 
2926  // Eventually StackSize will be calculated by a link-time pass; which will
2927  // also decide whether checking code needs to be injected into this particular
2928  // prologue.
2929  StackSize = MFI.getStackSize();
2930 
2931  if (!MFI.needsSplitStackProlog())
2932  return;
2933 
2934  MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
2935  MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
2937  bool IsNested = false;
2938 
2939  // We need to know if the function has a nest argument only in 64 bit mode.
2940  if (Is64Bit)
2941  IsNested = HasNestArgument(&MF);
2942 
2943  // The MOV R10, RAX needs to be in a different block, since the RET we emit in
2944  // allocMBB needs to be last (terminating) instruction.
2945 
2946  for (const auto &LI : PrologueMBB.liveins()) {
2947  allocMBB->addLiveIn(LI);
2948  checkMBB->addLiveIn(LI);
2949  }
2950 
2951  if (IsNested)
2952  allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
2953 
2954  MF.push_front(allocMBB);
2955  MF.push_front(checkMBB);
2956 
2957  // When the frame size is less than 256 we just compare the stack
2958  // boundary directly to the value of the stack pointer, per gcc.
2959  bool CompareStackPointer = StackSize < kSplitStackAvailable;
2960 
2961  // Read the limit off the current stacklet off the stack_guard location.
2962  if (Is64Bit) {
2963  if (STI.isTargetLinux()) {
2964  TlsReg = X86::FS;
2965  TlsOffset = IsLP64 ? 0x70 : 0x40;
2966  } else if (STI.isTargetDarwin()) {
2967  TlsReg = X86::GS;
2968  TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
2969  } else if (STI.isTargetWin64()) {
2970  TlsReg = X86::GS;
2971  TlsOffset = 0x28; // pvArbitrary, reserved for application use
2972  } else if (STI.isTargetFreeBSD()) {
2973  TlsReg = X86::FS;
2974  TlsOffset = 0x18;
2975  } else if (STI.isTargetDragonFly()) {
2976  TlsReg = X86::FS;
2977  TlsOffset = 0x20; // use tls_tcb.tcb_segstack
2978  } else {
2979  report_fatal_error("Segmented stacks not supported on this platform.");
2980  }
2981 
2982  if (CompareStackPointer)
2983  ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2984  else
2985  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2986  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2987 
2988  BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2989  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2990  } else {
2991  if (STI.isTargetLinux()) {
2992  TlsReg = X86::GS;
2993  TlsOffset = 0x30;
2994  } else if (STI.isTargetDarwin()) {
2995  TlsReg = X86::GS;
2996  TlsOffset = 0x48 + 90*4;
2997  } else if (STI.isTargetWin32()) {
2998  TlsReg = X86::FS;
2999  TlsOffset = 0x14; // pvArbitrary, reserved for application use
3000  } else if (STI.isTargetDragonFly()) {
3001  TlsReg = X86::FS;
3002  TlsOffset = 0x10; // use tls_tcb.tcb_segstack
3003  } else if (STI.isTargetFreeBSD()) {
3004  report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
3005  } else {
3006  report_fatal_error("Segmented stacks not supported on this platform.");
3007  }
3008 
3009  if (CompareStackPointer)
3010  ScratchReg = X86::ESP;
3011  else
3012  BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
3013  .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
3014 
3015  if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
3016  STI.isTargetDragonFly()) {
3017  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
3018  .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
3019  } else if (STI.isTargetDarwin()) {
3020 
3021  // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
3022  unsigned ScratchReg2;
3023  bool SaveScratch2;
3024  if (CompareStackPointer) {
3025  // The primary scratch register is available for holding the TLS offset.
3026  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
3027  SaveScratch2 = false;
3028  } else {
3029  // Need to use a second register to hold the TLS offset
3030  ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
3031 
3032  // Unfortunately, with fastcc the second scratch register may hold an
3033  // argument.
3034  SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
3035  }
3036 
3037  // If Scratch2 is live-in then it needs to be saved.
3038  assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
3039  "Scratch register is live-in and not saved");
3040 
3041  if (SaveScratch2)
3042  BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
3043  .addReg(ScratchReg2, RegState::Kill);
3044 
3045  BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
3046  .addImm(TlsOffset);
3047  BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
3048  .addReg(ScratchReg)
3049  .addReg(ScratchReg2).addImm(1).addReg(0)
3050  .addImm(0)
3051  .addReg(TlsReg);
3052 
3053  if (SaveScratch2)
3054  BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
3055  }
3056  }
3057 
3058  // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
3059  // It jumps to normal execution of the function body.
3060  BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
3061 
3062  // On 32 bit we first push the arguments size and then the frame size. On 64
3063  // bit, we pass the stack frame size in r10 and the argument size in r11.
3064  if (Is64Bit) {
3065  // Functions with nested arguments use R10, so it needs to be saved across
3066  // the call to _morestack
3067 
3068  const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
3069  const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
3070  const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
3071  const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
3072 
3073  if (IsNested)
3074  BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
3075 
3076  BuildMI(allocMBB, DL, TII.get(getMOVriOpcode(IsLP64, StackSize)), Reg10)
3077  .addImm(StackSize);
3078  BuildMI(allocMBB, DL,
3080  Reg11)
3081  .addImm(X86FI->getArgumentStackSize());
3082  } else {
3083  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
3084  .addImm(X86FI->getArgumentStackSize());
3085  BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
3086  .addImm(StackSize);
3087  }
3088 
3089  // __morestack is in libgcc
3090  if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
3091  // Under the large code model, we cannot assume that __morestack lives
3092  // within 2^31 bytes of the call site, so we cannot use pc-relative
3093  // addressing. We cannot perform the call via a temporary register,
3094  // as the rax register may be used to store the static chain, and all
3095  // other suitable registers may be either callee-save or used for
3096  // parameter passing. We cannot use the stack at this point either
3097  // because __morestack manipulates the stack directly.
3098  //
3099  // To avoid these issues, perform an indirect call via a read-only memory
3100  // location containing the address.
3101  //
3102  // This solution is not perfect, as it assumes that the .rodata section
3103  // is laid out within 2^31 bytes of each function body, but this seems
3104  // to be sufficient for JIT.
3105  // FIXME: Add retpoline support and remove the error here..
3106  if (STI.useIndirectThunkCalls())
3107  report_fatal_error("Emitting morestack calls on 64-bit with the large "
3108  "code model and thunks not yet implemented.");
3109  BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
3110  .addReg(X86::RIP)
3111  .addImm(0)
3112  .addReg(0)
3113  .addExternalSymbol("__morestack_addr")
3114  .addReg(0);
3115  } else {
3116  if (Is64Bit)
3117  BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
3118  .addExternalSymbol("__morestack");
3119  else
3120  BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
3121  .addExternalSymbol("__morestack");
3122  }
3123 
3124  if (IsNested)
3125  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
3126  else
3127  BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
3128 
3129  allocMBB->addSuccessor(&PrologueMBB);
3130 
3131  checkMBB->addSuccessor(allocMBB, BranchProbability::getZero());
3132  checkMBB->addSuccessor(&PrologueMBB, BranchProbability::getOne());
3133 
3134 #ifdef EXPENSIVE_CHECKS
3135  MF.verify();
3136 #endif
3137 }
3138 
3139 /// Lookup an ERTS parameter in the !hipe.literals named metadata node.
3140 /// HiPE provides Erlang Runtime System-internal parameters, such as PCB offsets
3141 /// to fields it needs, through a named metadata node "hipe.literals" containing
3142 /// name-value pairs.
3143 static unsigned getHiPELiteral(
3144  NamedMDNode *HiPELiteralsMD, const StringRef LiteralName) {
3145  for (int i = 0, e = HiPELiteralsMD->getNumOperands(); i != e; ++i) {
3146  MDNode *Node = HiPELiteralsMD->getOperand(i);
3147  if (Node->getNumOperands() != 2) continue;
3148  MDString *NodeName = dyn_cast<MDString>(Node->getOperand(0));
3149  ValueAsMetadata *NodeVal = dyn_cast<ValueAsMetadata>(Node->getOperand(1));
3150  if (!NodeName || !NodeVal) continue;
3151  ConstantInt *ValConst = dyn_cast_or_null<ConstantInt>(NodeVal->getValue());
3152  if (ValConst && NodeName->getString() == LiteralName) {
3153  return ValConst->getZExtValue();
3154  }
3155  }
3156 
3157  report_fatal_error("HiPE literal " + LiteralName
3158  + " required but not provided");
3159 }
3160 
3161 // Return true if there are no non-ehpad successors to MBB and there are no
3162 // non-meta instructions between MBBI and MBB.end().
3165  return llvm::all_of(
3166  MBB.successors(),
3167  [](const MachineBasicBlock *Succ) { return Succ->isEHPad(); }) &&
3168  std::all_of(MBBI, MBB.end(), [](const MachineInstr &MI) {
3169  return MI.isMetaInstruction();
3170  });
3171 }
3172 
3173 /// Erlang programs may need a special prologue to handle the stack size they
3174 /// might need at runtime. That is because Erlang/OTP does not implement a C
3175 /// stack but uses a custom implementation of hybrid stack/heap architecture.
3176 /// (for more information see Eric Stenman's Ph.D. thesis:
3177 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
3178 ///
3179 /// CheckStack:
3180 /// temp0 = sp - MaxStack
3181 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3182 /// OldStart:
3183 /// ...
3184 /// IncStack:
3185 /// call inc_stack # doubles the stack space
3186 /// temp0 = sp - MaxStack
3187 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
3189  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
3190  MachineFrameInfo &MFI = MF.getFrameInfo();
3191  DebugLoc DL;
3192 
3193  // To support shrink-wrapping we would need to insert the new blocks
3194  // at the right place and update the branches to PrologueMBB.
3195  assert(&(*MF.begin()) == &PrologueMBB && "Shrink-wrapping not supported yet");
3196 
3197  // HiPE-specific values
3198  NamedMDNode *HiPELiteralsMD = MF.getMMI().getModule()
3199  ->getNamedMetadata("hipe.literals");
3200  if (!HiPELiteralsMD)
3202  "Can't generate HiPE prologue without runtime parameters");
3203  const unsigned HipeLeafWords
3204  = getHiPELiteral(HiPELiteralsMD,
3205  Is64Bit ? "AMD64_LEAF_WORDS" : "X86_LEAF_WORDS");
3206  const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
3207  const unsigned Guaranteed = HipeLeafWords * SlotSize;
3208  unsigned CallerStkArity = MF.getFunction().arg_size() > CCRegisteredArgs ?
3209  MF.getFunction().arg_size() - CCRegisteredArgs : 0;
3210  unsigned MaxStack = MFI.getStackSize() + CallerStkArity*SlotSize + SlotSize;
3211 
3212  assert(STI.isTargetLinux() &&
3213  "HiPE prologue is only supported on Linux operating systems.");
3214 
3215  // Compute the largest caller's frame that is needed to fit the callees'
3216  // frames. This 'MaxStack' is computed from:
3217  //
3218  // a) the fixed frame size, which is the space needed for all spilled temps,
3219  // b) outgoing on-stack parameter areas, and
3220  // c) the minimum stack space this function needs to make available for the
3221  // functions it calls (a tunable ABI property).
3222  if (MFI.hasCalls()) {
3223  unsigned MoreStackForCalls = 0;
3224 
3225  for (auto &MBB : MF) {
3226  for (auto &MI : MBB) {
3227  if (!MI.isCall())
3228  continue;
3229 
3230  // Get callee operand.
3231  const MachineOperand &MO = MI.getOperand(0);
3232 
3233  // Only take account of global function calls (no closures etc.).
3234  if (!MO.isGlobal())
3235  continue;
3236 
3237  const Function *F = dyn_cast<Function>(MO.getGlobal());
3238  if (!F)
3239  continue;
3240 
3241  // Do not update 'MaxStack' for primitive and built-in functions
3242  // (encoded with names either starting with "erlang."/"bif_" or not
3243  // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
3244  // "_", such as the BIF "suspend_0") as they are executed on another
3245  // stack.
3246  if (F->getName().contains("erlang.") || F->getName().contains("bif_") ||
3247  F->getName().find_first_of("._") == StringRef::npos)
3248  continue;
3249 
3250  unsigned CalleeStkArity =
3251  F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
3252  if (HipeLeafWords - 1 > CalleeStkArity)
3253  MoreStackForCalls = std::max(MoreStackForCalls,
3254  (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
3255  }
3256  }
3257  MaxStack += MoreStackForCalls;
3258  }
3259 
3260  // If the stack frame needed is larger than the guaranteed then runtime checks
3261  // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
3262  if (MaxStack > Guaranteed) {
3263  MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
3264  MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
3265 
3266  for (const auto &LI : PrologueMBB.liveins()) {
3267  stackCheckMBB->addLiveIn(LI);
3268  incStackMBB->addLiveIn(LI);
3269  }
3270 
3271  MF.push_front(incStackMBB);
3272  MF.push_front(stackCheckMBB);
3273 
3274  unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
3275  unsigned LEAop, CMPop, CALLop;
3276  SPLimitOffset = getHiPELiteral(HiPELiteralsMD, "P_NSP_LIMIT");
3277  if (Is64Bit) {
3278  SPReg = X86::RSP;
3279  PReg = X86::RBP;
3280  LEAop = X86::LEA64r;
3281  CMPop = X86::CMP64rm;
3282  CALLop = X86::CALL64pcrel32;
3283  } else {
3284  SPReg = X86::ESP;
3285  PReg = X86::EBP;
3286  LEAop = X86::LEA32r;
3287  CMPop = X86::CMP32rm;
3288  CALLop = X86::CALLpcrel32;
3289  }
3290 
3291  ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
3292  assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
3293  "HiPE prologue scratch register is live-in");
3294 
3295  // Create new MBB for StackCheck:
3296  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
3297  SPReg, false, -MaxStack);
3298  // SPLimitOffset is in a fixed heap location (pointed by BP).
3299  addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
3300  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3301  BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
3302 
3303  // Create new MBB for IncStack:
3304  BuildMI(incStackMBB, DL, TII.get(CALLop)).
3305  addExternalSymbol("inc_stack_0");
3306  addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
3307  SPReg, false, -MaxStack);
3308  addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
3309  .addReg(ScratchReg), PReg, false, SPLimitOffset);
3310  BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
3311 
3312  stackCheckMBB->addSuccessor(&PrologueMBB, {99, 100});
3313  stackCheckMBB->addSuccessor(incStackMBB, {1, 100});
3314  incStackMBB->addSuccessor(&PrologueMBB, {99, 100});
3315  incStackMBB->addSuccessor(incStackMBB, {1, 100});
3316  }
3317 #ifdef EXPENSIVE_CHECKS
3318  MF.verify();
3319 #endif
3320 }
3321 
3322 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
3324  const DebugLoc &DL,
3325  int Offset) const {
3326  if (Offset <= 0)
3327  return false;
3328 
3329  if (Offset % SlotSize)
3330  return false;
3331 
3332  int NumPops = Offset / SlotSize;
3333  // This is only worth it if we have at most 2 pops.
3334  if (NumPops != 1 && NumPops != 2)
3335  return false;
3336 
3337  // Handle only the trivial case where the adjustment directly follows
3338  // a call. This is the most common one, anyway.
3339  if (MBBI == MBB.begin())
3340  return false;
3341  MachineBasicBlock::iterator Prev = std::prev(MBBI);
3342  if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
3343  return false;
3344 
3345  unsigned Regs[2];
3346  unsigned FoundRegs = 0;
3347 
3349  const MachineOperand &RegMask = Prev->getOperand(1);
3350 
3351  auto &RegClass =
3352  Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
3353  // Try to find up to NumPops free registers.
3354  for (auto Candidate : RegClass) {
3355  // Poor man's liveness:
3356  // Since we're immediately after a call, any register that is clobbered
3357  // by the call and not defined by it can be considered dead.
3358  if (!RegMask.clobbersPhysReg(Candidate))
3359  continue;
3360 
3361  // Don't clobber reserved registers
3362  if (MRI.isReserved(Candidate))
3363  continue;
3364 
3365  bool IsDef = false;
3366  for (const MachineOperand &MO : Prev->implicit_operands()) {
3367  if (MO.isReg() && MO.isDef() &&
3368  TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
3369  IsDef = true;
3370  break;
3371  }
3372  }
3373 
3374  if (IsDef)
3375  continue;
3376 
3377  Regs[FoundRegs++] = Candidate;
3378  if (FoundRegs == (unsigned)NumPops)
3379  break;
3380  }
3381 
3382  if (FoundRegs == 0)
3383  return false;
3384 
3385  // If we found only one free register, but need two, reuse the same one twice.
3386  while (FoundRegs < (unsigned)NumPops)
3387  Regs[FoundRegs++] = Regs[0];
3388 
3389  for (int i = 0; i < NumPops; ++i)
3390  BuildMI(MBB, MBBI, DL,
3391  TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
3392 
3393  return true;
3394 }
3395 
3399  bool reserveCallFrame = hasReservedCallFrame(MF);
3400  unsigned Opcode = I->getOpcode();
3401  bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
3402  DebugLoc DL = I->getDebugLoc(); // copy DebugLoc as I will be erased.
3403  uint64_t Amount = TII.getFrameSize(*I);
3404  uint64_t InternalAmt = (isDestroy || Amount) ? TII.getFrameAdjustment(*I) : 0;
3405  I = MBB.erase(I);
3406  auto InsertPos = skipDebugInstructionsForward(I, MBB.end());
3407 
3408  // Try to avoid emitting dead SP adjustments if the block end is unreachable,
3409  // typically because the function is marked noreturn (abort, throw,
3410  // assert_fail, etc).
3411  if (isDestroy && blockEndIsUnreachable(MBB, I))
3412  return I;
3413 
3414  if (!reserveCallFrame) {
3415  // If the stack pointer can be changed after prologue, turn the
3416  // adjcallstackup instruction into a 'sub ESP, <amt>' and the
3417  // adjcallstackdown instruction into 'add ESP, <amt>'
3418 
3419  // We need to keep the stack aligned properly. To do this, we round the
3420  // amount of space needed for the outgoing arguments up to the next
3421  // alignment boundary.
3422  Amount = alignTo(Amount, getStackAlign());
3423 
3424  const Function &F = MF.getFunction();
3425  bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
3426  bool DwarfCFI = !WindowsCFI && MF.needsFrameMoves();
3427 
3428  // If we have any exception handlers in this function, and we adjust
3429  // the SP before calls, we may need to indicate this to the unwinder
3430  // using GNU_ARGS_SIZE. Note that this may be necessary even when
3431  // Amount == 0, because the preceding function may have set a non-0
3432  // GNU_ARGS_SIZE.
3433  // TODO: We don't need to reset this between subsequent functions,
3434  // if it didn't change.
3435  bool HasDwarfEHHandlers = !WindowsCFI && !MF.getLandingPads().empty();
3436 
3437  if (HasDwarfEHHandlers && !isDestroy &&
3439  BuildCFI(MBB, InsertPos, DL,
3440  MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
3441 
3442  if (Amount == 0)
3443  return I;
3444 
3445  // Factor out the amount that gets handled inside the sequence
3446  // (Pushes of argument for frame setup, callee pops for frame destroy)
3447  Amount -= InternalAmt;
3448 
3449  // TODO: This is needed only if we require precise CFA.
3450  // If this is a callee-pop calling convention, emit a CFA adjust for
3451  // the amount the callee popped.
3452  if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF))
3453  BuildCFI(MBB, InsertPos, DL,
3454  MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
3455 
3456  // Add Amount to SP to destroy a frame, or subtract to setup.
3457  int64_t StackAdjustment = isDestroy ? Amount : -Amount;
3458 
3459  if (StackAdjustment) {
3460  // Merge with any previous or following adjustment instruction. Note: the
3461  // instructions merged with here do not have CFI, so their stack
3462  // adjustments do not feed into CfaAdjustment.
3463  StackAdjustment += mergeSPUpdates(MBB, InsertPos, true);
3464  StackAdjustment += mergeSPUpdates(MBB, InsertPos, false);
3465 
3466  if (StackAdjustment) {
3467  if (!(F.hasMinSize() &&
3468  adjustStackWithPops(MBB, InsertPos, DL, StackAdjustment)))
3469  BuildStackAdjustment(MBB, InsertPos, DL, StackAdjustment,
3470  /*InEpilogue=*/false);
3471  }
3472  }
3473 
3474  if (DwarfCFI && !hasFP(MF)) {
3475  // If we don't have FP, but need to generate unwind information,
3476  // we need to set the correct CFA offset after the stack adjustment.
3477  // How much we adjust the CFA offset depends on whether we're emitting
3478  // CFI only for EH purposes or for debugging. EH only requires the CFA
3479  // offset to be correct at each call site, while for debugging we want
3480  // it to be more precise.
3481 
3482  int64_t CfaAdjustment = -StackAdjustment;
3483  // TODO: When not using precise CFA, we also need to adjust for the
3484  // InternalAmt here.
3485  if (CfaAdjustment) {
3486  BuildCFI(MBB, InsertPos, DL,
3488  CfaAdjustment));
3489  }
3490  }
3491 
3492  return I;
3493  }
3494 
3495  if (InternalAmt) {
3498  while (CI != B && !std::prev(CI)->isCall())
3499  --CI;
3500  BuildStackAdjustment(MBB, CI, DL, -InternalAmt, /*InEpilogue=*/false);
3501  }
3502 
3503  return I;
3504 }
3505 
3507  assert(MBB.getParent() && "Block is not attached to a function!");
3508  const MachineFunction &MF = *MBB.getParent();
3509  if (!MBB.isLiveIn(X86::EFLAGS))
3510  return true;
3511 
3512  // If stack probes have to loop inline or call, that will clobber EFLAGS.
3513  // FIXME: we could allow cases that will use emitStackProbeInlineGenericBlock.
3514  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
3515  const X86TargetLowering &TLI = *STI.getTargetLowering();
3516  if (TLI.hasInlineStackProbe(MF) || TLI.hasStackProbeSymbol(MF))
3517  return false;
3518 
3520  return !TRI->hasStackRealignment(MF) && !X86FI->hasSwiftAsyncContext();
3521 }
3522 
3524  assert(MBB.getParent() && "Block is not attached to a function!");
3525 
3526  // Win64 has strict requirements in terms of epilogue and we are
3527  // not taking a chance at messing with them.
3528  // I.e., unless this block is already an exit block, we can't use
3529  // it as an epilogue.
3530  if (STI.isTargetWin64() && !MBB.succ_empty() && !MBB.isReturnBlock())
3531  return false;
3532 
3533  // Swift async context epilogue has a BTR instruction that clobbers parts of
3534  // EFLAGS.
3535  const MachineFunction &MF = *MBB.getParent();
3538 
3540  return true;
3541 
3542  // If we cannot use LEA to adjust SP, we may need to use ADD, which
3543  // clobbers the EFLAGS. Check that we do not need to preserve it,
3544  // otherwise, conservatively assume this is not
3545  // safe to insert the epilogue here.
3547 }
3548 
3550  // If we may need to emit frameless compact unwind information, give
3551  // up as this is currently broken: PR25614.
3552  bool CompactUnwind =
3554  nullptr;
3555  return (MF.getFunction().hasFnAttribute(Attribute::NoUnwind) || hasFP(MF) ||
3556  !CompactUnwind) &&
3557  // The lowering of segmented stack and HiPE only support entry
3558  // blocks as prologue blocks: PR26107. This limitation may be
3559  // lifted if we fix:
3560  // - adjustForSegmentedStacks
3561  // - adjustForHiPEPrologue
3563  !MF.shouldSplitStack();
3564 }
3565 
3568  const DebugLoc &DL, bool RestoreSP) const {
3569  assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
3570  assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
3571  assert(STI.is32Bit() && !Uses64BitFramePtr &&
3572  "restoring EBP/ESI on non-32-bit target");
3573 
3574  MachineFunction &MF = *MBB.getParent();
3575  Register FramePtr = TRI->getFrameRegister(MF);
3576  Register BasePtr = TRI->getBaseRegister();
3577  WinEHFuncInfo &FuncInfo = *MF.getWinEHFuncInfo();
3579  MachineFrameInfo &MFI = MF.getFrameInfo();
3580 
3581  // FIXME: Don't set FrameSetup flag in catchret case.
3582 
3583  int FI = FuncInfo.EHRegNodeFrameIndex;
3584  int EHRegSize = MFI.getObjectSize(FI);
3585 
3586  if (RestoreSP) {
3587  // MOV32rm -EHRegSize(%ebp), %esp
3588  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
3589  X86::EBP, true, -EHRegSize)
3591  }
3592 
3593  Register UsedReg;
3594  int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg).getFixed();
3595  int EndOffset = -EHRegOffset - EHRegSize;
3596  FuncInfo.EHRegNodeEndOffset = EndOffset;
3597 
3598  if (UsedReg == FramePtr) {
3599  // ADD $offset, %ebp
3600  unsigned ADDri = getADDriOpcode(false, EndOffset);
3601  BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
3602  .addReg(FramePtr)
3603  .addImm(EndOffset)
3605  ->getOperand(3)
3606  .setIsDead();
3607  assert(EndOffset >= 0 &&
3608  "end of registration object above normal EBP position!");
3609  } else if (UsedReg == BasePtr) {
3610  // LEA offset(%ebp), %esi
3611  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
3612  FramePtr, false, EndOffset)
3614  // MOV32rm SavedEBPOffset(%esi), %ebp
3615  assert(X86FI->getHasSEHFramePtrSave());
3616  int Offset =
3617  getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg)
3618  .getFixed();
3619  assert(UsedReg == BasePtr);
3620  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
3621  UsedReg, true, Offset)
3623  } else {
3624  llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
3625  }
3626  return MBBI;
3627 }
3628 
3630  return TRI->getSlotSize();
3631 }
3632 
3633 Register
3635  return TRI->getDwarfRegNum(StackPtr, true);
3636 }
3637 
3638 namespace {
3639 // Struct used by orderFrameObjects to help sort the stack objects.
3640 struct X86FrameSortingObject {
3641  bool IsValid = false; // true if we care about this Object.
3642  unsigned ObjectIndex = 0; // Index of Object into MFI list.
3643  unsigned ObjectSize = 0; // Size of Object in bytes.
3644  Align ObjectAlignment = Align(1); // Alignment of Object in bytes.
3645  unsigned ObjectNumUses = 0; // Object static number of uses.
3646 };
3647 
3648 // The comparison function we use for std::sort to order our local
3649 // stack symbols. The current algorithm is to use an estimated
3650 // "density". This takes into consideration the size and number of
3651 // uses each object has in order to roughly minimize code size.
3652 // So, for example, an object of size 16B that is referenced 5 times
3653 // will get higher priority than 4 4B objects referenced 1 time each.
3654 // It's not perfect and we may be able to squeeze a few more bytes out of
3655 // it (for example : 0(esp) requires fewer bytes, symbols allocated at the
3656 // fringe end can have special consideration, given their size is less
3657 // important, etc.), but the algorithmic complexity grows too much to be
3658 // worth the extra gains we get. This gets us pretty close.
3659 // The final order leaves us with objects with highest priority going
3660 // at the end of our list.
3661 struct X86FrameSortingComparator {
3662  inline bool operator()(const X86FrameSortingObject &A,
3663  const X86FrameSortingObject &B) const {
3664  uint64_t DensityAScaled, DensityBScaled;
3665 
3666  // For consistency in our comparison, all invalid objects are placed
3667  // at the end. This also allows us to stop walking when we hit the
3668  // first invalid item after it's all sorted.
3669  if (!A.IsValid)
3670  return false;
3671  if (!B.IsValid)
3672  return true;
3673 
3674  // The density is calculated by doing :
3675  // (double)DensityA = A.ObjectNumUses / A.ObjectSize
3676  // (double)DensityB = B.ObjectNumUses / B.ObjectSize
3677  // Since this approach may cause inconsistencies in
3678  // the floating point <, >, == comparisons, depending on the floating
3679  // point model with which the compiler was built, we're going
3680  // to scale both sides by multiplying with
3681  // A.ObjectSize * B.ObjectSize. This ends up factoring away
3682  // the division and, with it, the need for any floating point
3683  // arithmetic.
3684  DensityAScaled = static_cast<uint64_t>(A.ObjectNumUses) *
3685  static_cast<uint64_t>(B.ObjectSize);
3686  DensityBScaled = static_cast<uint64_t>(B.ObjectNumUses) *
3687  static_cast<uint64_t>(A.ObjectSize);
3688 
3689  // If the two densities are equal, prioritize highest alignment
3690  // objects. This allows for similar alignment objects
3691  // to be packed together (given the same density).
3692  // There's room for improvement here, also, since we can pack
3693  // similar alignment (different density) objects next to each
3694  // other to save padding. This will also require further
3695  // complexity/iterations, and the overall gain isn't worth it,
3696  // in general. Something to keep in mind, though.
3697  if (DensityAScaled == DensityBScaled)
3698  return A.ObjectAlignment < B.ObjectAlignment;
3699 
3700  return DensityAScaled < DensityBScaled;
3701  }
3702 };
3703 } // namespace
3704 
3705 // Order the symbols in the local stack.
3706 // We want to place the local stack objects in some sort of sensible order.
3707 // The heuristic we use is to try and pack them according to static number
3708 // of uses and size of object in order to minimize code size.
3710  const MachineFunction &MF, SmallVectorImpl<int> &ObjectsToAllocate) const {
3711  const MachineFrameInfo &MFI = MF.getFrameInfo();
3712 
3713  // Don't waste time if there's nothing to do.
3714  if (ObjectsToAllocate.empty())
3715  return;
3716 
3717  // Create an array of all MFI objects. We won't need all of these
3718  // objects, but we're going to create a full array of them to make
3719  // it easier to index into when we're counting "uses" down below.
3720  // We want to be able to easily/cheaply access an object by simply
3721  // indexing into it, instead of having to search for it every time.
3722  std::vector<X86FrameSortingObject> SortingObjects(MFI.getObjectIndexEnd());
3723 
3724  // Walk the objects we care about and mark them as such in our working
3725  // struct.
3726  for (auto &Obj : ObjectsToAllocate) {
3727  SortingObjects[Obj].IsValid = true;
3728  SortingObjects[Obj].ObjectIndex = Obj;
3729  SortingObjects[Obj].ObjectAlignment = MFI.getObjectAlign(Obj);
3730  // Set the size.
3731  int ObjectSize = MFI.getObjectSize(Obj);
3732  if (ObjectSize == 0)
3733  // Variable size. Just use 4.
3734  SortingObjects[Obj].ObjectSize = 4;
3735  else
3736  SortingObjects[Obj].ObjectSize = ObjectSize;
3737  }
3738 
3739  // Count the number of uses for each object.
3740  for (auto &MBB : MF) {
3741  for (auto &MI : MBB) {
3742  if (MI.isDebugInstr())
3743  continue;
3744  for (const MachineOperand &MO : MI.operands()) {
3745  // Check to see if it's a local stack symbol.
3746  if (!MO.isFI())
3747  continue;
3748  int Index = MO.getIndex();
3749  // Check to see if it falls within our range, and is tagged
3750  // to require ordering.
3751  if (Index >= 0 && Index < MFI.getObjectIndexEnd() &&
3752  SortingObjects[Index].IsValid)
3753  SortingObjects[Index].ObjectNumUses++;
3754  }
3755  }
3756  }
3757 
3758  // Sort the objects using X86FrameSortingAlgorithm (see its comment for
3759  // info).
3760  llvm::stable_sort(SortingObjects, X86FrameSortingComparator());
3761 
3762  // Now modify the original list to represent the final order that
3763  // we want. The order will depend on whether we're going to access them
3764  // from the stack pointer or the frame pointer. For SP, the list should
3765  // end up with the END containing objects that we want with smaller offsets.
3766  // For FP, it should be flipped.
3767  int i = 0;
3768  for (auto &Obj : SortingObjects) {
3769  // All invalid items are sorted at the end, so it's safe to stop.
3770  if (!Obj.IsValid)
3771  break;
3772  ObjectsToAllocate[i++] = Obj.ObjectIndex;
3773  }
3774 
3775  // Flip it if we're accessing off of the FP.
3776  if (!TRI->hasStackRealignment(MF) && hasFP(MF))
3777  std::reverse(ObjectsToAllocate.begin(), ObjectsToAllocate.end());
3778 }
3779 
3780 
3782  // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
3783  unsigned Offset = 16;
3784  // RBP is immediately pushed.
3785  Offset += SlotSize;
3786  // All callee-saved registers are then pushed.
3787  Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
3788  // Every funclet allocates enough stack space for the largest outgoing call.
3789  Offset += getWinEHFuncletFrameSize(MF);
3790  return Offset;
3791 }
3792 
3794  MachineFunction &MF, RegScavenger *RS) const {
3795  // Mark the function as not having WinCFI. We will set it back to true in
3796  // emitPrologue if it gets called and emits CFI.
3797  MF.setHasWinCFI(false);
3798 
3799  // If we are using Windows x64 CFI, ensure that the stack is always 8 byte
3800  // aligned. The format doesn't support misaligned stack adjustments.
3801  if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())
3803 
3804  // If this function isn't doing Win64-style C++ EH, we don't need to do
3805  // anything.
3806  if (STI.is64Bit() && MF.hasEHFunclets() &&
3809  adjustFrameForMsvcCxxEh(MF);
3810  }
3811 }
3812 
3813 void X86FrameLowering::adjustFrameForMsvcCxxEh(MachineFunction &MF) const {
3814  // Win64 C++ EH needs to allocate the UnwindHelp object at some fixed offset
3815  // relative to RSP after the prologue. Find the offset of the last fixed
3816  // object, so that we can allocate a slot immediately following it. If there
3817  // were no fixed objects, use offset -SlotSize, which is immediately after the
3818  // return address. Fixed objects have negative frame indices.
3819  MachineFrameInfo &MFI = MF.getFrameInfo();
3820  WinEHFuncInfo &EHInfo = *MF.getWinEHFuncInfo();
3821  int64_t MinFixedObjOffset = -SlotSize;
3822  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I)
3823  MinFixedObjOffset = std::min(MinFixedObjOffset, MFI.getObjectOffset(I));
3824 
3825  for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
3826  for (WinEHHandlerType &H : TBME.HandlerArray) {
3827  int FrameIndex = H.CatchObj.FrameIndex;
3828  if (FrameIndex != INT_MAX) {
3829  // Ensure alignment.
3830  unsigned Align = MFI.getObjectAlign(FrameIndex).value();
3831  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % Align;
3832  MinFixedObjOffset -= MFI.getObjectSize(FrameIndex);
3833  MFI.setObjectOffset(FrameIndex, MinFixedObjOffset);
3834  }
3835  }
3836  }
3837 
3838  // Ensure alignment.
3839  MinFixedObjOffset -= std::abs(MinFixedObjOffset) % 8;
3840  int64_t UnwindHelpOffset = MinFixedObjOffset - SlotSize;
3841  int UnwindHelpFI =
3842  MFI.CreateFixedObject(SlotSize, UnwindHelpOffset, /*IsImmutable=*/false);
3843  EHInfo.UnwindHelpFrameIdx = UnwindHelpFI;
3844 
3845  // Store -2 into UnwindHelp on function entry. We have to scan forwards past
3846  // other frame setup instructions.
3847  MachineBasicBlock &MBB = MF.front();
3848  auto MBBI = MBB.begin();
3849  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
3850  ++MBBI;
3851 
3853  addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
3854  UnwindHelpFI)
3855  .addImm(-2);
3856 }
3857 
3859  MachineFunction &MF, RegScavenger *RS) const {
3860  if (STI.is32Bit() && MF.hasEHFunclets())
3862 }
3863 
3865  MachineFunction &MF) const {
3866  // 32-bit functions have to restore stack pointers when control is transferred
3867  // back to the parent function. These blocks are identified as eh pads that
3868  // are not funclet entries.
3869  bool IsSEH = isAsynchronousEHPersonality(
3871  for (MachineBasicBlock &MBB : MF) {
3872  bool NeedsRestore = MBB.isEHPad() && !MBB.isEHFuncletEntry();
3873  if (NeedsRestore)
3875  /*RestoreSP=*/IsSEH);
3876  }
3877 }
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:739
llvm::EHPersonality::MSVC_CXX
@ MSVC_CXX
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::X86FrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: X86FrameLowering.cpp:61
llvm::isAsynchronousEHPersonality
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
Definition: EHPersonalities.h:49
getADDriOpcode
static unsigned getADDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:119
llvm::X86FrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: X86FrameLowering.cpp:3523
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::dwarf::CallingConvention
CallingConvention
Definition: Dwarf.h:335
llvm::MCContext::getObjectFileInfo
const MCObjectFileInfo * getObjectFileInfo() const
Definition: MCContext.h:451
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
Attrs
Function Attrs
Definition: README_ALTIVEC.txt:215
llvm::X86FrameLowering::TRI
const X86RegisterInfo * TRI
Definition: X86FrameLowering.h:36
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:146
llvm::X86MachineFunctionInfo::getArgumentStackSize
unsigned getArgumentStackSize() const
Definition: X86MachineFunctionInfo.h:191
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2371
llvm::X86FrameLowering::adjustForHiPEPrologue
void adjustForHiPEPrologue(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Erlang programs may need a special prologue to handle the stack size they might need at runtime.
Definition: X86FrameLowering.cpp:3188
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
calculateSetFPREG
static unsigned calculateSetFPREG(uint64_t SPAdjust)
Definition: X86FrameLowering.cpp:1188
llvm::X86FrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: X86FrameLowering.cpp:2683
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
it
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Definition: README-SSE.txt:81
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::NamedMDNode
A tuple of MDNodes.
Definition: Metadata.h:1588
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
llvm::X86MachineFunctionInfo::getRestoreBasePointer
bool getRestoreBasePointer() const
Definition: X86MachineFunctionInfo.h:150
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:209
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::NamedMDNode::getNumOperands
unsigned getNumOperands() const
Definition: Metadata.cpp:1212
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:143
PHI
Rewrite undef for PHI
Definition: AMDGPURewriteUndefForPHI.cpp:101
X86Subtarget.h
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:281
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:449
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:95
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:128
llvm::X86MachineFunctionInfo::hasSwiftAsyncContext
bool hasSwiftAsyncContext() const
Definition: X86MachineFunctionInfo.h:219
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1018
X86InstrBuilder.h
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::MachineFrameInfo::hasCopyImplyingStackAdjustment
bool hasCopyImplyingStackAdjustment() const
Returns true if the function contains operations which will lower down to instructions which manipula...
Definition: MachineFrameInfo.h:622
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:602
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::MachineFrameInfo::setCVBytesOfCalleeSavedRegisters
void setCVBytesOfCalleeSavedRegisters(unsigned S)
Definition: MachineFrameInfo.h:671
llvm::X86FrameLowering::emitCalleeSavedFrameMoves
void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool IsPrologue) const
Definition: X86FrameLowering.cpp:472
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:52
llvm::X86InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:693
Statistic.h
llvm::Module::getCodeViewFlag
unsigned getCodeViewFlag() const
Returns the CodeView Version by checking module flags.
Definition: Module.cpp:569
llvm::X86MachineFunctionInfo::setCalleeSavedFrameSize
void setCalleeSavedFrameSize(unsigned bytes)
Definition: X86MachineFunctionInfo.h:159
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:915
llvm::recomputeLiveIns
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Definition: LivePhysRegs.h:198
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:179
llvm::BitVector::set_bits
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:133
isEAXLiveIn
static bool isEAXLiveIn(MachineBasicBlock &MBB)
Definition: X86FrameLowering.cpp:165
llvm::WinEHHandlerType
Definition: WinEHFuncInfo.h:60
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::X86FrameLowering::emitCalleeSavedFrameMovesFullCFA
void emitCalleeSavedFrameMovesFullCFA(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Emits Dwarf Info specifying offsets of callee saved registers and frame pointer.
Definition: X86FrameLowering.cpp:451
llvm::X86FrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: X86FrameLowering.cpp:2570
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:864
llvm::X86FrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: X86FrameLowering.cpp:3549
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1388
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
getSUBrrOpcode
static unsigned getSUBrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:131
MCObjectFileInfo.h
llvm::MachineFunction::push_front
void push_front(MachineBasicBlock *MBB)
Definition: MachineFunction.h:872
llvm::Function::arg_size
size_t arg_size() const
Definition: Function.h:755
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::X86MachineFunctionInfo::setHasSEHFramePtrSave
void setHasSEHFramePtrSave(bool V)
Definition: X86MachineFunctionInfo.h:198
llvm::WinEHFuncInfo::TryBlockMap
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:96
llvm::BranchProbability::getZero
static BranchProbability getZero()
Definition: BranchProbability.h:49
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:449
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::X86FrameLowering::orderFrameObjects
void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl< int > &ObjectsToAllocate) const override
Order the symbols in the local stack.
Definition: X86FrameLowering.cpp:3709
getANDriOpcode
static unsigned getANDriOpcode(bool IsLP64, int64_t Imm)
Definition: X86FrameLowering.cpp:139
llvm::addRegOffset
static const MachineInstrBuilder & addRegOffset(const MachineInstrBuilder &MIB, unsigned Reg, bool isKill, int Offset)
addRegOffset - This function is used to add a memory reference of the form [Reg + Offset],...
Definition: X86InstrBuilder.h:157
EHPersonalities.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::X86FrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: X86FrameLowering.cpp:3397
llvm::Optional
Definition: APInt.h:33
llvm::MachineFunction::callsUnwindInit
bool callsUnwindInit() const
Definition: MachineFunction.h:1091
llvm::X86MachineFunctionInfo::getRestoreBasePointerOffset
int getRestoreBasePointerOffset() const
Definition: X86MachineFunctionInfo.h:152
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::X86FrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: X86FrameLowering.cpp:3506
HasNestArgument
static bool HasNestArgument(const MachineFunction *MF)
Definition: X86FrameLowering.cpp:2852
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:410
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:325
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:315
llvm::getX86SubSuperRegisterOrZero
MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:745
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::X86FrameLowering::has128ByteRedZone
bool has128ByteRedZone(const MachineFunction &MF) const
Return true if the function has a redzone (accessible bytes past the frame of the top of stack functi...
Definition: X86FrameLowering.cpp:1367
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:546
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:552
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::MachineFunction::getFrameInstructions
const std::vector< MCCFIInstruction > & getFrameInstructions() const
Returns a reference to a list of cfi instructions in the function's prologue.
Definition: MachineFunction.h:1056
isTailCallOpcode
static bool isTailCallOpcode(unsigned Opc)
Definition: X86FrameLowering.cpp:2159
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
flagsNeedToBePreservedBeforeTheTerminators
static bool flagsNeedToBePreservedBeforeTheTerminators(const MachineBasicBlock &MBB)
Check if the flags need to be preserved before the terminators.
Definition: X86FrameLowering.cpp:182
X86FrameLowering.h
llvm::SwiftAsyncFramePointerMode::Never
@ Never
Never set the bit.
llvm::MachineFrameInfo::hasStackObjects
bool hasStackObjects() const
Return true if there are any stack objects in this function.
Definition: MachineFrameInfo.h:350
llvm::X86MachineFunctionInfo::getHasPushSequences
bool getHasPushSequences() const
Definition: X86MachineFunctionInfo.h:147
llvm::X86FrameLowering::getFrameIndexReferencePreferSP
StackOffset getFrameIndexReferencePreferSP(const MachineFunction &MF, int FI, Register &FrameReg, bool IgnoreSPUpdates) const override
Same as getFrameIndexReference, except that the stack pointer (as opposed to the frame pointer) will ...
Definition: X86FrameLowering.cpp:2488
llvm::X86MachineFunctionInfo::hasPreallocatedCall
bool hasPreallocatedCall() const
Definition: X86MachineFunctionInfo.h:216
getADDrrOpcode
static unsigned getADDrrOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:135
llvm::classifyEHPersonality
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Definition: EHPersonalities.cpp:22
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
getLEArOpcode
static unsigned getLEArOpcode(bool IsLP64)
Definition: X86FrameLowering.cpp:150
llvm::X86FrameLowering::restoreWinEHStackPointersInParent
void restoreWinEHStackPointersInParent(MachineFunction &MF) const
Definition: X86FrameLowering.cpp:3864
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
X86MachineFunctionInfo.h
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:540
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1709
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:866
llvm::X86FrameLowering::stackProbeFunctionModifiesSP
bool stackProbeFunctionModifiesSP() const override
Does the stack probe function call return with a modified stack pointer?
Definition: X86FrameLowering.cpp:597
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
PageSize
static cl::opt< int > PageSize("imp-null-check-page-size", cl::desc("The page size of the target in bytes"), cl::init(4096), cl::Hidden)
llvm::X86FrameLowering::getWin64EHFrameIndexRef
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
Definition: X86FrameLowering.cpp:2462
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
llvm::X86FrameLowering::needsFrameIndexResolution
bool needsFrameIndexResolution(const MachineFunction &MF) const override
Definition: X86FrameLowering.cpp:87
llvm::X86MachineFunctionInfo::setSEHFramePtrSaveIndex
void setSEHFramePtrSaveIndex(int Index)
Definition: X86MachineFunctionInfo.h:201
llvm::X86FrameLowering::getFrameIndexReferenceSP
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
Definition: X86FrameLowering.cpp:2478
llvm::MachineFrameInfo::ensureMaxAlignment
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
Definition: MachineFrameInfo.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:517
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::X86Subtarget::isTargetWin32
bool isTargetWin32() const
Definition: X86Subtarget.h:317
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1044
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
false
Function Alias Analysis false
Definition: AliasAnalysis.cpp:772
llvm::X86MachineFunctionInfo::getTCReturnAddrDelta
int getTCReturnAddrDelta() const
Definition: X86MachineFunctionInfo.h:170
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::WinEHFuncInfo::EHRegNodeFrameIndex
int EHRegNodeFrameIndex
Definition: WinEHFuncInfo.h:107
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::X86RegisterInfo::getFramePtr
Register getFramePtr() const
Returns physical register used as frame pointer.
Definition: X86RegisterInfo.h:156
MCSymbol.h
llvm::X86MachineFunctionInfo::getCalleeSavedFrameSize
unsigned getCalleeSavedFrameSize() const
Definition: X86MachineFunctionInfo.h:158
llvm::MVT::v64i1
@ v64i1
Definition: MachineValueType.h:72
llvm::X86FrameLowering::canUseLEAForSPInEpilogue
bool canUseLEAForSPInEpilogue(const MachineFunction &MF) const
Check that LEA can be used on SP in an epilogue sequence for MF.
Definition: X86FrameLowering.cpp:2082
llvm::X86RegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: X86RegisterInfo.h:151
llvm::X86Subtarget::isTargetWindowsCoreCLR
bool isTargetWindowsCoreCLR() const
Definition: X86Subtarget.h:295
llvm::X86FrameLowering::TII
const X86InstrInfo & TII
Definition: X86FrameLowering.h:35
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: PPCInstrBuilder.h:32
llvm::MVT::v16i1
@ v16i1
Definition: MachineValueType.h:70
llvm::MCObjectFileInfo::getCompactUnwindSection
MCSection * getCompactUnwindSection() const
Definition: MCObjectFileInfo.h:268
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:694
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::codeview::ProcSymFlags::HasFP
@ HasFP
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MachineBasicBlock::RegisterMaskPair
Pair of physical register and lane mask.
Definition: MachineBasicBlock.h:100
STATISTIC
STATISTIC(NumFrameLoopProbe, "Number of loop stack probes used in prologue")
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:74
llvm::X86FrameLowering::emitStackProbe
void emitStackProbe(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog, Optional< MachineFunction::DebugInstrOperandPair > InstrNum=None) const
Emit target stack probe code.
Definition: X86FrameLowering.cpp:580
llvm::X86::COND_A
@ COND_A
Definition: X86BaseInfo.h:88
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::X86FrameLowering::processFunctionBeforeFrameIndicesReplaced
void processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameIndicesReplaced - This method is called immediately before MO_FrameIndex op...
Definition: X86FrameLowering.cpp:3858
llvm::Function::hasPersonalityFn
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:759
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack() const
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:305
llvm::X86InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3929
llvm::MachineFunction::begin
iterator begin()
Definition: MachineFunction.h:854
llvm::X86TargetLowering
Definition: X86ISelLowering.h:959
llvm::MachineFunction::setHasWinCFI
void setHasWinCFI(bool v)
Definition: MachineFunction.h:742
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
llvm::MCCFIInstruction::getOperation
OpType getOperation() const
Definition: MCDwarf.h:641
llvm::X86FrameLowering::restoreWin32EHStackPointers
MachineBasicBlock::iterator restoreWin32EHStackPointers(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool RestoreSP=false) const
Sets up EBP and optionally ESI based on the incoming EBP value.
Definition: X86FrameLowering.cpp:3566
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineBasicBlock::isCleanupFuncletEntry
bool isCleanupFuncletEntry() const
Returns true if this is the entry block of a cleanup funclet.
Definition: MachineBasicBlock.h:608
llvm::BitVector
Definition: BitVector.h:75
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:342
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isOSWindows
bool isOSWindows() const
Definition: X86Subtarget.h:313
llvm::MachineFrameInfo::getObjectIndexBegin
int getObjectIndexBegin() const
Return the minimum frame object index.
Definition: MachineFrameInfo.h:407
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:82
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::X86FrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: X86FrameLowering.cpp:3793
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MCCFIInstruction
Definition: MCDwarf.h:478
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:539
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFrameInfo::CreateSpillStackObject
int CreateSpillStackObject(uint64_t Size, Align Alignment)
Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...
Definition: MachineFrameInfo.cpp:66
llvm::Function::getAttributes
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:314
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:608
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::X86FrameLowering::emitSPUpdate
void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &DL, int64_t NumBytes, bool InEpilogue) const
Emit a series of instructions to increment / decrement the stack pointer by a constant value.
Definition: X86FrameLowering.cpp:218
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::WinEHTryBlockMapEntry
Definition: WinEHFuncInfo.h:72
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:445
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::MachineFrameInfo::CreateFixedSpillStackObject
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:102
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:515
llvm::WinEHFuncInfo
Definition: WinEHFuncInfo.h:90
X86MCTargetDesc.h
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::X86::COND_AE
@ COND_AE
Definition: X86BaseInfo.h:84
llvm::MCCFIInstruction::OpDefCfaOffset
@ OpDefCfaOffset
Definition: MCDwarf.h:487
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::X86TargetLowering::hasInlineStackProbe
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
Definition: X86ISelLowering.cpp:57330
llvm::MachineFunction::callsEHReturn
bool callsEHReturn() const
Definition: MachineFunction.h:1088
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
llvm::X86MachineFunctionInfo::getUsesRedZone
bool getUsesRedZone() const
Definition: X86MachineFunctionInfo.h:210
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::MCCFIInstruction::createGnuArgsSize
static MCCFIInstruction createGnuArgsSize(MCSymbol *L, int Size)
A special wrapper for .cfi_escape that indicates GNU_ARGS_SIZE.
Definition: MCDwarf.h:637
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:918
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
AH
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference AH
Definition: README-X86-64.txt:44
llvm::X86MachineFunctionInfo::getWinEHXMMSlotInfo
DenseMap< int, unsigned > & getWinEHXMMSlotInfo()
Definition: X86MachineFunctionInfo.h:154
llvm::X86FrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: X86FrameLowering.cpp:1473
llvm::TargetOptions::SwiftAsyncFramePointer
SwiftAsyncFramePointerMode SwiftAsyncFramePointer
Control when and how the Swift async frame pointer bit should be set.
Definition: TargetOptions.h:243
llvm::X86FrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: X86FrameLowering.cpp:2783
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::WinEHTryBlockMapEntry::HandlerArray
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1048
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::X86InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3953
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:560
llvm::MachineBasicBlock::getFirstNonPHI
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: MachineBasicBlock.cpp:197
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::NamedMDNode::getOperand
MDNode * getOperand(unsigned i) const
Definition: Metadata.cpp:1216
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:117
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::X86TargetLowering::getStackProbeSymbolName
StringRef getStackProbeSymbolName(const MachineFunction &MF) const override
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Definition: X86ISelLowering.cpp:57348
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:124
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::X86::COND_B
@ COND_B
Definition: X86BaseInfo.h:83
llvm::CallingConv::X86_INTR
@ X86_INTR
x86 hardware interrupt context.
Definition: CallingConv.h:174
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::X86FrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: X86FrameLowering.cpp:2166
llvm::X86FrameLowering::mergeSPUpdates
int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, bool doMergeWithPrevious) const
Check the instruction before/after the passed instruction.
Definition: X86FrameLowering.cpp:375
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::X86MachineFunctionInfo::hasVirtualTileReg
bool hasVirtualTileReg() const
Definition: X86MachineFunctionInfo.h:222
blockEndIsUnreachable
static bool blockEndIsUnreachable(const MachineBasicBlock &MBB, MachineBasicBlock::const_iterator MBBI)
Definition: X86FrameLowering.cpp:3163
llvm::MachineFunction::getLandingPads
const std::vector< LandingPadInfo > & getLandingPads() const
Return a reference to the landing pad info for the current function.
Definition: MachineFunction.h:1111
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MachineFunction::makeDebugValueSubstitution
void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair, unsigned SubReg=0)
Create a substitution between one <instr,operand> value to a different, new value.
Definition: MachineFunction.cpp:977
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::MCCFIInstruction::OpAdjustCfaOffset
@ OpAdjustCfaOffset
Definition: MCDwarf.h:490
MachineModuleInfo.h
llvm::WinEHFuncInfo::UnwindHelpFrameIdx
int UnwindHelpFrameIdx
Definition: WinEHFuncInfo.h:99
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::X86Subtarget::isTargetDragonFly
bool isTargetDragonFly() const
Definition: X86Subtarget.h:273
GetScratchRegister
static unsigned GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary)
GetScratchRegister - Get a temp register for performing work in the segmented stack and the Erlang/Hi...
Definition: X86FrameLowering.cpp:2867
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::ValueAsMetadata::getValue
Value * getValue() const
Definition: Metadata.h:385
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineFrameInfo::needsSplitStackProlog
bool needsSplitStackProlog() const
Return true if this function requires a split stack prolog, even if it uses no stack space.
Definition: MachineFrameInfo.h:402
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::EHPersonality::CoreCLR
@ CoreCLR
llvm::X86::COND_LE
@ COND_LE
Definition: X86BaseInfo.h:95
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::BranchProbability::getOne
static BranchProbability getOne()
Definition: BranchProbability.h:50
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:384
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:204
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::skipDebugInstructionsForward
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Definition: MachineBasicBlock.h:1265
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:271
llvm::MachineBasicBlock::setMachineBlockAddressTaken
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
Definition: MachineBasicBlock.h:247
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineFrameInfo::hasPatchPoint
bool hasPatchPoint() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:389
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::X86AS::GS
@ GS
Definition: X86.h:199
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
DataLayout.h
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::MachineBasicBlock::isEHPad
bool isEHPad() const
Returns true if the block is a landing pad.
Definition: MachineBasicBlock.h:576
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1009
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::X86MachineFunctionInfo::getFAIndex
int getFAIndex() const
Definition: X86MachineFunctionInfo.h:167
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::SwiftAsyncFramePointerMode::DeploymentBased
@ DeploymentBased
Determine whether to set the bit statically or dynamically based on the deployment target.
llvm::MCCFIInstruction::createAdjustCfaOffset
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment)
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
Definition: MCDwarf.h:553
llvm::WinEHFuncInfo::EHRegNodeEndOffset
int EHRegNodeEndOffset
Definition: WinEHFuncInfo.h:108
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::X86FrameLowering::adjustForSegmentedStacks
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &PrologueMBB) const override
Adjust the prologue to have the function use segmented stacks.
Definition: X86FrameLowering.cpp:2904
llvm::EHPersonality
EHPersonality
Definition: EHPersonalities.h:21
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
llvm::X86TargetLowering::hasStackProbeSymbol
bool hasStackProbeSymbol(const MachineFunction &MF) const override
Returns true if stack probing through a function call is requested.
Definition: X86ISelLowering.cpp:57325
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:601
llvm::X86InstrInfo::getFrameAdjustment
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:161
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:371
llvm::WinEHFuncInfo::PSPSymFrameIdx
int PSPSymFrameIdx
Definition: WinEHFuncInfo.h:100
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:582
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::EHPersonality::Unknown
@ Unknown
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86Subtarget::isTargetFreeBSD
bool isTargetFreeBSD() const
Definition: X86Subtarget.h:272
llvm::stable_sort
void stable_sort(R &&Range)
Definition: STLExtras.h:1922
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:438
llvm::X86FrameLowering::SlotSize
unsigned SlotSize
Definition: X86FrameLowering.h:38
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623