LLVM  14.0.0git
X86CallLowering.cpp
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1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/MC/MCRegisterInfo.h"
45 #include <cassert>
46 #include <cstdint>
47 
48 using namespace llvm;
49 
51  : CallLowering(&TLI) {}
52 
53 namespace {
54 
55 struct X86OutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
56 private:
57  uint64_t StackSize = 0;
58  unsigned NumXMMRegs = 0;
59 
60 public:
61  uint64_t getStackSize() { return StackSize; }
62  unsigned getNumXmmRegs() { return NumXMMRegs; }
63 
64  X86OutgoingValueAssigner(CCAssignFn *AssignFn_)
65  : CallLowering::OutgoingValueAssigner(AssignFn_) {}
66 
67  bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
68  CCValAssign::LocInfo LocInfo,
70  CCState &State) override {
71  bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
72  StackSize = State.getNextStackOffset();
73 
74  static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
75  X86::XMM3, X86::XMM4, X86::XMM5,
76  X86::XMM6, X86::XMM7};
77  if (!Info.IsFixed)
78  NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
79 
80  return Res;
81  }
82 };
83 
84 struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
85  X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder,
87  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
88  DL(MIRBuilder.getMF().getDataLayout()),
89  STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
90 
91  Register getStackAddress(uint64_t Size, int64_t Offset,
92  MachinePointerInfo &MPO,
93  ISD::ArgFlagsTy Flags) override {
94  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
95  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
96  auto SPReg =
97  MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister());
98 
99  auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
100 
101  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
102 
103  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
104  return AddrReg.getReg(0);
105  }
106 
107  void assignValueToReg(Register ValVReg, Register PhysReg,
108  CCValAssign &VA) override {
109  MIB.addUse(PhysReg, RegState::Implicit);
110  Register ExtReg = extendRegister(ValVReg, VA);
111  MIRBuilder.buildCopy(PhysReg, ExtReg);
112  }
113 
114  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
115  MachinePointerInfo &MPO, CCValAssign &VA) override {
116  MachineFunction &MF = MIRBuilder.getMF();
117  Register ExtReg = extendRegister(ValVReg, VA);
118 
119  auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
120  inferAlignFromPtrInfo(MF, MPO));
121  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
122  }
123 
124 protected:
125  MachineInstrBuilder &MIB;
126  const DataLayout &DL;
127  const X86Subtarget &STI;
128 };
129 
130 } // end anonymous namespace
131 
133  const Value *Val, ArrayRef<Register> VRegs,
134  FunctionLoweringInfo &FLI) const {
135  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
136  "Return value without a vreg");
137  auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
138 
139  if (!VRegs.empty()) {
140  MachineFunction &MF = MIRBuilder.getMF();
141  const Function &F = MF.getFunction();
143  const DataLayout &DL = MF.getDataLayout();
144 
145  ArgInfo OrigRetInfo(VRegs, Val->getType(), 0);
146  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
147 
148  SmallVector<ArgInfo, 4> SplitRetInfos;
149  splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
150 
151  X86OutgoingValueAssigner Assigner(RetCC_X86);
152  X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
153  if (!determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
154  MIRBuilder, F.getCallingConv(),
155  F.isVarArg()))
156  return false;
157  }
158 
159  MIRBuilder.insertInstr(MIB);
160  return true;
161 }
162 
163 namespace {
164 
165 struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
166  X86IncomingValueHandler(MachineIRBuilder &MIRBuilder,
168  : IncomingValueHandler(MIRBuilder, MRI),
169  DL(MIRBuilder.getMF().getDataLayout()) {}
170 
171  Register getStackAddress(uint64_t Size, int64_t Offset,
172  MachinePointerInfo &MPO,
173  ISD::ArgFlagsTy Flags) override {
174  auto &MFI = MIRBuilder.getMF().getFrameInfo();
175 
176  // Byval is assumed to be writable memory, but other stack passed arguments
177  // are not.
178  const bool IsImmutable = !Flags.isByVal();
179 
180  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
181  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
182 
183  return MIRBuilder
184  .buildFrameIndex(LLT::pointer(0, DL.getPointerSizeInBits(0)), FI)
185  .getReg(0);
186  }
187 
188  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
189  MachinePointerInfo &MPO, CCValAssign &VA) override {
190  MachineFunction &MF = MIRBuilder.getMF();
191  auto *MMO = MF.getMachineMemOperand(
193  inferAlignFromPtrInfo(MF, MPO));
194  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
195  }
196 
197  void assignValueToReg(Register ValVReg, Register PhysReg,
198  CCValAssign &VA) override {
199  markPhysRegUsed(PhysReg);
200  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
201  }
202 
203  /// How the physical register gets marked varies between formal
204  /// parameters (it's a basic-block live-in), and a call instruction
205  /// (it's an implicit-def of the BL).
206  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
207 
208 protected:
209  const DataLayout &DL;
210 };
211 
212 struct FormalArgHandler : public X86IncomingValueHandler {
214  : X86IncomingValueHandler(MIRBuilder, MRI) {}
215 
216  void markPhysRegUsed(unsigned PhysReg) override {
217  MIRBuilder.getMRI()->addLiveIn(PhysReg);
218  MIRBuilder.getMBB().addLiveIn(PhysReg);
219  }
220 };
221 
222 struct CallReturnHandler : public X86IncomingValueHandler {
223  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
224  MachineInstrBuilder &MIB)
225  : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
226 
227  void markPhysRegUsed(unsigned PhysReg) override {
228  MIB.addDef(PhysReg, RegState::Implicit);
229  }
230 
231 protected:
232  MachineInstrBuilder &MIB;
233 };
234 
235 } // end anonymous namespace
236 
238  const Function &F,
240  FunctionLoweringInfo &FLI) const {
241  if (F.arg_empty())
242  return true;
243 
244  // TODO: handle variadic function
245  if (F.isVarArg())
246  return false;
247 
248  MachineFunction &MF = MIRBuilder.getMF();
250  auto DL = MF.getDataLayout();
251 
252  SmallVector<ArgInfo, 8> SplitArgs;
253  unsigned Idx = 0;
254  for (const auto &Arg : F.args()) {
255  // TODO: handle not simple cases.
256  if (Arg.hasAttribute(Attribute::ByVal) ||
257  Arg.hasAttribute(Attribute::InReg) ||
258  Arg.hasAttribute(Attribute::StructRet) ||
259  Arg.hasAttribute(Attribute::SwiftSelf) ||
260  Arg.hasAttribute(Attribute::SwiftError) ||
261  Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
262  return false;
263 
264  ArgInfo OrigArg(VRegs[Idx], Arg.getType(), Idx);
265  setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
266  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
267  Idx++;
268  }
269 
270  MachineBasicBlock &MBB = MIRBuilder.getMBB();
271  if (!MBB.empty())
272  MIRBuilder.setInstr(*MBB.begin());
273 
274  X86OutgoingValueAssigner Assigner(CC_X86);
275  FormalArgHandler Handler(MIRBuilder, MRI);
276  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
277  F.getCallingConv(), F.isVarArg()))
278  return false;
279 
280  // Move back to the end of the basic block.
281  MIRBuilder.setMBB(MBB);
282 
283  return true;
284 }
285 
287  CallLoweringInfo &Info) const {
288  MachineFunction &MF = MIRBuilder.getMF();
289  const Function &F = MF.getFunction();
291  const DataLayout &DL = F.getParent()->getDataLayout();
292  const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
293  const TargetInstrInfo &TII = *STI.getInstrInfo();
294  const X86RegisterInfo *TRI = STI.getRegisterInfo();
295 
296  // Handle only Linux C, X86_64_SysV calling conventions for now.
297  if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
298  Info.CallConv == CallingConv::X86_64_SysV))
299  return false;
300 
301  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
302  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
303 
304  // Create a temporarily-floating call instruction so we can add the implicit
305  // uses of arg registers.
306  bool Is64Bit = STI.is64Bit();
307  unsigned CallOpc = Info.Callee.isReg()
308  ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
309  : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
310 
311  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
312  .add(Info.Callee)
313  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
314 
315  SmallVector<ArgInfo, 8> SplitArgs;
316  for (const auto &OrigArg : Info.OrigArgs) {
317 
318  // TODO: handle not simple cases.
319  if (OrigArg.Flags[0].isByVal())
320  return false;
321 
322  if (OrigArg.Regs.size() > 1)
323  return false;
324 
325  splitToValueTypes(OrigArg, SplitArgs, DL, Info.CallConv);
326  }
327  // Do the actual argument marshalling.
328  X86OutgoingValueAssigner Assigner(CC_X86);
329  X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
330  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
331  Info.CallConv, Info.IsVarArg))
332  return false;
333 
334  bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
335  if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(Info.CallConv)) {
336  // From AMD64 ABI document:
337  // For calls that may call functions that use varargs or stdargs
338  // (prototype-less calls or calls to functions containing ellipsis (...) in
339  // the declaration) %al is used as hidden argument to specify the number
340  // of SSE registers used. The contents of %al do not need to match exactly
341  // the number of registers, but must be an ubound on the number of SSE
342  // registers used and is in the range 0 - 8 inclusive.
343 
344  MIRBuilder.buildInstr(X86::MOV8ri)
345  .addDef(X86::AL)
346  .addImm(Assigner.getNumXmmRegs());
348  }
349 
350  // Now we can add the actual call instruction to the correct basic block.
351  MIRBuilder.insertInstr(MIB);
352 
353  // If Callee is a reg, since it is used by a target specific
354  // instruction, it must have a register class matching the
355  // constraint of that instruction.
356  if (Info.Callee.isReg())
358  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
359  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
360  0));
361 
362  // Finally we can copy the returned value back into its virtual-register. In
363  // symmetry with the arguments, the physical register must be an
364  // implicit-define of the call instruction.
365 
366  if (!Info.OrigRet.Ty->isVoidTy()) {
367  if (Info.OrigRet.Regs.size() > 1)
368  return false;
369 
370  SplitArgs.clear();
371  SmallVector<Register, 8> NewRegs;
372 
373  splitToValueTypes(Info.OrigRet, SplitArgs, DL, Info.CallConv);
374 
375  X86OutgoingValueAssigner Assigner(RetCC_X86);
376  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
377  if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
378  Info.CallConv, Info.IsVarArg))
379  return false;
380 
381  if (!NewRegs.empty())
382  MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
383  }
384 
385  CallSeqStart.addImm(Assigner.getStackSize())
386  .addImm(0 /* see getFrameTotalSize */)
387  .addImm(0 /* see getFrameAdjustment */);
388 
389  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
390  MIRBuilder.buildInstr(AdjStackUp)
391  .addImm(Assigner.getStackSize())
392  .addImm(0 /* NumBytesForCalleeToPop */);
393 
394  return true;
395 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:944
ValueTypes.h
LowLevelType.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
X86CallLowering.h
X86Subtarget.h
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:61
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:852
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::X86Subtarget::getInstrInfo
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:560
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:280
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
MachineBasicBlock.h
llvm::X86CallLowering::X86CallLowering
X86CallLowering(const X86TargetLowering &TLI)
Definition: X86CallLowering.cpp:50
llvm::X86CallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: X86CallLowering.cpp:286
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:326
TargetInstrInfo.h
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:211
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:333
MachineIRBuilder.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::X86CallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: X86CallLowering.cpp:132
MachineRegisterInfo.h
MachineValueType.h
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:206
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:324
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::X86Subtarget::getRegisterInfo
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:570
Utils.h
llvm::RetCC_X86
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
llvm::FormalArgHandler
Definition: M68kCallLowering.h:65
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:219
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:311
llvm::X86TargetLowering
Definition: X86ISelLowering.h:918
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
LowLevelTypeImpl.h
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:401
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:648
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:20
Analysis.h
MCRegisterInfo.h
ArrayRef.h
llvm::CallingConv::X86_64_SysV
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:159
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::TargetSubtargetInfo::getRegBankInfo
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
Definition: TargetSubtargetInfo.h:128
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
DataLayout.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86CallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: X86CallLowering.cpp:237
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::CCState::getFirstUnallocated
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Definition: CallingConvLower.h:336
X86CallingConv.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
CallingConvLower.h
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:227
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:899
MachineFrameInfo.h
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::CC_X86
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:522
Function.h
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:101
X86ISelLowering.h
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:226
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
X86RegisterInfo.h
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1003
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:49
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:586
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
MachineMemOperand.h
MachineOperand.h
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:606
MachineFunction.h
X86InstrInfo.h
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1815
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Value.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1016
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:403
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:66
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:153