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58 unsigned NumXMMRegs = 0;
61 uint64_t getStackSize() {
return StackSize; }
62 unsigned getNumXmmRegs() {
return NumXMMRegs; }
64 X86OutgoingValueAssigner(
CCAssignFn *AssignFn_)
67 bool assignArg(
unsigned ValNo,
EVT OrigVT,
MVT ValVT,
MVT LocVT,
71 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
74 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
75 X86::XMM3, X86::XMM4, X86::XMM5,
76 X86::XMM6, X86::XMM7};
87 : OutgoingValueHandler(MIRBuilder,
MRI), MIB(MIB),
88 DL(MIRBuilder.getMF().getDataLayout()),
97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister());
99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
104 return AddrReg.getReg(0);
110 Register ExtReg = extendRegister(ValVReg, VA);
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
117 Register ExtReg = extendRegister(ValVReg, VA);
121 MIRBuilder.buildStore(ExtReg,
Addr, *MMO);
136 "Return value without a vreg");
139 if (!VRegs.
empty()) {
151 X86OutgoingValueAssigner Assigner(
RetCC_X86);
152 X86OutgoingValueHandler Handler(MIRBuilder,
MRI, MIB);
154 MIRBuilder,
F.getCallingConv(),
168 : IncomingValueHandler(MIRBuilder,
MRI),
169 DL(MIRBuilder.getMF().getDataLayout()) {}
174 auto &MFI = MIRBuilder.getMF().getFrameInfo();
178 const bool IsImmutable = !Flags.
isByVal();
180 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
194 MIRBuilder.buildLoad(ValVReg,
Addr, *MMO);
199 markPhysRegUsed(PhysReg);
200 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
206 virtual void markPhysRegUsed(
unsigned PhysReg) = 0;
216 void markPhysRegUsed(
unsigned PhysReg)
override {
227 void markPhysRegUsed(
unsigned PhysReg)
override {
254 for (
const auto &
Arg :
F.args()) {
256 if (
Arg.hasAttribute(Attribute::ByVal) ||
257 Arg.hasAttribute(Attribute::InReg) ||
258 Arg.hasAttribute(Attribute::StructRet) ||
259 Arg.hasAttribute(Attribute::SwiftSelf) ||
260 Arg.hasAttribute(Attribute::SwiftError) ||
261 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
264 ArgInfo OrigArg(VRegs[Idx],
Arg.getType(), Idx);
274 X86OutgoingValueAssigner Assigner(
CC_X86);
277 F.getCallingConv(),
F.isVarArg()))
301 unsigned AdjStackDown =
TII.getCallFrameSetupOpcode();
302 auto CallSeqStart = MIRBuilder.
buildInstr(AdjStackDown);
306 bool Is64Bit = STI.is64Bit();
307 unsigned CallOpc =
Info.Callee.isReg()
308 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
309 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
316 for (
const auto &OrigArg :
Info.OrigArgs) {
319 if (OrigArg.Flags[0].isByVal())
322 if (OrigArg.Regs.size() > 1)
328 X86OutgoingValueAssigner Assigner(
CC_X86);
329 X86OutgoingValueHandler Handler(MIRBuilder,
MRI, MIB);
334 bool IsFixed =
Info.OrigArgs.empty() ?
true :
Info.OrigArgs.back().IsFixed;
346 .
addImm(Assigner.getNumXmmRegs());
356 if (
Info.Callee.isReg())
366 if (!
Info.OrigRet.Ty->isVoidTy()) {
367 if (
Info.OrigRet.Regs.size() > 1)
375 X86OutgoingValueAssigner Assigner(
RetCC_X86);
381 if (!NewRegs.empty())
385 CallSeqStart.
addImm(Assigner.getStackSize())
389 unsigned AdjStackUp =
TII.getCallFrameDestroyOpcode();
391 .
addImm(Assigner.getStackSize())
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
A parsed version of the target data layout string in and methods for querying it.
CCState - This class holds information needed while lowering arguments and return values.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool isTargetLinux() const
virtual const TargetInstrInfo * getInstrInfo() const
const X86InstrInfo * getInstrInfo() const override
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
@ MOInvariant
The memory access always returns the same value (or traps).
X86CallLowering(const X86TargetLowering &TLI)
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
unsigned const TargetRegisterInfo * TRI
bool empty() const
empty - Check if the array is empty.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
CCValAssign - Represent assignment of one arg/retval to a location.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
const MachineOperand & getOperand(unsigned i) const
const X86RegisterInfo * getRegisterInfo() const override
bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
const HexagonInstrInfo * TII
MachineFunction & getMF()
Getter for the function we currently build.
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Analysis containing CSE Info
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Helper class to build MachineInstr.
This class contains a discriminated union of information about pointers in memory operands,...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Type * getType() const
All values are typed, get the type of this value.
@ C
C - The default llvm calling convention, compatible with C.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineRegisterInfo & MRI
bool isCallingConvWin64(CallingConv::ID CC) const
bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
MachineIRBuilder & MIRBuilder
@ MOStore
The memory access writes data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void setReg(Register Reg)
Change the register this operand corresponds to.
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
LLVM Value Representation.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const